* If this function is not defined here,
* board.c alters dram bank zero configuration defined above.
*/
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
dram_init();
+
+ return 0;
}
return ea_size;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
phys_size_t dp_ddr_size;
}
}
#endif
+
+ return 0;
}
#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
/* board/.../... */
int board_init(void);
-void dram_init_banksize (void);
+int dram_init_banksize(void);
void board_quiesce_devices(void);
/* cpu/.../interrupt.c */
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
}
#endif
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
/* Reserve first 16 MiB of RAM for firmware */
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024);
gd->bd->bi_dram[0].size = gd->ram_size - (16 * 1024 * 1024);
+
+ return 0;
}
void reset_cpu(ulong addr)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
const void *fdt = gd->fdt_blob;
const fdt32_t *val;
val = get_memory_reg_prop(fdt, &len);
if (len < 0)
- return;
+ return -ENXIO;
ac = fdt_address_cells(fdt, 0);
sc = fdt_size_cells(fdt, 0);
if (ac < 1 || sc > 2 || sc < 1 || sc > 2) {
printf("invalid address/size cells\n");
- return;
+ return -ENXIO;
}
cells = ac + sc;
i, (unsigned long)gd->bd->bi_dram[i].start,
(unsigned long)gd->bd->bi_dram[i].size);
}
+
+ return 0;
}
int arch_cpu_init(void)
* If this function is not defined here,
* board.c alters dram bank zero configuration defined above.
*/
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
u64 size = 0;
int i;
if (size > SDRAM_SIZE_MAX)
mvebu_sdram_bs_set(i, 0x40000000);
}
+
+ return 0;
}
#if defined(CONFIG_ARCH_MVEBU)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
}
return 0;
}
-void dram_init_banksize (void)
+int dram_init_banksize(void)
{
unsigned int size0 = 0, size1 = 0;
gd->bd->bi_dram[0].size = size0;
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
gd->bd->bi_dram[1].size = size1;
+
+ return 0;
}
/*
return 0;
}
-void dram_init_banksize (void)
+int dram_init_banksize(void)
{
unsigned int size0 = 0, size1 = 0;
gd->bd->bi_dram[0].size = size0;
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
gd->bd->bi_dram[1].size = size1;
+
+ return 0;
}
/*
return 0;
}
-void dram_init_banksize (void)
+int dram_init_banksize(void)
{
int i;
(long *) (gd->bd->bi_dram[i].start),
CONFIG_MAX_RAM_BANK_SIZE);
}
+
+ return 0;
}
* start address of that bank cannot be represented in the 32-bit .size
* field.
*/
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
gd->bd->bi_dram[1].start = 0;
gd->bd->bi_dram[1].size = 0;
}
+
+ return 0;
}
/*
extern unsigned long nvtboot_boot_x0;
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
int i;
gd->bd->bi_dram[i].start = ram_banks[i].start;
gd->bd->bi_dram[i].size = ram_banks[i].size;
}
+
+ return 0;
}
ulong board_get_usable_ram_top(ulong total_size)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
struct uniphier_dram_map dram_map[3] = {};
int i;
gd->bd->bi_dram[i].start = dram_map[i].base;
gd->bd->bi_dram[i].size = dram_map[i].size;
}
+
+ return 0;
}
#ifdef CONFIG_OF_BOARD_SETUP
return mrc_common_board_get_usable_ram_top(total_size);
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
mrc_common_dram_init_banksize();
+
+ return 0;
}
void broadwell_fill_pei_data(struct pei_data *pei_data)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
int i, j;
}
}
}
+
+ return 0;
}
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = efi_get_ram_base();
gd->bd->bi_dram[0].size = CONFIG_EFI_RAM_SIZE;
+
+ return 0;
}
return mrc_common_board_get_usable_ram_top(total_size);
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
mrc_common_dram_init_banksize();
+
+ return 0;
}
static int read_seed_from_cmos(struct pei_data *pei_data)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = 0;
gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
}
/*
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = 0;
gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
}
/*
int x86_init_cache(void);
void reset_cpu(ulong addr);
ulong board_get_usable_ram_top(ulong total_size);
-void dram_init_banksize(void);
+int dram_init_banksize(void);
int default_print_cpuinfo(void);
/* Set up a UART which can be used with printch(), printhex8(), etc. */
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
struct efi_mem_desc *desc, *end;
struct efi_entry_memmap *map;
if (ret) {
/* We should have stopped in dram_init(), something is wrong */
debug("%s: Missing memory map\n", __func__);
- return;
+ return -ENXIO;
}
end = (struct efi_mem_desc *)((ulong)map + size);
desc = map->desc;
EFI_PAGE_SHIFT;
num_banks++;
}
+
+ return 0;
}
int checkcpu(void)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = 0;
gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
}
/*
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
}
int board_eth_init(bd_t *bd)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_2_SIZE);
else
gd->bd->bi_dram[1].size = 0;
+
+ return 0;
}
ulong board_get_usable_ram_top(ulong total_size)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size =
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size =
get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+ return 0;
}
/*
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
#endif
+
+ return 0;
}
/*
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = mx53_dram_size[0];
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = mx53_dram_size[1];
+
+ return 0;
}
u32 get_board_rev(void)
}
/* This is called after dram_init() so use get_ram_size result */
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
}
#ifdef CONFIG_MMC_SDHCI_KONA
}
/* This is called after dram_init() so use get_ram_size result */
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
}
#ifdef CONFIG_MMC_SDHCI_KONA
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
}
int board_early_init_f(void)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+ return 0;
}
void reset_cpu(ulong addr)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE);
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
}
int board_postclk_init(void)
return dram_total;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
dram_init_banksize_int(0);
+
+ return 0;
}
/* called in board_init_f (before relocation) */
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = 0x7FF00000;
break;
}
+
+ return 0;
}
int dram_init(void)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = mx53_dram_size[0];
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = mx53_dram_size[1];
+
+ return 0;
}
static void setup_iomux_uart(void)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+ return 0;
}
int board_eth_init(bd_t *bis)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
}
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+ return 0;
}
#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+ return 0;
}
#ifdef CONFIG_NAND_MXC
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = mx53_dram_size[0];
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = mx53_dram_size[1];
+
+ return 0;
}
u32 get_board_rev(void)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+ return 0;
}
#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
/*
* Reserve regions below from DT memory node (which gets generated
gd->bd->bi_dram[5].start = 0x22000000;
gd->bd->bi_dram[5].size = 0x1c000000;
+
+ return 0;
}
void reset_cpu(ulong addr)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
PHYS_SDRAM_2_SIZE);
+
+ return 0;
}
#ifdef CONFIG_RESET_PHY_R
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
}
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
/* Reserve 0x200000 for ATF bl31 */
gd->bd->bi_dram[0].start = 0x200000;
gd->bd->bi_dram[0].size = 0x7e000000;
+
+ return 0;
}
int usb_gadget_handle_interrupts(void)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
/* Reserve 0x200000 for ATF bl31 */
gd->bd->bi_dram[0].start = 0x200000;
gd->bd->bi_dram[0].size = 0x7e000000;
+
+ return 0;
}
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+ return 0;
}
#ifdef CONFIG_RESET_PHY_R
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+ return 0;
}
#ifdef CONFIG_RESET_PHY_R
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+ return 0;
}
#ifdef CONFIG_RESET_PHY_R
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
int i;
u32 addr, size;
gd->bd->bi_dram[i].start = addr;
gd->bd->bi_dram[i].size = size;
}
+
+ return 0;
}
#ifdef CONFIG_GENERIC_MMC
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
unsigned int i;
unsigned long addr, size;
gd->bd->bi_dram[i].start = addr;
gd->bd->bi_dram[i].size = size;
}
+
+ return 0;
}
static int board_uart_init(void)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+
+ return 0;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
PHYS_SDRAM_4_SIZE);
+
+ return 0;
}
int board_eth_init(bd_t *bis)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
}
int board_early_init_f()
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
}
int board_init(void)
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
}
#ifdef CONFIG_CMD_NET
return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
u64 ram_size;
gd->bd->bi_dram[1].start = 0x200000000;
gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
}
+
+ return 0;
}
int board_late_init(void)
ulong ram_base;
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = ram_base;
gd->bd->bi_dram[0].size = get_effective_memsize();
+
+ return 0;
}
int dram_init(void)
}
#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
fdtdec_setup_memory_banksize();
+
+ return 0;
}
int dram_init(void)
}
#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
fdtdec_setup_memory_banksize();
+
+ return 0;
}
int dram_init(void)
}
#endif
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
}
#ifdef CONFIG_CMD_MMC
return 0;
}
-__weak void dram_init_banksize(void)
+__weak int dram_init_banksize(void)
{
#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = get_effective_memsize();
#endif
+
+ return 0;
}
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
}
#endif
-static int setup_dram_config(void)
-{
- /* Ram is board specific, so move it to board code ... */
- dram_init_banksize();
-
- return 0;
-}
-
static int reloc_fdt(void)
{
#ifndef CONFIG_OF_EMBED
reserve_fdt,
reserve_arch,
reserve_stacks,
- setup_dram_config,
+ dram_init_banksize,
show_dram_config,
#if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
defined(CONFIG_SH)