]> git.sur5r.net Git - u-boot/commitdiff
arm: mx6: Change defines ENET_xxMHz to ENET_xxMHZ (no CamelCase)
authorStefan Roese <sr@denx.de>
Thu, 27 Nov 2014 12:46:43 +0000 (13:46 +0100)
committerStefano Babic <sbabic@denx.de>
Mon, 1 Dec 2014 09:20:20 +0000 (10:20 +0100)
As checkpatch complaines about these camel-case defines, lets change
them to only use upper-case characters.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Jon Nettleton <jon.nettleton@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/include/asm/arch-mx6/clock.h
board/aristainetos/aristainetos.c
board/freescale/mx6slevk/mx6slevk.c
board/freescale/mx6sxsabresd/mx6sxsabresd.c
board/solidrun/hummingboard/hummingboard.c

index ab7ac3d703e2050de9c9ab92f575e8f7055fb17d..93a02adcec4d843e68196903f891cccaddb566ab 100644 (file)
@@ -443,7 +443,7 @@ int enable_fec_anatop_clock(enum enet_freq freq)
        struct anatop_regs __iomem *anatop =
                (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 
-       if (freq < ENET_25MHz || freq > ENET_125MHz)
+       if (freq < ENET_25MHZ || freq > ENET_125MHZ)
                return -EINVAL;
 
        reg = readl(&anatop->pll_enet);
index 323805c75ca576287fb2727a9410f508bc34f392..226a4cde17e0c9b3b528f155ca786f27c7110ec1 100644 (file)
@@ -43,10 +43,10 @@ enum mxc_clock {
 };
 
 enum enet_freq {
-       ENET_25MHz,
-       ENET_50MHz,
-       ENET_100MHz,
-       ENET_125MHz,
+       ENET_25MHZ,
+       ENET_50MHZ,
+       ENET_100MHZ,
+       ENET_125MHZ,
 };
 
 u32 imx_get_uartclk(void);
index 06922c0020601636f6d40a37a789c691a6ce596e..67ac260055233eb8bfa4a5060e3a7035026602a2 100644 (file)
@@ -301,7 +301,7 @@ int board_eth_init(bd_t *bis)
        /* clear gpr1[14], gpr1[18:17] to select anatop clock */
        clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
 
-       ret = enable_fec_anatop_clock(ENET_50MHz);
+       ret = enable_fec_anatop_clock(ENET_50MHZ);
        if (ret)
                return ret;
 
index 8111edf804291e56ec9172695cc43e9e77c495e2..cac6d73a7f81a9a1f3a7b8bd1b3b682b8fd16807 100644 (file)
@@ -234,7 +234,7 @@ static int setup_fec(void)
        /* clear gpr1[14], gpr1[18:17] to select anatop clock */
        clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
 
-       return enable_fec_anatop_clock(ENET_50MHz);
+       return enable_fec_anatop_clock(ENET_50MHZ);
 }
 #endif
 
index 7aee074a87ab3f00bddf74eefbb3dd079b84aad7..8b959b9fc6a02b56afcc87b2fdd937ce8dad600b 100644 (file)
@@ -168,7 +168,7 @@ static int setup_fec(void)
        reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
        writel(reg, &anatop->pll_enet);
 
-       return enable_fec_anatop_clock(ENET_125MHz);
+       return enable_fec_anatop_clock(ENET_125MHZ);
 }
 
 int board_eth_init(bd_t *bis)
index 6d204b343e58f1088cee7d5ccf032ce7d91cba78..52c384bdd4cf30550200c1db27750c8f9252223c 100644 (file)
@@ -146,7 +146,7 @@ int board_eth_init(bd_t *bis)
 {
        struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 
-       int ret = enable_fec_anatop_clock(ENET_25MHz);
+       int ret = enable_fec_anatop_clock(ENET_25MHZ);
        if (ret)
                return ret;