ARM: uniphier: shrink arrays of DDR-PHY parameters for LD20 SoC

The two arrays ddrphy_{op,ip}_dq_shift_val, occupy more than 3.8 KB
memory footprint, which is significant in SPL.

There are PHY parameters for 5 boards, but they are actually not
board specific, but SoC specific.  After all, we just need to have
2 patterns, for LD20 and LD21.  Also, the shift values are small
enough to become "short" type instead of "int".  This change will
save about 3 KB memory footprint.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/dram/umc-ld20.c b/arch/arm/mach-uniphier/dram/umc-ld20.c
index 61f62ae6d753876d7c167f1a48c31d2c186a07b9..157b915a7b7ec9ca53130fbd058c1333df9c53df 100644 (file)
--- a/arch/arm/mach-uniphier/dram/umc-ld20.c
+++ b/arch/arm/mach-uniphier/dram/umc-ld20.c
@@ -1,7 +1,7 @@
 /*
- * Copyright (C) 2016 Socionext Inc.
+ * Copyright (C) 2016-2017 Socionext Inc.
  *
- * based on commit 1f6feb76e7f9753f51955444e422486521f9b3a3 of Diag
+ * based on commit e732175d0b0dbc2a3855cb8ac791c538666b6fd4 of Diag
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -77,191 +77,95 @@ static const u32 ddrphy_scl_gate_timing[DRAM_CH_NR] = {
        0x00000140, 0x00000180, 0x00000140
 };
 
-static const int ddrphy_op_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
-       { /* LD20 reference */
-               {
-                       2, 1, 0, 1, 2, 1, 1, 1,
-                       2, 1, 1, 2, 1, 1, 1, 1,
-                       1, 2, 1, 1, 1, 2, 1, 1,
-                       2, 2, 0, 1, 1, 2, 2, 1,
-               },
-               {
-                       1, 1, 0, 1, 2, 2, 1, 1,
-                       1, 1, 1, 1, 1, 1, 1, 1,
-                       1, 1, 0, 0, 1, 1, 0, 0,
-                       0, 1, 1, 1, 2, 1, 2, 1,
-               },
-               {
-                       2, 2, 0, 2, 1, 1, 2, 1,
-                       1, 1, 0, 1, 1, -1, 1, 1,
-                       2, 2, 2, 2, 1, 1, 1, 1,
-                       1, 1, 1, 0, 2, 2, 1, 2,
-               },
+static const short ddrphy_op_dq_shift_val_ld20[DRAM_CH_NR][32] = {
+       {
+               2, 1, 0, 1, 2, 1, 1, 1,
+               2, 1, 1, 2, 1, 1, 1, 1,
+               1, 2, 1, 1, 1, 2, 1, 1,
+               2, 2, 0, 1, 1, 2, 2, 1,
        },
-       { /* LD20 TV */
-               {
-                       2, 1, 0, 1, 2, 1, 1, 1,
-                       2, 1, 1, 2, 1, 1, 1, 1,
-                       1, 2, 1, 1, 1, 2, 1, 1,
-                       2, 2, 0, 1, 1, 2, 2, 1,
-               },
-               {
-                       1, 1, 0, 1, 2, 2, 1, 1,
-                       1, 1, 1, 1, 1, 1, 1, 1,
-                       1, 1, 0, 0, 1, 1, 0, 0,
-                       0, 1, 1, 1, 2, 1, 2, 1,
-               },
-               {
-                       2, 2, 0, 2, 1, 1, 2, 1,
-                       1, 1, 0, 1, 1, -1, 1, 1,
-                       2, 2, 2, 2, 1, 1, 1, 1,
-                       1, 1, 1, 0, 2, 2, 1, 2,
-               },
+       {
+               1, 1, 0, 1, 2, 2, 1, 1,
+               1, 1, 1, 1, 1, 1, 1, 1,
+               1, 1, 0, 0, 1, 1, 0, 0,
+               0, 1, 1, 1, 2, 1, 2, 1,
        },
-       { /* LD20 TV C1 */
-               {
-                       2, 1, 0, 1, 2, 1, 1, 1,
-                       2, 1, 1, 2, 1, 1, 1, 1,
-                       1, 2, 1, 1, 1, 2, 1, 1,
-                       2, 2, 0, 1, 1, 2, 2, 1,
-               },
-               {
-                       1, 1, 0, 1, 2, 2, 1, 1,
-                       1, 1, 1, 1, 1, 1, 1, 1,
-                       1, 1, 0, 0, 1, 1, 0, 0,
-                       0, 1, 1, 1, 2, 1, 2, 1,
-               },
-               {
-                       2, 2, 0, 2, 1, 1, 2, 1,
-                       1, 1, 0, 1, 1, -1, 1, 1,
-                       2, 2, 2, 2, 1, 1, 1, 1,
-                       1, 1, 1, 0, 2, 2, 1, 2,
-               },
+       {
+               2, 2, 0, 2, 1, 1, 2, 1,
+               1, 1, 0, 1, 1, -1, 1, 1,
+               2, 2, 2, 2, 1, 1, 1, 1,
+               1, 1, 1, 0, 2, 2, 1, 2,
        },
-       { /* LD21 reference */
-               {
-                       1, 1, 0, 1, 1, 1, 1, 1,
-                       1, 0, 0, 0, 1, 1, 0, 2,
-                       1, 1, 0, 0, 1, 1, 1, 1,
-                       1, 0, 0, 0, 1, 0, 0, 1,
-               },
-               {       1, 0, 2, 1, 1, 1, 1, 0,
-                       1, 0, 0, 1, 0, 1, 0, 0,
-                       1, 0, 1, 0, 1, 1, 1, 0,
-                       1, 1, 1, 1, 0, 1, 0, 0,
-               },
-               /* No CH2 */
+};
+
+static const short ddrphy_op_dq_shift_val_ld21[DRAM_CH_NR][32] = {
+       {
+               1, 1, 0, 1, 1, 1, 1, 1,
+               1, 0, 0, 0, 1, 1, 0, 2,
+               1, 1, 0, 0, 1, 1, 1, 1,
+               1, 0, 0, 0, 1, 0, 0, 1,
        },
-       { /* LD21 TV */
-               {
-                       1, 1, 0, 1, 1, 1, 1, 1,
-                       1, 0, 0, 0, 1, 1, 0, 2,
-                       1, 1, 0, 0, 1, 1, 1, 1,
-                       1, 0, 0, 0, 1, 0, 0, 1,
-               },
-               {       1, 0, 2, 1, 1, 1, 1, 0,
-                       1, 0, 0, 1, 0, 1, 0, 0,
-                       1, 0, 1, 0, 1, 1, 1, 0,
-                       1, 1, 1, 1, 0, 1, 0, 0,
-               },
-               /* No CH2 */
+       {       1, 0, 2, 1, 1, 1, 1, 0,
+               1, 0, 0, 1, 0, 1, 0, 0,
+               1, 0, 1, 0, 1, 1, 1, 0,
+               1, 1, 1, 1, 0, 1, 0, 0,
        },
+       /* No CH2 */
+};
+
+static const short (* const ddrphy_op_dq_shift_val[DRAM_BOARD_NR])[32] = {
+       ddrphy_op_dq_shift_val_ld20,    /* LD20 reference */
+       ddrphy_op_dq_shift_val_ld20,    /* LD20 TV */
+       ddrphy_op_dq_shift_val_ld20,    /* LD20 TV C */
+       ddrphy_op_dq_shift_val_ld21,    /* LD21 reference */
+       ddrphy_op_dq_shift_val_ld21,    /* LD21 TV */
 };
 
-static int ddrphy_ip_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
-       { /* LD20 reference */
-               {
-                       3, 3, 3, 2, 3, 2, 0, 2,
-                       2, 3, 3, 1, 2, 2, 2, 2,
-                       2, 2, 2, 2, 0, 1, 1, 1,
-                       2, 2, 2, 2, 3, 0, 2, 2,
-               },
-               {
-                       2, 2, 1, 1, -1, 1, 1, 1,
-                       2, 0, 2, 2, 2, 1, 0, 2,
-                       2, 1, 2, 1, 0, 1, 1, 1,
-                       2, 2, 2, 2, 2, 2, 2, 2,
-               },
-               {
-                       2, 2, 3, 2, 1, 2, 2, 2,
-                       2, 3, 4, 2, 3, 4, 3, 3,
-                       2, 2, 1, 2, 1, 1, 1, 1,
-                       2, 2, 2, 2, 1, 2, 2, 1,
-               },
+static const short ddrphy_ip_dq_shift_val_ld20[DRAM_CH_NR][32] = {
+       {
+               3, 3, 3, 2, 3, 2, 0, 2,
+               2, 3, 3, 1, 2, 2, 2, 2,
+               2, 2, 2, 2, 0, 1, 1, 1,
+               2, 2, 2, 2, 3, 0, 2, 2,
        },
-       { /* LD20 TV */
-               {
-                       3, 3, 3, 2, 3, 2, 0, 2,
-                       2, 3, 3, 1, 2, 2, 2, 2,
-                       2, 2, 2, 2, 0, 1, 1, 1,
-                       2, 2, 2, 2, 3, 0, 2, 2,
-               },
-               {
-                       2, 2, 1, 1, -1, 1, 1, 1,
-                       2, 0, 2, 2, 2, 1, 0, 2,
-                       2, 1, 2, 1, 0, 1, 1, 1,
-                       2, 2, 2, 2, 2, 2, 2, 2,
-               },
-               {
-                       2, 2, 3, 2, 1, 2, 2, 2,
-                       2, 3, 4, 2, 3, 4, 3, 3,
-                       2, 2, 1, 2, 1, 1, 1, 1,
-                       2, 2, 2, 2, 1, 2, 2, 1,
-               },
+       {
+               2, 2, 1, 1, -1, 1, 1, 1,
+               2, 0, 2, 2, 2, 1, 0, 2,
+               2, 1, 2, 1, 0, 1, 1, 1,
+               2, 2, 2, 2, 2, 2, 2, 2,
        },
-       { /* LD20 TV C1 */
-               {
-                       3, 3, 3, 2, 3, 2, 0, 2,
-                       2, 3, 3, 1, 2, 2, 2, 2,
-                       2, 2, 2, 2, 0, 1, 1, 1,
-                       2, 2, 2, 2, 3, 0, 2, 2,
-               },
-               {
-                       2, 2, 1, 1, -1, 1, 1, 1,
-                       2, 0, 2, 2, 2, 1, 0, 2,
-                       2, 1, 2, 1, 0, 1, 1, 1,
-                       2, 2, 2, 2, 2, 2, 2, 2,
-               },
-               {
-                       2, 2, 3, 2, 1, 2, 2, 2,
-                       2, 3, 4, 2, 3, 4, 3, 3,
-                       2, 2, 1, 2, 1, 1, 1, 1,
-                       2, 2, 2, 2, 1, 2, 2, 1,
-               },
+       {
+               2, 2, 3, 2, 1, 2, 2, 2,
+               2, 3, 4, 2, 3, 4, 3, 3,
+               2, 2, 1, 2, 1, 1, 1, 1,
+               2, 2, 2, 2, 1, 2, 2, 1,
        },
-       { /* LD21 reference */
-               {
-                       2, 2, 2, 2, 1, 2, 2, 2,
-                       2, 3, 3, 2, 2, 2, 2, 2,
-                       2, 1, 2, 2, 1, 1, 1, 1,
-                       2, 2, 2, 3, 1, 2, 2, 2,
-               },
-               {
-                       3, 4, 4, 1, 0, 1, 1, 1,
-                       1, 2, 1, 2, 2, 3, 3, 2,
-                       1, 0, 2, 1, 1, 0, 1, 0,
-                       0, 1, 0, 0, 1, 1, 0, 1,
-               },
-               /* No CH2 */
+};
+
+static const short ddrphy_ip_dq_shift_val_ld21[DRAM_CH_NR][32] = {
+       {
+               2, 2, 2, 2, 1, 2, 2, 2,
+               2, 3, 3, 2, 2, 2, 2, 2,
+               2, 1, 2, 2, 1, 1, 1, 1,
+               2, 2, 2, 3, 1, 2, 2, 2,
        },
-       { /* LD21 TV */
-               {
-                       2, 2, 2, 2, 1, 2, 2, 2,
-                       2, 3, 3, 2, 2, 2, 2, 2,
-                       2, 1, 2, 2, 1, 1, 1, 1,
-                       2, 2, 2, 3, 1, 2, 2, 2,
-               },
-               {
-                       3, 4, 4, 1, 0, 1, 1, 1,
-                       1, 2, 1, 2, 2, 3, 3, 2,
-                       1, 0, 2, 1, 1, 0, 1, 0,
-                       0, 1, 0, 0, 1, 1, 0, 1,
-               },
-               /* No CH2 */
+       {
+               3, 4, 4, 1, 0, 1, 1, 1,
+               1, 2, 1, 2, 2, 3, 3, 2,
+               1, 0, 2, 1, 1, 0, 1, 0,
+               0, 1, 0, 0, 1, 1, 0, 1,
        },
+       /* No CH2 */
+};
+
+static const short (* const ddrphy_ip_dq_shift_val[DRAM_BOARD_NR])[32] = {
+       ddrphy_ip_dq_shift_val_ld20,    /* LD20 reference */
+       ddrphy_ip_dq_shift_val_ld20,    /* LD20 TV */
+       ddrphy_ip_dq_shift_val_ld20,    /* LD20 TV C */
+       ddrphy_ip_dq_shift_val_ld21,    /* LD21 reference */
+       ddrphy_ip_dq_shift_val_ld21,    /* LD21 TV */
 };
 
-/* DDR PHY */
 static void ddrphy_select_lane(void __iomem *phy_base, unsigned int lane,
                               unsigned int bit)
 {
@@ -380,7 +284,7 @@ static void ddrphy_init_tail(void __iomem *phy_base, enum dram_board board,
 }
 
 static void ddrphy_shift_one_dq(void __iomem *phy_base, unsigned int reg,
-                               u32 mask, u32 incr, int shift_val)
+                               u32 mask, u32 incr, short shift_val)
 {
        u32 tmp;
        int val;
@@ -403,7 +307,7 @@ static void ddrphy_shift_one_dq(void __iomem *phy_base, unsigned int reg,
 
 static void ddrphy_shift_dq(void __iomem *phy_base, unsigned int reg,
                            u32 mask, u32 incr, u32 override,
-                           const int *shift_val_array)
+                           const short *shift_val_array)
 {
        u32 tmp;
        int dx, bit;