char cExpectedString[ 15 ];\r
char cReceivedString[ 15 ];\r
char cMessage;\r
-const TickType_t xShortBlockTime = pdMS_TO_TICKS( 5 );\r
+const TickType_t xShortBlockTime = pdMS_TO_TICKS( 150 );\r
\r
/* This task is created more than once so the task's parameter is used to\r
pass in a task number, which is then used as an index into the message\r
\r
void vGenerateM4ToM7Interrupt( void * xUpdatedMessageBuffer )\r
{\r
-MessageBufferHandle_t xUpdatedBuffer = ( MessageBufferHandle_t ) xUpdatedMessageBuffer;\r
-const char cMessage[] = "\r\nvGenerateM4ToM7Interrupt\r\n";\r
-\r
/* Called by the implementation of sbRECEIVE_COMPLETED() in FreeRTOSConfig.h.\r
See the comments at the top of this file. Write the handle of the data\r
message buffer to which data was written to the control message buffer. */\r
-#if 0\r
- if( xUpdatedBuffer != xControlMessageBuffer )\r
- {\r
- while( xMessageBufferSend( xControlMessageBuffer, &xUpdatedBuffer, sizeof( xUpdatedBuffer ), mbaDONT_BLOCK ) != sizeof( xUpdatedBuffer ) )\r
- {\r
- /* Nothing to do here. Note it is very bad to loop in an interrupt\r
- service routine. If a loop is really required then defer the\r
- routine to a task. */\r
- }\r
-\r
- /* Generate interrupt in the M4 core. */\r
- HAL_EXTI_D1_EventInputConfig( EXTI_LINE0, EXTI_MODE_IT, DISABLE );\r
- HAL_EXTI_D2_EventInputConfig( EXTI_LINE0, EXTI_MODE_IT, ENABLE );\r
- HAL_EXTI_GenerateSWInterrupt( EXTI_LINE0 );\r
- }\r
-#endif\r
\r
/* Generate interrupt in the M7 core. */\r
HAL_EXTI_D2_EventInputConfig( EXTI_LINE1, EXTI_MODE_IT, DISABLE );\r
{\r
BaseType_t x;\r
uint32_t ulNextValue = 0;\r
-const TickType_t xDelay = pdMS_TO_TICKS( 25 );\r
char cString[ 15 ];\r
size_t xStringLength;\r
\r
( void * ) cString,\r
xStringLength,\r
portMAX_DELAY ) != xStringLength );\r
-\r
- /* Delay before repeating */\r
-// vTaskDelay( xDelay );\r
}\r
\r
ulNextValue++;\r
+++ /dev/null
-/* ----------------------------------------------------------------------\r
- * Project: CMSIS DSP Library\r
- * Title: arm_math.h\r
- * Description: Public header file for CMSIS DSP Library\r
- *\r
- * $Date: 27. January 2017\r
- * $Revision: V.1.5.1\r
- *\r
- * Target Processor: Cortex-M cores\r
- * -------------------------------------------------------------------- */\r
-/*\r
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-/**\r
- \mainpage CMSIS DSP Software Library\r
- *\r
- * Introduction\r
- * ------------\r
- *\r
- * This user manual describes the CMSIS DSP software library,\r
- * a suite of common signal processing functions for use on Cortex-M processor based devices.\r
- *\r
- * The library is divided into a number of functions each covering a specific category:\r
- * - Basic math functions\r
- * - Fast math functions\r
- * - Complex math functions\r
- * - Filters\r
- * - Matrix functions\r
- * - Transforms\r
- * - Motor control functions\r
- * - Statistical functions\r
- * - Support functions\r
- * - Interpolation functions\r
- *\r
- * The library has separate functions for operating on 8-bit integers, 16-bit integers,\r
- * 32-bit integer and 32-bit floating-point values.\r
- *\r
- * Using the Library\r
- * ------------\r
- *\r
- * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.\r
- * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)\r
- * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)\r
- * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)\r
- * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)\r
- * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)\r
- * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)\r
- * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)\r
- * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)\r
- * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)\r
- * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)\r
- * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)\r
- * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)\r
- * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)\r
- * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)\r
- * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian)\r
- * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian)\r
- * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit)\r
- * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions)\r
- * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)\r
- *\r
- * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.\r
- * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single\r
- * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.\r
- * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or\r
- * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.\r
- * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.\r
- * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions.\r
- * \r
- *\r
- * Examples\r
- * --------\r
- *\r
- * The library ships with a number of examples which demonstrate how to use the library functions.\r
- *\r
- * Toolchain Support\r
- * ------------\r
- *\r
- * The library has been developed and tested with MDK-ARM version 5.14.0.0\r
- * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\r
- *\r
- * Building the Library\r
- * ------------\r
- *\r
- * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.\r
- * - arm_cortexM_math.uvprojx\r
- *\r
- *\r
- * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.\r
- *\r
- * Pre-processor Macros\r
- * ------------\r
- *\r
- * Each library project have differant pre-processor macros.\r
- *\r
- * - UNALIGNED_SUPPORT_DISABLE:\r
- *\r
- * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access\r
- *\r
- * - ARM_MATH_BIG_ENDIAN:\r
- *\r
- * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.\r
- *\r
- * - ARM_MATH_MATRIX_CHECK:\r
- *\r
- * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices\r
- *\r
- * - ARM_MATH_ROUNDING:\r
- *\r
- * Define macro ARM_MATH_ROUNDING for rounding on support functions\r
- *\r
- * - ARM_MATH_CMx:\r
- *\r
- * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target\r
- * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and\r
- * ARM_MATH_CM7 for building the library on cortex-M7.\r
- *\r
- * - ARM_MATH_ARMV8MxL:\r
- *\r
- * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library\r
- * on ARMv8M Mainline target.\r
- *\r
- * - __FPU_PRESENT:\r
- *\r
- * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.\r
- *\r
- * - __DSP_PRESENT:\r
- *\r
- * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions.\r
- *\r
- * <hr>\r
- * CMSIS-DSP in ARM::CMSIS Pack\r
- * -----------------------------\r
- *\r
- * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:\r
- * |File/Folder |Content |\r
- * |------------------------------|------------------------------------------------------------------------|\r
- * |\b CMSIS\\Documentation\\DSP | This documentation |\r
- * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |\r
- * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |\r
- * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |\r
- *\r
- * <hr>\r
- * Revision History of CMSIS-DSP\r
- * ------------\r
- * Please refer to \ref ChangeLog_pg.\r
- *\r
- * Copyright Notice\r
- * ------------\r
- *\r
- * Copyright (C) 2010-2015 ARM Limited. All rights reserved.\r
- */\r
-\r
-\r
-/**\r
- * @defgroup groupMath Basic Math Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupFastMath Fast Math Functions\r
- * This set of functions provides a fast approximation to sine, cosine, and square root.\r
- * As compared to most of the other functions in the CMSIS math library, the fast math functions\r
- * operate on individual values and not arrays.\r
- * There are separate functions for Q15, Q31, and floating-point data.\r
- *\r
- */\r
-\r
-/**\r
- * @defgroup groupCmplxMath Complex Math Functions\r
- * This set of functions operates on complex data vectors.\r
- * The data in the complex arrays is stored in an interleaved fashion\r
- * (real, imag, real, imag, ...).\r
- * In the API functions, the number of samples in a complex array refers\r
- * to the number of complex values; the array contains twice this number of\r
- * real values.\r
- */\r
-\r
-/**\r
- * @defgroup groupFilters Filtering Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupMatrix Matrix Functions\r
- *\r
- * This set of functions provides basic matrix math operations.\r
- * The functions operate on matrix data structures. For example,\r
- * the type\r
- * definition for the floating-point matrix structure is shown\r
- * below:\r
- * <pre>\r
- * typedef struct\r
- * {\r
- * uint16_t numRows; // number of rows of the matrix.\r
- * uint16_t numCols; // number of columns of the matrix.\r
- * float32_t *pData; // points to the data of the matrix.\r
- * } arm_matrix_instance_f32;\r
- * </pre>\r
- * There are similar definitions for Q15 and Q31 data types.\r
- *\r
- * The structure specifies the size of the matrix and then points to\r
- * an array of data. The array is of size <code>numRows X numCols</code>\r
- * and the values are arranged in row order. That is, the\r
- * matrix element (i, j) is stored at:\r
- * <pre>\r
- * pData[i*numCols + j]\r
- * </pre>\r
- *\r
- * \par Init Functions\r
- * There is an associated initialization function for each type of matrix\r
- * data structure.\r
- * The initialization function sets the values of the internal structure fields.\r
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>\r
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.\r
- *\r
- * \par\r
- * Use of the initialization function is optional. However, if initialization function is used\r
- * then the instance structure cannot be placed into a const data section.\r
- * To place the instance structure in a const data\r
- * section, manually initialize the data structure. For example:\r
- * <pre>\r
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>\r
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>\r
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>\r
- * </pre>\r
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>\r
- * specifies the number of columns, and <code>pData</code> points to the\r
- * data array.\r
- *\r
- * \par Size Checking\r
- * By default all of the matrix functions perform size checking on the input and\r
- * output matrices. For example, the matrix addition function verifies that the\r
- * two input matrices and the output matrix all have the same number of rows and\r
- * columns. If the size check fails the functions return:\r
- * <pre>\r
- * ARM_MATH_SIZE_MISMATCH\r
- * </pre>\r
- * Otherwise the functions return\r
- * <pre>\r
- * ARM_MATH_SUCCESS\r
- * </pre>\r
- * There is some overhead associated with this matrix size checking.\r
- * The matrix size checking is enabled via the \#define\r
- * <pre>\r
- * ARM_MATH_MATRIX_CHECK\r
- * </pre>\r
- * within the library project settings. By default this macro is defined\r
- * and size checking is enabled. By changing the project settings and\r
- * undefining this macro size checking is eliminated and the functions\r
- * run a bit faster. With size checking disabled the functions always\r
- * return <code>ARM_MATH_SUCCESS</code>.\r
- */\r
-\r
-/**\r
- * @defgroup groupTransforms Transform Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupController Controller Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupStats Statistics Functions\r
- */\r
-/**\r
- * @defgroup groupSupport Support Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupInterpolation Interpolation Functions\r
- * These functions perform 1- and 2-dimensional interpolation of data.\r
- * Linear interpolation is used for 1-dimensional data and\r
- * bilinear interpolation is used for 2-dimensional data.\r
- */\r
-\r
-/**\r
- * @defgroup groupExamples Examples\r
- */\r
-#ifndef _ARM_MATH_H\r
-#define _ARM_MATH_H\r
-\r
-/* Compiler specific diagnostic adjustment */\r
-#if defined ( __CC_ARM )\r
-\r
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
-\r
-#elif defined ( __GNUC__ )\r
-#pragma GCC diagnostic push\r
-#pragma GCC diagnostic ignored "-Wsign-conversion"\r
-#pragma GCC diagnostic ignored "-Wconversion"\r
-#pragma GCC diagnostic ignored "-Wunused-parameter"\r
-\r
-#elif defined ( __ICCARM__ )\r
-\r
-#elif defined ( __TI_ARM__ )\r
-\r
-#elif defined ( __CSMC__ )\r
-\r
-#elif defined ( __TASKING__ )\r
-\r
-#else\r
- #error Unknown compiler\r
-#endif\r
-\r
-\r
-#define __CMSIS_GENERIC /* disable NVIC and Systick functions */\r
-\r
-#if defined(ARM_MATH_CM7)\r
- #include "core_cm7.h"\r
- #define ARM_MATH_DSP\r
-#elif defined (ARM_MATH_CM4)\r
- #include "core_cm4.h"\r
- #define ARM_MATH_DSP\r
-#elif defined (ARM_MATH_CM3)\r
- #include "core_cm3.h"\r
-#elif defined (ARM_MATH_CM0)\r
- #include "core_cm0.h"\r
- #define ARM_MATH_CM0_FAMILY\r
-#elif defined (ARM_MATH_CM0PLUS)\r
- #include "core_cm0plus.h"\r
- #define ARM_MATH_CM0_FAMILY\r
-#elif defined (ARM_MATH_ARMV8MBL)\r
- #include "core_armv8mbl.h"\r
- #define ARM_MATH_CM0_FAMILY\r
-#elif defined (ARM_MATH_ARMV8MML)\r
- #include "core_armv8mml.h"\r
- #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))\r
- #define ARM_MATH_DSP\r
- #endif\r
-#else\r
- #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"\r
-#endif\r
-\r
-#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */\r
-#include "string.h"\r
-#include "math.h"\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-\r
- /**\r
- * @brief Macros required for reciprocal calculation in Normalized LMS\r
- */\r
-\r
-#define DELTA_Q31 (0x100)\r
-#define DELTA_Q15 0x5\r
-#define INDEX_MASK 0x0000003F\r
-#ifndef PI\r
- #define PI 3.14159265358979f\r
-#endif\r
-\r
- /**\r
- * @brief Macros required for SINE and COSINE Fast math approximations\r
- */\r
-\r
-#define FAST_MATH_TABLE_SIZE 512\r
-#define FAST_MATH_Q31_SHIFT (32 - 10)\r
-#define FAST_MATH_Q15_SHIFT (16 - 10)\r
-#define CONTROLLER_Q31_SHIFT (32 - 9)\r
-#define TABLE_SPACING_Q31 0x400000\r
-#define TABLE_SPACING_Q15 0x80\r
-\r
- /**\r
- * @brief Macros required for SINE and COSINE Controller functions\r
- */\r
- /* 1.31(q31) Fixed value of 2/360 */\r
- /* -1 to +1 is divided into 360 values so total spacing is (2/360) */\r
-#define INPUT_SPACING 0xB60B61\r
-\r
- /**\r
- * @brief Macro for Unaligned Support\r
- */\r
-#ifndef UNALIGNED_SUPPORT_DISABLE\r
- #define ALIGN4\r
-#else\r
- #if defined (__GNUC__)\r
- #define ALIGN4 __attribute__((aligned(4)))\r
- #else\r
- #define ALIGN4 __align(4)\r
- #endif\r
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */\r
-\r
- /**\r
- * @brief Error status returned by some functions in the library.\r
- */\r
-\r
- typedef enum\r
- {\r
- ARM_MATH_SUCCESS = 0, /**< No error */\r
- ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */\r
- ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */\r
- ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */\r
- ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */\r
- ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */\r
- ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */\r
- } arm_status;\r
-\r
- /**\r
- * @brief 8-bit fractional data type in 1.7 format.\r
- */\r
- typedef int8_t q7_t;\r
-\r
- /**\r
- * @brief 16-bit fractional data type in 1.15 format.\r
- */\r
- typedef int16_t q15_t;\r
-\r
- /**\r
- * @brief 32-bit fractional data type in 1.31 format.\r
- */\r
- typedef int32_t q31_t;\r
-\r
- /**\r
- * @brief 64-bit fractional data type in 1.63 format.\r
- */\r
- typedef int64_t q63_t;\r
-\r
- /**\r
- * @brief 32-bit floating-point type definition.\r
- */\r
- typedef float float32_t;\r
-\r
- /**\r
- * @brief 64-bit floating-point type definition.\r
- */\r
- typedef double float64_t;\r
-\r
- /**\r
- * @brief definition to read/write two 16 bit values.\r
- */\r
-#if defined ( __CC_ARM )\r
- #define __SIMD32_TYPE int32_t __packed\r
- #define CMSIS_UNUSED __attribute__((unused))\r
- #define CMSIS_INLINE __attribute__((always_inline))\r
-\r
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
- #define __SIMD32_TYPE int32_t\r
- #define CMSIS_UNUSED __attribute__((unused))\r
- #define CMSIS_INLINE __attribute__((always_inline))\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __SIMD32_TYPE int32_t\r
- #define CMSIS_UNUSED __attribute__((unused))\r
- #define CMSIS_INLINE __attribute__((always_inline))\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __SIMD32_TYPE int32_t __packed\r
- #define CMSIS_UNUSED\r
- #define CMSIS_INLINE\r
-\r
-#elif defined ( __TI_ARM__ )\r
- #define __SIMD32_TYPE int32_t\r
- #define CMSIS_UNUSED __attribute__((unused))\r
- #define CMSIS_INLINE\r
-\r
-#elif defined ( __CSMC__ )\r
- #define __SIMD32_TYPE int32_t\r
- #define CMSIS_UNUSED\r
- #define CMSIS_INLINE\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __SIMD32_TYPE __unaligned int32_t\r
- #define CMSIS_UNUSED\r
- #define CMSIS_INLINE\r
-\r
-#else\r
- #error Unknown compiler\r
-#endif\r
-\r
-#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))\r
-#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))\r
-#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))\r
-#define __SIMD64(addr) (*(int64_t **) & (addr))\r
-\r
-/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */\r
-#if !defined (ARM_MATH_DSP)\r
- /**\r
- * @brief definition to pack two 16 bit values.\r
- */\r
-#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \\r
- (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )\r
-#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \\r
- (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )\r
-\r
-/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */\r
-#endif /* !defined (ARM_MATH_DSP) */\r
-\r
- /**\r
- * @brief definition to pack four 8 bit values.\r
- */\r
-#ifndef ARM_MATH_BIG_ENDIAN\r
-\r
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \\r
- (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \\r
- (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \\r
- (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )\r
-#else\r
-\r
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \\r
- (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \\r
- (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \\r
- (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )\r
-\r
-#endif\r
-\r
-\r
- /**\r
- * @brief Clips Q63 to Q31 values.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(\r
- q63_t x)\r
- {\r
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
- ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;\r
- }\r
-\r
- /**\r
- * @brief Clips Q63 to Q15 values.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(\r
- q63_t x)\r
- {\r
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
- ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);\r
- }\r
-\r
- /**\r
- * @brief Clips Q31 to Q7 values.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(\r
- q31_t x)\r
- {\r
- return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?\r
- ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;\r
- }\r
-\r
- /**\r
- * @brief Clips Q31 to Q15 values.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(\r
- q31_t x)\r
- {\r
- return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?\r
- ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;\r
- }\r
-\r
- /**\r
- * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.\r
- */\r
-\r
- CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(\r
- q63_t x,\r
- q31_t y)\r
- {\r
- return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +\r
- (((q63_t) (x >> 32) * y)));\r
- }\r
-\r
-/*\r
- #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )\r
- #define __CLZ __clz\r
- #endif\r
- */\r
-/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */\r
-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) )\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(\r
- q31_t data);\r
-\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(\r
- q31_t data)\r
- {\r
- uint32_t count = 0;\r
- uint32_t mask = 0x80000000;\r
-\r
- while ((data & mask) == 0)\r
- {\r
- count += 1u;\r
- mask = mask >> 1u;\r
- }\r
-\r
- return (count);\r
- }\r
-#endif\r
-\r
- /**\r
- * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.\r
- */\r
-\r
- CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(\r
- q31_t in,\r
- q31_t * dst,\r
- q31_t * pRecipTable)\r
- {\r
- q31_t out;\r
- uint32_t tempVal;\r
- uint32_t index, i;\r
- uint32_t signBits;\r
-\r
- if (in > 0)\r
- {\r
- signBits = ((uint32_t) (__CLZ( in) - 1));\r
- }\r
- else\r
- {\r
- signBits = ((uint32_t) (__CLZ(-in) - 1));\r
- }\r
-\r
- /* Convert input sample to 1.31 format */\r
- in = (in << signBits);\r
-\r
- /* calculation of index for initial approximated Val */\r
- index = (uint32_t)(in >> 24);\r
- index = (index & INDEX_MASK);\r
-\r
- /* 1.31 with exp 1 */\r
- out = pRecipTable[index];\r
-\r
- /* calculation of reciprocal value */\r
- /* running approximation for two iterations */\r
- for (i = 0u; i < 2u; i++)\r
- {\r
- tempVal = (uint32_t) (((q63_t) in * out) >> 31);\r
- tempVal = 0x7FFFFFFFu - tempVal;\r
- /* 1.31 with exp 1 */\r
- /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */\r
- out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);\r
- }\r
-\r
- /* write output */\r
- *dst = out;\r
-\r
- /* return num of signbits of out = 1/in value */\r
- return (signBits + 1u);\r
- }\r
-\r
-\r
- /**\r
- * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(\r
- q15_t in,\r
- q15_t * dst,\r
- q15_t * pRecipTable)\r
- {\r
- q15_t out = 0;\r
- uint32_t tempVal = 0;\r
- uint32_t index = 0, i = 0;\r
- uint32_t signBits = 0;\r
-\r
- if (in > 0)\r
- {\r
- signBits = ((uint32_t)(__CLZ( in) - 17));\r
- }\r
- else\r
- {\r
- signBits = ((uint32_t)(__CLZ(-in) - 17));\r
- }\r
-\r
- /* Convert input sample to 1.15 format */\r
- in = (in << signBits);\r
-\r
- /* calculation of index for initial approximated Val */\r
- index = (uint32_t)(in >> 8);\r
- index = (index & INDEX_MASK);\r
-\r
- /* 1.15 with exp 1 */\r
- out = pRecipTable[index];\r
-\r
- /* calculation of reciprocal value */\r
- /* running approximation for two iterations */\r
- for (i = 0u; i < 2u; i++)\r
- {\r
- tempVal = (uint32_t) (((q31_t) in * out) >> 15);\r
- tempVal = 0x7FFFu - tempVal;\r
- /* 1.15 with exp 1 */\r
- out = (q15_t) (((q31_t) out * tempVal) >> 14);\r
- /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */\r
- }\r
-\r
- /* write output */\r
- *dst = out;\r
-\r
- /* return num of signbits of out = 1/in value */\r
- return (signBits + 1);\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined intrinisic function for only M0 processors\r
- */\r
-#if defined(ARM_MATH_CM0_FAMILY)\r
- CMSIS_INLINE __STATIC_INLINE q31_t __SSAT(\r
- q31_t x,\r
- uint32_t y)\r
- {\r
- int32_t posMax, negMin;\r
- uint32_t i;\r
-\r
- posMax = 1;\r
- for (i = 0; i < (y - 1); i++)\r
- {\r
- posMax = posMax * 2;\r
- }\r
-\r
- if (x > 0)\r
- {\r
- posMax = (posMax - 1);\r
-\r
- if (x > posMax)\r
- {\r
- x = posMax;\r
- }\r
- }\r
- else\r
- {\r
- negMin = -posMax;\r
-\r
- if (x < negMin)\r
- {\r
- x = negMin;\r
- }\r
- }\r
- return (x);\r
- }\r
-#endif /* end of ARM_MATH_CM0_FAMILY */\r
-\r
-\r
- /*\r
- * @brief C custom defined intrinsic function for M3 and M0 processors\r
- */\r
-/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */\r
-#if !defined (ARM_MATH_DSP)\r
-\r
- /*\r
- * @brief C custom defined QADD8 for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s, t, u;\r
-\r
- r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\r
- s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\r
- t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;\r
- u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;\r
-\r
- return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QSUB8 for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s, t, u;\r
-\r
- r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\r
- s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\r
- t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;\r
- u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;\r
-\r
- return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QADD16 for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
-/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */\r
- q31_t r = 0, s = 0;\r
-\r
- r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
- s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SHADD16 for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
- s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QSUB16 for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
- s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SHSUB16 for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
- s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QASX for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
- s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SHASX for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
- s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QSAX for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
- s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SHSAX for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
- s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMUSDX for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -\r
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));\r
- }\r
-\r
- /*\r
- * @brief C custom defined SMUADX for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +\r
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QADD for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE int32_t __QADD(\r
- int32_t x,\r
- int32_t y)\r
- {\r
- return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QSUB for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(\r
- int32_t x,\r
- int32_t y)\r
- {\r
- return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMLAD for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(\r
- uint32_t x,\r
- uint32_t y,\r
- uint32_t sum)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +\r
- ( ((q31_t)sum ) ) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMLADX for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(\r
- uint32_t x,\r
- uint32_t y,\r
- uint32_t sum)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +\r
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +\r
- ( ((q31_t)sum ) ) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMLSDX for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(\r
- uint32_t x,\r
- uint32_t y,\r
- uint32_t sum)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -\r
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +\r
- ( ((q31_t)sum ) ) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMLALD for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(\r
- uint32_t x,\r
- uint32_t y,\r
- uint64_t sum)\r
- {\r
-/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */\r
- return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +\r
- ( ((q63_t)sum ) ) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMLALDX for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(\r
- uint32_t x,\r
- uint32_t y,\r
- uint64_t sum)\r
- {\r
-/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */\r
- return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +\r
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +\r
- ( ((q63_t)sum ) ) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMUAD for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMUSD for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -\r
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SXTB16 for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(\r
- uint32_t x)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |\r
- ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));\r
- }\r
-\r
- /*\r
- * @brief C custom defined SMMLA for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(\r
- int32_t x,\r
- int32_t y,\r
- int32_t sum)\r
- {\r
- return (sum + (int32_t) (((int64_t) x * y) >> 32));\r
- }\r
-\r
-#if 0\r
- /*\r
- * @brief C custom defined PKHBT for unavailable DSP extension\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT(\r
- uint32_t x,\r
- uint32_t y,\r
- uint32_t leftshift)\r
- {\r
- return ( ((x ) & 0x0000FFFFUL) |\r
- ((y << leftshift) & 0xFFFF0000UL) );\r
- }\r
-\r
- /*\r
- * @brief C custom defined PKHTB for unavailable DSP extension\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB(\r
- uint32_t x,\r
- uint32_t y,\r
- uint32_t rightshift)\r
- {\r
- return ( ((x ) & 0xFFFF0000UL) |\r
- ((y >> rightshift) & 0x0000FFFFUL) );\r
- }\r
-#endif\r
-\r
-/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */\r
-#endif /* !defined (ARM_MATH_DSP) */\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q7 FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
- q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- } arm_fir_instance_q7;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- } arm_fir_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- } arm_fir_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- } arm_fir_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q7 FIR filter.\r
- * @param[in] S points to an instance of the Q7 FIR filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_q7(\r
- const arm_fir_instance_q7 * S,\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q7 FIR filter.\r
- * @param[in,out] S points to an instance of the Q7 FIR structure.\r
- * @param[in] numTaps Number of filter coefficients in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of samples that are processed.\r
- */\r
- void arm_fir_init_q7(\r
- arm_fir_instance_q7 * S,\r
- uint16_t numTaps,\r
- q7_t * pCoeffs,\r
- q7_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR filter.\r
- * @param[in] S points to an instance of the Q15 FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_q15(\r
- const arm_fir_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.\r
- * @param[in] S points to an instance of the Q15 FIR filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_fast_q15(\r
- const arm_fir_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 FIR filter.\r
- * @param[in,out] S points to an instance of the Q15 FIR filter structure.\r
- * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of samples that are processed at a time.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if\r
- * <code>numTaps</code> is not a supported value.\r
- */\r
- arm_status arm_fir_init_q15(\r
- arm_fir_instance_q15 * S,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR filter.\r
- * @param[in] S points to an instance of the Q31 FIR filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_q31(\r
- const arm_fir_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.\r
- * @param[in] S points to an instance of the Q31 FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_fast_q31(\r
- const arm_fir_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 FIR filter.\r
- * @param[in,out] S points to an instance of the Q31 FIR structure.\r
- * @param[in] numTaps Number of filter coefficients in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of samples that are processed at a time.\r
- */\r
- void arm_fir_init_q31(\r
- arm_fir_instance_q31 * S,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point FIR filter.\r
- * @param[in] S points to an instance of the floating-point FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_f32(\r
- const arm_fir_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point FIR filter.\r
- * @param[in,out] S points to an instance of the floating-point FIR filter structure.\r
- * @param[in] numTaps Number of filter coefficients in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of samples that are processed at a time.\r
- */\r
- void arm_fir_init_f32(\r
- arm_fir_instance_f32 * S,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
- q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
- int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
- } arm_biquad_casd_df1_inst_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
- q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
- uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
- } arm_biquad_casd_df1_inst_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
- float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
- } arm_biquad_casd_df1_inst_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 Biquad cascade filter.\r
- * @param[in] S points to an instance of the Q15 Biquad cascade structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df1_q15(\r
- const arm_biquad_casd_df1_inst_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 Biquad cascade filter.\r
- * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
- */\r
- void arm_biquad_cascade_df1_init_q15(\r
- arm_biquad_casd_df1_inst_q15 * S,\r
- uint8_t numStages,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- int8_t postShift);\r
-\r
-\r
- /**\r
- * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
- * @param[in] S points to an instance of the Q15 Biquad cascade structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df1_fast_q15(\r
- const arm_biquad_casd_df1_inst_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 Biquad cascade filter\r
- * @param[in] S points to an instance of the Q31 Biquad cascade structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df1_q31(\r
- const arm_biquad_casd_df1_inst_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
- * @param[in] S points to an instance of the Q31 Biquad cascade structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df1_fast_q31(\r
- const arm_biquad_casd_df1_inst_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 Biquad cascade filter.\r
- * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
- */\r
- void arm_biquad_cascade_df1_init_q31(\r
- arm_biquad_casd_df1_inst_q31 * S,\r
- uint8_t numStages,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- int8_t postShift);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point Biquad cascade filter.\r
- * @param[in] S points to an instance of the floating-point Biquad cascade structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df1_f32(\r
- const arm_biquad_casd_df1_inst_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point Biquad cascade filter.\r
- * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- */\r
- void arm_biquad_cascade_df1_init_f32(\r
- arm_biquad_casd_df1_inst_f32 * S,\r
- uint8_t numStages,\r
- float32_t * pCoeffs,\r
- float32_t * pState);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point matrix structure.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows of the matrix. */\r
- uint16_t numCols; /**< number of columns of the matrix. */\r
- float32_t *pData; /**< points to the data of the matrix. */\r
- } arm_matrix_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point matrix structure.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows of the matrix. */\r
- uint16_t numCols; /**< number of columns of the matrix. */\r
- float64_t *pData; /**< points to the data of the matrix. */\r
- } arm_matrix_instance_f64;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 matrix structure.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows of the matrix. */\r
- uint16_t numCols; /**< number of columns of the matrix. */\r
- q15_t *pData; /**< points to the data of the matrix. */\r
- } arm_matrix_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 matrix structure.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows of the matrix. */\r
- uint16_t numCols; /**< number of columns of the matrix. */\r
- q31_t *pData; /**< points to the data of the matrix. */\r
- } arm_matrix_instance_q31;\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix addition.\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_add_f32(\r
- const arm_matrix_instance_f32 * pSrcA,\r
- const arm_matrix_instance_f32 * pSrcB,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix addition.\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_add_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix addition.\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_add_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Floating-point, complex, matrix multiplication.\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_cmplx_mult_f32(\r
- const arm_matrix_instance_f32 * pSrcA,\r
- const arm_matrix_instance_f32 * pSrcB,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15, complex, matrix multiplication.\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_cmplx_mult_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst,\r
- q15_t * pScratch);\r
-\r
-\r
- /**\r
- * @brief Q31, complex, matrix multiplication.\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_cmplx_mult_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix transpose.\r
- * @param[in] pSrc points to the input matrix\r
- * @param[out] pDst points to the output matrix\r
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_trans_f32(\r
- const arm_matrix_instance_f32 * pSrc,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix transpose.\r
- * @param[in] pSrc points to the input matrix\r
- * @param[out] pDst points to the output matrix\r
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_trans_q15(\r
- const arm_matrix_instance_q15 * pSrc,\r
- arm_matrix_instance_q15 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix transpose.\r
- * @param[in] pSrc points to the input matrix\r
- * @param[out] pDst points to the output matrix\r
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_trans_q31(\r
- const arm_matrix_instance_q31 * pSrc,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix multiplication\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_mult_f32(\r
- const arm_matrix_instance_f32 * pSrcA,\r
- const arm_matrix_instance_f32 * pSrcB,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix multiplication\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @param[in] pState points to the array for storing intermediate results\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_mult_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst,\r
- q15_t * pState);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @param[in] pState points to the array for storing intermediate results\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_mult_fast_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst,\r
- q15_t * pState);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix multiplication\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_mult_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_mult_fast_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix subtraction\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_sub_f32(\r
- const arm_matrix_instance_f32 * pSrcA,\r
- const arm_matrix_instance_f32 * pSrcB,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix subtraction\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_sub_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix subtraction\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_sub_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix scaling.\r
- * @param[in] pSrc points to the input matrix\r
- * @param[in] scale scale factor\r
- * @param[out] pDst points to the output matrix\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_scale_f32(\r
- const arm_matrix_instance_f32 * pSrc,\r
- float32_t scale,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix scaling.\r
- * @param[in] pSrc points to input matrix\r
- * @param[in] scaleFract fractional portion of the scale factor\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] pDst points to output matrix\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_scale_q15(\r
- const arm_matrix_instance_q15 * pSrc,\r
- q15_t scaleFract,\r
- int32_t shift,\r
- arm_matrix_instance_q15 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix scaling.\r
- * @param[in] pSrc points to input matrix\r
- * @param[in] scaleFract fractional portion of the scale factor\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_scale_q31(\r
- const arm_matrix_instance_q31 * pSrc,\r
- q31_t scaleFract,\r
- int32_t shift,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix initialization.\r
- * @param[in,out] S points to an instance of the floating-point matrix structure.\r
- * @param[in] nRows number of rows in the matrix.\r
- * @param[in] nColumns number of columns in the matrix.\r
- * @param[in] pData points to the matrix data array.\r
- */\r
- void arm_mat_init_q31(\r
- arm_matrix_instance_q31 * S,\r
- uint16_t nRows,\r
- uint16_t nColumns,\r
- q31_t * pData);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix initialization.\r
- * @param[in,out] S points to an instance of the floating-point matrix structure.\r
- * @param[in] nRows number of rows in the matrix.\r
- * @param[in] nColumns number of columns in the matrix.\r
- * @param[in] pData points to the matrix data array.\r
- */\r
- void arm_mat_init_q15(\r
- arm_matrix_instance_q15 * S,\r
- uint16_t nRows,\r
- uint16_t nColumns,\r
- q15_t * pData);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix initialization.\r
- * @param[in,out] S points to an instance of the floating-point matrix structure.\r
- * @param[in] nRows number of rows in the matrix.\r
- * @param[in] nColumns number of columns in the matrix.\r
- * @param[in] pData points to the matrix data array.\r
- */\r
- void arm_mat_init_f32(\r
- arm_matrix_instance_f32 * S,\r
- uint16_t nRows,\r
- uint16_t nColumns,\r
- float32_t * pData);\r
-\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 PID Control.\r
- */\r
- typedef struct\r
- {\r
- q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
-#if !defined (ARM_MATH_DSP)\r
- q15_t A1;\r
- q15_t A2;\r
-#else\r
- q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/\r
-#endif\r
- q15_t state[3]; /**< The state array of length 3. */\r
- q15_t Kp; /**< The proportional gain. */\r
- q15_t Ki; /**< The integral gain. */\r
- q15_t Kd; /**< The derivative gain. */\r
- } arm_pid_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 PID Control.\r
- */\r
- typedef struct\r
- {\r
- q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
- q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
- q31_t A2; /**< The derived gain, A2 = Kd . */\r
- q31_t state[3]; /**< The state array of length 3. */\r
- q31_t Kp; /**< The proportional gain. */\r
- q31_t Ki; /**< The integral gain. */\r
- q31_t Kd; /**< The derivative gain. */\r
- } arm_pid_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point PID Control.\r
- */\r
- typedef struct\r
- {\r
- float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
- float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
- float32_t A2; /**< The derived gain, A2 = Kd . */\r
- float32_t state[3]; /**< The state array of length 3. */\r
- float32_t Kp; /**< The proportional gain. */\r
- float32_t Ki; /**< The integral gain. */\r
- float32_t Kd; /**< The derivative gain. */\r
- } arm_pid_instance_f32;\r
-\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point PID Control.\r
- * @param[in,out] S points to an instance of the PID structure.\r
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
- */\r
- void arm_pid_init_f32(\r
- arm_pid_instance_f32 * S,\r
- int32_t resetStateFlag);\r
-\r
-\r
- /**\r
- * @brief Reset function for the floating-point PID Control.\r
- * @param[in,out] S is an instance of the floating-point PID Control structure\r
- */\r
- void arm_pid_reset_f32(\r
- arm_pid_instance_f32 * S);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 PID Control.\r
- * @param[in,out] S points to an instance of the Q15 PID structure.\r
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
- */\r
- void arm_pid_init_q31(\r
- arm_pid_instance_q31 * S,\r
- int32_t resetStateFlag);\r
-\r
-\r
- /**\r
- * @brief Reset function for the Q31 PID Control.\r
- * @param[in,out] S points to an instance of the Q31 PID Control structure\r
- */\r
-\r
- void arm_pid_reset_q31(\r
- arm_pid_instance_q31 * S);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 PID Control.\r
- * @param[in,out] S points to an instance of the Q15 PID structure.\r
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
- */\r
- void arm_pid_init_q15(\r
- arm_pid_instance_q15 * S,\r
- int32_t resetStateFlag);\r
-\r
-\r
- /**\r
- * @brief Reset function for the Q15 PID Control.\r
- * @param[in,out] S points to an instance of the q15 PID Control structure\r
- */\r
- void arm_pid_reset_q15(\r
- arm_pid_instance_q15 * S);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point Linear Interpolate function.\r
- */\r
- typedef struct\r
- {\r
- uint32_t nValues; /**< nValues */\r
- float32_t x1; /**< x1 */\r
- float32_t xSpacing; /**< xSpacing */\r
- float32_t *pYData; /**< pointer to the table of Y values */\r
- } arm_linear_interp_instance_f32;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point bilinear interpolation function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows in the data table. */\r
- uint16_t numCols; /**< number of columns in the data table. */\r
- float32_t *pData; /**< points to the data table. */\r
- } arm_bilinear_interp_instance_f32;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 bilinear interpolation function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows in the data table. */\r
- uint16_t numCols; /**< number of columns in the data table. */\r
- q31_t *pData; /**< points to the data table. */\r
- } arm_bilinear_interp_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 bilinear interpolation function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows in the data table. */\r
- uint16_t numCols; /**< number of columns in the data table. */\r
- q15_t *pData; /**< points to the data table. */\r
- } arm_bilinear_interp_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 bilinear interpolation function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows in the data table. */\r
- uint16_t numCols; /**< number of columns in the data table. */\r
- q7_t *pData; /**< points to the data table. */\r
- } arm_bilinear_interp_instance_q7;\r
-\r
-\r
- /**\r
- * @brief Q7 vector multiplication.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_mult_q7(\r
- q7_t * pSrcA,\r
- q7_t * pSrcB,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q15 vector multiplication.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_mult_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q31 vector multiplication.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_mult_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Floating-point vector multiplication.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_mult_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- } arm_cfft_radix2_instance_q15;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix2_init_q15(\r
- arm_cfft_radix2_instance_q15 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix2_q15(\r
- const arm_cfft_radix2_instance_q15 * S,\r
- q15_t * pSrc);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- } arm_cfft_radix4_instance_q15;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix4_init_q15(\r
- arm_cfft_radix4_instance_q15 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix4_q15(\r
- const arm_cfft_radix4_instance_q15 * S,\r
- q15_t * pSrc);\r
-\r
- /**\r
- * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- q31_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- } arm_cfft_radix2_instance_q31;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix2_init_q31(\r
- arm_cfft_radix2_instance_q31 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix2_q31(\r
- const arm_cfft_radix2_instance_q31 * S,\r
- q31_t * pSrc);\r
-\r
- /**\r
- * @brief Instance structure for the Q31 CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- } arm_cfft_radix4_instance_q31;\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix4_q31(\r
- const arm_cfft_radix4_instance_q31 * S,\r
- q31_t * pSrc);\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix4_init_q31(\r
- arm_cfft_radix4_instance_q31 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- float32_t onebyfftLen; /**< value of 1/fftLen. */\r
- } arm_cfft_radix2_instance_f32;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix2_init_f32(\r
- arm_cfft_radix2_instance_f32 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix2_f32(\r
- const arm_cfft_radix2_instance_f32 * S,\r
- float32_t * pSrc);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- float32_t onebyfftLen; /**< value of 1/fftLen. */\r
- } arm_cfft_radix4_instance_f32;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix4_init_f32(\r
- arm_cfft_radix4_instance_f32 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix4_f32(\r
- const arm_cfft_radix4_instance_f32 * S,\r
- float32_t * pSrc);\r
-\r
- /**\r
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- const q15_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t bitRevLength; /**< bit reversal table length. */\r
- } arm_cfft_instance_q15;\r
-\r
-void arm_cfft_q15(\r
- const arm_cfft_instance_q15 * S,\r
- q15_t * p1,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
- /**\r
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- const q31_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t bitRevLength; /**< bit reversal table length. */\r
- } arm_cfft_instance_q31;\r
-\r
-void arm_cfft_q31(\r
- const arm_cfft_instance_q31 * S,\r
- q31_t * p1,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- const float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t bitRevLength; /**< bit reversal table length. */\r
- } arm_cfft_instance_f32;\r
-\r
- void arm_cfft_f32(\r
- const arm_cfft_instance_f32 * S,\r
- float32_t * p1,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
- /**\r
- * @brief Instance structure for the Q15 RFFT/RIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint32_t fftLenReal; /**< length of the real FFT. */\r
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
- q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
- const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_rfft_instance_q15;\r
-\r
- arm_status arm_rfft_init_q15(\r
- arm_rfft_instance_q15 * S,\r
- uint32_t fftLenReal,\r
- uint32_t ifftFlagR,\r
- uint32_t bitReverseFlag);\r
-\r
- void arm_rfft_q15(\r
- const arm_rfft_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst);\r
-\r
- /**\r
- * @brief Instance structure for the Q31 RFFT/RIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint32_t fftLenReal; /**< length of the real FFT. */\r
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
- q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
- const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_rfft_instance_q31;\r
-\r
- arm_status arm_rfft_init_q31(\r
- arm_rfft_instance_q31 * S,\r
- uint32_t fftLenReal,\r
- uint32_t ifftFlagR,\r
- uint32_t bitReverseFlag);\r
-\r
- void arm_rfft_q31(\r
- const arm_rfft_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint32_t fftLenReal; /**< length of the real FFT. */\r
- uint16_t fftLenBy2; /**< length of the complex FFT. */\r
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
- float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_rfft_instance_f32;\r
-\r
- arm_status arm_rfft_init_f32(\r
- arm_rfft_instance_f32 * S,\r
- arm_cfft_radix4_instance_f32 * S_CFFT,\r
- uint32_t fftLenReal,\r
- uint32_t ifftFlagR,\r
- uint32_t bitReverseFlag);\r
-\r
- void arm_rfft_f32(\r
- const arm_rfft_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
- */\r
-typedef struct\r
- {\r
- arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */\r
- uint16_t fftLenRFFT; /**< length of the real sequence */\r
- float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */\r
- } arm_rfft_fast_instance_f32 ;\r
-\r
-arm_status arm_rfft_fast_init_f32 (\r
- arm_rfft_fast_instance_f32 * S,\r
- uint16_t fftLen);\r
-\r
-void arm_rfft_fast_f32(\r
- arm_rfft_fast_instance_f32 * S,\r
- float32_t * p, float32_t * pOut,\r
- uint8_t ifftFlag);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point DCT4/IDCT4 function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t N; /**< length of the DCT4. */\r
- uint16_t Nby2; /**< half of the length of the DCT4. */\r
- float32_t normalize; /**< normalizing factor. */\r
- float32_t *pTwiddle; /**< points to the twiddle factor table. */\r
- float32_t *pCosFactor; /**< points to the cosFactor table. */\r
- arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */\r
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_dct4_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point DCT4/IDCT4.\r
- * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.\r
- * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.\r
- * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.\r
- * @param[in] N length of the DCT4.\r
- * @param[in] Nby2 half of the length of the DCT4.\r
- * @param[in] normalize normalizing factor.\r
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.\r
- */\r
- arm_status arm_dct4_init_f32(\r
- arm_dct4_instance_f32 * S,\r
- arm_rfft_instance_f32 * S_RFFT,\r
- arm_cfft_radix4_instance_f32 * S_CFFT,\r
- uint16_t N,\r
- uint16_t Nby2,\r
- float32_t normalize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point DCT4/IDCT4.\r
- * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.\r
- * @param[in] pState points to state buffer.\r
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.\r
- */\r
- void arm_dct4_f32(\r
- const arm_dct4_instance_f32 * S,\r
- float32_t * pState,\r
- float32_t * pInlineBuffer);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q31 DCT4/IDCT4 function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t N; /**< length of the DCT4. */\r
- uint16_t Nby2; /**< half of the length of the DCT4. */\r
- q31_t normalize; /**< normalizing factor. */\r
- q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
- q31_t *pCosFactor; /**< points to the cosFactor table. */\r
- arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */\r
- arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_dct4_instance_q31;\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 DCT4/IDCT4.\r
- * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.\r
- * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure\r
- * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure\r
- * @param[in] N length of the DCT4.\r
- * @param[in] Nby2 half of the length of the DCT4.\r
- * @param[in] normalize normalizing factor.\r
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
- */\r
- arm_status arm_dct4_init_q31(\r
- arm_dct4_instance_q31 * S,\r
- arm_rfft_instance_q31 * S_RFFT,\r
- arm_cfft_radix4_instance_q31 * S_CFFT,\r
- uint16_t N,\r
- uint16_t Nby2,\r
- q31_t normalize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 DCT4/IDCT4.\r
- * @param[in] S points to an instance of the Q31 DCT4 structure.\r
- * @param[in] pState points to state buffer.\r
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.\r
- */\r
- void arm_dct4_q31(\r
- const arm_dct4_instance_q31 * S,\r
- q31_t * pState,\r
- q31_t * pInlineBuffer);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 DCT4/IDCT4 function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t N; /**< length of the DCT4. */\r
- uint16_t Nby2; /**< half of the length of the DCT4. */\r
- q15_t normalize; /**< normalizing factor. */\r
- q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
- q15_t *pCosFactor; /**< points to the cosFactor table. */\r
- arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */\r
- arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_dct4_instance_q15;\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 DCT4/IDCT4.\r
- * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.\r
- * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.\r
- * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.\r
- * @param[in] N length of the DCT4.\r
- * @param[in] Nby2 half of the length of the DCT4.\r
- * @param[in] normalize normalizing factor.\r
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
- */\r
- arm_status arm_dct4_init_q15(\r
- arm_dct4_instance_q15 * S,\r
- arm_rfft_instance_q15 * S_RFFT,\r
- arm_cfft_radix4_instance_q15 * S_CFFT,\r
- uint16_t N,\r
- uint16_t Nby2,\r
- q15_t normalize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 DCT4/IDCT4.\r
- * @param[in] S points to an instance of the Q15 DCT4 structure.\r
- * @param[in] pState points to state buffer.\r
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.\r
- */\r
- void arm_dct4_q15(\r
- const arm_dct4_instance_q15 * S,\r
- q15_t * pState,\r
- q15_t * pInlineBuffer);\r
-\r
-\r
- /**\r
- * @brief Floating-point vector addition.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_add_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q7 vector addition.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_add_q7(\r
- q7_t * pSrcA,\r
- q7_t * pSrcB,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q15 vector addition.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_add_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q31 vector addition.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_add_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Floating-point vector subtraction.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_sub_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q7 vector subtraction.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_sub_q7(\r
- q7_t * pSrcA,\r
- q7_t * pSrcB,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q15 vector subtraction.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_sub_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q31 vector subtraction.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_sub_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Multiplies a floating-point vector by a scalar.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] scale scale factor to be applied\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_scale_f32(\r
- float32_t * pSrc,\r
- float32_t scale,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Multiplies a Q7 vector by a scalar.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] scaleFract fractional portion of the scale value\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_scale_q7(\r
- q7_t * pSrc,\r
- q7_t scaleFract,\r
- int8_t shift,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Multiplies a Q15 vector by a scalar.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] scaleFract fractional portion of the scale value\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_scale_q15(\r
- q15_t * pSrc,\r
- q15_t scaleFract,\r
- int8_t shift,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Multiplies a Q31 vector by a scalar.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] scaleFract fractional portion of the scale value\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_scale_q31(\r
- q31_t * pSrc,\r
- q31_t scaleFract,\r
- int8_t shift,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q7 vector absolute value.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[out] pDst points to the output buffer\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_abs_q7(\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Floating-point vector absolute value.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[out] pDst points to the output buffer\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_abs_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q15 vector absolute value.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[out] pDst points to the output buffer\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_abs_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q31 vector absolute value.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[out] pDst points to the output buffer\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_abs_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Dot product of floating-point vectors.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @param[out] result output result returned here\r
- */\r
- void arm_dot_prod_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- uint32_t blockSize,\r
- float32_t * result);\r
-\r
-\r
- /**\r
- * @brief Dot product of Q7 vectors.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @param[out] result output result returned here\r
- */\r
- void arm_dot_prod_q7(\r
- q7_t * pSrcA,\r
- q7_t * pSrcB,\r
- uint32_t blockSize,\r
- q31_t * result);\r
-\r
-\r
- /**\r
- * @brief Dot product of Q15 vectors.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @param[out] result output result returned here\r
- */\r
- void arm_dot_prod_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- uint32_t blockSize,\r
- q63_t * result);\r
-\r
-\r
- /**\r
- * @brief Dot product of Q31 vectors.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @param[out] result output result returned here\r
- */\r
- void arm_dot_prod_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- uint32_t blockSize,\r
- q63_t * result);\r
-\r
-\r
- /**\r
- * @brief Shifts the elements of a Q7 vector a specified number of bits.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_shift_q7(\r
- q7_t * pSrc,\r
- int8_t shiftBits,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Shifts the elements of a Q15 vector a specified number of bits.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_shift_q15(\r
- q15_t * pSrc,\r
- int8_t shiftBits,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Shifts the elements of a Q31 vector a specified number of bits.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_shift_q31(\r
- q31_t * pSrc,\r
- int8_t shiftBits,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Adds a constant offset to a floating-point vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] offset is the offset to be added\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_offset_f32(\r
- float32_t * pSrc,\r
- float32_t offset,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Adds a constant offset to a Q7 vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] offset is the offset to be added\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_offset_q7(\r
- q7_t * pSrc,\r
- q7_t offset,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Adds a constant offset to a Q15 vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] offset is the offset to be added\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_offset_q15(\r
- q15_t * pSrc,\r
- q15_t offset,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Adds a constant offset to a Q31 vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] offset is the offset to be added\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_offset_q31(\r
- q31_t * pSrc,\r
- q31_t offset,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Negates the elements of a floating-point vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_negate_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Negates the elements of a Q7 vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_negate_q7(\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Negates the elements of a Q15 vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_negate_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Negates the elements of a Q31 vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_negate_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Copies the elements of a floating-point vector.\r
- * @param[in] pSrc input pointer\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_copy_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Copies the elements of a Q7 vector.\r
- * @param[in] pSrc input pointer\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_copy_q7(\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Copies the elements of a Q15 vector.\r
- * @param[in] pSrc input pointer\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_copy_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Copies the elements of a Q31 vector.\r
- * @param[in] pSrc input pointer\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_copy_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Fills a constant value into a floating-point vector.\r
- * @param[in] value input value to be filled\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_fill_f32(\r
- float32_t value,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Fills a constant value into a Q7 vector.\r
- * @param[in] value input value to be filled\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_fill_q7(\r
- q7_t value,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Fills a constant value into a Q15 vector.\r
- * @param[in] value input value to be filled\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_fill_q15(\r
- q15_t value,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Fills a constant value into a Q31 vector.\r
- * @param[in] value input value to be filled\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_fill_q31(\r
- q31_t value,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-/**\r
- * @brief Convolution of floating-point sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
- */\r
- void arm_conv_f32(\r
- float32_t * pSrcA,\r
- uint32_t srcALen,\r
- float32_t * pSrcB,\r
- uint32_t srcBLen,\r
- float32_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q15 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
- */\r
- void arm_conv_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
-/**\r
- * @brief Convolution of Q15 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
- */\r
- void arm_conv_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- */\r
- void arm_conv_fast_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
- */\r
- void arm_conv_fast_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q31 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- */\r
- void arm_conv_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- */\r
- void arm_conv_fast_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q7 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
- */\r
- void arm_conv_opt_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q7 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- */\r
- void arm_conv_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of floating-point sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_f32(\r
- float32_t * pSrcA,\r
- uint32_t srcALen,\r
- float32_t * pSrcB,\r
- uint32_t srcBLen,\r
- float32_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q15 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q15 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_fast_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_fast_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q31 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_fast_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q7 sequences\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_opt_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
-/**\r
- * @brief Partial convolution of Q7 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 FIR decimator.\r
- */\r
- typedef struct\r
- {\r
- uint8_t M; /**< decimation factor. */\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- } arm_fir_decimate_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 FIR decimator.\r
- */\r
- typedef struct\r
- {\r
- uint8_t M; /**< decimation factor. */\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- } arm_fir_decimate_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point FIR decimator.\r
- */\r
- typedef struct\r
- {\r
- uint8_t M; /**< decimation factor. */\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- } arm_fir_decimate_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point FIR decimator.\r
- * @param[in] S points to an instance of the floating-point FIR decimator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_decimate_f32(\r
- const arm_fir_decimate_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point FIR decimator.\r
- * @param[in,out] S points to an instance of the floating-point FIR decimator structure.\r
- * @param[in] numTaps number of coefficients in the filter.\r
- * @param[in] M decimation factor.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * <code>blockSize</code> is not a multiple of <code>M</code>.\r
- */\r
- arm_status arm_fir_decimate_init_f32(\r
- arm_fir_decimate_instance_f32 * S,\r
- uint16_t numTaps,\r
- uint8_t M,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR decimator.\r
- * @param[in] S points to an instance of the Q15 FIR decimator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_decimate_q15(\r
- const arm_fir_decimate_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
- * @param[in] S points to an instance of the Q15 FIR decimator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_decimate_fast_q15(\r
- const arm_fir_decimate_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 FIR decimator.\r
- * @param[in,out] S points to an instance of the Q15 FIR decimator structure.\r
- * @param[in] numTaps number of coefficients in the filter.\r
- * @param[in] M decimation factor.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * <code>blockSize</code> is not a multiple of <code>M</code>.\r
- */\r
- arm_status arm_fir_decimate_init_q15(\r
- arm_fir_decimate_instance_q15 * S,\r
- uint16_t numTaps,\r
- uint8_t M,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR decimator.\r
- * @param[in] S points to an instance of the Q31 FIR decimator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_decimate_q31(\r
- const arm_fir_decimate_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
- * @param[in] S points to an instance of the Q31 FIR decimator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_decimate_fast_q31(\r
- arm_fir_decimate_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 FIR decimator.\r
- * @param[in,out] S points to an instance of the Q31 FIR decimator structure.\r
- * @param[in] numTaps number of coefficients in the filter.\r
- * @param[in] M decimation factor.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * <code>blockSize</code> is not a multiple of <code>M</code>.\r
- */\r
- arm_status arm_fir_decimate_init_q31(\r
- arm_fir_decimate_instance_q31 * S,\r
- uint16_t numTaps,\r
- uint8_t M,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 FIR interpolator.\r
- */\r
- typedef struct\r
- {\r
- uint8_t L; /**< upsample factor. */\r
- uint16_t phaseLength; /**< length of each polyphase filter component. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
- } arm_fir_interpolate_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 FIR interpolator.\r
- */\r
- typedef struct\r
- {\r
- uint8_t L; /**< upsample factor. */\r
- uint16_t phaseLength; /**< length of each polyphase filter component. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
- } arm_fir_interpolate_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point FIR interpolator.\r
- */\r
- typedef struct\r
- {\r
- uint8_t L; /**< upsample factor. */\r
- uint16_t phaseLength; /**< length of each polyphase filter component. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */\r
- } arm_fir_interpolate_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR interpolator.\r
- * @param[in] S points to an instance of the Q15 FIR interpolator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_interpolate_q15(\r
- const arm_fir_interpolate_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 FIR interpolator.\r
- * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.\r
- * @param[in] L upsample factor.\r
- * @param[in] numTaps number of filter coefficients in the filter.\r
- * @param[in] pCoeffs points to the filter coefficient buffer.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
- */\r
- arm_status arm_fir_interpolate_init_q15(\r
- arm_fir_interpolate_instance_q15 * S,\r
- uint8_t L,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR interpolator.\r
- * @param[in] S points to an instance of the Q15 FIR interpolator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_interpolate_q31(\r
- const arm_fir_interpolate_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 FIR interpolator.\r
- * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.\r
- * @param[in] L upsample factor.\r
- * @param[in] numTaps number of filter coefficients in the filter.\r
- * @param[in] pCoeffs points to the filter coefficient buffer.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
- */\r
- arm_status arm_fir_interpolate_init_q31(\r
- arm_fir_interpolate_instance_q31 * S,\r
- uint8_t L,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point FIR interpolator.\r
- * @param[in] S points to an instance of the floating-point FIR interpolator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_interpolate_f32(\r
- const arm_fir_interpolate_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point FIR interpolator.\r
- * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.\r
- * @param[in] L upsample factor.\r
- * @param[in] numTaps number of filter coefficients in the filter.\r
- * @param[in] pCoeffs points to the filter coefficient buffer.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
- */\r
- arm_status arm_fir_interpolate_init_f32(\r
- arm_fir_interpolate_instance_f32 * S,\r
- uint8_t L,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the high precision Q31 Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
- q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
- uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */\r
- } arm_biquad_cas_df1_32x64_ins_q31;\r
-\r
-\r
- /**\r
- * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cas_df1_32x64_q31(\r
- const arm_biquad_cas_df1_32x64_ins_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format\r
- */\r
- void arm_biquad_cas_df1_32x64_init_q31(\r
- arm_biquad_cas_df1_32x64_ins_q31 * S,\r
- uint8_t numStages,\r
- q31_t * pCoeffs,\r
- q63_t * pState,\r
- uint8_t postShift);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
- float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
- } arm_biquad_cascade_df2T_instance_f32;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
- float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
- } arm_biquad_cascade_stereo_df2T_instance_f32;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
- float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
- } arm_biquad_cascade_df2T_instance_f64;\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in] S points to an instance of the filter data structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df2T_f32(\r
- const arm_biquad_cascade_df2T_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels\r
- * @param[in] S points to an instance of the filter data structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_stereo_df2T_f32(\r
- const arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in] S points to an instance of the filter data structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df2T_f64(\r
- const arm_biquad_cascade_df2T_instance_f64 * S,\r
- float64_t * pSrc,\r
- float64_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in,out] S points to an instance of the filter data structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- */\r
- void arm_biquad_cascade_df2T_init_f32(\r
- arm_biquad_cascade_df2T_instance_f32 * S,\r
- uint8_t numStages,\r
- float32_t * pCoeffs,\r
- float32_t * pState);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in,out] S points to an instance of the filter data structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- */\r
- void arm_biquad_cascade_stereo_df2T_init_f32(\r
- arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r
- uint8_t numStages,\r
- float32_t * pCoeffs,\r
- float32_t * pState);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in,out] S points to an instance of the filter data structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- */\r
- void arm_biquad_cascade_df2T_init_f64(\r
- arm_biquad_cascade_df2T_instance_f64 * S,\r
- uint8_t numStages,\r
- float64_t * pCoeffs,\r
- float64_t * pState);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 FIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of filter stages. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
- } arm_fir_lattice_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 FIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of filter stages. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
- } arm_fir_lattice_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point FIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of filter stages. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
- } arm_fir_lattice_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 FIR lattice filter.\r
- * @param[in] S points to an instance of the Q15 FIR lattice structure.\r
- * @param[in] numStages number of filter stages.\r
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.\r
- * @param[in] pState points to the state buffer. The array is of length numStages.\r
- */\r
- void arm_fir_lattice_init_q15(\r
- arm_fir_lattice_instance_q15 * S,\r
- uint16_t numStages,\r
- q15_t * pCoeffs,\r
- q15_t * pState);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR lattice filter.\r
- * @param[in] S points to an instance of the Q15 FIR lattice structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_lattice_q15(\r
- const arm_fir_lattice_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 FIR lattice filter.\r
- * @param[in] S points to an instance of the Q31 FIR lattice structure.\r
- * @param[in] numStages number of filter stages.\r
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.\r
- * @param[in] pState points to the state buffer. The array is of length numStages.\r
- */\r
- void arm_fir_lattice_init_q31(\r
- arm_fir_lattice_instance_q31 * S,\r
- uint16_t numStages,\r
- q31_t * pCoeffs,\r
- q31_t * pState);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR lattice filter.\r
- * @param[in] S points to an instance of the Q31 FIR lattice structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_lattice_q31(\r
- const arm_fir_lattice_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-/**\r
- * @brief Initialization function for the floating-point FIR lattice filter.\r
- * @param[in] S points to an instance of the floating-point FIR lattice structure.\r
- * @param[in] numStages number of filter stages.\r
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.\r
- * @param[in] pState points to the state buffer. The array is of length numStages.\r
- */\r
- void arm_fir_lattice_init_f32(\r
- arm_fir_lattice_instance_f32 * S,\r
- uint16_t numStages,\r
- float32_t * pCoeffs,\r
- float32_t * pState);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point FIR lattice filter.\r
- * @param[in] S points to an instance of the floating-point FIR lattice structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_lattice_f32(\r
- const arm_fir_lattice_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 IIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of stages in the filter. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
- q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
- q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
- } arm_iir_lattice_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 IIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of stages in the filter. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
- q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
- q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
- } arm_iir_lattice_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point IIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of stages in the filter. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
- float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
- float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
- } arm_iir_lattice_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point IIR lattice filter.\r
- * @param[in] S points to an instance of the floating-point IIR lattice structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_iir_lattice_f32(\r
- const arm_iir_lattice_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point IIR lattice filter.\r
- * @param[in] S points to an instance of the floating-point IIR lattice structure.\r
- * @param[in] numStages number of stages in the filter.\r
- * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
- * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
- * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_iir_lattice_init_f32(\r
- arm_iir_lattice_instance_f32 * S,\r
- uint16_t numStages,\r
- float32_t * pkCoeffs,\r
- float32_t * pvCoeffs,\r
- float32_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 IIR lattice filter.\r
- * @param[in] S points to an instance of the Q31 IIR lattice structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_iir_lattice_q31(\r
- const arm_iir_lattice_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 IIR lattice filter.\r
- * @param[in] S points to an instance of the Q31 IIR lattice structure.\r
- * @param[in] numStages number of stages in the filter.\r
- * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
- * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
- * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_iir_lattice_init_q31(\r
- arm_iir_lattice_instance_q31 * S,\r
- uint16_t numStages,\r
- q31_t * pkCoeffs,\r
- q31_t * pvCoeffs,\r
- q31_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 IIR lattice filter.\r
- * @param[in] S points to an instance of the Q15 IIR lattice structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_iir_lattice_q15(\r
- const arm_iir_lattice_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-/**\r
- * @brief Initialization function for the Q15 IIR lattice filter.\r
- * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.\r
- * @param[in] numStages number of stages in the filter.\r
- * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.\r
- * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.\r
- * @param[in] pState points to state buffer. The array is of length numStages+blockSize.\r
- * @param[in] blockSize number of samples to process per call.\r
- */\r
- void arm_iir_lattice_init_q15(\r
- arm_iir_lattice_instance_q15 * S,\r
- uint16_t numStages,\r
- q15_t * pkCoeffs,\r
- q15_t * pvCoeffs,\r
- q15_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- float32_t mu; /**< step size that controls filter coefficient updates. */\r
- } arm_lms_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for floating-point LMS filter.\r
- * @param[in] S points to an instance of the floating-point LMS filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[in] pRef points to the block of reference data.\r
- * @param[out] pOut points to the block of output data.\r
- * @param[out] pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_f32(\r
- const arm_lms_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pRef,\r
- float32_t * pOut,\r
- float32_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for floating-point LMS filter.\r
- * @param[in] S points to an instance of the floating-point LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] pCoeffs points to the coefficient buffer.\r
- * @param[in] pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_init_f32(\r
- arm_lms_instance_f32 * S,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- float32_t mu,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- q15_t mu; /**< step size that controls filter coefficient updates. */\r
- uint32_t postShift; /**< bit shift applied to coefficients. */\r
- } arm_lms_instance_q15;\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 LMS filter.\r
- * @param[in] S points to an instance of the Q15 LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] pCoeffs points to the coefficient buffer.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- * @param[in] postShift bit shift applied to coefficients.\r
- */\r
- void arm_lms_init_q15(\r
- arm_lms_instance_q15 * S,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- q15_t mu,\r
- uint32_t blockSize,\r
- uint32_t postShift);\r
-\r
-\r
- /**\r
- * @brief Processing function for Q15 LMS filter.\r
- * @param[in] S points to an instance of the Q15 LMS filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[in] pRef points to the block of reference data.\r
- * @param[out] pOut points to the block of output data.\r
- * @param[out] pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_q15(\r
- const arm_lms_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pRef,\r
- q15_t * pOut,\r
- q15_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q31 LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- q31_t mu; /**< step size that controls filter coefficient updates. */\r
- uint32_t postShift; /**< bit shift applied to coefficients. */\r
- } arm_lms_instance_q31;\r
-\r
-\r
- /**\r
- * @brief Processing function for Q31 LMS filter.\r
- * @param[in] S points to an instance of the Q15 LMS filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[in] pRef points to the block of reference data.\r
- * @param[out] pOut points to the block of output data.\r
- * @param[out] pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_q31(\r
- const arm_lms_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pRef,\r
- q31_t * pOut,\r
- q31_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for Q31 LMS filter.\r
- * @param[in] S points to an instance of the Q31 LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] pCoeffs points to coefficient buffer.\r
- * @param[in] pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- * @param[in] postShift bit shift applied to coefficients.\r
- */\r
- void arm_lms_init_q31(\r
- arm_lms_instance_q31 * S,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- q31_t mu,\r
- uint32_t blockSize,\r
- uint32_t postShift);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point normalized LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- float32_t mu; /**< step size that control filter coefficient updates. */\r
- float32_t energy; /**< saves previous frame energy. */\r
- float32_t x0; /**< saves previous input sample. */\r
- } arm_lms_norm_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for floating-point normalized LMS filter.\r
- * @param[in] S points to an instance of the floating-point normalized LMS filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[in] pRef points to the block of reference data.\r
- * @param[out] pOut points to the block of output data.\r
- * @param[out] pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_norm_f32(\r
- arm_lms_norm_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pRef,\r
- float32_t * pOut,\r
- float32_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for floating-point normalized LMS filter.\r
- * @param[in] S points to an instance of the floating-point LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] pCoeffs points to coefficient buffer.\r
- * @param[in] pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_norm_init_f32(\r
- arm_lms_norm_instance_f32 * S,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- float32_t mu,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q31 normalized LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- q31_t mu; /**< step size that controls filter coefficient updates. */\r
- uint8_t postShift; /**< bit shift applied to coefficients. */\r
- q31_t *recipTable; /**< points to the reciprocal initial value table. */\r
- q31_t energy; /**< saves previous frame energy. */\r
- q31_t x0; /**< saves previous input sample. */\r
- } arm_lms_norm_instance_q31;\r
-\r
-\r
- /**\r
- * @brief Processing function for Q31 normalized LMS filter.\r
- * @param[in] S points to an instance of the Q31 normalized LMS filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[in] pRef points to the block of reference data.\r
- * @param[out] pOut points to the block of output data.\r
- * @param[out] pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_norm_q31(\r
- arm_lms_norm_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pRef,\r
- q31_t * pOut,\r
- q31_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for Q31 normalized LMS filter.\r
- * @param[in] S points to an instance of the Q31 normalized LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] pCoeffs points to coefficient buffer.\r
- * @param[in] pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- * @param[in] postShift bit shift applied to coefficients.\r
- */\r
- void arm_lms_norm_init_q31(\r
- arm_lms_norm_instance_q31 * S,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- q31_t mu,\r
- uint32_t blockSize,\r
- uint8_t postShift);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 normalized LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< Number of coefficients in the filter. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- q15_t mu; /**< step size that controls filter coefficient updates. */\r
- uint8_t postShift; /**< bit shift applied to coefficients. */\r
- q15_t *recipTable; /**< Points to the reciprocal initial value table. */\r
- q15_t energy; /**< saves previous frame energy. */\r
- q15_t x0; /**< saves previous input sample. */\r
- } arm_lms_norm_instance_q15;\r
-\r
-\r
- /**\r
- * @brief Processing function for Q15 normalized LMS filter.\r
- * @param[in] S points to an instance of the Q15 normalized LMS filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[in] pRef points to the block of reference data.\r
- * @param[out] pOut points to the block of output data.\r
- * @param[out] pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_norm_q15(\r
- arm_lms_norm_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pRef,\r
- q15_t * pOut,\r
- q15_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for Q15 normalized LMS filter.\r
- * @param[in] S points to an instance of the Q15 normalized LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] pCoeffs points to coefficient buffer.\r
- * @param[in] pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- * @param[in] postShift bit shift applied to coefficients.\r
- */\r
- void arm_lms_norm_init_q15(\r
- arm_lms_norm_instance_q15 * S,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- q15_t mu,\r
- uint32_t blockSize,\r
- uint8_t postShift);\r
-\r
-\r
- /**\r
- * @brief Correlation of floating-point sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- */\r
- void arm_correlate_f32(\r
- float32_t * pSrcA,\r
- uint32_t srcALen,\r
- float32_t * pSrcB,\r
- uint32_t srcBLen,\r
- float32_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q15 sequences\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- */\r
- void arm_correlate_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- q15_t * pScratch);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q15 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- */\r
-\r
- void arm_correlate_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- */\r
-\r
- void arm_correlate_fast_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- */\r
- void arm_correlate_fast_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- q15_t * pScratch);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q31 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- */\r
- void arm_correlate_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- */\r
- void arm_correlate_fast_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q7 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
- */\r
- void arm_correlate_opt_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q7 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- */\r
- void arm_correlate_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point sparse FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
- float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
- } arm_fir_sparse_instance_f32;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 sparse FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
- q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
- } arm_fir_sparse_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 sparse FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
- q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
- } arm_fir_sparse_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q7 sparse FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
- q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
- } arm_fir_sparse_instance_q7;\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point sparse FIR filter.\r
- * @param[in] S points to an instance of the floating-point sparse FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_sparse_f32(\r
- arm_fir_sparse_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- float32_t * pScratchIn,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point sparse FIR filter.\r
- * @param[in,out] S points to an instance of the floating-point sparse FIR structure.\r
- * @param[in] numTaps number of nonzero coefficients in the filter.\r
- * @param[in] pCoeffs points to the array of filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] pTapDelay points to the array of offset times.\r
- * @param[in] maxDelay maximum offset time supported.\r
- * @param[in] blockSize number of samples that will be processed per block.\r
- */\r
- void arm_fir_sparse_init_f32(\r
- arm_fir_sparse_instance_f32 * S,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- int32_t * pTapDelay,\r
- uint16_t maxDelay,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 sparse FIR filter.\r
- * @param[in] S points to an instance of the Q31 sparse FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_sparse_q31(\r
- arm_fir_sparse_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- q31_t * pScratchIn,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 sparse FIR filter.\r
- * @param[in,out] S points to an instance of the Q31 sparse FIR structure.\r
- * @param[in] numTaps number of nonzero coefficients in the filter.\r
- * @param[in] pCoeffs points to the array of filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] pTapDelay points to the array of offset times.\r
- * @param[in] maxDelay maximum offset time supported.\r
- * @param[in] blockSize number of samples that will be processed per block.\r
- */\r
- void arm_fir_sparse_init_q31(\r
- arm_fir_sparse_instance_q31 * S,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- int32_t * pTapDelay,\r
- uint16_t maxDelay,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 sparse FIR filter.\r
- * @param[in] S points to an instance of the Q15 sparse FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
- * @param[in] pScratchOut points to a temporary buffer of size blockSize.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_sparse_q15(\r
- arm_fir_sparse_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- q15_t * pScratchIn,\r
- q31_t * pScratchOut,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 sparse FIR filter.\r
- * @param[in,out] S points to an instance of the Q15 sparse FIR structure.\r
- * @param[in] numTaps number of nonzero coefficients in the filter.\r
- * @param[in] pCoeffs points to the array of filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] pTapDelay points to the array of offset times.\r
- * @param[in] maxDelay maximum offset time supported.\r
- * @param[in] blockSize number of samples that will be processed per block.\r
- */\r
- void arm_fir_sparse_init_q15(\r
- arm_fir_sparse_instance_q15 * S,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- int32_t * pTapDelay,\r
- uint16_t maxDelay,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q7 sparse FIR filter.\r
- * @param[in] S points to an instance of the Q7 sparse FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
- * @param[in] pScratchOut points to a temporary buffer of size blockSize.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_sparse_q7(\r
- arm_fir_sparse_instance_q7 * S,\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- q7_t * pScratchIn,\r
- q31_t * pScratchOut,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q7 sparse FIR filter.\r
- * @param[in,out] S points to an instance of the Q7 sparse FIR structure.\r
- * @param[in] numTaps number of nonzero coefficients in the filter.\r
- * @param[in] pCoeffs points to the array of filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] pTapDelay points to the array of offset times.\r
- * @param[in] maxDelay maximum offset time supported.\r
- * @param[in] blockSize number of samples that will be processed per block.\r
- */\r
- void arm_fir_sparse_init_q7(\r
- arm_fir_sparse_instance_q7 * S,\r
- uint16_t numTaps,\r
- q7_t * pCoeffs,\r
- q7_t * pState,\r
- int32_t * pTapDelay,\r
- uint16_t maxDelay,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Floating-point sin_cos function.\r
- * @param[in] theta input value in degrees\r
- * @param[out] pSinVal points to the processed sine output.\r
- * @param[out] pCosVal points to the processed cos output.\r
- */\r
- void arm_sin_cos_f32(\r
- float32_t theta,\r
- float32_t * pSinVal,\r
- float32_t * pCosVal);\r
-\r
-\r
- /**\r
- * @brief Q31 sin_cos function.\r
- * @param[in] theta scaled input value in degrees\r
- * @param[out] pSinVal points to the processed sine output.\r
- * @param[out] pCosVal points to the processed cosine output.\r
- */\r
- void arm_sin_cos_q31(\r
- q31_t theta,\r
- q31_t * pSinVal,\r
- q31_t * pCosVal);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex conjugate.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- */\r
- void arm_cmplx_conj_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t numSamples);\r
-\r
- /**\r
- * @brief Q31 complex conjugate.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- */\r
- void arm_cmplx_conj_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q15 complex conjugate.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- */\r
- void arm_cmplx_conj_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex magnitude squared\r
- * @param[in] pSrc points to the complex input vector\r
- * @param[out] pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- */\r
- void arm_cmplx_mag_squared_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q31 complex magnitude squared\r
- * @param[in] pSrc points to the complex input vector\r
- * @param[out] pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- */\r
- void arm_cmplx_mag_squared_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q15 complex magnitude squared\r
- * @param[in] pSrc points to the complex input vector\r
- * @param[out] pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- */\r
- void arm_cmplx_mag_squared_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup PID PID Motor Control\r
- *\r
- * A Proportional Integral Derivative (PID) controller is a generic feedback control\r
- * loop mechanism widely used in industrial control systems.\r
- * A PID controller is the most commonly used type of feedback controller.\r
- *\r
- * This set of functions implements (PID) controllers\r
- * for Q15, Q31, and floating-point data types. The functions operate on a single sample\r
- * of data and each call to the function returns a single processed value.\r
- * <code>S</code> points to an instance of the PID control data structure. <code>in</code>\r
- * is the input sample value. The functions return the output value.\r
- *\r
- * \par Algorithm:\r
- * <pre>\r
- * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\r
- * A0 = Kp + Ki + Kd\r
- * A1 = (-Kp ) - (2 * Kd )\r
- * A2 = Kd </pre>\r
- *\r
- * \par\r
- * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant\r
- *\r
- * \par\r
- * \image html PID.gif "Proportional Integral Derivative Controller"\r
- *\r
- * \par\r
- * The PID controller calculates an "error" value as the difference between\r
- * the measured output and the reference input.\r
- * The controller attempts to minimize the error by adjusting the process control inputs.\r
- * The proportional value determines the reaction to the current error,\r
- * the integral value determines the reaction based on the sum of recent errors,\r
- * and the derivative value determines the reaction based on the rate at which the error has been changing.\r
- *\r
- * \par Instance Structure\r
- * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.\r
- * A separate instance structure must be defined for each PID Controller.\r
- * There are separate instance structure declarations for each of the 3 supported data types.\r
- *\r
- * \par Reset Functions\r
- * There is also an associated reset function for each data type which clears the state array.\r
- *\r
- * \par Initialization Functions\r
- * There is also an associated initialization function for each data type.\r
- * The initialization function performs the following operations:\r
- * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.\r
- * - Zeros out the values in the state buffer.\r
- *\r
- * \par\r
- * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.\r
- *\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the fixed-point versions of the PID Controller functions.\r
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup PID\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Process function for the floating-point PID Control.\r
- * @param[in,out] S is an instance of the floating-point PID Control structure\r
- * @param[in] in input sample to process\r
- * @return out processed output sample.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(\r
- arm_pid_instance_f32 * S,\r
- float32_t in)\r
- {\r
- float32_t out;\r
-\r
- /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */\r
- out = (S->A0 * in) +\r
- (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);\r
-\r
- /* Update state */\r
- S->state[1] = S->state[0];\r
- S->state[0] = in;\r
- S->state[2] = out;\r
-\r
- /* return to application */\r
- return (out);\r
-\r
- }\r
-\r
- /**\r
- * @brief Process function for the Q31 PID Control.\r
- * @param[in,out] S points to an instance of the Q31 PID Control structure\r
- * @param[in] in input sample to process\r
- * @return out processed output sample.\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 64-bit accumulator.\r
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.\r
- * Thus, if the accumulator result overflows it wraps around rather than clip.\r
- * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.\r
- * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(\r
- arm_pid_instance_q31 * S,\r
- q31_t in)\r
- {\r
- q63_t acc;\r
- q31_t out;\r
-\r
- /* acc = A0 * x[n] */\r
- acc = (q63_t) S->A0 * in;\r
-\r
- /* acc += A1 * x[n-1] */\r
- acc += (q63_t) S->A1 * S->state[0];\r
-\r
- /* acc += A2 * x[n-2] */\r
- acc += (q63_t) S->A2 * S->state[1];\r
-\r
- /* convert output to 1.31 format to add y[n-1] */\r
- out = (q31_t) (acc >> 31u);\r
-\r
- /* out += y[n-1] */\r
- out += S->state[2];\r
-\r
- /* Update state */\r
- S->state[1] = S->state[0];\r
- S->state[0] = in;\r
- S->state[2] = out;\r
-\r
- /* return to application */\r
- return (out);\r
- }\r
-\r
-\r
- /**\r
- * @brief Process function for the Q15 PID Control.\r
- * @param[in,out] S points to an instance of the Q15 PID Control structure\r
- * @param[in] in input sample to process\r
- * @return out processed output sample.\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using a 64-bit internal accumulator.\r
- * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.\r
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.\r
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.\r
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.\r
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(\r
- arm_pid_instance_q15 * S,\r
- q15_t in)\r
- {\r
- q63_t acc;\r
- q15_t out;\r
-\r
-#if defined (ARM_MATH_DSP)\r
- __SIMD32_TYPE *vstate;\r
-\r
- /* Implementation of PID controller */\r
-\r
- /* acc = A0 * x[n] */\r
- acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);\r
-\r
- /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
- vstate = __SIMD32_CONST(S->state);\r
- acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);\r
-#else\r
- /* acc = A0 * x[n] */\r
- acc = ((q31_t) S->A0) * in;\r
-\r
- /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
- acc += (q31_t) S->A1 * S->state[0];\r
- acc += (q31_t) S->A2 * S->state[1];\r
-#endif\r
-\r
- /* acc += y[n-1] */\r
- acc += (q31_t) S->state[2] << 15;\r
-\r
- /* saturate the output */\r
- out = (q15_t) (__SSAT((acc >> 15), 16));\r
-\r
- /* Update state */\r
- S->state[1] = S->state[0];\r
- S->state[0] = in;\r
- S->state[2] = out;\r
-\r
- /* return to application */\r
- return (out);\r
- }\r
-\r
- /**\r
- * @} end of PID group\r
- */\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix inverse.\r
- * @param[in] src points to the instance of the input floating-point matrix structure.\r
- * @param[out] dst points to the instance of the output floating-point matrix structure.\r
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
- */\r
- arm_status arm_mat_inverse_f32(\r
- const arm_matrix_instance_f32 * src,\r
- arm_matrix_instance_f32 * dst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix inverse.\r
- * @param[in] src points to the instance of the input floating-point matrix structure.\r
- * @param[out] dst points to the instance of the output floating-point matrix structure.\r
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
- */\r
- arm_status arm_mat_inverse_f64(\r
- const arm_matrix_instance_f64 * src,\r
- arm_matrix_instance_f64 * dst);\r
-\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup clarke Vector Clarke Transform\r
- * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.\r
- * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents\r
- * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.\r
- * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below\r
- * \image html clarke.gif Stator current space vector and its components in (a,b).\r
- * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>\r
- * can be calculated using only <code>Ia</code> and <code>Ib</code>.\r
- *\r
- * The function operates on a single sample of data and each call to the function returns the processed output.\r
- * The library provides separate functions for Q31 and floating-point data types.\r
- * \par Algorithm\r
- * \image html clarkeFormula.gif\r
- * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and\r
- * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the Q31 version of the Clarke transform.\r
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup clarke\r
- * @{\r
- */\r
-\r
- /**\r
- *\r
- * @brief Floating-point Clarke transform\r
- * @param[in] Ia input three-phase coordinate <code>a</code>\r
- * @param[in] Ib input three-phase coordinate <code>b</code>\r
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(\r
- float32_t Ia,\r
- float32_t Ib,\r
- float32_t * pIalpha,\r
- float32_t * pIbeta)\r
- {\r
- /* Calculate pIalpha using the equation, pIalpha = Ia */\r
- *pIalpha = Ia;\r
-\r
- /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */\r
- *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);\r
- }\r
-\r
-\r
- /**\r
- * @brief Clarke transform for Q31 version\r
- * @param[in] Ia input three-phase coordinate <code>a</code>\r
- * @param[in] Ib input three-phase coordinate <code>b</code>\r
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 32-bit accumulator.\r
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
- * There is saturation on the addition, hence there is no risk of overflow.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(\r
- q31_t Ia,\r
- q31_t Ib,\r
- q31_t * pIalpha,\r
- q31_t * pIbeta)\r
- {\r
- q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
-\r
- /* Calculating pIalpha from Ia by equation pIalpha = Ia */\r
- *pIalpha = Ia;\r
-\r
- /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */\r
- product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);\r
-\r
- /* Intermediate product is calculated by (2/sqrt(3) * Ib) */\r
- product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);\r
-\r
- /* pIbeta is calculated by adding the intermediate products */\r
- *pIbeta = __QADD(product1, product2);\r
- }\r
-\r
- /**\r
- * @} end of clarke group\r
- */\r
-\r
- /**\r
- * @brief Converts the elements of the Q7 vector to Q31 vector.\r
- * @param[in] pSrc input pointer\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_q7_to_q31(\r
- q7_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup inv_clarke Vector Inverse Clarke Transform\r
- * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.\r
- *\r
- * The function operates on a single sample of data and each call to the function returns the processed output.\r
- * The library provides separate functions for Q31 and floating-point data types.\r
- * \par Algorithm\r
- * \image html clarkeInvFormula.gif\r
- * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and\r
- * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the Q31 version of the Clarke transform.\r
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup inv_clarke\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Floating-point Inverse Clarke transform\r
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
- * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
- * @param[out] pIa points to output three-phase coordinate <code>a</code>\r
- * @param[out] pIb points to output three-phase coordinate <code>b</code>\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(\r
- float32_t Ialpha,\r
- float32_t Ibeta,\r
- float32_t * pIa,\r
- float32_t * pIb)\r
- {\r
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
- *pIa = Ialpha;\r
-\r
- /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */\r
- *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;\r
- }\r
-\r
-\r
- /**\r
- * @brief Inverse Clarke transform for Q31 version\r
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
- * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
- * @param[out] pIa points to output three-phase coordinate <code>a</code>\r
- * @param[out] pIb points to output three-phase coordinate <code>b</code>\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 32-bit accumulator.\r
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
- * There is saturation on the subtraction, hence there is no risk of overflow.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(\r
- q31_t Ialpha,\r
- q31_t Ibeta,\r
- q31_t * pIa,\r
- q31_t * pIb)\r
- {\r
- q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
-\r
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
- *pIa = Ialpha;\r
-\r
- /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */\r
- product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);\r
-\r
- /* Intermediate product is calculated by (1/sqrt(3) * pIb) */\r
- product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);\r
-\r
- /* pIb is calculated by subtracting the products */\r
- *pIb = __QSUB(product2, product1);\r
- }\r
-\r
- /**\r
- * @} end of inv_clarke group\r
- */\r
-\r
- /**\r
- * @brief Converts the elements of the Q7 vector to Q15 vector.\r
- * @param[in] pSrc input pointer\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_q7_to_q15(\r
- q7_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup park Vector Park Transform\r
- *\r
- * Forward Park transform converts the input two-coordinate vector to flux and torque components.\r
- * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents\r
- * from the stationary to the moving reference frame and control the spatial relationship between\r
- * the stator vector current and rotor flux vector.\r
- * If we consider the d axis aligned with the rotor flux, the diagram below shows the\r
- * current vector and the relationship from the two reference frames:\r
- * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"\r
- *\r
- * The function operates on a single sample of data and each call to the function returns the processed output.\r
- * The library provides separate functions for Q31 and floating-point data types.\r
- * \par Algorithm\r
- * \image html parkFormula.gif\r
- * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,\r
- * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
- * cosine and sine values of theta (rotor flux position).\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the Q31 version of the Park transform.\r
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup park\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Floating-point Park transform\r
- * @param[in] Ialpha input two-phase vector coordinate alpha\r
- * @param[in] Ibeta input two-phase vector coordinate beta\r
- * @param[out] pId points to output rotor reference frame d\r
- * @param[out] pIq points to output rotor reference frame q\r
- * @param[in] sinVal sine value of rotation angle theta\r
- * @param[in] cosVal cosine value of rotation angle theta\r
- *\r
- * The function implements the forward Park transform.\r
- *\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_park_f32(\r
- float32_t Ialpha,\r
- float32_t Ibeta,\r
- float32_t * pId,\r
- float32_t * pIq,\r
- float32_t sinVal,\r
- float32_t cosVal)\r
- {\r
- /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */\r
- *pId = Ialpha * cosVal + Ibeta * sinVal;\r
-\r
- /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */\r
- *pIq = -Ialpha * sinVal + Ibeta * cosVal;\r
- }\r
-\r
-\r
- /**\r
- * @brief Park transform for Q31 version\r
- * @param[in] Ialpha input two-phase vector coordinate alpha\r
- * @param[in] Ibeta input two-phase vector coordinate beta\r
- * @param[out] pId points to output rotor reference frame d\r
- * @param[out] pIq points to output rotor reference frame q\r
- * @param[in] sinVal sine value of rotation angle theta\r
- * @param[in] cosVal cosine value of rotation angle theta\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 32-bit accumulator.\r
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
- * There is saturation on the addition and subtraction, hence there is no risk of overflow.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_park_q31(\r
- q31_t Ialpha,\r
- q31_t Ibeta,\r
- q31_t * pId,\r
- q31_t * pIq,\r
- q31_t sinVal,\r
- q31_t cosVal)\r
- {\r
- q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
- q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
-\r
- /* Intermediate product is calculated by (Ialpha * cosVal) */\r
- product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);\r
-\r
- /* Intermediate product is calculated by (Ibeta * sinVal) */\r
- product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);\r
-\r
-\r
- /* Intermediate product is calculated by (Ialpha * sinVal) */\r
- product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);\r
-\r
- /* Intermediate product is calculated by (Ibeta * cosVal) */\r
- product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);\r
-\r
- /* Calculate pId by adding the two intermediate products 1 and 2 */\r
- *pId = __QADD(product1, product2);\r
-\r
- /* Calculate pIq by subtracting the two intermediate products 3 from 4 */\r
- *pIq = __QSUB(product4, product3);\r
- }\r
-\r
- /**\r
- * @} end of park group\r
- */\r
-\r
- /**\r
- * @brief Converts the elements of the Q7 vector to floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q7_to_float(\r
- q7_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup inv_park Vector Inverse Park transform\r
- * Inverse Park transform converts the input flux and torque components to two-coordinate vector.\r
- *\r
- * The function operates on a single sample of data and each call to the function returns the processed output.\r
- * The library provides separate functions for Q31 and floating-point data types.\r
- * \par Algorithm\r
- * \image html parkInvFormula.gif\r
- * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,\r
- * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
- * cosine and sine values of theta (rotor flux position).\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the Q31 version of the Park transform.\r
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup inv_park\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Floating-point Inverse Park transform\r
- * @param[in] Id input coordinate of rotor reference frame d\r
- * @param[in] Iq input coordinate of rotor reference frame q\r
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
- * @param[in] sinVal sine value of rotation angle theta\r
- * @param[in] cosVal cosine value of rotation angle theta\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(\r
- float32_t Id,\r
- float32_t Iq,\r
- float32_t * pIalpha,\r
- float32_t * pIbeta,\r
- float32_t sinVal,\r
- float32_t cosVal)\r
- {\r
- /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */\r
- *pIalpha = Id * cosVal - Iq * sinVal;\r
-\r
- /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */\r
- *pIbeta = Id * sinVal + Iq * cosVal;\r
- }\r
-\r
-\r
- /**\r
- * @brief Inverse Park transform for Q31 version\r
- * @param[in] Id input coordinate of rotor reference frame d\r
- * @param[in] Iq input coordinate of rotor reference frame q\r
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
- * @param[in] sinVal sine value of rotation angle theta\r
- * @param[in] cosVal cosine value of rotation angle theta\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 32-bit accumulator.\r
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
- * There is saturation on the addition, hence there is no risk of overflow.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(\r
- q31_t Id,\r
- q31_t Iq,\r
- q31_t * pIalpha,\r
- q31_t * pIbeta,\r
- q31_t sinVal,\r
- q31_t cosVal)\r
- {\r
- q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
- q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
-\r
- /* Intermediate product is calculated by (Id * cosVal) */\r
- product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);\r
-\r
- /* Intermediate product is calculated by (Iq * sinVal) */\r
- product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);\r
-\r
-\r
- /* Intermediate product is calculated by (Id * sinVal) */\r
- product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);\r
-\r
- /* Intermediate product is calculated by (Iq * cosVal) */\r
- product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);\r
-\r
- /* Calculate pIalpha by using the two intermediate products 1 and 2 */\r
- *pIalpha = __QSUB(product1, product2);\r
-\r
- /* Calculate pIbeta by using the two intermediate products 3 and 4 */\r
- *pIbeta = __QADD(product4, product3);\r
- }\r
-\r
- /**\r
- * @} end of Inverse park group\r
- */\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q31 vector to floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q31_to_float(\r
- q31_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @ingroup groupInterpolation\r
- */\r
-\r
- /**\r
- * @defgroup LinearInterpolate Linear Interpolation\r
- *\r
- * Linear interpolation is a method of curve fitting using linear polynomials.\r
- * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line\r
- *\r
- * \par\r
- * \image html LinearInterp.gif "Linear interpolation"\r
- *\r
- * \par\r
- * A Linear Interpolate function calculates an output value(y), for the input(x)\r
- * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)\r
- *\r
- * \par Algorithm:\r
- * <pre>\r
- * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\r
- * where x0, x1 are nearest values of input x\r
- * y0, y1 are nearest values to output y\r
- * </pre>\r
- *\r
- * \par\r
- * This set of functions implements Linear interpolation process\r
- * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single\r
- * sample of data and each call to the function returns a single processed value.\r
- * <code>S</code> points to an instance of the Linear Interpolate function data structure.\r
- * <code>x</code> is the input sample value. The functions returns the output value.\r
- *\r
- * \par\r
- * if x is outside of the table boundary, Linear interpolation returns first value of the table\r
- * if x is below input range and returns last value of table if x is above range.\r
- */\r
-\r
- /**\r
- * @addtogroup LinearInterpolate\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Process function for the floating-point Linear Interpolation Function.\r
- * @param[in,out] S is an instance of the floating-point Linear Interpolation structure\r
- * @param[in] x input sample to process\r
- * @return y processed output sample.\r
- *\r
- */\r
- CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(\r
- arm_linear_interp_instance_f32 * S,\r
- float32_t x)\r
- {\r
- float32_t y;\r
- float32_t x0, x1; /* Nearest input values */\r
- float32_t y0, y1; /* Nearest output values */\r
- float32_t xSpacing = S->xSpacing; /* spacing between input values */\r
- int32_t i; /* Index variable */\r
- float32_t *pYData = S->pYData; /* pointer to output table */\r
-\r
- /* Calculation of index */\r
- i = (int32_t) ((x - S->x1) / xSpacing);\r
-\r
- if (i < 0)\r
- {\r
- /* Iniatilize output for below specified range as least output value of table */\r
- y = pYData[0];\r
- }\r
- else if ((uint32_t)i >= S->nValues)\r
- {\r
- /* Iniatilize output for above specified range as last output value of table */\r
- y = pYData[S->nValues - 1];\r
- }\r
- else\r
- {\r
- /* Calculation of nearest input values */\r
- x0 = S->x1 + i * xSpacing;\r
- x1 = S->x1 + (i + 1) * xSpacing;\r
-\r
- /* Read of nearest output values */\r
- y0 = pYData[i];\r
- y1 = pYData[i + 1];\r
-\r
- /* Calculation of output */\r
- y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));\r
-\r
- }\r
-\r
- /* returns output value */\r
- return (y);\r
- }\r
-\r
-\r
- /**\r
- *\r
- * @brief Process function for the Q31 Linear Interpolation Function.\r
- * @param[in] pYData pointer to Q31 Linear Interpolation table\r
- * @param[in] x input sample to process\r
- * @param[in] nValues number of table values\r
- * @return y processed output sample.\r
- *\r
- * \par\r
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
- * This function can support maximum of table size 2^12.\r
- *\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(\r
- q31_t * pYData,\r
- q31_t x,\r
- uint32_t nValues)\r
- {\r
- q31_t y; /* output */\r
- q31_t y0, y1; /* Nearest output values */\r
- q31_t fract; /* fractional part */\r
- int32_t index; /* Index to read nearest output values */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- index = ((x & (q31_t)0xFFF00000) >> 20);\r
-\r
- if (index >= (int32_t)(nValues - 1))\r
- {\r
- return (pYData[nValues - 1]);\r
- }\r
- else if (index < 0)\r
- {\r
- return (pYData[0]);\r
- }\r
- else\r
- {\r
- /* 20 bits for the fractional part */\r
- /* shift left by 11 to keep fract in 1.31 format */\r
- fract = (x & 0x000FFFFF) << 11;\r
-\r
- /* Read two nearest output values from the index in 1.31(q31) format */\r
- y0 = pYData[index];\r
- y1 = pYData[index + 1];\r
-\r
- /* Calculation of y0 * (1-fract) and y is in 2.30 format */\r
- y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));\r
-\r
- /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */\r
- y += ((q31_t) (((q63_t) y1 * fract) >> 32));\r
-\r
- /* Convert y to 1.31 format */\r
- return (y << 1u);\r
- }\r
- }\r
-\r
-\r
- /**\r
- *\r
- * @brief Process function for the Q15 Linear Interpolation Function.\r
- * @param[in] pYData pointer to Q15 Linear Interpolation table\r
- * @param[in] x input sample to process\r
- * @param[in] nValues number of table values\r
- * @return y processed output sample.\r
- *\r
- * \par\r
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
- * This function can support maximum of table size 2^12.\r
- *\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(\r
- q15_t * pYData,\r
- q31_t x,\r
- uint32_t nValues)\r
- {\r
- q63_t y; /* output */\r
- q15_t y0, y1; /* Nearest output values */\r
- q31_t fract; /* fractional part */\r
- int32_t index; /* Index to read nearest output values */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- index = ((x & (int32_t)0xFFF00000) >> 20);\r
-\r
- if (index >= (int32_t)(nValues - 1))\r
- {\r
- return (pYData[nValues - 1]);\r
- }\r
- else if (index < 0)\r
- {\r
- return (pYData[0]);\r
- }\r
- else\r
- {\r
- /* 20 bits for the fractional part */\r
- /* fract is in 12.20 format */\r
- fract = (x & 0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- y0 = pYData[index];\r
- y1 = pYData[index + 1];\r
-\r
- /* Calculation of y0 * (1-fract) and y is in 13.35 format */\r
- y = ((q63_t) y0 * (0xFFFFF - fract));\r
-\r
- /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */\r
- y += ((q63_t) y1 * (fract));\r
-\r
- /* convert y to 1.15 format */\r
- return (q15_t) (y >> 20);\r
- }\r
- }\r
-\r
-\r
- /**\r
- *\r
- * @brief Process function for the Q7 Linear Interpolation Function.\r
- * @param[in] pYData pointer to Q7 Linear Interpolation table\r
- * @param[in] x input sample to process\r
- * @param[in] nValues number of table values\r
- * @return y processed output sample.\r
- *\r
- * \par\r
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
- * This function can support maximum of table size 2^12.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(\r
- q7_t * pYData,\r
- q31_t x,\r
- uint32_t nValues)\r
- {\r
- q31_t y; /* output */\r
- q7_t y0, y1; /* Nearest output values */\r
- q31_t fract; /* fractional part */\r
- uint32_t index; /* Index to read nearest output values */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- if (x < 0)\r
- {\r
- return (pYData[0]);\r
- }\r
- index = (x >> 20) & 0xfff;\r
-\r
- if (index >= (nValues - 1))\r
- {\r
- return (pYData[nValues - 1]);\r
- }\r
- else\r
- {\r
- /* 20 bits for the fractional part */\r
- /* fract is in 12.20 format */\r
- fract = (x & 0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index and are in 1.7(q7) format */\r
- y0 = pYData[index];\r
- y1 = pYData[index + 1];\r
-\r
- /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */\r
- y = ((y0 * (0xFFFFF - fract)));\r
-\r
- /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */\r
- y += (y1 * fract);\r
-\r
- /* convert y to 1.7(q7) format */\r
- return (q7_t) (y >> 20);\r
- }\r
- }\r
-\r
- /**\r
- * @} end of LinearInterpolate group\r
- */\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric sine function for floating-point data.\r
- * @param[in] x input value in radians.\r
- * @return sin(x).\r
- */\r
- float32_t arm_sin_f32(\r
- float32_t x);\r
-\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric sine function for Q31 data.\r
- * @param[in] x Scaled input value in radians.\r
- * @return sin(x).\r
- */\r
- q31_t arm_sin_q31(\r
- q31_t x);\r
-\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric sine function for Q15 data.\r
- * @param[in] x Scaled input value in radians.\r
- * @return sin(x).\r
- */\r
- q15_t arm_sin_q15(\r
- q15_t x);\r
-\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric cosine function for floating-point data.\r
- * @param[in] x input value in radians.\r
- * @return cos(x).\r
- */\r
- float32_t arm_cos_f32(\r
- float32_t x);\r
-\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric cosine function for Q31 data.\r
- * @param[in] x Scaled input value in radians.\r
- * @return cos(x).\r
- */\r
- q31_t arm_cos_q31(\r
- q31_t x);\r
-\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric cosine function for Q15 data.\r
- * @param[in] x Scaled input value in radians.\r
- * @return cos(x).\r
- */\r
- q15_t arm_cos_q15(\r
- q15_t x);\r
-\r
-\r
- /**\r
- * @ingroup groupFastMath\r
- */\r
-\r
-\r
- /**\r
- * @defgroup SQRT Square Root\r
- *\r
- * Computes the square root of a number.\r
- * There are separate functions for Q15, Q31, and floating-point data types.\r
- * The square root function is computed using the Newton-Raphson algorithm.\r
- * This is an iterative algorithm of the form:\r
- * <pre>\r
- * x1 = x0 - f(x0)/f'(x0)\r
- * </pre>\r
- * where <code>x1</code> is the current estimate,\r
- * <code>x0</code> is the previous estimate, and\r
- * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.\r
- * For the square root function, the algorithm reduces to:\r
- * <pre>\r
- * x0 = in/2 [initial guess]\r
- * x1 = 1/2 * ( x0 + in / x0) [each iteration]\r
- * </pre>\r
- */\r
-\r
-\r
- /**\r
- * @addtogroup SQRT\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Floating-point square root function.\r
- * @param[in] in input value.\r
- * @param[out] pOut square root of input value.\r
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
- * <code>in</code> is negative value and returns zero output for negative values.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(\r
- float32_t in,\r
- float32_t * pOut)\r
- {\r
- if (in >= 0.0f)\r
- {\r
-\r
-#if (__FPU_USED == 1) && defined ( __CC_ARM )\r
- *pOut = __sqrtf(in);\r
-#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\r
- *pOut = __builtin_sqrtf(in);\r
-#elif (__FPU_USED == 1) && defined(__GNUC__)\r
- *pOut = __builtin_sqrtf(in);\r
-#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)\r
- __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));\r
-#else\r
- *pOut = sqrtf(in);\r
-#endif\r
-\r
- return (ARM_MATH_SUCCESS);\r
- }\r
- else\r
- {\r
- *pOut = 0.0f;\r
- return (ARM_MATH_ARGUMENT_ERROR);\r
- }\r
- }\r
-\r
-\r
- /**\r
- * @brief Q31 square root function.\r
- * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.\r
- * @param[out] pOut square root of input value.\r
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
- * <code>in</code> is negative value and returns zero output for negative values.\r
- */\r
- arm_status arm_sqrt_q31(\r
- q31_t in,\r
- q31_t * pOut);\r
-\r
-\r
- /**\r
- * @brief Q15 square root function.\r
- * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.\r
- * @param[out] pOut square root of input value.\r
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
- * <code>in</code> is negative value and returns zero output for negative values.\r
- */\r
- arm_status arm_sqrt_q15(\r
- q15_t in,\r
- q15_t * pOut);\r
-\r
- /**\r
- * @} end of SQRT group\r
- */\r
-\r
-\r
- /**\r
- * @brief floating-point Circular write function.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(\r
- int32_t * circBuffer,\r
- int32_t L,\r
- uint16_t * writeOffset,\r
- int32_t bufferInc,\r
- const int32_t * src,\r
- int32_t srcInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0u;\r
- int32_t wOffset;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location where the input samples to be copied */\r
- wOffset = *writeOffset;\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while (i > 0u)\r
- {\r
- /* copy the input sample to the circular buffer */\r
- circBuffer[wOffset] = *src;\r
-\r
- /* Update the input pointer */\r
- src += srcInc;\r
-\r
- /* Circularly update wOffset. Watch out for positive and negative value */\r
- wOffset += bufferInc;\r
- if (wOffset >= L)\r
- wOffset -= L;\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *writeOffset = (uint16_t)wOffset;\r
- }\r
-\r
-\r
-\r
- /**\r
- * @brief floating-point Circular Read function.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(\r
- int32_t * circBuffer,\r
- int32_t L,\r
- int32_t * readOffset,\r
- int32_t bufferInc,\r
- int32_t * dst,\r
- int32_t * dst_base,\r
- int32_t dst_length,\r
- int32_t dstInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0u;\r
- int32_t rOffset, dst_end;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location from where the input samples to be read */\r
- rOffset = *readOffset;\r
- dst_end = (int32_t) (dst_base + dst_length);\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while (i > 0u)\r
- {\r
- /* copy the sample from the circular buffer to the destination buffer */\r
- *dst = circBuffer[rOffset];\r
-\r
- /* Update the input pointer */\r
- dst += dstInc;\r
-\r
- if (dst == (int32_t *) dst_end)\r
- {\r
- dst = dst_base;\r
- }\r
-\r
- /* Circularly update rOffset. Watch out for positive and negative value */\r
- rOffset += bufferInc;\r
-\r
- if (rOffset >= L)\r
- {\r
- rOffset -= L;\r
- }\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *readOffset = rOffset;\r
- }\r
-\r
-\r
- /**\r
- * @brief Q15 Circular write function.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(\r
- q15_t * circBuffer,\r
- int32_t L,\r
- uint16_t * writeOffset,\r
- int32_t bufferInc,\r
- const q15_t * src,\r
- int32_t srcInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0u;\r
- int32_t wOffset;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location where the input samples to be copied */\r
- wOffset = *writeOffset;\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while (i > 0u)\r
- {\r
- /* copy the input sample to the circular buffer */\r
- circBuffer[wOffset] = *src;\r
-\r
- /* Update the input pointer */\r
- src += srcInc;\r
-\r
- /* Circularly update wOffset. Watch out for positive and negative value */\r
- wOffset += bufferInc;\r
- if (wOffset >= L)\r
- wOffset -= L;\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *writeOffset = (uint16_t)wOffset;\r
- }\r
-\r
-\r
- /**\r
- * @brief Q15 Circular Read function.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(\r
- q15_t * circBuffer,\r
- int32_t L,\r
- int32_t * readOffset,\r
- int32_t bufferInc,\r
- q15_t * dst,\r
- q15_t * dst_base,\r
- int32_t dst_length,\r
- int32_t dstInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0;\r
- int32_t rOffset, dst_end;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location from where the input samples to be read */\r
- rOffset = *readOffset;\r
-\r
- dst_end = (int32_t) (dst_base + dst_length);\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while (i > 0u)\r
- {\r
- /* copy the sample from the circular buffer to the destination buffer */\r
- *dst = circBuffer[rOffset];\r
-\r
- /* Update the input pointer */\r
- dst += dstInc;\r
-\r
- if (dst == (q15_t *) dst_end)\r
- {\r
- dst = dst_base;\r
- }\r
-\r
- /* Circularly update wOffset. Watch out for positive and negative value */\r
- rOffset += bufferInc;\r
-\r
- if (rOffset >= L)\r
- {\r
- rOffset -= L;\r
- }\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *readOffset = rOffset;\r
- }\r
-\r
-\r
- /**\r
- * @brief Q7 Circular write function.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(\r
- q7_t * circBuffer,\r
- int32_t L,\r
- uint16_t * writeOffset,\r
- int32_t bufferInc,\r
- const q7_t * src,\r
- int32_t srcInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0u;\r
- int32_t wOffset;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location where the input samples to be copied */\r
- wOffset = *writeOffset;\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while (i > 0u)\r
- {\r
- /* copy the input sample to the circular buffer */\r
- circBuffer[wOffset] = *src;\r
-\r
- /* Update the input pointer */\r
- src += srcInc;\r
-\r
- /* Circularly update wOffset. Watch out for positive and negative value */\r
- wOffset += bufferInc;\r
- if (wOffset >= L)\r
- wOffset -= L;\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *writeOffset = (uint16_t)wOffset;\r
- }\r
-\r
-\r
- /**\r
- * @brief Q7 Circular Read function.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(\r
- q7_t * circBuffer,\r
- int32_t L,\r
- int32_t * readOffset,\r
- int32_t bufferInc,\r
- q7_t * dst,\r
- q7_t * dst_base,\r
- int32_t dst_length,\r
- int32_t dstInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0;\r
- int32_t rOffset, dst_end;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location from where the input samples to be read */\r
- rOffset = *readOffset;\r
-\r
- dst_end = (int32_t) (dst_base + dst_length);\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while (i > 0u)\r
- {\r
- /* copy the sample from the circular buffer to the destination buffer */\r
- *dst = circBuffer[rOffset];\r
-\r
- /* Update the input pointer */\r
- dst += dstInc;\r
-\r
- if (dst == (q7_t *) dst_end)\r
- {\r
- dst = dst_base;\r
- }\r
-\r
- /* Circularly update rOffset. Watch out for positive and negative value */\r
- rOffset += bufferInc;\r
-\r
- if (rOffset >= L)\r
- {\r
- rOffset -= L;\r
- }\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *readOffset = rOffset;\r
- }\r
-\r
-\r
- /**\r
- * @brief Sum of the squares of the elements of a Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_power_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q63_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Sum of the squares of the elements of a floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_power_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Sum of the squares of the elements of a Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_power_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q63_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Sum of the squares of the elements of a Q7 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_power_q7(\r
- q7_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Mean value of a Q7 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_mean_q7(\r
- q7_t * pSrc,\r
- uint32_t blockSize,\r
- q7_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Mean value of a Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_mean_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Mean value of a Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_mean_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Mean value of a floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_mean_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Variance of the elements of a floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_var_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Variance of the elements of a Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_var_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Variance of the elements of a Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_var_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Root Mean Square of the elements of a floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_rms_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Root Mean Square of the elements of a Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_rms_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Root Mean Square of the elements of a Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_rms_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Standard deviation of the elements of a floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_std_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Standard deviation of the elements of a Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_std_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Standard deviation of the elements of a Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_std_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex magnitude\r
- * @param[in] pSrc points to the complex input vector\r
- * @param[out] pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- */\r
- void arm_cmplx_mag_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q31 complex magnitude\r
- * @param[in] pSrc points to the complex input vector\r
- * @param[out] pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- */\r
- void arm_cmplx_mag_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q15 complex magnitude\r
- * @param[in] pSrc points to the complex input vector\r
- * @param[out] pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- */\r
- void arm_cmplx_mag_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q15 complex dot product\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- * @param[out] realResult real part of the result returned here\r
- * @param[out] imagResult imaginary part of the result returned here\r
- */\r
- void arm_cmplx_dot_prod_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- uint32_t numSamples,\r
- q31_t * realResult,\r
- q31_t * imagResult);\r
-\r
-\r
- /**\r
- * @brief Q31 complex dot product\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- * @param[out] realResult real part of the result returned here\r
- * @param[out] imagResult imaginary part of the result returned here\r
- */\r
- void arm_cmplx_dot_prod_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- uint32_t numSamples,\r
- q63_t * realResult,\r
- q63_t * imagResult);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex dot product\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- * @param[out] realResult real part of the result returned here\r
- * @param[out] imagResult imaginary part of the result returned here\r
- */\r
- void arm_cmplx_dot_prod_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- uint32_t numSamples,\r
- float32_t * realResult,\r
- float32_t * imagResult);\r
-\r
-\r
- /**\r
- * @brief Q15 complex-by-real multiplication\r
- * @param[in] pSrcCmplx points to the complex input vector\r
- * @param[in] pSrcReal points to the real input vector\r
- * @param[out] pCmplxDst points to the complex output vector\r
- * @param[in] numSamples number of samples in each vector\r
- */\r
- void arm_cmplx_mult_real_q15(\r
- q15_t * pSrcCmplx,\r
- q15_t * pSrcReal,\r
- q15_t * pCmplxDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q31 complex-by-real multiplication\r
- * @param[in] pSrcCmplx points to the complex input vector\r
- * @param[in] pSrcReal points to the real input vector\r
- * @param[out] pCmplxDst points to the complex output vector\r
- * @param[in] numSamples number of samples in each vector\r
- */\r
- void arm_cmplx_mult_real_q31(\r
- q31_t * pSrcCmplx,\r
- q31_t * pSrcReal,\r
- q31_t * pCmplxDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex-by-real multiplication\r
- * @param[in] pSrcCmplx points to the complex input vector\r
- * @param[in] pSrcReal points to the real input vector\r
- * @param[out] pCmplxDst points to the complex output vector\r
- * @param[in] numSamples number of samples in each vector\r
- */\r
- void arm_cmplx_mult_real_f32(\r
- float32_t * pSrcCmplx,\r
- float32_t * pSrcReal,\r
- float32_t * pCmplxDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Minimum value of a Q7 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] result is output pointer\r
- * @param[in] index is the array index of the minimum value in the input buffer.\r
- */\r
- void arm_min_q7(\r
- q7_t * pSrc,\r
- uint32_t blockSize,\r
- q7_t * result,\r
- uint32_t * index);\r
-\r
-\r
- /**\r
- * @brief Minimum value of a Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output pointer\r
- * @param[in] pIndex is the array index of the minimum value in the input buffer.\r
- */\r
- void arm_min_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
- /**\r
- * @brief Minimum value of a Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output pointer\r
- * @param[out] pIndex is the array index of the minimum value in the input buffer.\r
- */\r
- void arm_min_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
- /**\r
- * @brief Minimum value of a floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output pointer\r
- * @param[out] pIndex is the array index of the minimum value in the input buffer.\r
- */\r
- void arm_min_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
-/**\r
- * @brief Maximum value of a Q7 vector.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[in] blockSize length of the input vector\r
- * @param[out] pResult maximum value returned here\r
- * @param[out] pIndex index of maximum value returned here\r
- */\r
- void arm_max_q7(\r
- q7_t * pSrc,\r
- uint32_t blockSize,\r
- q7_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
-/**\r
- * @brief Maximum value of a Q15 vector.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[in] blockSize length of the input vector\r
- * @param[out] pResult maximum value returned here\r
- * @param[out] pIndex index of maximum value returned here\r
- */\r
- void arm_max_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
-/**\r
- * @brief Maximum value of a Q31 vector.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[in] blockSize length of the input vector\r
- * @param[out] pResult maximum value returned here\r
- * @param[out] pIndex index of maximum value returned here\r
- */\r
- void arm_max_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
-/**\r
- * @brief Maximum value of a floating-point vector.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[in] blockSize length of the input vector\r
- * @param[out] pResult maximum value returned here\r
- * @param[out] pIndex index of maximum value returned here\r
- */\r
- void arm_max_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
- /**\r
- * @brief Q15 complex-by-complex multiplication\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- */\r
- void arm_cmplx_mult_cmplx_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- q15_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q31 complex-by-complex multiplication\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- */\r
- void arm_cmplx_mult_cmplx_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- q31_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex-by-complex multiplication\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- */\r
- void arm_cmplx_mult_cmplx_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- float32_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the floating-point vector to Q31 vector.\r
- * @param[in] pSrc points to the floating-point input vector\r
- * @param[out] pDst points to the Q31 output vector\r
- * @param[in] blockSize length of the input vector\r
- */\r
- void arm_float_to_q31(\r
- float32_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the floating-point vector to Q15 vector.\r
- * @param[in] pSrc points to the floating-point input vector\r
- * @param[out] pDst points to the Q15 output vector\r
- * @param[in] blockSize length of the input vector\r
- */\r
- void arm_float_to_q15(\r
- float32_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the floating-point vector to Q7 vector.\r
- * @param[in] pSrc points to the floating-point input vector\r
- * @param[out] pDst points to the Q7 output vector\r
- * @param[in] blockSize length of the input vector\r
- */\r
- void arm_float_to_q7(\r
- float32_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q31 vector to Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q31_to_q15(\r
- q31_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q31 vector to Q7 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q31_to_q7(\r
- q31_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q15 vector to floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q15_to_float(\r
- q15_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q15 vector to Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q15_to_q31(\r
- q15_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q15 vector to Q7 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q15_to_q7(\r
- q15_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @ingroup groupInterpolation\r
- */\r
-\r
- /**\r
- * @defgroup BilinearInterpolate Bilinear Interpolation\r
- *\r
- * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.\r
- * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process\r
- * determines values between the grid points.\r
- * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.\r
- * Bilinear interpolation is often used in image processing to rescale images.\r
- * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.\r
- *\r
- * <b>Algorithm</b>\r
- * \par\r
- * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.\r
- * For floating-point, the instance structure is defined as:\r
- * <pre>\r
- * typedef struct\r
- * {\r
- * uint16_t numRows;\r
- * uint16_t numCols;\r
- * float32_t *pData;\r
- * } arm_bilinear_interp_instance_f32;\r
- * </pre>\r
- *\r
- * \par\r
- * where <code>numRows</code> specifies the number of rows in the table;\r
- * <code>numCols</code> specifies the number of columns in the table;\r
- * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.\r
- * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.\r
- * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.\r
- *\r
- * \par\r
- * Let <code>(x, y)</code> specify the desired interpolation point. Then define:\r
- * <pre>\r
- * XF = floor(x)\r
- * YF = floor(y)\r
- * </pre>\r
- * \par\r
- * The interpolated output point is computed as:\r
- * <pre>\r
- * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\r
- * + f(XF+1, YF) * (x-XF)*(1-(y-YF))\r
- * + f(XF, YF+1) * (1-(x-XF))*(y-YF)\r
- * + f(XF+1, YF+1) * (x-XF)*(y-YF)\r
- * </pre>\r
- * Note that the coordinates (x, y) contain integer and fractional components.\r
- * The integer components specify which portion of the table to use while the\r
- * fractional components control the interpolation processor.\r
- *\r
- * \par\r
- * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.\r
- */\r
-\r
- /**\r
- * @addtogroup BilinearInterpolate\r
- * @{\r
- */\r
-\r
-\r
- /**\r
- *\r
- * @brief Floating-point bilinear interpolation.\r
- * @param[in,out] S points to an instance of the interpolation structure.\r
- * @param[in] X interpolation coordinate.\r
- * @param[in] Y interpolation coordinate.\r
- * @return out interpolated value.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(\r
- const arm_bilinear_interp_instance_f32 * S,\r
- float32_t X,\r
- float32_t Y)\r
- {\r
- float32_t out;\r
- float32_t f00, f01, f10, f11;\r
- float32_t *pData = S->pData;\r
- int32_t xIndex, yIndex, index;\r
- float32_t xdiff, ydiff;\r
- float32_t b1, b2, b3, b4;\r
-\r
- xIndex = (int32_t) X;\r
- yIndex = (int32_t) Y;\r
-\r
- /* Care taken for table outside boundary */\r
- /* Returns zero output when values are outside table boundary */\r
- if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))\r
- {\r
- return (0);\r
- }\r
-\r
- /* Calculation of index for two nearest points in X-direction */\r
- index = (xIndex - 1) + (yIndex - 1) * S->numCols;\r
-\r
-\r
- /* Read two nearest points in X-direction */\r
- f00 = pData[index];\r
- f01 = pData[index + 1];\r
-\r
- /* Calculation of index for two nearest points in Y-direction */\r
- index = (xIndex - 1) + (yIndex) * S->numCols;\r
-\r
-\r
- /* Read two nearest points in Y-direction */\r
- f10 = pData[index];\r
- f11 = pData[index + 1];\r
-\r
- /* Calculation of intermediate values */\r
- b1 = f00;\r
- b2 = f01 - f00;\r
- b3 = f10 - f00;\r
- b4 = f00 - f01 - f10 + f11;\r
-\r
- /* Calculation of fractional part in X */\r
- xdiff = X - xIndex;\r
-\r
- /* Calculation of fractional part in Y */\r
- ydiff = Y - yIndex;\r
-\r
- /* Calculation of bi-linear interpolated output */\r
- out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;\r
-\r
- /* return to application */\r
- return (out);\r
- }\r
-\r
-\r
- /**\r
- *\r
- * @brief Q31 bilinear interpolation.\r
- * @param[in,out] S points to an instance of the interpolation structure.\r
- * @param[in] X interpolation coordinate in 12.20 format.\r
- * @param[in] Y interpolation coordinate in 12.20 format.\r
- * @return out interpolated value.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(\r
- arm_bilinear_interp_instance_q31 * S,\r
- q31_t X,\r
- q31_t Y)\r
- {\r
- q31_t out; /* Temporary output */\r
- q31_t acc = 0; /* output */\r
- q31_t xfract, yfract; /* X, Y fractional parts */\r
- q31_t x1, x2, y1, y2; /* Nearest output values */\r
- int32_t rI, cI; /* Row and column indices */\r
- q31_t *pYData = S->pData; /* pointer to output table values */\r
- uint32_t nCols = S->numCols; /* num of rows */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- rI = ((X & (q31_t)0xFFF00000) >> 20);\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- cI = ((Y & (q31_t)0xFFF00000) >> 20);\r
-\r
- /* Care taken for table outside boundary */\r
- /* Returns zero output when values are outside table boundary */\r
- if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
- {\r
- return (0);\r
- }\r
-\r
- /* 20 bits for the fractional part */\r
- /* shift left xfract by 11 to keep 1.31 format */\r
- xfract = (X & 0x000FFFFF) << 11u;\r
-\r
- /* Read two nearest output values from the index */\r
- x1 = pYData[(rI) + (int32_t)nCols * (cI) ];\r
- x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];\r
-\r
- /* 20 bits for the fractional part */\r
- /* shift left yfract by 11 to keep 1.31 format */\r
- yfract = (Y & 0x000FFFFF) << 11u;\r
-\r
- /* Read two nearest output values from the index */\r
- y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];\r
- y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];\r
-\r
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */\r
- out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));\r
- acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));\r
-\r
- /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */\r
- out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));\r
- acc += ((q31_t) ((q63_t) out * (xfract) >> 32));\r
-\r
- /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */\r
- out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));\r
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
-\r
- /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */\r
- out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));\r
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
-\r
- /* Convert acc to 1.31(q31) format */\r
- return ((q31_t)(acc << 2));\r
- }\r
-\r
-\r
- /**\r
- * @brief Q15 bilinear interpolation.\r
- * @param[in,out] S points to an instance of the interpolation structure.\r
- * @param[in] X interpolation coordinate in 12.20 format.\r
- * @param[in] Y interpolation coordinate in 12.20 format.\r
- * @return out interpolated value.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(\r
- arm_bilinear_interp_instance_q15 * S,\r
- q31_t X,\r
- q31_t Y)\r
- {\r
- q63_t acc = 0; /* output */\r
- q31_t out; /* Temporary output */\r
- q15_t x1, x2, y1, y2; /* Nearest output values */\r
- q31_t xfract, yfract; /* X, Y fractional parts */\r
- int32_t rI, cI; /* Row and column indices */\r
- q15_t *pYData = S->pData; /* pointer to output table values */\r
- uint32_t nCols = S->numCols; /* num of rows */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- rI = ((X & (q31_t)0xFFF00000) >> 20);\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- cI = ((Y & (q31_t)0xFFF00000) >> 20);\r
-\r
- /* Care taken for table outside boundary */\r
- /* Returns zero output when values are outside table boundary */\r
- if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
- {\r
- return (0);\r
- }\r
-\r
- /* 20 bits for the fractional part */\r
- /* xfract should be in 12.20 format */\r
- xfract = (X & 0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];\r
- x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\r
-\r
- /* 20 bits for the fractional part */\r
- /* yfract should be in 12.20 format */\r
- yfract = (Y & 0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];\r
- y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\r
-\r
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */\r
-\r
- /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */\r
- /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */\r
- out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);\r
- acc = ((q63_t) out * (0xFFFFF - yfract));\r
-\r
- /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */\r
- out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);\r
- acc += ((q63_t) out * (xfract));\r
-\r
- /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */\r
- out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);\r
- acc += ((q63_t) out * (yfract));\r
-\r
- /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */\r
- out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);\r
- acc += ((q63_t) out * (yfract));\r
-\r
- /* acc is in 13.51 format and down shift acc by 36 times */\r
- /* Convert out to 1.15 format */\r
- return ((q15_t)(acc >> 36));\r
- }\r
-\r
-\r
- /**\r
- * @brief Q7 bilinear interpolation.\r
- * @param[in,out] S points to an instance of the interpolation structure.\r
- * @param[in] X interpolation coordinate in 12.20 format.\r
- * @param[in] Y interpolation coordinate in 12.20 format.\r
- * @return out interpolated value.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(\r
- arm_bilinear_interp_instance_q7 * S,\r
- q31_t X,\r
- q31_t Y)\r
- {\r
- q63_t acc = 0; /* output */\r
- q31_t out; /* Temporary output */\r
- q31_t xfract, yfract; /* X, Y fractional parts */\r
- q7_t x1, x2, y1, y2; /* Nearest output values */\r
- int32_t rI, cI; /* Row and column indices */\r
- q7_t *pYData = S->pData; /* pointer to output table values */\r
- uint32_t nCols = S->numCols; /* num of rows */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- rI = ((X & (q31_t)0xFFF00000) >> 20);\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- cI = ((Y & (q31_t)0xFFF00000) >> 20);\r
-\r
- /* Care taken for table outside boundary */\r
- /* Returns zero output when values are outside table boundary */\r
- if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
- {\r
- return (0);\r
- }\r
-\r
- /* 20 bits for the fractional part */\r
- /* xfract should be in 12.20 format */\r
- xfract = (X & (q31_t)0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];\r
- x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\r
-\r
- /* 20 bits for the fractional part */\r
- /* yfract should be in 12.20 format */\r
- yfract = (Y & (q31_t)0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];\r
- y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\r
-\r
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */\r
- out = ((x1 * (0xFFFFF - xfract)));\r
- acc = (((q63_t) out * (0xFFFFF - yfract)));\r
-\r
- /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */\r
- out = ((x2 * (0xFFFFF - yfract)));\r
- acc += (((q63_t) out * (xfract)));\r
-\r
- /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */\r
- out = ((y1 * (0xFFFFF - xfract)));\r
- acc += (((q63_t) out * (yfract)));\r
-\r
- /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */\r
- out = ((y2 * (yfract)));\r
- acc += (((q63_t) out * (xfract)));\r
-\r
- /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */\r
- return ((q7_t)(acc >> 40));\r
- }\r
-\r
- /**\r
- * @} end of BilinearInterpolate group\r
- */\r
-\r
-\r
-/* SMMLAR */\r
-#define multAcc_32x32_keep32_R(a, x, y) \\r
- a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)\r
-\r
-/* SMMLSR */\r
-#define multSub_32x32_keep32_R(a, x, y) \\r
- a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)\r
-\r
-/* SMMULR */\r
-#define mult_32x32_keep32_R(a, x, y) \\r
- a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)\r
-\r
-/* SMMLA */\r
-#define multAcc_32x32_keep32(a, x, y) \\r
- a += (q31_t) (((q63_t) x * y) >> 32)\r
-\r
-/* SMMLS */\r
-#define multSub_32x32_keep32(a, x, y) \\r
- a -= (q31_t) (((q63_t) x * y) >> 32)\r
-\r
-/* SMMUL */\r
-#define mult_32x32_keep32(a, x, y) \\r
- a = (q31_t) (((q63_t) x * y ) >> 32)\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- /* Enter low optimization region - place directly above function definition */\r
- #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\r
- #define LOW_OPTIMIZATION_ENTER \\r
- _Pragma ("push") \\r
- _Pragma ("O1")\r
- #else\r
- #define LOW_OPTIMIZATION_ENTER\r
- #endif\r
-\r
- /* Exit low optimization region - place directly after end of function definition */\r
- #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )\r
- #define LOW_OPTIMIZATION_EXIT \\r
- _Pragma ("pop")\r
- #else\r
- #define LOW_OPTIMIZATION_EXIT\r
- #endif\r
-\r
- /* Enter low optimization region - place directly above function definition */\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
-\r
- /* Exit low optimization region - place directly after end of function definition */\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
- #define LOW_OPTIMIZATION_ENTER\r
- #define LOW_OPTIMIZATION_EXIT\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined ( __GNUC__ )\r
- #define LOW_OPTIMIZATION_ENTER \\r
- __attribute__(( optimize("-O1") ))\r
- #define LOW_OPTIMIZATION_EXIT\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined ( __ICCARM__ )\r
- /* Enter low optimization region - place directly above function definition */\r
- #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )\r
- #define LOW_OPTIMIZATION_ENTER \\r
- _Pragma ("optimize=low")\r
- #else\r
- #define LOW_OPTIMIZATION_ENTER\r
- #endif\r
-\r
- /* Exit low optimization region - place directly after end of function definition */\r
- #define LOW_OPTIMIZATION_EXIT\r
-\r
- /* Enter low optimization region - place directly above function definition */\r
- #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \\r
- _Pragma ("optimize=low")\r
- #else\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
- #endif\r
-\r
- /* Exit low optimization region - place directly after end of function definition */\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined ( __TI_ARM__ )\r
- #define LOW_OPTIMIZATION_ENTER\r
- #define LOW_OPTIMIZATION_EXIT\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined ( __CSMC__ )\r
- #define LOW_OPTIMIZATION_ENTER\r
- #define LOW_OPTIMIZATION_EXIT\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined ( __TASKING__ )\r
- #define LOW_OPTIMIZATION_ENTER\r
- #define LOW_OPTIMIZATION_EXIT\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#endif\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-/* Compiler specific diagnostic adjustment */\r
-#if defined ( __CC_ARM )\r
-\r
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
-\r
-#elif defined ( __GNUC__ )\r
-#pragma GCC diagnostic pop\r
-\r
-#elif defined ( __ICCARM__ )\r
-\r
-#elif defined ( __TI_ARM__ )\r
-\r
-#elif defined ( __CSMC__ )\r
-\r
-#elif defined ( __TASKING__ )\r
-\r
-#else\r
- #error Unknown compiler\r
-#endif\r
-\r
-#endif /* _ARM_MATH_H */\r
-\r
-/**\r
- *\r
- * End of file.\r
- */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm0.h\r
- * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File\r
- * @version V5.0.2\r
- * @date 19. April 2017\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM0_H_GENERIC\r
-#define __CORE_CM0_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
- \ingroup Cortex_M0\r
- @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
- \r
-/* CMSIS CM0 definitions */\r
-#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \\r
- __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0U) /*!< Cortex-M Core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
- This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED 0U\r
-\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #if defined __ARM_PCS_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
- #if defined __TI_VFP_SUPPORT__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __CSMC__ )\r
- #if ( __CSMC__ & 0x400U)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM0_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM0_H_DEPENDANT\r
-#define __CORE_CM0_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __CM0_REV\r
- #define __CM0_REV 0x0000U\r
- #warning "__CM0_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 2U\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0U\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
-#define __OM volatile /*! Defines 'write only' structure member permissions */\r
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex_M0 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos 31U /*!< APSR: N Position */\r
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos 29U /*!< APSR: C Position */\r
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos 28U /*!< APSR: V Position */\r
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
-\r
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
-\r
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:1; /*!< bit: 0 Reserved */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[31U];\r
- __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[31U];\r
- __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[31U];\r
- __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[31U];\r
- uint32_t RESERVED4[64U];\r
- __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
-} NVIC_Type;\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- uint32_t RESERVED0;\r
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- uint32_t RESERVED1;\r
- __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
- Therefore they are not covered by the Cortex-M0 header file.\r
- @{\r
- */\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_bitfield Core register bit field macros\r
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
- @{\r
- */\r
-\r
-/**\r
- \brief Mask and shift a bit field value for use in a register bit range.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
- \return Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
- \brief Mask and shift a register value to extract a bit filed value.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
- \return Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
- #endif\r
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
-/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */\r
-/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */\r
- #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
- #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
-/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */\r
- #define NVIC_SetPriority __NVIC_SetPriority\r
- #define NVIC_GetPriority __NVIC_GetPriority\r
- #define NVIC_SystemReset __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
- #endif\r
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
- #define NVIC_SetVector __NVIC_SetVector\r
- #define NVIC_GetVector __NVIC_GetVector\r
-#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET 16\r
-\r
-\r
-/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
-/* The following MACROS handle generation of the register offset and byte masks */\r
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
-\r
-\r
-/**\r
- \brief Enable Interrupt\r
- \details Enables a device specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Enable status\r
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt is not enabled.\r
- \return 1 Interrupt is enabled.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Disable Interrupt\r
- \details Disables a device specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- __DSB();\r
- __ISB();\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Pending Interrupt\r
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Pending Interrupt\r
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Clear Pending Interrupt\r
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Priority\r
- \details Sets the priority of a device specific interrupt or a processor exception.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- \note The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
- }\r
- else\r
- {\r
- SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Priority\r
- \details Reads the priority of a device specific interrupt or a processor exception.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority.\r
- Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
- else\r
- {\r
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Vector\r
- \details Sets an interrupt vector in SRAM based interrupt vector table.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- Address 0 must be mapped to SRAM.\r
- \param [in] IRQn Interrupt number\r
- \param [in] vector Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
- uint32_t *vectors = (uint32_t *)0x0U;\r
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Vector\r
- \details Reads an interrupt vector from interrupt vector table.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \return Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
- uint32_t *vectors = (uint32_t *)0x0U;\r
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-}\r
-\r
-\r
-/**\r
- \brief System Reset\r
- \details Initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- SCB_AIRCR_SYSRESETREQ_Msk);\r
- __DSB(); /* Ensure completion of memory access */\r
-\r
- for(;;) /* wait until reset */\r
- {\r
- __NOP();\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-/* ########################## FPU functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
- \brief Function that provides FPU type.\r
- @{\r
- */\r
-\r
-/**\r
- \brief get FPU type\r
- \details returns the FPU type\r
- \returns\r
- - \b 0: No FPU\r
- - \b 1: Single precision FPU\r
- - \b 2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
- return 0U; /* No FPU */\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
- \brief System Tick Configuration\r
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
- \param [in] ticks Number of ticks between two interrupts.\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
- {\r
- return (1UL); /* Reload value impossible */\r
- }\r
-\r
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0UL); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM0_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm0plus.h\r
- * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File\r
- * @version V5.0.2\r
- * @date 19. April 2017\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM0PLUS_H_GENERIC\r
-#define __CORE_CM0PLUS_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
- \ingroup Cortex-M0+\r
- @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
- \r
-/* CMSIS CM0+ definitions */\r
-#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
-#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \\r
- __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0U) /*!< Cortex-M Core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
- This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED 0U\r
-\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #if defined __ARM_PCS_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
- #if defined __TI_VFP_SUPPORT__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __CSMC__ )\r
- #if ( __CSMC__ & 0x400U)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM0PLUS_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM0PLUS_H_DEPENDANT\r
-#define __CORE_CM0PLUS_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __CM0PLUS_REV\r
- #define __CM0PLUS_REV 0x0000U\r
- #warning "__CM0PLUS_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0U\r
- #warning "__MPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __VTOR_PRESENT\r
- #define __VTOR_PRESENT 0U\r
- #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 2U\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0U\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
-#define __OM volatile /*! Defines 'write only' structure member permissions */\r
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex-M0+ */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- - Core MPU Register\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos 31U /*!< APSR: N Position */\r
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos 29U /*!< APSR: C Position */\r
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos 28U /*!< APSR: V Position */\r
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
-\r
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
-\r
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[31U];\r
- __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[31U];\r
- __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[31U];\r
- __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[31U];\r
- uint32_t RESERVED4[64U];\r
- __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
-} NVIC_Type;\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
-#else\r
- uint32_t RESERVED0;\r
-#endif\r
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- uint32_t RESERVED1;\r
- __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-#endif\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
- \brief Type definitions for the Memory Protection Unit (MPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
- Therefore they are not covered by the Cortex-M0+ header file.\r
- @{\r
- */\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_bitfield Core register bit field macros\r
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
- @{\r
- */\r
-\r
-/**\r
- \brief Mask and shift a bit field value for use in a register bit range.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
- \return Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
- \brief Mask and shift a register value to extract a bit filed value.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
- \return Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
- #endif\r
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
-/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */\r
-/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */\r
- #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
- #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
-/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */\r
- #define NVIC_SetPriority __NVIC_SetPriority\r
- #define NVIC_GetPriority __NVIC_GetPriority\r
- #define NVIC_SystemReset __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
- #endif\r
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
- #define NVIC_SetVector __NVIC_SetVector\r
- #define NVIC_GetVector __NVIC_GetVector\r
-#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET 16\r
-\r
-\r
-/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
-/* The following MACROS handle generation of the register offset and byte masks */\r
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
-\r
-\r
-/**\r
- \brief Enable Interrupt\r
- \details Enables a device specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Enable status\r
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt is not enabled.\r
- \return 1 Interrupt is enabled.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Disable Interrupt\r
- \details Disables a device specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- __DSB();\r
- __ISB();\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Pending Interrupt\r
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Pending Interrupt\r
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Clear Pending Interrupt\r
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Priority\r
- \details Sets the priority of a device specific interrupt or a processor exception.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- \note The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
- }\r
- else\r
- {\r
- SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Priority\r
- \details Reads the priority of a device specific interrupt or a processor exception.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority.\r
- Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
- else\r
- {\r
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Vector\r
- \details Sets an interrupt vector in SRAM based interrupt vector table.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- VTOR must been relocated to SRAM before.\r
- If VTOR is not present address 0 must be mapped to SRAM.\r
- \param [in] IRQn Interrupt number\r
- \param [in] vector Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
- uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-#else\r
- uint32_t *vectors = (uint32_t *)0x0U;\r
-#endif\r
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Vector\r
- \details Reads an interrupt vector from interrupt vector table.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \return Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
- uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-#else\r
- uint32_t *vectors = (uint32_t *)0x0U;\r
-#endif\r
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-\r
-}\r
-\r
-\r
-/**\r
- \brief System Reset\r
- \details Initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- SCB_AIRCR_SYSRESETREQ_Msk);\r
- __DSB(); /* Ensure completion of memory access */\r
-\r
- for(;;) /* wait until reset */\r
- {\r
- __NOP();\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-/* ########################## MPU functions #################################### */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-\r
-#include "mpu_armv7.h"\r
-\r
-#endif\r
-\r
-/* ########################## FPU functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
- \brief Function that provides FPU type.\r
- @{\r
- */\r
-\r
-/**\r
- \brief get FPU type\r
- \details returns the FPU type\r
- \returns\r
- - \b 0: No FPU\r
- - \b 1: Single precision FPU\r
- - \b 2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
- return 0U; /* No FPU */\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
- \brief System Tick Configuration\r
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
- \param [in] ticks Number of ticks between two interrupts.\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
- {\r
- return (1UL); /* Reload value impossible */\r
- }\r
-\r
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0UL); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm3.h\r
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
- * @version V5.0.2\r
- * @date 19. April 2017\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM3_H_GENERIC\r
-#define __CORE_CM3_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
- \ingroup Cortex_M3\r
- @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
- \r
-/* CMSIS CM3 definitions */\r
-#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \\r
- __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (3U) /*!< Cortex-M Core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
- This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED 0U\r
-\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #if defined __ARM_PCS_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
- #if defined __TI_VFP_SUPPORT__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __CSMC__ )\r
- #if ( __CSMC__ & 0x400U)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM3_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM3_H_DEPENDANT\r
-#define __CORE_CM3_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __CM3_REV\r
- #define __CM3_REV 0x0200U\r
- #warning "__CM3_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0U\r
- #warning "__MPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 3U\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0U\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
-#define __OM volatile /*! Defines 'write only' structure member permissions */\r
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex_M3 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- - Core Debug Register\r
- - Core MPU Register\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos 31U /*!< APSR: N Position */\r
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos 29U /*!< APSR: C Position */\r
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos 28U /*!< APSR: V Position */\r
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
-\r
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
- uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
- uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */\r
- uint32_t T:1; /*!< bit: 24 Thumb bit */\r
- uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
-\r
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
-\r
-#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
-#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
-\r
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
-\r
-#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
-#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
-\r
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24U];\r
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24U];\r
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24U];\r
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24U];\r
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
- uint32_t RESERVED4[56U];\r
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644U];\r
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
- __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
- __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
- __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
- __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
- __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
- uint32_t RESERVED0[5U];\r
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */\r
-#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */\r
-#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
-\r
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-#else\r
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-#endif\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Register Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
-\r
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
-\r
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
-\r
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
-\r
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
-\r
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
-\r
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
-\r
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
-\r
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
-\r
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
-\r
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
-\r
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
-\r
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
-\r
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
-\r
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
-\r
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
-\r
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
-\r
-/* SCB Hard Fault Status Register Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
- \brief Type definitions for the System Control and ID Register not in the SCB\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1U];\r
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
-#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)\r
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
-#else\r
- uint32_t RESERVED1[1U];\r
-#endif\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/* Auxiliary Control Register Definitions */\r
-\r
-#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
-\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
-\r
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
- __OM union\r
- {\r
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864U];\r
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
- uint32_t RESERVED1[15U];\r
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15U];\r
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
- uint32_t RESERVED3[29U];\r
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43U];\r
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
- uint32_t RESERVED5[6U];\r
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
- \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
- uint32_t RESERVED0[1U];\r
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
- uint32_t RESERVED1[1U];\r
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
- uint32_t RESERVED2[1U];\r
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
-\r
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
-\r
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
-\r
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
-\r
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
-\r
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
-\r
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
-\r
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
-\r
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
-\r
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
-\r
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
-\r
-/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
-\r
-/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
-\r
-/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
-\r
-/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
-\r
-/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
-\r
-/* DWT Comparator Mask Register Definitions */\r
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
-\r
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
-\r
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
-\r
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
-\r
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
- \brief Type definitions for the Trace Port Interface (TPI)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
- uint32_t RESERVED0[2U];\r
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
- uint32_t RESERVED1[55U];\r
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
- uint32_t RESERVED2[131U];\r
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
- uint32_t RESERVED3[759U];\r
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
- uint32_t RESERVED4[1U];\r
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
- uint32_t RESERVED5[39U];\r
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
- uint32_t RESERVED7[8U];\r
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
-\r
-/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
-\r
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
-\r
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
-\r
-/* TPI ITATBCTR2 Register Definitions */\r
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
-\r
-/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
-\r
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
-\r
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
-\r
-/* TPI ITATBCTR0 Register Definitions */\r
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
-\r
-/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
-\r
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
-\r
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
- \brief Type definitions for the Memory Protection Unit (MPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Type definitions for the Core Debug Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register Definitions */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register Definitions */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register Definitions */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_bitfield Core register bit field macros\r
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
- @{\r
- */\r
-\r
-/**\r
- \brief Mask and shift a bit field value for use in a register bit range.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
- \return Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
- \brief Mask and shift a register value to extract a bit filed value.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
- \return Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Debug Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
- #endif\r
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
- #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
- #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
- #define NVIC_GetActive __NVIC_GetActive\r
- #define NVIC_SetPriority __NVIC_SetPriority\r
- #define NVIC_GetPriority __NVIC_GetPriority\r
- #define NVIC_SystemReset __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
- #endif\r
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
- #define NVIC_SetVector __NVIC_SetVector\r
- #define NVIC_GetVector __NVIC_GetVector\r
-#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET 16\r
-\r
-\r
-\r
-/**\r
- \brief Set Priority Grouping\r
- \details Sets the priority grouping field using the required unlock sequence.\r
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
- Only values from 0..7 are used.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Priority grouping field.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
-\r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Priority Grouping\r
- \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
- \brief Enable Interrupt\r
- \details Enables a device specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Enable status\r
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt is not enabled.\r
- \return 1 Interrupt is enabled.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Disable Interrupt\r
- \details Disables a device specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- __DSB();\r
- __ISB();\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Pending Interrupt\r
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Pending Interrupt\r
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Clear Pending Interrupt\r
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Active Interrupt\r
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt status is not active.\r
- \return 1 Interrupt status is active.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Priority\r
- \details Sets the priority of a device specific interrupt or a processor exception.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- \note The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
- else\r
- {\r
- SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Priority\r
- \details Reads the priority of a device specific interrupt or a processor exception.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority.\r
- Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
- else\r
- {\r
- return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Encode Priority\r
- \details Encodes the priority for an interrupt with the given priority group,\r
- preemptive priority value, and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Used priority group.\r
- \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
- \param [in] SubPriority Subpriority value (starting from 0).\r
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- return (\r
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
- );\r
-}\r
-\r
-\r
-/**\r
- \brief Decode Priority\r
- \details Decodes an interrupt priority value with a given priority group to\r
- preemptive priority value and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
- \param [in] PriorityGroup Used priority group.\r
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
- \param [out] pSubPriority Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Vector\r
- \details Sets an interrupt vector in SRAM based interrupt vector table.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- VTOR must been relocated to SRAM before.\r
- \param [in] IRQn Interrupt number\r
- \param [in] vector Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
- uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Vector\r
- \details Reads an interrupt vector from interrupt vector table.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \return Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
- uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-}\r
-\r
-\r
-/**\r
- \brief System Reset\r
- \details Initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
-\r
- for(;;) /* wait until reset */\r
- {\r
- __NOP();\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-/* ########################## MPU functions #################################### */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-\r
-#include "mpu_armv7.h"\r
-\r
-#endif\r
-\r
-/* ########################## FPU functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
- \brief Function that provides FPU type.\r
- @{\r
- */\r
-\r
-/**\r
- \brief get FPU type\r
- \details returns the FPU type\r
- \returns\r
- - \b 0: No FPU\r
- - \b 1: Single precision FPU\r
- - \b 2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
- return 0U; /* No FPU */\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
- \brief System Tick Configuration\r
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
- \param [in] ticks Number of ticks between two interrupts.\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
- {\r
- return (1UL); /* Reload value impossible */\r
- }\r
-\r
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0UL); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_core_DebugFunctions ITM Functions\r
- \brief Functions that access the ITM debug interface.\r
- @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
-#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/**\r
- \brief ITM Send Character\r
- \details Transmits a character via the ITM channel 0, and\r
- \li Just returns when no debugger is connected that has booked the output.\r
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
- \param [in] ch Character to transmit.\r
- \returns Character to transmit.\r
- */\r
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
- {\r
- while (ITM->PORT[0U].u32 == 0UL)\r
- {\r
- __NOP();\r
- }\r
- ITM->PORT[0U].u8 = (uint8_t)ch;\r
- }\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Receive Character\r
- \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
- \return Received character.\r
- \return -1 No character pending.\r
- */\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
-{\r
- int32_t ch = -1; /* no character available */\r
-\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
- {\r
- ch = ITM_RxBuffer;\r
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
- }\r
-\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Check Character\r
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
- \return 0 No character available.\r
- \return 1 Character available.\r
- */\r
-__STATIC_INLINE int32_t ITM_CheckChar (void)\r
-{\r
-\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
- {\r
- return (0); /* no character available */\r
- }\r
- else\r
- {\r
- return (1); /* character available */\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM3_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm4.h\r
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
- * @version V5.0.2\r
- * @date 19. April 2017\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM4_H_GENERIC\r
-#define __CORE_CM4_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
- \ingroup Cortex_M4\r
- @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
- \r
-/* CMSIS CM4 definitions */\r
-#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
-#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\r
- __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (4U) /*!< Cortex-M Core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
-*/\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #if defined __ARM_PCS_VFP\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
- #if defined __TI_VFP_SUPPORT__\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __CSMC__ )\r
- #if ( __CSMC__ & 0x400U)\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM4_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM4_H_DEPENDANT\r
-#define __CORE_CM4_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __CM4_REV\r
- #define __CM4_REV 0x0000U\r
- #warning "__CM4_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __FPU_PRESENT\r
- #define __FPU_PRESENT 0U\r
- #warning "__FPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0U\r
- #warning "__MPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 3U\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0U\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
-#define __OM volatile /*! Defines 'write only' structure member permissions */\r
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex_M4 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- - Core Debug Register\r
- - Core MPU Register\r
- - Core FPU Register\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos 31U /*!< APSR: N Position */\r
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos 29U /*!< APSR: C Position */\r
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos 28U /*!< APSR: V Position */\r
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
-\r
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
-\r
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
- uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
- uint32_t T:1; /*!< bit: 24 Thumb bit */\r
- uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
-\r
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
-\r
-#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
-#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
-\r
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
-\r
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
-\r
-#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
-#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
-\r
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
-\r
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24U];\r
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24U];\r
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24U];\r
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24U];\r
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
- uint32_t RESERVED4[56U];\r
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644U];\r
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
- __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
- __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
- __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
- __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
- __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
- uint32_t RESERVED0[5U];\r
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Register Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
-\r
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
-#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
-\r
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
-\r
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
-\r
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
-\r
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
-\r
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
-\r
-#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
-#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
-\r
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
-\r
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
-\r
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
-\r
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
-\r
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
-\r
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
-\r
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
-\r
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
-\r
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
-\r
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
-\r
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
-\r
-/* SCB Hard Fault Status Register Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
- \brief Type definitions for the System Control and ID Register not in the SCB\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1U];\r
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/* Auxiliary Control Register Definitions */\r
-#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */\r
-#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */\r
-\r
-#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */\r
-#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */\r
-\r
-#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
-\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
-\r
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
- __OM union\r
- {\r
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864U];\r
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
- uint32_t RESERVED1[15U];\r
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15U];\r
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
- uint32_t RESERVED3[29U];\r
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43U];\r
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
- uint32_t RESERVED5[6U];\r
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
- \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
- uint32_t RESERVED0[1U];\r
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
- uint32_t RESERVED1[1U];\r
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
- uint32_t RESERVED2[1U];\r
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
-\r
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
-\r
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
-\r
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
-\r
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
-\r
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
-\r
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
-\r
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
-\r
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
-\r
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
-\r
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
-\r
-/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
-\r
-/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
-\r
-/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
-\r
-/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
-\r
-/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
-\r
-/* DWT Comparator Mask Register Definitions */\r
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
-\r
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
-\r
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
-\r
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
-\r
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
- \brief Type definitions for the Trace Port Interface (TPI)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
- uint32_t RESERVED0[2U];\r
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
- uint32_t RESERVED1[55U];\r
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
- uint32_t RESERVED2[131U];\r
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
- uint32_t RESERVED3[759U];\r
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
- uint32_t RESERVED4[1U];\r
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
- uint32_t RESERVED5[39U];\r
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
- uint32_t RESERVED7[8U];\r
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
-\r
-/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
-\r
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
-\r
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
-\r
-/* TPI ITATBCTR2 Register Definitions */\r
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
-\r
-/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
-\r
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
-\r
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
-\r
-/* TPI ITATBCTR0 Register Definitions */\r
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
-\r
-/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
-\r
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
-\r
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
- \brief Type definitions for the Memory Protection Unit (MPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
- \brief Type definitions for the Floating Point Unit (FPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Floating Point Unit (FPU).\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1U];\r
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
-} FPU_Type;\r
-\r
-/* Floating-Point Context Control Register Definitions */\r
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
-\r
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
-\r
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
-\r
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
-\r
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
-\r
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
-\r
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
-\r
-/* Floating-Point Context Address Register Definitions */\r
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
-\r
-/* Floating-Point Default Status Control Register Definitions */\r
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
-\r
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
-\r
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
-\r
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
-\r
-/* Media and FP Feature Register 0 Definitions */\r
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
-\r
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
-\r
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
-\r
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
-\r
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
-\r
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
-\r
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
-\r
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
-\r
-/* Media and FP Feature Register 1 Definitions */\r
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
-\r
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
-\r
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
-\r
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
-\r
-/*@} end of group CMSIS_FPU */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Type definitions for the Core Debug Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register Definitions */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register Definitions */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register Definitions */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_bitfield Core register bit field macros\r
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
- @{\r
- */\r
-\r
-/**\r
- \brief Mask and shift a bit field value for use in a register bit range.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
- \return Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
- \brief Mask and shift a register value to extract a bit filed value.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
- \return Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
-#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Debug Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
- #endif\r
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
- #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
- #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
- #define NVIC_GetActive __NVIC_GetActive\r
- #define NVIC_SetPriority __NVIC_SetPriority\r
- #define NVIC_GetPriority __NVIC_GetPriority\r
- #define NVIC_SystemReset __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
- #endif\r
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
- #define NVIC_SetVector __NVIC_SetVector\r
- #define NVIC_GetVector __NVIC_GetVector\r
-#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET 16\r
-\r
-\r
-\r
-/**\r
- \brief Set Priority Grouping\r
- \details Sets the priority grouping field using the required unlock sequence.\r
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
- Only values from 0..7 are used.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Priority grouping field.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
-\r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Priority Grouping\r
- \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
- \brief Enable Interrupt\r
- \details Enables a device specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Enable status\r
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt is not enabled.\r
- \return 1 Interrupt is enabled.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Disable Interrupt\r
- \details Disables a device specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- __DSB();\r
- __ISB();\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Pending Interrupt\r
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Pending Interrupt\r
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Clear Pending Interrupt\r
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Active Interrupt\r
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt status is not active.\r
- \return 1 Interrupt status is active.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Priority\r
- \details Sets the priority of a device specific interrupt or a processor exception.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- \note The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
- else\r
- {\r
- SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Priority\r
- \details Reads the priority of a device specific interrupt or a processor exception.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority.\r
- Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
- else\r
- {\r
- return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Encode Priority\r
- \details Encodes the priority for an interrupt with the given priority group,\r
- preemptive priority value, and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Used priority group.\r
- \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
- \param [in] SubPriority Subpriority value (starting from 0).\r
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- return (\r
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
- );\r
-}\r
-\r
-\r
-/**\r
- \brief Decode Priority\r
- \details Decodes an interrupt priority value with a given priority group to\r
- preemptive priority value and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
- \param [in] PriorityGroup Used priority group.\r
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
- \param [out] pSubPriority Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Vector\r
- \details Sets an interrupt vector in SRAM based interrupt vector table.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- VTOR must been relocated to SRAM before.\r
- \param [in] IRQn Interrupt number\r
- \param [in] vector Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
- uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Vector\r
- \details Reads an interrupt vector from interrupt vector table.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \return Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
- uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-}\r
-\r
-\r
-/**\r
- \brief System Reset\r
- \details Initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
-\r
- for(;;) /* wait until reset */\r
- {\r
- __NOP();\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-/* ########################## MPU functions #################################### */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-\r
-#include "mpu_armv7.h"\r
-\r
-#endif\r
-\r
-\r
-/* ########################## FPU functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
- \brief Function that provides FPU type.\r
- @{\r
- */\r
-\r
-/**\r
- \brief get FPU type\r
- \details returns the FPU type\r
- \returns\r
- - \b 0: No FPU\r
- - \b 1: Single precision FPU\r
- - \b 2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
- uint32_t mvfr0;\r
-\r
- mvfr0 = FPU->MVFR0;\r
- if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
- {\r
- return 1U; /* Single precision FPU */\r
- }\r
- else\r
- {\r
- return 0U; /* No FPU */\r
- }\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
- \brief System Tick Configuration\r
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
- \param [in] ticks Number of ticks between two interrupts.\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
- {\r
- return (1UL); /* Reload value impossible */\r
- }\r
-\r
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0UL); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_core_DebugFunctions ITM Functions\r
- \brief Functions that access the ITM debug interface.\r
- @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
-#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/**\r
- \brief ITM Send Character\r
- \details Transmits a character via the ITM channel 0, and\r
- \li Just returns when no debugger is connected that has booked the output.\r
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
- \param [in] ch Character to transmit.\r
- \returns Character to transmit.\r
- */\r
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
- {\r
- while (ITM->PORT[0U].u32 == 0UL)\r
- {\r
- __NOP();\r
- }\r
- ITM->PORT[0U].u8 = (uint8_t)ch;\r
- }\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Receive Character\r
- \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
- \return Received character.\r
- \return -1 No character pending.\r
- */\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
-{\r
- int32_t ch = -1; /* no character available */\r
-\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
- {\r
- ch = ITM_RxBuffer;\r
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
- }\r
-\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Check Character\r
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
- \return 0 No character available.\r
- \return 1 Character available.\r
- */\r
-__STATIC_INLINE int32_t ITM_CheckChar (void)\r
-{\r
-\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
- {\r
- return (0); /* no character available */\r
- }\r
- else\r
- {\r
- return (1); /* character available */\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM4_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm7.h\r
- * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File\r
- * @version V5.0.2\r
- * @date 19. April 2017\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM7_H_GENERIC\r
-#define __CORE_CM7_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
- \ingroup Cortex_M7\r
- @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
-\r
-/* CMSIS CM7 definitions */\r
-#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
-#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \\r
- __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (7U) /*!< Cortex-M Core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
-*/\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #if defined __ARM_PCS_VFP\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
- #if defined __TI_VFP_SUPPORT__\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __CSMC__ )\r
- #if ( __CSMC__ & 0x400U)\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM7_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM7_H_DEPENDANT\r
-#define __CORE_CM7_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __CM7_REV\r
- #define __CM7_REV 0x0000U\r
- #warning "__CM7_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __FPU_PRESENT\r
- #define __FPU_PRESENT 0U\r
- #warning "__FPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0U\r
- #warning "__MPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __ICACHE_PRESENT\r
- #define __ICACHE_PRESENT 0U\r
- #warning "__ICACHE_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __DCACHE_PRESENT\r
- #define __DCACHE_PRESENT 0U\r
- #warning "__DCACHE_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __DTCM_PRESENT\r
- #define __DTCM_PRESENT 0U\r
- #warning "__DTCM_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 3U\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0U\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
-#define __OM volatile /*! Defines 'write only' structure member permissions */\r
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex_M7 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- - Core Debug Register\r
- - Core MPU Register\r
- - Core FPU Register\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos 31U /*!< APSR: N Position */\r
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos 29U /*!< APSR: C Position */\r
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos 28U /*!< APSR: V Position */\r
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
-\r
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
-\r
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
- uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
- uint32_t T:1; /*!< bit: 24 Thumb bit */\r
- uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
-\r
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
-\r
-#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
-#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
-\r
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
-\r
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
-\r
-#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
-#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
-\r
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
-\r
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24U];\r
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24U];\r
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24U];\r
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24U];\r
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
- uint32_t RESERVED4[56U];\r
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644U];\r
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
- __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
- __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
- __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
- __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
- __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
- uint32_t RESERVED0[1U];\r
- __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
- __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
- __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
- __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
- uint32_t RESERVED3[93U];\r
- __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
- uint32_t RESERVED4[15U];\r
- __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
- __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
- __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */\r
- uint32_t RESERVED5[1U];\r
- __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
- uint32_t RESERVED6[1U];\r
- __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
- __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
- __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
- __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
- __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
- __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
- __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
- __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
- uint32_t RESERVED7[6U];\r
- __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
- __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
- __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
- __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
- __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
- uint32_t RESERVED8[1U];\r
- __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */\r
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */\r
-\r
-#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */\r
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */\r
-\r
-#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */\r
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */\r
-\r
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Register Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
-\r
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
-#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
-\r
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
-\r
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
-\r
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
-\r
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
-\r
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
-\r
-#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
-#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
-\r
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
-\r
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
-\r
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
-\r
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
-\r
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
-\r
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
-\r
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
-\r
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
-\r
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
-\r
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
-\r
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
-\r
-/* SCB Hard Fault Status Register Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
-\r
-/* SCB Cache Level ID Register Definitions */\r
-#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */\r
-#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
-\r
-#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */\r
-#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */\r
-\r
-/* SCB Cache Type Register Definitions */\r
-#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */\r
-#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
-\r
-#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */\r
-#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
-\r
-#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */\r
-#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
-\r
-#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */\r
-#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
-\r
-#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */\r
-#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */\r
-\r
-/* SCB Cache Size ID Register Definitions */\r
-#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */\r
-#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
-\r
-#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */\r
-#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
-\r
-#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */\r
-#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
-\r
-#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */\r
-#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
-\r
-#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */\r
-#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
-\r
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */\r
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
-\r
-#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */\r
-#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */\r
-\r
-/* SCB Cache Size Selection Register Definitions */\r
-#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */\r
-#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
-\r
-#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */\r
-#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */\r
-\r
-/* SCB Software Triggered Interrupt Register Definitions */\r
-#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */\r
-#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */\r
-\r
-/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
-#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */\r
-#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */\r
-\r
-#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */\r
-#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */\r
-\r
-/* SCB D-Cache Clean by Set-way Register Definitions */\r
-#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */\r
-#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */\r
-\r
-#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */\r
-#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */\r
-\r
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
-#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */\r
-#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */\r
-\r
-#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */\r
-#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */\r
-\r
-/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
-#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */\r
-#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
-\r
-#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */\r
-#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
-\r
-#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */\r
-#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
-\r
-#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */\r
-#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */\r
-\r
-/* Data Tightly-Coupled Memory Control Register Definitions */\r
-#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */\r
-#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
-\r
-#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */\r
-#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
-\r
-#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */\r
-#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
-\r
-#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */\r
-#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */\r
-\r
-/* AHBP Control Register Definitions */\r
-#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */\r
-#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
-\r
-#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */\r
-#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */\r
-\r
-/* L1 Cache Control Register Definitions */\r
-#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */\r
-#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
-\r
-#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */\r
-#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
-\r
-#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */\r
-#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */\r
-\r
-/* AHBS Control Register Definitions */\r
-#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */\r
-#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
-\r
-#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */\r
-#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
-\r
-#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/\r
-#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */\r
-\r
-/* Auxiliary Bus Fault Status Register Definitions */\r
-#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/\r
-#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
-\r
-#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/\r
-#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
-\r
-#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/\r
-#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
-\r
-#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/\r
-#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
-\r
-#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/\r
-#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
-\r
-#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/\r
-#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
- \brief Type definitions for the System Control and ID Register not in the SCB\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1U];\r
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/* Auxiliary Control Register Definitions */\r
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */\r
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */\r
-\r
-#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */\r
-#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */\r
-\r
-#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */\r
-#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */\r
-\r
-#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
-\r
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
- __OM union\r
- {\r
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864U];\r
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
- uint32_t RESERVED1[15U];\r
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15U];\r
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
- uint32_t RESERVED3[29U];\r
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43U];\r
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
- uint32_t RESERVED5[6U];\r
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
- \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
- uint32_t RESERVED0[1U];\r
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
- uint32_t RESERVED1[1U];\r
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
- uint32_t RESERVED2[1U];\r
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
- uint32_t RESERVED3[981U];\r
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */\r
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
-\r
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
-\r
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
-\r
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
-\r
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
-\r
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
-\r
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
-\r
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
-\r
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
-\r
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
-\r
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
-\r
-/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
-\r
-/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
-\r
-/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
-\r
-/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
-\r
-/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
-\r
-/* DWT Comparator Mask Register Definitions */\r
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
-\r
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
-\r
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
-\r
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
-\r
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
- \brief Type definitions for the Trace Port Interface (TPI)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
- uint32_t RESERVED0[2U];\r
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
- uint32_t RESERVED1[55U];\r
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
- uint32_t RESERVED2[131U];\r
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
- uint32_t RESERVED3[759U];\r
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
- uint32_t RESERVED4[1U];\r
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
- uint32_t RESERVED5[39U];\r
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
- uint32_t RESERVED7[8U];\r
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
-\r
-/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
-\r
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
-\r
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
-\r
-/* TPI ITATBCTR2 Register Definitions */\r
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
-\r
-/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
-\r
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
-\r
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
-\r
-/* TPI ITATBCTR0 Register Definitions */\r
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
-\r
-/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
-\r
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
-\r
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
- \brief Type definitions for the Memory Protection Unit (MPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
- \brief Type definitions for the Floating Point Unit (FPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Floating Point Unit (FPU).\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1U];\r
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
- __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */\r
-} FPU_Type;\r
-\r
-/* Floating-Point Context Control Register Definitions */\r
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
-\r
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
-\r
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
-\r
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
-\r
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
-\r
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
-\r
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
-\r
-/* Floating-Point Context Address Register Definitions */\r
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
-\r
-/* Floating-Point Default Status Control Register Definitions */\r
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
-\r
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
-\r
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
-\r
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
-\r
-/* Media and FP Feature Register 0 Definitions */\r
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
-\r
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
-\r
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
-\r
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
-\r
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
-\r
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
-\r
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
-\r
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
-\r
-/* Media and FP Feature Register 1 Definitions */\r
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
-\r
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
-\r
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
-\r
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
-\r
-/* Media and FP Feature Register 2 Definitions */\r
-\r
-/*@} end of group CMSIS_FPU */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Type definitions for the Core Debug Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register Definitions */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register Definitions */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register Definitions */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_bitfield Core register bit field macros\r
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
- @{\r
- */\r
-\r
-/**\r
- \brief Mask and shift a bit field value for use in a register bit range.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
- \return Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
- \brief Mask and shift a register value to extract a bit filed value.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
- \return Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
-#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Debug Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
- #endif\r
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
- #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
- #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
- #define NVIC_GetActive __NVIC_GetActive\r
- #define NVIC_SetPriority __NVIC_SetPriority\r
- #define NVIC_GetPriority __NVIC_GetPriority\r
- #define NVIC_SystemReset __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
- #endif\r
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
- #define NVIC_SetVector __NVIC_SetVector\r
- #define NVIC_GetVector __NVIC_GetVector\r
-#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET 16\r
-\r
-\r
-\r
-/**\r
- \brief Set Priority Grouping\r
- \details Sets the priority grouping field using the required unlock sequence.\r
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
- Only values from 0..7 are used.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Priority grouping field.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
-\r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Priority Grouping\r
- \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
- \brief Enable Interrupt\r
- \details Enables a device specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Enable status\r
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt is not enabled.\r
- \return 1 Interrupt is enabled.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Disable Interrupt\r
- \details Disables a device specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- __DSB();\r
- __ISB();\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Pending Interrupt\r
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Pending Interrupt\r
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Clear Pending Interrupt\r
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Active Interrupt\r
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt status is not active.\r
- \return 1 Interrupt status is active.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Priority\r
- \details Sets the priority of a device specific interrupt or a processor exception.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- \note The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
- else\r
- {\r
- SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Priority\r
- \details Reads the priority of a device specific interrupt or a processor exception.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority.\r
- Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
- else\r
- {\r
- return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Encode Priority\r
- \details Encodes the priority for an interrupt with the given priority group,\r
- preemptive priority value, and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Used priority group.\r
- \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
- \param [in] SubPriority Subpriority value (starting from 0).\r
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- return (\r
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
- );\r
-}\r
-\r
-\r
-/**\r
- \brief Decode Priority\r
- \details Decodes an interrupt priority value with a given priority group to\r
- preemptive priority value and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
- \param [in] PriorityGroup Used priority group.\r
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
- \param [out] pSubPriority Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Vector\r
- \details Sets an interrupt vector in SRAM based interrupt vector table.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- VTOR must been relocated to SRAM before.\r
- \param [in] IRQn Interrupt number\r
- \param [in] vector Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
- uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Vector\r
- \details Reads an interrupt vector from interrupt vector table.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \return Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
- uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-}\r
-\r
-\r
-/**\r
- \brief System Reset\r
- \details Initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
-\r
- for(;;) /* wait until reset */\r
- {\r
- __NOP();\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-/* ########################## MPU functions #################################### */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-\r
-#include "mpu_armv7.h"\r
-\r
-#endif\r
-\r
-/* ########################## FPU functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
- \brief Function that provides FPU type.\r
- @{\r
- */\r
-\r
-/**\r
- \brief get FPU type\r
- \details returns the FPU type\r
- \returns\r
- - \b 0: No FPU\r
- - \b 1: Single precision FPU\r
- - \b 2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
- uint32_t mvfr0;\r
-\r
- mvfr0 = SCB->MVFR0;\r
- if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
- {\r
- return 2U; /* Double + Single precision FPU */\r
- }\r
- else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
- {\r
- return 1U; /* Single precision FPU */\r
- }\r
- else\r
- {\r
- return 0U; /* No FPU */\r
- }\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ########################## Cache functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_CacheFunctions Cache Functions\r
- \brief Functions that configure Instruction and Data cache.\r
- @{\r
- */\r
-\r
-/* Cache Size ID Register Macros */\r
-#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\r
-#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )\r
-\r
-\r
-/**\r
- \brief Enable I-Cache\r
- \details Turns on I-Cache\r
- */\r
-__STATIC_INLINE void SCB_EnableICache (void)\r
-{\r
- #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
- __DSB();\r
- __ISB();\r
- SCB->ICIALLU = 0UL; /* invalidate I-Cache */\r
- __DSB();\r
- __ISB();\r
- SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief Disable I-Cache\r
- \details Turns off I-Cache\r
- */\r
-__STATIC_INLINE void SCB_DisableICache (void)\r
-{\r
- #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
- __DSB();\r
- __ISB();\r
- SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */\r
- SCB->ICIALLU = 0UL; /* invalidate I-Cache */\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief Invalidate I-Cache\r
- \details Invalidates I-Cache\r
- */\r
-__STATIC_INLINE void SCB_InvalidateICache (void)\r
-{\r
- #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
- __DSB();\r
- __ISB();\r
- SCB->ICIALLU = 0UL;\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief Enable D-Cache\r
- \details Turns on D-Cache\r
- */\r
-__STATIC_INLINE void SCB_EnableDCache (void)\r
-{\r
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
- uint32_t ccsidr;\r
- uint32_t sets;\r
- uint32_t ways;\r
-\r
- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
- __DSB();\r
-\r
- ccsidr = SCB->CCSIDR;\r
-\r
- /* invalidate D-Cache */\r
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
- do {\r
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
- do {\r
- SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
- ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );\r
- #if defined ( __CC_ARM )\r
- __schedule_barrier();\r
- #endif\r
- } while (ways-- != 0U);\r
- } while(sets-- != 0U);\r
- __DSB();\r
-\r
- SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief Disable D-Cache\r
- \details Turns off D-Cache\r
- */\r
-__STATIC_INLINE void SCB_DisableDCache (void)\r
-{\r
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
- register uint32_t ccsidr;\r
- register uint32_t sets;\r
- register uint32_t ways;\r
-\r
- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
- __DSB();\r
-\r
- SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */\r
- __DSB();\r
-\r
- ccsidr = SCB->CCSIDR;\r
-\r
- /* clean & invalidate D-Cache */\r
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
- do {\r
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
- do {\r
- SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
- ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );\r
- #if defined ( __CC_ARM )\r
- __schedule_barrier();\r
- #endif\r
- } while (ways-- != 0U);\r
- } while(sets-- != 0U);\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief Invalidate D-Cache\r
- \details Invalidates D-Cache\r
- */\r
-__STATIC_INLINE void SCB_InvalidateDCache (void)\r
-{\r
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
- uint32_t ccsidr;\r
- uint32_t sets;\r
- uint32_t ways;\r
-\r
- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
- __DSB();\r
-\r
- ccsidr = SCB->CCSIDR;\r
-\r
- /* invalidate D-Cache */\r
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
- do {\r
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
- do {\r
- SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
- ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );\r
- #if defined ( __CC_ARM )\r
- __schedule_barrier();\r
- #endif\r
- } while (ways-- != 0U);\r
- } while(sets-- != 0U);\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief Clean D-Cache\r
- \details Cleans D-Cache\r
- */\r
-__STATIC_INLINE void SCB_CleanDCache (void)\r
-{\r
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
- uint32_t ccsidr;\r
- uint32_t sets;\r
- uint32_t ways;\r
-\r
- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
- __DSB();\r
-\r
- ccsidr = SCB->CCSIDR;\r
-\r
- /* clean D-Cache */\r
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
- do {\r
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
- do {\r
- SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |\r
- ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );\r
- #if defined ( __CC_ARM )\r
- __schedule_barrier();\r
- #endif\r
- } while (ways-- != 0U);\r
- } while(sets-- != 0U);\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief Clean & Invalidate D-Cache\r
- \details Cleans and Invalidates D-Cache\r
- */\r
-__STATIC_INLINE void SCB_CleanInvalidateDCache (void)\r
-{\r
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
- uint32_t ccsidr;\r
- uint32_t sets;\r
- uint32_t ways;\r
-\r
- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
- __DSB();\r
-\r
- ccsidr = SCB->CCSIDR;\r
-\r
- /* clean & invalidate D-Cache */\r
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
- do {\r
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
- do {\r
- SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
- ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );\r
- #if defined ( __CC_ARM )\r
- __schedule_barrier();\r
- #endif\r
- } while (ways-- != 0U);\r
- } while(sets-- != 0U);\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief D-Cache Invalidate by address\r
- \details Invalidates D-Cache for the given address\r
- \param[in] addr address (aligned to 32-byte boundary)\r
- \param[in] dsize size of memory block (in number of bytes)\r
-*/\r
-__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
-{\r
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
- int32_t op_size = dsize;\r
- uint32_t op_addr = (uint32_t)addr;\r
- int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
-\r
- __DSB();\r
-\r
- while (op_size > 0) {\r
- SCB->DCIMVAC = op_addr;\r
- op_addr += (uint32_t)linesize;\r
- op_size -= linesize;\r
- }\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief D-Cache Clean by address\r
- \details Cleans D-Cache for the given address\r
- \param[in] addr address (aligned to 32-byte boundary)\r
- \param[in] dsize size of memory block (in number of bytes)\r
-*/\r
-__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
-{\r
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
- int32_t op_size = dsize;\r
- uint32_t op_addr = (uint32_t) addr;\r
- int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
-\r
- __DSB();\r
-\r
- while (op_size > 0) {\r
- SCB->DCCMVAC = op_addr;\r
- op_addr += (uint32_t)linesize;\r
- op_size -= linesize;\r
- }\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief D-Cache Clean and Invalidate by address\r
- \details Cleans and invalidates D_Cache for the given address\r
- \param[in] addr address (aligned to 32-byte boundary)\r
- \param[in] dsize size of memory block (in number of bytes)\r
-*/\r
-__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
-{\r
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
- int32_t op_size = dsize;\r
- uint32_t op_addr = (uint32_t) addr;\r
- int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
-\r
- __DSB();\r
-\r
- while (op_size > 0) {\r
- SCB->DCCIMVAC = op_addr;\r
- op_addr += (uint32_t)linesize;\r
- op_size -= linesize;\r
- }\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_CacheFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
- \brief System Tick Configuration\r
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
- \param [in] ticks Number of ticks between two interrupts.\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
- {\r
- return (1UL); /* Reload value impossible */\r
- }\r
-\r
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0UL); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_core_DebugFunctions ITM Functions\r
- \brief Functions that access the ITM debug interface.\r
- @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
-#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/**\r
- \brief ITM Send Character\r
- \details Transmits a character via the ITM channel 0, and\r
- \li Just returns when no debugger is connected that has booked the output.\r
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
- \param [in] ch Character to transmit.\r
- \returns Character to transmit.\r
- */\r
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
- {\r
- while (ITM->PORT[0U].u32 == 0UL)\r
- {\r
- __NOP();\r
- }\r
- ITM->PORT[0U].u8 = (uint8_t)ch;\r
- }\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Receive Character\r
- \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
- \return Received character.\r
- \return -1 No character pending.\r
- */\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
-{\r
- int32_t ch = -1; /* no character available */\r
-\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
- {\r
- ch = ITM_RxBuffer;\r
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
- }\r
-\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Check Character\r
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
- \return 0 No character available.\r
- \return 1 Character available.\r
- */\r
-__STATIC_INLINE int32_t ITM_CheckChar (void)\r
-{\r
-\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
- {\r
- return (0); /* no character available */\r
- }\r
- else\r
- {\r
- return (1); /* character available */\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM7_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_sc000.h\r
- * @brief CMSIS SC000 Core Peripheral Access Layer Header File\r
- * @version V5.0.2\r
- * @date 19. April 2017\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_SC000_H_GENERIC\r
-#define __CORE_SC000_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
- \ingroup SC000\r
- @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
-\r
-/* CMSIS SC000 definitions */\r
-#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
-#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \\r
- __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_SC (000U) /*!< Cortex secure core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
- This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED 0U\r
-\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #if defined __ARM_PCS_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
- #if defined __TI_VFP_SUPPORT__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __CSMC__ )\r
- #if ( __CSMC__ & 0x400U)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_SC000_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_SC000_H_DEPENDANT\r
-#define __CORE_SC000_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __SC000_REV\r
- #define __SC000_REV 0x0000U\r
- #warning "__SC000_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0U\r
- #warning "__MPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 2U\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0U\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
-#define __OM volatile /*! Defines 'write only' structure member permissions */\r
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group SC000 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- - Core MPU Register\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos 31U /*!< APSR: N Position */\r
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos 29U /*!< APSR: C Position */\r
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos 28U /*!< APSR: V Position */\r
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
-\r
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
-\r
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:1; /*!< bit: 0 Reserved */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[31U];\r
- __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[31U];\r
- __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[31U];\r
- __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[31U];\r
- uint32_t RESERVED4[64U];\r
- __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
-} NVIC_Type;\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- uint32_t RESERVED0[1U];\r
- __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
- uint32_t RESERVED1[154U];\r
- __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
- \brief Type definitions for the System Control and ID Register not in the SCB\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[2U];\r
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
-} SCnSCB_Type;\r
-\r
-/* Auxiliary Control Register Definitions */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
- \brief Type definitions for the Memory Protection Unit (MPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
- Therefore they are not covered by the SC000 header file.\r
- @{\r
- */\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_bitfield Core register bit field macros\r
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
- @{\r
- */\r
-\r
-/**\r
- \brief Mask and shift a bit field value for use in a register bit range.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
- \return Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
- \brief Mask and shift a register value to extract a bit filed value.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
- \return Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
- #endif\r
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
-/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */\r
-/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */\r
- #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
- #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
-/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */\r
- #define NVIC_SetPriority __NVIC_SetPriority\r
- #define NVIC_GetPriority __NVIC_GetPriority\r
- #define NVIC_SystemReset __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
- #endif\r
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
- #define NVIC_SetVector __NVIC_SetVector\r
- #define NVIC_GetVector __NVIC_GetVector\r
-#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET 16\r
-\r
-\r
-/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
-/* The following MACROS handle generation of the register offset and byte masks */\r
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
-\r
-\r
-/**\r
- \brief Enable Interrupt\r
- \details Enables a device specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Enable status\r
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt is not enabled.\r
- \return 1 Interrupt is enabled.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Disable Interrupt\r
- \details Disables a device specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- __DSB();\r
- __ISB();\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Pending Interrupt\r
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Pending Interrupt\r
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Clear Pending Interrupt\r
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Priority\r
- \details Sets the priority of a device specific interrupt or a processor exception.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- \note The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
- }\r
- else\r
- {\r
- SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Priority\r
- \details Reads the priority of a device specific interrupt or a processor exception.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority.\r
- Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
- else\r
- {\r
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Vector\r
- \details Sets an interrupt vector in SRAM based interrupt vector table.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- VTOR must been relocated to SRAM before.\r
- \param [in] IRQn Interrupt number\r
- \param [in] vector Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
- uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Vector\r
- \details Reads an interrupt vector from interrupt vector table.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \return Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
- uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-}\r
-\r
-\r
-/**\r
- \brief System Reset\r
- \details Initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- SCB_AIRCR_SYSRESETREQ_Msk);\r
- __DSB(); /* Ensure completion of memory access */\r
-\r
- for(;;) /* wait until reset */\r
- {\r
- __NOP();\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-/* ########################## FPU functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
- \brief Function that provides FPU type.\r
- @{\r
- */\r
-\r
-/**\r
- \brief get FPU type\r
- \details returns the FPU type\r
- \returns\r
- - \b 0: No FPU\r
- - \b 1: Single precision FPU\r
- - \b 2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
- return 0U; /* No FPU */\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
- \brief System Tick Configuration\r
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
- \param [in] ticks Number of ticks between two interrupts.\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
- {\r
- return (1UL); /* Reload value impossible */\r
- }\r
-\r
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0UL); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_SC000_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_sc300.h\r
- * @brief CMSIS SC300 Core Peripheral Access Layer Header File\r
- * @version V5.0.2\r
- * @date 19. April 2017\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_SC300_H_GENERIC\r
-#define __CORE_SC300_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
- \ingroup SC3000\r
- @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
-\r
-/* CMSIS SC300 definitions */\r
-#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
-#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \\r
- __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_SC (300U) /*!< Cortex secure core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
- This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED 0U\r
-\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #if defined __ARM_PCS_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
- #if defined __TI_VFP_SUPPORT__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __CSMC__ )\r
- #if ( __CSMC__ & 0x400U)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_SC300_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_SC300_H_DEPENDANT\r
-#define __CORE_SC300_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __SC300_REV\r
- #define __SC300_REV 0x0000U\r
- #warning "__SC300_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0U\r
- #warning "__MPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 3U\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0U\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
-#define __OM volatile /*! Defines 'write only' structure member permissions */\r
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group SC300 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- - Core Debug Register\r
- - Core MPU Register\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos 31U /*!< APSR: N Position */\r
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos 29U /*!< APSR: C Position */\r
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos 28U /*!< APSR: V Position */\r
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
-\r
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
- uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
- uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */\r
- uint32_t T:1; /*!< bit: 24 Thumb bit */\r
- uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
-\r
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
-\r
-#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
-#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
-\r
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
-\r
-#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
-#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
-\r
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24U];\r
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24U];\r
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24U];\r
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24U];\r
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
- uint32_t RESERVED4[56U];\r
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644U];\r
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
- __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
- __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
- __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
- __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
- __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
- uint32_t RESERVED0[5U];\r
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
- uint32_t RESERVED1[129U];\r
- __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */\r
-#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
-\r
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Register Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
-\r
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
-\r
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
-\r
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
-\r
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
-\r
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
-\r
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
-\r
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
-\r
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
-\r
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
-\r
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
-\r
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
-\r
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
-\r
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
-\r
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
-\r
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
-\r
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
-\r
-/* SCB Hard Fault Status Register Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
- \brief Type definitions for the System Control and ID Register not in the SCB\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1U];\r
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
- uint32_t RESERVED1[1U];\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
- __OM union\r
- {\r
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864U];\r
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
- uint32_t RESERVED1[15U];\r
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15U];\r
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
- uint32_t RESERVED3[29U];\r
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43U];\r
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
- uint32_t RESERVED5[6U];\r
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
- \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
- uint32_t RESERVED0[1U];\r
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
- uint32_t RESERVED1[1U];\r
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
- uint32_t RESERVED2[1U];\r
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
-\r
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
-\r
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
-\r
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
-\r
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
-\r
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
-\r
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
-\r
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
-\r
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
-\r
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
-\r
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
-\r
-/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
-\r
-/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
-\r
-/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
-\r
-/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
-\r
-/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
-\r
-/* DWT Comparator Mask Register Definitions */\r
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
-\r
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
-\r
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
-\r
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
-\r
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
- \brief Type definitions for the Trace Port Interface (TPI)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
- uint32_t RESERVED0[2U];\r
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
- uint32_t RESERVED1[55U];\r
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
- uint32_t RESERVED2[131U];\r
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
- uint32_t RESERVED3[759U];\r
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
- uint32_t RESERVED4[1U];\r
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
- uint32_t RESERVED5[39U];\r
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
- uint32_t RESERVED7[8U];\r
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
-\r
-/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
-\r
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
-\r
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
-\r
-/* TPI ITATBCTR2 Register Definitions */\r
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
-\r
-/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
-\r
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
-\r
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
-\r
-/* TPI ITATBCTR0 Register Definitions */\r
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
-\r
-/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
-\r
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
-\r
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
- \brief Type definitions for the Memory Protection Unit (MPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Type definitions for the Core Debug Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register Definitions */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register Definitions */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register Definitions */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_bitfield Core register bit field macros\r
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
- @{\r
- */\r
-\r
-/**\r
- \brief Mask and shift a bit field value for use in a register bit range.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
- \return Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
- \brief Mask and shift a register value to extract a bit filed value.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
- \return Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Debug Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
- #endif\r
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
- #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
- #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
- #define NVIC_GetActive __NVIC_GetActive\r
- #define NVIC_SetPriority __NVIC_SetPriority\r
- #define NVIC_GetPriority __NVIC_GetPriority\r
- #define NVIC_SystemReset __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
- #endif\r
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
- #define NVIC_SetVector __NVIC_SetVector\r
- #define NVIC_GetVector __NVIC_GetVector\r
-#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET 16\r
-\r
-\r
-\r
-/**\r
- \brief Set Priority Grouping\r
- \details Sets the priority grouping field using the required unlock sequence.\r
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
- Only values from 0..7 are used.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Priority grouping field.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
-\r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Priority Grouping\r
- \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
- \brief Enable Interrupt\r
- \details Enables a device specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Enable status\r
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt is not enabled.\r
- \return 1 Interrupt is enabled.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Disable Interrupt\r
- \details Disables a device specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- __DSB();\r
- __ISB();\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Pending Interrupt\r
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Pending Interrupt\r
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Clear Pending Interrupt\r
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Active Interrupt\r
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt status is not active.\r
- \return 1 Interrupt status is active.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Priority\r
- \details Sets the priority of a device specific interrupt or a processor exception.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- \note The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
- else\r
- {\r
- SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Priority\r
- \details Reads the priority of a device specific interrupt or a processor exception.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority.\r
- Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
- else\r
- {\r
- return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Encode Priority\r
- \details Encodes the priority for an interrupt with the given priority group,\r
- preemptive priority value, and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Used priority group.\r
- \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
- \param [in] SubPriority Subpriority value (starting from 0).\r
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- return (\r
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
- );\r
-}\r
-\r
-\r
-/**\r
- \brief Decode Priority\r
- \details Decodes an interrupt priority value with a given priority group to\r
- preemptive priority value and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
- \param [in] PriorityGroup Used priority group.\r
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
- \param [out] pSubPriority Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Vector\r
- \details Sets an interrupt vector in SRAM based interrupt vector table.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- VTOR must been relocated to SRAM before.\r
- \param [in] IRQn Interrupt number\r
- \param [in] vector Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
- uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Vector\r
- \details Reads an interrupt vector from interrupt vector table.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \return Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
- uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-}\r
-\r
-\r
-/**\r
- \brief System Reset\r
- \details Initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
-\r
- for(;;) /* wait until reset */\r
- {\r
- __NOP();\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-/* ########################## FPU functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
- \brief Function that provides FPU type.\r
- @{\r
- */\r
-\r
-/**\r
- \brief get FPU type\r
- \details returns the FPU type\r
- \returns\r
- - \b 0: No FPU\r
- - \b 1: Single precision FPU\r
- - \b 2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
- return 0U; /* No FPU */\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
- \brief System Tick Configuration\r
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
- \param [in] ticks Number of ticks between two interrupts.\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
- {\r
- return (1UL); /* Reload value impossible */\r
- }\r
-\r
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0UL); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_core_DebugFunctions ITM Functions\r
- \brief Functions that access the ITM debug interface.\r
- @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
-#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/**\r
- \brief ITM Send Character\r
- \details Transmits a character via the ITM channel 0, and\r
- \li Just returns when no debugger is connected that has booked the output.\r
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
- \param [in] ch Character to transmit.\r
- \returns Character to transmit.\r
- */\r
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
- {\r
- while (ITM->PORT[0U].u32 == 0UL)\r
- {\r
- __NOP();\r
- }\r
- ITM->PORT[0U].u8 = (uint8_t)ch;\r
- }\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Receive Character\r
- \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
- \return Received character.\r
- \return -1 No character pending.\r
- */\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
-{\r
- int32_t ch = -1; /* no character available */\r
-\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
- {\r
- ch = ITM_RxBuffer;\r
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
- }\r
-\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Check Character\r
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
- \return 0 No character available.\r
- \return 1 Character available.\r
- */\r
-__STATIC_INLINE int32_t ITM_CheckChar (void)\r
-{\r
-\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
- {\r
- return (0); /* no character available */\r
- }\r
- else\r
- {\r
- return (1); /* character available */\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_SC300_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
static void prvBootNonSecure( uint32_t ulNonSecureStartAddress );\r
/*-----------------------------------------------------------*/\r
\r
+/* Secure main. */\r
+int main(void)\r
+{\r
+ /* Unlock protected registers. */\r
+ SYS_UnlockReg();\r
+\r
+ /* Initialize the hardware. */\r
+ prvSetupHardware();\r
+\r
+ /* Print banner. */\r
+ printf( "\n" );\r
+ printf( "+---------------------------------------------+\n" );\r
+ printf( "| Secure is running ... |\n" );\r
+ printf( "+---------------------------------------------+\n" );\r
+\r
+ /* Do not generate Systick interrupt on secure side. */\r
+ SysTick_Config( 1 );\r
+\r
+ /* Set GPIO Port A to non-secure for controlling LEDs from the non-secure\r
+ * side . */\r
+ SCU_SET_IONSSET( SCU_IONSSET_PA_Msk );\r
+\r
+ /* Set UART0 to non-secure for debug output from non-secure side. */\r
+ SCU_SET_PNSSET( UART0_Attr );\r
+\r
+ /* Lock protected registers before booting non-secure code. */\r
+ SYS_LockReg();\r
+\r
+ /* Boot the non-secure code. */\r
+ printf( "Entering non-secure world ...\n" );\r
+ prvBootNonSecure( mainNONSECURE_APP_START_ADDRESS );\r
+\r
+ /* Non-secure software does not return, this code is not executed. */\r
+ for( ; ; )\r
+ {\r
+ /* Should not reach here. */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
static void prvSetupHardware( void )\r
{\r
/* Init System Clock. */\r
}\r
/*-----------------------------------------------------------*/\r
\r
-/* Secure main. */\r
-int main(void)\r
-{\r
- /* Unlock protected registers. */\r
- SYS_UnlockReg();\r
-\r
- /* Initialize the hardware. */\r
- prvSetupHardware();\r
-\r
- /* Print banner. */\r
- printf( "\n" );\r
- printf( "+---------------------------------------------+\n" );\r
- printf( "| Secure is running ... |\n" );\r
- printf( "+---------------------------------------------+\n" );\r
-\r
- /* Do not generate Systick interrupt on secure side. */\r
- SysTick_Config( 1 );\r
-\r
- /* Set GPIO Port A to non-secure for controlling LEDs from the non-secure\r
- * side . */\r
- SCU_SET_IONSSET( SCU_IONSSET_PA_Msk );\r
-\r
- /* Set UART0 to non-secure for debug output from non-secure side. */\r
- SCU_SET_PNSSET( UART0_Attr );\r
-\r
- /* Lock protected registers before booting non-secure code. */\r
- SYS_LockReg();\r
-\r
- /* Boot the non-secure code. */\r
- printf( "Entering non-secure world ...\n" );\r
- prvBootNonSecure( mainNONSECURE_APP_START_ADDRESS );\r
-\r
- /* Non-secure software does not return, this code is not executed. */\r
- for( ; ; )\r
- {\r
- /* Should not reach here. */\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
+++ /dev/null
-/******************************************************************************\r
- * @file arm_math.h\r
- * @brief Public header file for CMSIS DSP LibraryU\r
- * @version V1.5.3\r
- * @date 10. January 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-/**\r
- \mainpage CMSIS DSP Software Library\r
- *\r
- * Introduction\r
- * ------------\r
- *\r
- * This user manual describes the CMSIS DSP software library,\r
- * a suite of common signal processing functions for use on Cortex-M processor based devices.\r
- *\r
- * The library is divided into a number of functions each covering a specific category:\r
- * - Basic math functions\r
- * - Fast math functions\r
- * - Complex math functions\r
- * - Filters\r
- * - Matrix functions\r
- * - Transforms\r
- * - Motor control functions\r
- * - Statistical functions\r
- * - Support functions\r
- * - Interpolation functions\r
- *\r
- * The library has separate functions for operating on 8-bit integers, 16-bit integers,\r
- * 32-bit integer and 32-bit floating-point values.\r
- *\r
- * Using the Library\r
- * ------------\r
- *\r
- * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.\r
- * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)\r
- * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)\r
- * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)\r
- * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)\r
- * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)\r
- * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)\r
- * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)\r
- * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)\r
- * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)\r
- * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)\r
- * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)\r
- * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)\r
- * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)\r
- * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)\r
- * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)\r
- * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)\r
- * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)\r
- * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)\r
- * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)\r
- *\r
- * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.\r
- * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single\r
- * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.\r
- * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or\r
- * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.\r
- * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.\r
- * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.\r
- * \r
- *\r
- * Examples\r
- * --------\r
- *\r
- * The library ships with a number of examples which demonstrate how to use the library functions.\r
- *\r
- * Toolchain Support\r
- * ------------\r
- *\r
- * The library has been developed and tested with MDK version 5.14.0.0\r
- * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\r
- *\r
- * Building the Library\r
- * ------------\r
- *\r
- * The library installer contains a project file to rebuild libraries on MDK toolchain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.\r
- * - arm_cortexM_math.uvprojx\r
- *\r
- *\r
- * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.\r
- *\r
- * Preprocessor Macros\r
- * ------------\r
- *\r
- * Each library project have different preprocessor macros.\r
- *\r
- * - UNALIGNED_SUPPORT_DISABLE:\r
- *\r
- * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access\r
- *\r
- * - ARM_MATH_BIG_ENDIAN:\r
- *\r
- * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.\r
- *\r
- * - ARM_MATH_MATRIX_CHECK:\r
- *\r
- * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices\r
- *\r
- * - ARM_MATH_ROUNDING:\r
- *\r
- * Define macro ARM_MATH_ROUNDING for rounding on support functions\r
- *\r
- * - ARM_MATH_CMx:\r
- *\r
- * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target\r
- * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and\r
- * ARM_MATH_CM7 for building the library on cortex-M7.\r
- *\r
- * - ARM_MATH_ARMV8MxL:\r
- *\r
- * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library\r
- * on Armv8-M Mainline target.\r
- *\r
- * - __FPU_PRESENT:\r
- *\r
- * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.\r
- *\r
- * - __DSP_PRESENT:\r
- *\r
- * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions.\r
- *\r
- * <hr>\r
- * CMSIS-DSP in ARM::CMSIS Pack\r
- * -----------------------------\r
- *\r
- * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:\r
- * |File/Folder |Content |\r
- * |------------------------------|------------------------------------------------------------------------|\r
- * |\b CMSIS\\Documentation\\DSP | This documentation |\r
- * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |\r
- * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |\r
- * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |\r
- *\r
- * <hr>\r
- * Revision History of CMSIS-DSP\r
- * ------------\r
- * Please refer to \ref ChangeLog_pg.\r
- *\r
- * Copyright Notice\r
- * ------------\r
- *\r
- * Copyright (C) 2010-2015 Arm Limited. All rights reserved.\r
- */\r
-\r
-\r
-/**\r
- * @defgroup groupMath Basic Math Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupFastMath Fast Math Functions\r
- * This set of functions provides a fast approximation to sine, cosine, and square root.\r
- * As compared to most of the other functions in the CMSIS math library, the fast math functions\r
- * operate on individual values and not arrays.\r
- * There are separate functions for Q15, Q31, and floating-point data.\r
- *\r
- */\r
-\r
-/**\r
- * @defgroup groupCmplxMath Complex Math Functions\r
- * This set of functions operates on complex data vectors.\r
- * The data in the complex arrays is stored in an interleaved fashion\r
- * (real, imag, real, imag, ...).\r
- * In the API functions, the number of samples in a complex array refers\r
- * to the number of complex values; the array contains twice this number of\r
- * real values.\r
- */\r
-\r
-/**\r
- * @defgroup groupFilters Filtering Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupMatrix Matrix Functions\r
- *\r
- * This set of functions provides basic matrix math operations.\r
- * The functions operate on matrix data structures. For example,\r
- * the type\r
- * definition for the floating-point matrix structure is shown\r
- * below:\r
- * <pre>\r
- * typedef struct\r
- * {\r
- * uint16_t numRows; // number of rows of the matrix.\r
- * uint16_t numCols; // number of columns of the matrix.\r
- * float32_t *pData; // points to the data of the matrix.\r
- * } arm_matrix_instance_f32;\r
- * </pre>\r
- * There are similar definitions for Q15 and Q31 data types.\r
- *\r
- * The structure specifies the size of the matrix and then points to\r
- * an array of data. The array is of size <code>numRows X numCols</code>\r
- * and the values are arranged in row order. That is, the\r
- * matrix element (i, j) is stored at:\r
- * <pre>\r
- * pData[i*numCols + j]\r
- * </pre>\r
- *\r
- * \par Init Functions\r
- * There is an associated initialization function for each type of matrix\r
- * data structure.\r
- * The initialization function sets the values of the internal structure fields.\r
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>\r
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.\r
- *\r
- * \par\r
- * Use of the initialization function is optional. However, if initialization function is used\r
- * then the instance structure cannot be placed into a const data section.\r
- * To place the instance structure in a const data\r
- * section, manually initialize the data structure. For example:\r
- * <pre>\r
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>\r
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>\r
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>\r
- * </pre>\r
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>\r
- * specifies the number of columns, and <code>pData</code> points to the\r
- * data array.\r
- *\r
- * \par Size Checking\r
- * By default all of the matrix functions perform size checking on the input and\r
- * output matrices. For example, the matrix addition function verifies that the\r
- * two input matrices and the output matrix all have the same number of rows and\r
- * columns. If the size check fails the functions return:\r
- * <pre>\r
- * ARM_MATH_SIZE_MISMATCH\r
- * </pre>\r
- * Otherwise the functions return\r
- * <pre>\r
- * ARM_MATH_SUCCESS\r
- * </pre>\r
- * There is some overhead associated with this matrix size checking.\r
- * The matrix size checking is enabled via the \#define\r
- * <pre>\r
- * ARM_MATH_MATRIX_CHECK\r
- * </pre>\r
- * within the library project settings. By default this macro is defined\r
- * and size checking is enabled. By changing the project settings and\r
- * undefining this macro size checking is eliminated and the functions\r
- * run a bit faster. With size checking disabled the functions always\r
- * return <code>ARM_MATH_SUCCESS</code>.\r
- */\r
-\r
-/**\r
- * @defgroup groupTransforms Transform Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupController Controller Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupStats Statistics Functions\r
- */\r
-/**\r
- * @defgroup groupSupport Support Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupInterpolation Interpolation Functions\r
- * These functions perform 1- and 2-dimensional interpolation of data.\r
- * Linear interpolation is used for 1-dimensional data and\r
- * bilinear interpolation is used for 2-dimensional data.\r
- */\r
-\r
-/**\r
- * @defgroup groupExamples Examples\r
- */\r
-#ifndef _ARM_MATH_H\r
-#define _ARM_MATH_H\r
-\r
-/* Compiler specific diagnostic adjustment */\r
-#if defined ( __CC_ARM )\r
-\r
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
-\r
-#elif defined ( __GNUC__ )\r
-#pragma GCC diagnostic push\r
-#pragma GCC diagnostic ignored "-Wsign-conversion"\r
-#pragma GCC diagnostic ignored "-Wconversion"\r
-#pragma GCC diagnostic ignored "-Wunused-parameter"\r
-\r
-#elif defined ( __ICCARM__ )\r
-\r
-#elif defined ( __TI_ARM__ )\r
-\r
-#elif defined ( __CSMC__ )\r
-\r
-#elif defined ( __TASKING__ )\r
-\r
-#else\r
- #error Unknown compiler\r
-#endif\r
-\r
-\r
-#define __CMSIS_GENERIC /* disable NVIC and Systick functions */\r
-\r
-#if defined(ARM_MATH_CM7)\r
- #include "core_cm7.h"\r
- #define ARM_MATH_DSP\r
-#elif defined (ARM_MATH_CM4)\r
- #include "core_cm4.h"\r
- #define ARM_MATH_DSP\r
-#elif defined (ARM_MATH_CM33)\r
- #include "core_cm33.h"\r
- #define ARM_MATH_DSP\r
-#elif defined (ARM_MATH_CM3)\r
- #include "core_cm3.h"\r
-#elif defined (ARM_MATH_CM0)\r
- #include "core_cm0.h"\r
- #define ARM_MATH_CM0_FAMILY\r
-#elif defined (ARM_MATH_CM0PLUS)\r
- #include "core_cm0plus.h"\r
- #define ARM_MATH_CM0_FAMILY\r
-#elif defined (ARM_MATH_ARMV8MBL)\r
- #include "core_armv8mbl.h"\r
- #define ARM_MATH_CM0_FAMILY\r
-#elif defined (ARM_MATH_ARMV8MML)\r
- #include "core_armv8mml.h"\r
- #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))\r
- #define ARM_MATH_DSP\r
- #endif\r
-#else\r
- #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"\r
-#endif\r
-\r
-#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */\r
-#include "string.h"\r
-#include "math.h"\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-\r
- /**\r
- * @brief Macros required for reciprocal calculation in Normalized LMS\r
- */\r
-\r
-#define DELTA_Q31 (0x100)\r
-#define DELTA_Q15 0x5\r
-#define INDEX_MASK 0x0000003F\r
-#ifndef PI\r
- #define PI 3.14159265358979f\r
-#endif\r
-\r
- /**\r
- * @brief Macros required for SINE and COSINE Fast math approximations\r
- */\r
-\r
-#define FAST_MATH_TABLE_SIZE 512\r
-#define FAST_MATH_Q31_SHIFT (32 - 10)\r
-#define FAST_MATH_Q15_SHIFT (16 - 10)\r
-#define CONTROLLER_Q31_SHIFT (32 - 9)\r
-#define TABLE_SPACING_Q31 0x400000\r
-#define TABLE_SPACING_Q15 0x80\r
-\r
- /**\r
- * @brief Macros required for SINE and COSINE Controller functions\r
- */\r
- /* 1.31(q31) Fixed value of 2/360 */\r
- /* -1 to +1 is divided into 360 values so total spacing is (2/360) */\r
-#define INPUT_SPACING 0xB60B61\r
-\r
- /**\r
- * @brief Macro for Unaligned Support\r
- */\r
-#ifndef UNALIGNED_SUPPORT_DISABLE\r
- #define ALIGN4\r
-#else\r
- #if defined (__GNUC__)\r
- #define ALIGN4 __attribute__((aligned(4)))\r
- #else\r
- #define ALIGN4 __align(4)\r
- #endif\r
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */\r
-\r
- /**\r
- * @brief Error status returned by some functions in the library.\r
- */\r
-\r
- typedef enum\r
- {\r
- ARM_MATH_SUCCESS = 0, /**< No error */\r
- ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */\r
- ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */\r
- ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */\r
- ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */\r
- ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */\r
- ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */\r
- } arm_status;\r
-\r
- /**\r
- * @brief 8-bit fractional data type in 1.7 format.\r
- */\r
- typedef int8_t q7_t;\r
-\r
- /**\r
- * @brief 16-bit fractional data type in 1.15 format.\r
- */\r
- typedef int16_t q15_t;\r
-\r
- /**\r
- * @brief 32-bit fractional data type in 1.31 format.\r
- */\r
- typedef int32_t q31_t;\r
-\r
- /**\r
- * @brief 64-bit fractional data type in 1.63 format.\r
- */\r
- typedef int64_t q63_t;\r
-\r
- /**\r
- * @brief 32-bit floating-point type definition.\r
- */\r
- typedef float float32_t;\r
-\r
- /**\r
- * @brief 64-bit floating-point type definition.\r
- */\r
- typedef double float64_t;\r
-\r
- /**\r
- * @brief definition to read/write two 16 bit values.\r
- */\r
-#if defined ( __CC_ARM )\r
- #define __SIMD32_TYPE int32_t __packed\r
- #define CMSIS_UNUSED __attribute__((unused))\r
- #define CMSIS_INLINE __attribute__((always_inline))\r
-\r
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
- #define __SIMD32_TYPE int32_t\r
- #define CMSIS_UNUSED __attribute__((unused))\r
- #define CMSIS_INLINE __attribute__((always_inline))\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __SIMD32_TYPE int32_t\r
- #define CMSIS_UNUSED __attribute__((unused))\r
- #define CMSIS_INLINE __attribute__((always_inline))\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __SIMD32_TYPE int32_t __packed\r
- #define CMSIS_UNUSED\r
- #define CMSIS_INLINE\r
-\r
-#elif defined ( __TI_ARM__ )\r
- #define __SIMD32_TYPE int32_t\r
- #define CMSIS_UNUSED __attribute__((unused))\r
- #define CMSIS_INLINE\r
-\r
-#elif defined ( __CSMC__ )\r
- #define __SIMD32_TYPE int32_t\r
- #define CMSIS_UNUSED\r
- #define CMSIS_INLINE\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __SIMD32_TYPE __unaligned int32_t\r
- #define CMSIS_UNUSED\r
- #define CMSIS_INLINE\r
-\r
-#else\r
- #error Unknown compiler\r
-#endif\r
-\r
-#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))\r
-#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))\r
-#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))\r
-#define __SIMD64(addr) (*(int64_t **) & (addr))\r
-\r
-#if !defined (ARM_MATH_DSP)\r
- /**\r
- * @brief definition to pack two 16 bit values.\r
- */\r
-#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \\r
- (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )\r
-#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \\r
- (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )\r
-\r
-#endif /* !defined (ARM_MATH_DSP) */\r
-\r
- /**\r
- * @brief definition to pack four 8 bit values.\r
- */\r
-#ifndef ARM_MATH_BIG_ENDIAN\r
-\r
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \\r
- (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \\r
- (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \\r
- (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )\r
-#else\r
-\r
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \\r
- (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \\r
- (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \\r
- (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )\r
-\r
-#endif\r
-\r
-\r
- /**\r
- * @brief Clips Q63 to Q31 values.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(\r
- q63_t x)\r
- {\r
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
- ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;\r
- }\r
-\r
- /**\r
- * @brief Clips Q63 to Q15 values.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(\r
- q63_t x)\r
- {\r
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
- ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);\r
- }\r
-\r
- /**\r
- * @brief Clips Q31 to Q7 values.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(\r
- q31_t x)\r
- {\r
- return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?\r
- ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;\r
- }\r
-\r
- /**\r
- * @brief Clips Q31 to Q15 values.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(\r
- q31_t x)\r
- {\r
- return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?\r
- ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;\r
- }\r
-\r
- /**\r
- * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.\r
- */\r
-\r
- CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(\r
- q63_t x,\r
- q31_t y)\r
- {\r
- return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +\r
- (((q63_t) (x >> 32) * y)));\r
- }\r
-\r
- /**\r
- * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.\r
- */\r
-\r
- CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(\r
- q31_t in,\r
- q31_t * dst,\r
- q31_t * pRecipTable)\r
- {\r
- q31_t out;\r
- uint32_t tempVal;\r
- uint32_t index, i;\r
- uint32_t signBits;\r
-\r
- if (in > 0)\r
- {\r
- signBits = ((uint32_t) (__CLZ( in) - 1));\r
- }\r
- else\r
- {\r
- signBits = ((uint32_t) (__CLZ(-in) - 1));\r
- }\r
-\r
- /* Convert input sample to 1.31 format */\r
- in = (in << signBits);\r
-\r
- /* calculation of index for initial approximated Val */\r
- index = (uint32_t)(in >> 24);\r
- index = (index & INDEX_MASK);\r
-\r
- /* 1.31 with exp 1 */\r
- out = pRecipTable[index];\r
-\r
- /* calculation of reciprocal value */\r
- /* running approximation for two iterations */\r
- for (i = 0U; i < 2U; i++)\r
- {\r
- tempVal = (uint32_t) (((q63_t) in * out) >> 31);\r
- tempVal = 0x7FFFFFFFu - tempVal;\r
- /* 1.31 with exp 1 */\r
- /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */\r
- out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);\r
- }\r
-\r
- /* write output */\r
- *dst = out;\r
-\r
- /* return num of signbits of out = 1/in value */\r
- return (signBits + 1U);\r
- }\r
-\r
-\r
- /**\r
- * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(\r
- q15_t in,\r
- q15_t * dst,\r
- q15_t * pRecipTable)\r
- {\r
- q15_t out = 0;\r
- uint32_t tempVal = 0;\r
- uint32_t index = 0, i = 0;\r
- uint32_t signBits = 0;\r
-\r
- if (in > 0)\r
- {\r
- signBits = ((uint32_t)(__CLZ( in) - 17));\r
- }\r
- else\r
- {\r
- signBits = ((uint32_t)(__CLZ(-in) - 17));\r
- }\r
-\r
- /* Convert input sample to 1.15 format */\r
- in = (in << signBits);\r
-\r
- /* calculation of index for initial approximated Val */\r
- index = (uint32_t)(in >> 8);\r
- index = (index & INDEX_MASK);\r
-\r
- /* 1.15 with exp 1 */\r
- out = pRecipTable[index];\r
-\r
- /* calculation of reciprocal value */\r
- /* running approximation for two iterations */\r
- for (i = 0U; i < 2U; i++)\r
- {\r
- tempVal = (uint32_t) (((q31_t) in * out) >> 15);\r
- tempVal = 0x7FFFu - tempVal;\r
- /* 1.15 with exp 1 */\r
- out = (q15_t) (((q31_t) out * tempVal) >> 14);\r
- /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */\r
- }\r
-\r
- /* write output */\r
- *dst = out;\r
-\r
- /* return num of signbits of out = 1/in value */\r
- return (signBits + 1);\r
- }\r
-\r
-\r
-/*\r
- * @brief C custom defined intrinsic function for M3 and M0 processors\r
- */\r
-#if !defined (ARM_MATH_DSP)\r
-\r
- /*\r
- * @brief C custom defined QADD8 for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s, t, u;\r
-\r
- r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\r
- s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\r
- t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;\r
- u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;\r
-\r
- return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QSUB8 for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s, t, u;\r
-\r
- r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\r
- s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\r
- t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;\r
- u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;\r
-\r
- return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QADD16 for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
-/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */\r
- q31_t r = 0, s = 0;\r
-\r
- r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
- s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SHADD16 for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
- s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QSUB16 for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
- s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SHSUB16 for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
- s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QASX for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
- s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SHASX for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
- s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QSAX for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
- s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SHSAX for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
- s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMUSDX for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -\r
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));\r
- }\r
-\r
- /*\r
- * @brief C custom defined SMUADX for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +\r
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QADD for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE int32_t __QADD(\r
- int32_t x,\r
- int32_t y)\r
- {\r
- return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QSUB for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(\r
- int32_t x,\r
- int32_t y)\r
- {\r
- return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMLAD for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(\r
- uint32_t x,\r
- uint32_t y,\r
- uint32_t sum)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +\r
- ( ((q31_t)sum ) ) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMLADX for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(\r
- uint32_t x,\r
- uint32_t y,\r
- uint32_t sum)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +\r
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +\r
- ( ((q31_t)sum ) ) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMLSDX for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(\r
- uint32_t x,\r
- uint32_t y,\r
- uint32_t sum)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -\r
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +\r
- ( ((q31_t)sum ) ) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMLALD for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(\r
- uint32_t x,\r
- uint32_t y,\r
- uint64_t sum)\r
- {\r
-/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */\r
- return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +\r
- ( ((q63_t)sum ) ) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMLALDX for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(\r
- uint32_t x,\r
- uint32_t y,\r
- uint64_t sum)\r
- {\r
-/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */\r
- return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +\r
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +\r
- ( ((q63_t)sum ) ) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMUAD for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMUSD for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -\r
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SXTB16 for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(\r
- uint32_t x)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |\r
- ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));\r
- }\r
-\r
- /*\r
- * @brief C custom defined SMMLA for M3 and M0 processors\r
- */\r
- CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(\r
- int32_t x,\r
- int32_t y,\r
- int32_t sum)\r
- {\r
- return (sum + (int32_t) (((int64_t) x * y) >> 32));\r
- }\r
-\r
-#endif /* !defined (ARM_MATH_DSP) */\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q7 FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
- q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- } arm_fir_instance_q7;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- } arm_fir_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- } arm_fir_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- } arm_fir_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q7 FIR filter.\r
- * @param[in] S points to an instance of the Q7 FIR filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_q7(\r
- const arm_fir_instance_q7 * S,\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q7 FIR filter.\r
- * @param[in,out] S points to an instance of the Q7 FIR structure.\r
- * @param[in] numTaps Number of filter coefficients in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of samples that are processed.\r
- */\r
- void arm_fir_init_q7(\r
- arm_fir_instance_q7 * S,\r
- uint16_t numTaps,\r
- q7_t * pCoeffs,\r
- q7_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR filter.\r
- * @param[in] S points to an instance of the Q15 FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_q15(\r
- const arm_fir_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.\r
- * @param[in] S points to an instance of the Q15 FIR filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_fast_q15(\r
- const arm_fir_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 FIR filter.\r
- * @param[in,out] S points to an instance of the Q15 FIR filter structure.\r
- * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of samples that are processed at a time.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if\r
- * <code>numTaps</code> is not a supported value.\r
- */\r
- arm_status arm_fir_init_q15(\r
- arm_fir_instance_q15 * S,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR filter.\r
- * @param[in] S points to an instance of the Q31 FIR filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_q31(\r
- const arm_fir_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.\r
- * @param[in] S points to an instance of the Q31 FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_fast_q31(\r
- const arm_fir_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 FIR filter.\r
- * @param[in,out] S points to an instance of the Q31 FIR structure.\r
- * @param[in] numTaps Number of filter coefficients in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of samples that are processed at a time.\r
- */\r
- void arm_fir_init_q31(\r
- arm_fir_instance_q31 * S,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point FIR filter.\r
- * @param[in] S points to an instance of the floating-point FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_f32(\r
- const arm_fir_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point FIR filter.\r
- * @param[in,out] S points to an instance of the floating-point FIR filter structure.\r
- * @param[in] numTaps Number of filter coefficients in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of samples that are processed at a time.\r
- */\r
- void arm_fir_init_f32(\r
- arm_fir_instance_f32 * S,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
- q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
- int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
- } arm_biquad_casd_df1_inst_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
- q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
- uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
- } arm_biquad_casd_df1_inst_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
- float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
- } arm_biquad_casd_df1_inst_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 Biquad cascade filter.\r
- * @param[in] S points to an instance of the Q15 Biquad cascade structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df1_q15(\r
- const arm_biquad_casd_df1_inst_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 Biquad cascade filter.\r
- * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
- */\r
- void arm_biquad_cascade_df1_init_q15(\r
- arm_biquad_casd_df1_inst_q15 * S,\r
- uint8_t numStages,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- int8_t postShift);\r
-\r
-\r
- /**\r
- * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
- * @param[in] S points to an instance of the Q15 Biquad cascade structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df1_fast_q15(\r
- const arm_biquad_casd_df1_inst_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 Biquad cascade filter\r
- * @param[in] S points to an instance of the Q31 Biquad cascade structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df1_q31(\r
- const arm_biquad_casd_df1_inst_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
- * @param[in] S points to an instance of the Q31 Biquad cascade structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df1_fast_q31(\r
- const arm_biquad_casd_df1_inst_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 Biquad cascade filter.\r
- * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
- */\r
- void arm_biquad_cascade_df1_init_q31(\r
- arm_biquad_casd_df1_inst_q31 * S,\r
- uint8_t numStages,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- int8_t postShift);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point Biquad cascade filter.\r
- * @param[in] S points to an instance of the floating-point Biquad cascade structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df1_f32(\r
- const arm_biquad_casd_df1_inst_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point Biquad cascade filter.\r
- * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- */\r
- void arm_biquad_cascade_df1_init_f32(\r
- arm_biquad_casd_df1_inst_f32 * S,\r
- uint8_t numStages,\r
- float32_t * pCoeffs,\r
- float32_t * pState);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point matrix structure.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows of the matrix. */\r
- uint16_t numCols; /**< number of columns of the matrix. */\r
- float32_t *pData; /**< points to the data of the matrix. */\r
- } arm_matrix_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point matrix structure.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows of the matrix. */\r
- uint16_t numCols; /**< number of columns of the matrix. */\r
- float64_t *pData; /**< points to the data of the matrix. */\r
- } arm_matrix_instance_f64;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 matrix structure.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows of the matrix. */\r
- uint16_t numCols; /**< number of columns of the matrix. */\r
- q15_t *pData; /**< points to the data of the matrix. */\r
- } arm_matrix_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 matrix structure.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows of the matrix. */\r
- uint16_t numCols; /**< number of columns of the matrix. */\r
- q31_t *pData; /**< points to the data of the matrix. */\r
- } arm_matrix_instance_q31;\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix addition.\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_add_f32(\r
- const arm_matrix_instance_f32 * pSrcA,\r
- const arm_matrix_instance_f32 * pSrcB,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix addition.\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_add_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix addition.\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_add_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Floating-point, complex, matrix multiplication.\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_cmplx_mult_f32(\r
- const arm_matrix_instance_f32 * pSrcA,\r
- const arm_matrix_instance_f32 * pSrcB,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15, complex, matrix multiplication.\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_cmplx_mult_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst,\r
- q15_t * pScratch);\r
-\r
-\r
- /**\r
- * @brief Q31, complex, matrix multiplication.\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_cmplx_mult_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix transpose.\r
- * @param[in] pSrc points to the input matrix\r
- * @param[out] pDst points to the output matrix\r
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_trans_f32(\r
- const arm_matrix_instance_f32 * pSrc,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix transpose.\r
- * @param[in] pSrc points to the input matrix\r
- * @param[out] pDst points to the output matrix\r
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_trans_q15(\r
- const arm_matrix_instance_q15 * pSrc,\r
- arm_matrix_instance_q15 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix transpose.\r
- * @param[in] pSrc points to the input matrix\r
- * @param[out] pDst points to the output matrix\r
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_trans_q31(\r
- const arm_matrix_instance_q31 * pSrc,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix multiplication\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_mult_f32(\r
- const arm_matrix_instance_f32 * pSrcA,\r
- const arm_matrix_instance_f32 * pSrcB,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix multiplication\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @param[in] pState points to the array for storing intermediate results\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_mult_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst,\r
- q15_t * pState);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @param[in] pState points to the array for storing intermediate results\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_mult_fast_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst,\r
- q15_t * pState);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix multiplication\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_mult_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_mult_fast_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix subtraction\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_sub_f32(\r
- const arm_matrix_instance_f32 * pSrcA,\r
- const arm_matrix_instance_f32 * pSrcB,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix subtraction\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_sub_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix subtraction\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_sub_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix scaling.\r
- * @param[in] pSrc points to the input matrix\r
- * @param[in] scale scale factor\r
- * @param[out] pDst points to the output matrix\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_scale_f32(\r
- const arm_matrix_instance_f32 * pSrc,\r
- float32_t scale,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix scaling.\r
- * @param[in] pSrc points to input matrix\r
- * @param[in] scaleFract fractional portion of the scale factor\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] pDst points to output matrix\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_scale_q15(\r
- const arm_matrix_instance_q15 * pSrc,\r
- q15_t scaleFract,\r
- int32_t shift,\r
- arm_matrix_instance_q15 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix scaling.\r
- * @param[in] pSrc points to input matrix\r
- * @param[in] scaleFract fractional portion of the scale factor\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_scale_q31(\r
- const arm_matrix_instance_q31 * pSrc,\r
- q31_t scaleFract,\r
- int32_t shift,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix initialization.\r
- * @param[in,out] S points to an instance of the floating-point matrix structure.\r
- * @param[in] nRows number of rows in the matrix.\r
- * @param[in] nColumns number of columns in the matrix.\r
- * @param[in] pData points to the matrix data array.\r
- */\r
- void arm_mat_init_q31(\r
- arm_matrix_instance_q31 * S,\r
- uint16_t nRows,\r
- uint16_t nColumns,\r
- q31_t * pData);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix initialization.\r
- * @param[in,out] S points to an instance of the floating-point matrix structure.\r
- * @param[in] nRows number of rows in the matrix.\r
- * @param[in] nColumns number of columns in the matrix.\r
- * @param[in] pData points to the matrix data array.\r
- */\r
- void arm_mat_init_q15(\r
- arm_matrix_instance_q15 * S,\r
- uint16_t nRows,\r
- uint16_t nColumns,\r
- q15_t * pData);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix initialization.\r
- * @param[in,out] S points to an instance of the floating-point matrix structure.\r
- * @param[in] nRows number of rows in the matrix.\r
- * @param[in] nColumns number of columns in the matrix.\r
- * @param[in] pData points to the matrix data array.\r
- */\r
- void arm_mat_init_f32(\r
- arm_matrix_instance_f32 * S,\r
- uint16_t nRows,\r
- uint16_t nColumns,\r
- float32_t * pData);\r
-\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 PID Control.\r
- */\r
- typedef struct\r
- {\r
- q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
-#if !defined (ARM_MATH_DSP)\r
- q15_t A1;\r
- q15_t A2;\r
-#else\r
- q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/\r
-#endif\r
- q15_t state[3]; /**< The state array of length 3. */\r
- q15_t Kp; /**< The proportional gain. */\r
- q15_t Ki; /**< The integral gain. */\r
- q15_t Kd; /**< The derivative gain. */\r
- } arm_pid_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 PID Control.\r
- */\r
- typedef struct\r
- {\r
- q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
- q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
- q31_t A2; /**< The derived gain, A2 = Kd . */\r
- q31_t state[3]; /**< The state array of length 3. */\r
- q31_t Kp; /**< The proportional gain. */\r
- q31_t Ki; /**< The integral gain. */\r
- q31_t Kd; /**< The derivative gain. */\r
- } arm_pid_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point PID Control.\r
- */\r
- typedef struct\r
- {\r
- float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
- float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
- float32_t A2; /**< The derived gain, A2 = Kd . */\r
- float32_t state[3]; /**< The state array of length 3. */\r
- float32_t Kp; /**< The proportional gain. */\r
- float32_t Ki; /**< The integral gain. */\r
- float32_t Kd; /**< The derivative gain. */\r
- } arm_pid_instance_f32;\r
-\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point PID Control.\r
- * @param[in,out] S points to an instance of the PID structure.\r
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
- */\r
- void arm_pid_init_f32(\r
- arm_pid_instance_f32 * S,\r
- int32_t resetStateFlag);\r
-\r
-\r
- /**\r
- * @brief Reset function for the floating-point PID Control.\r
- * @param[in,out] S is an instance of the floating-point PID Control structure\r
- */\r
- void arm_pid_reset_f32(\r
- arm_pid_instance_f32 * S);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 PID Control.\r
- * @param[in,out] S points to an instance of the Q15 PID structure.\r
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
- */\r
- void arm_pid_init_q31(\r
- arm_pid_instance_q31 * S,\r
- int32_t resetStateFlag);\r
-\r
-\r
- /**\r
- * @brief Reset function for the Q31 PID Control.\r
- * @param[in,out] S points to an instance of the Q31 PID Control structure\r
- */\r
-\r
- void arm_pid_reset_q31(\r
- arm_pid_instance_q31 * S);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 PID Control.\r
- * @param[in,out] S points to an instance of the Q15 PID structure.\r
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
- */\r
- void arm_pid_init_q15(\r
- arm_pid_instance_q15 * S,\r
- int32_t resetStateFlag);\r
-\r
-\r
- /**\r
- * @brief Reset function for the Q15 PID Control.\r
- * @param[in,out] S points to an instance of the q15 PID Control structure\r
- */\r
- void arm_pid_reset_q15(\r
- arm_pid_instance_q15 * S);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point Linear Interpolate function.\r
- */\r
- typedef struct\r
- {\r
- uint32_t nValues; /**< nValues */\r
- float32_t x1; /**< x1 */\r
- float32_t xSpacing; /**< xSpacing */\r
- float32_t *pYData; /**< pointer to the table of Y values */\r
- } arm_linear_interp_instance_f32;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point bilinear interpolation function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows in the data table. */\r
- uint16_t numCols; /**< number of columns in the data table. */\r
- float32_t *pData; /**< points to the data table. */\r
- } arm_bilinear_interp_instance_f32;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 bilinear interpolation function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows in the data table. */\r
- uint16_t numCols; /**< number of columns in the data table. */\r
- q31_t *pData; /**< points to the data table. */\r
- } arm_bilinear_interp_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 bilinear interpolation function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows in the data table. */\r
- uint16_t numCols; /**< number of columns in the data table. */\r
- q15_t *pData; /**< points to the data table. */\r
- } arm_bilinear_interp_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 bilinear interpolation function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows in the data table. */\r
- uint16_t numCols; /**< number of columns in the data table. */\r
- q7_t *pData; /**< points to the data table. */\r
- } arm_bilinear_interp_instance_q7;\r
-\r
-\r
- /**\r
- * @brief Q7 vector multiplication.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_mult_q7(\r
- q7_t * pSrcA,\r
- q7_t * pSrcB,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q15 vector multiplication.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_mult_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q31 vector multiplication.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_mult_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Floating-point vector multiplication.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_mult_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- } arm_cfft_radix2_instance_q15;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix2_init_q15(\r
- arm_cfft_radix2_instance_q15 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix2_q15(\r
- const arm_cfft_radix2_instance_q15 * S,\r
- q15_t * pSrc);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- } arm_cfft_radix4_instance_q15;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix4_init_q15(\r
- arm_cfft_radix4_instance_q15 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix4_q15(\r
- const arm_cfft_radix4_instance_q15 * S,\r
- q15_t * pSrc);\r
-\r
- /**\r
- * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- q31_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- } arm_cfft_radix2_instance_q31;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix2_init_q31(\r
- arm_cfft_radix2_instance_q31 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix2_q31(\r
- const arm_cfft_radix2_instance_q31 * S,\r
- q31_t * pSrc);\r
-\r
- /**\r
- * @brief Instance structure for the Q31 CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- } arm_cfft_radix4_instance_q31;\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix4_q31(\r
- const arm_cfft_radix4_instance_q31 * S,\r
- q31_t * pSrc);\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix4_init_q31(\r
- arm_cfft_radix4_instance_q31 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- float32_t onebyfftLen; /**< value of 1/fftLen. */\r
- } arm_cfft_radix2_instance_f32;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix2_init_f32(\r
- arm_cfft_radix2_instance_f32 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix2_f32(\r
- const arm_cfft_radix2_instance_f32 * S,\r
- float32_t * pSrc);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- float32_t onebyfftLen; /**< value of 1/fftLen. */\r
- } arm_cfft_radix4_instance_f32;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix4_init_f32(\r
- arm_cfft_radix4_instance_f32 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix4_f32(\r
- const arm_cfft_radix4_instance_f32 * S,\r
- float32_t * pSrc);\r
-\r
- /**\r
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- const q15_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t bitRevLength; /**< bit reversal table length. */\r
- } arm_cfft_instance_q15;\r
-\r
-void arm_cfft_q15(\r
- const arm_cfft_instance_q15 * S,\r
- q15_t * p1,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
- /**\r
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- const q31_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t bitRevLength; /**< bit reversal table length. */\r
- } arm_cfft_instance_q31;\r
-\r
-void arm_cfft_q31(\r
- const arm_cfft_instance_q31 * S,\r
- q31_t * p1,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- const float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t bitRevLength; /**< bit reversal table length. */\r
- } arm_cfft_instance_f32;\r
-\r
- void arm_cfft_f32(\r
- const arm_cfft_instance_f32 * S,\r
- float32_t * p1,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
- /**\r
- * @brief Instance structure for the Q15 RFFT/RIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint32_t fftLenReal; /**< length of the real FFT. */\r
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
- q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
- const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_rfft_instance_q15;\r
-\r
- arm_status arm_rfft_init_q15(\r
- arm_rfft_instance_q15 * S,\r
- uint32_t fftLenReal,\r
- uint32_t ifftFlagR,\r
- uint32_t bitReverseFlag);\r
-\r
- void arm_rfft_q15(\r
- const arm_rfft_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst);\r
-\r
- /**\r
- * @brief Instance structure for the Q31 RFFT/RIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint32_t fftLenReal; /**< length of the real FFT. */\r
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
- q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
- const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_rfft_instance_q31;\r
-\r
- arm_status arm_rfft_init_q31(\r
- arm_rfft_instance_q31 * S,\r
- uint32_t fftLenReal,\r
- uint32_t ifftFlagR,\r
- uint32_t bitReverseFlag);\r
-\r
- void arm_rfft_q31(\r
- const arm_rfft_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint32_t fftLenReal; /**< length of the real FFT. */\r
- uint16_t fftLenBy2; /**< length of the complex FFT. */\r
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
- float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_rfft_instance_f32;\r
-\r
- arm_status arm_rfft_init_f32(\r
- arm_rfft_instance_f32 * S,\r
- arm_cfft_radix4_instance_f32 * S_CFFT,\r
- uint32_t fftLenReal,\r
- uint32_t ifftFlagR,\r
- uint32_t bitReverseFlag);\r
-\r
- void arm_rfft_f32(\r
- const arm_rfft_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
- */\r
-typedef struct\r
- {\r
- arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */\r
- uint16_t fftLenRFFT; /**< length of the real sequence */\r
- float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */\r
- } arm_rfft_fast_instance_f32 ;\r
-\r
-arm_status arm_rfft_fast_init_f32 (\r
- arm_rfft_fast_instance_f32 * S,\r
- uint16_t fftLen);\r
-\r
-void arm_rfft_fast_f32(\r
- arm_rfft_fast_instance_f32 * S,\r
- float32_t * p, float32_t * pOut,\r
- uint8_t ifftFlag);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point DCT4/IDCT4 function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t N; /**< length of the DCT4. */\r
- uint16_t Nby2; /**< half of the length of the DCT4. */\r
- float32_t normalize; /**< normalizing factor. */\r
- float32_t *pTwiddle; /**< points to the twiddle factor table. */\r
- float32_t *pCosFactor; /**< points to the cosFactor table. */\r
- arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */\r
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_dct4_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point DCT4/IDCT4.\r
- * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.\r
- * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.\r
- * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.\r
- * @param[in] N length of the DCT4.\r
- * @param[in] Nby2 half of the length of the DCT4.\r
- * @param[in] normalize normalizing factor.\r
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.\r
- */\r
- arm_status arm_dct4_init_f32(\r
- arm_dct4_instance_f32 * S,\r
- arm_rfft_instance_f32 * S_RFFT,\r
- arm_cfft_radix4_instance_f32 * S_CFFT,\r
- uint16_t N,\r
- uint16_t Nby2,\r
- float32_t normalize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point DCT4/IDCT4.\r
- * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.\r
- * @param[in] pState points to state buffer.\r
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.\r
- */\r
- void arm_dct4_f32(\r
- const arm_dct4_instance_f32 * S,\r
- float32_t * pState,\r
- float32_t * pInlineBuffer);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q31 DCT4/IDCT4 function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t N; /**< length of the DCT4. */\r
- uint16_t Nby2; /**< half of the length of the DCT4. */\r
- q31_t normalize; /**< normalizing factor. */\r
- q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
- q31_t *pCosFactor; /**< points to the cosFactor table. */\r
- arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */\r
- arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_dct4_instance_q31;\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 DCT4/IDCT4.\r
- * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.\r
- * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure\r
- * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure\r
- * @param[in] N length of the DCT4.\r
- * @param[in] Nby2 half of the length of the DCT4.\r
- * @param[in] normalize normalizing factor.\r
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
- */\r
- arm_status arm_dct4_init_q31(\r
- arm_dct4_instance_q31 * S,\r
- arm_rfft_instance_q31 * S_RFFT,\r
- arm_cfft_radix4_instance_q31 * S_CFFT,\r
- uint16_t N,\r
- uint16_t Nby2,\r
- q31_t normalize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 DCT4/IDCT4.\r
- * @param[in] S points to an instance of the Q31 DCT4 structure.\r
- * @param[in] pState points to state buffer.\r
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.\r
- */\r
- void arm_dct4_q31(\r
- const arm_dct4_instance_q31 * S,\r
- q31_t * pState,\r
- q31_t * pInlineBuffer);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 DCT4/IDCT4 function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t N; /**< length of the DCT4. */\r
- uint16_t Nby2; /**< half of the length of the DCT4. */\r
- q15_t normalize; /**< normalizing factor. */\r
- q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
- q15_t *pCosFactor; /**< points to the cosFactor table. */\r
- arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */\r
- arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_dct4_instance_q15;\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 DCT4/IDCT4.\r
- * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.\r
- * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.\r
- * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.\r
- * @param[in] N length of the DCT4.\r
- * @param[in] Nby2 half of the length of the DCT4.\r
- * @param[in] normalize normalizing factor.\r
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
- */\r
- arm_status arm_dct4_init_q15(\r
- arm_dct4_instance_q15 * S,\r
- arm_rfft_instance_q15 * S_RFFT,\r
- arm_cfft_radix4_instance_q15 * S_CFFT,\r
- uint16_t N,\r
- uint16_t Nby2,\r
- q15_t normalize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 DCT4/IDCT4.\r
- * @param[in] S points to an instance of the Q15 DCT4 structure.\r
- * @param[in] pState points to state buffer.\r
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.\r
- */\r
- void arm_dct4_q15(\r
- const arm_dct4_instance_q15 * S,\r
- q15_t * pState,\r
- q15_t * pInlineBuffer);\r
-\r
-\r
- /**\r
- * @brief Floating-point vector addition.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_add_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q7 vector addition.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_add_q7(\r
- q7_t * pSrcA,\r
- q7_t * pSrcB,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q15 vector addition.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_add_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q31 vector addition.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_add_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Floating-point vector subtraction.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_sub_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q7 vector subtraction.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_sub_q7(\r
- q7_t * pSrcA,\r
- q7_t * pSrcB,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q15 vector subtraction.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_sub_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q31 vector subtraction.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_sub_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Multiplies a floating-point vector by a scalar.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] scale scale factor to be applied\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_scale_f32(\r
- float32_t * pSrc,\r
- float32_t scale,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Multiplies a Q7 vector by a scalar.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] scaleFract fractional portion of the scale value\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_scale_q7(\r
- q7_t * pSrc,\r
- q7_t scaleFract,\r
- int8_t shift,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Multiplies a Q15 vector by a scalar.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] scaleFract fractional portion of the scale value\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_scale_q15(\r
- q15_t * pSrc,\r
- q15_t scaleFract,\r
- int8_t shift,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Multiplies a Q31 vector by a scalar.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] scaleFract fractional portion of the scale value\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_scale_q31(\r
- q31_t * pSrc,\r
- q31_t scaleFract,\r
- int8_t shift,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q7 vector absolute value.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[out] pDst points to the output buffer\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_abs_q7(\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Floating-point vector absolute value.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[out] pDst points to the output buffer\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_abs_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q15 vector absolute value.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[out] pDst points to the output buffer\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_abs_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q31 vector absolute value.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[out] pDst points to the output buffer\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_abs_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Dot product of floating-point vectors.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @param[out] result output result returned here\r
- */\r
- void arm_dot_prod_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- uint32_t blockSize,\r
- float32_t * result);\r
-\r
-\r
- /**\r
- * @brief Dot product of Q7 vectors.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @param[out] result output result returned here\r
- */\r
- void arm_dot_prod_q7(\r
- q7_t * pSrcA,\r
- q7_t * pSrcB,\r
- uint32_t blockSize,\r
- q31_t * result);\r
-\r
-\r
- /**\r
- * @brief Dot product of Q15 vectors.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @param[out] result output result returned here\r
- */\r
- void arm_dot_prod_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- uint32_t blockSize,\r
- q63_t * result);\r
-\r
-\r
- /**\r
- * @brief Dot product of Q31 vectors.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @param[out] result output result returned here\r
- */\r
- void arm_dot_prod_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- uint32_t blockSize,\r
- q63_t * result);\r
-\r
-\r
- /**\r
- * @brief Shifts the elements of a Q7 vector a specified number of bits.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_shift_q7(\r
- q7_t * pSrc,\r
- int8_t shiftBits,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Shifts the elements of a Q15 vector a specified number of bits.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_shift_q15(\r
- q15_t * pSrc,\r
- int8_t shiftBits,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Shifts the elements of a Q31 vector a specified number of bits.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_shift_q31(\r
- q31_t * pSrc,\r
- int8_t shiftBits,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Adds a constant offset to a floating-point vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] offset is the offset to be added\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_offset_f32(\r
- float32_t * pSrc,\r
- float32_t offset,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Adds a constant offset to a Q7 vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] offset is the offset to be added\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_offset_q7(\r
- q7_t * pSrc,\r
- q7_t offset,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Adds a constant offset to a Q15 vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] offset is the offset to be added\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_offset_q15(\r
- q15_t * pSrc,\r
- q15_t offset,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Adds a constant offset to a Q31 vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] offset is the offset to be added\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_offset_q31(\r
- q31_t * pSrc,\r
- q31_t offset,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Negates the elements of a floating-point vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_negate_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Negates the elements of a Q7 vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_negate_q7(\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Negates the elements of a Q15 vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_negate_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Negates the elements of a Q31 vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_negate_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Copies the elements of a floating-point vector.\r
- * @param[in] pSrc input pointer\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_copy_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Copies the elements of a Q7 vector.\r
- * @param[in] pSrc input pointer\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_copy_q7(\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Copies the elements of a Q15 vector.\r
- * @param[in] pSrc input pointer\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_copy_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Copies the elements of a Q31 vector.\r
- * @param[in] pSrc input pointer\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_copy_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Fills a constant value into a floating-point vector.\r
- * @param[in] value input value to be filled\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_fill_f32(\r
- float32_t value,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Fills a constant value into a Q7 vector.\r
- * @param[in] value input value to be filled\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_fill_q7(\r
- q7_t value,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Fills a constant value into a Q15 vector.\r
- * @param[in] value input value to be filled\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_fill_q15(\r
- q15_t value,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Fills a constant value into a Q31 vector.\r
- * @param[in] value input value to be filled\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_fill_q31(\r
- q31_t value,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-/**\r
- * @brief Convolution of floating-point sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
- */\r
- void arm_conv_f32(\r
- float32_t * pSrcA,\r
- uint32_t srcALen,\r
- float32_t * pSrcB,\r
- uint32_t srcBLen,\r
- float32_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q15 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
- */\r
- void arm_conv_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
-/**\r
- * @brief Convolution of Q15 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
- */\r
- void arm_conv_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- */\r
- void arm_conv_fast_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
- */\r
- void arm_conv_fast_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q31 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- */\r
- void arm_conv_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- */\r
- void arm_conv_fast_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q7 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
- */\r
- void arm_conv_opt_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q7 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- */\r
- void arm_conv_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of floating-point sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_f32(\r
- float32_t * pSrcA,\r
- uint32_t srcALen,\r
- float32_t * pSrcB,\r
- uint32_t srcBLen,\r
- float32_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q15 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q15 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_fast_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_fast_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q31 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_fast_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q7 sequences\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_opt_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
-/**\r
- * @brief Partial convolution of Q7 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 FIR decimator.\r
- */\r
- typedef struct\r
- {\r
- uint8_t M; /**< decimation factor. */\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- } arm_fir_decimate_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 FIR decimator.\r
- */\r
- typedef struct\r
- {\r
- uint8_t M; /**< decimation factor. */\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- } arm_fir_decimate_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point FIR decimator.\r
- */\r
- typedef struct\r
- {\r
- uint8_t M; /**< decimation factor. */\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- } arm_fir_decimate_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point FIR decimator.\r
- * @param[in] S points to an instance of the floating-point FIR decimator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_decimate_f32(\r
- const arm_fir_decimate_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point FIR decimator.\r
- * @param[in,out] S points to an instance of the floating-point FIR decimator structure.\r
- * @param[in] numTaps number of coefficients in the filter.\r
- * @param[in] M decimation factor.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * <code>blockSize</code> is not a multiple of <code>M</code>.\r
- */\r
- arm_status arm_fir_decimate_init_f32(\r
- arm_fir_decimate_instance_f32 * S,\r
- uint16_t numTaps,\r
- uint8_t M,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR decimator.\r
- * @param[in] S points to an instance of the Q15 FIR decimator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_decimate_q15(\r
- const arm_fir_decimate_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
- * @param[in] S points to an instance of the Q15 FIR decimator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_decimate_fast_q15(\r
- const arm_fir_decimate_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 FIR decimator.\r
- * @param[in,out] S points to an instance of the Q15 FIR decimator structure.\r
- * @param[in] numTaps number of coefficients in the filter.\r
- * @param[in] M decimation factor.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * <code>blockSize</code> is not a multiple of <code>M</code>.\r
- */\r
- arm_status arm_fir_decimate_init_q15(\r
- arm_fir_decimate_instance_q15 * S,\r
- uint16_t numTaps,\r
- uint8_t M,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR decimator.\r
- * @param[in] S points to an instance of the Q31 FIR decimator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_decimate_q31(\r
- const arm_fir_decimate_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
- * @param[in] S points to an instance of the Q31 FIR decimator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_decimate_fast_q31(\r
- arm_fir_decimate_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 FIR decimator.\r
- * @param[in,out] S points to an instance of the Q31 FIR decimator structure.\r
- * @param[in] numTaps number of coefficients in the filter.\r
- * @param[in] M decimation factor.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * <code>blockSize</code> is not a multiple of <code>M</code>.\r
- */\r
- arm_status arm_fir_decimate_init_q31(\r
- arm_fir_decimate_instance_q31 * S,\r
- uint16_t numTaps,\r
- uint8_t M,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 FIR interpolator.\r
- */\r
- typedef struct\r
- {\r
- uint8_t L; /**< upsample factor. */\r
- uint16_t phaseLength; /**< length of each polyphase filter component. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
- } arm_fir_interpolate_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 FIR interpolator.\r
- */\r
- typedef struct\r
- {\r
- uint8_t L; /**< upsample factor. */\r
- uint16_t phaseLength; /**< length of each polyphase filter component. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
- } arm_fir_interpolate_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point FIR interpolator.\r
- */\r
- typedef struct\r
- {\r
- uint8_t L; /**< upsample factor. */\r
- uint16_t phaseLength; /**< length of each polyphase filter component. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */\r
- } arm_fir_interpolate_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR interpolator.\r
- * @param[in] S points to an instance of the Q15 FIR interpolator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_interpolate_q15(\r
- const arm_fir_interpolate_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 FIR interpolator.\r
- * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.\r
- * @param[in] L upsample factor.\r
- * @param[in] numTaps number of filter coefficients in the filter.\r
- * @param[in] pCoeffs points to the filter coefficient buffer.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
- */\r
- arm_status arm_fir_interpolate_init_q15(\r
- arm_fir_interpolate_instance_q15 * S,\r
- uint8_t L,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR interpolator.\r
- * @param[in] S points to an instance of the Q15 FIR interpolator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_interpolate_q31(\r
- const arm_fir_interpolate_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 FIR interpolator.\r
- * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.\r
- * @param[in] L upsample factor.\r
- * @param[in] numTaps number of filter coefficients in the filter.\r
- * @param[in] pCoeffs points to the filter coefficient buffer.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
- */\r
- arm_status arm_fir_interpolate_init_q31(\r
- arm_fir_interpolate_instance_q31 * S,\r
- uint8_t L,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point FIR interpolator.\r
- * @param[in] S points to an instance of the floating-point FIR interpolator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_interpolate_f32(\r
- const arm_fir_interpolate_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point FIR interpolator.\r
- * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.\r
- * @param[in] L upsample factor.\r
- * @param[in] numTaps number of filter coefficients in the filter.\r
- * @param[in] pCoeffs points to the filter coefficient buffer.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
- */\r
- arm_status arm_fir_interpolate_init_f32(\r
- arm_fir_interpolate_instance_f32 * S,\r
- uint8_t L,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the high precision Q31 Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
- q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
- uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */\r
- } arm_biquad_cas_df1_32x64_ins_q31;\r
-\r
-\r
- /**\r
- * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cas_df1_32x64_q31(\r
- const arm_biquad_cas_df1_32x64_ins_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format\r
- */\r
- void arm_biquad_cas_df1_32x64_init_q31(\r
- arm_biquad_cas_df1_32x64_ins_q31 * S,\r
- uint8_t numStages,\r
- q31_t * pCoeffs,\r
- q63_t * pState,\r
- uint8_t postShift);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
- float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
- } arm_biquad_cascade_df2T_instance_f32;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
- float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
- } arm_biquad_cascade_stereo_df2T_instance_f32;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
- float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
- } arm_biquad_cascade_df2T_instance_f64;\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in] S points to an instance of the filter data structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df2T_f32(\r
- const arm_biquad_cascade_df2T_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels\r
- * @param[in] S points to an instance of the filter data structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_stereo_df2T_f32(\r
- const arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in] S points to an instance of the filter data structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df2T_f64(\r
- const arm_biquad_cascade_df2T_instance_f64 * S,\r
- float64_t * pSrc,\r
- float64_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in,out] S points to an instance of the filter data structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- */\r
- void arm_biquad_cascade_df2T_init_f32(\r
- arm_biquad_cascade_df2T_instance_f32 * S,\r
- uint8_t numStages,\r
- float32_t * pCoeffs,\r
- float32_t * pState);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in,out] S points to an instance of the filter data structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- */\r
- void arm_biquad_cascade_stereo_df2T_init_f32(\r
- arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r
- uint8_t numStages,\r
- float32_t * pCoeffs,\r
- float32_t * pState);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in,out] S points to an instance of the filter data structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- */\r
- void arm_biquad_cascade_df2T_init_f64(\r
- arm_biquad_cascade_df2T_instance_f64 * S,\r
- uint8_t numStages,\r
- float64_t * pCoeffs,\r
- float64_t * pState);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 FIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of filter stages. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
- } arm_fir_lattice_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 FIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of filter stages. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
- } arm_fir_lattice_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point FIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of filter stages. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
- } arm_fir_lattice_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 FIR lattice filter.\r
- * @param[in] S points to an instance of the Q15 FIR lattice structure.\r
- * @param[in] numStages number of filter stages.\r
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.\r
- * @param[in] pState points to the state buffer. The array is of length numStages.\r
- */\r
- void arm_fir_lattice_init_q15(\r
- arm_fir_lattice_instance_q15 * S,\r
- uint16_t numStages,\r
- q15_t * pCoeffs,\r
- q15_t * pState);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR lattice filter.\r
- * @param[in] S points to an instance of the Q15 FIR lattice structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_lattice_q15(\r
- const arm_fir_lattice_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 FIR lattice filter.\r
- * @param[in] S points to an instance of the Q31 FIR lattice structure.\r
- * @param[in] numStages number of filter stages.\r
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.\r
- * @param[in] pState points to the state buffer. The array is of length numStages.\r
- */\r
- void arm_fir_lattice_init_q31(\r
- arm_fir_lattice_instance_q31 * S,\r
- uint16_t numStages,\r
- q31_t * pCoeffs,\r
- q31_t * pState);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR lattice filter.\r
- * @param[in] S points to an instance of the Q31 FIR lattice structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_lattice_q31(\r
- const arm_fir_lattice_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-/**\r
- * @brief Initialization function for the floating-point FIR lattice filter.\r
- * @param[in] S points to an instance of the floating-point FIR lattice structure.\r
- * @param[in] numStages number of filter stages.\r
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.\r
- * @param[in] pState points to the state buffer. The array is of length numStages.\r
- */\r
- void arm_fir_lattice_init_f32(\r
- arm_fir_lattice_instance_f32 * S,\r
- uint16_t numStages,\r
- float32_t * pCoeffs,\r
- float32_t * pState);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point FIR lattice filter.\r
- * @param[in] S points to an instance of the floating-point FIR lattice structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_lattice_f32(\r
- const arm_fir_lattice_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 IIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of stages in the filter. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
- q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
- q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
- } arm_iir_lattice_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 IIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of stages in the filter. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
- q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
- q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
- } arm_iir_lattice_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point IIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of stages in the filter. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
- float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
- float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
- } arm_iir_lattice_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point IIR lattice filter.\r
- * @param[in] S points to an instance of the floating-point IIR lattice structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_iir_lattice_f32(\r
- const arm_iir_lattice_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point IIR lattice filter.\r
- * @param[in] S points to an instance of the floating-point IIR lattice structure.\r
- * @param[in] numStages number of stages in the filter.\r
- * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
- * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
- * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_iir_lattice_init_f32(\r
- arm_iir_lattice_instance_f32 * S,\r
- uint16_t numStages,\r
- float32_t * pkCoeffs,\r
- float32_t * pvCoeffs,\r
- float32_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 IIR lattice filter.\r
- * @param[in] S points to an instance of the Q31 IIR lattice structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_iir_lattice_q31(\r
- const arm_iir_lattice_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 IIR lattice filter.\r
- * @param[in] S points to an instance of the Q31 IIR lattice structure.\r
- * @param[in] numStages number of stages in the filter.\r
- * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
- * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
- * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_iir_lattice_init_q31(\r
- arm_iir_lattice_instance_q31 * S,\r
- uint16_t numStages,\r
- q31_t * pkCoeffs,\r
- q31_t * pvCoeffs,\r
- q31_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 IIR lattice filter.\r
- * @param[in] S points to an instance of the Q15 IIR lattice structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_iir_lattice_q15(\r
- const arm_iir_lattice_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-/**\r
- * @brief Initialization function for the Q15 IIR lattice filter.\r
- * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.\r
- * @param[in] numStages number of stages in the filter.\r
- * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.\r
- * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.\r
- * @param[in] pState points to state buffer. The array is of length numStages+blockSize.\r
- * @param[in] blockSize number of samples to process per call.\r
- */\r
- void arm_iir_lattice_init_q15(\r
- arm_iir_lattice_instance_q15 * S,\r
- uint16_t numStages,\r
- q15_t * pkCoeffs,\r
- q15_t * pvCoeffs,\r
- q15_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- float32_t mu; /**< step size that controls filter coefficient updates. */\r
- } arm_lms_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for floating-point LMS filter.\r
- * @param[in] S points to an instance of the floating-point LMS filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[in] pRef points to the block of reference data.\r
- * @param[out] pOut points to the block of output data.\r
- * @param[out] pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_f32(\r
- const arm_lms_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pRef,\r
- float32_t * pOut,\r
- float32_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for floating-point LMS filter.\r
- * @param[in] S points to an instance of the floating-point LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] pCoeffs points to the coefficient buffer.\r
- * @param[in] pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_init_f32(\r
- arm_lms_instance_f32 * S,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- float32_t mu,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- q15_t mu; /**< step size that controls filter coefficient updates. */\r
- uint32_t postShift; /**< bit shift applied to coefficients. */\r
- } arm_lms_instance_q15;\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 LMS filter.\r
- * @param[in] S points to an instance of the Q15 LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] pCoeffs points to the coefficient buffer.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- * @param[in] postShift bit shift applied to coefficients.\r
- */\r
- void arm_lms_init_q15(\r
- arm_lms_instance_q15 * S,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- q15_t mu,\r
- uint32_t blockSize,\r
- uint32_t postShift);\r
-\r
-\r
- /**\r
- * @brief Processing function for Q15 LMS filter.\r
- * @param[in] S points to an instance of the Q15 LMS filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[in] pRef points to the block of reference data.\r
- * @param[out] pOut points to the block of output data.\r
- * @param[out] pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_q15(\r
- const arm_lms_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pRef,\r
- q15_t * pOut,\r
- q15_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q31 LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- q31_t mu; /**< step size that controls filter coefficient updates. */\r
- uint32_t postShift; /**< bit shift applied to coefficients. */\r
- } arm_lms_instance_q31;\r
-\r
-\r
- /**\r
- * @brief Processing function for Q31 LMS filter.\r
- * @param[in] S points to an instance of the Q15 LMS filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[in] pRef points to the block of reference data.\r
- * @param[out] pOut points to the block of output data.\r
- * @param[out] pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_q31(\r
- const arm_lms_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pRef,\r
- q31_t * pOut,\r
- q31_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for Q31 LMS filter.\r
- * @param[in] S points to an instance of the Q31 LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] pCoeffs points to coefficient buffer.\r
- * @param[in] pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- * @param[in] postShift bit shift applied to coefficients.\r
- */\r
- void arm_lms_init_q31(\r
- arm_lms_instance_q31 * S,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- q31_t mu,\r
- uint32_t blockSize,\r
- uint32_t postShift);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point normalized LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- float32_t mu; /**< step size that control filter coefficient updates. */\r
- float32_t energy; /**< saves previous frame energy. */\r
- float32_t x0; /**< saves previous input sample. */\r
- } arm_lms_norm_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for floating-point normalized LMS filter.\r
- * @param[in] S points to an instance of the floating-point normalized LMS filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[in] pRef points to the block of reference data.\r
- * @param[out] pOut points to the block of output data.\r
- * @param[out] pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_norm_f32(\r
- arm_lms_norm_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pRef,\r
- float32_t * pOut,\r
- float32_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for floating-point normalized LMS filter.\r
- * @param[in] S points to an instance of the floating-point LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] pCoeffs points to coefficient buffer.\r
- * @param[in] pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_norm_init_f32(\r
- arm_lms_norm_instance_f32 * S,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- float32_t mu,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q31 normalized LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- q31_t mu; /**< step size that controls filter coefficient updates. */\r
- uint8_t postShift; /**< bit shift applied to coefficients. */\r
- q31_t *recipTable; /**< points to the reciprocal initial value table. */\r
- q31_t energy; /**< saves previous frame energy. */\r
- q31_t x0; /**< saves previous input sample. */\r
- } arm_lms_norm_instance_q31;\r
-\r
-\r
- /**\r
- * @brief Processing function for Q31 normalized LMS filter.\r
- * @param[in] S points to an instance of the Q31 normalized LMS filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[in] pRef points to the block of reference data.\r
- * @param[out] pOut points to the block of output data.\r
- * @param[out] pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_norm_q31(\r
- arm_lms_norm_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pRef,\r
- q31_t * pOut,\r
- q31_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for Q31 normalized LMS filter.\r
- * @param[in] S points to an instance of the Q31 normalized LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] pCoeffs points to coefficient buffer.\r
- * @param[in] pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- * @param[in] postShift bit shift applied to coefficients.\r
- */\r
- void arm_lms_norm_init_q31(\r
- arm_lms_norm_instance_q31 * S,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- q31_t mu,\r
- uint32_t blockSize,\r
- uint8_t postShift);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 normalized LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< Number of coefficients in the filter. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- q15_t mu; /**< step size that controls filter coefficient updates. */\r
- uint8_t postShift; /**< bit shift applied to coefficients. */\r
- q15_t *recipTable; /**< Points to the reciprocal initial value table. */\r
- q15_t energy; /**< saves previous frame energy. */\r
- q15_t x0; /**< saves previous input sample. */\r
- } arm_lms_norm_instance_q15;\r
-\r
-\r
- /**\r
- * @brief Processing function for Q15 normalized LMS filter.\r
- * @param[in] S points to an instance of the Q15 normalized LMS filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[in] pRef points to the block of reference data.\r
- * @param[out] pOut points to the block of output data.\r
- * @param[out] pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_norm_q15(\r
- arm_lms_norm_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pRef,\r
- q15_t * pOut,\r
- q15_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for Q15 normalized LMS filter.\r
- * @param[in] S points to an instance of the Q15 normalized LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] pCoeffs points to coefficient buffer.\r
- * @param[in] pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- * @param[in] postShift bit shift applied to coefficients.\r
- */\r
- void arm_lms_norm_init_q15(\r
- arm_lms_norm_instance_q15 * S,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- q15_t mu,\r
- uint32_t blockSize,\r
- uint8_t postShift);\r
-\r
-\r
- /**\r
- * @brief Correlation of floating-point sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- */\r
- void arm_correlate_f32(\r
- float32_t * pSrcA,\r
- uint32_t srcALen,\r
- float32_t * pSrcB,\r
- uint32_t srcBLen,\r
- float32_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q15 sequences\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- */\r
- void arm_correlate_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- q15_t * pScratch);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q15 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- */\r
-\r
- void arm_correlate_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- */\r
-\r
- void arm_correlate_fast_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- */\r
- void arm_correlate_fast_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- q15_t * pScratch);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q31 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- */\r
- void arm_correlate_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- */\r
- void arm_correlate_fast_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q7 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
- */\r
- void arm_correlate_opt_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q7 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- */\r
- void arm_correlate_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point sparse FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
- float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
- } arm_fir_sparse_instance_f32;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 sparse FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
- q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
- } arm_fir_sparse_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 sparse FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
- q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
- } arm_fir_sparse_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q7 sparse FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
- q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
- } arm_fir_sparse_instance_q7;\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point sparse FIR filter.\r
- * @param[in] S points to an instance of the floating-point sparse FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_sparse_f32(\r
- arm_fir_sparse_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- float32_t * pScratchIn,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point sparse FIR filter.\r
- * @param[in,out] S points to an instance of the floating-point sparse FIR structure.\r
- * @param[in] numTaps number of nonzero coefficients in the filter.\r
- * @param[in] pCoeffs points to the array of filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] pTapDelay points to the array of offset times.\r
- * @param[in] maxDelay maximum offset time supported.\r
- * @param[in] blockSize number of samples that will be processed per block.\r
- */\r
- void arm_fir_sparse_init_f32(\r
- arm_fir_sparse_instance_f32 * S,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- int32_t * pTapDelay,\r
- uint16_t maxDelay,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 sparse FIR filter.\r
- * @param[in] S points to an instance of the Q31 sparse FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_sparse_q31(\r
- arm_fir_sparse_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- q31_t * pScratchIn,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 sparse FIR filter.\r
- * @param[in,out] S points to an instance of the Q31 sparse FIR structure.\r
- * @param[in] numTaps number of nonzero coefficients in the filter.\r
- * @param[in] pCoeffs points to the array of filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] pTapDelay points to the array of offset times.\r
- * @param[in] maxDelay maximum offset time supported.\r
- * @param[in] blockSize number of samples that will be processed per block.\r
- */\r
- void arm_fir_sparse_init_q31(\r
- arm_fir_sparse_instance_q31 * S,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- int32_t * pTapDelay,\r
- uint16_t maxDelay,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 sparse FIR filter.\r
- * @param[in] S points to an instance of the Q15 sparse FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
- * @param[in] pScratchOut points to a temporary buffer of size blockSize.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_sparse_q15(\r
- arm_fir_sparse_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- q15_t * pScratchIn,\r
- q31_t * pScratchOut,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 sparse FIR filter.\r
- * @param[in,out] S points to an instance of the Q15 sparse FIR structure.\r
- * @param[in] numTaps number of nonzero coefficients in the filter.\r
- * @param[in] pCoeffs points to the array of filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] pTapDelay points to the array of offset times.\r
- * @param[in] maxDelay maximum offset time supported.\r
- * @param[in] blockSize number of samples that will be processed per block.\r
- */\r
- void arm_fir_sparse_init_q15(\r
- arm_fir_sparse_instance_q15 * S,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- int32_t * pTapDelay,\r
- uint16_t maxDelay,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q7 sparse FIR filter.\r
- * @param[in] S points to an instance of the Q7 sparse FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
- * @param[in] pScratchOut points to a temporary buffer of size blockSize.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_sparse_q7(\r
- arm_fir_sparse_instance_q7 * S,\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- q7_t * pScratchIn,\r
- q31_t * pScratchOut,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q7 sparse FIR filter.\r
- * @param[in,out] S points to an instance of the Q7 sparse FIR structure.\r
- * @param[in] numTaps number of nonzero coefficients in the filter.\r
- * @param[in] pCoeffs points to the array of filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] pTapDelay points to the array of offset times.\r
- * @param[in] maxDelay maximum offset time supported.\r
- * @param[in] blockSize number of samples that will be processed per block.\r
- */\r
- void arm_fir_sparse_init_q7(\r
- arm_fir_sparse_instance_q7 * S,\r
- uint16_t numTaps,\r
- q7_t * pCoeffs,\r
- q7_t * pState,\r
- int32_t * pTapDelay,\r
- uint16_t maxDelay,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Floating-point sin_cos function.\r
- * @param[in] theta input value in degrees\r
- * @param[out] pSinVal points to the processed sine output.\r
- * @param[out] pCosVal points to the processed cos output.\r
- */\r
- void arm_sin_cos_f32(\r
- float32_t theta,\r
- float32_t * pSinVal,\r
- float32_t * pCosVal);\r
-\r
-\r
- /**\r
- * @brief Q31 sin_cos function.\r
- * @param[in] theta scaled input value in degrees\r
- * @param[out] pSinVal points to the processed sine output.\r
- * @param[out] pCosVal points to the processed cosine output.\r
- */\r
- void arm_sin_cos_q31(\r
- q31_t theta,\r
- q31_t * pSinVal,\r
- q31_t * pCosVal);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex conjugate.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- */\r
- void arm_cmplx_conj_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t numSamples);\r
-\r
- /**\r
- * @brief Q31 complex conjugate.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- */\r
- void arm_cmplx_conj_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q15 complex conjugate.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- */\r
- void arm_cmplx_conj_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex magnitude squared\r
- * @param[in] pSrc points to the complex input vector\r
- * @param[out] pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- */\r
- void arm_cmplx_mag_squared_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q31 complex magnitude squared\r
- * @param[in] pSrc points to the complex input vector\r
- * @param[out] pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- */\r
- void arm_cmplx_mag_squared_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q15 complex magnitude squared\r
- * @param[in] pSrc points to the complex input vector\r
- * @param[out] pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- */\r
- void arm_cmplx_mag_squared_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup PID PID Motor Control\r
- *\r
- * A Proportional Integral Derivative (PID) controller is a generic feedback control\r
- * loop mechanism widely used in industrial control systems.\r
- * A PID controller is the most commonly used type of feedback controller.\r
- *\r
- * This set of functions implements (PID) controllers\r
- * for Q15, Q31, and floating-point data types. The functions operate on a single sample\r
- * of data and each call to the function returns a single processed value.\r
- * <code>S</code> points to an instance of the PID control data structure. <code>in</code>\r
- * is the input sample value. The functions return the output value.\r
- *\r
- * \par Algorithm:\r
- * <pre>\r
- * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\r
- * A0 = Kp + Ki + Kd\r
- * A1 = (-Kp ) - (2 * Kd )\r
- * A2 = Kd </pre>\r
- *\r
- * \par\r
- * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant\r
- *\r
- * \par\r
- * \image html PID.gif "Proportional Integral Derivative Controller"\r
- *\r
- * \par\r
- * The PID controller calculates an "error" value as the difference between\r
- * the measured output and the reference input.\r
- * The controller attempts to minimize the error by adjusting the process control inputs.\r
- * The proportional value determines the reaction to the current error,\r
- * the integral value determines the reaction based on the sum of recent errors,\r
- * and the derivative value determines the reaction based on the rate at which the error has been changing.\r
- *\r
- * \par Instance Structure\r
- * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.\r
- * A separate instance structure must be defined for each PID Controller.\r
- * There are separate instance structure declarations for each of the 3 supported data types.\r
- *\r
- * \par Reset Functions\r
- * There is also an associated reset function for each data type which clears the state array.\r
- *\r
- * \par Initialization Functions\r
- * There is also an associated initialization function for each data type.\r
- * The initialization function performs the following operations:\r
- * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.\r
- * - Zeros out the values in the state buffer.\r
- *\r
- * \par\r
- * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.\r
- *\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the fixed-point versions of the PID Controller functions.\r
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup PID\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Process function for the floating-point PID Control.\r
- * @param[in,out] S is an instance of the floating-point PID Control structure\r
- * @param[in] in input sample to process\r
- * @return out processed output sample.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(\r
- arm_pid_instance_f32 * S,\r
- float32_t in)\r
- {\r
- float32_t out;\r
-\r
- /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */\r
- out = (S->A0 * in) +\r
- (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);\r
-\r
- /* Update state */\r
- S->state[1] = S->state[0];\r
- S->state[0] = in;\r
- S->state[2] = out;\r
-\r
- /* return to application */\r
- return (out);\r
-\r
- }\r
-\r
- /**\r
- * @brief Process function for the Q31 PID Control.\r
- * @param[in,out] S points to an instance of the Q31 PID Control structure\r
- * @param[in] in input sample to process\r
- * @return out processed output sample.\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 64-bit accumulator.\r
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.\r
- * Thus, if the accumulator result overflows it wraps around rather than clip.\r
- * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.\r
- * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(\r
- arm_pid_instance_q31 * S,\r
- q31_t in)\r
- {\r
- q63_t acc;\r
- q31_t out;\r
-\r
- /* acc = A0 * x[n] */\r
- acc = (q63_t) S->A0 * in;\r
-\r
- /* acc += A1 * x[n-1] */\r
- acc += (q63_t) S->A1 * S->state[0];\r
-\r
- /* acc += A2 * x[n-2] */\r
- acc += (q63_t) S->A2 * S->state[1];\r
-\r
- /* convert output to 1.31 format to add y[n-1] */\r
- out = (q31_t) (acc >> 31U);\r
-\r
- /* out += y[n-1] */\r
- out += S->state[2];\r
-\r
- /* Update state */\r
- S->state[1] = S->state[0];\r
- S->state[0] = in;\r
- S->state[2] = out;\r
-\r
- /* return to application */\r
- return (out);\r
- }\r
-\r
-\r
- /**\r
- * @brief Process function for the Q15 PID Control.\r
- * @param[in,out] S points to an instance of the Q15 PID Control structure\r
- * @param[in] in input sample to process\r
- * @return out processed output sample.\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using a 64-bit internal accumulator.\r
- * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.\r
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.\r
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.\r
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.\r
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(\r
- arm_pid_instance_q15 * S,\r
- q15_t in)\r
- {\r
- q63_t acc;\r
- q15_t out;\r
-\r
-#if defined (ARM_MATH_DSP)\r
- __SIMD32_TYPE *vstate;\r
-\r
- /* Implementation of PID controller */\r
-\r
- /* acc = A0 * x[n] */\r
- acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);\r
-\r
- /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
- vstate = __SIMD32_CONST(S->state);\r
- acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);\r
-#else\r
- /* acc = A0 * x[n] */\r
- acc = ((q31_t) S->A0) * in;\r
-\r
- /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
- acc += (q31_t) S->A1 * S->state[0];\r
- acc += (q31_t) S->A2 * S->state[1];\r
-#endif\r
-\r
- /* acc += y[n-1] */\r
- acc += (q31_t) S->state[2] << 15;\r
-\r
- /* saturate the output */\r
- out = (q15_t) (__SSAT((acc >> 15), 16));\r
-\r
- /* Update state */\r
- S->state[1] = S->state[0];\r
- S->state[0] = in;\r
- S->state[2] = out;\r
-\r
- /* return to application */\r
- return (out);\r
- }\r
-\r
- /**\r
- * @} end of PID group\r
- */\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix inverse.\r
- * @param[in] src points to the instance of the input floating-point matrix structure.\r
- * @param[out] dst points to the instance of the output floating-point matrix structure.\r
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
- */\r
- arm_status arm_mat_inverse_f32(\r
- const arm_matrix_instance_f32 * src,\r
- arm_matrix_instance_f32 * dst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix inverse.\r
- * @param[in] src points to the instance of the input floating-point matrix structure.\r
- * @param[out] dst points to the instance of the output floating-point matrix structure.\r
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
- */\r
- arm_status arm_mat_inverse_f64(\r
- const arm_matrix_instance_f64 * src,\r
- arm_matrix_instance_f64 * dst);\r
-\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup clarke Vector Clarke Transform\r
- * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.\r
- * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents\r
- * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.\r
- * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below\r
- * \image html clarke.gif Stator current space vector and its components in (a,b).\r
- * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>\r
- * can be calculated using only <code>Ia</code> and <code>Ib</code>.\r
- *\r
- * The function operates on a single sample of data and each call to the function returns the processed output.\r
- * The library provides separate functions for Q31 and floating-point data types.\r
- * \par Algorithm\r
- * \image html clarkeFormula.gif\r
- * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and\r
- * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the Q31 version of the Clarke transform.\r
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup clarke\r
- * @{\r
- */\r
-\r
- /**\r
- *\r
- * @brief Floating-point Clarke transform\r
- * @param[in] Ia input three-phase coordinate <code>a</code>\r
- * @param[in] Ib input three-phase coordinate <code>b</code>\r
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(\r
- float32_t Ia,\r
- float32_t Ib,\r
- float32_t * pIalpha,\r
- float32_t * pIbeta)\r
- {\r
- /* Calculate pIalpha using the equation, pIalpha = Ia */\r
- *pIalpha = Ia;\r
-\r
- /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */\r
- *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);\r
- }\r
-\r
-\r
- /**\r
- * @brief Clarke transform for Q31 version\r
- * @param[in] Ia input three-phase coordinate <code>a</code>\r
- * @param[in] Ib input three-phase coordinate <code>b</code>\r
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 32-bit accumulator.\r
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
- * There is saturation on the addition, hence there is no risk of overflow.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(\r
- q31_t Ia,\r
- q31_t Ib,\r
- q31_t * pIalpha,\r
- q31_t * pIbeta)\r
- {\r
- q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
-\r
- /* Calculating pIalpha from Ia by equation pIalpha = Ia */\r
- *pIalpha = Ia;\r
-\r
- /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */\r
- product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);\r
-\r
- /* Intermediate product is calculated by (2/sqrt(3) * Ib) */\r
- product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);\r
-\r
- /* pIbeta is calculated by adding the intermediate products */\r
- *pIbeta = __QADD(product1, product2);\r
- }\r
-\r
- /**\r
- * @} end of clarke group\r
- */\r
-\r
- /**\r
- * @brief Converts the elements of the Q7 vector to Q31 vector.\r
- * @param[in] pSrc input pointer\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_q7_to_q31(\r
- q7_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup inv_clarke Vector Inverse Clarke Transform\r
- * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.\r
- *\r
- * The function operates on a single sample of data and each call to the function returns the processed output.\r
- * The library provides separate functions for Q31 and floating-point data types.\r
- * \par Algorithm\r
- * \image html clarkeInvFormula.gif\r
- * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and\r
- * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the Q31 version of the Clarke transform.\r
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup inv_clarke\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Floating-point Inverse Clarke transform\r
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
- * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
- * @param[out] pIa points to output three-phase coordinate <code>a</code>\r
- * @param[out] pIb points to output three-phase coordinate <code>b</code>\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(\r
- float32_t Ialpha,\r
- float32_t Ibeta,\r
- float32_t * pIa,\r
- float32_t * pIb)\r
- {\r
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
- *pIa = Ialpha;\r
-\r
- /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */\r
- *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;\r
- }\r
-\r
-\r
- /**\r
- * @brief Inverse Clarke transform for Q31 version\r
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
- * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
- * @param[out] pIa points to output three-phase coordinate <code>a</code>\r
- * @param[out] pIb points to output three-phase coordinate <code>b</code>\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 32-bit accumulator.\r
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
- * There is saturation on the subtraction, hence there is no risk of overflow.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(\r
- q31_t Ialpha,\r
- q31_t Ibeta,\r
- q31_t * pIa,\r
- q31_t * pIb)\r
- {\r
- q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
-\r
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
- *pIa = Ialpha;\r
-\r
- /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */\r
- product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);\r
-\r
- /* Intermediate product is calculated by (1/sqrt(3) * pIb) */\r
- product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);\r
-\r
- /* pIb is calculated by subtracting the products */\r
- *pIb = __QSUB(product2, product1);\r
- }\r
-\r
- /**\r
- * @} end of inv_clarke group\r
- */\r
-\r
- /**\r
- * @brief Converts the elements of the Q7 vector to Q15 vector.\r
- * @param[in] pSrc input pointer\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_q7_to_q15(\r
- q7_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup park Vector Park Transform\r
- *\r
- * Forward Park transform converts the input two-coordinate vector to flux and torque components.\r
- * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents\r
- * from the stationary to the moving reference frame and control the spatial relationship between\r
- * the stator vector current and rotor flux vector.\r
- * If we consider the d axis aligned with the rotor flux, the diagram below shows the\r
- * current vector and the relationship from the two reference frames:\r
- * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"\r
- *\r
- * The function operates on a single sample of data and each call to the function returns the processed output.\r
- * The library provides separate functions for Q31 and floating-point data types.\r
- * \par Algorithm\r
- * \image html parkFormula.gif\r
- * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,\r
- * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
- * cosine and sine values of theta (rotor flux position).\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the Q31 version of the Park transform.\r
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup park\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Floating-point Park transform\r
- * @param[in] Ialpha input two-phase vector coordinate alpha\r
- * @param[in] Ibeta input two-phase vector coordinate beta\r
- * @param[out] pId points to output rotor reference frame d\r
- * @param[out] pIq points to output rotor reference frame q\r
- * @param[in] sinVal sine value of rotation angle theta\r
- * @param[in] cosVal cosine value of rotation angle theta\r
- *\r
- * The function implements the forward Park transform.\r
- *\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_park_f32(\r
- float32_t Ialpha,\r
- float32_t Ibeta,\r
- float32_t * pId,\r
- float32_t * pIq,\r
- float32_t sinVal,\r
- float32_t cosVal)\r
- {\r
- /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */\r
- *pId = Ialpha * cosVal + Ibeta * sinVal;\r
-\r
- /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */\r
- *pIq = -Ialpha * sinVal + Ibeta * cosVal;\r
- }\r
-\r
-\r
- /**\r
- * @brief Park transform for Q31 version\r
- * @param[in] Ialpha input two-phase vector coordinate alpha\r
- * @param[in] Ibeta input two-phase vector coordinate beta\r
- * @param[out] pId points to output rotor reference frame d\r
- * @param[out] pIq points to output rotor reference frame q\r
- * @param[in] sinVal sine value of rotation angle theta\r
- * @param[in] cosVal cosine value of rotation angle theta\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 32-bit accumulator.\r
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
- * There is saturation on the addition and subtraction, hence there is no risk of overflow.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_park_q31(\r
- q31_t Ialpha,\r
- q31_t Ibeta,\r
- q31_t * pId,\r
- q31_t * pIq,\r
- q31_t sinVal,\r
- q31_t cosVal)\r
- {\r
- q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
- q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
-\r
- /* Intermediate product is calculated by (Ialpha * cosVal) */\r
- product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);\r
-\r
- /* Intermediate product is calculated by (Ibeta * sinVal) */\r
- product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);\r
-\r
-\r
- /* Intermediate product is calculated by (Ialpha * sinVal) */\r
- product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);\r
-\r
- /* Intermediate product is calculated by (Ibeta * cosVal) */\r
- product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);\r
-\r
- /* Calculate pId by adding the two intermediate products 1 and 2 */\r
- *pId = __QADD(product1, product2);\r
-\r
- /* Calculate pIq by subtracting the two intermediate products 3 from 4 */\r
- *pIq = __QSUB(product4, product3);\r
- }\r
-\r
- /**\r
- * @} end of park group\r
- */\r
-\r
- /**\r
- * @brief Converts the elements of the Q7 vector to floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q7_to_float(\r
- q7_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup inv_park Vector Inverse Park transform\r
- * Inverse Park transform converts the input flux and torque components to two-coordinate vector.\r
- *\r
- * The function operates on a single sample of data and each call to the function returns the processed output.\r
- * The library provides separate functions for Q31 and floating-point data types.\r
- * \par Algorithm\r
- * \image html parkInvFormula.gif\r
- * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,\r
- * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
- * cosine and sine values of theta (rotor flux position).\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the Q31 version of the Park transform.\r
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup inv_park\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Floating-point Inverse Park transform\r
- * @param[in] Id input coordinate of rotor reference frame d\r
- * @param[in] Iq input coordinate of rotor reference frame q\r
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
- * @param[in] sinVal sine value of rotation angle theta\r
- * @param[in] cosVal cosine value of rotation angle theta\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(\r
- float32_t Id,\r
- float32_t Iq,\r
- float32_t * pIalpha,\r
- float32_t * pIbeta,\r
- float32_t sinVal,\r
- float32_t cosVal)\r
- {\r
- /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */\r
- *pIalpha = Id * cosVal - Iq * sinVal;\r
-\r
- /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */\r
- *pIbeta = Id * sinVal + Iq * cosVal;\r
- }\r
-\r
-\r
- /**\r
- * @brief Inverse Park transform for Q31 version\r
- * @param[in] Id input coordinate of rotor reference frame d\r
- * @param[in] Iq input coordinate of rotor reference frame q\r
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
- * @param[in] sinVal sine value of rotation angle theta\r
- * @param[in] cosVal cosine value of rotation angle theta\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 32-bit accumulator.\r
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
- * There is saturation on the addition, hence there is no risk of overflow.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(\r
- q31_t Id,\r
- q31_t Iq,\r
- q31_t * pIalpha,\r
- q31_t * pIbeta,\r
- q31_t sinVal,\r
- q31_t cosVal)\r
- {\r
- q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
- q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
-\r
- /* Intermediate product is calculated by (Id * cosVal) */\r
- product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);\r
-\r
- /* Intermediate product is calculated by (Iq * sinVal) */\r
- product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);\r
-\r
-\r
- /* Intermediate product is calculated by (Id * sinVal) */\r
- product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);\r
-\r
- /* Intermediate product is calculated by (Iq * cosVal) */\r
- product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);\r
-\r
- /* Calculate pIalpha by using the two intermediate products 1 and 2 */\r
- *pIalpha = __QSUB(product1, product2);\r
-\r
- /* Calculate pIbeta by using the two intermediate products 3 and 4 */\r
- *pIbeta = __QADD(product4, product3);\r
- }\r
-\r
- /**\r
- * @} end of Inverse park group\r
- */\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q31 vector to floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q31_to_float(\r
- q31_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @ingroup groupInterpolation\r
- */\r
-\r
- /**\r
- * @defgroup LinearInterpolate Linear Interpolation\r
- *\r
- * Linear interpolation is a method of curve fitting using linear polynomials.\r
- * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line\r
- *\r
- * \par\r
- * \image html LinearInterp.gif "Linear interpolation"\r
- *\r
- * \par\r
- * A Linear Interpolate function calculates an output value(y), for the input(x)\r
- * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)\r
- *\r
- * \par Algorithm:\r
- * <pre>\r
- * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\r
- * where x0, x1 are nearest values of input x\r
- * y0, y1 are nearest values to output y\r
- * </pre>\r
- *\r
- * \par\r
- * This set of functions implements Linear interpolation process\r
- * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single\r
- * sample of data and each call to the function returns a single processed value.\r
- * <code>S</code> points to an instance of the Linear Interpolate function data structure.\r
- * <code>x</code> is the input sample value. The functions returns the output value.\r
- *\r
- * \par\r
- * if x is outside of the table boundary, Linear interpolation returns first value of the table\r
- * if x is below input range and returns last value of table if x is above range.\r
- */\r
-\r
- /**\r
- * @addtogroup LinearInterpolate\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Process function for the floating-point Linear Interpolation Function.\r
- * @param[in,out] S is an instance of the floating-point Linear Interpolation structure\r
- * @param[in] x input sample to process\r
- * @return y processed output sample.\r
- *\r
- */\r
- CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(\r
- arm_linear_interp_instance_f32 * S,\r
- float32_t x)\r
- {\r
- float32_t y;\r
- float32_t x0, x1; /* Nearest input values */\r
- float32_t y0, y1; /* Nearest output values */\r
- float32_t xSpacing = S->xSpacing; /* spacing between input values */\r
- int32_t i; /* Index variable */\r
- float32_t *pYData = S->pYData; /* pointer to output table */\r
-\r
- /* Calculation of index */\r
- i = (int32_t) ((x - S->x1) / xSpacing);\r
-\r
- if (i < 0)\r
- {\r
- /* Iniatilize output for below specified range as least output value of table */\r
- y = pYData[0];\r
- }\r
- else if ((uint32_t)i >= S->nValues)\r
- {\r
- /* Iniatilize output for above specified range as last output value of table */\r
- y = pYData[S->nValues - 1];\r
- }\r
- else\r
- {\r
- /* Calculation of nearest input values */\r
- x0 = S->x1 + i * xSpacing;\r
- x1 = S->x1 + (i + 1) * xSpacing;\r
-\r
- /* Read of nearest output values */\r
- y0 = pYData[i];\r
- y1 = pYData[i + 1];\r
-\r
- /* Calculation of output */\r
- y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));\r
-\r
- }\r
-\r
- /* returns output value */\r
- return (y);\r
- }\r
-\r
-\r
- /**\r
- *\r
- * @brief Process function for the Q31 Linear Interpolation Function.\r
- * @param[in] pYData pointer to Q31 Linear Interpolation table\r
- * @param[in] x input sample to process\r
- * @param[in] nValues number of table values\r
- * @return y processed output sample.\r
- *\r
- * \par\r
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
- * This function can support maximum of table size 2^12.\r
- *\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(\r
- q31_t * pYData,\r
- q31_t x,\r
- uint32_t nValues)\r
- {\r
- q31_t y; /* output */\r
- q31_t y0, y1; /* Nearest output values */\r
- q31_t fract; /* fractional part */\r
- int32_t index; /* Index to read nearest output values */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- index = ((x & (q31_t)0xFFF00000) >> 20);\r
-\r
- if (index >= (int32_t)(nValues - 1))\r
- {\r
- return (pYData[nValues - 1]);\r
- }\r
- else if (index < 0)\r
- {\r
- return (pYData[0]);\r
- }\r
- else\r
- {\r
- /* 20 bits for the fractional part */\r
- /* shift left by 11 to keep fract in 1.31 format */\r
- fract = (x & 0x000FFFFF) << 11;\r
-\r
- /* Read two nearest output values from the index in 1.31(q31) format */\r
- y0 = pYData[index];\r
- y1 = pYData[index + 1];\r
-\r
- /* Calculation of y0 * (1-fract) and y is in 2.30 format */\r
- y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));\r
-\r
- /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */\r
- y += ((q31_t) (((q63_t) y1 * fract) >> 32));\r
-\r
- /* Convert y to 1.31 format */\r
- return (y << 1U);\r
- }\r
- }\r
-\r
-\r
- /**\r
- *\r
- * @brief Process function for the Q15 Linear Interpolation Function.\r
- * @param[in] pYData pointer to Q15 Linear Interpolation table\r
- * @param[in] x input sample to process\r
- * @param[in] nValues number of table values\r
- * @return y processed output sample.\r
- *\r
- * \par\r
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
- * This function can support maximum of table size 2^12.\r
- *\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(\r
- q15_t * pYData,\r
- q31_t x,\r
- uint32_t nValues)\r
- {\r
- q63_t y; /* output */\r
- q15_t y0, y1; /* Nearest output values */\r
- q31_t fract; /* fractional part */\r
- int32_t index; /* Index to read nearest output values */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- index = ((x & (int32_t)0xFFF00000) >> 20);\r
-\r
- if (index >= (int32_t)(nValues - 1))\r
- {\r
- return (pYData[nValues - 1]);\r
- }\r
- else if (index < 0)\r
- {\r
- return (pYData[0]);\r
- }\r
- else\r
- {\r
- /* 20 bits for the fractional part */\r
- /* fract is in 12.20 format */\r
- fract = (x & 0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- y0 = pYData[index];\r
- y1 = pYData[index + 1];\r
-\r
- /* Calculation of y0 * (1-fract) and y is in 13.35 format */\r
- y = ((q63_t) y0 * (0xFFFFF - fract));\r
-\r
- /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */\r
- y += ((q63_t) y1 * (fract));\r
-\r
- /* convert y to 1.15 format */\r
- return (q15_t) (y >> 20);\r
- }\r
- }\r
-\r
-\r
- /**\r
- *\r
- * @brief Process function for the Q7 Linear Interpolation Function.\r
- * @param[in] pYData pointer to Q7 Linear Interpolation table\r
- * @param[in] x input sample to process\r
- * @param[in] nValues number of table values\r
- * @return y processed output sample.\r
- *\r
- * \par\r
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
- * This function can support maximum of table size 2^12.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(\r
- q7_t * pYData,\r
- q31_t x,\r
- uint32_t nValues)\r
- {\r
- q31_t y; /* output */\r
- q7_t y0, y1; /* Nearest output values */\r
- q31_t fract; /* fractional part */\r
- uint32_t index; /* Index to read nearest output values */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- if (x < 0)\r
- {\r
- return (pYData[0]);\r
- }\r
- index = (x >> 20) & 0xfff;\r
-\r
- if (index >= (nValues - 1))\r
- {\r
- return (pYData[nValues - 1]);\r
- }\r
- else\r
- {\r
- /* 20 bits for the fractional part */\r
- /* fract is in 12.20 format */\r
- fract = (x & 0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index and are in 1.7(q7) format */\r
- y0 = pYData[index];\r
- y1 = pYData[index + 1];\r
-\r
- /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */\r
- y = ((y0 * (0xFFFFF - fract)));\r
-\r
- /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */\r
- y += (y1 * fract);\r
-\r
- /* convert y to 1.7(q7) format */\r
- return (q7_t) (y >> 20);\r
- }\r
- }\r
-\r
- /**\r
- * @} end of LinearInterpolate group\r
- */\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric sine function for floating-point data.\r
- * @param[in] x input value in radians.\r
- * @return sin(x).\r
- */\r
- float32_t arm_sin_f32(\r
- float32_t x);\r
-\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric sine function for Q31 data.\r
- * @param[in] x Scaled input value in radians.\r
- * @return sin(x).\r
- */\r
- q31_t arm_sin_q31(\r
- q31_t x);\r
-\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric sine function for Q15 data.\r
- * @param[in] x Scaled input value in radians.\r
- * @return sin(x).\r
- */\r
- q15_t arm_sin_q15(\r
- q15_t x);\r
-\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric cosine function for floating-point data.\r
- * @param[in] x input value in radians.\r
- * @return cos(x).\r
- */\r
- float32_t arm_cos_f32(\r
- float32_t x);\r
-\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric cosine function for Q31 data.\r
- * @param[in] x Scaled input value in radians.\r
- * @return cos(x).\r
- */\r
- q31_t arm_cos_q31(\r
- q31_t x);\r
-\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric cosine function for Q15 data.\r
- * @param[in] x Scaled input value in radians.\r
- * @return cos(x).\r
- */\r
- q15_t arm_cos_q15(\r
- q15_t x);\r
-\r
-\r
- /**\r
- * @ingroup groupFastMath\r
- */\r
-\r
-\r
- /**\r
- * @defgroup SQRT Square Root\r
- *\r
- * Computes the square root of a number.\r
- * There are separate functions for Q15, Q31, and floating-point data types.\r
- * The square root function is computed using the Newton-Raphson algorithm.\r
- * This is an iterative algorithm of the form:\r
- * <pre>\r
- * x1 = x0 - f(x0)/f'(x0)\r
- * </pre>\r
- * where <code>x1</code> is the current estimate,\r
- * <code>x0</code> is the previous estimate, and\r
- * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.\r
- * For the square root function, the algorithm reduces to:\r
- * <pre>\r
- * x0 = in/2 [initial guess]\r
- * x1 = 1/2 * ( x0 + in / x0) [each iteration]\r
- * </pre>\r
- */\r
-\r
-\r
- /**\r
- * @addtogroup SQRT\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Floating-point square root function.\r
- * @param[in] in input value.\r
- * @param[out] pOut square root of input value.\r
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
- * <code>in</code> is negative value and returns zero output for negative values.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(\r
- float32_t in,\r
- float32_t * pOut)\r
- {\r
- if (in >= 0.0f)\r
- {\r
-\r
-#if (__FPU_USED == 1) && defined ( __CC_ARM )\r
- *pOut = __sqrtf(in);\r
-#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\r
- *pOut = __builtin_sqrtf(in);\r
-#elif (__FPU_USED == 1) && defined(__GNUC__)\r
- *pOut = __builtin_sqrtf(in);\r
-#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)\r
- __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));\r
-#else\r
- *pOut = sqrtf(in);\r
-#endif\r
-\r
- return (ARM_MATH_SUCCESS);\r
- }\r
- else\r
- {\r
- *pOut = 0.0f;\r
- return (ARM_MATH_ARGUMENT_ERROR);\r
- }\r
- }\r
-\r
-\r
- /**\r
- * @brief Q31 square root function.\r
- * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.\r
- * @param[out] pOut square root of input value.\r
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
- * <code>in</code> is negative value and returns zero output for negative values.\r
- */\r
- arm_status arm_sqrt_q31(\r
- q31_t in,\r
- q31_t * pOut);\r
-\r
-\r
- /**\r
- * @brief Q15 square root function.\r
- * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.\r
- * @param[out] pOut square root of input value.\r
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
- * <code>in</code> is negative value and returns zero output for negative values.\r
- */\r
- arm_status arm_sqrt_q15(\r
- q15_t in,\r
- q15_t * pOut);\r
-\r
- /**\r
- * @} end of SQRT group\r
- */\r
-\r
-\r
- /**\r
- * @brief floating-point Circular write function.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(\r
- int32_t * circBuffer,\r
- int32_t L,\r
- uint16_t * writeOffset,\r
- int32_t bufferInc,\r
- const int32_t * src,\r
- int32_t srcInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0U;\r
- int32_t wOffset;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location where the input samples to be copied */\r
- wOffset = *writeOffset;\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while (i > 0U)\r
- {\r
- /* copy the input sample to the circular buffer */\r
- circBuffer[wOffset] = *src;\r
-\r
- /* Update the input pointer */\r
- src += srcInc;\r
-\r
- /* Circularly update wOffset. Watch out for positive and negative value */\r
- wOffset += bufferInc;\r
- if (wOffset >= L)\r
- wOffset -= L;\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *writeOffset = (uint16_t)wOffset;\r
- }\r
-\r
-\r
-\r
- /**\r
- * @brief floating-point Circular Read function.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(\r
- int32_t * circBuffer,\r
- int32_t L,\r
- int32_t * readOffset,\r
- int32_t bufferInc,\r
- int32_t * dst,\r
- int32_t * dst_base,\r
- int32_t dst_length,\r
- int32_t dstInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0U;\r
- int32_t rOffset, dst_end;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location from where the input samples to be read */\r
- rOffset = *readOffset;\r
- dst_end = (int32_t) (dst_base + dst_length);\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while (i > 0U)\r
- {\r
- /* copy the sample from the circular buffer to the destination buffer */\r
- *dst = circBuffer[rOffset];\r
-\r
- /* Update the input pointer */\r
- dst += dstInc;\r
-\r
- if (dst == (int32_t *) dst_end)\r
- {\r
- dst = dst_base;\r
- }\r
-\r
- /* Circularly update rOffset. Watch out for positive and negative value */\r
- rOffset += bufferInc;\r
-\r
- if (rOffset >= L)\r
- {\r
- rOffset -= L;\r
- }\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *readOffset = rOffset;\r
- }\r
-\r
-\r
- /**\r
- * @brief Q15 Circular write function.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(\r
- q15_t * circBuffer,\r
- int32_t L,\r
- uint16_t * writeOffset,\r
- int32_t bufferInc,\r
- const q15_t * src,\r
- int32_t srcInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0U;\r
- int32_t wOffset;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location where the input samples to be copied */\r
- wOffset = *writeOffset;\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while (i > 0U)\r
- {\r
- /* copy the input sample to the circular buffer */\r
- circBuffer[wOffset] = *src;\r
-\r
- /* Update the input pointer */\r
- src += srcInc;\r
-\r
- /* Circularly update wOffset. Watch out for positive and negative value */\r
- wOffset += bufferInc;\r
- if (wOffset >= L)\r
- wOffset -= L;\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *writeOffset = (uint16_t)wOffset;\r
- }\r
-\r
-\r
- /**\r
- * @brief Q15 Circular Read function.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(\r
- q15_t * circBuffer,\r
- int32_t L,\r
- int32_t * readOffset,\r
- int32_t bufferInc,\r
- q15_t * dst,\r
- q15_t * dst_base,\r
- int32_t dst_length,\r
- int32_t dstInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0;\r
- int32_t rOffset, dst_end;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location from where the input samples to be read */\r
- rOffset = *readOffset;\r
-\r
- dst_end = (int32_t) (dst_base + dst_length);\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while (i > 0U)\r
- {\r
- /* copy the sample from the circular buffer to the destination buffer */\r
- *dst = circBuffer[rOffset];\r
-\r
- /* Update the input pointer */\r
- dst += dstInc;\r
-\r
- if (dst == (q15_t *) dst_end)\r
- {\r
- dst = dst_base;\r
- }\r
-\r
- /* Circularly update wOffset. Watch out for positive and negative value */\r
- rOffset += bufferInc;\r
-\r
- if (rOffset >= L)\r
- {\r
- rOffset -= L;\r
- }\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *readOffset = rOffset;\r
- }\r
-\r
-\r
- /**\r
- * @brief Q7 Circular write function.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(\r
- q7_t * circBuffer,\r
- int32_t L,\r
- uint16_t * writeOffset,\r
- int32_t bufferInc,\r
- const q7_t * src,\r
- int32_t srcInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0U;\r
- int32_t wOffset;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location where the input samples to be copied */\r
- wOffset = *writeOffset;\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while (i > 0U)\r
- {\r
- /* copy the input sample to the circular buffer */\r
- circBuffer[wOffset] = *src;\r
-\r
- /* Update the input pointer */\r
- src += srcInc;\r
-\r
- /* Circularly update wOffset. Watch out for positive and negative value */\r
- wOffset += bufferInc;\r
- if (wOffset >= L)\r
- wOffset -= L;\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *writeOffset = (uint16_t)wOffset;\r
- }\r
-\r
-\r
- /**\r
- * @brief Q7 Circular Read function.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(\r
- q7_t * circBuffer,\r
- int32_t L,\r
- int32_t * readOffset,\r
- int32_t bufferInc,\r
- q7_t * dst,\r
- q7_t * dst_base,\r
- int32_t dst_length,\r
- int32_t dstInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0;\r
- int32_t rOffset, dst_end;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location from where the input samples to be read */\r
- rOffset = *readOffset;\r
-\r
- dst_end = (int32_t) (dst_base + dst_length);\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while (i > 0U)\r
- {\r
- /* copy the sample from the circular buffer to the destination buffer */\r
- *dst = circBuffer[rOffset];\r
-\r
- /* Update the input pointer */\r
- dst += dstInc;\r
-\r
- if (dst == (q7_t *) dst_end)\r
- {\r
- dst = dst_base;\r
- }\r
-\r
- /* Circularly update rOffset. Watch out for positive and negative value */\r
- rOffset += bufferInc;\r
-\r
- if (rOffset >= L)\r
- {\r
- rOffset -= L;\r
- }\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *readOffset = rOffset;\r
- }\r
-\r
-\r
- /**\r
- * @brief Sum of the squares of the elements of a Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_power_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q63_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Sum of the squares of the elements of a floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_power_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Sum of the squares of the elements of a Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_power_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q63_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Sum of the squares of the elements of a Q7 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_power_q7(\r
- q7_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Mean value of a Q7 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_mean_q7(\r
- q7_t * pSrc,\r
- uint32_t blockSize,\r
- q7_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Mean value of a Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_mean_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Mean value of a Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_mean_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Mean value of a floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_mean_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Variance of the elements of a floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_var_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Variance of the elements of a Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_var_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Variance of the elements of a Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_var_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Root Mean Square of the elements of a floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_rms_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Root Mean Square of the elements of a Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_rms_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Root Mean Square of the elements of a Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_rms_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Standard deviation of the elements of a floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_std_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Standard deviation of the elements of a Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_std_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Standard deviation of the elements of a Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_std_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex magnitude\r
- * @param[in] pSrc points to the complex input vector\r
- * @param[out] pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- */\r
- void arm_cmplx_mag_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q31 complex magnitude\r
- * @param[in] pSrc points to the complex input vector\r
- * @param[out] pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- */\r
- void arm_cmplx_mag_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q15 complex magnitude\r
- * @param[in] pSrc points to the complex input vector\r
- * @param[out] pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- */\r
- void arm_cmplx_mag_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q15 complex dot product\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- * @param[out] realResult real part of the result returned here\r
- * @param[out] imagResult imaginary part of the result returned here\r
- */\r
- void arm_cmplx_dot_prod_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- uint32_t numSamples,\r
- q31_t * realResult,\r
- q31_t * imagResult);\r
-\r
-\r
- /**\r
- * @brief Q31 complex dot product\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- * @param[out] realResult real part of the result returned here\r
- * @param[out] imagResult imaginary part of the result returned here\r
- */\r
- void arm_cmplx_dot_prod_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- uint32_t numSamples,\r
- q63_t * realResult,\r
- q63_t * imagResult);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex dot product\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- * @param[out] realResult real part of the result returned here\r
- * @param[out] imagResult imaginary part of the result returned here\r
- */\r
- void arm_cmplx_dot_prod_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- uint32_t numSamples,\r
- float32_t * realResult,\r
- float32_t * imagResult);\r
-\r
-\r
- /**\r
- * @brief Q15 complex-by-real multiplication\r
- * @param[in] pSrcCmplx points to the complex input vector\r
- * @param[in] pSrcReal points to the real input vector\r
- * @param[out] pCmplxDst points to the complex output vector\r
- * @param[in] numSamples number of samples in each vector\r
- */\r
- void arm_cmplx_mult_real_q15(\r
- q15_t * pSrcCmplx,\r
- q15_t * pSrcReal,\r
- q15_t * pCmplxDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q31 complex-by-real multiplication\r
- * @param[in] pSrcCmplx points to the complex input vector\r
- * @param[in] pSrcReal points to the real input vector\r
- * @param[out] pCmplxDst points to the complex output vector\r
- * @param[in] numSamples number of samples in each vector\r
- */\r
- void arm_cmplx_mult_real_q31(\r
- q31_t * pSrcCmplx,\r
- q31_t * pSrcReal,\r
- q31_t * pCmplxDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex-by-real multiplication\r
- * @param[in] pSrcCmplx points to the complex input vector\r
- * @param[in] pSrcReal points to the real input vector\r
- * @param[out] pCmplxDst points to the complex output vector\r
- * @param[in] numSamples number of samples in each vector\r
- */\r
- void arm_cmplx_mult_real_f32(\r
- float32_t * pSrcCmplx,\r
- float32_t * pSrcReal,\r
- float32_t * pCmplxDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Minimum value of a Q7 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] result is output pointer\r
- * @param[in] index is the array index of the minimum value in the input buffer.\r
- */\r
- void arm_min_q7(\r
- q7_t * pSrc,\r
- uint32_t blockSize,\r
- q7_t * result,\r
- uint32_t * index);\r
-\r
-\r
- /**\r
- * @brief Minimum value of a Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output pointer\r
- * @param[in] pIndex is the array index of the minimum value in the input buffer.\r
- */\r
- void arm_min_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
- /**\r
- * @brief Minimum value of a Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output pointer\r
- * @param[out] pIndex is the array index of the minimum value in the input buffer.\r
- */\r
- void arm_min_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
- /**\r
- * @brief Minimum value of a floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output pointer\r
- * @param[out] pIndex is the array index of the minimum value in the input buffer.\r
- */\r
- void arm_min_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
-/**\r
- * @brief Maximum value of a Q7 vector.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[in] blockSize length of the input vector\r
- * @param[out] pResult maximum value returned here\r
- * @param[out] pIndex index of maximum value returned here\r
- */\r
- void arm_max_q7(\r
- q7_t * pSrc,\r
- uint32_t blockSize,\r
- q7_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
-/**\r
- * @brief Maximum value of a Q15 vector.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[in] blockSize length of the input vector\r
- * @param[out] pResult maximum value returned here\r
- * @param[out] pIndex index of maximum value returned here\r
- */\r
- void arm_max_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
-/**\r
- * @brief Maximum value of a Q31 vector.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[in] blockSize length of the input vector\r
- * @param[out] pResult maximum value returned here\r
- * @param[out] pIndex index of maximum value returned here\r
- */\r
- void arm_max_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
-/**\r
- * @brief Maximum value of a floating-point vector.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[in] blockSize length of the input vector\r
- * @param[out] pResult maximum value returned here\r
- * @param[out] pIndex index of maximum value returned here\r
- */\r
- void arm_max_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
- /**\r
- * @brief Q15 complex-by-complex multiplication\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- */\r
- void arm_cmplx_mult_cmplx_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- q15_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q31 complex-by-complex multiplication\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- */\r
- void arm_cmplx_mult_cmplx_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- q31_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex-by-complex multiplication\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- */\r
- void arm_cmplx_mult_cmplx_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- float32_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the floating-point vector to Q31 vector.\r
- * @param[in] pSrc points to the floating-point input vector\r
- * @param[out] pDst points to the Q31 output vector\r
- * @param[in] blockSize length of the input vector\r
- */\r
- void arm_float_to_q31(\r
- float32_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the floating-point vector to Q15 vector.\r
- * @param[in] pSrc points to the floating-point input vector\r
- * @param[out] pDst points to the Q15 output vector\r
- * @param[in] blockSize length of the input vector\r
- */\r
- void arm_float_to_q15(\r
- float32_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the floating-point vector to Q7 vector.\r
- * @param[in] pSrc points to the floating-point input vector\r
- * @param[out] pDst points to the Q7 output vector\r
- * @param[in] blockSize length of the input vector\r
- */\r
- void arm_float_to_q7(\r
- float32_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q31 vector to Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q31_to_q15(\r
- q31_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q31 vector to Q7 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q31_to_q7(\r
- q31_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q15 vector to floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q15_to_float(\r
- q15_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q15 vector to Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q15_to_q31(\r
- q15_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q15 vector to Q7 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q15_to_q7(\r
- q15_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @ingroup groupInterpolation\r
- */\r
-\r
- /**\r
- * @defgroup BilinearInterpolate Bilinear Interpolation\r
- *\r
- * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.\r
- * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process\r
- * determines values between the grid points.\r
- * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.\r
- * Bilinear interpolation is often used in image processing to rescale images.\r
- * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.\r
- *\r
- * <b>Algorithm</b>\r
- * \par\r
- * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.\r
- * For floating-point, the instance structure is defined as:\r
- * <pre>\r
- * typedef struct\r
- * {\r
- * uint16_t numRows;\r
- * uint16_t numCols;\r
- * float32_t *pData;\r
- * } arm_bilinear_interp_instance_f32;\r
- * </pre>\r
- *\r
- * \par\r
- * where <code>numRows</code> specifies the number of rows in the table;\r
- * <code>numCols</code> specifies the number of columns in the table;\r
- * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.\r
- * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.\r
- * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.\r
- *\r
- * \par\r
- * Let <code>(x, y)</code> specify the desired interpolation point. Then define:\r
- * <pre>\r
- * XF = floor(x)\r
- * YF = floor(y)\r
- * </pre>\r
- * \par\r
- * The interpolated output point is computed as:\r
- * <pre>\r
- * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\r
- * + f(XF+1, YF) * (x-XF)*(1-(y-YF))\r
- * + f(XF, YF+1) * (1-(x-XF))*(y-YF)\r
- * + f(XF+1, YF+1) * (x-XF)*(y-YF)\r
- * </pre>\r
- * Note that the coordinates (x, y) contain integer and fractional components.\r
- * The integer components specify which portion of the table to use while the\r
- * fractional components control the interpolation processor.\r
- *\r
- * \par\r
- * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.\r
- */\r
-\r
- /**\r
- * @addtogroup BilinearInterpolate\r
- * @{\r
- */\r
-\r
-\r
- /**\r
- *\r
- * @brief Floating-point bilinear interpolation.\r
- * @param[in,out] S points to an instance of the interpolation structure.\r
- * @param[in] X interpolation coordinate.\r
- * @param[in] Y interpolation coordinate.\r
- * @return out interpolated value.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(\r
- const arm_bilinear_interp_instance_f32 * S,\r
- float32_t X,\r
- float32_t Y)\r
- {\r
- float32_t out;\r
- float32_t f00, f01, f10, f11;\r
- float32_t *pData = S->pData;\r
- int32_t xIndex, yIndex, index;\r
- float32_t xdiff, ydiff;\r
- float32_t b1, b2, b3, b4;\r
-\r
- xIndex = (int32_t) X;\r
- yIndex = (int32_t) Y;\r
-\r
- /* Care taken for table outside boundary */\r
- /* Returns zero output when values are outside table boundary */\r
- if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))\r
- {\r
- return (0);\r
- }\r
-\r
- /* Calculation of index for two nearest points in X-direction */\r
- index = (xIndex - 1) + (yIndex - 1) * S->numCols;\r
-\r
-\r
- /* Read two nearest points in X-direction */\r
- f00 = pData[index];\r
- f01 = pData[index + 1];\r
-\r
- /* Calculation of index for two nearest points in Y-direction */\r
- index = (xIndex - 1) + (yIndex) * S->numCols;\r
-\r
-\r
- /* Read two nearest points in Y-direction */\r
- f10 = pData[index];\r
- f11 = pData[index + 1];\r
-\r
- /* Calculation of intermediate values */\r
- b1 = f00;\r
- b2 = f01 - f00;\r
- b3 = f10 - f00;\r
- b4 = f00 - f01 - f10 + f11;\r
-\r
- /* Calculation of fractional part in X */\r
- xdiff = X - xIndex;\r
-\r
- /* Calculation of fractional part in Y */\r
- ydiff = Y - yIndex;\r
-\r
- /* Calculation of bi-linear interpolated output */\r
- out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;\r
-\r
- /* return to application */\r
- return (out);\r
- }\r
-\r
-\r
- /**\r
- *\r
- * @brief Q31 bilinear interpolation.\r
- * @param[in,out] S points to an instance of the interpolation structure.\r
- * @param[in] X interpolation coordinate in 12.20 format.\r
- * @param[in] Y interpolation coordinate in 12.20 format.\r
- * @return out interpolated value.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(\r
- arm_bilinear_interp_instance_q31 * S,\r
- q31_t X,\r
- q31_t Y)\r
- {\r
- q31_t out; /* Temporary output */\r
- q31_t acc = 0; /* output */\r
- q31_t xfract, yfract; /* X, Y fractional parts */\r
- q31_t x1, x2, y1, y2; /* Nearest output values */\r
- int32_t rI, cI; /* Row and column indices */\r
- q31_t *pYData = S->pData; /* pointer to output table values */\r
- uint32_t nCols = S->numCols; /* num of rows */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- rI = ((X & (q31_t)0xFFF00000) >> 20);\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- cI = ((Y & (q31_t)0xFFF00000) >> 20);\r
-\r
- /* Care taken for table outside boundary */\r
- /* Returns zero output when values are outside table boundary */\r
- if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
- {\r
- return (0);\r
- }\r
-\r
- /* 20 bits for the fractional part */\r
- /* shift left xfract by 11 to keep 1.31 format */\r
- xfract = (X & 0x000FFFFF) << 11U;\r
-\r
- /* Read two nearest output values from the index */\r
- x1 = pYData[(rI) + (int32_t)nCols * (cI) ];\r
- x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];\r
-\r
- /* 20 bits for the fractional part */\r
- /* shift left yfract by 11 to keep 1.31 format */\r
- yfract = (Y & 0x000FFFFF) << 11U;\r
-\r
- /* Read two nearest output values from the index */\r
- y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];\r
- y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];\r
-\r
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */\r
- out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));\r
- acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));\r
-\r
- /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */\r
- out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));\r
- acc += ((q31_t) ((q63_t) out * (xfract) >> 32));\r
-\r
- /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */\r
- out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));\r
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
-\r
- /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */\r
- out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));\r
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
-\r
- /* Convert acc to 1.31(q31) format */\r
- return ((q31_t)(acc << 2));\r
- }\r
-\r
-\r
- /**\r
- * @brief Q15 bilinear interpolation.\r
- * @param[in,out] S points to an instance of the interpolation structure.\r
- * @param[in] X interpolation coordinate in 12.20 format.\r
- * @param[in] Y interpolation coordinate in 12.20 format.\r
- * @return out interpolated value.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(\r
- arm_bilinear_interp_instance_q15 * S,\r
- q31_t X,\r
- q31_t Y)\r
- {\r
- q63_t acc = 0; /* output */\r
- q31_t out; /* Temporary output */\r
- q15_t x1, x2, y1, y2; /* Nearest output values */\r
- q31_t xfract, yfract; /* X, Y fractional parts */\r
- int32_t rI, cI; /* Row and column indices */\r
- q15_t *pYData = S->pData; /* pointer to output table values */\r
- uint32_t nCols = S->numCols; /* num of rows */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- rI = ((X & (q31_t)0xFFF00000) >> 20);\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- cI = ((Y & (q31_t)0xFFF00000) >> 20);\r
-\r
- /* Care taken for table outside boundary */\r
- /* Returns zero output when values are outside table boundary */\r
- if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
- {\r
- return (0);\r
- }\r
-\r
- /* 20 bits for the fractional part */\r
- /* xfract should be in 12.20 format */\r
- xfract = (X & 0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];\r
- x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\r
-\r
- /* 20 bits for the fractional part */\r
- /* yfract should be in 12.20 format */\r
- yfract = (Y & 0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];\r
- y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\r
-\r
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */\r
-\r
- /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */\r
- /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */\r
- out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U);\r
- acc = ((q63_t) out * (0xFFFFF - yfract));\r
-\r
- /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */\r
- out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U);\r
- acc += ((q63_t) out * (xfract));\r
-\r
- /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */\r
- out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U);\r
- acc += ((q63_t) out * (yfract));\r
-\r
- /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */\r
- out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);\r
- acc += ((q63_t) out * (yfract));\r
-\r
- /* acc is in 13.51 format and down shift acc by 36 times */\r
- /* Convert out to 1.15 format */\r
- return ((q15_t)(acc >> 36));\r
- }\r
-\r
-\r
- /**\r
- * @brief Q7 bilinear interpolation.\r
- * @param[in,out] S points to an instance of the interpolation structure.\r
- * @param[in] X interpolation coordinate in 12.20 format.\r
- * @param[in] Y interpolation coordinate in 12.20 format.\r
- * @return out interpolated value.\r
- */\r
- CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(\r
- arm_bilinear_interp_instance_q7 * S,\r
- q31_t X,\r
- q31_t Y)\r
- {\r
- q63_t acc = 0; /* output */\r
- q31_t out; /* Temporary output */\r
- q31_t xfract, yfract; /* X, Y fractional parts */\r
- q7_t x1, x2, y1, y2; /* Nearest output values */\r
- int32_t rI, cI; /* Row and column indices */\r
- q7_t *pYData = S->pData; /* pointer to output table values */\r
- uint32_t nCols = S->numCols; /* num of rows */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- rI = ((X & (q31_t)0xFFF00000) >> 20);\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- cI = ((Y & (q31_t)0xFFF00000) >> 20);\r
-\r
- /* Care taken for table outside boundary */\r
- /* Returns zero output when values are outside table boundary */\r
- if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
- {\r
- return (0);\r
- }\r
-\r
- /* 20 bits for the fractional part */\r
- /* xfract should be in 12.20 format */\r
- xfract = (X & (q31_t)0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];\r
- x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\r
-\r
- /* 20 bits for the fractional part */\r
- /* yfract should be in 12.20 format */\r
- yfract = (Y & (q31_t)0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];\r
- y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\r
-\r
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */\r
- out = ((x1 * (0xFFFFF - xfract)));\r
- acc = (((q63_t) out * (0xFFFFF - yfract)));\r
-\r
- /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */\r
- out = ((x2 * (0xFFFFF - yfract)));\r
- acc += (((q63_t) out * (xfract)));\r
-\r
- /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */\r
- out = ((y1 * (0xFFFFF - xfract)));\r
- acc += (((q63_t) out * (yfract)));\r
-\r
- /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */\r
- out = ((y2 * (yfract)));\r
- acc += (((q63_t) out * (xfract)));\r
-\r
- /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */\r
- return ((q7_t)(acc >> 40));\r
- }\r
-\r
- /**\r
- * @} end of BilinearInterpolate group\r
- */\r
-\r
-\r
-/* SMMLAR */\r
-#define multAcc_32x32_keep32_R(a, x, y) \\r
- a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)\r
-\r
-/* SMMLSR */\r
-#define multSub_32x32_keep32_R(a, x, y) \\r
- a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)\r
-\r
-/* SMMULR */\r
-#define mult_32x32_keep32_R(a, x, y) \\r
- a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)\r
-\r
-/* SMMLA */\r
-#define multAcc_32x32_keep32(a, x, y) \\r
- a += (q31_t) (((q63_t) x * y) >> 32)\r
-\r
-/* SMMLS */\r
-#define multSub_32x32_keep32(a, x, y) \\r
- a -= (q31_t) (((q63_t) x * y) >> 32)\r
-\r
-/* SMMUL */\r
-#define mult_32x32_keep32(a, x, y) \\r
- a = (q31_t) (((q63_t) x * y ) >> 32)\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- /* Enter low optimization region - place directly above function definition */\r
- #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\r
- #define LOW_OPTIMIZATION_ENTER \\r
- _Pragma ("push") \\r
- _Pragma ("O1")\r
- #else\r
- #define LOW_OPTIMIZATION_ENTER\r
- #endif\r
-\r
- /* Exit low optimization region - place directly after end of function definition */\r
- #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )\r
- #define LOW_OPTIMIZATION_EXIT \\r
- _Pragma ("pop")\r
- #else\r
- #define LOW_OPTIMIZATION_EXIT\r
- #endif\r
-\r
- /* Enter low optimization region - place directly above function definition */\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
-\r
- /* Exit low optimization region - place directly after end of function definition */\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
- #define LOW_OPTIMIZATION_ENTER\r
- #define LOW_OPTIMIZATION_EXIT\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined ( __GNUC__ )\r
- #define LOW_OPTIMIZATION_ENTER \\r
- __attribute__(( optimize("-O1") ))\r
- #define LOW_OPTIMIZATION_EXIT\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined ( __ICCARM__ )\r
- /* Enter low optimization region - place directly above function definition */\r
- #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )\r
- #define LOW_OPTIMIZATION_ENTER \\r
- _Pragma ("optimize=low")\r
- #else\r
- #define LOW_OPTIMIZATION_ENTER\r
- #endif\r
-\r
- /* Exit low optimization region - place directly after end of function definition */\r
- #define LOW_OPTIMIZATION_EXIT\r
-\r
- /* Enter low optimization region - place directly above function definition */\r
- #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \\r
- _Pragma ("optimize=low")\r
- #else\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
- #endif\r
-\r
- /* Exit low optimization region - place directly after end of function definition */\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined ( __TI_ARM__ )\r
- #define LOW_OPTIMIZATION_ENTER\r
- #define LOW_OPTIMIZATION_EXIT\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined ( __CSMC__ )\r
- #define LOW_OPTIMIZATION_ENTER\r
- #define LOW_OPTIMIZATION_EXIT\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined ( __TASKING__ )\r
- #define LOW_OPTIMIZATION_ENTER\r
- #define LOW_OPTIMIZATION_EXIT\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#endif\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-/* Compiler specific diagnostic adjustment */\r
-#if defined ( __CC_ARM )\r
-\r
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
-\r
-#elif defined ( __GNUC__ )\r
-#pragma GCC diagnostic pop\r
-\r
-#elif defined ( __ICCARM__ )\r
-\r
-#elif defined ( __TI_ARM__ )\r
-\r
-#elif defined ( __CSMC__ )\r
-\r
-#elif defined ( __TASKING__ )\r
-\r
-#else\r
- #error Unknown compiler\r
-#endif\r
-\r
-#endif /* _ARM_MATH_H */\r
-\r
-/**\r
- *\r
- * End of file.\r
- */\r
void SystemInitHook( void );\r
/*-----------------------------------------------------------*/\r
\r
+/* Secure main(). */\r
+int main(void)\r
+{\r
+ PRINTF( "Booting Secure World.\r\n" );\r
+\r
+ /* Attach main clock divide to FLEXCOMM0 (debug console). */\r
+ CLOCK_AttachClk( BOARD_DEBUG_UART_CLK_ATTACH );\r
+\r
+ /* Init board hardware. */\r
+ BOARD_InitPins();\r
+ BOARD_BootClockFROHF96M();\r
+ BOARD_InitDebugConsole();\r
+\r
+ /* Boot the non-secure code. */\r
+ PRINTF( "Booting Non-Secure World.\r\n" );\r
+ prvBootNonSecure( mainNONSECURE_APP_START_ADDRESS );\r
+\r
+ /* Non-secure software does not return, this code is not executed. */\r
+ for( ; ; )\r
+ {\r
+ /* Should not reach here. */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
static void prvBootNonSecure( uint32_t ulNonSecureStartAddress )\r
{\r
NonSecureResetHandler_t pxNonSecureResetHandler;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-/* Secure main(). */\r
-int main(void)\r
-{\r
- PRINTF( "Booting Secure World.\r\n" );\r
-\r
- /* Attach main clock divide to FLEXCOMM0 (debug console). */\r
- CLOCK_AttachClk( BOARD_DEBUG_UART_CLK_ATTACH );\r
-\r
- /* Init board hardware. */\r
- BOARD_InitPins();\r
- BOARD_BootClockFROHF96M();\r
- BOARD_InitDebugConsole();\r
-\r
- /* Boot the non-secure code. */\r
- PRINTF( "Booting Non-Secure World.\r\n" );\r
- prvBootNonSecure( mainNONSECURE_APP_START_ADDRESS );\r
-\r
- /* Non-secure software does not return, this code is not executed. */\r
- for( ; ; )\r
- {\r
- /* Should not reach here. */\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
projects / freertos / commitdiff