source "arch/arm/mach-davinci/Kconfig"
-source "arch/arm/cpu/armv7/exynos/Kconfig"
+source "arch/arm/mach-exynos/Kconfig"
source "arch/arm/mach-highbank/Kconfig"
machine-$(CONFIG_ARCH_AT91) += at91
machine-$(CONFIG_ARCH_BCM283X) += bcm283x
machine-$(CONFIG_ARCH_DAVINCI) += davinci
+machine-$(CONFIG_ARCH_EXYNOS) += exynos
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
-obj-$(CONFIG_ARCH_EXYNOS) += exynos/
obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
obj-$(if $(filter mx5,$(SOC)),y) += mx5/
obj-$(CONFIG_MX6) += mx6/
+++ /dev/null
-if ARCH_EXYNOS
-
-choice
- prompt "EXYNOS board select"
- optional
-
-config TARGET_SMDKV310
- select SUPPORT_SPL
- bool "Exynos4210 SMDKV310 board"
- select OF_CONTROL
- select SPL_DISABLE_OF_CONTROL
-
-config TARGET_TRATS
- bool "Exynos4210 Trats board"
-
-config TARGET_S5PC210_UNIVERSAL
- bool "EXYNOS4210 Universal C210 board"
-
-config TARGET_ORIGEN
- bool "Exynos4412 Origen board"
- select SUPPORT_SPL
-
-config TARGET_TRATS2
- bool "Exynos4412 Trat2 board"
-
-config TARGET_ODROID
- bool "Exynos4412 Odroid board"
-
-config TARGET_ODROID_XU3
- bool "Exynos5422 Odroid board"
- select OF_CONTROL
- select SPL_DISABLE_OF_CONTROL
-
-config TARGET_ARNDALE
- bool "Exynos5250 Arndale board"
- select CPU_V7_HAS_NONSEC
- select CPU_V7_HAS_VIRT
- select SUPPORT_SPL
- select OF_CONTROL
- select SPL_DISABLE_OF_CONTROL
-
-config TARGET_SMDK5250
- bool "SMDK5250 board"
- select SUPPORT_SPL
- select OF_CONTROL
- select SPL_DISABLE_OF_CONTROL
-
-config TARGET_SNOW
- bool "Snow board"
- select SUPPORT_SPL
- select OF_CONTROL
- select SPL_DISABLE_OF_CONTROL
-
-config TARGET_SPRING
- bool "Spring board"
- select SUPPORT_SPL
- select OF_CONTROL
- select SPL_DISABLE_OF_CONTROL
-
-config TARGET_SMDK5420
- bool "SMDK5420 board"
- select SUPPORT_SPL
- select OF_CONTROL
- select SPL_DISABLE_OF_CONTROL
-
-config TARGET_PEACH_PI
- bool "Peach Pi board"
- select SUPPORT_SPL
- select OF_CONTROL
- select SPL_DISABLE_OF_CONTROL
-
-config TARGET_PEACH_PIT
- bool "Peach Pit board"
- select SUPPORT_SPL
- select OF_CONTROL
- select SPL_DISABLE_OF_CONTROL
-
-endchoice
-
-config SYS_SOC
- default "exynos"
-
-source "board/samsung/smdkv310/Kconfig"
-source "board/samsung/trats/Kconfig"
-source "board/samsung/universal_c210/Kconfig"
-source "board/samsung/origen/Kconfig"
-source "board/samsung/trats2/Kconfig"
-source "board/samsung/odroid/Kconfig"
-source "board/samsung/arndale/Kconfig"
-source "board/samsung/smdk5250/Kconfig"
-source "board/samsung/smdk5420/Kconfig"
-
-endif
+++ /dev/null
-#
-# Copyright (C) 2009 Samsung Electronics
-# Minkyu Kang <mk7.kang@samsung.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o
-
-obj-$(CONFIG_EXYNOS5420) += sec_boot.o
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
-obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
-obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
-obj-y += spl_boot.o
-obj-y += lowlevel_init.o
-endif
+++ /dev/null
-/*
- * Copyright (C) 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/periph.h>
-
-#define PLL_DIV_1024 1024
-#define PLL_DIV_65535 65535
-#define PLL_DIV_65536 65536
-/* *
- * This structure is to store the src bit, div bit and prediv bit
- * positions of the peripheral clocks of the src and div registers
- */
-struct clk_bit_info {
- enum periph_id id;
- int32_t src_mask;
- int32_t div_mask;
- int32_t prediv_mask;
- int8_t src_bit;
- int8_t div_bit;
- int8_t prediv_bit;
-};
-
-static struct clk_bit_info exynos5_bit_info[] = {
- /* periph id s_mask d_mask p_mask s_bit d_bit p_bit */
- {PERIPH_ID_UART0, 0xf, 0xf, -1, 0, 0, -1},
- {PERIPH_ID_UART1, 0xf, 0xf, -1, 4, 4, -1},
- {PERIPH_ID_UART2, 0xf, 0xf, -1, 8, 8, -1},
- {PERIPH_ID_UART3, 0xf, 0xf, -1, 12, 12, -1},
- {PERIPH_ID_I2C0, -1, 0x7, 0x7, -1, 24, 0},
- {PERIPH_ID_I2C1, -1, 0x7, 0x7, -1, 24, 0},
- {PERIPH_ID_I2C2, -1, 0x7, 0x7, -1, 24, 0},
- {PERIPH_ID_I2C3, -1, 0x7, 0x7, -1, 24, 0},
- {PERIPH_ID_I2C4, -1, 0x7, 0x7, -1, 24, 0},
- {PERIPH_ID_I2C5, -1, 0x7, 0x7, -1, 24, 0},
- {PERIPH_ID_I2C6, -1, 0x7, 0x7, -1, 24, 0},
- {PERIPH_ID_I2C7, -1, 0x7, 0x7, -1, 24, 0},
- {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 16, 0, 8},
- {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 20, 16, 24},
- {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 24, 0, 8},
- {PERIPH_ID_SDMMC0, 0xf, 0xf, 0xff, 0, 0, 8},
- {PERIPH_ID_SDMMC1, 0xf, 0xf, 0xff, 4, 16, 24},
- {PERIPH_ID_SDMMC2, 0xf, 0xf, 0xff, 8, 0, 8},
- {PERIPH_ID_SDMMC3, 0xf, 0xf, 0xff, 12, 16, 24},
- {PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4},
- {PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16},
- {PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 0, 0, 4},
- {PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 4, 12, 16},
- {PERIPH_ID_SDMMC4, 0xf, 0xf, 0xff, 16, 0, 8},
- {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 0, -1},
- {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 0, -1},
- {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 0, -1},
- {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 0, -1},
- {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 0, -1},
-
- {PERIPH_ID_NONE, -1, -1, -1, -1, -1, -1},
-};
-
-static struct clk_bit_info exynos542x_bit_info[] = {
- /* periph id s_mask d_mask p_mask s_bit d_bit p_bit */
- {PERIPH_ID_UART0, 0xf, 0xf, -1, 4, 8, -1},
- {PERIPH_ID_UART1, 0xf, 0xf, -1, 8, 12, -1},
- {PERIPH_ID_UART2, 0xf, 0xf, -1, 12, 16, -1},
- {PERIPH_ID_UART3, 0xf, 0xf, -1, 16, 20, -1},
- {PERIPH_ID_I2C0, -1, 0x3f, -1, -1, 8, -1},
- {PERIPH_ID_I2C1, -1, 0x3f, -1, -1, 8, -1},
- {PERIPH_ID_I2C2, -1, 0x3f, -1, -1, 8, -1},
- {PERIPH_ID_I2C3, -1, 0x3f, -1, -1, 8, -1},
- {PERIPH_ID_I2C4, -1, 0x3f, -1, -1, 8, -1},
- {PERIPH_ID_I2C5, -1, 0x3f, -1, -1, 8, -1},
- {PERIPH_ID_I2C6, -1, 0x3f, -1, -1, 8, -1},
- {PERIPH_ID_I2C7, -1, 0x3f, -1, -1, 8, -1},
- {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 20, 20, 8},
- {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 24, 24, 16},
- {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 28, 28, 24},
- {PERIPH_ID_SDMMC0, 0x7, 0x3ff, -1, 8, 0, -1},
- {PERIPH_ID_SDMMC1, 0x7, 0x3ff, -1, 12, 10, -1},
- {PERIPH_ID_SDMMC2, 0x7, 0x3ff, -1, 16, 20, -1},
- {PERIPH_ID_I2C8, -1, 0x3f, -1, -1, 8, -1},
- {PERIPH_ID_I2C9, -1, 0x3f, -1, -1, 8, -1},
- {PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4},
- {PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16},
- {PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 12, 16, 0},
- {PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 16, 20, 8},
- {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 28, -1},
- {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 28, -1},
- {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 28, -1},
- {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 28, -1},
- {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 28, -1},
- {PERIPH_ID_I2C10, -1, 0x3f, -1, -1, 8, -1},
-
- {PERIPH_ID_NONE, -1, -1, -1, -1, -1, -1},
-};
-
-/* Epll Clock division values to achive different frequency output */
-static struct set_epll_con_val exynos5_epll_div[] = {
- { 192000000, 0, 48, 3, 1, 0 },
- { 180000000, 0, 45, 3, 1, 0 },
- { 73728000, 1, 73, 3, 3, 47710 },
- { 67737600, 1, 90, 4, 3, 20762 },
- { 49152000, 0, 49, 3, 3, 9961 },
- { 45158400, 0, 45, 3, 3, 10381 },
- { 180633600, 0, 45, 3, 1, 10381 }
-};
-
-/* exynos: return pll clock frequency */
-static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
-{
- unsigned long m, p, s = 0, mask, fout;
- unsigned int div;
- unsigned int freq;
- /*
- * APLL_CON: MIDV [25:16]
- * MPLL_CON: MIDV [25:16]
- * EPLL_CON: MIDV [24:16]
- * VPLL_CON: MIDV [24:16]
- * BPLL_CON: MIDV [25:16]: Exynos5
- */
- if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
- pllreg == SPLL)
- mask = 0x3ff;
- else
- mask = 0x1ff;
-
- m = (r >> 16) & mask;
-
- /* PDIV [13:8] */
- p = (r >> 8) & 0x3f;
- /* SDIV [2:0] */
- s = r & 0x7;
-
- freq = CONFIG_SYS_CLK_FREQ;
-
- if (pllreg == EPLL || pllreg == RPLL) {
- k = k & 0xffff;
- /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
- fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
- } else if (pllreg == VPLL) {
- k = k & 0xfff;
-
- /*
- * Exynos4210
- * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
- *
- * Exynos4412
- * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
- *
- * Exynos5250
- * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
- */
- if (proid_is_exynos4210())
- div = PLL_DIV_1024;
- else if (proid_is_exynos4412())
- div = PLL_DIV_65535;
- else if (proid_is_exynos5250() || proid_is_exynos5420()
- || proid_is_exynos5800())
- div = PLL_DIV_65536;
- else
- return 0;
-
- fout = (m + k / div) * (freq / (p * (1 << s)));
- } else {
- /*
- * Exynos4412 / Exynos5250
- * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
- *
- * Exynos4210
- * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
- */
- if (proid_is_exynos4210())
- fout = m * (freq / (p * (1 << (s - 1))));
- else
- fout = m * (freq / (p * (1 << s)));
- }
- return fout;
-}
-
-/* exynos4: return pll clock frequency */
-static unsigned long exynos4_get_pll_clk(int pllreg)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
- unsigned long r, k = 0;
-
- switch (pllreg) {
- case APLL:
- r = readl(&clk->apll_con0);
- break;
- case MPLL:
- r = readl(&clk->mpll_con0);
- break;
- case EPLL:
- r = readl(&clk->epll_con0);
- k = readl(&clk->epll_con1);
- break;
- case VPLL:
- r = readl(&clk->vpll_con0);
- k = readl(&clk->vpll_con1);
- break;
- default:
- printf("Unsupported PLL (%d)\n", pllreg);
- return 0;
- }
-
- return exynos_get_pll_clk(pllreg, r, k);
-}
-
-/* exynos4x12: return pll clock frequency */
-static unsigned long exynos4x12_get_pll_clk(int pllreg)
-{
- struct exynos4x12_clock *clk =
- (struct exynos4x12_clock *)samsung_get_base_clock();
- unsigned long r, k = 0;
-
- switch (pllreg) {
- case APLL:
- r = readl(&clk->apll_con0);
- break;
- case MPLL:
- r = readl(&clk->mpll_con0);
- break;
- case EPLL:
- r = readl(&clk->epll_con0);
- k = readl(&clk->epll_con1);
- break;
- case VPLL:
- r = readl(&clk->vpll_con0);
- k = readl(&clk->vpll_con1);
- break;
- default:
- printf("Unsupported PLL (%d)\n", pllreg);
- return 0;
- }
-
- return exynos_get_pll_clk(pllreg, r, k);
-}
-
-/* exynos5: return pll clock frequency */
-static unsigned long exynos5_get_pll_clk(int pllreg)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned long r, k = 0, fout;
- unsigned int pll_div2_sel, fout_sel;
-
- switch (pllreg) {
- case APLL:
- r = readl(&clk->apll_con0);
- break;
- case MPLL:
- r = readl(&clk->mpll_con0);
- break;
- case EPLL:
- r = readl(&clk->epll_con0);
- k = readl(&clk->epll_con1);
- break;
- case VPLL:
- r = readl(&clk->vpll_con0);
- k = readl(&clk->vpll_con1);
- break;
- case BPLL:
- r = readl(&clk->bpll_con0);
- break;
- default:
- printf("Unsupported PLL (%d)\n", pllreg);
- return 0;
- }
-
- fout = exynos_get_pll_clk(pllreg, r, k);
-
- /* According to the user manual, in EVT1 MPLL and BPLL always gives
- * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
- if (pllreg == MPLL || pllreg == BPLL) {
- pll_div2_sel = readl(&clk->pll_div2_sel);
-
- switch (pllreg) {
- case MPLL:
- fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
- & MPLL_FOUT_SEL_MASK;
- break;
- case BPLL:
- fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
- & BPLL_FOUT_SEL_MASK;
- break;
- default:
- fout_sel = -1;
- break;
- }
-
- if (fout_sel == 0)
- fout /= 2;
- }
-
- return fout;
-}
-
-/* exynos542x: return pll clock frequency */
-static unsigned long exynos542x_get_pll_clk(int pllreg)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned long r, k = 0;
-
- switch (pllreg) {
- case APLL:
- r = readl(&clk->apll_con0);
- break;
- case MPLL:
- r = readl(&clk->mpll_con0);
- break;
- case EPLL:
- r = readl(&clk->epll_con0);
- k = readl(&clk->epll_con1);
- break;
- case VPLL:
- r = readl(&clk->vpll_con0);
- k = readl(&clk->vpll_con1);
- break;
- case BPLL:
- r = readl(&clk->bpll_con0);
- break;
- case RPLL:
- r = readl(&clk->rpll_con0);
- k = readl(&clk->rpll_con1);
- break;
- case SPLL:
- r = readl(&clk->spll_con0);
- break;
- default:
- printf("Unsupported PLL (%d)\n", pllreg);
- return 0;
- }
-
- return exynos_get_pll_clk(pllreg, r, k);
-}
-
-static struct clk_bit_info *get_clk_bit_info(int peripheral)
-{
- int i;
- struct clk_bit_info *info;
-
- if (proid_is_exynos5420() || proid_is_exynos5800())
- info = exynos542x_bit_info;
- else
- info = exynos5_bit_info;
-
- for (i = 0; info[i].id != PERIPH_ID_NONE; i++) {
- if (info[i].id == peripheral)
- break;
- }
-
- if (info[i].id == PERIPH_ID_NONE)
- debug("ERROR: Peripheral ID %d not found\n", peripheral);
-
- return &info[i];
-}
-
-static unsigned long exynos5_get_periph_rate(int peripheral)
-{
- struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
- unsigned long sclk = 0;
- unsigned int src = 0, div = 0, sub_div = 0;
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
-
- switch (peripheral) {
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- src = readl(&clk->src_peric0);
- div = readl(&clk->div_peric0);
- break;
- case PERIPH_ID_PWM0:
- case PERIPH_ID_PWM1:
- case PERIPH_ID_PWM2:
- case PERIPH_ID_PWM3:
- case PERIPH_ID_PWM4:
- src = readl(&clk->src_peric0);
- div = readl(&clk->div_peric3);
- break;
- case PERIPH_ID_I2S0:
- src = readl(&clk->src_mau);
- div = sub_div = readl(&clk->div_mau);
- case PERIPH_ID_SPI0:
- case PERIPH_ID_SPI1:
- src = readl(&clk->src_peric1);
- div = sub_div = readl(&clk->div_peric1);
- break;
- case PERIPH_ID_SPI2:
- src = readl(&clk->src_peric1);
- div = sub_div = readl(&clk->div_peric2);
- break;
- case PERIPH_ID_SPI3:
- case PERIPH_ID_SPI4:
- src = readl(&clk->sclk_src_isp);
- div = sub_div = readl(&clk->sclk_div_isp);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- src = readl(&clk->src_fsys);
- div = sub_div = readl(&clk->div_fsys1);
- break;
- case PERIPH_ID_SDMMC2:
- case PERIPH_ID_SDMMC3:
- src = readl(&clk->src_fsys);
- div = sub_div = readl(&clk->div_fsys2);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
- case PERIPH_ID_I2C5:
- case PERIPH_ID_I2C6:
- case PERIPH_ID_I2C7:
- src = EXYNOS_SRC_MPLL;
- div = readl(&clk->div_top1);
- sub_div = readl(&clk->div_top0);
- break;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return -1;
- };
-
- if (bit_info->src_bit >= 0)
- src = (src >> bit_info->src_bit) & bit_info->src_mask;
-
- switch (src) {
- case EXYNOS_SRC_MPLL:
- sclk = exynos5_get_pll_clk(MPLL);
- break;
- case EXYNOS_SRC_EPLL:
- sclk = exynos5_get_pll_clk(EPLL);
- break;
- case EXYNOS_SRC_VPLL:
- sclk = exynos5_get_pll_clk(VPLL);
- break;
- default:
- debug("%s: EXYNOS_SRC %d not supported\n", __func__, src);
- return 0;
- }
-
- /* Clock divider ratio for this peripheral */
- if (bit_info->div_bit >= 0)
- div = (div >> bit_info->div_bit) & bit_info->div_mask;
-
- /* Clock pre-divider ratio for this peripheral */
- if (bit_info->prediv_bit >= 0)
- sub_div = (sub_div >> bit_info->prediv_bit)
- & bit_info->prediv_mask;
-
- /* Calculate and return required clock rate */
- return (sclk / (div + 1)) / (sub_div + 1);
-}
-
-static unsigned long exynos542x_get_periph_rate(int peripheral)
-{
- struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
- unsigned long sclk = 0;
- unsigned int src = 0, div = 0, sub_div = 0;
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
-
- switch (peripheral) {
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- case PERIPH_ID_PWM0:
- case PERIPH_ID_PWM1:
- case PERIPH_ID_PWM2:
- case PERIPH_ID_PWM3:
- case PERIPH_ID_PWM4:
- src = readl(&clk->src_peric0);
- div = readl(&clk->div_peric0);
- break;
- case PERIPH_ID_SPI0:
- case PERIPH_ID_SPI1:
- case PERIPH_ID_SPI2:
- src = readl(&clk->src_peric1);
- div = readl(&clk->div_peric1);
- sub_div = readl(&clk->div_peric4);
- break;
- case PERIPH_ID_SPI3:
- case PERIPH_ID_SPI4:
- src = readl(&clk->src_isp);
- div = readl(&clk->div_isp1);
- sub_div = readl(&clk->div_isp1);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- case PERIPH_ID_SDMMC2:
- case PERIPH_ID_SDMMC3:
- src = readl(&clk->src_fsys);
- div = readl(&clk->div_fsys1);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
- case PERIPH_ID_I2C5:
- case PERIPH_ID_I2C6:
- case PERIPH_ID_I2C7:
- case PERIPH_ID_I2C8:
- case PERIPH_ID_I2C9:
- case PERIPH_ID_I2C10:
- src = EXYNOS542X_SRC_MPLL;
- div = readl(&clk->div_top1);
- break;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return -1;
- };
-
- if (bit_info->src_bit >= 0)
- src = (src >> bit_info->src_bit) & bit_info->src_mask;
-
- switch (src) {
- case EXYNOS542X_SRC_MPLL:
- sclk = exynos542x_get_pll_clk(MPLL);
- break;
- case EXYNOS542X_SRC_SPLL:
- sclk = exynos542x_get_pll_clk(SPLL);
- break;
- case EXYNOS542X_SRC_EPLL:
- sclk = exynos542x_get_pll_clk(EPLL);
- break;
- case EXYNOS542X_SRC_RPLL:
- sclk = exynos542x_get_pll_clk(RPLL);
- break;
- default:
- debug("%s: EXYNOS542X_SRC %d not supported", __func__, src);
- return 0;
- }
-
- /* Clock divider ratio for this peripheral */
- if (bit_info->div_bit >= 0)
- div = (div >> bit_info->div_bit) & bit_info->div_mask;
-
- /* Clock pre-divider ratio for this peripheral */
- if (bit_info->prediv_bit >= 0)
- sub_div = (sub_div >> bit_info->prediv_bit)
- & bit_info->prediv_mask;
-
- /* Calculate and return required clock rate */
- return (sclk / (div + 1)) / (sub_div + 1);
-}
-
-unsigned long clock_get_periph_rate(int peripheral)
-{
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos542x_get_periph_rate(peripheral);
- return exynos5_get_periph_rate(peripheral);
- } else {
- return 0;
- }
-}
-
-/* exynos4: return ARM clock frequency */
-static unsigned long exynos4_get_arm_clk(void)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
- unsigned long div;
- unsigned long armclk;
- unsigned int core_ratio;
- unsigned int core2_ratio;
-
- div = readl(&clk->div_cpu0);
-
- /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
- core_ratio = (div >> 0) & 0x7;
- core2_ratio = (div >> 28) & 0x7;
-
- armclk = get_pll_clk(APLL) / (core_ratio + 1);
- armclk /= (core2_ratio + 1);
-
- return armclk;
-}
-
-/* exynos4x12: return ARM clock frequency */
-static unsigned long exynos4x12_get_arm_clk(void)
-{
- struct exynos4x12_clock *clk =
- (struct exynos4x12_clock *)samsung_get_base_clock();
- unsigned long div;
- unsigned long armclk;
- unsigned int core_ratio;
- unsigned int core2_ratio;
-
- div = readl(&clk->div_cpu0);
-
- /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
- core_ratio = (div >> 0) & 0x7;
- core2_ratio = (div >> 28) & 0x7;
-
- armclk = get_pll_clk(APLL) / (core_ratio + 1);
- armclk /= (core2_ratio + 1);
-
- return armclk;
-}
-
-/* exynos5: return ARM clock frequency */
-static unsigned long exynos5_get_arm_clk(void)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned long div;
- unsigned long armclk;
- unsigned int arm_ratio;
- unsigned int arm2_ratio;
-
- div = readl(&clk->div_cpu0);
-
- /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
- arm_ratio = (div >> 0) & 0x7;
- arm2_ratio = (div >> 28) & 0x7;
-
- armclk = get_pll_clk(APLL) / (arm_ratio + 1);
- armclk /= (arm2_ratio + 1);
-
- return armclk;
-}
-
-/* exynos4: return pwm clock frequency */
-static unsigned long exynos4_get_pwm_clk(void)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
- unsigned long pclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- if (s5p_get_cpu_rev() == 0) {
- /*
- * CLK_SRC_PERIL0
- * PWM_SEL [27:24]
- */
- sel = readl(&clk->src_peril0);
- sel = (sel >> 24) & 0xf;
-
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_PERIL3
- * PWM_RATIO [3:0]
- */
- ratio = readl(&clk->div_peril3);
- ratio = ratio & 0xf;
- } else if (s5p_get_cpu_rev() == 1) {
- sclk = get_pll_clk(MPLL);
- ratio = 8;
- } else
- return 0;
-
- pclk = sclk / (ratio + 1);
-
- return pclk;
-}
-
-/* exynos4x12: return pwm clock frequency */
-static unsigned long exynos4x12_get_pwm_clk(void)
-{
- unsigned long pclk, sclk;
- unsigned int ratio;
-
- sclk = get_pll_clk(MPLL);
- ratio = 8;
-
- pclk = sclk / (ratio + 1);
-
- return pclk;
-}
-
-/* exynos4: return uart clock frequency */
-static unsigned long exynos4_get_uart_clk(int dev_index)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- /*
- * CLK_SRC_PERIL0
- * UART0_SEL [3:0]
- * UART1_SEL [7:4]
- * UART2_SEL [8:11]
- * UART3_SEL [12:15]
- * UART4_SEL [16:19]
- * UART5_SEL [23:20]
- */
- sel = readl(&clk->src_peril0);
- sel = (sel >> (dev_index << 2)) & 0xf;
-
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_PERIL0
- * UART0_RATIO [3:0]
- * UART1_RATIO [7:4]
- * UART2_RATIO [8:11]
- * UART3_RATIO [12:15]
- * UART4_RATIO [16:19]
- * UART5_RATIO [23:20]
- */
- ratio = readl(&clk->div_peril0);
- ratio = (ratio >> (dev_index << 2)) & 0xf;
-
- uclk = sclk / (ratio + 1);
-
- return uclk;
-}
-
-/* exynos4x12: return uart clock frequency */
-static unsigned long exynos4x12_get_uart_clk(int dev_index)
-{
- struct exynos4x12_clock *clk =
- (struct exynos4x12_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- /*
- * CLK_SRC_PERIL0
- * UART0_SEL [3:0]
- * UART1_SEL [7:4]
- * UART2_SEL [8:11]
- * UART3_SEL [12:15]
- * UART4_SEL [16:19]
- */
- sel = readl(&clk->src_peril0);
- sel = (sel >> (dev_index << 2)) & 0xf;
-
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_PERIL0
- * UART0_RATIO [3:0]
- * UART1_RATIO [7:4]
- * UART2_RATIO [8:11]
- * UART3_RATIO [12:15]
- * UART4_RATIO [16:19]
- */
- ratio = readl(&clk->div_peril0);
- ratio = (ratio >> (dev_index << 2)) & 0xf;
-
- uclk = sclk / (ratio + 1);
-
- return uclk;
-}
-
-static unsigned long exynos4_get_mmc_clk(int dev_index)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel, ratio, pre_ratio;
- int shift = 0;
-
- sel = readl(&clk->src_fsys);
- sel = (sel >> (dev_index << 2)) & 0xf;
-
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- switch (dev_index) {
- case 0:
- case 1:
- ratio = readl(&clk->div_fsys1);
- pre_ratio = readl(&clk->div_fsys1);
- break;
- case 2:
- case 3:
- ratio = readl(&clk->div_fsys2);
- pre_ratio = readl(&clk->div_fsys2);
- break;
- case 4:
- ratio = readl(&clk->div_fsys3);
- pre_ratio = readl(&clk->div_fsys3);
- break;
- default:
- return 0;
- }
-
- if (dev_index == 1 || dev_index == 3)
- shift = 16;
-
- ratio = (ratio >> shift) & 0xf;
- pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
- uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
-
- return uclk;
-}
-
-/* exynos4: set the mmc clock */
-static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
- unsigned int addr, clear_bit, set_bit;
-
- /*
- * CLK_DIV_FSYS1
- * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
- * CLK_DIV_FSYS2
- * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
- * CLK_DIV_FSYS3
- * MMC4_RATIO [3:0]
- */
- if (dev_index < 2) {
- addr = (unsigned int)&clk->div_fsys1;
- clear_bit = MASK_PRE_RATIO(dev_index);
- set_bit = SET_PRE_RATIO(dev_index, div);
- } else if (dev_index == 4) {
- addr = (unsigned int)&clk->div_fsys3;
- dev_index -= 4;
- /* MMC4 is controlled with the MMC4_RATIO value */
- clear_bit = MASK_RATIO(dev_index);
- set_bit = SET_RATIO(dev_index, div);
- } else {
- addr = (unsigned int)&clk->div_fsys2;
- dev_index -= 2;
- clear_bit = MASK_PRE_RATIO(dev_index);
- set_bit = SET_PRE_RATIO(dev_index, div);
- }
-
- clrsetbits_le32(addr, clear_bit, set_bit);
-}
-
-/* exynos5: set the mmc clock */
-static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned int addr;
-
- /*
- * CLK_DIV_FSYS1
- * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
- * CLK_DIV_FSYS2
- * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
- */
- if (dev_index < 2) {
- addr = (unsigned int)&clk->div_fsys1;
- } else {
- addr = (unsigned int)&clk->div_fsys2;
- dev_index -= 2;
- }
-
- clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
- (div & 0xff) << ((dev_index << 4) + 8));
-}
-
-/* exynos5: set the mmc clock */
-static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned int addr;
- unsigned int shift;
-
- /*
- * CLK_DIV_FSYS1
- * MMC0_RATIO [9:0]
- * MMC1_RATIO [19:10]
- * MMC2_RATIO [29:20]
- */
- addr = (unsigned int)&clk->div_fsys1;
- shift = dev_index * 10;
-
- clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
-}
-
-/* get_lcd_clk: return lcd clock frequency */
-static unsigned long exynos4_get_lcd_clk(void)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
- unsigned long pclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- /*
- * CLK_SRC_LCD0
- * FIMD0_SEL [3:0]
- */
- sel = readl(&clk->src_lcd0);
- sel = sel & 0xf;
-
- /*
- * 0x6: SCLK_MPLL
- * 0x7: SCLK_EPLL
- * 0x8: SCLK_VPLL
- */
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_LCD0
- * FIMD0_RATIO [3:0]
- */
- ratio = readl(&clk->div_lcd0);
- ratio = ratio & 0xf;
-
- pclk = sclk / (ratio + 1);
-
- return pclk;
-}
-
-/* get_lcd_clk: return lcd clock frequency */
-static unsigned long exynos5_get_lcd_clk(void)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned long pclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- /*
- * CLK_SRC_LCD0
- * FIMD0_SEL [3:0]
- */
- sel = readl(&clk->src_disp1_0);
- sel = sel & 0xf;
-
- /*
- * 0x6: SCLK_MPLL
- * 0x7: SCLK_EPLL
- * 0x8: SCLK_VPLL
- */
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_LCD0
- * FIMD0_RATIO [3:0]
- */
- ratio = readl(&clk->div_disp1_0);
- ratio = ratio & 0xf;
-
- pclk = sclk / (ratio + 1);
-
- return pclk;
-}
-
-static unsigned long exynos5420_get_lcd_clk(void)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned long pclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- /*
- * CLK_SRC_DISP10
- * FIMD1_SEL [4]
- * 0: SCLK_RPLL
- * 1: SCLK_SPLL
- */
- sel = readl(&clk->src_disp10);
- sel &= (1 << 4);
-
- if (sel)
- sclk = get_pll_clk(SPLL);
- else
- sclk = get_pll_clk(RPLL);
-
- /*
- * CLK_DIV_DISP10
- * FIMD1_RATIO [3:0]
- */
- ratio = readl(&clk->div_disp10);
- ratio = ratio & 0xf;
-
- pclk = sclk / (ratio + 1);
-
- return pclk;
-}
-
-static unsigned long exynos5800_get_lcd_clk(void)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned long sclk;
- unsigned int sel;
- unsigned int ratio;
-
- /*
- * CLK_SRC_DISP10
- * CLKMUX_FIMD1 [6:4]
- */
- sel = (readl(&clk->src_disp10) >> 4) & 0x7;
-
- if (sel) {
- /*
- * Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into
- * PLLs. The first element is a placeholder to bypass the
- * default settig.
- */
- const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL,
- RPLL};
- sclk = get_pll_clk(reg_map[sel]);
- } else
- sclk = CONFIG_SYS_CLK_FREQ;
- /*
- * CLK_DIV_DISP10
- * FIMD1_RATIO [3:0]
- */
- ratio = readl(&clk->div_disp10) & 0xf;
-
- return sclk / (ratio + 1);
-}
-
-void exynos4_set_lcd_clk(void)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
-
- /*
- * CLK_GATE_BLOCK
- * CLK_CAM [0]
- * CLK_TV [1]
- * CLK_MFC [2]
- * CLK_G3D [3]
- * CLK_LCD0 [4]
- * CLK_LCD1 [5]
- * CLK_GPS [7]
- */
- setbits_le32(&clk->gate_block, 1 << 4);
-
- /*
- * CLK_SRC_LCD0
- * FIMD0_SEL [3:0]
- * MDNIE0_SEL [7:4]
- * MDNIE_PWM0_SEL [8:11]
- * MIPI0_SEL [12:15]
- * set lcd0 src clock 0x6: SCLK_MPLL
- */
- clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
-
- /*
- * CLK_GATE_IP_LCD0
- * CLK_FIMD0 [0]
- * CLK_MIE0 [1]
- * CLK_MDNIE0 [2]
- * CLK_DSIM0 [3]
- * CLK_SMMUFIMD0 [4]
- * CLK_PPMULCD0 [5]
- * Gating all clocks for FIMD0
- */
- setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
-
- /*
- * CLK_DIV_LCD0
- * FIMD0_RATIO [3:0]
- * MDNIE0_RATIO [7:4]
- * MDNIE_PWM0_RATIO [11:8]
- * MDNIE_PWM_PRE_RATIO [15:12]
- * MIPI0_RATIO [19:16]
- * MIPI0_PRE_RATIO [23:20]
- * set fimd ratio
- */
- clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
-}
-
-void exynos5_set_lcd_clk(void)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
-
- /*
- * CLK_GATE_BLOCK
- * CLK_CAM [0]
- * CLK_TV [1]
- * CLK_MFC [2]
- * CLK_G3D [3]
- * CLK_LCD0 [4]
- * CLK_LCD1 [5]
- * CLK_GPS [7]
- */
- setbits_le32(&clk->gate_block, 1 << 4);
-
- /*
- * CLK_SRC_LCD0
- * FIMD0_SEL [3:0]
- * MDNIE0_SEL [7:4]
- * MDNIE_PWM0_SEL [8:11]
- * MIPI0_SEL [12:15]
- * set lcd0 src clock 0x6: SCLK_MPLL
- */
- clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);
-
- /*
- * CLK_GATE_IP_LCD0
- * CLK_FIMD0 [0]
- * CLK_MIE0 [1]
- * CLK_MDNIE0 [2]
- * CLK_DSIM0 [3]
- * CLK_SMMUFIMD0 [4]
- * CLK_PPMULCD0 [5]
- * Gating all clocks for FIMD0
- */
- setbits_le32(&clk->gate_ip_disp1, 1 << 0);
-
- /*
- * CLK_DIV_LCD0
- * FIMD0_RATIO [3:0]
- * MDNIE0_RATIO [7:4]
- * MDNIE_PWM0_RATIO [11:8]
- * MDNIE_PWM_PRE_RATIO [15:12]
- * MIPI0_RATIO [19:16]
- * MIPI0_PRE_RATIO [23:20]
- * set fimd ratio
- */
- clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
-}
-
-void exynos5420_set_lcd_clk(void)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned int cfg;
-
- /*
- * CLK_SRC_DISP10
- * FIMD1_SEL [4]
- * 0: SCLK_RPLL
- * 1: SCLK_SPLL
- */
- cfg = readl(&clk->src_disp10);
- cfg &= ~(0x1 << 4);
- cfg |= (0 << 4);
- writel(cfg, &clk->src_disp10);
-
- /*
- * CLK_DIV_DISP10
- * FIMD1_RATIO [3:0]
- */
- cfg = readl(&clk->div_disp10);
- cfg &= ~(0xf << 0);
- cfg |= (0 << 0);
- writel(cfg, &clk->div_disp10);
-}
-
-void exynos5800_set_lcd_clk(void)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned int cfg;
-
- /*
- * Use RPLL for pixel clock
- * CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]
- * ==================
- * 111: SCLK_RPLL
- */
- cfg = readl(&clk->src_disp10) | (0x7 << 4);
- writel(cfg, &clk->src_disp10);
-
- /*
- * CLK_DIV_DISP10
- * FIMD1_RATIO [3:0]
- */
- clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0);
-}
-
-void exynos4_set_mipi_clk(void)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
-
- /*
- * CLK_SRC_LCD0
- * FIMD0_SEL [3:0]
- * MDNIE0_SEL [7:4]
- * MDNIE_PWM0_SEL [8:11]
- * MIPI0_SEL [12:15]
- * set mipi0 src clock 0x6: SCLK_MPLL
- */
- clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);
-
- /*
- * CLK_SRC_MASK_LCD0
- * FIMD0_MASK [0]
- * MDNIE0_MASK [4]
- * MDNIE_PWM0_MASK [8]
- * MIPI0_MASK [12]
- * set src mask mipi0 0x1: Unmask
- */
- setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
-
- /*
- * CLK_GATE_IP_LCD0
- * CLK_FIMD0 [0]
- * CLK_MIE0 [1]
- * CLK_MDNIE0 [2]
- * CLK_DSIM0 [3]
- * CLK_SMMUFIMD0 [4]
- * CLK_PPMULCD0 [5]
- * Gating all clocks for MIPI0
- */
- setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
-
- /*
- * CLK_DIV_LCD0
- * FIMD0_RATIO [3:0]
- * MDNIE0_RATIO [7:4]
- * MDNIE_PWM0_RATIO [11:8]
- * MDNIE_PWM_PRE_RATIO [15:12]
- * MIPI0_RATIO [19:16]
- * MIPI0_PRE_RATIO [23:20]
- * set mipi ratio
- */
- clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
-}
-
-int exynos5_set_epll_clk(unsigned long rate)
-{
- unsigned int epll_con, epll_con_k;
- unsigned int i;
- unsigned int lockcnt;
- unsigned int start;
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
-
- epll_con = readl(&clk->epll_con0);
- epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
- EPLL_CON0_LOCK_DET_EN_SHIFT) |
- EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
- EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
- EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
-
- for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
- if (exynos5_epll_div[i].freq_out == rate)
- break;
- }
-
- if (i == ARRAY_SIZE(exynos5_epll_div))
- return -1;
-
- epll_con_k = exynos5_epll_div[i].k_dsm << 0;
- epll_con |= exynos5_epll_div[i].en_lock_det <<
- EPLL_CON0_LOCK_DET_EN_SHIFT;
- epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
- epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
- epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
-
- /*
- * Required period ( in cycles) to genarate a stable clock output.
- * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
- * frequency input (as per spec)
- */
- lockcnt = 3000 * exynos5_epll_div[i].p_div;
-
- writel(lockcnt, &clk->epll_lock);
- writel(epll_con, &clk->epll_con0);
- writel(epll_con_k, &clk->epll_con1);
-
- start = get_timer(0);
-
- while (!(readl(&clk->epll_con0) &
- (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
- if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
- debug("%s: Timeout waiting for EPLL lock\n", __func__);
- return -1;
- }
- }
- return 0;
-}
-
-int exynos5_set_i2s_clk_source(unsigned int i2s_id)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned int *audio_ass = (unsigned int *)samsung_get_base_audio_ass();
-
- if (i2s_id == 0) {
- setbits_le32(&clk->src_top2, CLK_SRC_MOUT_EPLL);
- clrsetbits_le32(&clk->src_mau, AUDIO0_SEL_MASK,
- (CLK_SRC_SCLK_EPLL));
- setbits_le32(audio_ass, AUDIO_CLKMUX_ASS);
- } else if (i2s_id == 1) {
- clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
- (CLK_SRC_SCLK_EPLL));
- } else {
- return -1;
- }
- return 0;
-}
-
-int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
- unsigned int dst_frq,
- unsigned int i2s_id)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned int div;
-
- if ((dst_frq == 0) || (src_frq == 0)) {
- debug("%s: Invalid requency input for prescaler\n", __func__);
- debug("src frq = %d des frq = %d ", src_frq, dst_frq);
- return -1;
- }
-
- div = (src_frq / dst_frq);
- if (i2s_id == 0) {
- if (div > AUDIO_0_RATIO_MASK) {
- debug("%s: Frequency ratio is out of range\n",
- __func__);
- debug("src frq = %d des frq = %d ", src_frq, dst_frq);
- return -1;
- }
- clrsetbits_le32(&clk->div_mau, AUDIO_0_RATIO_MASK,
- (div & AUDIO_0_RATIO_MASK));
- } else if (i2s_id == 1) {
- if (div > AUDIO_1_RATIO_MASK) {
- debug("%s: Frequency ratio is out of range\n",
- __func__);
- debug("src frq = %d des frq = %d ", src_frq, dst_frq);
- return -1;
- }
- clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
- (div & AUDIO_1_RATIO_MASK));
- } else {
- return -1;
- }
- return 0;
-}
-
-/**
- * Linearly searches for the most accurate main and fine stage clock scalars
- * (divisors) for a specified target frequency and scalar bit sizes by checking
- * all multiples of main_scalar_bits values. Will always return scalars up to or
- * slower than target.
- *
- * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
- * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
- * @param input_freq Clock frequency to be scaled in Hz
- * @param target_freq Desired clock frequency in Hz
- * @param best_fine_scalar Pointer to store the fine stage divisor
- *
- * @return best_main_scalar Main scalar for desired frequency or -1 if none
- * found
- */
-static int clock_calc_best_scalar(unsigned int main_scaler_bits,
- unsigned int fine_scalar_bits, unsigned int input_rate,
- unsigned int target_rate, unsigned int *best_fine_scalar)
-{
- int i;
- int best_main_scalar = -1;
- unsigned int best_error = target_rate;
- const unsigned int cap = (1 << fine_scalar_bits) - 1;
- const unsigned int loops = 1 << main_scaler_bits;
-
- debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
- target_rate, cap);
-
- assert(best_fine_scalar != NULL);
- assert(main_scaler_bits <= fine_scalar_bits);
-
- *best_fine_scalar = 1;
-
- if (input_rate == 0 || target_rate == 0)
- return -1;
-
- if (target_rate >= input_rate)
- return 1;
-
- for (i = 1; i <= loops; i++) {
- const unsigned int effective_div =
- max(min(input_rate / i / target_rate, cap), 1U);
- const unsigned int effective_rate = input_rate / i /
- effective_div;
- const int error = target_rate - effective_rate;
-
- debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
- effective_rate, error);
-
- if (error >= 0 && error <= best_error) {
- best_error = error;
- best_main_scalar = i;
- *best_fine_scalar = effective_div;
- }
- }
-
- return best_main_scalar;
-}
-
-static int exynos5_set_spi_clk(enum periph_id periph_id,
- unsigned int rate)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- int main;
- unsigned int fine;
- unsigned shift, pre_shift;
- unsigned mask = 0xff;
- u32 *reg;
-
- main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
- if (main < 0) {
- debug("%s: Cannot set clock rate for periph %d",
- __func__, periph_id);
- return -1;
- }
- main = main - 1;
- fine = fine - 1;
-
- switch (periph_id) {
- case PERIPH_ID_SPI0:
- reg = &clk->div_peric1;
- shift = 0;
- pre_shift = 8;
- break;
- case PERIPH_ID_SPI1:
- reg = &clk->div_peric1;
- shift = 16;
- pre_shift = 24;
- break;
- case PERIPH_ID_SPI2:
- reg = &clk->div_peric2;
- shift = 0;
- pre_shift = 8;
- break;
- case PERIPH_ID_SPI3:
- reg = &clk->sclk_div_isp;
- shift = 0;
- pre_shift = 4;
- break;
- case PERIPH_ID_SPI4:
- reg = &clk->sclk_div_isp;
- shift = 12;
- pre_shift = 16;
- break;
- default:
- debug("%s: Unsupported peripheral ID %d\n", __func__,
- periph_id);
- return -1;
- }
- clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
- clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
-
- return 0;
-}
-
-static int exynos5420_set_spi_clk(enum periph_id periph_id,
- unsigned int rate)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- int main;
- unsigned int fine;
- unsigned shift, pre_shift;
- unsigned div_mask = 0xf, pre_div_mask = 0xff;
- u32 *reg;
- u32 *pre_reg;
-
- main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
- if (main < 0) {
- debug("%s: Cannot set clock rate for periph %d",
- __func__, periph_id);
- return -1;
- }
- main = main - 1;
- fine = fine - 1;
-
- switch (periph_id) {
- case PERIPH_ID_SPI0:
- reg = &clk->div_peric1;
- shift = 20;
- pre_reg = &clk->div_peric4;
- pre_shift = 8;
- break;
- case PERIPH_ID_SPI1:
- reg = &clk->div_peric1;
- shift = 24;
- pre_reg = &clk->div_peric4;
- pre_shift = 16;
- break;
- case PERIPH_ID_SPI2:
- reg = &clk->div_peric1;
- shift = 28;
- pre_reg = &clk->div_peric4;
- pre_shift = 24;
- break;
- case PERIPH_ID_SPI3:
- reg = &clk->div_isp1;
- shift = 16;
- pre_reg = &clk->div_isp1;
- pre_shift = 0;
- break;
- case PERIPH_ID_SPI4:
- reg = &clk->div_isp1;
- shift = 20;
- pre_reg = &clk->div_isp1;
- pre_shift = 8;
- break;
- default:
- debug("%s: Unsupported peripheral ID %d\n", __func__,
- periph_id);
- return -1;
- }
-
- clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift);
- clrsetbits_le32(pre_reg, pre_div_mask << pre_shift,
- (fine & pre_div_mask) << pre_shift);
-
- return 0;
-}
-
-static unsigned long exynos4_get_i2c_clk(void)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
- unsigned long sclk, aclk_100;
- unsigned int ratio;
-
- sclk = get_pll_clk(APLL);
-
- ratio = (readl(&clk->div_top)) >> 4;
- ratio &= 0xf;
- aclk_100 = sclk / (ratio + 1);
- return aclk_100;
-}
-
-unsigned long get_pll_clk(int pllreg)
-{
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos542x_get_pll_clk(pllreg);
- return exynos5_get_pll_clk(pllreg);
- } else if (cpu_is_exynos4()) {
- if (proid_is_exynos4412())
- return exynos4x12_get_pll_clk(pllreg);
- return exynos4_get_pll_clk(pllreg);
- }
-
- return 0;
-}
-
-unsigned long get_arm_clk(void)
-{
- if (cpu_is_exynos5()) {
- return exynos5_get_arm_clk();
- } else if (cpu_is_exynos4()) {
- if (proid_is_exynos4412())
- return exynos4x12_get_arm_clk();
- return exynos4_get_arm_clk();
- }
-
- return 0;
-}
-
-unsigned long get_i2c_clk(void)
-{
- if (cpu_is_exynos5())
- return clock_get_periph_rate(PERIPH_ID_I2C0);
- else if (cpu_is_exynos4())
- return exynos4_get_i2c_clk();
-
- return 0;
-}
-
-unsigned long get_pwm_clk(void)
-{
- if (cpu_is_exynos5()) {
- return clock_get_periph_rate(PERIPH_ID_PWM0);
- } else if (cpu_is_exynos4()) {
- if (proid_is_exynos4412())
- return exynos4x12_get_pwm_clk();
- return exynos4_get_pwm_clk();
- }
-
- return 0;
-}
-
-unsigned long get_uart_clk(int dev_index)
-{
- enum periph_id id;
-
- switch (dev_index) {
- case 0:
- id = PERIPH_ID_UART0;
- break;
- case 1:
- id = PERIPH_ID_UART1;
- break;
- case 2:
- id = PERIPH_ID_UART2;
- break;
- case 3:
- id = PERIPH_ID_UART3;
- break;
- default:
- debug("%s: invalid UART index %d", __func__, dev_index);
- return -1;
- }
-
- if (cpu_is_exynos5()) {
- return clock_get_periph_rate(id);
- } else if (cpu_is_exynos4()) {
- if (proid_is_exynos4412())
- return exynos4x12_get_uart_clk(dev_index);
- return exynos4_get_uart_clk(dev_index);
- }
-
- return 0;
-}
-
-unsigned long get_mmc_clk(int dev_index)
-{
- enum periph_id id;
-
- switch (dev_index) {
- case 0:
- id = PERIPH_ID_SDMMC0;
- break;
- case 1:
- id = PERIPH_ID_SDMMC1;
- break;
- case 2:
- id = PERIPH_ID_SDMMC2;
- break;
- case 3:
- id = PERIPH_ID_SDMMC3;
- break;
- default:
- debug("%s: invalid MMC index %d", __func__, dev_index);
- return -1;
- }
-
- if (cpu_is_exynos5())
- return clock_get_periph_rate(id);
- else if (cpu_is_exynos4())
- return exynos4_get_mmc_clk(dev_index);
-
- return 0;
-}
-
-void set_mmc_clk(int dev_index, unsigned int div)
-{
- /* If want to set correct value, it needs to substract one from div.*/
- if (div > 0)
- div -= 1;
-
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- exynos5420_set_mmc_clk(dev_index, div);
- else
- exynos5_set_mmc_clk(dev_index, div);
- } else if (cpu_is_exynos4()) {
- exynos4_set_mmc_clk(dev_index, div);
- }
-}
-
-unsigned long get_lcd_clk(void)
-{
- if (cpu_is_exynos4()) {
- return exynos4_get_lcd_clk();
- } else if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
- return exynos5420_get_lcd_clk();
- else if (proid_is_exynos5800())
- return exynos5800_get_lcd_clk();
- else
- return exynos5_get_lcd_clk();
- }
-
- return 0;
-}
-
-void set_lcd_clk(void)
-{
- if (cpu_is_exynos4()) {
- exynos4_set_lcd_clk();
- } else if (cpu_is_exynos5()) {
- if (proid_is_exynos5250())
- exynos5_set_lcd_clk();
- else if (proid_is_exynos5420())
- exynos5420_set_lcd_clk();
- else
- exynos5800_set_lcd_clk();
- }
-}
-
-void set_mipi_clk(void)
-{
- if (cpu_is_exynos4())
- exynos4_set_mipi_clk();
-}
-
-int set_spi_clk(int periph_id, unsigned int rate)
-{
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_set_spi_clk(periph_id, rate);
- return exynos5_set_spi_clk(periph_id, rate);
- }
-
- return 0;
-}
-
-int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
- unsigned int i2s_id)
-{
- if (cpu_is_exynos5())
- return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq, i2s_id);
-
- return 0;
-}
-
-int set_i2s_clk_source(unsigned int i2s_id)
-{
- if (cpu_is_exynos5())
- return exynos5_set_i2s_clk_source(i2s_id);
-
- return 0;
-}
-
-int set_epll_clk(unsigned long rate)
-{
- if (cpu_is_exynos5())
- return exynos5_set_epll_clk(rate);
-
- return 0;
-}
+++ /dev/null
-/*
- * Clock initialization routines
- *
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __EXYNOS_CLOCK_INIT_H
-#define __EXYNOS_CLOCK_INIT_H
-
-enum {
-#ifdef CONFIG_EXYNOS5420
- MEM_TIMINGS_MSR_COUNT = 5,
-#else
- MEM_TIMINGS_MSR_COUNT = 4,
-#endif
-};
-
-/* These are the ratio's for configuring ARM clock */
-struct arm_clk_ratios {
- unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */
-
- unsigned apll_mdiv;
- unsigned apll_pdiv;
- unsigned apll_sdiv;
-
- unsigned arm2_ratio;
- unsigned apll_ratio;
- unsigned pclk_dbg_ratio;
- unsigned atb_ratio;
- unsigned periph_ratio;
- unsigned acp_ratio;
- unsigned cpud_ratio;
- unsigned arm_ratio;
-};
-
-/* These are the memory timings for a particular memory type and speed */
-struct mem_timings {
- enum mem_manuf mem_manuf; /* Memory manufacturer */
- enum ddr_mode mem_type; /* Memory type */
- unsigned frequency_mhz; /* Frequency of memory in MHz */
-
- /* Here follow the timing parameters for the selected memory */
- unsigned apll_mdiv;
- unsigned apll_pdiv;
- unsigned apll_sdiv;
- unsigned mpll_mdiv;
- unsigned mpll_pdiv;
- unsigned mpll_sdiv;
- unsigned cpll_mdiv;
- unsigned cpll_pdiv;
- unsigned cpll_sdiv;
- unsigned gpll_mdiv;
- unsigned gpll_pdiv;
- unsigned gpll_sdiv;
- unsigned epll_mdiv;
- unsigned epll_pdiv;
- unsigned epll_sdiv;
- unsigned vpll_mdiv;
- unsigned vpll_pdiv;
- unsigned vpll_sdiv;
- unsigned bpll_mdiv;
- unsigned bpll_pdiv;
- unsigned bpll_sdiv;
- unsigned kpll_mdiv;
- unsigned kpll_pdiv;
- unsigned kpll_sdiv;
- unsigned dpll_mdiv;
- unsigned dpll_pdiv;
- unsigned dpll_sdiv;
- unsigned ipll_mdiv;
- unsigned ipll_pdiv;
- unsigned ipll_sdiv;
- unsigned spll_mdiv;
- unsigned spll_pdiv;
- unsigned spll_sdiv;
- unsigned rpll_mdiv;
- unsigned rpll_pdiv;
- unsigned rpll_sdiv;
- unsigned pclk_cdrex_ratio;
- unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
-
- unsigned timing_ref;
- unsigned timing_row;
- unsigned timing_data;
- unsigned timing_power;
-
- /* DQS, DQ, DEBUG offsets */
- unsigned phy0_dqs;
- unsigned phy1_dqs;
- unsigned phy0_dq;
- unsigned phy1_dq;
- unsigned phy0_tFS;
- unsigned phy1_tFS;
- unsigned phy0_pulld_dqs;
- unsigned phy1_pulld_dqs;
-
- unsigned lpddr3_ctrl_phy_reset;
- unsigned ctrl_start_point;
- unsigned ctrl_inc;
- unsigned ctrl_start;
- unsigned ctrl_dll_on;
- unsigned ctrl_ref;
-
- unsigned ctrl_force;
- unsigned ctrl_rdlat;
- unsigned ctrl_bstlen;
-
- unsigned fp_resync;
- unsigned iv_size;
- unsigned dfi_init_start;
- unsigned aref_en;
-
- unsigned rd_fetch;
-
- unsigned zq_mode_dds;
- unsigned zq_mode_term;
- unsigned zq_mode_noterm; /* 1 to allow termination disable */
-
- unsigned memcontrol;
- unsigned memconfig;
-
- unsigned membaseconfig0;
- unsigned membaseconfig1;
- unsigned prechconfig_tp_cnt;
- unsigned dpwrdn_cyc;
- unsigned dsref_cyc;
- unsigned concontrol;
- /* Channel and Chip Selection */
- uint8_t dmc_channels; /* number of memory channels */
- uint8_t chips_per_channel; /* number of chips per channel */
- uint8_t chips_to_configure; /* number of chips to configure */
- uint8_t send_zq_init; /* 1 to send this command */
- unsigned impedance; /* drive strength impedeance */
- uint8_t gate_leveling_enable; /* check gate leveling is enabled */
- uint8_t read_leveling_enable; /* check h/w read leveling is enabled */
-};
-
-/**
- * Get the correct memory timings for our selected memory type and speed.
- *
- * This function can be called from SPL or the main U-Boot.
- *
- * @return pointer to the memory timings that we should use
- */
-struct mem_timings *clock_get_mem_timings(void);
-
-/*
- * Initialize clock for the device
- */
-void system_clock_init(void);
-
-/*
- * Set clock divisor value for booting from EMMC.
- */
-void emmc_boot_clk_div_set(void);
-#endif
+++ /dev/null
-/*
- * Clock Initialization for board based on EXYNOS4210
- *
- * Copyright (C) 2013 Samsung Electronics
- * Rajeshwari Shinde <rajeshwari.s@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/clock.h>
-#include "common_setup.h"
-#include "exynos4_setup.h"
-
-/*
- * system_clock_init: Initialize core clock and bus clock.
- * void system_clock_init(void)
- */
-void system_clock_init(void)
-{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
-
- writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
-
- sdelay(0x10000);
-
- writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
- writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
- writel(CLK_SRC_DMC_VAL, &clk->src_dmc);
- writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus);
- writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus);
- writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
- writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0);
- writel(CLK_SRC_CAM_VAL, &clk->src_cam);
- writel(CLK_SRC_MFC_VAL, &clk->src_mfc);
- writel(CLK_SRC_G3D_VAL, &clk->src_g3d);
- writel(CLK_SRC_LCD0_VAL, &clk->src_lcd0);
-
- sdelay(0x10000);
-
- writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
- writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
- writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0);
- writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1);
- writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus);
- writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus);
- writel(CLK_DIV_TOP_VAL, &clk->div_top);
- writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
- writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
- writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
- writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0);
- writel(CLK_DIV_CAM_VAL, &clk->div_cam);
- writel(CLK_DIV_MFC_VAL, &clk->div_mfc);
- writel(CLK_DIV_G3D_VAL, &clk->div_g3d);
- writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0);
-
- /* Set PLL locktime */
- writel(PLL_LOCKTIME, &clk->apll_lock);
- writel(PLL_LOCKTIME, &clk->mpll_lock);
- writel(PLL_LOCKTIME, &clk->epll_lock);
- writel(PLL_LOCKTIME, &clk->vpll_lock);
-
- writel(APLL_CON1_VAL, &clk->apll_con1);
- writel(APLL_CON0_VAL, &clk->apll_con0);
- writel(MPLL_CON1_VAL, &clk->mpll_con1);
- writel(MPLL_CON0_VAL, &clk->mpll_con0);
- writel(EPLL_CON1_VAL, &clk->epll_con1);
- writel(EPLL_CON0_VAL, &clk->epll_con0);
- writel(VPLL_CON1_VAL, &clk->vpll_con1);
- writel(VPLL_CON0_VAL, &clk->vpll_con0);
-
- sdelay(0x30000);
-}
+++ /dev/null
-/*
- * Clock setup for SMDK5250 board based on EXYNOS5
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/spl.h>
-#include <asm/arch/dwmmc.h>
-
-#include "clock_init.h"
-#include "common_setup.h"
-#include "exynos5_setup.h"
-
-#define FSYS1_MMC0_DIV_MASK 0xff0f
-#define FSYS1_MMC0_DIV_VAL 0x0701
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct arm_clk_ratios arm_clk_ratios[] = {
-#ifdef CONFIG_EXYNOS5420
- {
- .arm_freq_mhz = 900,
-
- .apll_mdiv = 0x96,
- .apll_pdiv = 0x2,
- .apll_sdiv = 0x1,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x3,
- .pclk_dbg_ratio = 0x6,
- .atb_ratio = 0x6,
- .periph_ratio = 0x7,
- .acp_ratio = 0x0,
- .cpud_ratio = 0x2,
- .arm_ratio = 0x0,
- }
-#else
- {
- .arm_freq_mhz = 600,
-
- .apll_mdiv = 0xc8,
- .apll_pdiv = 0x4,
- .apll_sdiv = 0x1,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x1,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x2,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x1,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 800,
-
- .apll_mdiv = 0x64,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x1,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x3,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x2,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1000,
-
- .apll_mdiv = 0x7d,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x1,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x4,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x2,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1200,
-
- .apll_mdiv = 0x96,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x3,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x5,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x3,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1400,
-
- .apll_mdiv = 0xaf,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x3,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x6,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x3,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1700,
-
- .apll_mdiv = 0x1a9,
- .apll_pdiv = 0x6,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x3,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x6,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x3,
- .arm_ratio = 0x0,
- }
-#endif
-};
-
-struct mem_timings mem_timings[] = {
-#ifdef CONFIG_EXYNOS5420
- {
- .mem_manuf = MEM_MANUF_SAMSUNG,
- .mem_type = DDR_MODE_DDR3,
- .frequency_mhz = 800,
-
- /* MPLL @800MHz*/
- .mpll_mdiv = 0xc8,
- .mpll_pdiv = 0x3,
- .mpll_sdiv = 0x1,
- /* CPLL @666MHz */
- .cpll_mdiv = 0xde,
- .cpll_pdiv = 0x4,
- .cpll_sdiv = 0x1,
- /* EPLL @600MHz */
- .epll_mdiv = 0x64,
- .epll_pdiv = 0x2,
- .epll_sdiv = 0x1,
- /* VPLL @430MHz */
- .vpll_mdiv = 0xd7,
- .vpll_pdiv = 0x3,
- .vpll_sdiv = 0x2,
- /* BPLL @800MHz */
- .bpll_mdiv = 0xc8,
- .bpll_pdiv = 0x3,
- .bpll_sdiv = 0x1,
- /* KPLL @600MHz */
- .kpll_mdiv = 0x190,
- .kpll_pdiv = 0x4,
- .kpll_sdiv = 0x2,
- /* DPLL @600MHz */
- .dpll_mdiv = 0x190,
- .dpll_pdiv = 0x4,
- .dpll_sdiv = 0x2,
- /* IPLL @370MHz */
- .ipll_mdiv = 0xb9,
- .ipll_pdiv = 0x3,
- .ipll_sdiv = 0x2,
- /* SPLL @400MHz */
- .spll_mdiv = 0xc8,
- .spll_pdiv = 0x3,
- .spll_sdiv = 0x2,
- /* RPLL @141Mhz */
- .rpll_mdiv = 0x5E,
- .rpll_pdiv = 0x2,
- .rpll_sdiv = 0x3,
-
- .direct_cmd_msr = {
- 0x00020018, 0x00030000, 0x00010046, 0x00000d70,
- 0x00000c70
- },
- .timing_ref = 0x000000bb,
- .timing_row = 0x6836650f,
- .timing_data = 0x3630580b,
- .timing_power = 0x41000a26,
- .phy0_dqs = 0x08080808,
- .phy1_dqs = 0x08080808,
- .phy0_dq = 0x08080808,
- .phy1_dq = 0x08080808,
- .phy0_tFS = 0x8,
- .phy1_tFS = 0x8,
- .phy0_pulld_dqs = 0xf,
- .phy1_pulld_dqs = 0xf,
-
- .lpddr3_ctrl_phy_reset = 0x1,
- .ctrl_start_point = 0x10,
- .ctrl_inc = 0x10,
- .ctrl_start = 0x1,
- .ctrl_dll_on = 0x1,
- .ctrl_ref = 0x8,
-
- .ctrl_force = 0x1a,
- .ctrl_rdlat = 0x0b,
- .ctrl_bstlen = 0x08,
-
- .fp_resync = 0x8,
- .iv_size = 0x7,
- .dfi_init_start = 1,
- .aref_en = 1,
-
- .rd_fetch = 0x3,
-
- .zq_mode_dds = 0x7,
- .zq_mode_term = 0x1,
- .zq_mode_noterm = 1,
-
- /*
- * Dynamic Clock: Always Running
- * Memory Burst length: 8
- * Number of chips: 1
- * Memory Bus width: 32 bit
- * Memory Type: DDR3
- * Additional Latancy for PLL: 0 Cycle
- */
- .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
- DMC_MEMCONTROL_DPWRDN_DISABLE |
- DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
- DMC_MEMCONTROL_TP_DISABLE |
- DMC_MEMCONTROL_DSREF_DISABLE |
- DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
- DMC_MEMCONTROL_MEM_TYPE_DDR3 |
- DMC_MEMCONTROL_MEM_WIDTH_32BIT |
- DMC_MEMCONTROL_NUM_CHIP_1 |
- DMC_MEMCONTROL_BL_8 |
- DMC_MEMCONTROL_PZQ_DISABLE |
- DMC_MEMCONTROL_MRR_BYTE_7_0,
- .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
- DMC_MEMCONFIGX_CHIP_COL_10 |
- DMC_MEMCONFIGX_CHIP_ROW_15 |
- DMC_MEMCONFIGX_CHIP_BANK_8,
- .prechconfig_tp_cnt = 0xff,
- .dpwrdn_cyc = 0xff,
- .dsref_cyc = 0xffff,
- .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
- DMC_CONCONTROL_TIMEOUT_LEVEL0 |
- DMC_CONCONTROL_RD_FETCH_DISABLE |
- DMC_CONCONTROL_EMPTY_DISABLE |
- DMC_CONCONTROL_AREF_EN_DISABLE |
- DMC_CONCONTROL_IO_PD_CON_DISABLE,
- .dmc_channels = 1,
- .chips_per_channel = 1,
- .chips_to_configure = 1,
- .send_zq_init = 1,
- .gate_leveling_enable = 1,
- .read_leveling_enable = 0,
- }
-#else
- {
- .mem_manuf = MEM_MANUF_ELPIDA,
- .mem_type = DDR_MODE_DDR3,
- .frequency_mhz = 800,
- .mpll_mdiv = 0xc8,
- .mpll_pdiv = 0x3,
- .mpll_sdiv = 0x0,
- .cpll_mdiv = 0xde,
- .cpll_pdiv = 0x4,
- .cpll_sdiv = 0x2,
- .gpll_mdiv = 0x215,
- .gpll_pdiv = 0xc,
- .gpll_sdiv = 0x1,
- .epll_mdiv = 0x60,
- .epll_pdiv = 0x3,
- .epll_sdiv = 0x3,
- .vpll_mdiv = 0x96,
- .vpll_pdiv = 0x3,
- .vpll_sdiv = 0x2,
-
- .bpll_mdiv = 0x64,
- .bpll_pdiv = 0x3,
- .bpll_sdiv = 0x0,
- .pclk_cdrex_ratio = 0x5,
- .direct_cmd_msr = {
- 0x00020018, 0x00030000, 0x00010042, 0x00000d70
- },
- .timing_ref = 0x000000bb,
- .timing_row = 0x8c36650e,
- .timing_data = 0x3630580b,
- .timing_power = 0x41000a44,
- .phy0_dqs = 0x08080808,
- .phy1_dqs = 0x08080808,
- .phy0_dq = 0x08080808,
- .phy1_dq = 0x08080808,
- .phy0_tFS = 0x4,
- .phy1_tFS = 0x4,
- .phy0_pulld_dqs = 0xf,
- .phy1_pulld_dqs = 0xf,
-
- .lpddr3_ctrl_phy_reset = 0x1,
- .ctrl_start_point = 0x10,
- .ctrl_inc = 0x10,
- .ctrl_start = 0x1,
- .ctrl_dll_on = 0x1,
- .ctrl_ref = 0x8,
-
- .ctrl_force = 0x1a,
- .ctrl_rdlat = 0x0b,
- .ctrl_bstlen = 0x08,
-
- .fp_resync = 0x8,
- .iv_size = 0x7,
- .dfi_init_start = 1,
- .aref_en = 1,
-
- .rd_fetch = 0x3,
-
- .zq_mode_dds = 0x7,
- .zq_mode_term = 0x1,
- .zq_mode_noterm = 0,
-
- /*
- * Dynamic Clock: Always Running
- * Memory Burst length: 8
- * Number of chips: 1
- * Memory Bus width: 32 bit
- * Memory Type: DDR3
- * Additional Latancy for PLL: 0 Cycle
- */
- .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
- DMC_MEMCONTROL_DPWRDN_DISABLE |
- DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
- DMC_MEMCONTROL_TP_DISABLE |
- DMC_MEMCONTROL_DSREF_ENABLE |
- DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
- DMC_MEMCONTROL_MEM_TYPE_DDR3 |
- DMC_MEMCONTROL_MEM_WIDTH_32BIT |
- DMC_MEMCONTROL_NUM_CHIP_1 |
- DMC_MEMCONTROL_BL_8 |
- DMC_MEMCONTROL_PZQ_DISABLE |
- DMC_MEMCONTROL_MRR_BYTE_7_0,
- .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
- DMC_MEMCONFIGX_CHIP_COL_10 |
- DMC_MEMCONFIGX_CHIP_ROW_15 |
- DMC_MEMCONFIGX_CHIP_BANK_8,
- .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
- .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
- .prechconfig_tp_cnt = 0xff,
- .dpwrdn_cyc = 0xff,
- .dsref_cyc = 0xffff,
- .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
- DMC_CONCONTROL_TIMEOUT_LEVEL0 |
- DMC_CONCONTROL_RD_FETCH_DISABLE |
- DMC_CONCONTROL_EMPTY_DISABLE |
- DMC_CONCONTROL_AREF_EN_DISABLE |
- DMC_CONCONTROL_IO_PD_CON_DISABLE,
- .dmc_channels = 2,
- .chips_per_channel = 2,
- .chips_to_configure = 1,
- .send_zq_init = 1,
- .impedance = IMP_OUTPUT_DRV_30_OHM,
- .gate_leveling_enable = 0,
- }, {
- .mem_manuf = MEM_MANUF_SAMSUNG,
- .mem_type = DDR_MODE_DDR3,
- .frequency_mhz = 800,
- .mpll_mdiv = 0xc8,
- .mpll_pdiv = 0x3,
- .mpll_sdiv = 0x0,
- .cpll_mdiv = 0xde,
- .cpll_pdiv = 0x4,
- .cpll_sdiv = 0x2,
- .gpll_mdiv = 0x215,
- .gpll_pdiv = 0xc,
- .gpll_sdiv = 0x1,
- .epll_mdiv = 0x60,
- .epll_pdiv = 0x3,
- .epll_sdiv = 0x3,
- .vpll_mdiv = 0x96,
- .vpll_pdiv = 0x3,
- .vpll_sdiv = 0x2,
-
- .bpll_mdiv = 0x64,
- .bpll_pdiv = 0x3,
- .bpll_sdiv = 0x0,
- .pclk_cdrex_ratio = 0x5,
- .direct_cmd_msr = {
- 0x00020018, 0x00030000, 0x00010000, 0x00000d70
- },
- .timing_ref = 0x000000bb,
- .timing_row = 0x8c36650e,
- .timing_data = 0x3630580b,
- .timing_power = 0x41000a44,
- .phy0_dqs = 0x08080808,
- .phy1_dqs = 0x08080808,
- .phy0_dq = 0x08080808,
- .phy1_dq = 0x08080808,
- .phy0_tFS = 0x8,
- .phy1_tFS = 0x8,
- .phy0_pulld_dqs = 0xf,
- .phy1_pulld_dqs = 0xf,
-
- .lpddr3_ctrl_phy_reset = 0x1,
- .ctrl_start_point = 0x10,
- .ctrl_inc = 0x10,
- .ctrl_start = 0x1,
- .ctrl_dll_on = 0x1,
- .ctrl_ref = 0x8,
-
- .ctrl_force = 0x1a,
- .ctrl_rdlat = 0x0b,
- .ctrl_bstlen = 0x08,
-
- .fp_resync = 0x8,
- .iv_size = 0x7,
- .dfi_init_start = 1,
- .aref_en = 1,
-
- .rd_fetch = 0x3,
-
- .zq_mode_dds = 0x5,
- .zq_mode_term = 0x1,
- .zq_mode_noterm = 1,
-
- /*
- * Dynamic Clock: Always Running
- * Memory Burst length: 8
- * Number of chips: 1
- * Memory Bus width: 32 bit
- * Memory Type: DDR3
- * Additional Latancy for PLL: 0 Cycle
- */
- .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
- DMC_MEMCONTROL_DPWRDN_DISABLE |
- DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
- DMC_MEMCONTROL_TP_DISABLE |
- DMC_MEMCONTROL_DSREF_ENABLE |
- DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
- DMC_MEMCONTROL_MEM_TYPE_DDR3 |
- DMC_MEMCONTROL_MEM_WIDTH_32BIT |
- DMC_MEMCONTROL_NUM_CHIP_1 |
- DMC_MEMCONTROL_BL_8 |
- DMC_MEMCONTROL_PZQ_DISABLE |
- DMC_MEMCONTROL_MRR_BYTE_7_0,
- .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
- DMC_MEMCONFIGX_CHIP_COL_10 |
- DMC_MEMCONFIGX_CHIP_ROW_15 |
- DMC_MEMCONFIGX_CHIP_BANK_8,
- .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
- .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
- .prechconfig_tp_cnt = 0xff,
- .dpwrdn_cyc = 0xff,
- .dsref_cyc = 0xffff,
- .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
- DMC_CONCONTROL_TIMEOUT_LEVEL0 |
- DMC_CONCONTROL_RD_FETCH_DISABLE |
- DMC_CONCONTROL_EMPTY_DISABLE |
- DMC_CONCONTROL_AREF_EN_DISABLE |
- DMC_CONCONTROL_IO_PD_CON_DISABLE,
- .dmc_channels = 2,
- .chips_per_channel = 2,
- .chips_to_configure = 1,
- .send_zq_init = 1,
- .impedance = IMP_OUTPUT_DRV_40_OHM,
- .gate_leveling_enable = 1,
- }
-#endif
-};
-
-/**
- * Get the required memory type and speed (SPL version).
- *
- * In SPL we have no device tree, so we use the machine parameters
- *
- * @param mem_type Returns memory type
- * @param frequency_mhz Returns memory speed in MHz
- * @param arm_freq Returns ARM clock speed in MHz
- * @param mem_manuf Return Memory Manufacturer name
- */
-static void clock_get_mem_selection(enum ddr_mode *mem_type,
- unsigned *frequency_mhz, unsigned *arm_freq,
- enum mem_manuf *mem_manuf)
-{
- struct spl_machine_param *params;
-
- params = spl_get_machine_params();
- *mem_type = params->mem_type;
- *frequency_mhz = params->frequency_mhz;
- *arm_freq = params->arm_freq_mhz;
- *mem_manuf = params->mem_manuf;
-}
-
-/* Get the ratios for setting ARM clock */
-struct arm_clk_ratios *get_arm_ratios(void)
-{
- struct arm_clk_ratios *arm_ratio;
- enum ddr_mode mem_type;
- enum mem_manuf mem_manuf;
- unsigned frequency_mhz, arm_freq;
- int i;
-
- clock_get_mem_selection(&mem_type, &frequency_mhz,
- &arm_freq, &mem_manuf);
-
- for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
- i++, arm_ratio++) {
- if (arm_ratio->arm_freq_mhz == arm_freq)
- return arm_ratio;
- }
-
- /* will hang if failed to find clock ratio */
- while (1)
- ;
-
- return NULL;
-}
-
-struct mem_timings *clock_get_mem_timings(void)
-{
- struct mem_timings *mem;
- enum ddr_mode mem_type;
- enum mem_manuf mem_manuf;
- unsigned frequency_mhz, arm_freq;
- int i;
-
- clock_get_mem_selection(&mem_type, &frequency_mhz,
- &arm_freq, &mem_manuf);
- for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
- i++, mem++) {
- if (mem->mem_type == mem_type &&
- mem->frequency_mhz == frequency_mhz &&
- mem->mem_manuf == mem_manuf)
- return mem;
- }
-
- /* will hang if failed to find memory timings */
- while (1)
- ;
-
- return NULL;
-}
-
-static void exynos5250_system_clock_init(void)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- struct mem_timings *mem;
- struct arm_clk_ratios *arm_clk_ratio;
- u32 val, tmp;
-
- mem = clock_get_mem_timings();
- arm_clk_ratio = get_arm_ratios();
-
- clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
- do {
- val = readl(&clk->mux_stat_cpu);
- } while ((val | MUX_APLL_SEL_MASK) != val);
-
- clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
- do {
- val = readl(&clk->mux_stat_core1);
- } while ((val | MUX_MPLL_SEL_MASK) != val);
-
- clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
- clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
- clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
- clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
- tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
- | MUX_GPLL_SEL_MASK;
- do {
- val = readl(&clk->mux_stat_top2);
- } while ((val | tmp) != val);
-
- clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
- do {
- val = readl(&clk->mux_stat_cdrex);
- } while ((val | MUX_BPLL_SEL_MASK) != val);
-
- /* PLL locktime */
- writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
- writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
- writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
- writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
- writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock);
- writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
- writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock);
-
- writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
-
- writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
- do {
- val = readl(&clk->mux_stat_cpu);
- } while ((val | HPM_SEL_SCLK_MPLL) != val);
-
- val = arm_clk_ratio->arm2_ratio << 28
- | arm_clk_ratio->apll_ratio << 24
- | arm_clk_ratio->pclk_dbg_ratio << 20
- | arm_clk_ratio->atb_ratio << 16
- | arm_clk_ratio->periph_ratio << 12
- | arm_clk_ratio->acp_ratio << 8
- | arm_clk_ratio->cpud_ratio << 4
- | arm_clk_ratio->arm_ratio;
- writel(val, &clk->div_cpu0);
- do {
- val = readl(&clk->div_stat_cpu0);
- } while (0 != val);
-
- writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
- do {
- val = readl(&clk->div_stat_cpu1);
- } while (0 != val);
-
- /* Set APLL */
- writel(APLL_CON1_VAL, &clk->apll_con1);
- val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
- arm_clk_ratio->apll_sdiv);
- writel(val, &clk->apll_con0);
- while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
- ;
-
- /* Set MPLL */
- writel(MPLL_CON1_VAL, &clk->mpll_con1);
- val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
- writel(val, &clk->mpll_con0);
- while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
- ;
-
- /* Set BPLL */
- writel(BPLL_CON1_VAL, &clk->bpll_con1);
- val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
- writel(val, &clk->bpll_con0);
- while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
- ;
-
- /* Set CPLL */
- writel(CPLL_CON1_VAL, &clk->cpll_con1);
- val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
- writel(val, &clk->cpll_con0);
- while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
- ;
-
- /* Set GPLL */
- writel(GPLL_CON1_VAL, &clk->gpll_con1);
- val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
- writel(val, &clk->gpll_con0);
- while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
- ;
-
- /* Set EPLL */
- writel(EPLL_CON2_VAL, &clk->epll_con2);
- writel(EPLL_CON1_VAL, &clk->epll_con1);
- val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
- writel(val, &clk->epll_con0);
- while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
- ;
-
- /* Set VPLL */
- writel(VPLL_CON2_VAL, &clk->vpll_con2);
- writel(VPLL_CON1_VAL, &clk->vpll_con1);
- val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
- writel(val, &clk->vpll_con0);
- while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
- ;
-
- writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
- writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
- while (readl(&clk->div_stat_core0) != 0)
- ;
-
- writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
- while (readl(&clk->div_stat_core1) != 0)
- ;
-
- writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
- while (readl(&clk->div_stat_sysrgt) != 0)
- ;
-
- writel(CLK_DIV_ACP_VAL, &clk->div_acp);
- while (readl(&clk->div_stat_acp) != 0)
- ;
-
- writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
- while (readl(&clk->div_stat_syslft) != 0)
- ;
-
- writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
- writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
- writel(TOP2_VAL, &clk->src_top2);
- writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
-
- writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
- while (readl(&clk->div_stat_top0))
- ;
-
- writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
- while (readl(&clk->div_stat_top1))
- ;
-
- writel(CLK_SRC_LEX_VAL, &clk->src_lex);
- while (1) {
- val = readl(&clk->mux_stat_lex);
- if (val == (val | 1))
- break;
- }
-
- writel(CLK_DIV_LEX_VAL, &clk->div_lex);
- while (readl(&clk->div_stat_lex))
- ;
-
- writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
- while (readl(&clk->div_stat_r0x))
- ;
-
- writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
- while (readl(&clk->div_stat_r0x))
- ;
-
- writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
- while (readl(&clk->div_stat_r1x))
- ;
-
- writel(CLK_REG_DISABLE, &clk->src_cdrex);
-
- writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
- while (readl(&clk->div_stat_cdrex))
- ;
-
- val = readl(&clk->src_cpu);
- val |= CLK_SRC_CPU_VAL;
- writel(val, &clk->src_cpu);
-
- val = readl(&clk->src_top2);
- val |= CLK_SRC_TOP2_VAL;
- writel(val, &clk->src_top2);
-
- val = readl(&clk->src_core1);
- val |= CLK_SRC_CORE1_VAL;
- writel(val, &clk->src_core1);
-
- writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
- writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
- while (readl(&clk->div_stat_fsys0))
- ;
-
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
-
- writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
- writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
-
- writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
- writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
- writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
- writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
-
- writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
- writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
- writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
- writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
- writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
-
- /* FIMD1 SRC CLK SELECTION */
- writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
-
- val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
- | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
- | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
- | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
- writel(val, &clk->div_fsys2);
-}
-
-static void exynos5420_system_clock_init(void)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- struct mem_timings *mem;
- struct arm_clk_ratios *arm_clk_ratio;
- u32 val;
-
- mem = clock_get_mem_timings();
- arm_clk_ratio = get_arm_ratios();
-
- /* PLL locktime */
- writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
- writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
- writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
- writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
- writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock);
- writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
- writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock);
- writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
- writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
- writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
- writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
-
- setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
-
- writel(0, &clk->src_top6);
-
- writel(0, &clk->src_cdrex);
- writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
- writel(HPM_RATIO, &clk->div_cpu1);
- writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
-
- /* switch A15 clock source to OSC clock before changing APLL */
- clrbits_le32(&clk->src_cpu, APLL_FOUT);
-
- /* Set APLL */
- writel(APLL_CON1_VAL, &clk->apll_con1);
- val = set_pll(arm_clk_ratio->apll_mdiv,
- arm_clk_ratio->apll_pdiv,
- arm_clk_ratio->apll_sdiv);
- writel(val, &clk->apll_con0);
- while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* now it is safe to switch to APLL */
- setbits_le32(&clk->src_cpu, APLL_FOUT);
-
- writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
- writel(CLK_DIV_KFC_VAL, &clk->div_kfc0);
-
- /* switch A7 clock source to OSC clock before changing KPLL */
- clrbits_le32(&clk->src_kfc, KPLL_FOUT);
-
- /* Set KPLL*/
- writel(KPLL_CON1_VAL, &clk->kpll_con1);
- val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv);
- writel(val, &clk->kpll_con0);
- while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* now it is safe to switch to KPLL */
- setbits_le32(&clk->src_kfc, KPLL_FOUT);
-
- /* Set MPLL */
- writel(MPLL_CON1_VAL, &clk->mpll_con1);
- val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
- writel(val, &clk->mpll_con0);
- while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* Set DPLL */
- writel(DPLL_CON1_VAL, &clk->dpll_con1);
- val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv);
- writel(val, &clk->dpll_con0);
- while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* Set EPLL */
- writel(EPLL_CON2_VAL, &clk->epll_con2);
- writel(EPLL_CON1_VAL, &clk->epll_con1);
- val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
- writel(val, &clk->epll_con0);
- while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* Set CPLL */
- writel(CPLL_CON1_VAL, &clk->cpll_con1);
- val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
- writel(val, &clk->cpll_con0);
- while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* Set IPLL */
- writel(IPLL_CON1_VAL, &clk->ipll_con1);
- val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv);
- writel(val, &clk->ipll_con0);
- while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* Set VPLL */
- writel(VPLL_CON1_VAL, &clk->vpll_con1);
- val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
- writel(val, &clk->vpll_con0);
- while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* Set BPLL */
- writel(BPLL_CON1_VAL, &clk->bpll_con1);
- val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
- writel(val, &clk->bpll_con0);
- while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* Set SPLL */
- writel(SPLL_CON1_VAL, &clk->spll_con1);
- val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv);
- writel(val, &clk->spll_con0);
- while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
- ;
-
- /* Set RPLL */
- writel(RPLL_CON2_VAL, &clk->rpll_con2);
- writel(RPLL_CON1_VAL, &clk->rpll_con1);
- val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv);
- writel(val, &clk->rpll_con0);
- while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0)
- ;
-
- writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
- writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
-
- writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
- writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
- writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
- writel(CLK_SRC_TOP7_VAL, &clk->src_top7);
-
- writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
- writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
- writel(CLK_DIV_TOP2_VAL, &clk->div_top2);
-
- writel(0, &clk->src_top10);
- writel(0, &clk->src_top11);
- writel(0, &clk->src_top12);
-
- writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
- writel(CLK_SRC_TOP4_VAL, &clk->src_top4);
- writel(CLK_SRC_TOP5_VAL, &clk->src_top5);
-
- /* DISP1 BLK CLK SELECTION */
- writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10);
- writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10);
-
- /* AUDIO BLK */
- writel(AUDIO0_SEL_EPLL, &clk->src_mau);
- writel(DIV_MAU_VAL, &clk->div_mau);
-
- /* FSYS */
- writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
- writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
- writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
- writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
-
- writel(CLK_SRC_ISP_VAL, &clk->src_isp);
- writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
- writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
-
- writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
- writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
-
- writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
- writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
- writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
- writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
- writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4);
-
- writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1);
-
- writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
- writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
- writel(CLK_DIV_G2D, &clk->div_g2d);
-
- writel(CLK_SRC_TOP6_VAL, &clk->src_top6);
- writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
- writel(CLK_SRC_KFC_VAL, &clk->src_kfc);
-}
-
-void system_clock_init(void)
-{
- if (proid_is_exynos5420() || proid_is_exynos5800())
- exynos5420_system_clock_init();
- else
- exynos5250_system_clock_init();
-}
-
-void clock_init_dp_clock(void)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
-
- /* DP clock enable */
- setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
-
- /* We run DP at 267 Mhz */
- setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
-}
-
-/*
- * Set clock divisor value for booting from EMMC.
- * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
- */
-void emmc_boot_clk_div_set(void)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned int div_mmc;
-
- div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK;
- div_mmc |= FSYS1_MMC0_DIV_VAL;
- writel(div_mmc, (unsigned int) &clk->div_fsys1);
-}
+++ /dev/null
-/*
- * Common APIs for EXYNOS based board
- *
- * Copyright (C) 2013 Samsung Electronics
- * Rajeshwari Shinde <rajeshwari.s@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/system.h>
-
-#define DMC_OFFSET 0x10000
-
-/*
- * Memory initialization
- *
- * @param reset Reset PHY during initialization.
- */
-void mem_ctrl_init(int reset);
-
- /* System Clock initialization */
-void system_clock_init(void);
-
-/*
- * Init subsystems according to the reset status
- *
- * @return 0 for a normal boot, non-zero for a resume
- */
-int do_lowlevel_init(void);
-
-void sdelay(unsigned long);
-
-enum l2_cache_params {
- CACHE_DATA_RAM_LATENCY_2_CYCLES = (2 << 0),
- CACHE_DATA_RAM_LATENCY_3_CYCLES = (3 << 0),
- CACHE_DISABLE_CLEAN_EVICT = (1 << 3),
- CACHE_DATA_RAM_SETUP = (1 << 5),
- CACHE_TAG_RAM_LATENCY_2_CYCLES = (2 << 6),
- CACHE_TAG_RAM_LATENCY_3_CYCLES = (3 << 6),
- CACHE_ENABLE_HAZARD_DETECT = (1 << 7),
- CACHE_TAG_RAM_SETUP = (1 << 9),
- CACHE_ECC_AND_PARITY = (1 << 21),
- CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27)
-};
-
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-/*
- * Configure L2CTLR to get timings that keep us from hanging/crashing.
- *
- * Must be inline here since low_power_start() is called without a
- * stack (!).
- */
-static inline void configure_l2_ctlr(void)
-{
- uint32_t val;
-
- mrc_l2_ctlr(val);
-
- val |= CACHE_TAG_RAM_SETUP |
- CACHE_DATA_RAM_SETUP |
- CACHE_TAG_RAM_LATENCY_2_CYCLES |
- CACHE_DATA_RAM_LATENCY_2_CYCLES;
-
- if (proid_is_exynos5420() || proid_is_exynos5800()) {
- val |= CACHE_ECC_AND_PARITY |
- CACHE_TAG_RAM_LATENCY_3_CYCLES |
- CACHE_DATA_RAM_LATENCY_3_CYCLES;
- }
-
- mcr_l2_ctlr(val);
-}
-
-/*
- * Configure L2ACTLR.
- *
- * Must be inline here since low_power_start() is called without a
- * stack (!).
- */
-static inline void configure_l2_actlr(void)
-{
- uint32_t val;
-
- if (proid_is_exynos5420() || proid_is_exynos5800()) {
- mrc_l2_aux_ctlr(val);
- val |= CACHE_ENABLE_FORCE_L2_LOGIC |
- CACHE_DISABLE_CLEAN_EVICT;
- mcr_l2_aux_ctlr(val);
- }
-}
-#endif
+++ /dev/null
-#
-# Copyright (C) Albert ARIBAUD <albert.u.boot@aribaud.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-SPL_OBJCFLAGS += -j .machine_param
+++ /dev/null
-/*
- * Mem setup common file for different types of DDR present on Exynos boards.
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/spl.h>
-
-#include "clock_init.h"
-#include "common_setup.h"
-#include "exynos5_setup.h"
-
-#define ZQ_INIT_TIMEOUT 10000
-
-int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16,
- uint32_t *phy1_con16, uint32_t *phy0_con17,
- uint32_t *phy1_con17)
-{
- unsigned long val = 0;
- int i;
-
- /*
- * ZQ Calibration:
- * Select Driver Strength,
- * long calibration for manual calibration
- */
- val = PHY_CON16_RESET_VAL;
- val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT;
- val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT;
- val |= ZQ_CLK_DIV_EN;
- writel(val, phy0_con16);
- writel(val, phy1_con16);
-
- /* Disable termination */
- if (mem->zq_mode_noterm)
- val |= PHY_CON16_ZQ_MODE_NOTERM_MASK;
- writel(val, phy0_con16);
- writel(val, phy1_con16);
-
- /* ZQ_MANUAL_START: Enable */
- val |= ZQ_MANUAL_STR;
- writel(val, phy0_con16);
- writel(val, phy1_con16);
-
- /* ZQ_MANUAL_START: Disable */
- val &= ~ZQ_MANUAL_STR;
-
- /*
- * Since we are manaully calibrating the ZQ values,
- * we are looping for the ZQ_init to complete.
- */
- i = ZQ_INIT_TIMEOUT;
- while ((readl(phy0_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
- sdelay(100);
- i--;
- }
- if (!i)
- return -1;
- writel(val, phy0_con16);
-
- i = ZQ_INIT_TIMEOUT;
- while ((readl(phy1_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
- sdelay(100);
- i--;
- }
- if (!i)
- return -1;
- writel(val, phy1_con16);
-
- return 0;
-}
-
-void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode mode)
-{
- unsigned long val;
-
- if (mode == DDR_MODE_DDR3) {
- val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE;
- writel(val, phycontrol0);
- }
-
- /* Update DLL Information: Force DLL Resyncronization */
- val = readl(phycontrol0);
- val |= FP_RSYNC;
- writel(val, phycontrol0);
-
- /* Reset Force DLL Resyncronization */
- val = readl(phycontrol0);
- val &= ~FP_RSYNC;
- writel(val, phycontrol0);
-}
-
-void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd)
-{
- int channel, chip;
-
- for (channel = 0; channel < mem->dmc_channels; channel++) {
- unsigned long mask;
-
- mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
- for (chip = 0; chip < mem->chips_to_configure; chip++) {
- int i;
-
- mask |= chip << DIRECT_CMD_CHIP_SHIFT;
-
- /* Sending NOP command */
- writel(DIRECT_CMD_NOP | mask, directcmd);
-
- /*
- * TODO(alim.akhtar@samsung.com): Do we need these
- * delays? This one and the next were not there for
- * DDR3.
- */
- sdelay(0x10000);
-
- /* Sending EMRS/MRS commands */
- for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
- writel(mem->direct_cmd_msr[i] | mask,
- directcmd);
- sdelay(0x10000);
- }
-
- if (mem->send_zq_init) {
- /* Sending ZQINIT command */
- writel(DIRECT_CMD_ZQINIT | mask,
- directcmd);
-
- sdelay(10000);
- }
- }
- }
-}
-
-void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd)
-{
- int channel, chip;
-
- for (channel = 0; channel < mem->dmc_channels; channel++) {
- unsigned long mask;
-
- mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
- for (chip = 0; chip < mem->chips_per_channel; chip++) {
- mask |= chip << DIRECT_CMD_CHIP_SHIFT;
-
- /* PALL (all banks precharge) CMD */
- writel(DIRECT_CMD_PALL | mask, directcmd);
- sdelay(0x10000);
- }
- }
-}
-
-void mem_ctrl_init(int reset)
-{
- struct spl_machine_param *param = spl_get_machine_params();
- struct mem_timings *mem;
- int ret;
-
- mem = clock_get_mem_timings();
-
- /* If there are any other memory variant, add their init call below */
- if (param->mem_type == DDR_MODE_DDR3) {
- ret = ddr3_mem_ctrl_init(mem, reset);
- if (ret) {
- /* will hang if failed to init memory control */
- while (1)
- ;
- }
- } else {
- /* will hang if unknow memory type */
- while (1)
- ;
- }
-}
+++ /dev/null
-/*
- * DDR3 mem setup file for board based on EXYNOS5
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/dmc.h>
-#include <asm/arch/power.h>
-#include "common_setup.h"
-#include "exynos5_setup.h"
-#include "clock_init.h"
-
-#define TIMEOUT_US 10000
-#define NUM_BYTE_LANES 4
-#define DEFAULT_DQS 8
-#define DEFAULT_DQS_X4 (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
- || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)
-
-#ifdef CONFIG_EXYNOS5250
-static void reset_phy_ctrl(void)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
-
- writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
- writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
-}
-
-int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
-{
- unsigned int val;
- struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
- struct exynos5_dmc *dmc;
- int i;
-
- phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy();
- phy1_ctrl = (struct exynos5_phy_control *)(samsung_get_base_dmc_phy()
- + DMC_OFFSET);
- dmc = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl();
-
- if (reset)
- reset_phy_ctrl();
-
- /* Set Impedance Output Driver */
- val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |
- (mem->impedance << CA_CKE_DRVR_DS_OFFSET) |
- (mem->impedance << CA_CS_DRVR_DS_OFFSET) |
- (mem->impedance << CA_ADR_DRVR_DS_OFFSET);
- writel(val, &phy0_ctrl->phy_con39);
- writel(val, &phy1_ctrl->phy_con39);
-
- /* Set Read Latency and Burst Length for PHY0 and PHY1 */
- val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
- (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
- writel(val, &phy0_ctrl->phy_con42);
- writel(val, &phy1_ctrl->phy_con42);
-
- /* ZQ Calibration */
- if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
- &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
- return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
-
- /* DQ Signal */
- writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14);
- writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14);
-
- writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
- | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT),
- &dmc->concontrol);
-
- update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
-
- /* DQS Signal */
- writel(mem->phy0_dqs, &phy0_ctrl->phy_con4);
- writel(mem->phy1_dqs, &phy1_ctrl->phy_con4);
-
- writel(mem->phy0_dq, &phy0_ctrl->phy_con6);
- writel(mem->phy1_dq, &phy1_ctrl->phy_con6);
-
- writel(mem->phy0_tFS, &phy0_ctrl->phy_con10);
- writel(mem->phy1_tFS, &phy1_ctrl->phy_con10);
-
- val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) |
- (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
- (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
- (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
- writel(val, &phy0_ctrl->phy_con12);
- writel(val, &phy1_ctrl->phy_con12);
-
- /* Start DLL locking */
- writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
- &phy0_ctrl->phy_con12);
- writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
- &phy1_ctrl->phy_con12);
-
- update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
-
- writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
- &dmc->concontrol);
-
- /* Memory Channel Inteleaving Size */
- writel(mem->iv_size, &dmc->ivcontrol);
-
- writel(mem->memconfig, &dmc->memconfig0);
- writel(mem->memconfig, &dmc->memconfig1);
- writel(mem->membaseconfig0, &dmc->membaseconfig0);
- writel(mem->membaseconfig1, &dmc->membaseconfig1);
-
- /* Precharge Configuration */
- writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
- &dmc->prechconfig);
-
- /* Power Down mode Configuration */
- writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
- mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT,
- &dmc->pwrdnconfig);
-
- /* TimingRow, TimingData, TimingPower and Timingaref
- * values as per Memory AC parameters
- */
- writel(mem->timing_ref, &dmc->timingref);
- writel(mem->timing_row, &dmc->timingrow);
- writel(mem->timing_data, &dmc->timingdata);
- writel(mem->timing_power, &dmc->timingpower);
-
- /* Send PALL command */
- dmc_config_prech(mem, &dmc->directcmd);
-
- /* Send NOP, MRS and ZQINIT commands */
- dmc_config_mrs(mem, &dmc->directcmd);
-
- if (mem->gate_leveling_enable) {
- val = PHY_CON0_RESET_VAL;
- val |= P0_CMD_EN;
- writel(val, &phy0_ctrl->phy_con0);
- writel(val, &phy1_ctrl->phy_con0);
-
- val = PHY_CON2_RESET_VAL;
- val |= INIT_DESKEW_EN;
- writel(val, &phy0_ctrl->phy_con2);
- writel(val, &phy1_ctrl->phy_con2);
-
- val = PHY_CON0_RESET_VAL;
- val |= P0_CMD_EN;
- val |= BYTE_RDLVL_EN;
- writel(val, &phy0_ctrl->phy_con0);
- writel(val, &phy1_ctrl->phy_con0);
-
- val = (mem->ctrl_start_point <<
- PHY_CON12_CTRL_START_POINT_SHIFT) |
- (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
- (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
- (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
- (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
- writel(val, &phy0_ctrl->phy_con12);
- writel(val, &phy1_ctrl->phy_con12);
-
- val = PHY_CON2_RESET_VAL;
- val |= INIT_DESKEW_EN;
- val |= RDLVL_GATE_EN;
- writel(val, &phy0_ctrl->phy_con2);
- writel(val, &phy1_ctrl->phy_con2);
-
- val = PHY_CON0_RESET_VAL;
- val |= P0_CMD_EN;
- val |= BYTE_RDLVL_EN;
- val |= CTRL_SHGATE;
- writel(val, &phy0_ctrl->phy_con0);
- writel(val, &phy1_ctrl->phy_con0);
-
- val = PHY_CON1_RESET_VAL;
- val &= ~(CTRL_GATEDURADJ_MASK);
- writel(val, &phy0_ctrl->phy_con1);
- writel(val, &phy1_ctrl->phy_con1);
-
- writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
- i = TIMEOUT_US;
- while ((readl(&dmc->phystatus) &
- (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
- (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
- /*
- * TODO(waihong): Comment on how long this take to
- * timeout
- */
- sdelay(100);
- i--;
- }
- if (!i)
- return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
- writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config);
-
- writel(0, &phy0_ctrl->phy_con14);
- writel(0, &phy1_ctrl->phy_con14);
-
- val = (mem->ctrl_start_point <<
- PHY_CON12_CTRL_START_POINT_SHIFT) |
- (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
- (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
- (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
- (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
- (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
- writel(val, &phy0_ctrl->phy_con12);
- writel(val, &phy1_ctrl->phy_con12);
-
- update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
- }
-
- /* Send PALL command */
- dmc_config_prech(mem, &dmc->directcmd);
-
- writel(mem->memcontrol, &dmc->memcontrol);
-
- /* Set DMC Concontrol and enable auto-refresh counter */
- writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
- | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
- return 0;
-}
-#endif
-
-#ifdef CONFIG_EXYNOS5420
-/**
- * RAM address to use in the test.
- *
- * We'll use 4 words at this address and 4 at this address + 0x80 (Ares
- * interleaves channels every 128 bytes). This will allow us to evaluate all of
- * the chips in a 1 chip per channel (2GB) system and half the chips in a 2
- * chip per channel (4GB) system. We can't test the 2nd chip since we need to
- * do tests before the 2nd chip is enabled. Looking at the 2nd chip isn't
- * critical because the 1st and 2nd chip have very similar timings (they'd
- * better have similar timings, since there's only a single adjustment that is
- * shared by both chips).
- */
-const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE;
-
-/* Test pattern with which RAM will be tested */
-static const unsigned int test_pattern[] = {
- 0x5a5a5a5a,
- 0xa5a5a5a5,
- 0xf0f0f0f0,
- 0x0f0f0f0f,
-};
-
-/**
- * This function is a test vector for sw read leveling,
- * it compares the read data with the written data.
- *
- * @param ch DMC channel number
- * @param byte_lane which DQS byte offset,
- * possible values are 0,1,2,3
- * @return TRUE if memory was good, FALSE if not.
- */
-static bool dmc_valid_window_test_vector(int ch, int byte_lane)
-{
- unsigned int read_data;
- unsigned int mask;
- int i;
-
- mask = 0xFF << (8 * byte_lane);
-
- for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
- read_data = readl(test_addr + i * 4 + ch * 0x80);
- if ((read_data & mask) != (test_pattern[i] & mask))
- return false;
- }
-
- return true;
-}
-
-/**
- * This function returns current read offset value.
- *
- * @param phy_ctrl pointer to the current phy controller
- */
-static unsigned int dmc_get_read_offset_value(struct exynos5420_phy_control
- *phy_ctrl)
-{
- return readl(&phy_ctrl->phy_con4);
-}
-
-/**
- * This function performs resync, so that slave DLL is updated.
- *
- * @param phy_ctrl pointer to the current phy controller
- */
-static void ddr_phy_set_do_resync(struct exynos5420_phy_control *phy_ctrl)
-{
- setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3);
- clrbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3);
-}
-
-/**
- * This function sets read offset value register with 'offset'.
- *
- * ...we also call call ddr_phy_set_do_resync().
- *
- * @param phy_ctrl pointer to the current phy controller
- * @param offset offset to read DQS
- */
-static void dmc_set_read_offset_value(struct exynos5420_phy_control *phy_ctrl,
- unsigned int offset)
-{
- writel(offset, &phy_ctrl->phy_con4);
- ddr_phy_set_do_resync(phy_ctrl);
-}
-
-/**
- * Convert a 2s complement byte to a byte with a sign bit.
- *
- * NOTE: you shouldn't use normal math on the number returned by this function.
- * As an example, -10 = 0xf6. After this function -10 = 0x8a. If you wanted
- * to do math and get the average of 10 and -10 (should be 0):
- * 0x8a + 0xa = 0x94 (-108)
- * 0x94 / 2 = 0xca (-54)
- * ...and 0xca = sign bit plus 0x4a, or -74
- *
- * Also note that you lose the ability to represent -128 since there are two
- * representations of 0.
- *
- * @param b The byte to convert in two's complement.
- * @return The 7-bit value + sign bit.
- */
-
-unsigned char make_signed_byte(signed char b)
-{
- if (b < 0)
- return 0x80 | -b;
- else
- return b;
-}
-
-/**
- * Test various shifts starting at 'start' and going to 'end'.
- *
- * For each byte lane, we'll walk through shift starting at 'start' and going
- * to 'end' (inclusive). When we are finally able to read the test pattern
- * we'll store the value in the results array.
- *
- * @param phy_ctrl pointer to the current phy controller
- * @param ch channel number
- * @param start the start shift. -127 to 127
- * @param end the end shift. -127 to 127
- * @param results we'll store results for each byte lane.
- */
-
-void test_shifts(struct exynos5420_phy_control *phy_ctrl, int ch,
- int start, int end, int results[NUM_BYTE_LANES])
-{
- int incr = (start < end) ? 1 : -1;
- int byte_lane;
-
- for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) {
- int shift;
-
- dmc_set_read_offset_value(phy_ctrl, DEFAULT_DQS_X4);
- results[byte_lane] = DEFAULT_DQS;
-
- for (shift = start; shift != (end + incr); shift += incr) {
- unsigned int byte_offsetr;
- unsigned int offsetr;
-
- byte_offsetr = make_signed_byte(shift);
-
- offsetr = dmc_get_read_offset_value(phy_ctrl);
- offsetr &= ~(0xFF << (8 * byte_lane));
- offsetr |= (byte_offsetr << (8 * byte_lane));
- dmc_set_read_offset_value(phy_ctrl, offsetr);
-
- if (dmc_valid_window_test_vector(ch, byte_lane)) {
- results[byte_lane] = shift;
- break;
- }
- }
- }
-}
-
-/**
- * This function performs SW read leveling to compensate DQ-DQS skew at
- * receiver it first finds the optimal read offset value on each DQS
- * then applies the value to PHY.
- *
- * Read offset value has its min margin and max margin. If read offset
- * value exceeds its min or max margin, read data will have corruption.
- * To avoid this we are doing sw read leveling.
- *
- * SW read leveling is:
- * 1> Finding offset value's left_limit and right_limit
- * 2> and calculate its center value
- * 3> finally programs that center value to PHY
- * 4> then PHY gets its optimal offset value.
- *
- * @param phy_ctrl pointer to the current phy controller
- * @param ch channel number
- * @param coarse_lock_val The coarse lock value read from PHY_CON13.
- * (0 - 0x7f)
- */
-static void software_find_read_offset(struct exynos5420_phy_control *phy_ctrl,
- int ch, unsigned int coarse_lock_val)
-{
- unsigned int offsetr_cent;
- int byte_lane;
- int left_limit;
- int right_limit;
- int left[NUM_BYTE_LANES];
- int right[NUM_BYTE_LANES];
- int i;
-
- /* Fill the memory with test patterns */
- for (i = 0; i < ARRAY_SIZE(test_pattern); i++)
- writel(test_pattern[i], test_addr + i * 4 + ch * 0x80);
-
- /* Figure out the limits we'll test with; keep -127 < limit < 127 */
- left_limit = DEFAULT_DQS - coarse_lock_val;
- right_limit = DEFAULT_DQS + coarse_lock_val;
- if (right_limit > 127)
- right_limit = 127;
-
- /* Fill in the location where reads were OK from left and right */
- test_shifts(phy_ctrl, ch, left_limit, right_limit, left);
- test_shifts(phy_ctrl, ch, right_limit, left_limit, right);
-
- /* Make a final value by taking the center between the left and right */
- offsetr_cent = 0;
- for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) {
- int temp_center;
- unsigned int vmwc;
-
- temp_center = (left[byte_lane] + right[byte_lane]) / 2;
- vmwc = make_signed_byte(temp_center);
- offsetr_cent |= vmwc << (8 * byte_lane);
- }
- dmc_set_read_offset_value(phy_ctrl, offsetr_cent);
-}
-
-int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- struct exynos5420_power *power =
- (struct exynos5420_power *)samsung_get_base_power();
- struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl;
- struct exynos5420_dmc *drex0, *drex1;
- struct exynos5420_tzasc *tzasc0, *tzasc1;
- struct exynos5_power *pmu;
- uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
- uint32_t lock0_info, lock1_info;
- int chip;
- int i;
-
- phy0_ctrl = (struct exynos5420_phy_control *)samsung_get_base_dmc_phy();
- phy1_ctrl = (struct exynos5420_phy_control *)(samsung_get_base_dmc_phy()
- + DMC_OFFSET);
- drex0 = (struct exynos5420_dmc *)samsung_get_base_dmc_ctrl();
- drex1 = (struct exynos5420_dmc *)(samsung_get_base_dmc_ctrl()
- + DMC_OFFSET);
- tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc();
- tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc()
- + DMC_OFFSET);
- pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
-
- if (CONFIG_NR_DRAM_BANKS > 4) {
- /* Need both controllers. */
- mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2;
- mem->chips_per_channel = 2;
- mem->chips_to_configure = 2;
- } else {
- /* 2GB requires a single controller */
- mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1;
- }
-
- /* Enable PAUSE for DREX */
- setbits_le32(&clk->pause, ENABLE_BIT);
-
- /* Enable BYPASS mode */
- setbits_le32(&clk->bpll_con1, BYPASS_EN);
-
- writel(MUX_BPLL_SEL_FOUTBPLL, &clk->src_cdrex);
- do {
- val = readl(&clk->mux_stat_cdrex);
- val &= BPLL_SEL_MASK;
- } while (val != FOUTBPLL);
-
- clrbits_le32(&clk->bpll_con1, BYPASS_EN);
-
- /* Specify the DDR memory type as DDR3 */
- val = readl(&phy0_ctrl->phy_con0);
- val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
- val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
- writel(val, &phy0_ctrl->phy_con0);
-
- val = readl(&phy1_ctrl->phy_con0);
- val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
- val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
- writel(val, &phy1_ctrl->phy_con0);
-
- /* Set Read Latency and Burst Length for PHY0 and PHY1 */
- val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
- (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
- writel(val, &phy0_ctrl->phy_con42);
- writel(val, &phy1_ctrl->phy_con42);
-
- val = readl(&phy0_ctrl->phy_con26);
- val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
- val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
- writel(val, &phy0_ctrl->phy_con26);
-
- val = readl(&phy1_ctrl->phy_con26);
- val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
- val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
- writel(val, &phy1_ctrl->phy_con26);
-
- /*
- * Set Driver strength for CK, CKE, CS & CA to 0x7
- * Set Driver strength for Data Slice 0~3 to 0x7
- */
- val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) |
- (0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET);
- val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) |
- (0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET);
- writel(val, &phy0_ctrl->phy_con39);
- writel(val, &phy1_ctrl->phy_con39);
-
- /* ZQ Calibration */
- if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
- &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
- return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
-
- clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN);
- clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN);
-
- /* DQ Signal */
- val = readl(&phy0_ctrl->phy_con14);
- val |= mem->phy0_pulld_dqs;
- writel(val, &phy0_ctrl->phy_con14);
- val = readl(&phy1_ctrl->phy_con14);
- val |= mem->phy1_pulld_dqs;
- writel(val, &phy1_ctrl->phy_con14);
-
- val = MEM_TERM_EN | PHY_TERM_EN;
- writel(val, &drex0->phycontrol0);
- writel(val, &drex1->phycontrol0);
-
- writel(mem->concontrol |
- (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
- (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
- &drex0->concontrol);
- writel(mem->concontrol |
- (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
- (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
- &drex1->concontrol);
-
- do {
- val = readl(&drex0->phystatus);
- } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
- do {
- val = readl(&drex1->phystatus);
- } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
-
- clrbits_le32(&drex0->concontrol, DFI_INIT_START);
- clrbits_le32(&drex1->concontrol, DFI_INIT_START);
-
- update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);
- update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);
-
- /*
- * Set Base Address:
- * 0x2000_0000 ~ 0x5FFF_FFFF
- * 0x6000_0000 ~ 0x9FFF_FFFF
- */
- /* MEMBASECONFIG0 */
- val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_0) |
- DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
- writel(val, &tzasc0->membaseconfig0);
- writel(val, &tzasc1->membaseconfig0);
-
- /* MEMBASECONFIG1 */
- val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_1) |
- DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
- writel(val, &tzasc0->membaseconfig1);
- writel(val, &tzasc1->membaseconfig1);
-
- /*
- * Memory Channel Inteleaving Size
- * Ares Channel interleaving = 128 bytes
- */
- /* MEMCONFIG0/1 */
- writel(mem->memconfig, &tzasc0->memconfig0);
- writel(mem->memconfig, &tzasc1->memconfig0);
- writel(mem->memconfig, &tzasc0->memconfig1);
- writel(mem->memconfig, &tzasc1->memconfig1);
-
- /* Precharge Configuration */
- writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
- &drex0->prechconfig0);
- writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
- &drex1->prechconfig0);
-
- /*
- * TimingRow, TimingData, TimingPower and Timingaref
- * values as per Memory AC parameters
- */
- writel(mem->timing_ref, &drex0->timingref);
- writel(mem->timing_ref, &drex1->timingref);
- writel(mem->timing_row, &drex0->timingrow0);
- writel(mem->timing_row, &drex1->timingrow0);
- writel(mem->timing_data, &drex0->timingdata0);
- writel(mem->timing_data, &drex1->timingdata0);
- writel(mem->timing_power, &drex0->timingpower0);
- writel(mem->timing_power, &drex1->timingpower0);
-
- if (reset) {
- /*
- * Send NOP, MRS and ZQINIT commands
- * Sending MRS command will reset the DRAM. We should not be
- * reseting the DRAM after resume, this will lead to memory
- * corruption as DRAM content is lost after DRAM reset
- */
- dmc_config_mrs(mem, &drex0->directcmd);
- dmc_config_mrs(mem, &drex1->directcmd);
- }
-
- /*
- * Get PHY_CON13 from both phys. Gate CLKM around reading since
- * PHY_CON13 is glitchy when CLKM is running. We're paranoid and
- * wait until we get a "fine lock", though a coarse lock is probably
- * OK (we only use the coarse numbers below). We try to gate the
- * clock for as short a time as possible in case SDRAM is somehow
- * sensitive. sdelay(10) in the loop is arbitrary to make sure
- * there is some time for PHY_CON13 to get updated. In practice
- * no delay appears to be needed.
- */
- val = readl(&clk->gate_bus_cdrex);
- while (true) {
- writel(val & ~0x1, &clk->gate_bus_cdrex);
- lock0_info = readl(&phy0_ctrl->phy_con13);
- writel(val, &clk->gate_bus_cdrex);
-
- if ((lock0_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED)
- break;
-
- sdelay(10);
- }
- while (true) {
- writel(val & ~0x2, &clk->gate_bus_cdrex);
- lock1_info = readl(&phy1_ctrl->phy_con13);
- writel(val, &clk->gate_bus_cdrex);
-
- if ((lock1_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED)
- break;
-
- sdelay(10);
- }
-
- if (!reset) {
- /*
- * During Suspend-Resume & S/W-Reset, as soon as PMU releases
- * pad retention, CKE goes high. This causes memory contents
- * not to be retained during DRAM initialization. Therfore,
- * there is a new control register(0x100431e8[28]) which lets us
- * release pad retention and retain the memory content until the
- * initialization is complete.
- */
- writel(PAD_RETENTION_DRAM_COREBLK_VAL,
- &power->pad_retention_dram_coreblk_option);
- do {
- val = readl(&power->pad_retention_dram_status);
- } while (val != 0x1);
-
- /*
- * CKE PAD retention disables DRAM self-refresh mode.
- * Send auto refresh command for DRAM refresh.
- */
- for (i = 0; i < 128; i++) {
- for (chip = 0; chip < mem->chips_to_configure; chip++) {
- writel(DIRECT_CMD_REFA |
- (chip << DIRECT_CMD_CHIP_SHIFT),
- &drex0->directcmd);
- writel(DIRECT_CMD_REFA |
- (chip << DIRECT_CMD_CHIP_SHIFT),
- &drex1->directcmd);
- }
- }
- }
-
- if (mem->gate_leveling_enable) {
- writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0);
- writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0);
-
- setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN);
- setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN);
-
- val = PHY_CON2_RESET_VAL;
- val |= INIT_DESKEW_EN;
- writel(val, &phy0_ctrl->phy_con2);
- writel(val, &phy1_ctrl->phy_con2);
-
- val = readl(&phy0_ctrl->phy_con1);
- val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
- writel(val, &phy0_ctrl->phy_con1);
-
- val = readl(&phy1_ctrl->phy_con1);
- val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
- writel(val, &phy1_ctrl->phy_con1);
-
- n_lock_w_phy0 = (lock0_info & CTRL_LOCK_COARSE_MASK) >> 2;
- n_lock_r = readl(&phy0_ctrl->phy_con12);
- n_lock_r &= ~CTRL_DLL_ON;
- n_lock_r |= n_lock_w_phy0;
- writel(n_lock_r, &phy0_ctrl->phy_con12);
-
- n_lock_w_phy1 = (lock1_info & CTRL_LOCK_COARSE_MASK) >> 2;
- n_lock_r = readl(&phy1_ctrl->phy_con12);
- n_lock_r &= ~CTRL_DLL_ON;
- n_lock_r |= n_lock_w_phy1;
- writel(n_lock_r, &phy1_ctrl->phy_con12);
-
- val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
- for (chip = 0; chip < mem->chips_to_configure; chip++) {
- writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
- &drex0->directcmd);
- writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
- &drex1->directcmd);
- }
-
- setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
- setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
-
- setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE);
- setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE);
-
- val = readl(&phy0_ctrl->phy_con1);
- val &= ~(CTRL_GATEDURADJ_MASK);
- writel(val, &phy0_ctrl->phy_con1);
-
- val = readl(&phy1_ctrl->phy_con1);
- val &= ~(CTRL_GATEDURADJ_MASK);
- writel(val, &phy1_ctrl->phy_con1);
-
- writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config);
- i = TIMEOUT_US;
- while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=
- RDLVL_COMPLETE_CHO) && (i > 0)) {
- /*
- * TODO(waihong): Comment on how long this take to
- * timeout
- */
- sdelay(100);
- i--;
- }
- if (!i)
- return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
- writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config);
-
- writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config);
- i = TIMEOUT_US;
- while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=
- RDLVL_COMPLETE_CHO) && (i > 0)) {
- /*
- * TODO(waihong): Comment on how long this take to
- * timeout
- */
- sdelay(100);
- i--;
- }
- if (!i)
- return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
- writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config);
-
- writel(0, &phy0_ctrl->phy_con14);
- writel(0, &phy1_ctrl->phy_con14);
-
- val = (0x3 << DIRECT_CMD_BANK_SHIFT);
- for (chip = 0; chip < mem->chips_to_configure; chip++) {
- writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
- &drex0->directcmd);
- writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
- &drex1->directcmd);
- }
-
- /* Common Settings for Leveling */
- val = PHY_CON12_RESET_VAL;
- writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12);
- writel((val + n_lock_w_phy1), &phy1_ctrl->phy_con12);
-
- setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN);
- setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN);
- }
-
- /*
- * Do software read leveling
- *
- * Do this before we turn on auto refresh since the auto refresh can
- * be in conflict with the resync operation that's part of setting
- * read leveling.
- */
- if (!reset) {
- /* restore calibrated value after resume */
- dmc_set_read_offset_value(phy0_ctrl, readl(&pmu->pmu_spare1));
- dmc_set_read_offset_value(phy1_ctrl, readl(&pmu->pmu_spare2));
- } else {
- software_find_read_offset(phy0_ctrl, 0,
- CTRL_LOCK_COARSE(lock0_info));
- software_find_read_offset(phy1_ctrl, 1,
- CTRL_LOCK_COARSE(lock1_info));
- /* save calibrated value to restore after resume */
- writel(dmc_get_read_offset_value(phy0_ctrl), &pmu->pmu_spare1);
- writel(dmc_get_read_offset_value(phy1_ctrl), &pmu->pmu_spare2);
- }
-
- /* Send PALL command */
- dmc_config_prech(mem, &drex0->directcmd);
- dmc_config_prech(mem, &drex1->directcmd);
-
- writel(mem->memcontrol, &drex0->memcontrol);
- writel(mem->memcontrol, &drex1->memcontrol);
-
- /*
- * Set DMC Concontrol: Enable auto-refresh counter, provide
- * read data fetch cycles and enable DREX auto set powerdown
- * for input buffer of I/O in none read memory state.
- */
- writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
- (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
- DMC_CONCONTROL_IO_PD_CON(0x2),
- &drex0->concontrol);
- writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
- (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
- DMC_CONCONTROL_IO_PD_CON(0x2),
- &drex1->concontrol);
-
- /*
- * Enable Clock Gating Control for DMC
- * this saves around 25 mw dmc power as compared to the power
- * consumption without these bits enabled
- */
- setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
- setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
-
- /*
- * As per Exynos5800 UM ver 0.00 section 17.13.2.1
- * CONCONTROL register bit 3 [update_mode], Exynos5800 does not
- * support the PHY initiated update. And it is recommended to set
- * this field to 1'b1 during initialization
- *
- * When we apply PHY-initiated mode, DLL lock value is determined
- * once at DMC init time and not updated later when we change the MIF
- * voltage based on ASV group in kernel. Applying MC-initiated mode
- * makes sure that DLL tracing is ON so that silicon is able to
- * compensate the voltage variation.
- */
- val = readl(&drex0->concontrol);
- val |= CONCONTROL_UPDATE_MODE;
- writel(val , &drex0->concontrol);
- val = readl(&drex1->concontrol);
- val |= CONCONTROL_UPDATE_MODE;
- writel(val , &drex1->concontrol);
-
- return 0;
-}
-#endif
+++ /dev/null
-/*
- * Memory setup for board based on EXYNOS4210
- *
- * Copyright (C) 2013 Samsung Electronics
- * Rajeshwari Shinde <rajeshwari.s@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/dmc.h>
-#include "common_setup.h"
-#include "exynos4_setup.h"
-
-struct mem_timings mem = {
- .direct_cmd_msr = {
- DIRECT_CMD1, DIRECT_CMD2, DIRECT_CMD3, DIRECT_CMD4
- },
- .timingref = TIMINGREF_VAL,
- .timingrow = TIMINGROW_VAL,
- .timingdata = TIMINGDATA_VAL,
- .timingpower = TIMINGPOWER_VAL,
- .zqcontrol = ZQ_CONTROL_VAL,
- .control0 = CONTROL0_VAL,
- .control1 = CONTROL1_VAL,
- .control2 = CONTROL2_VAL,
- .concontrol = CONCONTROL_VAL,
- .prechconfig = PRECHCONFIG,
- .memcontrol = MEMCONTROL_VAL,
- .memconfig0 = MEMCONFIG0_VAL,
- .memconfig1 = MEMCONFIG1_VAL,
- .dll_resync = FORCE_DLL_RESYNC,
- .dll_on = DLL_CONTROL_ON,
-};
-static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc)
-{
- if (ctrl_no) {
- writel((mem.control1 | (1 << mem.dll_resync)),
- &dmc->phycontrol1);
- writel((mem.control1 | (0 << mem.dll_resync)),
- &dmc->phycontrol1);
- } else {
- writel((mem.control0 | (0 << mem.dll_on)),
- &dmc->phycontrol0);
- writel((mem.control0 | (1 << mem.dll_on)),
- &dmc->phycontrol0);
- }
-}
-
-static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip)
-{
- int i;
- unsigned long mask = 0;
-
- if (chip)
- mask = DIRECT_CMD_CHIP1_SHIFT;
-
- for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
- writel(mem.direct_cmd_msr[i] | mask,
- &dmc->directcmd);
- }
-}
-
-static void dmc_init(struct exynos4_dmc *dmc)
-{
- /*
- * DLL Parameter Setting:
- * Termination: Enable R/W
- * Phase Delay for DQS Cleaning: 180' Shift
- */
- writel(mem.control1, &dmc->phycontrol1);
-
- /*
- * ZQ Calibration
- * Termination: Disable
- * Auto Calibration Start: Enable
- */
- writel(mem.zqcontrol, &dmc->phyzqcontrol);
- sdelay(0x100000);
-
- /*
- * Update DLL Information:
- * Force DLL Resyncronization
- */
- phy_control_reset(1, dmc);
- phy_control_reset(0, dmc);
-
- /* Set DLL Parameters */
- writel(mem.control1, &dmc->phycontrol1);
-
- /* DLL Start */
- writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc->phycontrol0);
-
- writel(mem.control2, &dmc->phycontrol2);
-
- /* Set Clock Ratio of Bus clock to Memory Clock */
- writel(mem.concontrol, &dmc->concontrol);
-
- /*
- * Memor Burst length: 8
- * Number of chips: 2
- * Memory Bus width: 32 bit
- * Memory Type: DDR3
- * Additional Latancy for PLL: 1 Cycle
- */
- writel(mem.memcontrol, &dmc->memcontrol);
-
- writel(mem.memconfig0, &dmc->memconfig0);
- writel(mem.memconfig1, &dmc->memconfig1);
-
- /* Config Precharge Policy */
- writel(mem.prechconfig, &dmc->prechconfig);
- /*
- * TimingAref, TimingRow, TimingData, TimingPower Setting:
- * Values as per Memory AC Parameters
- */
- writel(mem.timingref, &dmc->timingref);
- writel(mem.timingrow, &dmc->timingrow);
- writel(mem.timingdata, &dmc->timingdata);
- writel(mem.timingpower, &dmc->timingpower);
-
- /* Chip0: NOP Command: Assert and Hold CKE to high level */
- writel(DIRECT_CMD_NOP, &dmc->directcmd);
- sdelay(0x100000);
-
- /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
- dmc_config_mrs(dmc, 0);
- sdelay(0x100000);
-
- /* Chip0: ZQINIT */
- writel(DIRECT_CMD_ZQ, &dmc->directcmd);
- sdelay(0x100000);
-
- writel((DIRECT_CMD_NOP | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd);
- sdelay(0x100000);
-
- /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
- dmc_config_mrs(dmc, 1);
- sdelay(0x100000);
-
- /* Chip1: ZQINIT */
- writel((DIRECT_CMD_ZQ | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd);
- sdelay(0x100000);
-
- phy_control_reset(1, dmc);
- sdelay(0x100000);
-
- /* turn on DREX0, DREX1 */
- writel((mem.concontrol | AREF_EN), &dmc->concontrol);
-}
-
-void mem_ctrl_init(int reset)
-{
- struct exynos4_dmc *dmc;
-
- /*
- * Async bridge configuration at CPU_core:
- * 1: half_sync
- * 0: full_sync
- */
- writel(1, ASYNC_CONFIG);
-#ifdef CONFIG_ORIGEN
- /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
- writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
- APB_SFR_INTERLEAVE_CONF_OFFSET);
- /* Update MIU Configuration */
- writel(APB_SFR_ARBRITATION_CONF_VAL, EXYNOS4_MIU_BASE +
- APB_SFR_ARBRITATION_CONF_OFFSET);
-#else
- writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
- APB_SFR_INTERLEAVE_CONF_OFFSET);
- writel(INTERLEAVE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
- ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET);
- writel(INTERLEAVE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
- ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET);
- writel(INTERLEAVE_ADDR_MAP_EN, EXYNOS4_MIU_BASE +
- ABP_SFR_SLV_ADDRMAP_CONF_OFFSET);
-#ifdef CONFIG_MIU_LINEAR
- writel(SLAVE0_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
- ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET);
- writel(SLAVE0_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
- ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET);
- writel(SLAVE1_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
- ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET);
- writel(SLAVE1_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
- ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET);
- writel(APB_SFR_SLV_ADDR_MAP_CONF_VAL, EXYNOS4_MIU_BASE +
- ABP_SFR_SLV_ADDRMAP_CONF_OFFSET);
-#endif
-#endif
- /* DREX0 */
- dmc = (struct exynos4_dmc *)samsung_get_base_dmc_ctrl();
- dmc_init(dmc);
- dmc = (struct exynos4_dmc *)(samsung_get_base_dmc_ctrl()
- + DMC_OFFSET);
- dmc_init(dmc);
-}
+++ /dev/null
-/*
- * Machine Specific Values for EXYNOS4012 based board
- *
- * Copyright (C) 2011 Samsung Electronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ORIGEN_SETUP_H
-#define _ORIGEN_SETUP_H
-
-#include <config.h>
-#include <asm/arch/cpu.h>
-
-#ifdef CONFIG_CLK_800_330_165
-#define DRAM_CLK_330
-#endif
-#ifdef CONFIG_CLK_1000_200_200
-#define DRAM_CLK_200
-#endif
-#ifdef CONFIG_CLK_1000_330_165
-#define DRAM_CLK_330
-#endif
-#ifdef CONFIG_CLK_1000_400_200
-#define DRAM_CLK_400
-#endif
-
-/* Bus Configuration Register Address */
-#define ASYNC_CONFIG 0x10010350
-
-/* CLK_SRC_CPU */
-#define MUX_HPM_SEL_MOUTAPLL 0x0
-#define MUX_HPM_SEL_SCLKMPLL 0x1
-#define MUX_CORE_SEL_MOUTAPLL 0x0
-#define MUX_CORE_SEL_SCLKMPLL 0x1
-#define MUX_MPLL_SEL_FILPLL 0x0
-#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
-#define MUX_APLL_SEL_FILPLL 0x0
-#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
-#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \
- | (MUX_CORE_SEL_MOUTAPLL << 16) \
- | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
- | (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
-
-/* CLK_DIV_CPU0 */
-#define APLL_RATIO 0x0
-#define PCLK_DBG_RATIO 0x1
-#define ATB_RATIO 0x3
-#define PERIPH_RATIO 0x3
-#define COREM1_RATIO 0x7
-#define COREM0_RATIO 0x3
-#define CORE_RATIO 0x0
-#define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \
- | (PCLK_DBG_RATIO << 20) \
- | (ATB_RATIO << 16) \
- | (PERIPH_RATIO << 12) \
- | (COREM1_RATIO << 8) \
- | (COREM0_RATIO << 4) \
- | (CORE_RATIO << 0))
-
-/* CLK_DIV_CPU1 */
-#define HPM_RATIO 0x0
-#define COPY_RATIO 0x3
-#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO))
-
-/* CLK_SRC_DMC */
-#define MUX_PWI_SEL_XXTI 0x0
-#define MUX_PWI_SEL_XUSBXTI 0x1
-#define MUX_PWI_SEL_SCLK_HDMI24M 0x2
-#define MUX_PWI_SEL_SCLK_USBPHY0 0x3
-#define MUX_PWI_SEL_SCLK_USBPHY1 0x4
-#define MUX_PWI_SEL_SCLK_HDMIPHY 0x5
-#define MUX_PWI_SEL_SCLKMPLL 0x6
-#define MUX_PWI_SEL_SCLKEPLL 0x7
-#define MUX_PWI_SEL_SCLKVPLL 0x8
-#define MUX_DPHY_SEL_SCLKMPLL 0x0
-#define MUX_DPHY_SEL_SCLKAPLL 0x1
-#define MUX_DMC_BUS_SEL_SCLKMPLL 0x0
-#define MUX_DMC_BUS_SEL_SCLKAPLL 0x1
-#define CLK_SRC_DMC_VAL ((MUX_PWI_SEL_XUSBXTI << 16) \
- | (MUX_DPHY_SEL_SCLKMPLL << 8) \
- | (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
-
-/* CLK_DIV_DMC0 */
-#define CORE_TIMERS_RATIO 0x1
-#define COPY2_RATIO 0x3
-#define DMCP_RATIO 0x1
-#define DMCD_RATIO 0x1
-#define DMC_RATIO 0x1
-#define DPHY_RATIO 0x1
-#define ACP_PCLK_RATIO 0x1
-#define ACP_RATIO 0x3
-#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
- | (COPY2_RATIO << 24) \
- | (DMCP_RATIO << 20) \
- | (DMCD_RATIO << 16) \
- | (DMC_RATIO << 12) \
- | (DPHY_RATIO << 8) \
- | (ACP_PCLK_RATIO << 4) \
- | (ACP_RATIO << 0))
-
-/* CLK_DIV_DMC1 */
-#define DPM_RATIO 0x1
-#define DVSEM_RATIO 0x1
-#define PWI_RATIO 0x1
-#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \
- | (DVSEM_RATIO << 16) \
- | (PWI_RATIO << 8))
-
-/* CLK_SRC_TOP0 */
-#define MUX_ONENAND_SEL_ACLK_133 0x0
-#define MUX_ONENAND_SEL_ACLK_160 0x1
-#define MUX_ACLK_133_SEL_SCLKMPLL 0x0
-#define MUX_ACLK_133_SEL_SCLKAPLL 0x1
-#define MUX_ACLK_160_SEL_SCLKMPLL 0x0
-#define MUX_ACLK_160_SEL_SCLKAPLL 0x1
-#define MUX_ACLK_100_SEL_SCLKMPLL 0x0
-#define MUX_ACLK_100_SEL_SCLKAPLL 0x1
-#define MUX_ACLK_200_SEL_SCLKMPLL 0x0
-#define MUX_ACLK_200_SEL_SCLKAPLL 0x1
-#define MUX_VPLL_SEL_FINPLL 0x0
-#define MUX_VPLL_SEL_FOUTVPLL 0x1
-#define MUX_EPLL_SEL_FINPLL 0x0
-#define MUX_EPLL_SEL_FOUTEPLL 0x1
-#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
-#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
-#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_133 << 28) \
- | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
- | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
- | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
- | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
- | (MUX_VPLL_SEL_FINPLL << 8) \
- | (MUX_EPLL_SEL_FINPLL << 4)\
- | (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
-
-/* CLK_SRC_TOP1 */
-#define VPLLSRC_SEL_FINPLL 0x0
-#define VPLLSRC_SEL_SCLKHDMI24M 0x1
-#define CLK_SRC_TOP1_VAL (VPLLSRC_SEL_FINPLL)
-
-/* CLK_DIV_TOP */
-#define ONENAND_RATIO 0x0
-#define ACLK_133_RATIO 0x5
-#define ACLK_160_RATIO 0x4
-#define ACLK_100_RATIO 0x7
-#define ACLK_200_RATIO 0x3
-#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \
- | (ACLK_133_RATIO << 12)\
- | (ACLK_160_RATIO << 8) \
- | (ACLK_100_RATIO << 4) \
- | (ACLK_200_RATIO << 0))
-
-/* CLK_SRC_LEFTBUS */
-#define MUX_GDL_SEL_SCLKMPLL 0x0
-#define MUX_GDL_SEL_SCLKAPLL 0x1
-#define CLK_SRC_LEFTBUS_VAL (MUX_GDL_SEL_SCLKMPLL)
-
-/* CLK_DIV_LEFTBUS */
-#define GPL_RATIO 0x1
-#define GDL_RATIO 0x3
-#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO))
-
-/* CLK_SRC_RIGHTBUS */
-#define MUX_GDR_SEL_SCLKMPLL 0x0
-#define MUX_GDR_SEL_SCLKAPLL 0x1
-#define CLK_SRC_RIGHTBUS_VAL (MUX_GDR_SEL_SCLKMPLL)
-
-/* CLK_DIV_RIGHTBUS */
-#define GPR_RATIO 0x1
-#define GDR_RATIO 0x3
-#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO))
-
-/* CLK_SRS_FSYS: 6 = SCLKMPLL */
-#define SATA_SEL_SCLKMPLL 0
-#define SATA_SEL_SCLKAPLL 1
-
-#define MMC_SEL_XXTI 0
-#define MMC_SEL_XUSBXTI 1
-#define MMC_SEL_SCLK_HDMI24M 2
-#define MMC_SEL_SCLK_USBPHY0 3
-#define MMC_SEL_SCLK_USBPHY1 4
-#define MMC_SEL_SCLK_HDMIPHY 5
-#define MMC_SEL_SCLKMPLL 6
-#define MMC_SEL_SCLKEPLL 7
-#define MMC_SEL_SCLKVPLL 8
-
-#define MMCC0_SEL MMC_SEL_SCLKMPLL
-#define MMCC1_SEL MMC_SEL_SCLKMPLL
-#define MMCC2_SEL MMC_SEL_SCLKMPLL
-#define MMCC3_SEL MMC_SEL_SCLKMPLL
-#define MMCC4_SEL MMC_SEL_SCLKMPLL
-#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
- | (MMCC4_SEL << 16) \
- | (MMCC3_SEL << 12) \
- | (MMCC2_SEL << 8) \
- | (MMCC1_SEL << 4) \
- | (MMCC0_SEL << 0))
-
-/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
-/* CLK_DIV_FSYS1 */
-#define MMC0_RATIO 0xF
-#define MMC0_PRE_RATIO 0x0
-#define MMC1_RATIO 0xF
-#define MMC1_PRE_RATIO 0x0
-#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
- | (MMC1_RATIO << 16) \
- | (MMC0_PRE_RATIO << 8) \
- | (MMC0_RATIO << 0))
-
-/* CLK_DIV_FSYS2 */
-#define MMC2_RATIO 0xF
-#define MMC2_PRE_RATIO 0x0
-#define MMC3_RATIO 0xF
-#define MMC3_PRE_RATIO 0x0
-#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
- | (MMC3_RATIO << 16) \
- | (MMC2_PRE_RATIO << 8) \
- | (MMC2_RATIO << 0))
-
-/* CLK_DIV_FSYS3 */
-#define MMC4_RATIO 0xF
-#define MMC4_PRE_RATIO 0x0
-#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
- | (MMC4_RATIO << 0))
-
-/* CLK_SRC_PERIL0 */
-#define UART_SEL_XXTI 0
-#define UART_SEL_XUSBXTI 1
-#define UART_SEL_SCLK_HDMI24M 2
-#define UART_SEL_SCLK_USBPHY0 3
-#define UART_SEL_SCLK_USBPHY1 4
-#define UART_SEL_SCLK_HDMIPHY 5
-#define UART_SEL_SCLKMPLL 6
-#define UART_SEL_SCLKEPLL 7
-#define UART_SEL_SCLKVPLL 8
-
-#define UART0_SEL UART_SEL_SCLKMPLL
-#define UART1_SEL UART_SEL_SCLKMPLL
-#define UART2_SEL UART_SEL_SCLKMPLL
-#define UART3_SEL UART_SEL_SCLKMPLL
-#define UART4_SEL UART_SEL_SCLKMPLL
-#define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \
- | (UART3_SEL << 12) \
- | (UART2_SEL << 8) \
- | (UART1_SEL << 4) \
- | (UART0_SEL << 0))
-
-/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
-/* CLK_DIV_PERIL0 */
-#define UART0_RATIO 7
-#define UART1_RATIO 7
-#define UART2_RATIO 7
-#define UART3_RATIO 7
-#define UART4_RATIO 7
-#define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \
- | (UART3_RATIO << 12) \
- | (UART2_RATIO << 8) \
- | (UART1_RATIO << 4) \
- | (UART0_RATIO << 0))
-
-/* Clock Source CAM/FIMC */
-/* CLK_SRC_CAM */
-#define CAM0_SEL_XUSBXTI 1
-#define CAM1_SEL_XUSBXTI 1
-#define CSIS0_SEL_XUSBXTI 1
-#define CSIS1_SEL_XUSBXTI 1
-
-#define FIMC_SEL_SCLKMPLL 6
-#define FIMC0_LCLK_SEL FIMC_SEL_SCLKMPLL
-#define FIMC1_LCLK_SEL FIMC_SEL_SCLKMPLL
-#define FIMC2_LCLK_SEL FIMC_SEL_SCLKMPLL
-#define FIMC3_LCLK_SEL FIMC_SEL_SCLKMPLL
-
-#define CLK_SRC_CAM_VAL ((CSIS1_SEL_XUSBXTI << 28) \
- | (CSIS0_SEL_XUSBXTI << 24) \
- | (CAM1_SEL_XUSBXTI << 20) \
- | (CAM0_SEL_XUSBXTI << 16) \
- | (FIMC3_LCLK_SEL << 12) \
- | (FIMC2_LCLK_SEL << 8) \
- | (FIMC1_LCLK_SEL << 4) \
- | (FIMC0_LCLK_SEL << 0))
-
-/* SCLK CAM */
-/* CLK_DIV_CAM */
-#define FIMC0_LCLK_RATIO 4
-#define FIMC1_LCLK_RATIO 4
-#define FIMC2_LCLK_RATIO 4
-#define FIMC3_LCLK_RATIO 4
-#define CLK_DIV_CAM_VAL ((FIMC3_LCLK_RATIO << 12) \
- | (FIMC2_LCLK_RATIO << 8) \
- | (FIMC1_LCLK_RATIO << 4) \
- | (FIMC0_LCLK_RATIO << 0))
-
-/* SCLK MFC */
-/* CLK_SRC_MFC */
-#define MFC_SEL_MPLL 0
-#define MOUTMFC_0 0
-#define MFC_SEL MOUTMFC_0
-#define MFC_0_SEL MFC_SEL_MPLL
-#define CLK_SRC_MFC_VAL ((MFC_SEL << 8) | (MFC_0_SEL))
-
-
-/* CLK_DIV_MFC */
-#define MFC_RATIO 3
-#define CLK_DIV_MFC_VAL (MFC_RATIO)
-
-/* SCLK G3D */
-/* CLK_SRC_G3D */
-#define G3D_SEL_MPLL 0
-#define MOUTG3D_0 0
-#define G3D_SEL MOUTG3D_0
-#define G3D_0_SEL G3D_SEL_MPLL
-#define CLK_SRC_G3D_VAL ((G3D_SEL << 8) | (G3D_0_SEL))
-
-/* CLK_DIV_G3D */
-#define G3D_RATIO 1
-#define CLK_DIV_G3D_VAL (G3D_RATIO)
-
-/* SCLK LCD0 */
-/* CLK_SRC_LCD0 */
-#define FIMD_SEL_SCLKMPLL 6
-#define MDNIE0_SEL_XUSBXTI 1
-#define MDNIE_PWM0_SEL_XUSBXTI 1
-#define MIPI0_SEL_XUSBXTI 1
-#define CLK_SRC_LCD0_VAL ((MIPI0_SEL_XUSBXTI << 12) \
- | (MDNIE_PWM0_SEL_XUSBXTI << 8) \
- | (MDNIE0_SEL_XUSBXTI << 4) \
- | (FIMD_SEL_SCLKMPLL << 0))
-
-/* CLK_DIV_LCD0 */
-#define FIMD0_RATIO 4
-#define CLK_DIV_LCD0_VAL (FIMD0_RATIO)
-
-/* Required period to generate a stable clock output */
-/* PLL_LOCK_TIME */
-#define PLL_LOCKTIME 0x1C20
-
-/* PLL Values */
-#define DISABLE 0
-#define ENABLE 1
-#define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\
- | (mdiv << 16) \
- | (pdiv << 8) \
- | (sdiv << 0))
-
-/* APLL_CON0 */
-#define APLL_MDIV 0xFA
-#define APLL_PDIV 0x6
-#define APLL_SDIV 0x1
-#define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
-
-/* APLL_CON1 */
-#define APLL_AFC_ENB 0x1
-#define APLL_AFC 0xC
-#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
-
-/* MPLL_CON0 */
-#define MPLL_MDIV 0xC8
-#define MPLL_PDIV 0x6
-#define MPLL_SDIV 0x1
-#define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
-
-/* MPLL_CON1 */
-#define MPLL_AFC_ENB 0x0
-#define MPLL_AFC 0x1C
-#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
-
-/* EPLL_CON0 */
-#define EPLL_MDIV 0x30
-#define EPLL_PDIV 0x3
-#define EPLL_SDIV 0x2
-#define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
-
-/* EPLL_CON1 */
-#define EPLL_K 0x0
-#define EPLL_CON1_VAL (EPLL_K >> 0)
-
-/* VPLL_CON0 */
-#define VPLL_MDIV 0x35
-#define VPLL_PDIV 0x3
-#define VPLL_SDIV 0x2
-#define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
-
-/* VPLL_CON1 */
-#define VPLL_SSCG_EN DISABLE
-#define VPLL_SEL_PF_DN_SPREAD 0x0
-#define VPLL_MRR 0x11
-#define VPLL_MFR 0x0
-#define VPLL_K 0x400
-#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
- | (VPLL_SEL_PF_DN_SPREAD << 29) \
- | (VPLL_MRR << 24) \
- | (VPLL_MFR << 16) \
- | (VPLL_K << 0))
-
-/* DMC */
-#define DIRECT_CMD_NOP 0x07000000
-#define DIRECT_CMD_ZQ 0x0a000000
-#define DIRECT_CMD_CHIP1_SHIFT (1 << 20)
-#define MEM_TIMINGS_MSR_COUNT 4
-#define CTRL_START (1 << 0)
-#define CTRL_DLL_ON (1 << 1)
-#define AREF_EN (1 << 5)
-#define DRV_TYPE (1 << 6)
-
-struct mem_timings {
- unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
- unsigned timingref;
- unsigned timingrow;
- unsigned timingdata;
- unsigned timingpower;
- unsigned zqcontrol;
- unsigned control0;
- unsigned control1;
- unsigned control2;
- unsigned concontrol;
- unsigned prechconfig;
- unsigned memcontrol;
- unsigned memconfig0;
- unsigned memconfig1;
- unsigned dll_resync;
- unsigned dll_on;
-};
-
-/* MIU */
-/* MIU Config Register Offsets*/
-#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400
-#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
-#define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET 0x800
-#define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET 0x808
-#define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET 0x810
-#define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET 0x818
-#define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET 0x820
-#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET 0x828
-#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET 0x830
-
-#ifdef CONFIG_ORIGEN
-/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
-#define APB_SFR_INTERLEAVE_CONF_VAL 0x20001507
-#define APB_SFR_ARBRITATION_CONF_VAL 0x00000001
-#endif
-
-#define INTERLEAVE_ADDR_MAP_START_ADDR 0x40000000
-#define INTERLEAVE_ADDR_MAP_END_ADDR 0xbfffffff
-#define INTERLEAVE_ADDR_MAP_EN 0x00000001
-
-#ifdef CONFIG_MIU_1BIT_INTERLEAVED
-/* Interleave_bit0: 0xC*/
-#define APB_SFR_INTERLEAVE_CONF_VAL 0x0000000c
-#endif
-#ifdef CONFIG_MIU_2BIT_INTERLEAVED
-/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */
-#define APB_SFR_INTERLEAVE_CONF_VAL 0x2000150c
-#endif
-#define SLAVE0_SINGLE_ADDR_MAP_START_ADDR 0x40000000
-#define SLAVE0_SINGLE_ADDR_MAP_END_ADDR 0x7fffffff
-#define SLAVE1_SINGLE_ADDR_MAP_START_ADDR 0x80000000
-#define SLAVE1_SINGLE_ADDR_MAP_END_ADDR 0xbfffffff
-/* Enable SME0 and SME1*/
-#define APB_SFR_SLV_ADDR_MAP_CONF_VAL 0x00000006
-
-#define FORCE_DLL_RESYNC 3
-#define DLL_CONTROL_ON 1
-
-#define DIRECT_CMD1 0x00020000
-#define DIRECT_CMD2 0x00030000
-#define DIRECT_CMD3 0x00010002
-#define DIRECT_CMD4 0x00000328
-
-#define CTRL_ZQ_MODE_NOTERM (0x1 << 0)
-#define CTRL_ZQ_START (0x1 << 1)
-#define CTRL_ZQ_DIV (0 << 4)
-#define CTRL_ZQ_MODE_DDS (0x7 << 8)
-#define CTRL_ZQ_MODE_TERM (0x2 << 11)
-#define CTRL_ZQ_FORCE_IMPN (0x5 << 14)
-#define CTRL_ZQ_FORCE_IMPP (0x6 << 17)
-#define CTRL_DCC (0xE38 << 20)
-#define ZQ_CONTROL_VAL (CTRL_ZQ_MODE_NOTERM | CTRL_ZQ_START\
- | CTRL_ZQ_DIV | CTRL_ZQ_MODE_DDS\
- | CTRL_ZQ_MODE_TERM | CTRL_ZQ_FORCE_IMPN\
- | CTRL_ZQ_FORCE_IMPP | CTRL_DCC)
-
-#define ASYNC (0 << 0)
-#define CLK_RATIO (1 << 1)
-#define DIV_PIPE (1 << 3)
-#define AWR_ON (1 << 4)
-#define AREF_DISABLE (0 << 5)
-#define DRV_TYPE_DISABLE (0 << 6)
-#define CHIP0_NOT_EMPTY (0 << 8)
-#define CHIP1_NOT_EMPTY (0 << 9)
-#define DQ_SWAP_DISABLE (0 << 10)
-#define QOS_FAST_DISABLE (0 << 11)
-#define RD_FETCH (0x3 << 12)
-#define TIMEOUT_LEVEL0 (0xFFF << 16)
-#define CONCONTROL_VAL (ASYNC | CLK_RATIO | DIV_PIPE | AWR_ON\
- | AREF_DISABLE | DRV_TYPE_DISABLE\
- | CHIP0_NOT_EMPTY | CHIP1_NOT_EMPTY\
- | DQ_SWAP_DISABLE | QOS_FAST_DISABLE\
- | RD_FETCH | TIMEOUT_LEVEL0)
-
-#define CLK_STOP_DISABLE (0 << 1)
-#define DPWRDN_DISABLE (0 << 2)
-#define DPWRDN_TYPE (0 << 3)
-#define TP_DISABLE (0 << 4)
-#define DSREF_DIABLE (0 << 5)
-#define ADD_LAT_PALL (1 << 6)
-#define MEM_TYPE_DDR3 (0x6 << 8)
-#define MEM_WIDTH_32 (0x2 << 12)
-#define NUM_CHIP_2 (1 << 16)
-#define BL_8 (0x3 << 20)
-#define MEMCONTROL_VAL (CLK_STOP_DISABLE | DPWRDN_DISABLE\
- | DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\
- | ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\
- | NUM_CHIP_2 | BL_8)
-
-
-#define CHIP_BANK_8 (0x3 << 0)
-#define CHIP_ROW_14 (0x2 << 4)
-#define CHIP_COL_10 (0x3 << 8)
-#define CHIP_MAP_INTERLEAVED (1 << 12)
-#define CHIP_MASK (0xe0 << 16)
-#ifdef CONFIG_MIU_LINEAR
-#define CHIP0_BASE (0x40 << 24)
-#define CHIP1_BASE (0x60 << 24)
-#else
-#define CHIP0_BASE (0x20 << 24)
-#define CHIP1_BASE (0x40 << 24)
-#endif
-#define MEMCONFIG0_VAL (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
- | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP0_BASE)
-#define MEMCONFIG1_VAL (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
- | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP1_BASE)
-
-#define TP_CNT (0xff << 24)
-#define PRECHCONFIG TP_CNT
-
-#define CTRL_OFF (0 << 0)
-#define CTRL_DLL_OFF (0 << 1)
-#define CTRL_HALF (0 << 2)
-#define CTRL_DFDQS (1 << 3)
-#define DQS_DELAY (0 << 4)
-#define CTRL_START_POINT (0x10 << 8)
-#define CTRL_INC (0x10 << 16)
-#define CTRL_FORCE (0x71 << 24)
-#define CONTROL0_VAL (CTRL_OFF | CTRL_DLL_OFF | CTRL_HALF\
- | CTRL_DFDQS | DQS_DELAY | CTRL_START_POINT\
- | CTRL_INC | CTRL_FORCE)
-
-#define CTRL_SHIFTC (0x6 << 0)
-#define CTRL_REF (8 << 4)
-#define CTRL_SHGATE (1 << 29)
-#define TERM_READ_EN (1 << 30)
-#define TERM_WRITE_EN (1 << 31)
-#define CONTROL1_VAL (CTRL_SHIFTC | CTRL_REF | CTRL_SHGATE\
- | TERM_READ_EN | TERM_WRITE_EN)
-
-#define CONTROL2_VAL 0x00000000
-
-#ifdef CONFIG_ORIGEN
-#define TIMINGREF_VAL 0x000000BB
-#define TIMINGROW_VAL 0x4046654f
-#define TIMINGDATA_VAL 0x46400506
-#define TIMINGPOWER_VAL 0x52000A3C
-#else
-#define TIMINGREF_VAL 0x000000BC
-#ifdef DRAM_CLK_330
-#define TIMINGROW_VAL 0x3545548d
-#define TIMINGDATA_VAL 0x45430506
-#define TIMINGPOWER_VAL 0x4439033c
-#endif
-#ifdef DRAM_CLK_400
-#define TIMINGROW_VAL 0x45430506
-#define TIMINGDATA_VAL 0x56500506
-#define TIMINGPOWER_VAL 0x5444033d
-#endif
-#endif
-#endif
+++ /dev/null
-/*
- * Machine Specific Values for SMDK5250 board based on EXYNOS5
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SMDK5250_SETUP_H
-#define _SMDK5250_SETUP_H
-
-#include <config.h>
-#include <asm/arch/dmc.h>
-
-#define NOT_AVAILABLE 0
-#define DATA_MASK 0xFFFFF
-
-#define ENABLE_BIT 0x1
-#define DISABLE_BIT 0x0
-#define CA_SWAP_EN (1 << 0)
-
-/* Set PLL */
-#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
-
-/* MEMCONTROL register bit fields */
-#define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
-#define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
-#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)
-#define DMC_MEMCONTROL_TP_DISABLE (0 << 4)
-#define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)
-#define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5)
-#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)
-
-#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8)
-#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8)
-#define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)
-
-#define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)
-
-#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16)
-#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)
-
-#define DMC_MEMCONTROL_BL_8 (3 << 20)
-#define DMC_MEMCONTROL_BL_4 (2 << 20)
-
-#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)
-
-#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25)
-#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25)
-#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25)
-#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)
-
-/* MEMCONFIG0 register bit fields */
-#define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12)
-#define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12)
-#define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8)
-#define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4)
-#define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4)
-#define DMC_MEMCONFIGX_CHIP_BANK_8 (3 << 0)
-
-#define DMC_MEMBASECONFIGX_CHIP_BASE(x) (x << 16)
-#define DMC_MEMBASECONFIGX_CHIP_MASK(x) (x << 0)
-#define DMC_MEMBASECONFIG_VAL(x) ( \
- DMC_MEMBASECONFIGX_CHIP_BASE(x) | \
- DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \
-)
-
-/*
- * As we use channel interleaving, therefore value of the base address
- * register must be set as half of the bus base address
- * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
- * we need to set half 0x10 to the membaseconfigx registers
- * see exynos5420 UM section 17.17.3.21 for more.
- */
-#define DMC_CHIP_BASE_0 0x10
-#define DMC_CHIP_BASE_1 0x50
-#define DMC_CHIP_MASK 0x7C0
-
-#define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
-#define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
-
-#define DMC_PRECHCONFIG_VAL 0xFF000000
-#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
-
-#define DMC_CONCONTROL_RESET_VAL 0x0FFF0000
-#define DFI_INIT_START (1 << 28)
-#define EMPTY (1 << 8)
-#define AREF_EN (1 << 5)
-
-#define DFI_INIT_COMPLETE_CHO (1 << 2)
-#define DFI_INIT_COMPLETE_CH1 (1 << 3)
-
-#define RDLVL_COMPLETE_CHO (1 << 14)
-#define RDLVL_COMPLETE_CH1 (1 << 15)
-
-#define CLK_STOP_EN (1 << 0)
-#define DPWRDN_EN (1 << 1)
-#define DSREF_EN (1 << 5)
-
-/* COJCONTROL register bit fields */
-#define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
-#define DMC_CONCONTROL_IO_PD_CON_ENABLE (1 << 3)
-#define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
-#define DMC_CONCONTROL_AREF_EN_ENABLE (1 << 5)
-#define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
-#define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
-#define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
-#define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
-#define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
-
-#define DMC_CONCONTROL_VAL 0x1FFF2101
-
-#define DREX_CONCONTROL_VAL DMC_CONCONTROL_VAL \
- | DMC_CONCONTROL_AREF_EN_ENABLE \
- | DMC_CONCONTROL_IO_PD_CON_ENABLE
-
-#define DMC_CONCONTROL_IO_PD_CON(x) (x << 6)
-
-/* CLK_DIV_CPU1 */
-#define HPM_RATIO 0x2
-#define COPY_RATIO 0x0
-
-/* CLK_DIV_CPU1 = 0x00000003 */
-#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
- | (COPY_RATIO))
-
-/* CLK_SRC_CORE0 */
-#define CLK_SRC_CORE0_VAL 0x00000000
-
-/* CLK_SRC_CORE1 */
-#define CLK_SRC_CORE1_VAL 0x100
-
-/* CLK_DIV_CORE0 */
-#define CLK_DIV_CORE0_VAL 0x00120000
-
-/* CLK_DIV_CORE1 */
-#define CLK_DIV_CORE1_VAL 0x07070700
-
-/* CLK_DIV_SYSRGT */
-#define CLK_DIV_SYSRGT_VAL 0x00000111
-
-/* CLK_DIV_ACP */
-#define CLK_DIV_ACP_VAL 0x12
-
-/* CLK_DIV_SYSLFT */
-#define CLK_DIV_SYSLFT_VAL 0x00000311
-
-#define MUX_APLL_SEL_MASK (1 << 0)
-#define MUX_MPLL_SEL_MASK (1 << 8)
-#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
-#define MUX_CPLL_SEL_MASK (1 << 8)
-#define MUX_EPLL_SEL_MASK (1 << 12)
-#define MUX_VPLL_SEL_MASK (1 << 16)
-#define MUX_GPLL_SEL_MASK (1 << 28)
-#define MUX_BPLL_SEL_MASK (1 << 0)
-#define MUX_HPM_SEL_MASK (1 << 20)
-#define HPM_SEL_SCLK_MPLL (1 << 21)
-#define PLL_LOCKED (1 << 29)
-#define APLL_CON0_LOCKED (1 << 29)
-#define MPLL_CON0_LOCKED (1 << 29)
-#define BPLL_CON0_LOCKED (1 << 29)
-#define CPLL_CON0_LOCKED (1 << 29)
-#define EPLL_CON0_LOCKED (1 << 29)
-#define GPLL_CON0_LOCKED (1 << 29)
-#define VPLL_CON0_LOCKED (1 << 29)
-#define CLK_REG_DISABLE 0x0
-#define TOP2_VAL 0x0110000
-
-/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
-#define SPI0_ISP_SEL 6
-#define SPI1_ISP_SEL 6
-#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
- | (SPI0_ISP_SEL << 0)
-
-/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
-#define SPI0_ISP_RATIO 0xf
-#define SPI1_ISP_RATIO 0xf
-#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
- | (SPI0_ISP_RATIO << 0)
-
-/* CLK_DIV_FSYS2 */
-#define MMC2_RATIO_MASK 0xf
-#define MMC2_RATIO_VAL 0x3
-#define MMC2_RATIO_OFFSET 0
-
-#define MMC2_PRE_RATIO_MASK 0xff
-#define MMC2_PRE_RATIO_VAL 0x9
-#define MMC2_PRE_RATIO_OFFSET 8
-
-#define MMC3_RATIO_MASK 0xf
-#define MMC3_RATIO_VAL 0x1
-#define MMC3_RATIO_OFFSET 16
-
-#define MMC3_PRE_RATIO_MASK 0xff
-#define MMC3_PRE_RATIO_VAL 0x0
-#define MMC3_PRE_RATIO_OFFSET 24
-
-/* CLK_SRC_LEX */
-#define CLK_SRC_LEX_VAL 0x0
-
-/* CLK_DIV_LEX */
-#define CLK_DIV_LEX_VAL 0x10
-
-/* CLK_DIV_R0X */
-#define CLK_DIV_R0X_VAL 0x10
-
-/* CLK_DIV_L0X */
-#define CLK_DIV_R1X_VAL 0x10
-
-/* CLK_DIV_ISP2 */
-#define CLK_DIV_ISP2_VAL 0x1
-
-/* CLK_SRC_KFC */
-#define SRC_KFC_HPM_SEL (1 << 15)
-
-/* CLK_SRC_KFC */
-#define CLK_SRC_KFC_VAL 0x00008001
-
-/* CLK_DIV_KFC */
-#define CLK_DIV_KFC_VAL 0x03300110
-
-/* CLK_DIV2_RATIO */
-#define CLK_DIV2_RATIO 0x10111150
-
-/* CLK_DIV4_RATIO */
-#define CLK_DIV4_RATIO 0x00000003
-
-/* CLK_DIV_G2D */
-#define CLK_DIV_G2D 0x00000010
-
-/*
- * DIV_DISP1_0
- * For DP, divisor should be 2
- */
-#define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
-
-/* CLK_GATE_IP_DISP1 */
-#define CLK_GATE_DP1_ALLOW (1 << 4)
-
-/* AUDIO CLK SEL */
-#define AUDIO0_SEL_EPLL (0x6 << 28)
-#define AUDIO0_RATIO 0x5
-#define PCM0_RATIO 0x3
-#define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20)
-
-/* CLK_SRC_CDREX */
-#define MUX_MCLK_CDR_MSPLL (1 << 4)
-#define MUX_BPLL_SEL_FOUTBPLL (1 << 0)
-#define BPLL_SEL_MASK 0x7
-#define FOUTBPLL 2
-
-#define DDR3PHY_CTRL_PHY_RESET (1 << 0)
-#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
-
-#define PHY_CON0_RESET_VAL 0x17020a40
-#define P0_CMD_EN (1 << 14)
-#define BYTE_RDLVL_EN (1 << 13)
-#define CTRL_SHGATE (1 << 8)
-
-#define PHY_CON1_RESET_VAL 0x09210100
-#define RDLVL_PASS_ADJ_VAL 0x6
-#define RDLVL_PASS_ADJ_OFFSET 16
-#define CTRL_GATEDURADJ_MASK (0xf << 20)
-#define READ_LEVELLING_DDR3 0x0100
-
-#define PHY_CON2_RESET_VAL 0x00010004
-#define INIT_DESKEW_EN (1 << 6)
-#define DLL_DESKEW_EN (1 << 12)
-#define RDLVL_GATE_EN (1 << 24)
-#define RDLVL_EN (1 << 25)
-#define RDLVL_INCR_ADJ (0x1 << 16)
-
-/* DREX_PAUSE */
-#define DREX_PAUSE_EN (1 << 0)
-
-#define BYPASS_EN (1 << 22)
-
-/* MEMMORY VAL */
-#define PHY_CON0_VAL 0x17021A00
-
-#define PHY_CON12_RESET_VAL 0x10100070
-#define PHY_CON12_VAL 0x10107F50
-#define CTRL_START (1 << 6)
-#define CTRL_DLL_ON (1 << 5)
-#define CTRL_LOCK_COARSE_OFFSET 10
-#define CTRL_LOCK_COARSE_MASK (0x7F << CTRL_LOCK_COARSE_OFFSET)
-#define CTRL_LOCK_COARSE(x) (((x) & CTRL_LOCK_COARSE_MASK) >> \
- CTRL_LOCK_COARSE_OFFSET)
-#define CTRL_FORCE_MASK (0x7F << 8)
-#define CTRL_FINE_LOCKED 0x7
-
-#define CTRL_OFFSETD_RESET_VAL 0x8
-#define CTRL_OFFSETD_VAL 0x7F
-
-#define CTRL_OFFSETR0 0x7F
-#define CTRL_OFFSETR1 0x7F
-#define CTRL_OFFSETR2 0x7F
-#define CTRL_OFFSETR3 0x7F
-#define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \
- CTRL_OFFSETR1 << 8 | \
- CTRL_OFFSETR2 << 16 | \
- CTRL_OFFSETR3 << 24)
-#define PHY_CON4_RESET_VAL 0x08080808
-
-#define CTRL_OFFSETW0 0x7F
-#define CTRL_OFFSETW1 0x7F
-#define CTRL_OFFSETW2 0x7F
-#define CTRL_OFFSETW3 0x7F
-#define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \
- CTRL_OFFSETW1 << 8 | \
- CTRL_OFFSETW2 << 16 | \
- CTRL_OFFSETW3 << 24)
-#define PHY_CON6_RESET_VAL 0x08080808
-
-#define PHY_CON14_RESET_VAL 0x001F0000
-#define CTRL_PULLD_DQS 0xF
-#define CTRL_PULLD_DQS_OFFSET 0
-
-/* ZQ Configurations */
-#define PHY_CON16_RESET_VAL 0x08000304
-
-#define ZQ_CLK_EN (1 << 27)
-#define ZQ_CLK_DIV_EN (1 << 18)
-#define ZQ_MANUAL_STR (1 << 1)
-#define ZQ_DONE (1 << 0)
-#define ZQ_MODE_DDS_OFFSET 24
-
-#define CTRL_RDLVL_GATE_ENABLE 1
-#define CTRL_RDLVL_GATE_DISABLE 0
-#define CTRL_RDLVL_DATA_ENABLE 2
-
-/* Direct Command */
-#define DIRECT_CMD_NOP 0x07000000
-#define DIRECT_CMD_PALL 0x01000000
-#define DIRECT_CMD_ZQINIT 0x0a000000
-#define DIRECT_CMD_CHANNEL_SHIFT 28
-#define DIRECT_CMD_CHIP_SHIFT 20
-#define DIRECT_CMD_BANK_SHIFT 16
-#define DIRECT_CMD_REFA (5 << 24)
-#define DIRECT_CMD_MRS1 0x71C00
-#define DIRECT_CMD_MRS2 0x10BFC
-#define DIRECT_CMD_MRS3 0x0050C
-#define DIRECT_CMD_MRS4 0x00868
-#define DIRECT_CMD_MRS5 0x00C04
-
-/* Drive Strength */
-#define IMPEDANCE_48_OHM 4
-#define IMPEDANCE_40_OHM 5
-#define IMPEDANCE_34_OHM 6
-#define IMPEDANCE_30_OHM 7
-#define PHY_CON39_VAL_48_OHM 0x09240924
-#define PHY_CON39_VAL_40_OHM 0x0B6D0B6D
-#define PHY_CON39_VAL_34_OHM 0x0DB60DB6
-#define PHY_CON39_VAL_30_OHM 0x0FFF0FFF
-
-#define CTRL_BSTLEN_OFFSET 8
-#define CTRL_RDLAT_OFFSET 0
-
-#define CMD_DEFAULT_LPDDR3 0xF
-#define CMD_DEFUALT_OFFSET 0
-#define T_WRDATA_EN 0x7
-#define T_WRDATA_EN_DDR3 0x8
-#define T_WRDATA_EN_OFFSET 16
-#define T_WRDATA_EN_MASK 0x1f
-
-#define PHY_CON31_VAL 0x0C183060
-#define PHY_CON32_VAL 0x60C18306
-#define PHY_CON33_VAL 0x00000030
-
-#define PHY_CON31_RESET_VAL 0x0
-#define PHY_CON32_RESET_VAL 0x0
-#define PHY_CON33_RESET_VAL 0x0
-
-#define SL_DLL_DYN_CON_EN (1 << 1)
-#define FP_RESYNC (1 << 3)
-#define CTRL_START (1 << 6)
-
-#define DMC_AREF_EN (1 << 5)
-#define DMC_CONCONTROL_EMPTY (1 << 8)
-#define DFI_INIT_START (1 << 28)
-
-#define DMC_MEMCONTROL_VAL 0x00312700
-#define CLK_STOP_EN (1 << 0)
-#define DPWRDN_EN (1 << 1)
-#define DSREF_EN (1 << 5)
-
-#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
-#define MEMBASECONFIG_CHIP_MASK_OFFSET 0
-#define MEMBASECONFIG0_CHIP_BASE_VAL 0x20
-#define MEMBASECONFIG1_CHIP_BASE_VAL 0x40
-#define CHIP_BASE_OFFSET 16
-
-#define MEMCONFIG_VAL 0x1323
-#define PRECHCONFIG_DEFAULT_VAL 0xFF000000
-#define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF
-
-#define TIMINGAREF_VAL 0x5d
-#define TIMINGROW_VAL 0x345A8692
-#define TIMINGDATA_VAL 0x3630065C
-#define TIMINGPOWER_VAL 0x50380336
-#define DFI_INIT_COMPLETE (1 << 3)
-
-#define BRBRSVCONTROL_VAL 0x00000033
-#define BRBRSVCONFIG_VAL 0x88778877
-
-/* Clock Gating Control (CGCONTROL) register */
-#define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */
-#define SCG_CG_EN (1 << 2) /* Scheduler clock gating */
-#define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */
-#define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */
-#define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \
- BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)
-
-/* DMC PHY Control0 register */
-#define PHY_CONTROL0_RESET_VAL 0x0
-#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
-#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
-#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
-#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
-
-/* Driver strength for CK, CKE, CS & CA */
-#define IMP_OUTPUT_DRV_40_OHM 0x5
-#define IMP_OUTPUT_DRV_30_OHM 0x7
-#define DA_3_DS_OFFSET 25
-#define DA_2_DS_OFFSET 22
-#define DA_1_DS_OFFSET 19
-#define DA_0_DS_OFFSET 16
-#define CA_CK_DRVR_DS_OFFSET 9
-#define CA_CKE_DRVR_DS_OFFSET 6
-#define CA_CS_DRVR_DS_OFFSET 3
-#define CA_ADR_DRVR_DS_OFFSET 0
-
-#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
-#define PHY_CON42_CTRL_RDLAT_SHIFT 0
-
-/*
- * Definitions that differ with SoC's.
- * Below is the part defining macros for Exynos5250.
- * Else part introduces macros for Exynos5420.
- */
-#ifndef CONFIG_EXYNOS5420
-
-/* APLL_CON1 */
-#define APLL_CON1_VAL (0x00203800)
-
-/* MPLL_CON1 */
-#define MPLL_CON1_VAL (0x00203800)
-
-/* CPLL_CON1 */
-#define CPLL_CON1_VAL (0x00203800)
-
-/* DPLL_CON1 */
-#define DPLL_CON1_VAL (NOT_AVAILABLE)
-
-/* GPLL_CON1 */
-#define GPLL_CON1_VAL (0x00203800)
-
-/* EPLL_CON1, CON2 */
-#define EPLL_CON1_VAL 0x00000000
-#define EPLL_CON2_VAL 0x00000080
-
-/* VPLL_CON1, CON2 */
-#define VPLL_CON1_VAL 0x00000000
-#define VPLL_CON2_VAL 0x00000080
-
-/* RPLL_CON1, CON2 */
-#define RPLL_CON1_VAL NOT_AVAILABLE
-#define RPLL_CON2_VAL NOT_AVAILABLE
-
-/* BPLL_CON1 */
-#define BPLL_CON1_VAL 0x00203800
-
-/* SPLL_CON1 */
-#define SPLL_CON1_VAL NOT_AVAILABLE
-
-/* IPLL_CON1 */
-#define IPLL_CON1_VAL NOT_AVAILABLE
-
-/* KPLL_CON1 */
-#define KPLL_CON1_VAL NOT_AVAILABLE
-
-/* CLK_SRC_ISP */
-#define CLK_SRC_ISP_VAL NOT_AVAILABLE
-#define CLK_DIV_ISP0_VAL 0x31
-#define CLK_DIV_ISP1_VAL 0x0
-
-/* CLK_FSYS */
-#define CLK_SRC_FSYS0_VAL 0x66666
-#define CLK_DIV_FSYS0_VAL 0x0BB00000
-#define CLK_DIV_FSYS1_VAL NOT_AVAILABLE
-#define CLK_DIV_FSYS2_VAL NOT_AVAILABLE
-
-/* CLK_SRC_CPU */
-/* 0 = MOUTAPLL, 1 = SCLKMPLL */
-#define MUX_HPM_SEL 0
-#define MUX_CPU_SEL 0
-#define MUX_APLL_SEL 1
-
-#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
- | (MUX_CPU_SEL << 16) \
- | (MUX_APLL_SEL))
-
-/* CLK_SRC_CDREX */
-#define CLK_SRC_CDREX_VAL 0x1
-
-/* CLK_DIV_CDREX */
-#define CLK_DIV_CDREX0_VAL NOT_AVAILABLE
-#define CLK_DIV_CDREX1_VAL NOT_AVAILABLE
-
-/* CLK_DIV_CPU0_VAL */
-#define CLK_DIV_CPU0_VAL NOT_AVAILABLE
-
-#define MCLK_CDREX2_RATIO 0x0
-#define ACLK_EFCON_RATIO 0x1
-#define MCLK_DPHY_RATIO 0x1
-#define MCLK_CDREX_RATIO 0x1
-#define ACLK_C2C_200_RATIO 0x1
-#define C2C_CLK_400_RATIO 0x1
-#define PCLK_CDREX_RATIO 0x1
-#define ACLK_CDREX_RATIO 0x1
-
-#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \
- | (C2C_CLK_400_RATIO << 6) \
- | (PCLK_CDREX_RATIO << 4) \
- | (ACLK_CDREX_RATIO))
-
-/* CLK_SRC_TOP0 */
-#define MUX_ACLK_300_GSCL_SEL 0x0
-#define MUX_ACLK_300_GSCL_MID_SEL 0x0
-#define MUX_ACLK_400_G3D_MID_SEL 0x0
-#define MUX_ACLK_333_SEL 0x0
-#define MUX_ACLK_300_DISP1_SEL 0x0
-#define MUX_ACLK_300_DISP1_MID_SEL 0x0
-#define MUX_ACLK_200_SEL 0x0
-#define MUX_ACLK_166_SEL 0x0
-#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
- | (MUX_ACLK_300_GSCL_MID_SEL << 24) \
- | (MUX_ACLK_400_G3D_MID_SEL << 20) \
- | (MUX_ACLK_333_SEL << 16) \
- | (MUX_ACLK_300_DISP1_SEL << 15) \
- | (MUX_ACLK_300_DISP1_MID_SEL << 14) \
- | (MUX_ACLK_200_SEL << 12) \
- | (MUX_ACLK_166_SEL << 8))
-
-/* CLK_SRC_TOP1 */
-#define MUX_ACLK_400_G3D_SEL 0x1
-#define MUX_ACLK_400_ISP_SEL 0x0
-#define MUX_ACLK_400_IOP_SEL 0x0
-#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
-#define MUX_ACLK_300_GSCL_MID1_SEL 0x0
-#define MUX_ACLK_300_DISP1_MID1_SEL 0x0
-#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \
- |(MUX_ACLK_400_ISP_SEL << 24) \
- |(MUX_ACLK_400_IOP_SEL << 20) \
- |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \
- |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \
- |(MUX_ACLK_300_DISP1_MID1_SEL << 8))
-
-/* CLK_SRC_TOP2 */
-#define MUX_GPLL_SEL 0x1
-#define MUX_BPLL_USER_SEL 0x0
-#define MUX_MPLL_USER_SEL 0x0
-#define MUX_VPLL_SEL 0x1
-#define MUX_EPLL_SEL 0x1
-#define MUX_CPLL_SEL 0x1
-#define VPLLSRC_SEL 0x0
-#define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \
- | (MUX_BPLL_USER_SEL << 24) \
- | (MUX_MPLL_USER_SEL << 20) \
- | (MUX_VPLL_SEL << 16) \
- | (MUX_EPLL_SEL << 12) \
- | (MUX_CPLL_SEL << 8) \
- | (VPLLSRC_SEL))
-/* CLK_SRC_TOP3 */
-#define MUX_ACLK_333_SUB_SEL 0x1
-#define MUX_ACLK_400_SUB_SEL 0x1
-#define MUX_ACLK_266_ISP_SUB_SEL 0x1
-#define MUX_ACLK_266_GPS_SUB_SEL 0x0
-#define MUX_ACLK_300_GSCL_SUB_SEL 0x1
-#define MUX_ACLK_266_GSCL_SUB_SEL 0x1
-#define MUX_ACLK_300_DISP1_SUB_SEL 0x1
-#define MUX_ACLK_200_DISP1_SUB_SEL 0x1
-#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
- | (MUX_ACLK_400_SUB_SEL << 20) \
- | (MUX_ACLK_266_ISP_SUB_SEL << 16) \
- | (MUX_ACLK_266_GPS_SUB_SEL << 12) \
- | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
- | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
- | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
- | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
-
-#define CLK_SRC_TOP4_VAL NOT_AVAILABLE
-#define CLK_SRC_TOP5_VAL NOT_AVAILABLE
-#define CLK_SRC_TOP6_VAL NOT_AVAILABLE
-#define CLK_SRC_TOP7_VAL NOT_AVAILABLE
-
-/* CLK_DIV_TOP0 */
-#define ACLK_300_DISP1_RATIO 0x2
-#define ACLK_400_G3D_RATIO 0x0
-#define ACLK_333_RATIO 0x0
-#define ACLK_266_RATIO 0x2
-#define ACLK_200_RATIO 0x3
-#define ACLK_166_RATIO 0x1
-#define ACLK_133_RATIO 0x1
-#define ACLK_66_RATIO 0x5
-
-#define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \
- | (ACLK_400_G3D_RATIO << 24) \
- | (ACLK_333_RATIO << 20) \
- | (ACLK_266_RATIO << 16) \
- | (ACLK_200_RATIO << 12) \
- | (ACLK_166_RATIO << 8) \
- | (ACLK_133_RATIO << 4) \
- | (ACLK_66_RATIO))
-
-/* CLK_DIV_TOP1 */
-#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
-#define ACLK_66_PRE_RATIO 0x1
-#define ACLK_400_ISP_RATIO 0x1
-#define ACLK_400_IOP_RATIO 0x1
-#define ACLK_300_GSCL_RATIO 0x2
-
-#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
- | (ACLK_66_PRE_RATIO << 24) \
- | (ACLK_400_ISP_RATIO << 20) \
- | (ACLK_400_IOP_RATIO << 16) \
- | (ACLK_300_GSCL_RATIO << 12))
-
-#define CLK_DIV_TOP2_VAL NOT_AVAILABLE
-
-/* PLL Lock Value Factor */
-#define PLL_LOCK_FACTOR 250
-#define PLL_X_LOCK_FACTOR 3000
-
-/* CLK_SRC_PERIC0 */
-#define PWM_SEL 6
-#define UART3_SEL 6
-#define UART2_SEL 6
-#define UART1_SEL 6
-#define UART0_SEL 6
-/* SRC_CLOCK = SCLK_MPLL */
-#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
- | (UART3_SEL << 12) \
- | (UART2_SEL << 8) \
- | (UART1_SEL << 4) \
- | (UART0_SEL))
-
-/* CLK_SRC_PERIC1 */
-/* SRC_CLOCK = SCLK_MPLL */
-#define SPI0_SEL 6
-#define SPI1_SEL 6
-#define SPI2_SEL 6
-#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \
- | (SPI1_SEL << 20) \
- | (SPI0_SEL << 16))
-
-/* CLK_DIV_PERIL0 */
-#define UART5_RATIO 7
-#define UART4_RATIO 7
-#define UART3_RATIO 7
-#define UART2_RATIO 7
-#define UART1_RATIO 7
-#define UART0_RATIO 7
-
-#define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \
- | (UART2_RATIO << 8) \
- | (UART1_RATIO << 4) \
- | (UART0_RATIO))
-/* CLK_DIV_PERIC1 */
-#define SPI1_RATIO 0x7
-#define SPI0_RATIO 0xf
-#define SPI1_SUB_RATIO 0x0
-#define SPI0_SUB_RATIO 0x0
-#define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \
- | ((SPI1_RATIO << 16) \
- | (SPI0_SUB_RATIO << 8) \
- | (SPI0_RATIO << 0)))
-
-/* CLK_DIV_PERIC2 */
-#define SPI2_RATIO 0xf
-#define SPI2_SUB_RATIO 0x0
-#define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \
- | (SPI2_RATIO << 0))
-
-/* CLK_DIV_PERIC3 */
-#define PWM_RATIO 8
-#define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
-
-
-/* CLK_DIV_PERIC4 */
-#define CLK_DIV_PERIC4_VAL NOT_AVAILABLE
-
-/* CLK_SRC_DISP1_0 */
-#define CLK_SRC_DISP1_0_VAL 0x6
-#define CLK_DIV_DISP1_0_VAL NOT_AVAILABLE
-
-#define APLL_FOUT (1 << 0)
-#define KPLL_FOUT NOT_AVAILABLE
-
-#define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
-
-#else
-
-#define CPU_CONFIG_STATUS_OFFSET 0x80
-#define CPU_RST_FLAG_VAL 0xFCBA0D10
-#define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000
-
-/* APLL_CON1 */
-#define APLL_CON1_VAL (0x0020F300)
-
-/* MPLL_CON1 */
-#define MPLL_CON1_VAL (0x0020F300)
-
-
-/* CPLL_CON1 */
-#define CPLL_CON1_VAL 0x0020f300
-
-/* DPLL_CON1 */
-#define DPLL_CON1_VAL (0x0020F300)
-
-/* GPLL_CON1 */
-#define GPLL_CON1_VAL (NOT_AVAILABLE)
-
-
-/* EPLL_CON1, CON2 */
-#define EPLL_CON1_VAL 0x00000000
-#define EPLL_CON2_VAL 0x00000080
-
-/* VPLL_CON1, CON2 */
-#define VPLL_CON1_VAL 0x0020f300
-#define VPLL_CON2_VAL NOT_AVAILABLE
-
-/* RPLL_CON1, CON2 */
-#define RPLL_CON1_VAL 0x00000000
-#define RPLL_CON2_VAL 0x00000080
-
-/* BPLL_CON1 */
-#define BPLL_CON1_VAL 0x0020f300
-
-/* SPLL_CON1 */
-#define SPLL_CON1_VAL 0x0020f300
-
-/* IPLL_CON1 */
-#define IPLL_CON1_VAL 0x00000080
-
-/* KPLL_CON1 */
-#define KPLL_CON1_VAL 0x200000
-
-/* CLK_SRC_ISP */
-#define CLK_SRC_ISP_VAL 0x33366000
-#define CLK_DIV_ISP0_VAL 0x13131300
-#define CLK_DIV_ISP1_VAL 0xbb110202
-
-
-/* CLK_FSYS */
-#define CLK_SRC_FSYS0_VAL 0x33033300
-#define CLK_DIV_FSYS0_VAL 0x0
-#define CLK_DIV_FSYS1_VAL 0x04f13c4f
-#define CLK_DIV_FSYS2_VAL 0x041d0000
-
-/* CLK_SRC_CPU */
-/* 0 = MOUTAPLL, 1 = SCLKMPLL */
-#define MUX_HPM_SEL 1
-#define MUX_CPU_SEL 0
-#define MUX_APLL_SEL 1
-
-#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
- | (MUX_CPU_SEL << 16) \
- | (MUX_APLL_SEL))
-
-/* CLK_SRC_CDREX */
-#define CLK_SRC_CDREX_VAL 0x00000011
-
-/* CLK_DIV_CDREX */
-#define CLK_DIV_CDREX0_VAL 0x30010100
-#define CLK_DIV_CDREX1_VAL 0x300
-
-#define CLK_DIV_CDREX_VAL 0x17010100
-
-/* CLK_DIV_CPU0_VAL */
-#define CLK_DIV_CPU0_VAL 0x01440020
-
-/* CLK_SRC_TOP */
-#define CLK_SRC_TOP0_VAL 0x12221222
-#define CLK_SRC_TOP1_VAL 0x00100200
-#define CLK_SRC_TOP2_VAL 0x11101000
-#define CLK_SRC_TOP3_VAL 0x11111111
-#define CLK_SRC_TOP4_VAL 0x11110111
-#define CLK_SRC_TOP5_VAL 0x11111101
-#define CLK_SRC_TOP6_VAL 0x11110111
-#define CLK_SRC_TOP7_VAL 0x00022200
-
-/* CLK_DIV_TOP */
-#define CLK_DIV_TOP0_VAL 0x23712311
-#define CLK_DIV_TOP1_VAL 0x13100B00
-#define CLK_DIV_TOP2_VAL 0x11101100
-
-/* PLL Lock Value Factor */
-#define PLL_LOCK_FACTOR 200
-#define PLL_X_LOCK_FACTOR 3000
-
-/* CLK_SRC_PERIC0 */
-#define SPDIF_SEL 1
-#define PWM_SEL 3
-#define UART4_SEL 3
-#define UART3_SEL 3
-#define UART2_SEL 3
-#define UART1_SEL 3
-#define UART0_SEL 3
-/* SRC_CLOCK = SCLK_RPLL */
-#define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \
- | (PWM_SEL << 24) \
- | (UART4_SEL << 20) \
- | (UART3_SEL << 16) \
- | (UART2_SEL << 12) \
- | (UART1_SEL << 8) \
- | (UART0_SEL << 4))
-
-/* CLK_SRC_PERIC1 */
-/* SRC_CLOCK = SCLK_EPLL */
-#define SPI0_SEL 6
-#define SPI1_SEL 6
-#define SPI2_SEL 6
-#define AUDIO0_SEL 6
-#define AUDIO1_SEL 6
-#define AUDIO2_SEL 6
-#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \
- | (SPI1_SEL << 24) \
- | (SPI0_SEL << 20) \
- | (AUDIO2_SEL << 16) \
- | (AUDIO2_SEL << 12) \
- | (AUDIO2_SEL << 8))
-
-/* CLK_DIV_PERIC0 */
-#define PWM_RATIO 8
-#define UART4_RATIO 9
-#define UART3_RATIO 9
-#define UART2_RATIO 9
-#define UART1_RATIO 9
-#define UART0_RATIO 9
-
-#define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \
- | (UART4_RATIO << 24) \
- | (UART3_RATIO << 20) \
- | (UART2_RATIO << 16) \
- | (UART1_RATIO << 12) \
- | (UART0_RATIO << 8))
-/* CLK_DIV_PERIC1 */
-#define SPI2_RATIO 0x1
-#define SPI1_RATIO 0x1
-#define SPI0_RATIO 0x1
-#define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \
- | (SPI1_RATIO << 24) \
- | (SPI0_RATIO << 20))
-
-/* CLK_DIV_PERIC2 */
-#define PCM2_RATIO 0x3
-#define PCM1_RATIO 0x3
-#define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \
- | (PCM1_RATIO << 16))
-
-/* CLK_DIV_PERIC3 */
-#define AUDIO2_RATIO 0x5
-#define AUDIO1_RATIO 0x5
-#define AUDIO0_RATIO 0x5
-#define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \
- | (AUDIO1_RATIO << 24) \
- | (AUDIO0_RATIO << 20))
-
-/* CLK_DIV_PERIC4 */
-#define SPI2_PRE_RATIO 0x2
-#define SPI1_PRE_RATIO 0x2
-#define SPI0_PRE_RATIO 0x2
-#define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \
- | (SPI1_PRE_RATIO << 16) \
- | (SPI0_PRE_RATIO << 8))
-
-/* CLK_SRC_DISP1_0 */
-#define CLK_SRC_DISP1_0_VAL 0x10666600
-#define CLK_DIV_DISP1_0_VAL 0x01050211
-
-#define APLL_FOUT (1 << 0)
-#define KPLL_FOUT (1 << 0)
-
-#define CLK_DIV_CPERI1_VAL 0x3f3f0000
-#endif
-
-struct mem_timings;
-
-/* Errors that we can encourter in low-level setup */
-enum {
- SETUP_ERR_OK,
- SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
- SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
-};
-
-/*
- * Memory variant specific initialization code for DDR3
- *
- * @param mem Memory timings for this memory type.
- * @param reset Reset DDR PHY during initialization.
- * @return 0 if ok, SETUP_ERR_... if there is a problem
- */
-int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset);
-
-/* Memory variant specific initialization code for LPDDR3 */
-void lpddr3_mem_ctrl_init(void);
-
-/*
- * Configure ZQ I/O interface
- *
- * @param mem Memory timings for this memory type.
- * @param phy0_con16 Register address for dmc_phy0->phy_con16
- * @param phy1_con16 Register address for dmc_phy1->phy_con16
- * @param phy0_con17 Register address for dmc_phy0->phy_con17
- * @param phy1_con17 Register address for dmc_phy1->phy_con17
- * @return 0 if ok, -1 on error
- */
-int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16,
- uint32_t *phy1_con16, uint32_t *phy0_con17,
- uint32_t *phy1_con17);
-/*
- * Send NOP and MRS/EMRS Direct commands
- *
- * @param mem Memory timings for this memory type.
- * @param directcmd Register address for dmc_phy->directcmd
- */
-void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd);
-
-/*
- * Send PALL Direct commands
- *
- * @param mem Memory timings for this memory type.
- * @param directcmd Register address for dmc_phy->directcmd
- */
-void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd);
-
-/*
- * Reset the DLL. This function is common between DDR3 and LPDDR2.
- * However, the reset value is different. So we are passing a flag
- * ddr_mode to distinguish between LPDDR2 and DDR3.
- *
- * @param phycontrol0 Register address for dmc_phy->phycontrol0
- * @param ddr_mode Type of DDR memory
- */
-void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode);
-#endif
+++ /dev/null
-/*
- * Lowlevel setup for EXYNOS5 based board
- *
- * Copyright (C) 2013 Samsung Electronics
- * Rajeshwari Shinde <rajeshwari.s@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <debug_uart.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/dmc.h>
-#include <asm/arch/power.h>
-#include <asm/arch/tzpc.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/system.h>
-#include <asm/armv7.h>
-#include "common_setup.h"
-#include "exynos5_setup.h"
-
-/* These are the things we can do during low-level init */
-enum {
- DO_WAKEUP = 1 << 0,
- DO_CLOCKS = 1 << 1,
- DO_MEM_RESET = 1 << 2,
- DO_UART = 1 << 3,
- DO_POWER = 1 << 4,
-};
-
-#ifdef CONFIG_EXYNOS5420
-/*
- * Power up secondary CPUs.
- */
-static void secondary_cpu_start(void)
-{
- v7_enable_smp(EXYNOS5420_INFORM_BASE);
- svc32_mode_en();
- branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
-}
-
-/*
- * This is the entry point of hotplug-in and
- * cluster switching.
- */
-static void low_power_start(void)
-{
- uint32_t val, reg_val;
-
- reg_val = readl(EXYNOS5420_SPARE_BASE);
- if (reg_val != CPU_RST_FLAG_VAL) {
- writel(0x0, CONFIG_LOWPOWER_FLAG);
- branch_bx(0x0);
- }
-
- reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4);
- if (reg_val != (uint32_t)&low_power_start) {
- /* Store jump address as low_power_start if not present */
- writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4);
- dsb();
- sev();
- }
-
- /* Set the CPU to SVC32 mode */
- svc32_mode_en();
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
- /* Read MIDR for Primary Part Number */
- mrc_midr(val);
- val = (val >> 4);
- val &= 0xf;
-
- if (val == 0xf) {
- configure_l2_ctlr();
- configure_l2_actlr();
- v7_enable_l2_hazard_detect();
- }
-#endif
-
- /* Invalidate L1 & TLB */
- val = 0x0;
- mcr_tlb(val);
- mcr_icache(val);
-
- /* Disable MMU stuff and caches */
- mrc_sctlr(val);
-
- val &= ~((0x2 << 12) | 0x7);
- val |= ((0x1 << 12) | (0x8 << 8) | 0x2);
- mcr_sctlr(val);
-
- /* CPU state is hotplug or reset */
- secondary_cpu_start();
-
- /* Core should not enter into WFI here */
- wfi();
-}
-
-/*
- * Pointer to this function is stored in iRam which is used
- * for jump and power down of a specific core.
- */
-static void power_down_core(void)
-{
- uint32_t tmp, core_id, core_config;
-
- /* Get the unique core id */
- /*
- * Multiprocessor Affinity Register
- * [11:8] Cluster ID
- * [1:0] CPU ID
- */
- mrc_mpafr(core_id);
- tmp = core_id & 0x3;
- core_id = (core_id >> 6) & ~3;
- core_id |= tmp;
- core_id &= 0x3f;
-
- /* Set the status of the core to low */
- core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
- core_config += EXYNOS5420_CPU_CONFIG_BASE;
- writel(0x0, core_config);
-
- /* Core enter WFI */
- wfi();
-}
-
-/*
- * Configurations for secondary cores are inapt at this stage.
- * Reconfigure secondary cores. Shutdown and change the status
- * of all cores except the primary core.
- */
-static void secondary_cores_configure(void)
-{
- /* Clear secondary boot iRAM base */
- writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
-
- /* set lowpower flag and address */
- writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);
- writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR);
- writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE);
- /* Store jump address for power down */
- writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
-
- /* Need all core power down check */
- dsb();
- sev();
-}
-
-extern void relocate_wait_code(void);
-#endif
-
-int do_lowlevel_init(void)
-{
- uint32_t reset_status;
- int actions = 0;
-
- arch_cpu_init();
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
- /*
- * Init L2 cache parameters here for use by boot and resume
- *
- * These are here instead of in v7_outer_cache_enable() so that the
- * L2 cache settings get properly set even at resume time or if we're
- * running U-Boot with the cache off. The kernel still needs us to
- * set these for it.
- */
- configure_l2_ctlr();
- configure_l2_actlr();
- dsb();
- isb();
-#endif
-
-#ifdef CONFIG_EXYNOS5420
- relocate_wait_code();
-
- /* Reconfigure secondary cores */
- secondary_cores_configure();
-#endif
-
- reset_status = get_reset_status();
-
- switch (reset_status) {
- case S5P_CHECK_SLEEP:
- actions = DO_CLOCKS | DO_WAKEUP;
- break;
- case S5P_CHECK_DIDLE:
- case S5P_CHECK_LPA:
- actions = DO_WAKEUP;
- break;
- default:
- /* This is a normal boot (not a wake from sleep) */
- actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
- }
-
- if (actions & DO_POWER)
- set_ps_hold_ctrl();
-
- if (actions & DO_CLOCKS) {
- system_clock_init();
-#ifdef CONFIG_DEBUG_UART
- exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
- debug_uart_init();
-#endif
- mem_ctrl_init(actions & DO_MEM_RESET);
- tzpc_init();
- }
-
- return actions & DO_WAKEUP;
-}
+++ /dev/null
-/*
- * Copyright (c) 2012 Samsung Electronics.
- * Abhilash Kesavan <a.kesavan@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <fdtdec.h>
-#include <asm/gpio.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/sromc.h>
-
-static void exynos5_uart_config(int peripheral)
-{
- int i, start, count;
-
- switch (peripheral) {
- case PERIPH_ID_UART0:
- start = EXYNOS5_GPIO_A00;
- count = 4;
- break;
- case PERIPH_ID_UART1:
- start = EXYNOS5_GPIO_D00;
- count = 4;
- break;
- case PERIPH_ID_UART2:
- start = EXYNOS5_GPIO_A10;
- count = 4;
- break;
- case PERIPH_ID_UART3:
- start = EXYNOS5_GPIO_A14;
- count = 2;
- break;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return;
- }
- for (i = start; i < start + count; i++) {
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
- }
-}
-
-static void exynos5420_uart_config(int peripheral)
-{
- int i, start, count;
-
- switch (peripheral) {
- case PERIPH_ID_UART0:
- start = EXYNOS5420_GPIO_A00;
- count = 4;
- break;
- case PERIPH_ID_UART1:
- start = EXYNOS5420_GPIO_A04;
- count = 4;
- break;
- case PERIPH_ID_UART2:
- start = EXYNOS5420_GPIO_A10;
- count = 4;
- break;
- case PERIPH_ID_UART3:
- start = EXYNOS5420_GPIO_A14;
- count = 2;
- break;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return;
- }
-
- for (i = start; i < start + count; i++) {
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
- }
-}
-
-static int exynos5_mmc_config(int peripheral, int flags)
-{
- int i, start, start_ext, gpio_func = 0;
-
- switch (peripheral) {
- case PERIPH_ID_SDMMC0:
- start = EXYNOS5_GPIO_C00;
- start_ext = EXYNOS5_GPIO_C10;
- gpio_func = S5P_GPIO_FUNC(0x2);
- break;
- case PERIPH_ID_SDMMC1:
- start = EXYNOS5_GPIO_C20;
- start_ext = 0;
- break;
- case PERIPH_ID_SDMMC2:
- start = EXYNOS5_GPIO_C30;
- start_ext = EXYNOS5_GPIO_C43;
- gpio_func = S5P_GPIO_FUNC(0x3);
- break;
- case PERIPH_ID_SDMMC3:
- start = EXYNOS5_GPIO_C40;
- start_ext = 0;
- break;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return -1;
- }
- if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
- debug("SDMMC device %d does not support 8bit mode",
- peripheral);
- return -1;
- }
- if (flags & PINMUX_FLAG_8BIT_MODE) {
- for (i = start_ext; i <= (start_ext + 3); i++) {
- gpio_cfg_pin(i, gpio_func);
- gpio_set_pull(i, S5P_GPIO_PULL_UP);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
- }
- for (i = start; i < (start + 2); i++) {
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
- for (i = (start + 3); i <= (start + 6); i++) {
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
- gpio_set_pull(i, S5P_GPIO_PULL_UP);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
-
- return 0;
-}
-
-static int exynos5420_mmc_config(int peripheral, int flags)
-{
- int i, start = 0, start_ext = 0;
-
- switch (peripheral) {
- case PERIPH_ID_SDMMC0:
- start = EXYNOS5420_GPIO_C00;
- start_ext = EXYNOS5420_GPIO_C30;
- break;
- case PERIPH_ID_SDMMC1:
- start = EXYNOS5420_GPIO_C10;
- start_ext = EXYNOS5420_GPIO_D14;
- break;
- case PERIPH_ID_SDMMC2:
- start = EXYNOS5420_GPIO_C20;
- start_ext = 0;
- break;
- default:
- start = 0;
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return -1;
- }
-
- if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
- debug("SDMMC device %d does not support 8bit mode",
- peripheral);
- return -1;
- }
-
- if (flags & PINMUX_FLAG_8BIT_MODE) {
- for (i = start_ext; i <= (start_ext + 3); i++) {
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
- gpio_set_pull(i, S5P_GPIO_PULL_UP);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
- }
-
- for (i = start; i < (start + 3); i++) {
- /*
- * MMC0 is intended to be used for eMMC. The
- * card detect pin is used as a VDDEN signal to
- * power on the eMMC. The 5420 iROM makes
- * this same assumption.
- */
- if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) {
-#ifndef CONFIG_SPL_BUILD
- gpio_request(i, "sdmmc0_vdden");
-#endif
- gpio_set_value(i, 1);
- gpio_cfg_pin(i, S5P_GPIO_OUTPUT);
- } else {
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
- }
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
-
- for (i = (start + 3); i <= (start + 6); i++) {
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
- gpio_set_pull(i, S5P_GPIO_PULL_UP);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
-
- return 0;
-}
-
-static void exynos5_sromc_config(int flags)
-{
- int i;
-
- /*
- * SROM:CS1 and EBI
- *
- * GPY0[0] SROM_CSn[0]
- * GPY0[1] SROM_CSn[1](2)
- * GPY0[2] SROM_CSn[2]
- * GPY0[3] SROM_CSn[3]
- * GPY0[4] EBI_OEn(2)
- * GPY0[5] EBI_EEn(2)
- *
- * GPY1[0] EBI_BEn[0](2)
- * GPY1[1] EBI_BEn[1](2)
- * GPY1[2] SROM_WAIT(2)
- * GPY1[3] EBI_DATA_RDn(2)
- */
- gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
- S5P_GPIO_FUNC(2));
- gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2));
- gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2));
-
- for (i = 0; i < 4; i++)
- gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2));
-
- /*
- * EBI: 8 Addrss Lines
- *
- * GPY3[0] EBI_ADDR[0](2)
- * GPY3[1] EBI_ADDR[1](2)
- * GPY3[2] EBI_ADDR[2](2)
- * GPY3[3] EBI_ADDR[3](2)
- * GPY3[4] EBI_ADDR[4](2)
- * GPY3[5] EBI_ADDR[5](2)
- * GPY3[6] EBI_ADDR[6](2)
- * GPY3[7] EBI_ADDR[7](2)
- *
- * EBI: 16 Data Lines
- *
- * GPY5[0] EBI_DATA[0](2)
- * GPY5[1] EBI_DATA[1](2)
- * GPY5[2] EBI_DATA[2](2)
- * GPY5[3] EBI_DATA[3](2)
- * GPY5[4] EBI_DATA[4](2)
- * GPY5[5] EBI_DATA[5](2)
- * GPY5[6] EBI_DATA[6](2)
- * GPY5[7] EBI_DATA[7](2)
- *
- * GPY6[0] EBI_DATA[8](2)
- * GPY6[1] EBI_DATA[9](2)
- * GPY6[2] EBI_DATA[10](2)
- * GPY6[3] EBI_DATA[11](2)
- * GPY6[4] EBI_DATA[12](2)
- * GPY6[5] EBI_DATA[13](2)
- * GPY6[6] EBI_DATA[14](2)
- * GPY6[7] EBI_DATA[15](2)
- */
- for (i = 0; i < 8; i++) {
- gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2));
- gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP);
-
- gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2));
- gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP);
-
- gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2));
- gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP);
- }
-}
-
-static void exynos5_i2c_config(int peripheral, int flags)
-{
- int func01, func23;
-
- /* High-Speed I2C */
- if (flags & PINMUX_FLAG_HS_MODE) {
- func01 = 4;
- func23 = 4;
- } else {
- func01 = 2;
- func23 = 3;
- }
-
- switch (peripheral) {
- case PERIPH_ID_I2C0:
- gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(func01));
- gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(func01));
- break;
- case PERIPH_ID_I2C1:
- gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(func01));
- gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(func01));
- break;
- case PERIPH_ID_I2C2:
- gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(func23));
- gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(func23));
- break;
- case PERIPH_ID_I2C3:
- gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(func23));
- gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(func23));
- break;
- case PERIPH_ID_I2C4:
- gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C5:
- gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C6:
- gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4));
- gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4));
- break;
- case PERIPH_ID_I2C7:
- gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3));
- break;
- }
-}
-
-static void exynos5420_i2c_config(int peripheral)
-{
- switch (peripheral) {
- case PERIPH_ID_I2C0:
- gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C1:
- gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C2:
- gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C3:
- gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C4:
- gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C5:
- gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C6:
- gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4));
- gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4));
- break;
- case PERIPH_ID_I2C7:
- gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C8:
- gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C9:
- gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C10:
- gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2));
- break;
- }
-}
-
-static void exynos5_i2s_config(int peripheral)
-{
- int i;
-
- switch (peripheral) {
- case PERIPH_ID_I2S0:
- for (i = 0; i < 5; i++)
- gpio_cfg_pin(EXYNOS5_GPIO_Z0 + i, S5P_GPIO_FUNC(0x02));
- break;
- case PERIPH_ID_I2S1:
- for (i = 0; i < 5; i++)
- gpio_cfg_pin(EXYNOS5_GPIO_B00 + i, S5P_GPIO_FUNC(0x02));
- break;
- }
-}
-
-void exynos5_spi_config(int peripheral)
-{
- int cfg = 0, pin = 0, i;
-
- switch (peripheral) {
- case PERIPH_ID_SPI0:
- cfg = S5P_GPIO_FUNC(0x2);
- pin = EXYNOS5_GPIO_A20;
- break;
- case PERIPH_ID_SPI1:
- cfg = S5P_GPIO_FUNC(0x2);
- pin = EXYNOS5_GPIO_A24;
- break;
- case PERIPH_ID_SPI2:
- cfg = S5P_GPIO_FUNC(0x5);
- pin = EXYNOS5_GPIO_B11;
- break;
- case PERIPH_ID_SPI3:
- cfg = S5P_GPIO_FUNC(0x2);
- pin = EXYNOS5_GPIO_F10;
- break;
- case PERIPH_ID_SPI4:
- for (i = 0; i < 2; i++) {
- gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4));
- gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4));
- }
- break;
- }
- if (peripheral != PERIPH_ID_SPI4) {
- for (i = pin; i < pin + 4; i++)
- gpio_cfg_pin(i, cfg);
- }
-}
-
-void exynos5420_spi_config(int peripheral)
-{
- int cfg, pin, i;
-
- switch (peripheral) {
- case PERIPH_ID_SPI0:
- pin = EXYNOS5420_GPIO_A20;
- cfg = S5P_GPIO_FUNC(0x2);
- break;
- case PERIPH_ID_SPI1:
- pin = EXYNOS5420_GPIO_A24;
- cfg = S5P_GPIO_FUNC(0x2);
- break;
- case PERIPH_ID_SPI2:
- pin = EXYNOS5420_GPIO_B11;
- cfg = S5P_GPIO_FUNC(0x5);
- break;
- case PERIPH_ID_SPI3:
- pin = EXYNOS5420_GPIO_F10;
- cfg = S5P_GPIO_FUNC(0x2);
- break;
- case PERIPH_ID_SPI4:
- cfg = 0;
- pin = 0;
- break;
- default:
- cfg = 0;
- pin = 0;
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return;
- }
-
- if (peripheral != PERIPH_ID_SPI4) {
- for (i = pin; i < pin + 4; i++)
- gpio_cfg_pin(i, cfg);
- } else {
- for (i = 0; i < 2; i++) {
- gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i,
- S5P_GPIO_FUNC(0x4));
- gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i,
- S5P_GPIO_FUNC(0x4));
- }
- }
-}
-
-static int exynos5_pinmux_config(int peripheral, int flags)
-{
- switch (peripheral) {
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- exynos5_uart_config(peripheral);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- case PERIPH_ID_SDMMC2:
- case PERIPH_ID_SDMMC3:
- return exynos5_mmc_config(peripheral, flags);
- case PERIPH_ID_SROMC:
- exynos5_sromc_config(flags);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
- case PERIPH_ID_I2C5:
- case PERIPH_ID_I2C6:
- case PERIPH_ID_I2C7:
- exynos5_i2c_config(peripheral, flags);
- break;
- case PERIPH_ID_I2S0:
- case PERIPH_ID_I2S1:
- exynos5_i2s_config(peripheral);
- break;
- case PERIPH_ID_SPI0:
- case PERIPH_ID_SPI1:
- case PERIPH_ID_SPI2:
- case PERIPH_ID_SPI3:
- case PERIPH_ID_SPI4:
- exynos5_spi_config(peripheral);
- break;
- case PERIPH_ID_DPHPD:
- /* Set Hotplug detect for DP */
- gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
-
- /*
- * Hotplug detect should have an external pullup; disable the
- * internal pulldown so they don't fight.
- */
- gpio_set_pull(EXYNOS5_GPIO_X07, S5P_GPIO_PULL_NONE);
- break;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return -1;
- }
-
- return 0;
-}
-
-static int exynos5420_pinmux_config(int peripheral, int flags)
-{
- switch (peripheral) {
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- exynos5420_uart_config(peripheral);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- case PERIPH_ID_SDMMC2:
- case PERIPH_ID_SDMMC3:
- return exynos5420_mmc_config(peripheral, flags);
- case PERIPH_ID_SPI0:
- case PERIPH_ID_SPI1:
- case PERIPH_ID_SPI2:
- case PERIPH_ID_SPI3:
- case PERIPH_ID_SPI4:
- exynos5420_spi_config(peripheral);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
- case PERIPH_ID_I2C5:
- case PERIPH_ID_I2C6:
- case PERIPH_ID_I2C7:
- case PERIPH_ID_I2C8:
- case PERIPH_ID_I2C9:
- case PERIPH_ID_I2C10:
- exynos5420_i2c_config(peripheral);
- break;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return -1;
- }
-
- return 0;
-}
-
-static void exynos4_i2c_config(int peripheral, int flags)
-{
- switch (peripheral) {
- case PERIPH_ID_I2C0:
- gpio_cfg_pin(EXYNOS4_GPIO_D10, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS4_GPIO_D11, S5P_GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C1:
- gpio_cfg_pin(EXYNOS4_GPIO_D12, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS4_GPIO_D13, S5P_GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C2:
- gpio_cfg_pin(EXYNOS4_GPIO_A06, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4_GPIO_A07, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C3:
- gpio_cfg_pin(EXYNOS4_GPIO_A12, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4_GPIO_A13, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C4:
- gpio_cfg_pin(EXYNOS4_GPIO_B2, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4_GPIO_B3, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C5:
- gpio_cfg_pin(EXYNOS4_GPIO_B6, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4_GPIO_B7, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C6:
- gpio_cfg_pin(EXYNOS4_GPIO_C13, S5P_GPIO_FUNC(0x4));
- gpio_cfg_pin(EXYNOS4_GPIO_C14, S5P_GPIO_FUNC(0x4));
- break;
- case PERIPH_ID_I2C7:
- gpio_cfg_pin(EXYNOS4_GPIO_D02, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4_GPIO_D03, S5P_GPIO_FUNC(0x3));
- break;
- }
-}
-
-static int exynos4_mmc_config(int peripheral, int flags)
-{
- int i, start = 0, start_ext = 0;
- unsigned int func, ext_func;
-
- switch (peripheral) {
- case PERIPH_ID_SDMMC0:
- start = EXYNOS4_GPIO_K00;
- start_ext = EXYNOS4_GPIO_K13;
- func = S5P_GPIO_FUNC(0x2);
- ext_func = S5P_GPIO_FUNC(0x3);
- break;
- case PERIPH_ID_SDMMC2:
- start = EXYNOS4_GPIO_K20;
- start_ext = EXYNOS4_GPIO_K33;
- func = S5P_GPIO_FUNC(0x2);
- ext_func = S5P_GPIO_FUNC(0x3);
- break;
- case PERIPH_ID_SDMMC4:
- start = EXYNOS4_GPIO_K00;
- start_ext = EXYNOS4_GPIO_K13;
- func = S5P_GPIO_FUNC(0x3);
- ext_func = S5P_GPIO_FUNC(0x4);
- break;
- default:
- return -1;
- }
- for (i = start; i < (start + 7); i++) {
- if (i == (start + 2))
- continue;
- gpio_cfg_pin(i, func);
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
- /* SDMMC2 do not use 8bit mode at exynos4 */
- if (flags & PINMUX_FLAG_8BIT_MODE) {
- for (i = start_ext; i < (start_ext + 4); i++) {
- gpio_cfg_pin(i, ext_func);
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
- }
-
- return 0;
-}
-
-static void exynos4_uart_config(int peripheral)
-{
- int i, start, count;
-
- switch (peripheral) {
- case PERIPH_ID_UART0:
- start = EXYNOS4_GPIO_A00;
- count = 4;
- break;
- case PERIPH_ID_UART1:
- start = EXYNOS4_GPIO_A04;
- count = 4;
- break;
- case PERIPH_ID_UART2:
- start = EXYNOS4_GPIO_A10;
- count = 4;
- break;
- case PERIPH_ID_UART3:
- start = EXYNOS4_GPIO_A14;
- count = 2;
- break;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return;
- }
- for (i = start; i < (start + count); i++) {
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
- }
-}
-
-static void exynos4x12_i2c_config(int peripheral, int flags)
-{
- switch (peripheral) {
- case PERIPH_ID_I2C0:
- gpio_cfg_pin(EXYNOS4X12_GPIO_D10, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS4X12_GPIO_D11, S5P_GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C1:
- gpio_cfg_pin(EXYNOS4X12_GPIO_D12, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS4X12_GPIO_D13, S5P_GPIO_FUNC(0x2));
- break;
- case PERIPH_ID_I2C2:
- gpio_cfg_pin(EXYNOS4X12_GPIO_A06, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4X12_GPIO_A07, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C3:
- gpio_cfg_pin(EXYNOS4X12_GPIO_A12, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4X12_GPIO_A13, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C4:
- gpio_cfg_pin(EXYNOS4X12_GPIO_B2, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4X12_GPIO_B3, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C5:
- gpio_cfg_pin(EXYNOS4X12_GPIO_B6, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4X12_GPIO_B7, S5P_GPIO_FUNC(0x3));
- break;
- case PERIPH_ID_I2C6:
- gpio_cfg_pin(EXYNOS4X12_GPIO_C13, S5P_GPIO_FUNC(0x4));
- gpio_cfg_pin(EXYNOS4X12_GPIO_C14, S5P_GPIO_FUNC(0x4));
- break;
- case PERIPH_ID_I2C7:
- gpio_cfg_pin(EXYNOS4X12_GPIO_D02, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS4X12_GPIO_D03, S5P_GPIO_FUNC(0x3));
- break;
- }
-}
-
-static int exynos4x12_mmc_config(int peripheral, int flags)
-{
- int i, start = 0, start_ext = 0;
- unsigned int func, ext_func;
-
- switch (peripheral) {
- case PERIPH_ID_SDMMC0:
- start = EXYNOS4X12_GPIO_K00;
- start_ext = EXYNOS4X12_GPIO_K13;
- func = S5P_GPIO_FUNC(0x2);
- ext_func = S5P_GPIO_FUNC(0x3);
- break;
- case PERIPH_ID_SDMMC2:
- start = EXYNOS4X12_GPIO_K20;
- start_ext = EXYNOS4X12_GPIO_K33;
- func = S5P_GPIO_FUNC(0x2);
- ext_func = S5P_GPIO_FUNC(0x3);
- break;
- case PERIPH_ID_SDMMC4:
- start = EXYNOS4X12_GPIO_K00;
- start_ext = EXYNOS4X12_GPIO_K13;
- func = S5P_GPIO_FUNC(0x3);
- ext_func = S5P_GPIO_FUNC(0x4);
- break;
- default:
- return -1;
- }
- for (i = start; i < (start + 7); i++) {
- if (i == (start + 2))
- continue;
- gpio_cfg_pin(i, func);
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
- if (flags & PINMUX_FLAG_8BIT_MODE) {
- for (i = start_ext; i < (start_ext + 4); i++) {
- gpio_cfg_pin(i, ext_func);
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_set_drv(i, S5P_GPIO_DRV_4X);
- }
- }
-
- return 0;
-}
-
-static void exynos4x12_uart_config(int peripheral)
-{
- int i, start, count;
-
- switch (peripheral) {
- case PERIPH_ID_UART0:
- start = EXYNOS4X12_GPIO_A00;
- count = 4;
- break;
- case PERIPH_ID_UART1:
- start = EXYNOS4X12_GPIO_A04;
- count = 4;
- break;
- case PERIPH_ID_UART2:
- start = EXYNOS4X12_GPIO_A10;
- count = 4;
- break;
- case PERIPH_ID_UART3:
- start = EXYNOS4X12_GPIO_A14;
- count = 2;
- break;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return;
- }
- for (i = start; i < (start + count); i++) {
- gpio_set_pull(i, S5P_GPIO_PULL_NONE);
- gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
- }
-}
-
-static int exynos4_pinmux_config(int peripheral, int flags)
-{
- switch (peripheral) {
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- exynos4_uart_config(peripheral);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
- case PERIPH_ID_I2C5:
- case PERIPH_ID_I2C6:
- case PERIPH_ID_I2C7:
- exynos4_i2c_config(peripheral, flags);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC2:
- case PERIPH_ID_SDMMC4:
- return exynos4_mmc_config(peripheral, flags);
- case PERIPH_ID_SDMMC1:
- case PERIPH_ID_SDMMC3:
- debug("SDMMC device %d not implemented\n", peripheral);
- return -1;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return -1;
- }
-
- return 0;
-}
-
-static int exynos4x12_pinmux_config(int peripheral, int flags)
-{
- switch (peripheral) {
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- exynos4x12_uart_config(peripheral);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
- case PERIPH_ID_I2C5:
- case PERIPH_ID_I2C6:
- case PERIPH_ID_I2C7:
- exynos4x12_i2c_config(peripheral, flags);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC2:
- case PERIPH_ID_SDMMC4:
- return exynos4x12_mmc_config(peripheral, flags);
- case PERIPH_ID_SDMMC1:
- case PERIPH_ID_SDMMC3:
- debug("SDMMC device %d not implemented\n", peripheral);
- return -1;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return -1;
- }
-
- return 0;
-}
-
-int exynos_pinmux_config(int peripheral, int flags)
-{
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_pinmux_config(peripheral, flags);
- else if (proid_is_exynos5250())
- return exynos5_pinmux_config(peripheral, flags);
- } else if (cpu_is_exynos4()) {
- if (proid_is_exynos4412())
- return exynos4x12_pinmux_config(peripheral, flags);
- else
- return exynos4_pinmux_config(peripheral, flags);
- }
-
- debug("pinmux functionality not supported\n");
-
- return -1;
-}
-
-#ifdef CONFIG_OF_CONTROL
-static int exynos4_pinmux_decode_periph_id(const void *blob, int node)
-{
- int err;
- u32 cell[3];
-
- err = fdtdec_get_int_array(blob, node, "interrupts", cell,
- ARRAY_SIZE(cell));
- if (err) {
- debug(" invalid peripheral id\n");
- return PERIPH_ID_NONE;
- }
-
- return cell[1];
-}
-
-static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
-{
- int err;
- u32 cell[3];
-
- err = fdtdec_get_int_array(blob, node, "interrupts", cell,
- ARRAY_SIZE(cell));
- if (err)
- return PERIPH_ID_NONE;
-
- return cell[1];
-}
-
-int pinmux_decode_periph_id(const void *blob, int node)
-{
- if (cpu_is_exynos5())
- return exynos5_pinmux_decode_periph_id(blob, node);
- else if (cpu_is_exynos4())
- return exynos4_pinmux_decode_periph_id(blob, node);
-
- return PERIPH_ID_NONE;
-}
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- * Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/power.h>
-
-static void exynos4_mipi_phy_control(unsigned int dev_index,
- unsigned int enable)
-{
- struct exynos4_power *pmu =
- (struct exynos4_power *)samsung_get_base_power();
- unsigned int addr, cfg = 0;
-
- if (dev_index == 0)
- addr = (unsigned int)&pmu->mipi_phy0_control;
- else
- addr = (unsigned int)&pmu->mipi_phy1_control;
-
-
- cfg = readl(addr);
- if (enable)
- cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
- else
- cfg &= ~(EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
-
- writel(cfg, addr);
-}
-
-void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
-{
- if (cpu_is_exynos4())
- exynos4_mipi_phy_control(dev_index, enable);
-}
-
-void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
-{
- struct exynos5_power *power =
- (struct exynos5_power *)samsung_get_base_power();
-
- if (enable) {
- /* Enabling USBHOST_PHY */
- setbits_le32(&power->usbhost_phy_control,
- POWER_USB_HOST_PHY_CTRL_EN);
- } else {
- /* Disabling USBHOST_PHY */
- clrbits_le32(&power->usbhost_phy_control,
- POWER_USB_HOST_PHY_CTRL_EN);
- }
-}
-
-void exynos4412_set_usbhost_phy_ctrl(unsigned int enable)
-{
- struct exynos4412_power *power =
- (struct exynos4412_power *)samsung_get_base_power();
-
- if (enable) {
- /* Enabling USBHOST_PHY */
- setbits_le32(&power->usbhost_phy_control,
- POWER_USB_HOST_PHY_CTRL_EN);
- setbits_le32(&power->hsic1_phy_control,
- POWER_USB_HOST_PHY_CTRL_EN);
- setbits_le32(&power->hsic2_phy_control,
- POWER_USB_HOST_PHY_CTRL_EN);
- } else {
- /* Disabling USBHOST_PHY */
- clrbits_le32(&power->usbhost_phy_control,
- POWER_USB_HOST_PHY_CTRL_EN);
- clrbits_le32(&power->hsic1_phy_control,
- POWER_USB_HOST_PHY_CTRL_EN);
- clrbits_le32(&power->hsic2_phy_control,
- POWER_USB_HOST_PHY_CTRL_EN);
- }
-}
-
-void set_usbhost_phy_ctrl(unsigned int enable)
-{
- if (cpu_is_exynos5())
- exynos5_set_usbhost_phy_ctrl(enable);
- else if (cpu_is_exynos4())
- if (proid_is_exynos4412())
- exynos4412_set_usbhost_phy_ctrl(enable);
-}
-
-static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
-{
- struct exynos5_power *power =
- (struct exynos5_power *)samsung_get_base_power();
-
- if (enable) {
- /* Enabling USBDRD_PHY */
- setbits_le32(&power->usbdrd_phy_control,
- POWER_USB_DRD_PHY_CTRL_EN);
- } else {
- /* Disabling USBDRD_PHY */
- clrbits_le32(&power->usbdrd_phy_control,
- POWER_USB_DRD_PHY_CTRL_EN);
- }
-}
-
-static void exynos5420_set_usbdev_phy_ctrl(unsigned int enable)
-{
- struct exynos5420_power *power =
- (struct exynos5420_power *)samsung_get_base_power();
-
- if (enable) {
- /* Enabling USBDEV_PHY */
- setbits_le32(&power->usbdev_phy_control,
- POWER_USB_DRD_PHY_CTRL_EN);
- setbits_le32(&power->usbdev1_phy_control,
- POWER_USB_DRD_PHY_CTRL_EN);
- } else {
- /* Disabling USBDEV_PHY */
- clrbits_le32(&power->usbdev_phy_control,
- POWER_USB_DRD_PHY_CTRL_EN);
- clrbits_le32(&power->usbdev1_phy_control,
- POWER_USB_DRD_PHY_CTRL_EN);
- }
-}
-
-void set_usbdrd_phy_ctrl(unsigned int enable)
-{
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- exynos5420_set_usbdev_phy_ctrl(enable);
- else
- exynos5_set_usbdrd_phy_ctrl(enable);
- }
-}
-
-static void exynos5_dp_phy_control(unsigned int enable)
-{
- unsigned int cfg;
- struct exynos5_power *power =
- (struct exynos5_power *)samsung_get_base_power();
-
- cfg = readl(&power->dptx_phy_control);
- if (enable)
- cfg |= EXYNOS_DP_PHY_ENABLE;
- else
- cfg &= ~EXYNOS_DP_PHY_ENABLE;
-
- writel(cfg, &power->dptx_phy_control);
-}
-
-void set_dp_phy_ctrl(unsigned int enable)
-{
- if (cpu_is_exynos5())
- exynos5_dp_phy_control(enable);
-}
-
-static void exynos5_set_ps_hold_ctrl(void)
-{
- struct exynos5_power *power =
- (struct exynos5_power *)samsung_get_base_power();
-
- /* Set PS-Hold high */
- setbits_le32(&power->ps_hold_control,
- EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
-}
-
-/*
- * Set ps_hold data driving value high
- * This enables the machine to stay powered on
- * after the initial power-on condition goes away
- * (e.g. power button).
- */
-void set_ps_hold_ctrl(void)
-{
- if (cpu_is_exynos5())
- exynos5_set_ps_hold_ctrl();
-}
-
-
-static void exynos5_set_xclkout(void)
-{
- struct exynos5_power *power =
- (struct exynos5_power *)samsung_get_base_power();
-
- /* use xxti for xclk out */
- clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
- PMU_DEBUG_XXTI);
-}
-
-void set_xclkout(void)
-{
- if (cpu_is_exynos5())
- exynos5_set_xclkout();
-}
-
-/* Enables hardware tripping to power off the system when TMU fails */
-void set_hw_thermal_trip(void)
-{
- if (cpu_is_exynos5()) {
- struct exynos5_power *power =
- (struct exynos5_power *)samsung_get_base_power();
-
- /* PS_HOLD_CONTROL register ENABLE_HW_TRIP bit*/
- setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP);
- }
-}
-
-static uint32_t exynos5_get_reset_status(void)
-{
- struct exynos5_power *power =
- (struct exynos5_power *)samsung_get_base_power();
-
- return power->inform1;
-}
-
-static uint32_t exynos4_get_reset_status(void)
-{
- struct exynos4_power *power =
- (struct exynos4_power *)samsung_get_base_power();
-
- return power->inform1;
-}
-
-uint32_t get_reset_status(void)
-{
- if (cpu_is_exynos5())
- return exynos5_get_reset_status();
- else
- return exynos4_get_reset_status();
-}
-
-static void exynos5_power_exit_wakeup(void)
-{
- struct exynos5_power *power =
- (struct exynos5_power *)samsung_get_base_power();
- typedef void (*resume_func)(void);
-
- ((resume_func)power->inform0)();
-}
-
-static void exynos4_power_exit_wakeup(void)
-{
- struct exynos4_power *power =
- (struct exynos4_power *)samsung_get_base_power();
- typedef void (*resume_func)(void);
-
- ((resume_func)power->inform0)();
-}
-
-void power_exit_wakeup(void)
-{
- if (cpu_is_exynos5())
- exynos5_power_exit_wakeup();
- else
- exynos4_power_exit_wakeup();
-}
-
-unsigned int get_boot_mode(void)
-{
- unsigned int om_pin = samsung_get_base_power();
-
- return readl(om_pin) & OM_PIN_MASK;
-}
+++ /dev/null
-/*
- * Copyright (C) 2013 Samsung Electronics
- * Akshay Saraswat <akshay.s@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/arch/cpu.h>
-
- .globl relocate_wait_code
-relocate_wait_code:
- adr r0, code_base @ r0: source address (start)
- adr r1, code_end @ r1: source address (end)
- ldr r2, =0x02073000 @ r2: target address
-1:
- ldmia r0!, {r3-r6}
- stmia r2!, {r3-r6}
- cmp r0, r1
- blt 1b
- b code_end
- .ltorg
-/*
- * Secondary core waits here until Primary wake it up.
- * Below code is copied to CONFIG_EXYNOS_RELOCATE_CODE_BASE.
- * This is a workaround code which is supposed to act as a
- * substitute/supplement to the iROM code.
- *
- * This workaround code is relocated to the address 0x02073000
- * because that comes out to be the last 4KB of the iRAM
- * (Base Address - 0x02020000, Limit Address - 0x020740000).
- *
- * U-boot and kernel are aware of this code and flags by the simple
- * fact that we are implementing a workaround in the last 4KB
- * of the iRAM and we have already defined these flag and address
- * values in both kernel and U-boot for our use.
- */
-code_base:
- b 1f
-/*
- * These addresses are being used as flags in u-boot and kernel.
- *
- * Jump address for resume and flag to check for resume/reset:
- * Resume address - 0x2073008
- * Resume flag - 0x207300C
- *
- * Jump address for cluster switching:
- * Switch address - 0x2073018
- *
- * Jump address for core hotplug:
- * Hotplug address - 0x207301C
- *
- * Jump address for C2 state (Reserved for future not being used right now):
- * C2 address - 0x2073024
- *
- * Managed per core status for the active cluster:
- * CPU0 state - 0x2073028
- * CPU1 state - 0x207302C
- * CPU2 state - 0x2073030
- * CPU3 state - 0x2073034
- *
- * Managed per core GIC status for the active cluster:
- * CPU0 gic state - 0x2073038
- * CPU1 gic state - 0x207303C
- * CPU2 gic state - 0x2073040
- * CPU3 gic state - 0x2073044
- *
- * Logic of the code:
- * Step-1: Read current CPU status.
- * Step-2: If it's a resume then continue, else jump to step 4.
- * Step-3: Clear inform1 PMU register and jump to inform0 value.
- * Step-4: If it's a switch, C2 or reset, get the hotplug address.
- * Step-5: If address is not available, enter WFE.
- * Step-6: If address is available, jump to that address.
- */
- nop @ for backward compatibility
- .word 0x0 @ REG0: RESUME_ADDR
- .word 0x0 @ REG1: RESUME_FLAG
- .word 0x0 @ REG2
- .word 0x0 @ REG3
-_switch_addr:
- .word 0x0 @ REG4: SWITCH_ADDR
-_hotplug_addr:
- .word 0x0 @ REG5: CPU1_BOOT_REG
- .word 0x0 @ REG6
-_c2_addr:
- .word 0x0 @ REG7: REG_C2_ADDR
-_cpu_state:
- .word 0x1 @ CPU0_STATE : RESET
- .word 0x2 @ CPU1_STATE : SECONDARY RESET
- .word 0x2 @ CPU2_STATE : SECONDARY RESET
- .word 0x2 @ CPU3_STATE : SECONDARY RESET
-_gic_state:
- .word 0x0 @ CPU0 - GICD_IGROUPR0
- .word 0x0 @ CPU1 - GICD_IGROUPR0
- .word 0x0 @ CPU2 - GICD_IGROUPR0
- .word 0x0 @ CPU3 - GICD_IGROUPR0
-1:
- adr r0, _cpu_state
- mrc p15, 0, r7, c0, c0, 5 @ read MPIDR
- and r7, r7, #0xf @ r7 = cpu id
-/* Read the current cpu state */
- ldr r10, [r0, r7, lsl #2]
-svc_entry:
- tst r10, #(1 << 4)
- adrne r0, _switch_addr
- bne wait_for_addr
-/* Clear INFORM1 */
- ldr r0, =(0x10040000 + 0x804)
- ldr r1, [r0]
- cmp r1, #0x0
- movne r1, #0x0
- strne r1, [r0]
-/* Get INFORM0 */
- ldrne r1, =(0x10040000 + 0x800)
- ldrne pc, [r1]
- tst r10, #(1 << 0)
- ldrne pc, =0x23e00000
- adr r0, _hotplug_addr
-wait_for_addr:
- ldr r1, [r0]
- cmp r1, #0x0
- bxne r1
- wfe
- b wait_for_addr
- .ltorg
-code_end:
- mov pc, lr
+++ /dev/null
-/*
- * Copyright (c) 2010 Samsung Electronics.
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/system.h>
-
-void reset_cpu(ulong addr)
-{
- writel(0x1, samsung_get_base_swreset());
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-
-#include <asm/arch/clock.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/dmc.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/power.h>
-#include <asm/arch/spl.h>
-#include <asm/arch/spi.h>
-
-#include "common_setup.h"
-#include "clock_init.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Index into irom ptr table */
-enum index {
- MMC_INDEX,
- EMMC44_INDEX,
- EMMC44_END_INDEX,
- SPI_INDEX,
- USB_INDEX,
-};
-
-/* IROM Function Pointers Table */
-u32 irom_ptr_table[] = {
- [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */
- [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/
- [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer
- -EMMC4.4 end boot operation */
- [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */
- [USB_INDEX] = 0x02020070, /* iROM Function Pointer-USB boot*/
- };
-
-void *get_irom_func(int index)
-{
- return (void *)*(u32 *)irom_ptr_table[index];
-}
-
-#ifdef CONFIG_USB_BOOTING
-/*
- * Set/clear program flow prediction and return the previous state.
- */
-static int config_branch_prediction(int set_cr_z)
-{
- unsigned int cr;
-
- /* System Control Register: 11th bit Z Branch prediction enable */
- cr = get_cr();
- set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z);
-
- return cr & CR_Z;
-}
-#endif
-
-#ifdef CONFIG_SPI_BOOTING
-static void spi_rx_tx(struct exynos_spi *regs, int todo,
- void *dinp, void const *doutp, int i)
-{
- uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
- int rx_lvl, tx_lvl;
- uint out_bytes, in_bytes;
-
- out_bytes = todo;
- in_bytes = todo;
- setbits_le32(®s->ch_cfg, SPI_CH_RST);
- clrbits_le32(®s->ch_cfg, SPI_CH_RST);
- writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
-
- while (in_bytes) {
- uint32_t spi_sts;
- int temp;
-
- spi_sts = readl(®s->spi_sts);
- rx_lvl = ((spi_sts >> 15) & 0x7f);
- tx_lvl = ((spi_sts >> 6) & 0x7f);
- while (tx_lvl < 32 && out_bytes) {
- temp = 0xffffffff;
- writel(temp, ®s->tx_data);
- out_bytes -= 4;
- tx_lvl += 4;
- }
- while (rx_lvl >= 4 && in_bytes) {
- temp = readl(®s->rx_data);
- if (rxp)
- *rxp++ = temp;
- in_bytes -= 4;
- rx_lvl -= 4;
- }
- }
-}
-
-/*
- * Copy uboot from spi flash to RAM
- *
- * @parma uboot_size size of u-boot to copy
- * @param uboot_addr address in u-boot to copy
- */
-static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
-{
- int upto, todo;
- int i, timeout = 100;
- struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE;
-
- set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
- /* set the spi1 GPIO */
- exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE);
-
- /* set pktcnt and enable it */
- writel(4 | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
- /* set FB_CLK_SEL */
- writel(SPI_FB_DELAY_180, ®s->fb_clk);
- /* set CH_WIDTH and BUS_WIDTH as word */
- setbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
- SPI_MODE_BUS_WIDTH_WORD);
- clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
-
- /* clear rx and tx channel if set priveously */
- clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
-
- setbits_le32(®s->swap_cfg, SPI_RX_SWAP_EN |
- SPI_RX_BYTE_SWAP |
- SPI_RX_HWORD_SWAP);
-
- /* do a soft reset */
- setbits_le32(®s->ch_cfg, SPI_CH_RST);
- clrbits_le32(®s->ch_cfg, SPI_CH_RST);
-
- /* now set rx and tx channel ON */
- setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
- clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
-
- /* Send read instruction (0x3h) followed by a 24 bit addr */
- writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, ®s->tx_data);
-
- /* waiting for TX done */
- while (!(readl(®s->spi_sts) & SPI_ST_TX_DONE)) {
- if (!timeout) {
- debug("SPI TIMEOUT\n");
- break;
- }
- timeout--;
- }
-
- for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
- todo = min(uboot_size - upto, (unsigned int)(1 << 15));
- spi_rx_tx(regs, todo, (void *)(uboot_addr),
- (void *)(SPI_FLASH_UBOOT_POS), i);
- }
-
- setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
-
- /*
- * Let put controller mode to BYTE as
- * SPI driver does not support WORD mode yet
- */
- clrbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
- SPI_MODE_BUS_WIDTH_WORD);
- writel(0, ®s->swap_cfg);
-
- /*
- * Flush spi tx, rx fifos and reset the SPI controller
- * and clear rx/tx channel
- */
- clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
- clrbits_le32(®s->ch_cfg, SPI_CH_RST);
- clrbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
-}
-#endif
-
-/*
-* Copy U-boot from mmc to RAM:
-* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
-* Pointer to API (Data transfer from mmc to ram)
-*/
-void copy_uboot_to_ram(void)
-{
- unsigned int bootmode = BOOT_MODE_OM;
-
- u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
- u32 offset = 0, size = 0;
-#ifdef CONFIG_SPI_BOOTING
- struct spl_machine_param *param = spl_get_machine_params();
-#endif
-#ifdef CONFIG_SUPPORT_EMMC_BOOT
- u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
- void (*end_bootop_from_emmc)(void);
-#endif
-#ifdef CONFIG_USB_BOOTING
- int is_cr_z_set;
- unsigned int sec_boot_check;
-
- /*
- * Note that older hardware (before Exynos5800) does not expect any
- * arguments, but it does not hurt to pass them, so a common function
- * prototype is used.
- */
- u32 (*usb_copy)(u32 num_of_block, u32 *dst);
-
- /* Read iRAM location to check for secondary USB boot mode */
- sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
- if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
- bootmode = BOOT_MODE_USB;
-#endif
-
- if (bootmode == BOOT_MODE_OM)
- bootmode = get_boot_mode();
-
- switch (bootmode) {
-#ifdef CONFIG_SPI_BOOTING
- case BOOT_MODE_SERIAL:
- /* Customised function to copy u-boot from SF */
- exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE);
- break;
-#endif
- case BOOT_MODE_SD:
- offset = BL2_START_OFFSET;
- size = BL2_SIZE_BLOC_COUNT;
- copy_bl2 = get_irom_func(MMC_INDEX);
- break;
-#ifdef CONFIG_SUPPORT_EMMC_BOOT
- case BOOT_MODE_EMMC:
- /* Set the FSYS1 clock divisor value for EMMC boot */
- emmc_boot_clk_div_set();
-
- copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX);
- end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX);
-
- copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
- end_bootop_from_emmc();
- break;
-#endif
-#ifdef CONFIG_USB_BOOTING
- case BOOT_MODE_USB:
- /*
- * iROM needs program flow prediction to be disabled
- * before copy from USB device to RAM
- */
- is_cr_z_set = config_branch_prediction(0);
- usb_copy = get_irom_func(USB_INDEX);
- usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE);
- config_branch_prediction(is_cr_z_set);
- break;
-#endif
- default:
- break;
- }
-
- if (copy_bl2)
- copy_bl2(offset, size, CONFIG_SYS_TEXT_BASE);
-}
-
-void memzero(void *s, size_t n)
-{
- char *ptr = s;
- size_t i;
-
- for (i = 0; i < n; i++)
- *ptr++ = '\0';
-}
-
-/**
- * Set up the U-Boot global_data pointer
- *
- * This sets the address of the global data, and sets up basic values.
- *
- * @param gdp Value to give to gd
- */
-static void setup_global_data(gd_t *gdp)
-{
- gd = gdp;
- memzero((void *)gd, sizeof(gd_t));
- gd->flags |= GD_FLG_RELOC;
- gd->baudrate = CONFIG_BAUDRATE;
- gd->have_console = 1;
-}
-
-void board_init_f(unsigned long bootflag)
-{
- __aligned(8) gd_t local_gd;
- __attribute__((noreturn)) void (*uboot)(void);
-
- setup_global_data(&local_gd);
-
- if (do_lowlevel_init())
- power_exit_wakeup();
-
- copy_uboot_to_ram();
-
- /* Jump to U-Boot image */
- uboot = (void *)CONFIG_SYS_TEXT_BASE;
- (*uboot)();
- /* Never returns Here */
-}
-
-/* Place Holders */
-void board_init_r(gd_t *id, ulong dest_addr)
-{
- /* Function attribute is no-return */
- /* This Function never executes */
- while (1)
- ;
-}
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- * Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/system.h>
-
-static void exynos5_set_usbhost_mode(unsigned int mode)
-{
- struct exynos5_sysreg *sysreg =
- (struct exynos5_sysreg *)samsung_get_base_sysreg();
-
- /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */
- if (mode == USB20_PHY_CFG_HOST_LINK_EN) {
- setbits_le32(&sysreg->usb20phy_cfg,
- USB20_PHY_CFG_HOST_LINK_EN);
- } else {
- clrbits_le32(&sysreg->usb20phy_cfg,
- USB20_PHY_CFG_HOST_LINK_EN);
- }
-}
-
-void set_usbhost_mode(unsigned int mode)
-{
- if (cpu_is_exynos5())
- exynos5_set_usbhost_mode(mode);
-}
-
-static void exynos4_set_system_display(void)
-{
- struct exynos4_sysreg *sysreg =
- (struct exynos4_sysreg *)samsung_get_base_sysreg();
- unsigned int cfg = 0;
-
- /*
- * system register path set
- * 0: MIE/MDNIE
- * 1: FIMD Bypass
- */
- cfg = readl(&sysreg->display_ctrl);
- cfg |= (1 << 1);
- writel(cfg, &sysreg->display_ctrl);
-}
-
-static void exynos5_set_system_display(void)
-{
- struct exynos5_sysreg *sysreg =
- (struct exynos5_sysreg *)samsung_get_base_sysreg();
- unsigned int cfg = 0;
-
- /*
- * system register path set
- * 0: MIE/MDNIE
- * 1: FIMD Bypass
- */
- cfg = readl(&sysreg->disp1blk_cfg);
- cfg |= (1 << 15);
- writel(cfg, &sysreg->disp1blk_cfg);
-}
-
-void set_system_display_ctrl(void)
-{
- if (cpu_is_exynos4())
- exynos4_set_system_display();
- else
- exynos5_set_system_display();
-}
+++ /dev/null
-/*
- * Lowlevel setup for SMDK5250 board based on S5PC520
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/tzpc.h>
-#include <asm/io.h>
-
-/* Setting TZPC[TrustZone Protection Controller] */
-void tzpc_init(void)
-{
- struct exynos_tzpc *tzpc;
- unsigned int addr, start = 0, end = 0;
-
- start = samsung_get_base_tzpc();
-
- if (cpu_is_exynos5())
- end = start + ((EXYNOS5_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET);
- else if (cpu_is_exynos4())
- end = start + ((EXYNOS4_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET);
-
- for (addr = start; addr <= end; addr += TZPC_BASE_OFFSET) {
- tzpc = (struct exynos_tzpc *)addr;
-
- if (addr == start)
- writel(R0SIZE, &tzpc->r0size);
-
- writel(DECPROTXSET, &tzpc->decprot0set);
- writel(DECPROTXSET, &tzpc->decprot1set);
-
- if (cpu_is_exynos5() && (addr == end))
- break;
-
- writel(DECPROTXSET, &tzpc->decprot2set);
- writel(DECPROTXSET, &tzpc->decprot3set);
- }
-}
+++ /dev/null
-/*
- * Copyright (C) 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * MyungJoo Ham <myungjoo.ham@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_ADC_H_
-#define __ASM_ARM_ARCH_ADC_H_
-
-#ifndef __ASSEMBLY__
-struct s5p_adc {
- unsigned int adccon;
- unsigned int adctsc;
- unsigned int adcdly;
- unsigned int adcdat0;
- unsigned int adcdat1;
- unsigned int adcupdn;
- unsigned int adcclrint;
- unsigned int adcmux;
- unsigned int adcclrintpndnup;
-};
-#endif
-
-#endif /* __ASM_ARM_ARCH_ADC_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2013 Samsung Electronics
- * Rajeshwari Shinde <rajeshwari.s@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _EXYNOS_BOARD_H
-#define _EXYNOS_BOARD_H
-
-/*
- * Exynos baord specific changes for
- * board_init
- */
-int exynos_init(void);
-
-/*
- * Exynos board specific changes for
- * board_early_init_f
- */
-int exynos_early_init_f(void);
-
-/*
- * Exynos board specific changes for
- * board_power_init
- */
-int exynos_power_init(void);
-
-#endif /* EXYNOS_BOARD_H */
+++ /dev/null
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_CLK_H_
-#define __ASM_ARM_ARCH_CLK_H_
-
-#define APLL 0
-#define MPLL 1
-#define EPLL 2
-#define HPLL 3
-#define VPLL 4
-#define BPLL 5
-#define RPLL 6
-#define SPLL 7
-#define CPLL 8
-#define DPLL 9
-#define IPLL 10
-
-#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8))
-#define MASK_RATIO(x) (0xf << (x << 4))
-#define SET_PRE_RATIO(x, y) ((y & 0xff) << ((x << 4) + 8))
-#define SET_RATIO(x, y) ((y & 0xf) << (x << 4))
-
-enum pll_src_bit {
- EXYNOS_SRC_MPLL = 6,
- EXYNOS_SRC_EPLL,
- EXYNOS_SRC_VPLL,
- EXYNOS542X_SRC_MPLL = 3,
- EXYNOS542X_SRC_SPLL,
- EXYNOS542X_SRC_EPLL = 6,
- EXYNOS542X_SRC_RPLL,
-};
-
-unsigned long get_pll_clk(int pllreg);
-unsigned long get_arm_clk(void);
-unsigned long get_i2c_clk(void);
-unsigned long get_pwm_clk(void);
-unsigned long get_uart_clk(int dev_index);
-unsigned long get_mmc_clk(int dev_index);
-void set_mmc_clk(int dev_index, unsigned int div);
-unsigned long get_lcd_clk(void);
-void set_lcd_clk(void);
-void set_mipi_clk(void);
-int set_i2s_clk_source(unsigned int i2s_id);
-int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
- unsigned int i2s_id);
-int set_epll_clk(unsigned long rate);
-int set_spi_clk(int periph_id, unsigned int rate);
-
-/**
- * get the clk frequency of the required peripheral
- *
- * @param peripheral Peripheral id
- *
- * @return frequency of the peripheral clk
- */
-unsigned long clock_get_periph_rate(int peripheral);
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_CLOCK_H_
-#define __ASM_ARM_ARCH_CLOCK_H_
-
-#ifndef __ASSEMBLY__
-struct exynos4_clock {
- unsigned char res1[0x4200];
- unsigned int src_leftbus;
- unsigned char res2[0x1fc];
- unsigned int mux_stat_leftbus;
- unsigned char res4[0xfc];
- unsigned int div_leftbus;
- unsigned char res5[0xfc];
- unsigned int div_stat_leftbus;
- unsigned char res6[0x1fc];
- unsigned int gate_ip_leftbus;
- unsigned char res7[0x1fc];
- unsigned int clkout_leftbus;
- unsigned int clkout_leftbus_div_stat;
- unsigned char res8[0x37f8];
- unsigned int src_rightbus;
- unsigned char res9[0x1fc];
- unsigned int mux_stat_rightbus;
- unsigned char res10[0xfc];
- unsigned int div_rightbus;
- unsigned char res11[0xfc];
- unsigned int div_stat_rightbus;
- unsigned char res12[0x1fc];
- unsigned int gate_ip_rightbus;
- unsigned char res13[0x1fc];
- unsigned int clkout_rightbus;
- unsigned int clkout_rightbus_div_stat;
- unsigned char res14[0x3608];
- unsigned int epll_lock;
- unsigned char res15[0xc];
- unsigned int vpll_lock;
- unsigned char res16[0xec];
- unsigned int epll_con0;
- unsigned int epll_con1;
- unsigned char res17[0x8];
- unsigned int vpll_con0;
- unsigned int vpll_con1;
- unsigned char res18[0xe8];
- unsigned int src_top0;
- unsigned int src_top1;
- unsigned char res19[0x8];
- unsigned int src_cam;
- unsigned int src_tv;
- unsigned int src_mfc;
- unsigned int src_g3d;
- unsigned int src_image;
- unsigned int src_lcd0;
- unsigned int src_lcd1;
- unsigned int src_maudio;
- unsigned int src_fsys;
- unsigned char res20[0xc];
- unsigned int src_peril0;
- unsigned int src_peril1;
- unsigned char res21[0xb8];
- unsigned int src_mask_top;
- unsigned char res22[0xc];
- unsigned int src_mask_cam;
- unsigned int src_mask_tv;
- unsigned char res23[0xc];
- unsigned int src_mask_lcd0;
- unsigned int src_mask_lcd1;
- unsigned int src_mask_maudio;
- unsigned int src_mask_fsys;
- unsigned char res24[0xc];
- unsigned int src_mask_peril0;
- unsigned int src_mask_peril1;
- unsigned char res25[0xb8];
- unsigned int mux_stat_top;
- unsigned char res26[0x14];
- unsigned int mux_stat_mfc;
- unsigned int mux_stat_g3d;
- unsigned int mux_stat_image;
- unsigned char res27[0xdc];
- unsigned int div_top;
- unsigned char res28[0xc];
- unsigned int div_cam;
- unsigned int div_tv;
- unsigned int div_mfc;
- unsigned int div_g3d;
- unsigned int div_image;
- unsigned int div_lcd0;
- unsigned int div_lcd1;
- unsigned int div_maudio;
- unsigned int div_fsys0;
- unsigned int div_fsys1;
- unsigned int div_fsys2;
- unsigned int div_fsys3;
- unsigned int div_peril0;
- unsigned int div_peril1;
- unsigned int div_peril2;
- unsigned int div_peril3;
- unsigned int div_peril4;
- unsigned int div_peril5;
- unsigned char res29[0x18];
- unsigned int div2_ratio;
- unsigned char res30[0x8c];
- unsigned int div_stat_top;
- unsigned char res31[0xc];
- unsigned int div_stat_cam;
- unsigned int div_stat_tv;
- unsigned int div_stat_mfc;
- unsigned int div_stat_g3d;
- unsigned int div_stat_image;
- unsigned int div_stat_lcd0;
- unsigned int div_stat_lcd1;
- unsigned int div_stat_maudio;
- unsigned int div_stat_fsys0;
- unsigned int div_stat_fsys1;
- unsigned int div_stat_fsys2;
- unsigned int div_stat_fsys3;
- unsigned int div_stat_peril0;
- unsigned int div_stat_peril1;
- unsigned int div_stat_peril2;
- unsigned int div_stat_peril3;
- unsigned int div_stat_peril4;
- unsigned int div_stat_peril5;
- unsigned char res32[0x18];
- unsigned int div2_stat;
- unsigned char res33[0x29c];
- unsigned int gate_ip_cam;
- unsigned int gate_ip_tv;
- unsigned int gate_ip_mfc;
- unsigned int gate_ip_g3d;
- unsigned int gate_ip_image;
- unsigned int gate_ip_lcd0;
- unsigned int gate_ip_lcd1;
- unsigned char res34[0x4];
- unsigned int gate_ip_fsys;
- unsigned char res35[0x8];
- unsigned int gate_ip_gps;
- unsigned int gate_ip_peril;
- unsigned char res36[0xc];
- unsigned int gate_ip_perir;
- unsigned char res37[0xc];
- unsigned int gate_block;
- unsigned char res38[0x8c];
- unsigned int clkout_cmu_top;
- unsigned int clkout_cmu_top_div_stat;
- unsigned char res39[0x37f8];
- unsigned int src_dmc;
- unsigned char res40[0xfc];
- unsigned int src_mask_dmc;
- unsigned char res41[0xfc];
- unsigned int mux_stat_dmc;
- unsigned char res42[0xfc];
- unsigned int div_dmc0;
- unsigned int div_dmc1;
- unsigned char res43[0xf8];
- unsigned int div_stat_dmc0;
- unsigned int div_stat_dmc1;
- unsigned char res44[0x2f8];
- unsigned int gate_ip_dmc;
- unsigned char res45[0xfc];
- unsigned int clkout_cmu_dmc;
- unsigned int clkout_cmu_dmc_div_stat;
- unsigned char res46[0x5f8];
- unsigned int dcgidx_map0;
- unsigned int dcgidx_map1;
- unsigned int dcgidx_map2;
- unsigned char res47[0x14];
- unsigned int dcgperf_map0;
- unsigned int dcgperf_map1;
- unsigned char res48[0x18];
- unsigned int dvcidx_map;
- unsigned char res49[0x1c];
- unsigned int freq_cpu;
- unsigned int freq_dpm;
- unsigned char res50[0x18];
- unsigned int dvsemclk_en;
- unsigned int maxperf;
- unsigned char res51[0x2f78];
- unsigned int apll_lock;
- unsigned char res52[0x4];
- unsigned int mpll_lock;
- unsigned char res53[0xf4];
- unsigned int apll_con0;
- unsigned int apll_con1;
- unsigned int mpll_con0;
- unsigned int mpll_con1;
- unsigned char res54[0xf0];
- unsigned int src_cpu;
- unsigned char res55[0x1fc];
- unsigned int mux_stat_cpu;
- unsigned char res56[0xfc];
- unsigned int div_cpu0;
- unsigned int div_cpu1;
- unsigned char res57[0xf8];
- unsigned int div_stat_cpu0;
- unsigned int div_stat_cpu1;
- unsigned char res58[0x3f8];
- unsigned int clkout_cmu_cpu;
- unsigned int clkout_cmu_cpu_div_stat;
- unsigned char res59[0x5f8];
- unsigned int armclk_stopctrl;
- unsigned int atclk_stopctrl;
- unsigned char res60[0x8];
- unsigned int parityfail_status;
- unsigned int parityfail_clear;
- unsigned char res61[0xe8];
- unsigned int apll_con0_l8;
- unsigned int apll_con0_l7;
- unsigned int apll_con0_l6;
- unsigned int apll_con0_l5;
- unsigned int apll_con0_l4;
- unsigned int apll_con0_l3;
- unsigned int apll_con0_l2;
- unsigned int apll_con0_l1;
- unsigned int iem_control;
- unsigned char res62[0xdc];
- unsigned int apll_con1_l8;
- unsigned int apll_con1_l7;
- unsigned int apll_con1_l6;
- unsigned int apll_con1_l5;
- unsigned int apll_con1_l4;
- unsigned int apll_con1_l3;
- unsigned int apll_con1_l2;
- unsigned int apll_con1_l1;
- unsigned char res63[0xe0];
- unsigned int div_iem_l8;
- unsigned int div_iem_l7;
- unsigned int div_iem_l6;
- unsigned int div_iem_l5;
- unsigned int div_iem_l4;
- unsigned int div_iem_l3;
- unsigned int div_iem_l2;
- unsigned int div_iem_l1;
-};
-
-struct exynos4x12_clock {
- unsigned char res1[0x4200];
- unsigned int src_leftbus;
- unsigned char res2[0x1fc];
- unsigned int mux_stat_leftbus;
- unsigned char res3[0xfc];
- unsigned int div_leftbus;
- unsigned char res4[0xfc];
- unsigned int div_stat_leftbus;
- unsigned char res5[0x1fc];
- unsigned int gate_ip_leftbus;
- unsigned char res6[0x12c];
- unsigned int gate_ip_image;
- unsigned char res7[0xcc];
- unsigned int clkout_leftbus;
- unsigned int clkout_leftbus_div_stat;
- unsigned char res8[0x37f8];
- unsigned int src_rightbus;
- unsigned char res9[0x1fc];
- unsigned int mux_stat_rightbus;
- unsigned char res10[0xfc];
- unsigned int div_rightbus;
- unsigned char res11[0xfc];
- unsigned int div_stat_rightbus;
- unsigned char res12[0x1fc];
- unsigned int gate_ip_rightbus;
- unsigned char res13[0x15c];
- unsigned int gate_ip_perir;
- unsigned char res14[0x9c];
- unsigned int clkout_rightbus;
- unsigned int clkout_rightbus_div_stat;
- unsigned char res15[0x3608];
- unsigned int epll_lock;
- unsigned char res16[0xc];
- unsigned int vpll_lock;
- unsigned char res17[0xec];
- unsigned int epll_con0;
- unsigned int epll_con1;
- unsigned int epll_con2;
- unsigned char res18[0x4];
- unsigned int vpll_con0;
- unsigned int vpll_con1;
- unsigned int vpll_con2;
- unsigned char res19[0xe4];
- unsigned int src_top0;
- unsigned int src_top1;
- unsigned char res20[0x8];
- unsigned int src_cam;
- unsigned int src_tv;
- unsigned int src_mfc;
- unsigned int src_g3d;
- unsigned char res21[0x4];
- unsigned int src_lcd;
- unsigned int src_isp;
- unsigned int src_maudio;
- unsigned int src_fsys;
- unsigned char res22[0xc];
- unsigned int src_peril0;
- unsigned int src_peril1;
- unsigned int src_cam1;
- unsigned char res23[0xb4];
- unsigned int src_mask_top;
- unsigned char res24[0xc];
- unsigned int src_mask_cam;
- unsigned int src_mask_tv;
- unsigned char res25[0xc];
- unsigned int src_mask_lcd;
- unsigned int src_mask_isp;
- unsigned int src_mask_maudio;
- unsigned int src_mask_fsys;
- unsigned char res26[0xc];
- unsigned int src_mask_peril0;
- unsigned int src_mask_peril1;
- unsigned char res27[0xb8];
- unsigned int mux_stat_top0;
- unsigned int mux_stat_top1;
- unsigned char res28[0x10];
- unsigned int mux_stat_mfc;
- unsigned int mux_stat_g3d;
- unsigned char res29[0x28];
- unsigned int mux_stat_cam1;
- unsigned char res30[0xb4];
- unsigned int div_top;
- unsigned char res31[0xc];
- unsigned int div_cam;
- unsigned int div_tv;
- unsigned int div_mfc;
- unsigned int div_g3d;
- unsigned char res32[0x4];
- unsigned int div_lcd;
- unsigned int div_isp;
- unsigned int div_maudio;
- unsigned int div_fsys0;
- unsigned int div_fsys1;
- unsigned int div_fsys2;
- unsigned int div_fsys3;
- unsigned int div_peril0;
- unsigned int div_peril1;
- unsigned int div_peril2;
- unsigned int div_peril3;
- unsigned int div_peril4;
- unsigned int div_peril5;
- unsigned int div_cam1;
- unsigned char res33[0x14];
- unsigned int div2_ratio;
- unsigned char res34[0x8c];
- unsigned int div_stat_top;
- unsigned char res35[0xc];
- unsigned int div_stat_cam;
- unsigned int div_stat_tv;
- unsigned int div_stat_mfc;
- unsigned int div_stat_g3d;
- unsigned char res36[0x4];
- unsigned int div_stat_lcd;
- unsigned int div_stat_isp;
- unsigned int div_stat_maudio;
- unsigned int div_stat_fsys0;
- unsigned int div_stat_fsys1;
- unsigned int div_stat_fsys2;
- unsigned int div_stat_fsys3;
- unsigned int div_stat_peril0;
- unsigned int div_stat_peril1;
- unsigned int div_stat_peril2;
- unsigned int div_stat_peril3;
- unsigned int div_stat_peril4;
- unsigned int div_stat_peril5;
- unsigned int div_stat_cam1;
- unsigned char res37[0x14];
- unsigned int div2_stat;
- unsigned char res38[0x29c];
- unsigned int gate_ip_cam;
- unsigned int gate_ip_tv;
- unsigned int gate_ip_mfc;
- unsigned int gate_ip_g3d;
- unsigned char res39[0x4];
- unsigned int gate_ip_lcd;
- unsigned int gate_ip_isp;
- unsigned char res40[0x4];
- unsigned int gate_ip_fsys;
- unsigned char res41[0x8];
- unsigned int gate_ip_gps;
- unsigned int gate_ip_peril;
- unsigned char res42[0xc];
- unsigned char res43[0x4];
- unsigned char res44[0xc];
- unsigned int gate_block;
- unsigned char res45[0x8c];
- unsigned int clkout_cmu_top;
- unsigned int clkout_cmu_top_div_stat;
- unsigned char res46[0x3600];
- unsigned int mpll_lock;
- unsigned char res47[0xfc];
- unsigned int mpll_con0;
- unsigned int mpll_con1;
- unsigned char res48[0xf0];
- unsigned int src_dmc;
- unsigned char res49[0xfc];
- unsigned int src_mask_dmc;
- unsigned char res50[0xfc];
- unsigned int mux_stat_dmc;
- unsigned char res51[0xfc];
- unsigned int div_dmc0;
- unsigned int div_dmc1;
- unsigned char res52[0xf8];
- unsigned int div_stat_dmc0;
- unsigned int div_stat_dmc1;
- unsigned char res53[0xf8];
- unsigned int gate_bus_dmc0;
- unsigned int gate_bus_dmc1;
- unsigned char res54[0x1f8];
- unsigned int gate_ip_dmc0;
- unsigned int gate_ip_dmc1;
- unsigned char res55[0xf8];
- unsigned int clkout_cmu_dmc;
- unsigned int clkout_cmu_dmc_div_stat;
- unsigned char res56[0x5f8];
- unsigned int dcgidx_map0;
- unsigned int dcgidx_map1;
- unsigned int dcgidx_map2;
- unsigned char res57[0x14];
- unsigned int dcgperf_map0;
- unsigned int dcgperf_map1;
- unsigned char res58[0x18];
- unsigned int dvcidx_map;
- unsigned char res59[0x1c];
- unsigned int freq_cpu;
- unsigned int freq_dpm;
- unsigned char res60[0x18];
- unsigned int dvsemclk_en;
- unsigned int maxperf;
- unsigned char res61[0x8];
- unsigned int dmc_freq_ctrl;
- unsigned int dmc_pause_ctrl;
- unsigned int dddrphy_lock_ctrl;
- unsigned int c2c_state;
- unsigned char res62[0x2f60];
- unsigned int apll_lock;
- unsigned char res63[0x8];
- unsigned char res64[0xf4];
- unsigned int apll_con0;
- unsigned int apll_con1;
- unsigned char res65[0xf8];
- unsigned int src_cpu;
- unsigned char res66[0x1fc];
- unsigned int mux_stat_cpu;
- unsigned char res67[0xfc];
- unsigned int div_cpu0;
- unsigned int div_cpu1;
- unsigned char res68[0xf8];
- unsigned int div_stat_cpu0;
- unsigned int div_stat_cpu1;
- unsigned char res69[0x2f8];
- unsigned int clk_gate_ip_cpu;
- unsigned char res70[0xfc];
- unsigned int clkout_cmu_cpu;
- unsigned int clkout_cmu_cpu_div_stat;
- unsigned char res71[0x5f8];
- unsigned int armclk_stopctrl;
- unsigned int atclk_stopctrl;
- unsigned char res72[0x10];
- unsigned char res73[0x8];
- unsigned int pwr_ctrl;
- unsigned int pwr_ctrl2;
- unsigned char res74[0xd8];
- unsigned int apll_con0_l8;
- unsigned int apll_con0_l7;
- unsigned int apll_con0_l6;
- unsigned int apll_con0_l5;
- unsigned int apll_con0_l4;
- unsigned int apll_con0_l3;
- unsigned int apll_con0_l2;
- unsigned int apll_con0_l1;
- unsigned int iem_control;
- unsigned char res75[0xdc];
- unsigned int apll_con1_l8;
- unsigned int apll_con1_l7;
- unsigned int apll_con1_l6;
- unsigned int apll_con1_l5;
- unsigned int apll_con1_l4;
- unsigned int apll_con1_l3;
- unsigned int apll_con1_l2;
- unsigned int apll_con1_l1;
- unsigned char res76[0xe0];
- unsigned int div_iem_l8;
- unsigned int div_iem_l7;
- unsigned int div_iem_l6;
- unsigned int div_iem_l5;
- unsigned int div_iem_l4;
- unsigned int div_iem_l3;
- unsigned int div_iem_l2;
- unsigned int div_iem_l1;
- unsigned char res77[0xe0];
- unsigned int l2_status;
- unsigned char res78[0xc];
- unsigned int cpu_status;
- unsigned char res79[0xc];
- unsigned int ptm_status;
- unsigned char res80[0x2edc];
- unsigned int div_isp0;
- unsigned int div_isp1;
- unsigned char res81[0xf8];
- unsigned int div_stat_isp0;
- unsigned int div_stat_isp1;
- unsigned char res82[0x3f8];
- unsigned int gate_ip_isp0;
- unsigned int gate_ip_isp1;
- unsigned char res83[0x1f8];
- unsigned int clkout_cmu_isp;
- unsigned int clkout_cmu_ispd_div_stat;
- unsigned char res84[0xf8];
- unsigned int cmu_isp_spar0;
- unsigned int cmu_isp_spar1;
- unsigned int cmu_isp_spar2;
- unsigned int cmu_isp_spar3;
-};
-
-struct exynos5_clock {
- unsigned int apll_lock;
- unsigned char res1[0xfc];
- unsigned int apll_con0;
- unsigned int apll_con1;
- unsigned char res2[0xf8];
- unsigned int src_cpu;
- unsigned char res3[0x1fc];
- unsigned int mux_stat_cpu;
- unsigned char res4[0xfc];
- unsigned int div_cpu0;
- unsigned int div_cpu1;
- unsigned char res5[0xf8];
- unsigned int div_stat_cpu0;
- unsigned int div_stat_cpu1;
- unsigned char res6[0x1f8];
- unsigned int gate_sclk_cpu;
- unsigned char res7[0x1fc];
- unsigned int clkout_cmu_cpu;
- unsigned int clkout_cmu_cpu_div_stat;
- unsigned char res8[0x5f8];
- unsigned int armclk_stopctrl;
- unsigned char res9[0x0c];
- unsigned int parityfail_status;
- unsigned int parityfail_clear;
- unsigned char res10[0x8];
- unsigned int pwr_ctrl;
- unsigned int pwr_ctr2;
- unsigned char res11[0xd8];
- unsigned int apll_con0_l8;
- unsigned int apll_con0_l7;
- unsigned int apll_con0_l6;
- unsigned int apll_con0_l5;
- unsigned int apll_con0_l4;
- unsigned int apll_con0_l3;
- unsigned int apll_con0_l2;
- unsigned int apll_con0_l1;
- unsigned int iem_control;
- unsigned char res12[0xdc];
- unsigned int apll_con1_l8;
- unsigned int apll_con1_l7;
- unsigned int apll_con1_l6;
- unsigned int apll_con1_l5;
- unsigned int apll_con1_l4;
- unsigned int apll_con1_l3;
- unsigned int apll_con1_l2;
- unsigned int apll_con1_l1;
- unsigned char res13[0xe0];
- unsigned int div_iem_l8;
- unsigned int div_iem_l7;
- unsigned int div_iem_l6;
- unsigned int div_iem_l5;
- unsigned int div_iem_l4;
- unsigned int div_iem_l3;
- unsigned int div_iem_l2;
- unsigned int div_iem_l1;
- unsigned char res14[0x2ce0];
- unsigned int mpll_lock;
- unsigned char res15[0xfc];
- unsigned int mpll_con0;
- unsigned int mpll_con1;
- unsigned char res16[0xf8];
- unsigned int src_core0;
- unsigned int src_core1;
- unsigned char res17[0xf8];
- unsigned int src_mask_core;
- unsigned char res18[0x100];
- unsigned int mux_stat_core1;
- unsigned char res19[0xf8];
- unsigned int div_core0;
- unsigned int div_core1;
- unsigned int div_sysrgt;
- unsigned char res20[0xf4];
- unsigned int div_stat_core0;
- unsigned int div_stat_core1;
- unsigned int div_stat_sysrgt;
- unsigned char res21[0x2f4];
- unsigned int gate_ip_core;
- unsigned int gate_ip_sysrgt;
- unsigned char res22[0x8];
- unsigned int c2c_monitor;
- unsigned char res23[0xec];
- unsigned int clkout_cmu_core;
- unsigned int clkout_cmu_core_div_stat;
- unsigned char res24[0x5f8];
- unsigned int dcgidx_map0;
- unsigned int dcgidx_map1;
- unsigned int dcgidx_map2;
- unsigned char res25[0x14];
- unsigned int dcgperf_map0;
- unsigned int dcgperf_map1;
- unsigned char res26[0x18];
- unsigned int dvcidx_map;
- unsigned char res27[0x1c];
- unsigned int freq_cpu;
- unsigned int freq_dpm;
- unsigned char res28[0x18];
- unsigned int dvsemclk_en;
- unsigned int maxperf;
- unsigned char res29[0xf78];
- unsigned int c2c_config;
- unsigned char res30[0x24fc];
- unsigned int div_acp;
- unsigned char res31[0xfc];
- unsigned int div_stat_acp;
- unsigned char res32[0x1fc];
- unsigned int gate_ip_acp;
- unsigned char res33[0xfc];
- unsigned int div_syslft;
- unsigned char res34[0xc];
- unsigned int div_stat_syslft;
- unsigned char res35[0x1c];
- unsigned int gate_ip_syslft;
- unsigned char res36[0xcc];
- unsigned int clkout_cmu_acp;
- unsigned int clkout_cmu_acp_div_stat;
- unsigned char res37[0x8];
- unsigned int ufmc_config;
- unsigned char res38[0x38ec];
- unsigned int div_isp0;
- unsigned int div_isp1;
- unsigned int div_isp2;
- unsigned char res39[0xf4];
- unsigned int div_stat_isp0;
- unsigned int div_stat_isp1;
- unsigned int div_stat_isp2;
- unsigned char res40[0x3f4];
- unsigned int gate_ip_isp0;
- unsigned int gate_ip_isp1;
- unsigned char res41[0xf8];
- unsigned int gate_sclk_isp;
- unsigned char res42[0xc];
- unsigned int mcuisp_pwr_ctrl;
- unsigned char res43[0xec];
- unsigned int clkout_cmu_isp;
- unsigned int clkout_cmu_isp_div_stat;
- unsigned char res44[0x3618];
- unsigned int cpll_lock;
- unsigned char res45[0xc];
- unsigned int epll_lock;
- unsigned char res46[0xc];
- unsigned int vpll_lock;
- unsigned char res47[0xc];
- unsigned int gpll_lock;
- unsigned char res48[0xcc];
- unsigned int cpll_con0;
- unsigned int cpll_con1;
- unsigned char res49[0x8];
- unsigned int epll_con0;
- unsigned int epll_con1;
- unsigned int epll_con2;
- unsigned char res50[0x4];
- unsigned int vpll_con0;
- unsigned int vpll_con1;
- unsigned int vpll_con2;
- unsigned char res51[0x4];
- unsigned int gpll_con0;
- unsigned int gpll_con1;
- unsigned char res52[0xb8];
- unsigned int src_top0;
- unsigned int src_top1;
- unsigned int src_top2;
- unsigned int src_top3;
- unsigned int src_gscl;
- unsigned char res53[0x8];
- unsigned int src_disp1_0;
- unsigned char res54[0x10];
- unsigned int src_mau;
- unsigned int src_fsys;
- unsigned int src_gen;
- unsigned char res55[0x4];
- unsigned int src_peric0;
- unsigned int src_peric1;
- unsigned char res56[0x18];
- unsigned int sclk_src_isp;
- unsigned char res57[0x9c];
- unsigned int src_mask_top;
- unsigned char res58[0xc];
- unsigned int src_mask_gscl;
- unsigned char res59[0x8];
- unsigned int src_mask_disp1_0;
- unsigned char res60[0x4];
- unsigned int src_mask_mau;
- unsigned char res61[0x8];
- unsigned int src_mask_fsys;
- unsigned int src_mask_gen;
- unsigned char res62[0x8];
- unsigned int src_mask_peric0;
- unsigned int src_mask_peric1;
- unsigned char res63[0x18];
- unsigned int src_mask_isp;
- unsigned char res67[0x9c];
- unsigned int mux_stat_top0;
- unsigned int mux_stat_top1;
- unsigned int mux_stat_top2;
- unsigned int mux_stat_top3;
- unsigned char res68[0xf0];
- unsigned int div_top0;
- unsigned int div_top1;
- unsigned char res69[0x8];
- unsigned int div_gscl;
- unsigned char res70[0x8];
- unsigned int div_disp1_0;
- unsigned char res71[0xc];
- unsigned int div_gen;
- unsigned char res72[0x4];
- unsigned int div_mau;
- unsigned int div_fsys0;
- unsigned int div_fsys1;
- unsigned int div_fsys2;
- unsigned char res73[0x4];
- unsigned int div_peric0;
- unsigned int div_peric1;
- unsigned int div_peric2;
- unsigned int div_peric3;
- unsigned int div_peric4;
- unsigned int div_peric5;
- unsigned char res74[0x10];
- unsigned int sclk_div_isp;
- unsigned char res75[0xc];
- unsigned int div2_ratio0;
- unsigned int div2_ratio1;
- unsigned char res76[0x8];
- unsigned int div4_ratio;
- unsigned char res77[0x6c];
- unsigned int div_stat_top0;
- unsigned int div_stat_top1;
- unsigned char res78[0x8];
- unsigned int div_stat_gscl;
- unsigned char res79[0x8];
- unsigned int div_stat_disp1_0;
- unsigned char res80[0xc];
- unsigned int div_stat_gen;
- unsigned char res81[0x4];
- unsigned int div_stat_mau;
- unsigned int div_stat_fsys0;
- unsigned int div_stat_fsys1;
- unsigned int div_stat_fsys2;
- unsigned char res82[0x4];
- unsigned int div_stat_peric0;
- unsigned int div_stat_peric1;
- unsigned int div_stat_peric2;
- unsigned int div_stat_peric3;
- unsigned int div_stat_peric4;
- unsigned int div_stat_peric5;
- unsigned char res83[0x10];
- unsigned int sclk_div_stat_isp;
- unsigned char res84[0xc];
- unsigned int div2_stat0;
- unsigned int div2_stat1;
- unsigned char res85[0x8];
- unsigned int div4_stat;
- unsigned char res86[0x184];
- unsigned int gate_top_sclk_disp1;
- unsigned int gate_top_sclk_gen;
- unsigned char res87[0xc];
- unsigned int gate_top_sclk_mau;
- unsigned int gate_top_sclk_fsys;
- unsigned char res88[0xc];
- unsigned int gate_top_sclk_peric;
- unsigned char res89[0x1c];
- unsigned int gate_top_sclk_isp;
- unsigned char res90[0xac];
- unsigned int gate_ip_gscl;
- unsigned char res91[0x4];
- unsigned int gate_ip_disp1;
- unsigned int gate_ip_mfc;
- unsigned int gate_ip_g3d;
- unsigned int gate_ip_gen;
- unsigned char res92[0xc];
- unsigned int gate_ip_fsys;
- unsigned char res93[0x8];
- unsigned int gate_ip_peric;
- unsigned char res94[0xc];
- unsigned int gate_ip_peris;
- unsigned char res95[0x1c];
- unsigned int gate_block;
- unsigned char res96[0x1c];
- unsigned int mcuiop_pwr_ctrl;
- unsigned char res97[0x5c];
- unsigned int clkout_cmu_top;
- unsigned int clkout_cmu_top_div_stat;
- unsigned char res98[0x37f8];
- unsigned int src_lex;
- unsigned char res99[0x1fc];
- unsigned int mux_stat_lex;
- unsigned char res100[0xfc];
- unsigned int div_lex;
- unsigned char res101[0xfc];
- unsigned int div_stat_lex;
- unsigned char res102[0x1fc];
- unsigned int gate_ip_lex;
- unsigned char res103[0x1fc];
- unsigned int clkout_cmu_lex;
- unsigned int clkout_cmu_lex_div_stat;
- unsigned char res104[0x3af8];
- unsigned int div_r0x;
- unsigned char res105[0xfc];
- unsigned int div_stat_r0x;
- unsigned char res106[0x1fc];
- unsigned int gate_ip_r0x;
- unsigned char res107[0x1fc];
- unsigned int clkout_cmu_r0x;
- unsigned int clkout_cmu_r0x_div_stat;
- unsigned char res108[0x3af8];
- unsigned int div_r1x;
- unsigned char res109[0xfc];
- unsigned int div_stat_r1x;
- unsigned char res110[0x1fc];
- unsigned int gate_ip_r1x;
- unsigned char res111[0x1fc];
- unsigned int clkout_cmu_r1x;
- unsigned int clkout_cmu_r1x_div_stat;
- unsigned char res112[0x3608];
- unsigned int bpll_lock;
- unsigned char res113[0xfc];
- unsigned int bpll_con0;
- unsigned int bpll_con1;
- unsigned char res114[0xe8];
- unsigned int src_cdrex;
- unsigned char res115[0x1fc];
- unsigned int mux_stat_cdrex;
- unsigned char res116[0xfc];
- unsigned int div_cdrex;
- unsigned char res117[0xfc];
- unsigned int div_stat_cdrex;
- unsigned char res118[0x2fc];
- unsigned int gate_ip_cdrex;
- unsigned char res119[0x10];
- unsigned int dmc_freq_ctrl;
- unsigned char res120[0x4];
- unsigned int drex2_pause;
- unsigned char res121[0xe0];
- unsigned int clkout_cmu_cdrex;
- unsigned int clkout_cmu_cdrex_div_stat;
- unsigned char res122[0x8];
- unsigned int lpddr3phy_ctrl;
- unsigned int lpddr3phy_con0;
- unsigned int lpddr3phy_con1;
- unsigned int lpddr3phy_con2;
- unsigned int lpddr3phy_con3;
- unsigned int pll_div2_sel;
- unsigned char res123[0xf5d8];
-};
-
-struct exynos5420_clock {
- unsigned int apll_lock; /* 0x10010000 */
- unsigned char res1[0xfc];
- unsigned int apll_con0;
- unsigned int apll_con1;
- unsigned char res2[0xf8];
- unsigned int src_cpu;
- unsigned char res3[0x1fc];
- unsigned int mux_stat_cpu;
- unsigned char res4[0xfc];
- unsigned int div_cpu0; /* 0x10010500 */
- unsigned int div_cpu1;
- unsigned char res5[0xf8];
- unsigned int div_stat_cpu0;
- unsigned int div_stat_cpu1;
- unsigned char res6[0xf8];
- unsigned int gate_bus_cpu;
- unsigned char res7[0xfc];
- unsigned int gate_sclk_cpu;
- unsigned char res8[0x1fc];
- unsigned int clkout_cmu_cpu; /* 0x10010a00 */
- unsigned int clkout_cmu_cpu_div_stat;
- unsigned char res9[0x5f8];
- unsigned int armclk_stopctrl;
- unsigned char res10[0x4];
- unsigned int arm_ema_ctrl;
- unsigned int arm_ema_status;
- unsigned char res11[0x10];
- unsigned int pwr_ctrl;
- unsigned int pwr_ctrl2;
- unsigned char res12[0xd8];
- unsigned int apll_con0_l8; /* 0x1001100 */
- unsigned int apll_con0_l7;
- unsigned int apll_con0_l6;
- unsigned int apll_con0_l5;
- unsigned int apll_con0_l4;
- unsigned int apll_con0_l3;
- unsigned int apll_con0_l2;
- unsigned int apll_con0_l1;
- unsigned int iem_control;
- unsigned char res13[0xdc];
- unsigned int apll_con1_l8; /* 0x10011200 */
- unsigned int apll_con1_l7;
- unsigned int apll_con1_l6;
- unsigned int apll_con1_l5;
- unsigned int apll_con1_l4;
- unsigned int apll_con1_l3;
- unsigned int apll_con1_l2;
- unsigned int apll_con1_l1;
- unsigned char res14[0xe0];
- unsigned int clkdiv_iem_l8;
- unsigned int clkdiv_iem_l7; /* 0x10011304 */
- unsigned int clkdiv_iem_l6;
- unsigned int clkdiv_iem_l5;
- unsigned int clkdiv_iem_l4;
- unsigned int clkdiv_iem_l3;
- unsigned int clkdiv_iem_l2;
- unsigned int clkdiv_iem_l1;
- unsigned char res15[0xe0];
- unsigned int l2_status;
- unsigned char res16[0x0c];
- unsigned int cpu_status; /* 0x10011410 */
- unsigned char res17[0x0c];
- unsigned int ptm_status;
- unsigned char res18[0xbdc];
- unsigned int cmu_cpu_spare0;
- unsigned int cmu_cpu_spare1;
- unsigned int cmu_cpu_spare2;
- unsigned int cmu_cpu_spare3;
- unsigned int cmu_cpu_spare4;
- unsigned char res19[0x1fdc];
- unsigned int cmu_cpu_version;
- unsigned char res20[0x20c];
- unsigned int src_cperi0; /* 0x10014200 */
- unsigned int src_cperi1;
- unsigned char res21[0xf8];
- unsigned int src_mask_cperi;
- unsigned char res22[0x100];
- unsigned int mux_stat_cperi1;
- unsigned char res23[0xfc];
- unsigned int div_cperi1;
- unsigned char res24[0xfc];
- unsigned int div_stat_cperi1;
- unsigned char res25[0xf8];
- unsigned int gate_bus_cperi0; /* 0x10014700 */
- unsigned int gate_bus_cperi1;
- unsigned char res26[0xf8];
- unsigned int gate_sclk_cperi;
- unsigned char res27[0xfc];
- unsigned int gate_ip_cperi;
- unsigned char res28[0xfc];
- unsigned int clkout_cmu_cperi;
- unsigned int clkout_cmu_cperi_div_stat;
- unsigned char res29[0x5f8];
- unsigned int dcgidx_map0; /* 0x10015000 */
- unsigned int dcgidx_map1;
- unsigned int dcgidx_map2;
- unsigned char res30[0x14];
- unsigned int dcgperf_map0;
- unsigned int dcgperf_map1;
- unsigned char res31[0x18];
- unsigned int dvcidx_map;
- unsigned char res32[0x1c];
- unsigned int freq_cpu;
- unsigned int freq_dpm;
- unsigned char res33[0x18];
- unsigned int dvsemclk_en; /* 0x10015080 */
- unsigned int maxperf;
- unsigned char res34[0x2e78];
- unsigned int cmu_cperi_spare0;
- unsigned int cmu_cperi_spare1;
- unsigned int cmu_cperi_spare2;
- unsigned int cmu_cperi_spare3;
- unsigned int cmu_cperi_spare4;
- unsigned int cmu_cperi_spare5;
- unsigned int cmu_cperi_spare6;
- unsigned int cmu_cperi_spare7;
- unsigned int cmu_cperi_spare8;
- unsigned char res35[0xcc];
- unsigned int cmu_cperi_version; /* 0x10017ff0 */
- unsigned char res36[0x50c];
- unsigned int div_g2d;
- unsigned char res37[0xfc];
- unsigned int div_stat_g2d;
- unsigned char res38[0xfc];
- unsigned int gate_bus_g2d;
- unsigned char res39[0xfc];
- unsigned int gate_ip_g2d;
- unsigned char res40[0x1fc];
- unsigned int clkout_cmu_g2d;
- unsigned int clkout_cmu_g2d_div_stat; /* 0x10018a04 */
- unsigned char res41[0xf8];
- unsigned int cmu_g2d_spare0;
- unsigned int cmu_g2d_spare1;
- unsigned int cmu_g2d_spare2;
- unsigned int cmu_g2d_spare3;
- unsigned int cmu_g2d_spare4;
- unsigned char res42[0x34dc];
- unsigned int cmu_g2d_version;
- unsigned char res43[0x30c];
- unsigned int div_cmu_isp0;
- unsigned int div_cmu_isp1;
- unsigned int div_isp2; /* 0x1001c308 */
- unsigned char res44[0xf4];
- unsigned int div_stat_cmu_isp0;
- unsigned int div_stat_cmu_isp1;
- unsigned int div_stat_isp2;
- unsigned char res45[0x2f4];
- unsigned int gate_bus_isp0;
- unsigned int gate_bus_isp1;
- unsigned int gate_bus_isp2;
- unsigned int gate_bus_isp3;
- unsigned char res46[0xf0];
- unsigned int gate_ip_isp0;
- unsigned int gate_ip_isp1;
- unsigned char res47[0xf8];
- unsigned int gate_sclk_isp;
- unsigned char res48[0x0c];
- unsigned int mcuisp_pwr_ctrl; /* 0x1001c910 */
- unsigned char res49[0x0ec];
- unsigned int clkout_cmu_isp;
- unsigned int clkout_cmu_isp_div_stat;
- unsigned char res50[0xf8];
- unsigned int cmu_isp_spare0;
- unsigned int cmu_isp_spare1;
- unsigned int cmu_isp_spare2;
- unsigned int cmu_isp_spare3;
- unsigned char res51[0x34e0];
- unsigned int cmu_isp_version;
- unsigned char res52[0x2c];
- unsigned int cpll_lock; /* 10020020 */
- unsigned char res53[0xc];
- unsigned int dpll_lock;
- unsigned char res54[0xc];
- unsigned int epll_lock;
- unsigned char res55[0xc];
- unsigned int rpll_lock;
- unsigned char res56[0xc];
- unsigned int ipll_lock;
- unsigned char res57[0xc];
- unsigned int spll_lock;
- unsigned char res58[0xc];
- unsigned int vpll_lock;
- unsigned char res59[0xc];
- unsigned int mpll_lock;
- unsigned char res60[0x8c];
- unsigned int cpll_con0; /* 10020120 */
- unsigned int cpll_con1;
- unsigned int dpll_con0;
- unsigned int dpll_con1;
- unsigned int epll_con0;
- unsigned int epll_con1;
- unsigned int epll_con2;
- unsigned char res601[0x4];
- unsigned int rpll_con0;
- unsigned int rpll_con1;
- unsigned int rpll_con2;
- unsigned char res602[0x4];
- unsigned int ipll_con0;
- unsigned int ipll_con1;
- unsigned char res61[0x8];
- unsigned int spll_con0;
- unsigned int spll_con1;
- unsigned char res62[0x8];
- unsigned int vpll_con0;
- unsigned int vpll_con1;
- unsigned char res63[0x8];
- unsigned int mpll_con0;
- unsigned int mpll_con1;
- unsigned char res64[0x78];
- unsigned int src_top0; /* 0x10020200 */
- unsigned int src_top1;
- unsigned int src_top2;
- unsigned int src_top3;
- unsigned int src_top4;
- unsigned int src_top5;
- unsigned int src_top6;
- unsigned int src_top7;
- unsigned char res65[0xc];
- unsigned int src_disp10; /* 0x1002022c */
- unsigned char res66[0x10];
- unsigned int src_mau;
- unsigned int src_fsys;
- unsigned char res67[0x8];
- unsigned int src_peric0;
- unsigned int src_peric1;
- unsigned char res68[0x18];
- unsigned int src_isp;
- unsigned char res69[0x0c];
- unsigned int src_top10;
- unsigned int src_top11;
- unsigned int src_top12;
- unsigned char res70[0x74];
- unsigned int src_mask_top0;
- unsigned int src_mask_top1;
- unsigned int src_mask_top2;
- unsigned char res71[0x10];
- unsigned int src_mask_top7;
- unsigned char res72[0xc];
- unsigned int src_mask_disp10; /* 0x1002032c */
- unsigned char res73[0x4];
- unsigned int src_mask_mau;
- unsigned char res74[0x8];
- unsigned int src_mask_fsys;
- unsigned char res75[0xc];
- unsigned int src_mask_peric0;
- unsigned int src_mask_peric1;
- unsigned char res76[0x18];
- unsigned int src_mask_isp;
- unsigned char res77[0x8c];
- unsigned int mux_stat_top0; /* 0x10020400 */
- unsigned int mux_stat_top1;
- unsigned int mux_stat_top2;
- unsigned int mux_stat_top3;
- unsigned int mux_stat_top4;
- unsigned int mux_stat_top5;
- unsigned int mux_stat_top6;
- unsigned int mux_stat_top7;
- unsigned char res78[0x60];
- unsigned int mux_stat_top10;
- unsigned int mux_stat_top11;
- unsigned int mux_stat_top12;
- unsigned char res79[0x74];
- unsigned int div_top0; /* 0x10020500 */
- unsigned int div_top1;
- unsigned int div_top2;
- unsigned char res80[0x20];
- unsigned int div_disp10;
- unsigned char res81[0x14];
- unsigned int div_mau;
- unsigned int div_fsys0;
- unsigned int div_fsys1;
- unsigned int div_fsys2;
- unsigned char res82[0x4];
- unsigned int div_peric0;
- unsigned int div_peric1;
- unsigned int div_peric2;
- unsigned int div_peric3;
- unsigned int div_peric4; /* 0x10020568 */
- unsigned char res83[0x14];
- unsigned int div_isp0;
- unsigned int div_isp1;
- unsigned char res84[0x8];
- unsigned int clkdiv2_ratio;
- unsigned char res850[0xc];
- unsigned int clkdiv4_ratio;
- unsigned char res85[0x5c];
- unsigned int div_stat_top0;
- unsigned int div_stat_top1;
- unsigned int div_stat_top2;
- unsigned char res86[0x20];
- unsigned int div_stat_disp10;
- unsigned char res87[0x14];
- unsigned int div_stat_mau; /* 0x10020644 */
- unsigned int div_stat_fsys0;
- unsigned int div_stat_fsys1;
- unsigned int div_stat_fsys2;
- unsigned char res88[0x4];
- unsigned int div_stat_peric0;
- unsigned int div_stat_peric1;
- unsigned int div_stat_peric2;
- unsigned int div_stat_peric3;
- unsigned int div_stat_peric4;
- unsigned char res89[0x14];
- unsigned int div_stat_isp0;
- unsigned int div_stat_isp1;
- unsigned char res90[0x8];
- unsigned int clkdiv2_stat0;
- unsigned char res91[0xc];
- unsigned int clkdiv4_stat;
- unsigned char res92[0x5c];
- unsigned int gate_bus_top; /* 0x10020700 */
- unsigned char res93[0xc];
- unsigned int gate_bus_gscl0;
- unsigned char res94[0xc];
- unsigned int gate_bus_gscl1;
- unsigned char res95[0x4];
- unsigned int gate_bus_disp1;
- unsigned char res96[0x4];
- unsigned int gate_bus_wcore;
- unsigned int gate_bus_mfc;
- unsigned int gate_bus_g3d;
- unsigned int gate_bus_gen;
- unsigned int gate_bus_fsys0;
- unsigned int gate_bus_fsys1;
- unsigned int gate_bus_fsys2;
- unsigned int gate_bus_mscl;
- unsigned int gate_bus_peric;
- unsigned int gate_bus_peric1;
- unsigned char res97[0x8];
- unsigned int gate_bus_peris0;
- unsigned int gate_bus_peris1; /* 0x10020764 */
- unsigned char res98[0x8];
- unsigned int gate_bus_noc;
- unsigned char res99[0xac];
- unsigned int gate_top_sclk_gscl;
- unsigned char res1000[0x4];
- unsigned int gate_top_sclk_disp1;
- unsigned char res100[0x10];
- unsigned int gate_top_sclk_mau;
- unsigned int gate_top_sclk_fsys;
- unsigned char res101[0xc];
- unsigned int gate_top_sclk_peric;
- unsigned char res102[0xc];
- unsigned int gate_top_sclk_cperi;
- unsigned char res103[0xc];
- unsigned int gate_top_sclk_isp;
- unsigned char res104[0x9c];
- unsigned int gate_ip_gscl0;
- unsigned char res105[0xc];
- unsigned int gate_ip_gscl1;
- unsigned char res106[0x4];
- unsigned int gate_ip_disp1;
- unsigned int gate_ip_mfc;
- unsigned int gate_ip_g3d;
- unsigned int gate_ip_gen; /* 0x10020934 */
- unsigned char res107[0xc];
- unsigned int gate_ip_fsys;
- unsigned char res108[0x8];
- unsigned int gate_ip_peric;
- unsigned char res109[0xc];
- unsigned int gate_ip_peris;
- unsigned char res110[0xc];
- unsigned int gate_ip_mscl;
- unsigned char res111[0xc];
- unsigned int gate_ip_block;
- unsigned char res112[0xc];
- unsigned int bypass;
- unsigned char res113[0x6c];
- unsigned int clkout_cmu_top;
- unsigned int clkout_cmu_top_div_stat;
- unsigned char res114[0xf8];
- unsigned int clkout_top_spare0;
- unsigned int clkout_top_spare1;
- unsigned int clkout_top_spare2;
- unsigned int clkout_top_spare3;
- unsigned char res115[0x34e0];
- unsigned int clkout_top_version;
- unsigned char res116[0xc01c];
- unsigned int bpll_lock; /* 0x10030010 */
- unsigned char res117[0xfc];
- unsigned int bpll_con0;
- unsigned int bpll_con1;
- unsigned char res118[0xe8];
- unsigned int src_cdrex;
- unsigned char res119[0x1fc];
- unsigned int mux_stat_cdrex;
- unsigned char res120[0xfc];
- unsigned int div_cdrex0;
- unsigned int div_cdrex1;
- unsigned char res121[0xf8];
- unsigned int div_stat_cdrex;
- unsigned char res1211[0xfc];
- unsigned int gate_bus_cdrex;
- unsigned int gate_bus_cdrex1;
- unsigned char res122[0x1f8];
- unsigned int gate_ip_cdrex;
- unsigned char res123[0x10];
- unsigned int dmc_freq_ctrl; /* 0x10030914 */
- unsigned char res124[0x4];
- unsigned int pause;
- unsigned int ddrphy_lock_ctrl;
- unsigned char res125[0xdc];
- unsigned int clkout_cmu_cdrex;
- unsigned int clkout_cmu_cdrex_div_stat;
- unsigned char res126[0x8];
- unsigned int lpddr3phy_ctrl;
- unsigned int lpddr3phy_con0;
- unsigned int lpddr3phy_con1;
- unsigned int lpddr3phy_con2;
- unsigned int lpddr3phy_con3;
- unsigned int lpddr3phy_con4;
- unsigned int lpddr3phy_con5; /* 0x10030a28 */
- unsigned int pll_div2_sel;
- unsigned char res127[0xd0];
- unsigned int cmu_cdrex_spare0;
- unsigned int cmu_cdrex_spare1;
- unsigned int cmu_cdrex_spare2;
- unsigned int cmu_cdrex_spare3;
- unsigned int cmu_cdrex_spare4;
- unsigned char res128[0x34dc];
- unsigned int cmu_cdrex_version; /* 0x10033ff0 */
- unsigned char res129[0x400c];
- unsigned int kpll_lock;
- unsigned char res130[0xfc];
- unsigned int kpll_con0;
- unsigned int kpll_con1;
- unsigned char res131[0xf8];
- unsigned int src_kfc;
- unsigned char res132[0x1fc];
- unsigned int mux_stat_kfc; /* 0x10038400 */
- unsigned char res133[0xfc];
- unsigned int div_kfc0;
- unsigned char res134[0xfc];
- unsigned int div_stat_kfc0;
- unsigned char res135[0xfc];
- unsigned int gate_bus_cpu_kfc;
- unsigned char res136[0xfc];
- unsigned int gate_sclk_cpu_kfc;
- unsigned char res137[0x1fc];
- unsigned int clkout_cmu_kfc;
- unsigned int clkout_cmu_kfc_div_stat; /* 0x10038a04 */
- unsigned char res138[0x5f8];
- unsigned int armclk_stopctrl_kfc;
- unsigned char res139[0x4];
- unsigned int armclk_ema_ctrl_kfc;
- unsigned int armclk_ema_status_kfc;
- unsigned char res140[0x10];
- unsigned int pwr_ctrl_kfc;
- unsigned int pwr_ctrl2_kfc;
- unsigned char res141[0xd8];
- unsigned int kpll_con0_l8;
- unsigned int kpll_con0_l7;
- unsigned int kpll_con0_l6;
- unsigned int kpll_con0_l5;
- unsigned int kpll_con0_l4;
- unsigned int kpll_con0_l3;
- unsigned int kpll_con0_l2;
- unsigned int kpll_con0_l1;
- unsigned int iem_control_kfc; /* 0x10039120 */
- unsigned char res142[0xdc];
- unsigned int kpll_con1_l8;
- unsigned int kpll_con1_l7;
- unsigned int kpll_con1_l6;
- unsigned int kpll_con1_l5;
- unsigned int kpll_con1_l4;
- unsigned int kpll_con1_l3;
- unsigned int kpll_con1_l2;
- unsigned int kpll_con1_l1;
- unsigned char res143[0xe0];
- unsigned int clkdiv_iem_l8_kfc; /* 0x10039300 */
- unsigned int clkdiv_iem_l7_kfc;
- unsigned int clkdiv_iem_l6_kfc;
- unsigned int clkdiv_iem_l5_kfc;
- unsigned int clkdiv_iem_l4_kfc;
- unsigned int clkdiv_iem_l3_kfc;
- unsigned int clkdiv_iem_l2_kfc;
- unsigned int clkdiv_iem_l1_kfc;
- unsigned char res144[0xe0];
- unsigned int l2_status_kfc;
- unsigned char res145[0xc];
- unsigned int cpu_status_kfc; /* 0x10039410 */
- unsigned char res146[0xc];
- unsigned int ptm_status_kfc;
- unsigned char res147[0xbdc];
- unsigned int cmu_kfc_spare0;
- unsigned int cmu_kfc_spare1;
- unsigned int cmu_kfc_spare2;
- unsigned int cmu_kfc_spare3;
- unsigned int cmu_kfc_spare4;
- unsigned char res148[0x1fdc];
- unsigned int cmu_kfc_version; /* 0x1003bff0 */
-};
-
-/* structure for epll configuration used in audio clock configuration */
-struct set_epll_con_val {
- unsigned int freq_out; /* frequency out */
- unsigned int en_lock_det; /* enable lock detect */
- unsigned int m_div; /* m divider value */
- unsigned int p_div; /* p divider value */
- unsigned int s_div; /* s divider value */
- unsigned int k_dsm; /* k value of delta signal modulator */
-};
-#endif
-
-#define MPLL_FOUT_SEL_SHIFT 4
-#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/
-#define TIMEOUT_EPLL_LOCK 1000
-
-#define AUDIO_0_RATIO_MASK 0x0f
-#define AUDIO_1_RATIO_MASK 0x0f
-
-#define AUDIO0_SEL_MASK 0xf
-#define AUDIO1_SEL_MASK 0xf
-
-#define CLK_SRC_SCLK_EPLL 0x7
-#define CLK_SRC_MOUT_EPLL (1<<12)
-#define AUDIO_CLKMUX_ASS (1<<0)
-
-/* CON0 bit-fields */
-#define EPLL_CON0_MDIV_MASK 0x1ff
-#define EPLL_CON0_PDIV_MASK 0x3f
-#define EPLL_CON0_SDIV_MASK 0x7
-#define EPLL_CON0_MDIV_SHIFT 16
-#define EPLL_CON0_PDIV_SHIFT 8
-#define EPLL_CON0_SDIV_SHIFT 0
-#define EPLL_CON0_LOCK_DET_EN_SHIFT 28
-#define EPLL_CON0_LOCK_DET_EN_MASK 1
-
-#define MPLL_FOUT_SEL_MASK 0x1
-#define BPLL_FOUT_SEL_SHIFT 0
-#define BPLL_FOUT_SEL_MASK 0x1
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _EXYNOS4_CPU_H
-#define _EXYNOS4_CPU_H
-
-#define DEVICE_NOT_AVAILABLE 0
-
-#define EXYNOS_CPU_NAME "Exynos"
-#define EXYNOS4_ADDR_BASE 0x10000000
-
-/* EXYNOS4 Common*/
-#define EXYNOS4_I2C_SPACING 0x10000
-
-#define EXYNOS4_GPIO_PART3_BASE 0x03860000
-#define EXYNOS4_PRO_ID 0x10000000
-#define EXYNOS4_SYSREG_BASE 0x10010000
-#define EXYNOS4_POWER_BASE 0x10020000
-#define EXYNOS4_SWRESET 0x10020400
-#define EXYNOS4_CLOCK_BASE 0x10030000
-#define EXYNOS4_SYSTIMER_BASE 0x10050000
-#define EXYNOS4_WATCHDOG_BASE 0x10060000
-#define EXYNOS4_TZPC_BASE 0x10110000
-#define EXYNOS4_DMC_CTRL_BASE 0x10400000
-#define EXYNOS4_MIU_BASE 0x10600000
-#define EXYNOS4_ACE_SFR_BASE 0x10830000
-#define EXYNOS4_GPIO_PART2_BASE 0x11000000
-#define EXYNOS4_GPIO_PART2_0 0x11000000 /* GPJ0 */
-#define EXYNOS4_GPIO_PART2_1 0x11000c00 /* GPX0 */
-#define EXYNOS4_GPIO_PART1_BASE 0x11400000
-#define EXYNOS4_FIMD_BASE 0x11C00000
-#define EXYNOS4_MIPI_DSIM_BASE 0x11C80000
-#define EXYNOS4_USBOTG_BASE 0x12480000
-#define EXYNOS4_MMC_BASE 0x12510000
-#define EXYNOS4_SROMC_BASE 0x12570000
-#define EXYNOS4_USB_HOST_EHCI_BASE 0x12580000
-#define EXYNOS4_USBPHY_BASE 0x125B0000
-#define EXYNOS4_UART_BASE 0x13800000
-#define EXYNOS4_I2C_BASE 0x13860000
-#define EXYNOS4_ADC_BASE 0x13910000
-#define EXYNOS4_SPI_BASE 0x13920000
-#define EXYNOS4_PWMTIMER_BASE 0x139D0000
-#define EXYNOS4_MODEM_BASE 0x13A00000
-#define EXYNOS4_USBPHY_CONTROL 0x10020704
-#define EXYNOS4_I2S_BASE 0xE2100000
-
-#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4_USB3PHY_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE
-
-/* EXYNOS4X12 */
-#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000
-#define EXYNOS4X12_PRO_ID 0x10000000
-#define EXYNOS4X12_SYSREG_BASE 0x10010000
-#define EXYNOS4X12_POWER_BASE 0x10020000
-#define EXYNOS4X12_SWRESET 0x10020400
-#define EXYNOS4X12_USBPHY_CONTROL 0x10020704
-#define EXYNOS4X12_CLOCK_BASE 0x10030000
-#define EXYNOS4X12_SYSTIMER_BASE 0x10050000
-#define EXYNOS4X12_WATCHDOG_BASE 0x10060000
-#define EXYNOS4X12_TZPC_BASE 0x10110000
-#define EXYNOS4X12_DMC_CTRL_BASE 0x10600000
-#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
-#define EXYNOS4X12_ACE_SFR_BASE 0x10830000
-#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000
-#define EXYNOS4X12_GPIO_PART2_0 0x11000000
-#define EXYNOS4X12_GPIO_PART2_1 0x11000040 /* GPK0 */
-#define EXYNOS4X12_GPIO_PART2_2 0x11000260 /* GPM0 */
-#define EXYNOS4X12_GPIO_PART2_3 0x11000c00 /* GPX0 */
-#define EXYNOS4X12_GPIO_PART1_BASE 0x11400000
-#define EXYNOS4X12_GPIO_PART1_0 0x11400000 /* GPA0 */
-#define EXYNOS4X12_GPIO_PART1_1 0x11400180 /* GPF0 */
-#define EXYNOS4X12_GPIO_PART1_2 0x11400240 /* GPJ0 */
-#define EXYNOS4X12_FIMD_BASE 0x11C00000
-#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000
-#define EXYNOS4X12_USBOTG_BASE 0x12480000
-#define EXYNOS4X12_MMC_BASE 0x12510000
-#define EXYNOS4X12_SROMC_BASE 0x12570000
-#define EXYNOS4X12_USB_HOST_EHCI_BASE 0x12580000
-#define EXYNOS4X12_USBPHY_BASE 0x125B0000
-#define EXYNOS4X12_UART_BASE 0x13800000
-#define EXYNOS4X12_I2C_BASE 0x13860000
-#define EXYNOS4X12_PWMTIMER_BASE 0x139D0000
-
-#define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_USB3PHY_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE
-
-/* EXYNOS5 */
-#define EXYNOS5_I2C_SPACING 0x10000
-
-#define EXYNOS5_AUDIOSS_BASE 0x03810000
-#define EXYNOS5_GPIO_PART8_BASE 0x03860000
-#define EXYNOS5_PRO_ID 0x10000000
-#define EXYNOS5_CLOCK_BASE 0x10010000
-#define EXYNOS5_POWER_BASE 0x10040000
-#define EXYNOS5_SWRESET 0x10040400
-#define EXYNOS5_SYSREG_BASE 0x10050000
-#define EXYNOS5_TZPC_BASE 0x10100000
-#define EXYNOS5_WATCHDOG_BASE 0x101D0000
-#define EXYNOS5_ACE_SFR_BASE 0x10830000
-#define EXYNOS5_DMC_PHY_BASE 0x10C00000
-#define EXYNOS5_GPIO_PART5_BASE 0x10D10000
-#define EXYNOS5_GPIO_PART6_BASE 0x10D10060
-#define EXYNOS5_GPIO_PART7_BASE 0x10D100C0
-#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
-#define EXYNOS5_GPIO_PART1_BASE 0x11400000
-#define EXYNOS5_GPIO_PART2_BASE 0x114002E0
-#define EXYNOS5_GPIO_PART3_BASE 0x11400C00
-#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
-#define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000
-#define EXYNOS5_USB3PHY_BASE 0x12100000
-#define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000
-#define EXYNOS5_USBPHY_BASE 0x12130000
-#define EXYNOS5_USBOTG_BASE 0x12140000
-#define EXYNOS5_MMC_BASE 0x12200000
-#define EXYNOS5_SROMC_BASE 0x12250000
-#define EXYNOS5_UART_BASE 0x12C00000
-#define EXYNOS5_I2C_BASE 0x12C60000
-#define EXYNOS5_SPI_BASE 0x12D20000
-#define EXYNOS5_I2S_BASE 0x12D60000
-#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
-#define EXYNOS5_SPI_ISP_BASE 0x131A0000
-#define EXYNOS5_GPIO_PART4_BASE 0x13400000
-#define EXYNOS5_FIMD_BASE 0x14400000
-#define EXYNOS5_DP_BASE 0x145B0000
-
-#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS5_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE
-
-/* EXYNOS5420 */
-#define EXYNOS5420_AUDIOSS_BASE 0x03810000
-#define EXYNOS5420_GPIO_PART6_BASE 0x03860000
-#define EXYNOS5420_PRO_ID 0x10000000
-#define EXYNOS5420_CLOCK_BASE 0x10010000
-#define EXYNOS5420_POWER_BASE 0x10040000
-#define EXYNOS5420_SWRESET 0x10040400
-#define EXYNOS5420_INFORM_BASE 0x10040800
-#define EXYNOS5420_SPARE_BASE 0x10040900
-#define EXYNOS5420_CPU_CONFIG_BASE 0x10042000
-#define EXYNOS5420_CPU_STATUS_BASE 0x10042004
-#define EXYNOS5420_SYSREG_BASE 0x10050000
-#define EXYNOS5420_TZPC_BASE 0x100E0000
-#define EXYNOS5420_WATCHDOG_BASE 0x101D0000
-#define EXYNOS5420_ACE_SFR_BASE 0x10830000
-#define EXYNOS5420_DMC_PHY_BASE 0x10C00000
-#define EXYNOS5420_DMC_CTRL_BASE 0x10C20000
-#define EXYNOS5420_DMC_TZASC_BASE 0x10D40000
-#define EXYNOS5420_USB_HOST_EHCI_BASE 0x12110000
-#define EXYNOS5420_MMC_BASE 0x12200000
-#define EXYNOS5420_SROMC_BASE 0x12250000
-#define EXYNOS5420_USB3PHY_BASE 0x12500000
-#define EXYNOS5420_UART_BASE 0x12C00000
-#define EXYNOS5420_I2C_BASE 0x12C60000
-#define EXYNOS5420_I2C_8910_BASE 0x12E00000
-#define EXYNOS5420_SPI_BASE 0x12D20000
-#define EXYNOS5420_I2S_BASE 0x12D60000
-#define EXYNOS5420_PWMTIMER_BASE 0x12DD0000
-#define EXYNOS5420_SPI_ISP_BASE 0x131A0000
-#define EXYNOS5420_GPIO_PART2_BASE 0x13400000
-#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00
-#define EXYNOS5420_GPIO_PART4_BASE 0x13410000
-#define EXYNOS5420_GPIO_PART5_BASE 0x14000000
-#define EXYNOS5420_GPIO_PART1_BASE 0x14010000
-#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000
-#define EXYNOS5420_DP_BASE 0x145B0000
-
-#define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS5420_FIMD_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS5420_ADC_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
-
-
-#ifndef __ASSEMBLY__
-#include <asm/io.h>
-/* CPU detection macros */
-extern unsigned int s5p_cpu_id;
-extern unsigned int s5p_cpu_rev;
-
-static inline int s5p_get_cpu_rev(void)
-{
- return s5p_cpu_rev;
-}
-
-static inline void s5p_set_cpu_id(void)
-{
- unsigned int pro_id = readl(EXYNOS4_PRO_ID);
- unsigned int cpu_id = (pro_id & 0x00FFF000) >> 12;
- unsigned int cpu_rev = pro_id & 0x000000FF;
-
- switch (cpu_id) {
- case 0x200:
- /* Exynos4210 EVT0 */
- s5p_cpu_id = 0x4210;
- s5p_cpu_rev = 0;
- break;
- case 0x210:
- /* Exynos4210 EVT1 */
- s5p_cpu_id = 0x4210;
- s5p_cpu_rev = cpu_rev;
- break;
- case 0x412:
- /* Exynos4412 */
- s5p_cpu_id = 0x4412;
- s5p_cpu_rev = cpu_rev;
- break;
- case 0x520:
- /* Exynos5250 */
- s5p_cpu_id = 0x5250;
- break;
- case 0x420:
- /* Exynos5420 */
- s5p_cpu_id = 0x5420;
- break;
- case 0x422:
- /*
- * Exynos5800 is a variant of Exynos5420
- * and has product id 0x5422
- */
- s5p_cpu_id = 0x5800;
- break;
- }
-}
-
-static inline char *s5p_get_cpu_name(void)
-{
- return EXYNOS_CPU_NAME;
-}
-
-#define IS_SAMSUNG_TYPE(type, id) \
-static inline int __attribute__((no_instrument_function)) cpu_is_##type(void) \
-{ \
- return (s5p_cpu_id >> 12) == id; \
-}
-
-IS_SAMSUNG_TYPE(exynos4, 0x4)
-IS_SAMSUNG_TYPE(exynos5, 0x5)
-
-#define IS_EXYNOS_TYPE(type, id) \
-static inline int __attribute__((no_instrument_function)) \
- proid_is_##type(void) \
-{ \
- return s5p_cpu_id == id; \
-}
-
-IS_EXYNOS_TYPE(exynos4210, 0x4210)
-IS_EXYNOS_TYPE(exynos4412, 0x4412)
-IS_EXYNOS_TYPE(exynos5250, 0x5250)
-IS_EXYNOS_TYPE(exynos5420, 0x5420)
-IS_EXYNOS_TYPE(exynos5800, 0x5800)
-
-#define SAMSUNG_BASE(device, base) \
-static inline unsigned int __attribute__((no_instrument_function)) \
- samsung_get_base_##device(void) \
-{ \
- if (cpu_is_exynos4()) { \
- if (proid_is_exynos4412()) \
- return EXYNOS4X12_##base; \
- return EXYNOS4_##base; \
- } else if (cpu_is_exynos5()) { \
- if (proid_is_exynos5420() || proid_is_exynos5800()) \
- return EXYNOS5420_##base; \
- return EXYNOS5_##base; \
- } \
- return 0; \
-}
-
-SAMSUNG_BASE(adc, ADC_BASE)
-SAMSUNG_BASE(clock, CLOCK_BASE)
-SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
-SAMSUNG_BASE(dp, DP_BASE)
-SAMSUNG_BASE(sysreg, SYSREG_BASE)
-SAMSUNG_BASE(fimd, FIMD_BASE)
-SAMSUNG_BASE(i2c, I2C_BASE)
-SAMSUNG_BASE(i2s, I2S_BASE)
-SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
-SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
-SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
-SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
-SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE)
-SAMSUNG_BASE(pro_id, PRO_ID)
-SAMSUNG_BASE(mmc, MMC_BASE)
-SAMSUNG_BASE(modem, MODEM_BASE)
-SAMSUNG_BASE(sromc, SROMC_BASE)
-SAMSUNG_BASE(swreset, SWRESET)
-SAMSUNG_BASE(timer, PWMTIMER_BASE)
-SAMSUNG_BASE(uart, UART_BASE)
-SAMSUNG_BASE(usb_phy, USBPHY_BASE)
-SAMSUNG_BASE(usb3_phy, USB3PHY_BASE)
-SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
-SAMSUNG_BASE(usb_xhci, USB_HOST_XHCI_BASE)
-SAMSUNG_BASE(usb_otg, USBOTG_BASE)
-SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
-SAMSUNG_BASE(power, POWER_BASE)
-SAMSUNG_BASE(spi, SPI_BASE)
-SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
-SAMSUNG_BASE(tzpc, TZPC_BASE)
-SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE)
-SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE)
-SAMSUNG_BASE(dmc_tzasc, DMC_TZASC_BASE)
-SAMSUNG_BASE(audio_ass, AUDIOSS_BASE)
-#endif
-
-#endif /* _EXYNOS4_CPU_H */
+++ /dev/null
-#ifndef __DMC_H__
-#define __DMC_H__
-
-#ifndef __ASSEMBLY__
-struct exynos4_dmc {
- unsigned int concontrol;
- unsigned int memcontrol;
- unsigned int memconfig0;
- unsigned int memconfig1;
- unsigned int directcmd;
- unsigned int prechconfig;
- unsigned int phycontrol0;
- unsigned int phycontrol1;
- unsigned int phycontrol2;
- unsigned int phycontrol3;
- unsigned int pwrdnconfig;
- unsigned char res1[0x4];
- unsigned int timingref;
- unsigned int timingrow;
- unsigned int timingdata;
- unsigned int timingpower;
- unsigned int phystatus;
- unsigned int phyzqcontrol;
- unsigned int chip0status;
- unsigned int chip1status;
- unsigned int arefstatus;
- unsigned int mrstatus;
- unsigned int phytest0;
- unsigned int phytest1;
- unsigned int qoscontrol0;
- unsigned int qosconfig0;
- unsigned int qoscontrol1;
- unsigned int qosconfig1;
- unsigned int qoscontrol2;
- unsigned int qosconfig2;
- unsigned int qoscontrol3;
- unsigned int qosconfig3;
- unsigned int qoscontrol4;
- unsigned int qosconfig4;
- unsigned int qoscontrol5;
- unsigned int qosconfig5;
- unsigned int qoscontrol6;
- unsigned int qosconfig6;
- unsigned int qoscontrol7;
- unsigned int qosconfig7;
- unsigned int qoscontrol8;
- unsigned int qosconfig8;
- unsigned int qoscontrol9;
- unsigned int qosconfig9;
- unsigned int qoscontrol10;
- unsigned int qosconfig10;
- unsigned int qoscontrol11;
- unsigned int qosconfig11;
- unsigned int qoscontrol12;
- unsigned int qosconfig12;
- unsigned int qoscontrol13;
- unsigned int qosconfig13;
- unsigned int qoscontrol14;
- unsigned int qosconfig14;
- unsigned int qoscontrol15;
- unsigned int qosconfig15;
- unsigned int qostimeout0;
- unsigned int qostimeout1;
- unsigned char res2[0x8];
- unsigned int ivcontrol;
- unsigned char res3[0x8];
- unsigned int perevconfig;
- unsigned char res4[0xDF00];
- unsigned int pmnc_ppc_a;
- unsigned char res5[0xC];
- unsigned int cntens_ppc_a;
- unsigned char res6[0xC];
- unsigned int cntenc_ppc_a;
- unsigned char res7[0xC];
- unsigned int intens_ppc_a;
- unsigned char res8[0xC];
- unsigned int intenc_ppc_a;
- unsigned char res9[0xC];
- unsigned int flag_ppc_a;
- unsigned char res10[0xAC];
- unsigned int ccnt_ppc_a;
- unsigned char res11[0xC];
- unsigned int pmcnt0_ppc_a;
- unsigned char res12[0xC];
- unsigned int pmcnt1_ppc_a;
- unsigned char res13[0xC];
- unsigned int pmcnt2_ppc_a;
- unsigned char res14[0xC];
- unsigned int pmcnt3_ppc_a;
- unsigned char res15[0xEBC];
- unsigned int pmnc_ppc_m;
- unsigned char res16[0xC];
- unsigned int cntens_ppc_m;
- unsigned char res17[0xC];
- unsigned int cntenc_ppc_m;
- unsigned char res18[0xC];
- unsigned int intens_ppc_m;
- unsigned char res19[0xC];
- unsigned int intenc_ppc_m;
- unsigned char res20[0xC];
- unsigned int flag_ppc_m;
- unsigned char res21[0xAC];
- unsigned int ccnt_ppc_m;
- unsigned char res22[0xC];
- unsigned int pmcnt0_ppc_m;
- unsigned char res23[0xC];
- unsigned int pmcnt1_ppc_m;
- unsigned char res24[0xC];
- unsigned int pmcnt2_ppc_m;
- unsigned char res25[0xC];
- unsigned int pmcnt3_ppc_m;
-};
-
-struct exynos5_dmc {
- unsigned int concontrol;
- unsigned int memcontrol;
- unsigned int memconfig0;
- unsigned int memconfig1;
- unsigned int directcmd;
- unsigned int prechconfig;
- unsigned int phycontrol0;
- unsigned char res1[0xc];
- unsigned int pwrdnconfig;
- unsigned int timingpzq;
- unsigned int timingref;
- unsigned int timingrow;
- unsigned int timingdata;
- unsigned int timingpower;
- unsigned int phystatus;
- unsigned char res2[0x4];
- unsigned int chipstatus_ch0;
- unsigned int chipstatus_ch1;
- unsigned char res3[0x4];
- unsigned int mrstatus;
- unsigned char res4[0x8];
- unsigned int qoscontrol0;
- unsigned char resr5[0x4];
- unsigned int qoscontrol1;
- unsigned char res6[0x4];
- unsigned int qoscontrol2;
- unsigned char res7[0x4];
- unsigned int qoscontrol3;
- unsigned char res8[0x4];
- unsigned int qoscontrol4;
- unsigned char res9[0x4];
- unsigned int qoscontrol5;
- unsigned char res10[0x4];
- unsigned int qoscontrol6;
- unsigned char res11[0x4];
- unsigned int qoscontrol7;
- unsigned char res12[0x4];
- unsigned int qoscontrol8;
- unsigned char res13[0x4];
- unsigned int qoscontrol9;
- unsigned char res14[0x4];
- unsigned int qoscontrol10;
- unsigned char res15[0x4];
- unsigned int qoscontrol11;
- unsigned char res16[0x4];
- unsigned int qoscontrol12;
- unsigned char res17[0x4];
- unsigned int qoscontrol13;
- unsigned char res18[0x4];
- unsigned int qoscontrol14;
- unsigned char res19[0x4];
- unsigned int qoscontrol15;
- unsigned char res20[0x14];
- unsigned int ivcontrol;
- unsigned int wrtra_config;
- unsigned int rdlvl_config;
- unsigned char res21[0x8];
- unsigned int brbrsvconfig;
- unsigned int brbqosconfig;
- unsigned int membaseconfig0;
- unsigned int membaseconfig1;
- unsigned char res22[0xc];
- unsigned int wrlvl_config;
- unsigned char res23[0xc];
- unsigned int perevcontrol;
- unsigned int perev0config;
- unsigned int perev1config;
- unsigned int perev2config;
- unsigned int perev3config;
- unsigned char res24[0xdebc];
- unsigned int pmnc_ppc_a;
- unsigned char res25[0xc];
- unsigned int cntens_ppc_a;
- unsigned char res26[0xc];
- unsigned int cntenc_ppc_a;
- unsigned char res27[0xc];
- unsigned int intens_ppc_a;
- unsigned char res28[0xc];
- unsigned int intenc_ppc_a;
- unsigned char res29[0xc];
- unsigned int flag_ppc_a;
- unsigned char res30[0xac];
- unsigned int ccnt_ppc_a;
- unsigned char res31[0xc];
- unsigned int pmcnt0_ppc_a;
- unsigned char res32[0xc];
- unsigned int pmcnt1_ppc_a;
- unsigned char res33[0xc];
- unsigned int pmcnt2_ppc_a;
- unsigned char res34[0xc];
- unsigned int pmcnt3_ppc_a;
-};
-
-struct exynos5420_dmc {
- unsigned int concontrol;
- unsigned int memcontrol;
- unsigned int cgcontrol;
- unsigned char res500[0x4];
- unsigned int directcmd;
- unsigned int prechconfig0;
- unsigned int phycontrol0;
- unsigned int prechconfig1;
- unsigned char res1[0x8];
- unsigned int pwrdnconfig;
- unsigned int timingpzq;
- unsigned int timingref;
- unsigned int timingrow0;
- unsigned int timingdata0;
- unsigned int timingpower0;
- unsigned int phystatus;
- unsigned int etctiming;
- unsigned int chipstatus;
- unsigned char res3[0x8];
- unsigned int mrstatus;
- unsigned char res4[0x8];
- unsigned int qoscontrol0;
- unsigned char resr5[0x4];
- unsigned int qoscontrol1;
- unsigned char res6[0x4];
- unsigned int qoscontrol2;
- unsigned char res7[0x4];
- unsigned int qoscontrol3;
- unsigned char res8[0x4];
- unsigned int qoscontrol4;
- unsigned char res9[0x4];
- unsigned int qoscontrol5;
- unsigned char res10[0x4];
- unsigned int qoscontrol6;
- unsigned char res11[0x4];
- unsigned int qoscontrol7;
- unsigned char res12[0x4];
- unsigned int qoscontrol8;
- unsigned char res13[0x4];
- unsigned int qoscontrol9;
- unsigned char res14[0x4];
- unsigned int qoscontrol10;
- unsigned char res15[0x4];
- unsigned int qoscontrol11;
- unsigned char res16[0x4];
- unsigned int qoscontrol12;
- unsigned char res17[0x4];
- unsigned int qoscontrol13;
- unsigned char res18[0x4];
- unsigned int qoscontrol14;
- unsigned char res19[0x4];
- unsigned int qoscontrol15;
- unsigned char res20[0x4];
- unsigned int timing_set_sw;
- unsigned int timingrow1;
- unsigned int timingdata1;
- unsigned int timingpower1;
- unsigned char res300[0x4];
- unsigned int wrtra_config;
- unsigned int rdlvl_config;
- unsigned char res21[0x4];
- unsigned int brbrsvcontrol;
- unsigned int brbrsvconfig;
- unsigned int brbqosconfig;
- unsigned char res301[0x14];
- unsigned int wrlvl_config0;
- unsigned int wrlvl_config1;
- unsigned int wrlvl_status;
- unsigned char res23[0x4];
- unsigned int ppcclockon;
- unsigned int perevconfig0;
- unsigned int perevconfig1;
- unsigned int perevconfig2;
- unsigned int perevconfig3;
- unsigned char res24[0xc];
- unsigned int control_io_rdata;
- unsigned char res240[0xc];
- unsigned int cacal_config0;
- unsigned int cacal_config1;
- unsigned int cacal_status;
- unsigned char res302[0xa4];
- unsigned int bp_control0;
- unsigned int bp_config0_r;
- unsigned int bp_config0_w;
- unsigned char res303[0x4];
- unsigned int bp_control1;
- unsigned int bp_config1_r;
- unsigned int bp_config1_w;
- unsigned char res304[0x4];
- unsigned int bp_control2;
- unsigned int bp_config2_r;
- unsigned int bp_config2_w;
- unsigned char res305[0x4];
- unsigned int bp_control3;
- unsigned int bp_config3_r;
- unsigned int bp_config3_w;
- unsigned char res306[0xddb4];
- unsigned int pmnc_ppc;
- unsigned char res25[0xc];
- unsigned int cntens_ppc;
- unsigned char res26[0xc];
- unsigned int cntenc_ppc;
- unsigned char res27[0xc];
- unsigned int intens_ppc;
- unsigned char res28[0xc];
- unsigned int intenc_ppc;
- unsigned char res29[0xc];
- unsigned int flag_ppc;
- unsigned char res30[0xac];
- unsigned int ccnt_ppc;
- unsigned char res31[0xc];
- unsigned int pmcnt0_ppc;
- unsigned char res32[0xc];
- unsigned int pmcnt1_ppc;
- unsigned char res33[0xc];
- unsigned int pmcnt2_ppc;
- unsigned char res34[0xc];
- unsigned int pmcnt3_ppc;
-};
-
-struct exynos5_phy_control {
- unsigned int phy_con0;
- unsigned int phy_con1;
- unsigned int phy_con2;
- unsigned int phy_con3;
- unsigned int phy_con4;
- unsigned char res1[4];
- unsigned int phy_con6;
- unsigned char res2[4];
- unsigned int phy_con8;
- unsigned int phy_con9;
- unsigned int phy_con10;
- unsigned char res3[4];
- unsigned int phy_con12;
- unsigned int phy_con13;
- unsigned int phy_con14;
- unsigned int phy_con15;
- unsigned int phy_con16;
- unsigned char res4[4];
- unsigned int phy_con17;
- unsigned int phy_con18;
- unsigned int phy_con19;
- unsigned int phy_con20;
- unsigned int phy_con21;
- unsigned int phy_con22;
- unsigned int phy_con23;
- unsigned int phy_con24;
- unsigned int phy_con25;
- unsigned int phy_con26;
- unsigned int phy_con27;
- unsigned int phy_con28;
- unsigned int phy_con29;
- unsigned int phy_con30;
- unsigned int phy_con31;
- unsigned int phy_con32;
- unsigned int phy_con33;
- unsigned int phy_con34;
- unsigned int phy_con35;
- unsigned int phy_con36;
- unsigned int phy_con37;
- unsigned int phy_con38;
- unsigned int phy_con39;
- unsigned int phy_con40;
- unsigned int phy_con41;
- unsigned int phy_con42;
-};
-
-struct exynos5420_phy_control {
- unsigned int phy_con0;
- unsigned int phy_con1;
- unsigned int phy_con2;
- unsigned int phy_con3;
- unsigned int phy_con4;
- unsigned int phy_con5;
- unsigned int phy_con6;
- unsigned char res2[0x4];
- unsigned int phy_con8;
- unsigned char res5[0x4];
- unsigned int phy_con10;
- unsigned int phy_con11;
- unsigned int phy_con12;
- unsigned int phy_con13;
- unsigned int phy_con14;
- unsigned int phy_con15;
- unsigned int phy_con16;
- unsigned char res4[0x4];
- unsigned int phy_con17;
- unsigned int phy_con18;
- unsigned int phy_con19;
- unsigned int phy_con20;
- unsigned int phy_con21;
- unsigned int phy_con22;
- unsigned int phy_con23;
- unsigned int phy_con24;
- unsigned int phy_con25;
- unsigned int phy_con26;
- unsigned int phy_con27;
- unsigned int phy_con28;
- unsigned int phy_con29;
- unsigned int phy_con30;
- unsigned int phy_con31;
- unsigned int phy_con32;
- unsigned int phy_con33;
- unsigned int phy_con34;
- unsigned char res6[0x8];
- unsigned int phy_con37;
- unsigned char res7[0x4];
- unsigned int phy_con39;
- unsigned int phy_con40;
- unsigned int phy_con41;
- unsigned int phy_con42;
-};
-
-struct exynos5420_tzasc {
- unsigned char res1[0xf00];
- unsigned int membaseconfig0;
- unsigned int membaseconfig1;
- unsigned char res2[0x8];
- unsigned int memconfig0;
- unsigned int memconfig1;
-};
-
-enum ddr_mode {
- DDR_MODE_DDR2,
- DDR_MODE_DDR3,
- DDR_MODE_LPDDR2,
- DDR_MODE_LPDDR3,
-
- DDR_MODE_COUNT,
-};
-
-enum mem_manuf {
- MEM_MANUF_AUTODETECT,
- MEM_MANUF_ELPIDA,
- MEM_MANUF_SAMSUNG,
-
- MEM_MANUF_COUNT,
-};
-
-/* CONCONTROL register fields */
-#define CONCONTROL_DFI_INIT_START_SHIFT 28
-#define CONCONTROL_RD_FETCH_SHIFT 12
-#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
-#define CONCONTROL_AREF_EN_SHIFT 5
-#define CONCONTROL_UPDATE_MODE (1 << 3)
-
-/* PRECHCONFIG register field */
-#define PRECHCONFIG_TP_CNT_SHIFT 24
-
-/* PWRDNCONFIG register field */
-#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0
-#define PWRDNCONFIG_DSREF_CYC_SHIFT 16
-
-/* PHY_CON0 register fields */
-#define PHY_CON0_T_WRRDCMD_SHIFT 17
-#define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
-#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
-#define PHY_CON0_CTRL_DDR_MODE_MASK 0x3
-
-/* PHY_CON1 register fields */
-#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0
-
-/* PHY_CON4 rgister fields */
-#define PHY_CON10_CTRL_OFFSETR3 (1 << 24)
-
-/* PHY_CON12 register fields */
-#define PHY_CON12_CTRL_START_POINT_SHIFT 24
-#define PHY_CON12_CTRL_INC_SHIFT 16
-#define PHY_CON12_CTRL_FORCE_SHIFT 8
-#define PHY_CON12_CTRL_START_SHIFT 6
-#define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT)
-#define PHY_CON12_CTRL_DLL_ON_SHIFT 5
-#define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
-#define PHY_CON12_CTRL_REF_SHIFT 1
-
-/* PHY_CON16 register fields */
-#define PHY_CON16_ZQ_MODE_DDS_SHIFT 24
-#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
-
-#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
-#define PHY_CON16_ZQ_MODE_TERM_MASK (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
-
-#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19)
-
-/* PHY_CON42 register fields */
-#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
-#define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
-
-#define PHY_CON42_CTRL_RDLAT_SHIFT 0
-#define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
-
-#endif
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_DP_H_
-#define __ASM_ARM_ARCH_DP_H_
-
-#ifndef __ASSEMBLY__
-
-struct exynos_dp {
- unsigned char res1[0x10];
- unsigned int tx_version;
- unsigned int tx_sw_reset;
- unsigned int func_en1;
- unsigned int func_en2;
- unsigned int video_ctl1;
- unsigned int video_ctl2;
- unsigned int video_ctl3;
- unsigned int video_ctl4;
- unsigned int color_blue_cb;
- unsigned int color_green_y;
- unsigned int color_red_cr;
- unsigned int video_ctl8;
- unsigned char res2[0x4];
- unsigned int video_ctl10;
- unsigned int total_ln_cfg_l;
- unsigned int total_ln_cfg_h;
- unsigned int active_ln_cfg_l;
- unsigned int active_ln_cfg_h;
- unsigned int vfp_cfg;
- unsigned int vsw_cfg;
- unsigned int vbp_cfg;
- unsigned int total_pix_cfg_l;
- unsigned int total_pix_cfg_h;
- unsigned int active_pix_cfg_l;
- unsigned int active_pix_cfg_h;
- unsigned int hfp_cfg_l;
- unsigned int hfp_cfg_h;
- unsigned int hsw_cfg_l;
- unsigned int hsw_cfg_h;
- unsigned int hbp_cfg_l;
- unsigned int hbp_cfg_h;
- unsigned int video_status;
- unsigned int total_ln_sta_l;
- unsigned int total_ln_sta_h;
- unsigned int active_ln_sta_l;
- unsigned int active_ln_sta_h;
-
- unsigned int vfp_sta;
- unsigned int vsw_sta;
- unsigned int vbp_sta;
-
- unsigned int total_pix_sta_l;
- unsigned int total_pix_sta_h;
- unsigned int active_pix_sta_l;
- unsigned int active_pix_sta_h;
-
- unsigned int hfp_sta_l;
- unsigned int hfp_sta_h;
- unsigned int hsw_sta_l;
- unsigned int hsw_sta_h;
- unsigned int hbp_sta_l;
- unsigned int hbp_sta_h;
-
- unsigned char res3[0x288];
-
- unsigned int lane_map;
- unsigned char res4[0x10];
- unsigned int analog_ctl1;
- unsigned int analog_ctl2;
- unsigned int analog_ctl3;
-
- unsigned int pll_filter_ctl1;
- unsigned int amp_tuning_ctl;
- unsigned char res5[0xc];
-
- unsigned int aux_hw_retry_ctl;
- unsigned char res6[0x2c];
- unsigned int int_state;
- unsigned int common_int_sta1;
- unsigned int common_int_sta2;
- unsigned int common_int_sta3;
- unsigned int common_int_sta4;
- unsigned char res7[0x8];
-
- unsigned int int_sta;
- unsigned char res8[0x1c];
- unsigned int int_ctl;
- unsigned char res9[0x200];
- unsigned int sys_ctl1;
- unsigned int sys_ctl2;
- unsigned int sys_ctl3;
- unsigned int sys_ctl4;
- unsigned int vid_ctl;
- unsigned char res10[0x2c];
- unsigned int pkt_send_ctl;
- unsigned char res[0x4];
- unsigned int hdcp_ctl;
- unsigned char res11[0x34];
- unsigned int link_bw_set;
-
- unsigned int lane_count_set;
- unsigned int training_ptn_set;
- unsigned int ln0_link_training_ctl;
- unsigned int ln1_link_training_ctl;
- unsigned int ln2_link_training_ctl;
- unsigned int ln3_link_training_ctl;
- unsigned int dn_spread_ctl;
- unsigned int hw_link_training_ctl;
- unsigned char res12[0x1c];
-
- unsigned int debug_ctl;
- unsigned int hpd_deglitch_l;
- unsigned int hpd_deglitch_h;
-
- unsigned char res13[0x14];
- unsigned int link_debug_ctl;
-
- unsigned char res14[0x1c];
-
- unsigned int m_vid0;
- unsigned int m_vid1;
- unsigned int m_vid2;
- unsigned int n_vid0;
- unsigned int n_vid1;
- unsigned int n_vid2;
- unsigned int m_vid_mon;
- unsigned int pll_ctl;
- unsigned int phy_pd;
- unsigned int phy_test;
- unsigned char res15[0x8];
-
- unsigned int video_fifo_thrd;
- unsigned char res16[0x8];
- unsigned int audio_margin;
-
- unsigned int dn_spread_ctl1;
- unsigned int dn_spread_ctl2;
- unsigned char res17[0x18];
- unsigned int m_cal_ctl;
- unsigned int m_vid_gen_filter_th;
- unsigned char res18[0x10];
- unsigned int m_aud_gen_filter_th;
- unsigned char res50[0x4];
-
- unsigned int aux_ch_sta;
- unsigned int aux_err_num;
- unsigned int aux_ch_defer_ctl;
- unsigned int aux_rx_comm;
- unsigned int buffer_data_ctl;
-
- unsigned int aux_ch_ctl1;
- unsigned int aux_addr_7_0;
- unsigned int aux_addr_15_8;
- unsigned int aux_addr_19_16;
- unsigned int aux_ch_ctl2;
- unsigned char res19[0x18];
- unsigned int buf_data0;
- unsigned char res20[0x3c];
-
- unsigned int soc_general_ctl;
- unsigned char res21[0x8c];
- unsigned int crc_con;
- unsigned int crc_result;
- unsigned char res22[0x8];
-
- unsigned int common_int_mask1;
- unsigned int common_int_mask2;
- unsigned int common_int_mask3;
- unsigned int common_int_mask4;
- unsigned int int_sta_mask1;
- unsigned int int_sta_mask2;
- unsigned int int_sta_mask3;
- unsigned int int_sta_mask4;
- unsigned int int_sta_mask;
- unsigned int crc_result2;
- unsigned int scrambler_reset_cnt;
-
- unsigned int pn_inv;
- unsigned int psr_config;
- unsigned int psr_command0;
- unsigned int psr_command1;
- unsigned int psr_crc_mon0;
- unsigned int psr_crc_mon1;
-
- unsigned char res24[0x30];
- unsigned int phy_bist_ctrl;
- unsigned char res25[0xc];
- unsigned int phy_ctrl;
- unsigned char res26[0x1c];
- unsigned int test_pattern_gen_en;
- unsigned int test_pattern_gen_ctrl;
-};
-
-#endif /* __ASSEMBLY__ */
-
-/* For DP VIDEO CTL 1 */
-#define VIDEO_EN_MASK (0x01 << 7)
-#define VIDEO_MUTE_MASK (0x01 << 6)
-
-/* For DP VIDEO CTL 4 */
-#define VIDEO_BIST_MASK (0x1 << 3)
-
-/* EXYNOS_DP_ANALOG_CTL_1 */
-#define SEL_BG_NEW_BANDGAP (0x0 << 6)
-#define SEL_BG_INTERNAL_RESISTOR (0x1 << 6)
-#define TX_TERMINAL_CTRL_73_OHM (0x0 << 4)
-#define TX_TERMINAL_CTRL_61_OHM (0x1 << 4)
-#define TX_TERMINAL_CTRL_50_OHM (0x2 << 4)
-#define TX_TERMINAL_CTRL_45_OHM (0x3 << 4)
-#define SWING_A_30PER_G_INCREASE (0x1 << 3)
-#define SWING_A_30PER_G_NORMAL (0x0 << 3)
-
-/* EXYNOS_DP_ANALOG_CTL_2 */
-#define CPREG_BLEED (0x1 << 4)
-#define SEL_24M (0x1 << 3)
-#define TX_DVDD_BIT_1_0000V (0x3 << 0)
-#define TX_DVDD_BIT_1_0625V (0x4 << 0)
-#define TX_DVDD_BIT_1_1250V (0x5 << 0)
-
-/* EXYNOS_DP_ANALOG_CTL_3 */
-#define DRIVE_DVDD_BIT_1_0000V (0x3 << 5)
-#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5)
-#define DRIVE_DVDD_BIT_1_1250V (0x5 << 5)
-#define SEL_CURRENT_DEFAULT (0x0 << 3)
-#define VCO_BIT_000_MICRO (0x0 << 0)
-#define VCO_BIT_200_MICRO (0x1 << 0)
-#define VCO_BIT_300_MICRO (0x2 << 0)
-#define VCO_BIT_400_MICRO (0x3 << 0)
-#define VCO_BIT_500_MICRO (0x4 << 0)
-#define VCO_BIT_600_MICRO (0x5 << 0)
-#define VCO_BIT_700_MICRO (0x6 << 0)
-#define VCO_BIT_900_MICRO (0x7 << 0)
-
-/* EXYNOS_DP_PLL_FILTER_CTL_1 */
-#define PD_RING_OSC (0x1 << 6)
-#define AUX_TERMINAL_CTRL_52_OHM (0x3 << 4)
-#define AUX_TERMINAL_CTRL_69_OHM (0x2 << 4)
-#define AUX_TERMINAL_CTRL_102_OHM (0x1 << 4)
-#define AUX_TERMINAL_CTRL_200_OHM (0x0 << 4)
-#define TX_CUR1_1X (0x0 << 2)
-#define TX_CUR1_2X (0x1 << 2)
-#define TX_CUR1_3X (0x2 << 2)
-#define TX_CUR_1_MA (0x0 << 0)
-#define TX_CUR_2_MA (0x1 << 0)
-#define TX_CUR_3_MA (0x2 << 0)
-#define TX_CUR_4_MA (0x3 << 0)
-
-/* EXYNOS_DP_PLL_FILTER_CTL_2 */
-#define CH3_AMP_0_MV (0x3 << 12)
-#define CH2_AMP_0_MV (0x3 << 8)
-#define CH1_AMP_0_MV (0x3 << 4)
-#define CH0_AMP_0_MV (0x3 << 0)
-
-/* EXYNOS_DP_PLL_CTL */
-#define DP_PLL_PD (0x1 << 7)
-#define DP_PLL_RESET (0x1 << 6)
-#define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4)
-#define DP_PLL_REF_BIT_1_1250V (0x5 << 0)
-#define DP_PLL_REF_BIT_1_2500V (0x7 << 0)
-
-/* EXYNOS_DP_INT_CTL */
-#define SOFT_INT_CTRL (0x1 << 2)
-#define INT_POL (0x1 << 0)
-
-/* DP TX SW RESET */
-#define RESET_DP_TX (0x01 << 0)
-
-/* DP FUNC_EN_1 */
-#define MASTER_VID_FUNC_EN_N (0x1 << 7)
-#define SLAVE_VID_FUNC_EN_N (0x1 << 5)
-#define AUD_FIFO_FUNC_EN_N (0x1 << 4)
-#define AUD_FUNC_EN_N (0x1 << 3)
-#define HDCP_FUNC_EN_N (0x1 << 2)
-#define CRC_FUNC_EN_N (0x1 << 1)
-#define SW_FUNC_EN_N (0x1 << 0)
-
-/* DP FUNC_EN_2 */
-#define SSC_FUNC_EN_N (0x1 << 7)
-#define AUX_FUNC_EN_N (0x1 << 2)
-#define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
-#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
-
-/* EXYNOS_DP_PHY_PD */
-#define PHY_PD (0x1 << 5)
-#define AUX_PD (0x1 << 4)
-#define CH3_PD (0x1 << 3)
-#define CH2_PD (0x1 << 2)
-#define CH1_PD (0x1 << 1)
-#define CH0_PD (0x1 << 0)
-
-/* EXYNOS_DP_COMMON_INT_STA_1 */
-#define VSYNC_DET (0x1 << 7)
-#define PLL_LOCK_CHG (0x1 << 6)
-#define SPDIF_ERR (0x1 << 5)
-#define SPDIF_UNSTBL (0x1 << 4)
-#define VID_FORMAT_CHG (0x1 << 3)
-#define AUD_CLK_CHG (0x1 << 2)
-#define VID_CLK_CHG (0x1 << 1)
-#define SW_INT (0x1 << 0)
-
-/* EXYNOS_DP_DEBUG_CTL */
-#define PLL_LOCK (0x1 << 4)
-#define F_PLL_LOCK (0x1 << 3)
-#define PLL_LOCK_CTRL (0x1 << 2)
-
-/* EXYNOS_DP_FUNC_EN_2 */
-#define SSC_FUNC_EN_N (0x1 << 7)
-#define AUX_FUNC_EN_N (0x1 << 2)
-#define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
-#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
-
-/* EXYNOS_DP_COMMON_INT_STA_4 */
-#define PSR_ACTIVE (0x1 << 7)
-#define PSR_INACTIVE (0x1 << 6)
-#define SPDIF_BI_PHASE_ERR (0x1 << 5)
-#define HOTPLUG_CHG (0x1 << 2)
-#define HPD_LOST (0x1 << 1)
-#define PLUG (0x1 << 0)
-
-/* EXYNOS_DP_INT_STA */
-#define INT_HPD (0x1 << 6)
-#define HW_TRAINING_FINISH (0x1 << 5)
-#define RPLY_RECEIV (0x1 << 1)
-#define AUX_ERR (0x1 << 0)
-
-/* EXYNOS_DP_SYS_CTL_3 */
-#define HPD_STATUS (0x1 << 6)
-#define F_HPD (0x1 << 5)
-#define HPD_CTRL (0x1 << 4)
-#define HDCP_RDY (0x1 << 3)
-#define STRM_VALID (0x1 << 2)
-#define F_VALID (0x1 << 1)
-#define VALID_CTRL (0x1 << 0)
-
-/* EXYNOS_DP_AUX_HW_RETRY_CTL */
-#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8)
-#define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3)
-#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3)
-#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3)
-#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3)
-#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3)
-#define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0)
-
-/* EXYNOS_DP_AUX_CH_DEFER_CTL */
-#define DEFER_CTRL_EN (0x1 << 7)
-#define DEFER_COUNT(x) (((x) & 0x7f) << 0)
-
-#define COMMON_INT_MASK_1 (0)
-#define COMMON_INT_MASK_2 (0)
-#define COMMON_INT_MASK_3 (0)
-#define COMMON_INT_MASK_4 (0)
-#define INT_STA_MASK (0)
-
-/* EXYNOS_DP_BUFFER_DATA_CTL */
-#define BUF_CLR (0x1 << 7)
-#define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0)
-
-/* EXYNOS_DP_AUX_ADDR_7_0 */
-#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
-
-/* EXYNOS_DP_AUX_ADDR_15_8 */
-#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
-
-/* EXYNOS_DP_AUX_ADDR_19_16 */
-#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
-
-/* EXYNOS_DP_AUX_CH_CTL_1 */
-#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4)
-#define AUX_TX_COMM_MASK (0xf << 0)
-#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3)
-#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3)
-#define AUX_TX_COMM_MOT (0x1 << 2)
-#define AUX_TX_COMM_WRITE (0x0 << 0)
-#define AUX_TX_COMM_READ (0x1 << 0)
-
-/* EXYNOS_DP_AUX_CH_CTL_2 */
-#define ADDR_ONLY (0x1 << 1)
-#define AUX_EN (0x1 << 0)
-
-/* EXYNOS_DP_AUX_CH_STA */
-#define AUX_BUSY (0x1 << 4)
-#define AUX_STATUS_MASK (0xf << 0)
-
-/* EXYNOS_DP_AUX_RX_COMM */
-#define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
-#define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
-
-/* EXYNOS_DP_PHY_TEST */
-#define MACRO_RST (0x1 << 5)
-#define CH1_TEST (0x1 << 1)
-#define CH0_TEST (0x1 << 0)
-
-/* EXYNOS_DP_TRAINING_PTN_SET */
-#define SCRAMBLER_TYPE (0x1 << 9)
-#define HW_LINK_TRAINING_PATTERN (0x1 << 8)
-#define SCRAMBLING_DISABLE (0x1 << 5)
-#define SCRAMBLING_ENABLE (0x0 << 5)
-#define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2)
-#define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2)
-#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2)
-#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2)
-#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0)
-#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0)
-#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0)
-#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0)
-
-/* EXYNOS_DP_TOTAL_LINE_CFG */
-#define TOTAL_LINE_CFG_L(x) ((x) & 0xff)
-#define TOTAL_LINE_CFG_H(x) ((((x) >> 8)) & 0xff)
-#define ACTIVE_LINE_CFG_L(x) ((x) & 0xff)
-#define ACTIVE_LINE_CFG_H(x) (((x) >> 8) & 0xff)
-#define TOTAL_PIXEL_CFG_L(x) ((x) & 0xff)
-#define TOTAL_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff)
-#define ACTIVE_PIXEL_CFG_L(x) ((x) & 0xff)
-#define ACTIVE_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff)
-
-#define H_F_PORCH_CFG_L(x) ((x) & 0xff)
-#define H_F_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
-#define H_SYNC_PORCH_CFG_L(x) ((x) & 0xff)
-#define H_SYNC_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
-#define H_B_PORCH_CFG_L(x) ((x) & 0xff)
-#define H_B_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
-
-/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
-#define MAX_PRE_EMPHASIS_REACH_0 (0x1 << 5)
-#define PRE_EMPHASIS_SET_0_SET(x) (((x) & 0x3) << 3)
-#define PRE_EMPHASIS_SET_0_GET(x) (((x) >> 3) & 0x3)
-#define PRE_EMPHASIS_SET_0_MASK (0x3 << 3)
-#define PRE_EMPHASIS_SET_0_SHIFT (3)
-#define PRE_EMPHASIS_SET_0_LEVEL_3 (0x3 << 3)
-#define PRE_EMPHASIS_SET_0_LEVEL_2 (0x2 << 3)
-#define PRE_EMPHASIS_SET_0_LEVEL_1 (0x1 << 3)
-#define PRE_EMPHASIS_SET_0_LEVEL_0 (0x0 << 3)
-#define MAX_DRIVE_CURRENT_REACH_0 (0x1 << 2)
-#define DRIVE_CURRENT_SET_0_MASK (0x3 << 0)
-#define DRIVE_CURRENT_SET_0_SET(x) (((x) & 0x3) << 0)
-#define DRIVE_CURRENT_SET_0_GET(x) (((x) >> 0) & 0x3)
-#define DRIVE_CURRENT_SET_0_LEVEL_3 (0x3 << 0)
-#define DRIVE_CURRENT_SET_0_LEVEL_2 (0x2 << 0)
-#define DRIVE_CURRENT_SET_0_LEVEL_1 (0x1 << 0)
-#define DRIVE_CURRENT_SET_0_LEVEL_0 (0x0 << 0)
-
-/* EXYNOS_DP_LN1_LINK_TRAINING_CTL */
-#define MAX_PRE_EMPHASIS_REACH_1 (0x1 << 5)
-#define PRE_EMPHASIS_SET_1_SET(x) (((x) & 0x3) << 3)
-#define PRE_EMPHASIS_SET_1_GET(x) (((x) >> 3) & 0x3)
-#define PRE_EMPHASIS_SET_1_MASK (0x3 << 3)
-#define PRE_EMPHASIS_SET_1_SHIFT (3)
-#define PRE_EMPHASIS_SET_1_LEVEL_3 (0x3 << 3)
-#define PRE_EMPHASIS_SET_1_LEVEL_2 (0x2 << 3)
-#define PRE_EMPHASIS_SET_1_LEVEL_1 (0x1 << 3)
-#define PRE_EMPHASIS_SET_1_LEVEL_0 (0x0 << 3)
-#define MAX_DRIVE_CURRENT_REACH_1 (0x1 << 2)
-#define DRIVE_CURRENT_SET_1_MASK (0x3 << 0)
-#define DRIVE_CURRENT_SET_1_SET(x) (((x) & 0x3) << 0)
-#define DRIVE_CURRENT_SET_1_GET(x) (((x) >> 0) & 0x3)
-#define DRIVE_CURRENT_SET_1_LEVEL_3 (0x3 << 0)
-#define DRIVE_CURRENT_SET_1_LEVEL_2 (0x2 << 0)
-#define DRIVE_CURRENT_SET_1_LEVEL_1 (0x1 << 0)
-#define DRIVE_CURRENT_SET_1_LEVEL_0 (0x0 << 0)
-
-/* EXYNOS_DP_LN2_LINK_TRAINING_CTL */
-#define MAX_PRE_EMPHASIS_REACH_2 (0x1 << 5)
-#define PRE_EMPHASIS_SET_2_SET(x) (((x) & 0x3) << 3)
-#define PRE_EMPHASIS_SET_2_GET(x) (((x) >> 3) & 0x3)
-#define PRE_EMPHASIS_SET_2_MASK (0x3 << 3)
-#define PRE_EMPHASIS_SET_2_SHIFT (3)
-#define PRE_EMPHASIS_SET_2_LEVEL_3 (0x3 << 3)
-#define PRE_EMPHASIS_SET_2_LEVEL_2 (0x2 << 3)
-#define PRE_EMPHASIS_SET_2_LEVEL_1 (0x1 << 3)
-#define PRE_EMPHASIS_SET_2_LEVEL_0 (0x0 << 3)
-#define MAX_DRIVE_CURRENT_REACH_2 (0x1 << 2)
-#define DRIVE_CURRENT_SET_2_MASK (0x3 << 0)
-#define DRIVE_CURRENT_SET_2_SET(x) (((x) & 0x3) << 0)
-#define DRIVE_CURRENT_SET_2_GET(x) (((x) >> 0) & 0x3)
-#define DRIVE_CURRENT_SET_2_LEVEL_3 (0x3 << 0)
-#define DRIVE_CURRENT_SET_2_LEVEL_2 (0x2 << 0)
-#define DRIVE_CURRENT_SET_2_LEVEL_1 (0x1 << 0)
-#define DRIVE_CURRENT_SET_2_LEVEL_0 (0x0 << 0)
-
-/* EXYNOS_DP_LN3_LINK_TRAINING_CTL */
-#define MAX_PRE_EMPHASIS_REACH_3 (0x1 << 5)
-#define PRE_EMPHASIS_SET_3_SET(x) (((x) & 0x3) << 3)
-#define PRE_EMPHASIS_SET_3_GET(x) (((x) >> 3) & 0x3)
-#define PRE_EMPHASIS_SET_3_MASK (0x3 << 3)
-#define PRE_EMPHASIS_SET_3_SHIFT (3)
-#define PRE_EMPHASIS_SET_3_LEVEL_3 (0x3 << 3)
-#define PRE_EMPHASIS_SET_3_LEVEL_2 (0x2 << 3)
-#define PRE_EMPHASIS_SET_3_LEVEL_1 (0x1 << 3)
-#define PRE_EMPHASIS_SET_3_LEVEL_0 (0x0 << 3)
-#define MAX_DRIVE_CURRENT_REACH_3 (0x1 << 2)
-#define DRIVE_CURRENT_SET_3_MASK (0x3 << 0)
-#define DRIVE_CURRENT_SET_3_SET(x) (((x) & 0x3) << 0)
-#define DRIVE_CURRENT_SET_3_GET(x) (((x) >> 0) & 0x3)
-#define DRIVE_CURRENT_SET_3_LEVEL_3 (0x3 << 0)
-#define DRIVE_CURRENT_SET_3_LEVEL_2 (0x2 << 0)
-#define DRIVE_CURRENT_SET_3_LEVEL_1 (0x1 << 0)
-#define DRIVE_CURRENT_SET_3_LEVEL_0 (0x0 << 0)
-
-/* EXYNOS_DP_VIDEO_CTL_10 */
-#define FORMAT_SEL (0x1 << 4)
-#define INTERACE_SCAN_CFG (0x1 << 2)
-#define INTERACE_SCAN_CFG_SHIFT (2)
-#define VSYNC_POLARITY_CFG (0x1 << 1)
-#define V_S_POLARITY_CFG_SHIFT (1)
-#define HSYNC_POLARITY_CFG (0x1 << 0)
-#define H_S_POLARITY_CFG_SHIFT (0)
-
-/* EXYNOS_DP_SOC_GENERAL_CTL */
-#define AUDIO_MODE_SPDIF_MODE (0x1 << 8)
-#define AUDIO_MODE_MASTER_MODE (0x0 << 8)
-#define MASTER_VIDEO_INTERLACE_EN (0x1 << 4)
-#define VIDEO_MASTER_CLK_SEL (0x1 << 2)
-#define VIDEO_MASTER_MODE_EN (0x1 << 1)
-#define VIDEO_MODE_MASK (0x1 << 0)
-#define VIDEO_MODE_SLAVE_MODE (0x1 << 0)
-#define VIDEO_MODE_MASTER_MODE (0x0 << 0)
-
-/* EXYNOS_DP_VIDEO_CTL_1 */
-#define VIDEO_EN (0x1 << 7)
-#define HDCP_VIDEO_MUTE (0x1 << 6)
-
-/* EXYNOS_DP_VIDEO_CTL_2 */
-#define IN_D_RANGE_MASK (0x1 << 7)
-#define IN_D_RANGE_SHIFT (7)
-#define IN_D_RANGE_CEA (0x1 << 7)
-#define IN_D_RANGE_VESA (0x0 << 7)
-#define IN_BPC_MASK (0x7 << 4)
-#define IN_BPC_SHIFT (4)
-#define IN_BPC_12_BITS (0x3 << 4)
-#define IN_BPC_10_BITS (0x2 << 4)
-#define IN_BPC_8_BITS (0x1 << 4)
-#define IN_BPC_6_BITS (0x0 << 4)
-#define IN_COLOR_F_MASK (0x3 << 0)
-#define IN_COLOR_F_SHIFT (0)
-#define IN_COLOR_F_YCBCR444 (0x2 << 0)
-#define IN_COLOR_F_YCBCR422 (0x1 << 0)
-#define IN_COLOR_F_RGB (0x0 << 0)
-
-/* EXYNOS_DP_VIDEO_CTL_3 */
-#define IN_YC_COEFFI_MASK (0x1 << 7)
-#define IN_YC_COEFFI_SHIFT (7)
-#define IN_YC_COEFFI_ITU709 (0x1 << 7)
-#define IN_YC_COEFFI_ITU601 (0x0 << 7)
-#define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4)
-#define VID_CHK_UPDATE_TYPE_SHIFT (4)
-#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4)
-#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4)
-
-/* EXYNOS_DP_TEST_PATTERN_GEN_EN */
-#define TEST_PATTERN_GEN_EN (0x1 << 0)
-#define TEST_PATTERN_GEN_DIS (0x0 << 0)
-
-/* EXYNOS_DP_TEST_PATTERN_GEN_CTRL */
-#define TEST_PATTERN_MODE_COLOR_SQUARE (0x3 << 0)
-#define TEST_PATTERN_MODE_BALCK_WHITE_V_LINES (0x2 << 0)
-#define TEST_PATTERN_MODE_COLOR_RAMP (0x1 << 0)
-
-/* EXYNOS_DP_VIDEO_CTL_4 */
-#define BIST_EN (0x1 << 3)
-#define BIST_WIDTH_MASK (0x1 << 2)
-#define BIST_WIDTH_BAR_32_PIXEL (0x0 << 2)
-#define BIST_WIDTH_BAR_64_PIXEL (0x1 << 2)
-#define BIST_TYPE_MASK (0x3 << 0)
-#define BIST_TYPE_COLOR_BAR (0x0 << 0)
-#define BIST_TYPE_WHITE_GRAY_BLACK_BAR (0x1 << 0)
-#define BIST_TYPE_MOBILE_WHITE_BAR (0x2 << 0)
-
-/* EXYNOS_DP_SYS_CTL_1 */
-#define DET_STA (0x1 << 2)
-#define FORCE_DET (0x1 << 1)
-#define DET_CTRL (0x1 << 0)
-
-/* EXYNOS_DP_SYS_CTL_2 */
-#define CHA_CRI(x) (((x) & 0xf) << 4)
-#define CHA_STA (0x1 << 2)
-#define FORCE_CHA (0x1 << 1)
-#define CHA_CTRL (0x1 << 0)
-
-/* EXYNOS_DP_SYS_CTL_3 */
-#define HPD_STATUS (0x1 << 6)
-#define F_HPD (0x1 << 5)
-#define HPD_CTRL (0x1 << 4)
-#define HDCP_RDY (0x1 << 3)
-#define STRM_VALID (0x1 << 2)
-#define F_VALID (0x1 << 1)
-#define VALID_CTRL (0x1 << 0)
-
-/* EXYNOS_DP_SYS_CTL_4 */
-#define FIX_M_AUD (0x1 << 4)
-#define ENHANCED (0x1 << 3)
-#define FIX_M_VID (0x1 << 2)
-#define M_VID_UPDATE_CTRL (0x3 << 0)
-
-/* EXYNOS_M_VID_X */
-#define M_VID0_CFG(x) ((x) & 0xff)
-#define M_VID1_CFG(x) (((x) >> 8) & 0xff)
-#define M_VID2_CFG(x) (((x) >> 16) & 0xff)
-
-/* EXYNOS_M_VID_X */
-#define N_VID0_CFG(x) ((x) & 0xff)
-#define N_VID1_CFG(x) (((x) >> 8) & 0xff)
-#define N_VID2_CFG(x) (((x) >> 16) & 0xff)
-
-/* DPCD_TRAINING_PATTERN_SET */
-#define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
-#define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
-#define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
-#define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
-#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
-
-/* Definition for DPCD Register */
-#define DPCD_DPCD_REV (0x0000)
-#define DPCD_MAX_LINK_RATE (0x0001)
-#define DPCD_MAX_LANE_COUNT (0x0002)
-#define DPCD_LINK_BW_SET (0x0100)
-#define DPCD_LANE_COUNT_SET (0x0101)
-#define DPCD_TRAINING_PATTERN_SET (0x0102)
-#define DPCD_TRAINING_LANE0_SET (0x0103)
-#define DPCD_LANE0_1_STATUS (0x0202)
-#define DPCD_LN_ALIGN_UPDATED (0x0204)
-#define DPCD_ADJUST_REQUEST_LANE0_1 (0x0206)
-#define DPCD_ADJUST_REQUEST_LANE2_3 (0x0207)
-#define DPCD_TEST_REQUEST (0x0218)
-#define DPCD_TEST_RESPONSE (0x0260)
-#define DPCD_TEST_EDID_CHECKSUM (0x0261)
-#define DPCD_SINK_POWER_STATE (0x0600)
-
-/* DPCD_TEST_REQUEST */
-#define DPCD_TEST_EDID_READ (0x1 << 2)
-
-/* DPCD_TEST_RESPONSE */
-#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
-
-/* DPCD_SINK_POWER_STATE */
-#define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
-#define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR (0x50)
-#define I2C_E_EDID_DEVICE_ADDR (0x30)
-#define EDID_BLOCK_LENGTH (0x80)
-#define EDID_HEADER_PATTERN (0x00)
-#define EDID_EXTENSION_FLAG (0x7e)
-#define EDID_CHECKSUM (0x7f)
-
-/* DPCD_LANE0_1_STATUS */
-#define DPCD_LANE1_SYMBOL_LOCKED (0x1 << 6)
-#define DPCD_LANE1_CHANNEL_EQ_DONE (0x1 << 5)
-#define DPCD_LANE1_CR_DONE (0x1 << 4)
-#define DPCD_LANE0_SYMBOL_LOCKED (0x1 << 2)
-#define DPCD_LANE0_CHANNEL_EQ_DONE (0x1 << 1)
-#define DPCD_LANE0_CR_DONE (0x1 << 0)
-
-/* DPCD_ADJUST_REQUEST_LANE0_1 */
-#define DPCD_PRE_EMPHASIS_LANE1_MASK (0x3 << 6)
-#define DPCD_PRE_EMPHASIS_LANE1(x) (((x) >> 6) & 0x3)
-#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_3 (0x3 << 6)
-#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_2 (0x2 << 6)
-#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_1 (0x1 << 6)
-#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_0 (0x0 << 6)
-#define DPCD_VOLTAGE_SWING_LANE1_MASK (0x3 << 4)
-#define DPCD_VOLTAGE_SWING_LANE1(x) (((x) >> 4) & 0x3)
-#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_3 (0x3 << 4)
-#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_2 (0x2 << 4)
-#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_1 (0x1 << 4)
-#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_0 (0x0 << 4)
-#define DPCD_PRE_EMPHASIS_LANE0_MASK (0x3 << 2)
-#define DPCD_PRE_EMPHASIS_LANE0(x) (((x) >> 2) & 0x3)
-#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_3 (0x3 << 2)
-#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_2 (0x2 << 2)
-#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_1 (0x1 << 2)
-#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_0 (0x0 << 2)
-#define DPCD_VOLTAGE_SWING_LANE0_MASK (0x3 << 0)
-#define DPCD_VOLTAGE_SWING_LANE0(x) (((x) >> 0) & 0x3)
-#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_3 (0x3 << 0)
-#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_2 (0x2 << 0)
-#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_1 (0x1 << 0)
-#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_0 (0x0 << 0)
-
-/* DPCD_ADJUST_REQUEST_LANE2_3 */
-#define DPCD_PRE_EMPHASIS_LANE2_MASK (0x3 << 6)
-#define DPCD_PRE_EMPHASIS_LANE2(x) (((x) >> 6) & 0x3)
-#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_3 (0x3 << 6)
-#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_2 (0x2 << 6)
-#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_1 (0x1 << 6)
-#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_0 (0x0 << 6)
-#define DPCD_VOLTAGE_SWING_LANE2_MASK (0x3 << 4)
-#define DPCD_VOLTAGE_SWING_LANE2(x) (((x) >> 4) & 0x3)
-#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_3 (0x3 << 4)
-#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_2 (0x2 << 4)
-#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_1 (0x1 << 4)
-#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_0 (0x0 << 4)
-#define DPCD_PRE_EMPHASIS_LANE3_MASK (0x3 << 2)
-#define DPCD_PRE_EMPHASIS_LANE3(x) (((x) >> 2) & 0x3)
-#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_3 (0x3 << 2)
-#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_2 (0x2 << 2)
-#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_1 (0x1 << 2)
-#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_0 (0x0 << 2)
-#define DPCD_VOLTAGE_SWING_LANE3_MASK (0x3 << 0)
-#define DPCD_VOLTAGE_SWING_LANE3(x) (((x) >> 0) & 0x3)
-#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_3 (0x3 << 0)
-#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_2 (0x2 << 0)
-#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_1 (0x1 << 0)
-#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_0 (0x0 << 0)
-
-/* DPCD_LANE_COUNT_SET */
-#define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
-#define DPCD_LN_COUNT_SET(x) ((x) & 0x1f)
-
-/* DPCD_LANE_ALIGN__STATUS_UPDATED */
-#define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
-#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
-#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
-
-/* DPCD_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_3 (0x3 << 3)
-#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_2 (0x2 << 3)
-#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_1 (0x1 << 3)
-#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 (0x0 << 3)
-#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_3 (0x3 << 0)
-#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_2 (0x2 << 0)
-#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_1 (0x1 << 0)
-#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0 (0x0 << 0)
-
-#define DPCD_REQ_ADJ_SWING (0x00)
-#define DPCD_REQ_ADJ_EMPHASIS (0x01)
-
-#define DP_LANE_STAT_CR_DONE (0x01 << 0)
-#define DP_LANE_STAT_CE_DONE (0x01 << 1)
-#define DP_LANE_STAT_SYM_LOCK (0x01 << 2)
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _DP_INFO_H
-#define _DP_INFO_H
-
-#define msleep(a) udelay(a * 1000)
-
-#define DP_TIMEOUT_LOOP_COUNT 100
-#define MAX_CR_LOOP 5
-#define MAX_EQ_LOOP 4
-
-#define EXYNOS_DP_SUCCESS 0
-
-enum {
- DP_DISABLE,
- DP_ENABLE,
-};
-
-struct edp_disp_info {
- char *name;
- unsigned int h_total;
- unsigned int h_res;
- unsigned int h_sync_width;
- unsigned int h_back_porch;
- unsigned int h_front_porch;
- unsigned int v_total;
- unsigned int v_res;
- unsigned int v_sync_width;
- unsigned int v_back_porch;
- unsigned int v_front_porch;
-
- unsigned int v_sync_rate;
-};
-
-struct edp_link_train_info {
- unsigned int lt_status;
-
- unsigned int ep_loop;
- unsigned int cr_loop[4];
-
-};
-
-struct edp_video_info {
- unsigned int master_mode;
- unsigned int bist_mode;
- unsigned int bist_pattern;
-
- unsigned int h_sync_polarity;
- unsigned int v_sync_polarity;
- unsigned int interlaced;
-
- unsigned int color_space;
- unsigned int dynamic_range;
- unsigned int ycbcr_coeff;
- unsigned int color_depth;
-};
-
-struct edp_device_info {
- struct edp_disp_info disp_info;
- struct edp_link_train_info lt_info;
- struct edp_video_info video_info;
-
- /*below info get from panel during training*/
- unsigned char lane_bw;
- unsigned char lane_cnt;
- unsigned char dpcd_rev;
- /*support enhanced frame cap */
- unsigned char dpcd_efc;
-};
-
-enum analog_power_block {
- AUX_BLOCK,
- CH0_BLOCK,
- CH1_BLOCK,
- CH2_BLOCK,
- CH3_BLOCK,
- ANALOG_TOTAL,
- POWER_ALL
-};
-
-enum pll_status {
- PLL_UNLOCKED = 0,
- PLL_LOCKED
-};
-
-enum {
- COLOR_RGB,
- COLOR_YCBCR422,
- COLOR_YCBCR444
-};
-
-enum {
- VESA,
- CEA
-};
-
-enum {
- COLOR_YCBCR601,
- COLOR_YCBCR709
-};
-
-enum {
- COLOR_6,
- COLOR_8,
- COLOR_10,
- COLOR_12
-};
-
-enum {
- DP_LANE_BW_1_62 = 0x06,
- DP_LANE_BW_2_70 = 0x0a,
-};
-
-enum {
- DP_LANE_CNT_1 = 1,
- DP_LANE_CNT_2 = 2,
- DP_LANE_CNT_4 = 4,
-};
-
-enum {
- DP_DPCD_REV_10 = 0x10,
- DP_DPCD_REV_11 = 0x11,
-};
-
-enum {
- DP_LT_NONE,
- DP_LT_START,
- DP_LT_CR,
- DP_LT_ET,
- DP_LT_FINISHED,
- DP_LT_FAIL,
-};
-
-enum {
- PRE_EMPHASIS_LEVEL_0,
- PRE_EMPHASIS_LEVEL_1,
- PRE_EMPHASIS_LEVEL_2,
- PRE_EMPHASIS_LEVEL_3,
-};
-
-enum {
- PRBS7,
- D10_2,
- TRAINING_PTN1,
- TRAINING_PTN2,
- DP_NONE
-};
-
-enum {
- VOLTAGE_LEVEL_0,
- VOLTAGE_LEVEL_1,
- VOLTAGE_LEVEL_2,
- VOLTAGE_LEVEL_3,
-};
-
-enum pattern_type {
- NO_PATTERN,
- COLOR_RAMP,
- BALCK_WHITE_V_LINES,
- COLOR_SQUARE,
- INVALID_PATTERN,
- COLORBAR_32,
- COLORBAR_64,
- WHITE_GRAY_BALCKBAR_32,
- WHITE_GRAY_BALCKBAR_64,
- MOBILE_WHITEBAR_32,
- MOBILE_WHITEBAR_64
-};
-
-enum {
- CALCULATED_M,
- REGISTER_M
-};
-
-enum {
- VIDEO_TIMING_FROM_CAPTURE,
- VIDEO_TIMING_FROM_REGISTER
-};
-
-
-struct exynos_dp_platform_data {
- struct edp_device_info *edp_dev_info;
-};
-
-#ifdef CONFIG_EXYNOS_DP
-unsigned int exynos_init_dp(void);
-#else
-unsigned int exynos_init_dp(void)
-{
- return 0;
-}
-#endif
-
-#endif /* _DP_INFO_H */
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: InKi Dae <inki.dae@samsung.com>
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_DSIM_H_
-#define __ASM_ARM_ARCH_DSIM_H_
-
-#ifndef __ASSEMBLY__
-
-struct exynos_mipi_dsim {
- unsigned int status;
- unsigned int swrst;
- unsigned int clkctrl;
- unsigned int timeout;
- unsigned int config;
- unsigned int escmode;
- unsigned int mdresol;
- unsigned int mvporch;
- unsigned int mhporch;
- unsigned int msync;
- unsigned int sdresol;
- unsigned int intsrc;
- unsigned int intmsk;
- unsigned int pkthdr;
- unsigned int payload;
- unsigned int rxfifo;
- unsigned int fifothld;
- unsigned int fifoctrl;
- unsigned int memacchr;
- unsigned int pllctrl;
- unsigned int plltmr;
- unsigned int phyacchr;
- unsigned int phyacchr1;
-};
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Bit Definitions
- */
-/* DSIM_STATUS */
-#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
-#define DSIM_STOP_STATE_CLK (1 << 8)
-#define DSIM_TX_READY_HS_CLK (1 << 10)
-#define DSIM_PLL_STABLE (1 << 31)
-
-/* DSIM_SWRST */
-#define DSIM_FUNCRST (1 << 16)
-#define DSIM_SWRST (1 << 0)
-
-/* EXYNOS_DSIM_TIMEOUT */
-#define DSIM_LPDR_TOUT_SHIFT (0)
-#define DSIM_BTA_TOUT_SHIFT (16)
-
-/* EXYNOS_DSIM_CLKCTRL */
-#define DSIM_LANE_ESC_CLKEN_SHIFT (19)
-#define DSIM_BYTE_CLKEN_SHIFT (24)
-#define DSIM_BYTE_CLK_SRC_SHIFT (25)
-#define DSIM_PLL_BYPASS_SHIFT (27)
-#define DSIM_ESC_CLKEN_SHIFT (28)
-#define DSIM_TX_REQUEST_HSCLK_SHIFT (31)
-#define DSIM_LANE_ESC_CLKEN(x) (((x) & 0x1f) << \
- DSIM_LANE_ESC_CLKEN_SHIFT)
-#define DSIM_BYTE_CLK_ENABLE (1 << DSIM_BYTE_CLKEN_SHIFT)
-#define DSIM_BYTE_CLK_DISABLE (0 << DSIM_BYTE_CLKEN_SHIFT)
-#define DSIM_PLL_BYPASS_EXTERNAL (1 << DSIM_PLL_BYPASS_SHIFT)
-#define DSIM_ESC_CLKEN_ENABLE (1 << DSIM_ESC_CLKEN_SHIFT)
-#define DSIM_ESC_CLKEN_DISABLE (0 << DSIM_ESC_CLKEN_SHIFT)
-
-/* EXYNOS_DSIM_CONFIG */
-#define DSIM_NUM_OF_DATALANE_SHIFT (5)
-#define DSIM_SUBPIX_SHIFT (8)
-#define DSIM_MAINPIX_SHIFT (12)
-#define DSIM_SUBVC_SHIFT (16)
-#define DSIM_MAINVC_SHIFT (18)
-#define DSIM_HSA_MODE_SHIFT (20)
-#define DSIM_HBP_MODE_SHIFT (21)
-#define DSIM_HFP_MODE_SHIFT (22)
-#define DSIM_HSE_MODE_SHIFT (23)
-#define DSIM_AUTO_MODE_SHIFT (24)
-#define DSIM_VIDEO_MODE_SHIFT (25)
-#define DSIM_BURST_MODE_SHIFT (26)
-#define DSIM_EOT_PACKET_SHIFT (28)
-#define DSIM_AUTO_FLUSH_SHIFT (29)
-#define DSIM_LANE_ENx(x) (((x) & 0x1f) << 0)
-
-#define DSIM_NUM_OF_DATA_LANE(x) ((x) << DSIM_NUM_OF_DATALANE_SHIFT)
-
-/* EXYNOS_DSIM_ESCMODE */
-#define DSIM_TX_LPDT_SHIFT (6)
-#define DSIM_CMD_LPDT_SHIFT (7)
-#define DSIM_TX_LPDT_LP (1 << DSIM_TX_LPDT_SHIFT)
-#define DSIM_CMD_LPDT_LP (1 << DSIM_CMD_LPDT_SHIFT)
-#define DSIM_STOP_STATE_CNT_SHIFT (21)
-#define DSIM_FORCE_STOP_STATE_SHIFT (20)
-
-/* EXYNOS_DSIM_MDRESOL */
-#define DSIM_MAIN_STAND_BY (1 << 31)
-#define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16)
-#define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0)
-
-/* EXYNOS_DSIM_MVPORCH */
-#define DSIM_CMD_ALLOW_SHIFT (28)
-#define DSIM_STABLE_VFP_SHIFT (16)
-#define DSIM_MAIN_VBP_SHIFT (0)
-#define DSIM_CMD_ALLOW_MASK (0xf << DSIM_CMD_ALLOW_SHIFT)
-#define DSIM_STABLE_VFP_MASK (0x7ff << DSIM_STABLE_VFP_SHIFT)
-#define DSIM_MAIN_VBP_MASK (0x7ff << DSIM_MAIN_VBP_SHIFT)
-
-/* EXYNOS_DSIM_MHPORCH */
-#define DSIM_MAIN_HFP_SHIFT (16)
-#define DSIM_MAIN_HBP_SHIFT (0)
-#define DSIM_MAIN_HFP_MASK ((0xffff) << DSIM_MAIN_HFP_SHIFT)
-#define DSIM_MAIN_HBP_MASK ((0xffff) << DSIM_MAIN_HBP_SHIFT)
-
-/* EXYNOS_DSIM_MSYNC */
-#define DSIM_MAIN_VSA_SHIFT (22)
-#define DSIM_MAIN_HSA_SHIFT (0)
-#define DSIM_MAIN_VSA_MASK ((0x3ff) << DSIM_MAIN_VSA_SHIFT)
-#define DSIM_MAIN_HSA_MASK ((0xffff) << DSIM_MAIN_HSA_SHIFT)
-
-/* EXYNOS_DSIM_SDRESOL */
-#define DSIM_SUB_STANDY_SHIFT (31)
-#define DSIM_SUB_VRESOL_SHIFT (16)
-#define DSIM_SUB_HRESOL_SHIFT (0)
-#define DSIM_SUB_STANDY_MASK ((0x1) << DSIM_SUB_STANDY_SHIFT)
-#define DSIM_SUB_VRESOL_MASK ((0x7ff) << DSIM_SUB_VRESOL_SHIFT)
-#define DSIM_SUB_HRESOL_MASK ((0x7ff) << DSIM_SUB_HRESOL_SHIFT)
-
-/* EXYNOS_DSIM_INTSRC */
-#define INTSRC_FRAME_DONE (1 << 24)
-#define INTSRC_PLL_STABLE (1 << 31)
-#define INTSRC_SWRST_RELEASE (1 << 30)
-
-/* EXYNOS_DSIM_INTMSK */
-#define INTMSK_FRAME_DONE (1 << 24)
-
-/* EXYNOS_DSIM_FIFOCTRL */
-#define SFR_HEADER_EMPTY (1 << 22)
-
-/* EXYNOS_DSIM_PKTHDR */
-#define DSIM_PKTHDR_DI(x) (((x) & 0x3f) << 0)
-#define DSIM_PKTHDR_DAT0(x) ((x) << 8)
-#define DSIM_PKTHDR_DAT1(x) ((x) << 16)
-
-/* EXYNOS_DSIM_PHYACCHR */
-#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
-#define DSIM_AFC_CTL_SHIFT (5)
-#define DSIM_AFC_EN (1 << 14)
-
-/* EXYNOS_DSIM_PHYACCHR1 */
-#define DSIM_DPDN_SWAP_DATA_SHIFT (0)
-
-/* EXYNOS_DSIM_PLLCTRL */
-#define DSIM_SCALER_SHIFT (1)
-#define DSIM_MAIN_SHIFT (4)
-#define DSIM_PREDIV_SHIFT (13)
-#define DSIM_PRECTRL_SHIFT (20)
-#define DSIM_PLL_EN_SHIFT (23)
-#define DSIM_FREQ_BAND_SHIFT (24)
-#define DSIM_ZEROCTRL_SHIFT (28)
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2012 SAMSUNG Electronics
- * Jaehoon Chung <jh80.chung@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define DWMCI_CLKSEL 0x09C
-#define DWMCI_SET_SAMPLE_CLK(x) (x)
-#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
-#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
-
-#define EMMCP_MPSBEGIN0 0x1200
-#define EMMCP_SEND0 0x1204
-#define EMMCP_CTRL0 0x120C
-
-#define MPSCTRL_SECURE_READ_BIT (0x1<<7)
-#define MPSCTRL_SECURE_WRITE_BIT (0x1<<6)
-#define MPSCTRL_NON_SECURE_READ_BIT (0x1<<5)
-#define MPSCTRL_NON_SECURE_WRITE_BIT (0x1<<4)
-#define MPSCTRL_USE_FUSE_KEY (0x1<<3)
-#define MPSCTRL_ECB_MODE (0x1<<2)
-#define MPSCTRL_ENCRYPTION (0x1<<1)
-#define MPSCTRL_VALID (0x1<<0)
-
-/* CLKSEL Register */
-#define DWMCI_DIVRATIO_BIT 24
-#define DWMCI_DIVRATIO_MASK 0x7
-
-#ifdef CONFIG_OF_CONTROL
-int exynos_dwmmc_init(const void *blob);
-#endif
-int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel);
+++ /dev/null
-/*
- * SAMSUNG EXYNOS USB HOST EHCI Controller
- *
- * Copyright (C) 2012 Samsung Electronics Co.Ltd
- * Vivek Gautam <gautam.vivek@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_EHCI_H__
-#define __ASM_ARM_ARCH_EHCI_H__
-
-#define CLK_24MHZ 5
-
-#define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0)
-#define PHYPWR_NORMAL_MASK_PHY1 (0x7 << 6)
-#define PHYPWR_NORMAL_MASK_HSIC0 (0x7 << 9)
-#define PHYPWR_NORMAL_MASK_HSIC1 (0x7 << 12)
-#define RSTCON_HOSTPHY_SWRST (0xf << 3)
-#define RSTCON_SWRST (0x1 << 0)
-
-#define HOST_CTRL0_PHYSWRSTALL (1 << 31)
-#define HOST_CTRL0_COMMONON_N (1 << 9)
-#define HOST_CTRL0_SIDDQ (1 << 6)
-#define HOST_CTRL0_FORCESLEEP (1 << 5)
-#define HOST_CTRL0_FORCESUSPEND (1 << 4)
-#define HOST_CTRL0_WORDINTERFACE (1 << 3)
-#define HOST_CTRL0_UTMISWRST (1 << 2)
-#define HOST_CTRL0_LINKSWRST (1 << 1)
-#define HOST_CTRL0_PHYSWRST (1 << 0)
-
-#define HOST_CTRL0_FSEL_MASK (7 << 16)
-
-#define EHCICTRL_ENAINCRXALIGN (1 << 29)
-#define EHCICTRL_ENAINCR4 (1 << 28)
-#define EHCICTRL_ENAINCR8 (1 << 27)
-#define EHCICTRL_ENAINCR16 (1 << 26)
-
-#define HSIC_CTRL_REFCLKSEL (0x2)
-#define HSIC_CTRL_REFCLKSEL_MASK (0x3)
-#define HSIC_CTRL_REFCLKSEL_SHIFT (23)
-
-#define HSIC_CTRL_REFCLKDIV_12 (0x24)
-#define HSIC_CTRL_REFCLKDIV_MASK (0x7f)
-#define HSIC_CTRL_REFCLKDIV_SHIFT (16)
-
-#define HSIC_CTRL_SIDDQ (0x1 << 6)
-#define HSIC_CTRL_FORCESLEEP (0x1 << 5)
-#define HSIC_CTRL_FORCESUSPEND (0x1 << 4)
-#define HSIC_CTRL_UTMISWRST (0x1 << 2)
-#define HSIC_CTRL_PHYSWRST (0x1 << 0)
-
-/* Register map for PHY control */
-struct exynos_usb_phy {
- unsigned int usbphyctrl0;
- unsigned int usbphytune0;
- unsigned int reserved1[2];
- unsigned int hsicphyctrl1;
- unsigned int hsicphytune1;
- unsigned int reserved2[2];
- unsigned int hsicphyctrl2;
- unsigned int hsicphytune2;
- unsigned int reserved3[2];
- unsigned int ehcictrl;
- unsigned int ohcictrl;
- unsigned int usbotgsys;
- unsigned int reserved4;
- unsigned int usbotgtune;
-};
-
-struct exynos4412_usb_phy {
- unsigned int usbphyctrl;
- unsigned int usbphyclk;
- unsigned int usbphyrstcon;
-};
-
-/* Switch on the VBUS power. */
-int board_usb_vbus_init(void);
-
-#endif /* __ASM_ARM_ARCH_EHCI_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2012 Samsung Electronics
- * Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_FB_H_
-#define __ASM_ARM_ARCH_FB_H_
-
-#ifndef __ASSEMBLY__
-struct exynos_fb {
- unsigned int vidcon0;
- unsigned int vidcon1;
- unsigned int vidcon2;
- unsigned int vidcon3;
- unsigned int vidtcon0;
- unsigned int vidtcon1;
- unsigned int vidtcon2;
- unsigned int vidtcon3;
- unsigned int wincon0;
- unsigned int wincon1;
- unsigned int wincon2;
- unsigned int wincon3;
- unsigned int wincon4;
-
- unsigned int winshmap;
- unsigned int res1;
-
- unsigned int winchmap2;
- unsigned int vidosd0a;
- unsigned int vidosd0b;
- unsigned int vidosd0c;
- unsigned int res2;
-
- unsigned int vidosd1a;
- unsigned int vidosd1b;
- unsigned int vidosd1c;
- unsigned int vidosd1d;
-
- unsigned int vidosd2a;
- unsigned int vidosd2b;
- unsigned int vidosd2c;
- unsigned int vidosd2d;
-
- unsigned int vidosd3a;
- unsigned int vidosd3b;
- unsigned int vidosd3c;
- unsigned int res3;
-
- unsigned int vidosd4a;
- unsigned int vidosd4b;
- unsigned int vidosd4c;
- unsigned int res4[5];
-
- unsigned int vidw00add0b0;
- unsigned int vidw00add0b1;
- unsigned int vidw01add0b0;
- unsigned int vidw01add0b1;
-
- unsigned int vidw02add0b0;
- unsigned int vidw02add0b1;
- unsigned int vidw03add0b0;
- unsigned int vidw03add0b1;
- unsigned int vidw04add0b0;
- unsigned int vidw04add0b1;
- unsigned int res5[2];
-
- unsigned int vidw00add1b0;
- unsigned int vidw00add1b1;
- unsigned int vidw01add1b0;
- unsigned int vidw01add1b1;
-
- unsigned int vidw02add1b0;
- unsigned int vidw02add1b1;
- unsigned int vidw03add1b0;
- unsigned int vidw03add1b1;
-
- unsigned int vidw04add1b0;
- unsigned int vidw04add1b1;
- unsigned int res7[2];
-
- unsigned int vidw00add2;
- unsigned int vidw01add2;
- unsigned int vidw02add2;
- unsigned int vidw03add2;
- unsigned int vidw04add2;
- unsigned int res8[7];
-
- unsigned int vidintcon0;
- unsigned int vidintcon1;
- unsigned int res9[1];
-
- unsigned int w1keycon0;
- unsigned int w1keycon1;
- unsigned int w2keycon0;
- unsigned int w2keycon1;
- unsigned int w3keycon0;
- unsigned int w3keycon1;
- unsigned int w4keycon0;
- unsigned int w4keycon1;
-
- unsigned int w1keyalpha;
- unsigned int w2keyalpha;
- unsigned int w3keyalpha;
- unsigned int w4keyalpha;
-
- unsigned int dithmode;
- unsigned int res10[2];
-
- unsigned int win0map;
- unsigned int win1map;
- unsigned int win2map;
- unsigned int win3map;
- unsigned int win4map;
- unsigned int res11[1];
-
- unsigned int wpalcon_h;
- unsigned int wpalcon_l;
-
- unsigned int trigcon;
- unsigned int res12[2];
-
- unsigned int i80ifcona0;
- unsigned int i80ifcona1;
- unsigned int i80ifconb0;
- unsigned int i80ifconb1;
-
- unsigned int colorgaincon;
- unsigned int res13[2];
-
- unsigned int ldi_cmdcon0;
- unsigned int ldi_cmdcon1;
- unsigned int res14[1];
-
- /* To be updated */
-
- unsigned char res15[156];
- unsigned int dualrgb;
- unsigned char res16[16];
- unsigned int dp_mie_clkcon;
-};
-#endif
-
-/* LCD IF register offset */
-#define EXYNOS4_LCD_IF_BASE_OFFSET 0x0
-#define EXYNOS5_LCD_IF_BASE_OFFSET 0x20000
-
-static inline unsigned int exynos_fimd_get_base_offset(void)
-{
- if (cpu_is_exynos5())
- return EXYNOS5_LCD_IF_BASE_OFFSET;
- else
- return EXYNOS4_LCD_IF_BASE_OFFSET;
-}
-
-/*
- * Register offsets
-*/
-#define EXYNOS_WINCON(x) (x * 0x04)
-#define EXYNOS_VIDOSD(x) (x * 0x10)
-#define EXYNOS_BUFFER_OFFSET(x) (x * 0x08)
-#define EXYNOS_BUFFER_SIZE(x) (x * 0x04)
-
-/*
- * Bit Definitions
-*/
-
-/* VIDCON0 */
-#define EXYNOS_VIDCON0_DSI_DISABLE (0 << 30)
-#define EXYNOS_VIDCON0_DSI_ENABLE (1 << 30)
-#define EXYNOS_VIDCON0_SCAN_PROGRESSIVE (0 << 29)
-#define EXYNOS_VIDCON0_SCAN_INTERLACE (1 << 29)
-#define EXYNOS_VIDCON0_SCAN_MASK (1 << 29)
-#define EXYNOS_VIDCON0_VIDOUT_RGB (0 << 26)
-#define EXYNOS_VIDCON0_VIDOUT_ITU (1 << 26)
-#define EXYNOS_VIDCON0_VIDOUT_I80LDI0 (2 << 26)
-#define EXYNOS_VIDCON0_VIDOUT_I80LDI1 (3 << 26)
-#define EXYNOS_VIDCON0_VIDOUT_WB_RGB (4 << 26)
-#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI0 (6 << 26)
-#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI1 (7 << 26)
-#define EXYNOS_VIDCON0_VIDOUT_MASK (7 << 26)
-#define EXYNOS_VIDCON0_PNRMODE_RGB_P (0 << 17)
-#define EXYNOS_VIDCON0_PNRMODE_BGR_P (1 << 17)
-#define EXYNOS_VIDCON0_PNRMODE_RGB_S (2 << 17)
-#define EXYNOS_VIDCON0_PNRMODE_BGR_S (3 << 17)
-#define EXYNOS_VIDCON0_PNRMODE_MASK (3 << 17)
-#define EXYNOS_VIDCON0_PNRMODE_SHIFT (17)
-#define EXYNOS_VIDCON0_CLKVALUP_ALWAYS (0 << 16)
-#define EXYNOS_VIDCON0_CLKVALUP_START_FRAME (1 << 16)
-#define EXYNOS_VIDCON0_CLKVALUP_MASK (1 << 16)
-#define EXYNOS_VIDCON0_CLKVAL_F(x) (((x) & 0xff) << 6)
-#define EXYNOS_VIDCON0_VCLKEN_NORMAL (0 << 5)
-#define EXYNOS_VIDCON0_VCLKEN_FREERUN (1 << 5)
-#define EXYNOS_VIDCON0_VCLKEN_MASK (1 << 5)
-#define EXYNOS_VIDCON0_CLKDIR_DIRECTED (0 << 4)
-#define EXYNOS_VIDCON0_CLKDIR_DIVIDED (1 << 4)
-#define EXYNOS_VIDCON0_CLKDIR_MASK (1 << 4)
-#define EXYNOS_VIDCON0_CLKSEL_HCLK (0 << 2)
-#define EXYNOS_VIDCON0_CLKSEL_SCLK (1 << 2)
-#define EXYNOS_VIDCON0_CLKSEL_MASK (1 << 2)
-#define EXYNOS_VIDCON0_ENVID_ENABLE (1 << 1)
-#define EXYNOS_VIDCON0_ENVID_DISABLE (0 << 1)
-#define EXYNOS_VIDCON0_ENVID_F_ENABLE (1 << 0)
-#define EXYNOS_VIDCON0_ENVID_F_DISABLE (0 << 0)
-
-/* VIDCON1 */
-#define EXYNOS_VIDCON1_IVCLK_FALLING_EDGE (0 << 7)
-#define EXYNOS_VIDCON1_IVCLK_RISING_EDGE (1 << 7)
-#define EXYNOS_VIDCON1_IHSYNC_NORMAL (0 << 6)
-#define EXYNOS_VIDCON1_IHSYNC_INVERT (1 << 6)
-#define EXYNOS_VIDCON1_IVSYNC_NORMAL (0 << 5)
-#define EXYNOS_VIDCON1_IVSYNC_INVERT (1 << 5)
-#define EXYNOS_VIDCON1_IVDEN_NORMAL (0 << 4)
-#define EXYNOS_VIDCON1_IVDEN_INVERT (1 << 4)
-
-/* VIDCON2 */
-#define EXYNOS_VIDCON2_EN601_DISABLE (0 << 23)
-#define EXYNOS_VIDCON2_EN601_ENABLE (1 << 23)
-#define EXYNOS_VIDCON2_EN601_MASK (1 << 23)
-#define EXYNOS_VIDCON2_WB_DISABLE (0 << 15)
-#define EXYNOS_VIDCON2_WB_ENABLE (1 << 15)
-#define EXYNOS_VIDCON2_WB_MASK (1 << 15)
-#define EXYNOS_VIDCON2_TVFORMATSEL_HW (0 << 14)
-#define EXYNOS_VIDCON2_TVFORMATSEL_SW (1 << 14)
-#define EXYNOS_VIDCON2_TVFORMATSEL_MASK (1 << 14)
-#define EXYNOS_VIDCON2_TVFORMATSEL_YUV422 (1 << 12)
-#define EXYNOS_VIDCON2_TVFORMATSEL_YUV444 (2 << 12)
-#define EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK (3 << 12)
-#define EXYNOS_VIDCON2_ORGYUV_YCBCR (0 << 8)
-#define EXYNOS_VIDCON2_ORGYUV_CBCRY (1 << 8)
-#define EXYNOS_VIDCON2_ORGYUV_MASK (1 << 8)
-#define EXYNOS_VIDCON2_YUVORD_CBCR (0 << 7)
-#define EXYNOS_VIDCON2_YUVORD_CRCB (1 << 7)
-#define EXYNOS_VIDCON2_YUVORD_MASK (1 << 7)
-
-/* PRTCON */
-#define EXYNOS_PRTCON_UPDATABLE (0 << 11)
-#define EXYNOS_PRTCON_PROTECT (1 << 11)
-
-/* VIDTCON0 */
-#define EXYNOS_VIDTCON0_VBPDE(x) (((x) & 0xff) << 24)
-#define EXYNOS_VIDTCON0_VBPD(x) (((x) & 0xff) << 16)
-#define EXYNOS_VIDTCON0_VFPD(x) (((x) & 0xff) << 8)
-#define EXYNOS_VIDTCON0_VSPW(x) (((x) & 0xff) << 0)
-
-/* VIDTCON1 */
-#define EXYNOS_VIDTCON1_VFPDE(x) (((x) & 0xff) << 24)
-#define EXYNOS_VIDTCON1_HBPD(x) (((x) & 0xff) << 16)
-#define EXYNOS_VIDTCON1_HFPD(x) (((x) & 0xff) << 8)
-#define EXYNOS_VIDTCON1_HSPW(x) (((x) & 0xff) << 0)
-
-/* VIDTCON2 */
-#define EXYNOS_VIDTCON2_LINEVAL(x) (((x) & 0x7ff) << 11)
-#define EXYNOS_VIDTCON2_HOZVAL(x) (((x) & 0x7ff) << 0)
-#define EXYNOS_VIDTCON2_LINEVAL_E(x) ((((x) & 0x800) >> 11) << 23)
-#define EXYNOS_VIDTCON2_HOZVAL_E(x) ((((x) & 0x800) >> 11) << 22)
-
-/* Window 0~4 Control - WINCONx */
-#define EXYNOS_WINCON_DATAPATH_DMA (0 << 22)
-#define EXYNOS_WINCON_DATAPATH_LOCAL (1 << 22)
-#define EXYNOS_WINCON_DATAPATH_MASK (1 << 22)
-#define EXYNOS_WINCON_BUFSEL_0 (0 << 20)
-#define EXYNOS_WINCON_BUFSEL_1 (1 << 20)
-#define EXYNOS_WINCON_BUFSEL_MASK (1 << 20)
-#define EXYNOS_WINCON_BUFSEL_SHIFT (20)
-#define EXYNOS_WINCON_BUFAUTO_DISABLE (0 << 19)
-#define EXYNOS_WINCON_BUFAUTO_ENABLE (1 << 19)
-#define EXYNOS_WINCON_BUFAUTO_MASK (1 << 19)
-#define EXYNOS_WINCON_BITSWP_DISABLE (0 << 18)
-#define EXYNOS_WINCON_BITSWP_ENABLE (1 << 18)
-#define EXYNOS_WINCON_BITSWP_SHIFT (18)
-#define EXYNOS_WINCON_BYTESWP_DISABLE (0 << 17)
-#define EXYNOS_WINCON_BYTESWP_ENABLE (1 << 17)
-#define EXYNOS_WINCON_BYTESWP_SHIFT (17)
-#define EXYNOS_WINCON_HAWSWP_DISABLE (0 << 16)
-#define EXYNOS_WINCON_HAWSWP_ENABLE (1 << 16)
-#define EXYNOS_WINCON_HAWSWP_SHIFT (16)
-#define EXYNOS_WINCON_WSWP_DISABLE (0 << 15)
-#define EXYNOS_WINCON_WSWP_ENABLE (1 << 15)
-#define EXYNOS_WINCON_WSWP_SHIFT (15)
-#define EXYNOS_WINCON_INRGB_RGB (0 << 13)
-#define EXYNOS_WINCON_INRGB_YUV (1 << 13)
-#define EXYNOS_WINCON_INRGB_MASK (1 << 13)
-#define EXYNOS_WINCON_BURSTLEN_16WORD (0 << 9)
-#define EXYNOS_WINCON_BURSTLEN_8WORD (1 << 9)
-#define EXYNOS_WINCON_BURSTLEN_4WORD (2 << 9)
-#define EXYNOS_WINCON_BURSTLEN_MASK (3 << 9)
-#define EXYNOS_WINCON_ALPHA_MULTI_DISABLE (0 << 7)
-#define EXYNOS_WINCON_ALPHA_MULTI_ENABLE (1 << 7)
-#define EXYNOS_WINCON_BLD_PLANE (0 << 6)
-#define EXYNOS_WINCON_BLD_PIXEL (1 << 6)
-#define EXYNOS_WINCON_BLD_MASK (1 << 6)
-#define EXYNOS_WINCON_BPPMODE_1BPP (0 << 2)
-#define EXYNOS_WINCON_BPPMODE_2BPP (1 << 2)
-#define EXYNOS_WINCON_BPPMODE_4BPP (2 << 2)
-#define EXYNOS_WINCON_BPPMODE_8BPP_PAL (3 << 2)
-#define EXYNOS_WINCON_BPPMODE_8BPP (4 << 2)
-#define EXYNOS_WINCON_BPPMODE_16BPP_565 (5 << 2)
-#define EXYNOS_WINCON_BPPMODE_16BPP_A555 (6 << 2)
-#define EXYNOS_WINCON_BPPMODE_18BPP_666 (8 << 2)
-#define EXYNOS_WINCON_BPPMODE_18BPP_A665 (9 << 2)
-#define EXYNOS_WINCON_BPPMODE_24BPP_888 (0xb << 2)
-#define EXYNOS_WINCON_BPPMODE_24BPP_A887 (0xc << 2)
-#define EXYNOS_WINCON_BPPMODE_32BPP (0xd << 2)
-#define EXYNOS_WINCON_BPPMODE_16BPP_A444 (0xe << 2)
-#define EXYNOS_WINCON_BPPMODE_15BPP_555 (0xf << 2)
-#define EXYNOS_WINCON_BPPMODE_MASK (0xf << 2)
-#define EXYNOS_WINCON_BPPMODE_SHIFT (2)
-#define EXYNOS_WINCON_ALPHA0_SEL (0 << 1)
-#define EXYNOS_WINCON_ALPHA1_SEL (1 << 1)
-#define EXYNOS_WINCON_ALPHA_SEL_MASK (1 << 1)
-#define EXYNOS_WINCON_ENWIN_DISABLE (0 << 0)
-#define EXYNOS_WINCON_ENWIN_ENABLE (1 << 0)
-
-/* WINCON1 special */
-#define EXYNOS_WINCON1_VP_DISABLE (0 << 24)
-#define EXYNOS_WINCON1_VP_ENABLE (1 << 24)
-#define EXYNOS_WINCON1_LOCALSEL_FIMC1 (0 << 23)
-#define EXYNOS_WINCON1_LOCALSEL_VP (1 << 23)
-#define EXYNOS_WINCON1_LOCALSEL_MASK (1 << 23)
-
-/* WINSHMAP */
-#define EXYNOS_WINSHMAP_PROTECT(x) (((x) & 0x1f) << 10)
-#define EXYNOS_WINSHMAP_CH_ENABLE(x) (1 << (x))
-#define EXYNOS_WINSHMAP_CH_DISABLE(x) (1 << (x))
-#define EXYNOS_WINSHMAP_LOCAL_ENABLE(x) (0x20 << (x))
-#define EXYNOS_WINSHMAP_LOCAL_DISABLE(x) (0x20 << (x))
-
-/* VIDOSDxA, VIDOSDxB */
-#define EXYNOS_VIDOSD_LEFT_X(x) (((x) & 0x7ff) << 11)
-#define EXYNOS_VIDOSD_TOP_Y(x) (((x) & 0x7ff) << 0)
-#define EXYNOS_VIDOSD_RIGHT_X(x) (((x) & 0x7ff) << 11)
-#define EXYNOS_VIDOSD_BOTTOM_Y(x) (((x) & 0x7ff) << 0)
-#define EXYNOS_VIDOSD_RIGHT_X_E(x) (((x) & 0x1) << 23)
-#define EXYNOS_VIDOSD_BOTTOM_Y_E(x) (((x) & 0x1) << 22)
-
-/* VIDOSD0C, VIDOSDxD */
-#define EXYNOS_VIDOSD_SIZE(x) (((x) & 0xffffff) << 0)
-
-/* VIDOSDxC (1~4) */
-#define EXYNOS_VIDOSD_ALPHA0_R(x) (((x) & 0xf) << 20)
-#define EXYNOS_VIDOSD_ALPHA0_G(x) (((x) & 0xf) << 16)
-#define EXYNOS_VIDOSD_ALPHA0_B(x) (((x) & 0xf) << 12)
-#define EXYNOS_VIDOSD_ALPHA1_R(x) (((x) & 0xf) << 8)
-#define EXYNOS_VIDOSD_ALPHA1_G(x) (((x) & 0xf) << 4)
-#define EXYNOS_VIDOSD_ALPHA1_B(x) (((x) & 0xf) << 0)
-#define EXYNOS_VIDOSD_ALPHA0_SHIFT (12)
-#define EXYNOS_VIDOSD_ALPHA1_SHIFT (0)
-
-/* Start Address */
-#define EXYNOS_VIDADDR_START_VBANK(x) (((x) & 0xff) << 24)
-#define EXYNOS_VIDADDR_START_VBASEU(x) (((x) & 0xffffff) << 0)
-
-/* End Address */
-#define EXYNOS_VIDADDR_END_VBASEL(x) (((x) & 0xffffff) << 0)
-
-/* Buffer Size */
-#define EXYNOS_VIDADDR_OFFSIZE(x) (((x) & 0x1fff) << 13)
-#define EXYNOS_VIDADDR_PAGEWIDTH(x) (((x) & 0x1fff) << 0)
-#define EXYNOS_VIDADDR_OFFSIZE_E(x) ((((x) & 0x2000) >> 13) << 27)
-#define EXYNOS_VIDADDR_PAGEWIDTH_E(x) ((((x) & 0x2000) >> 13) << 26)
-
-/* WIN Color Map */
-#define EXYNOS_WINMAP_COLOR(x) ((x) & 0xffffff)
-
-/* VIDINTCON0 */
-#define EXYNOS_VIDINTCON0_SYSMAINCON_DISABLE (0 << 19)
-#define EXYNOS_VIDINTCON0_SYSMAINCON_ENABLE (1 << 19)
-#define EXYNOS_VIDINTCON0_SYSSUBCON_DISABLE (0 << 18)
-#define EXYNOS_VIDINTCON0_SYSSUBCON_ENABLE (1 << 18)
-#define EXYNOS_VIDINTCON0_SYSIFDONE_DISABLE (0 << 17)
-#define EXYNOS_VIDINTCON0_SYSIFDONE_ENABLE (1 << 17)
-#define EXYNOS_VIDINTCON0_FRAMESEL0_BACK (0 << 15)
-#define EXYNOS_VIDINTCON0_FRAMESEL0_VSYNC (1 << 15)
-#define EXYNOS_VIDINTCON0_FRAMESEL0_ACTIVE (2 << 15)
-#define EXYNOS_VIDINTCON0_FRAMESEL0_FRONT (3 << 15)
-#define EXYNOS_VIDINTCON0_FRAMESEL0_MASK (3 << 15)
-#define EXYNOS_VIDINTCON0_FRAMESEL1_NONE (0 << 13)
-#define EXYNOS_VIDINTCON0_FRAMESEL1_BACK (1 << 13)
-#define EXYNOS_VIDINTCON0_FRAMESEL1_VSYNC (2 << 13)
-#define EXYNOS_VIDINTCON0_FRAMESEL1_FRONT (3 << 13)
-#define EXYNOS_VIDINTCON0_INTFRMEN_DISABLE (0 << 12)
-#define EXYNOS_VIDINTCON0_INTFRMEN_ENABLE (1 << 12)
-#define EXYNOS_VIDINTCON0_FIFOSEL_WIN4 (1 << 11)
-#define EXYNOS_VIDINTCON0_FIFOSEL_WIN3 (1 << 10)
-#define EXYNOS_VIDINTCON0_FIFOSEL_WIN2 (1 << 9)
-#define EXYNOS_VIDINTCON0_FIFOSEL_WIN1 (1 << 6)
-#define EXYNOS_VIDINTCON0_FIFOSEL_WIN0 (1 << 5)
-#define EXYNOS_VIDINTCON0_FIFOSEL_ALL (0x73 << 5)
-#define EXYNOS_VIDINTCON0_FIFOSEL_MASK (0x73 << 5)
-#define EXYNOS_VIDINTCON0_FIFOLEVEL_25 (0 << 2)
-#define EXYNOS_VIDINTCON0_FIFOLEVEL_50 (1 << 2)
-#define EXYNOS_VIDINTCON0_FIFOLEVEL_75 (2 << 2)
-#define EXYNOS_VIDINTCON0_FIFOLEVEL_EMPTY (3 << 2)
-#define EXYNOS_VIDINTCON0_FIFOLEVEL_FULL (4 << 2)
-#define EXYNOS_VIDINTCON0_FIFOLEVEL_MASK (7 << 2)
-#define EXYNOS_VIDINTCON0_INTFIFO_DISABLE (0 << 1)
-#define EXYNOS_VIDINTCON0_INTFIFO_ENABLE (1 << 1)
-#define EXYNOS_VIDINTCON0_INT_DISABLE (0 << 0)
-#define EXYNOS_VIDINTCON0_INT_ENABLE (1 << 0)
-#define EXYNOS_VIDINTCON0_INT_MASK (1 << 0)
-
-/* VIDINTCON1 */
-#define EXYNOS_VIDINTCON1_INTVPPEND (1 << 5)
-#define EXYNOS_VIDINTCON1_INTI80PEND (1 << 2)
-#define EXYNOS_VIDINTCON1_INTFRMPEND (1 << 1)
-#define EXYNOS_VIDINTCON1_INTFIFOPEND (1 << 0)
-
-/* WINMAP */
-#define EXYNOS_WINMAP_ENABLE (1 << 24)
-
-/* WxKEYCON0 (1~4) */
-#define EXYNOS_KEYCON0_KEYBLEN_DISABLE (0 << 26)
-#define EXYNOS_KEYCON0_KEYBLEN_ENABLE (1 << 26)
-#define EXYNOS_KEYCON0_KEY_DISABLE (0 << 25)
-#define EXYNOS_KEYCON0_KEY_ENABLE (1 << 25)
-#define EXYNOS_KEYCON0_DIRCON_MATCH_FG (0 << 24)
-#define EXYNOS_KEYCON0_DIRCON_MATCH_BG (1 << 24)
-#define EXYNOS_KEYCON0_COMPKEY(x) (((x) & 0xffffff) << 0)
-
-/* WxKEYCON1 (1~4) */
-#define EXYNOS_KEYCON1_COLVAL(x) (((x) & 0xffffff) << 0)
-
-/* DUALRGB */
-#define EXYNOS_DUALRGB_BYPASS_SINGLE (0x00 << 0)
-#define EXYNOS_DUALRGB_BYPASS_DUAL (0x01 << 0)
-#define EXYNOS_DUALRGB_MIE_DUAL (0x10 << 0)
-#define EXYNOS_DUALRGB_MIE_SINGLE (0x11 << 0)
-#define EXYNOS_DUALRGB_LINESPLIT (0x0 << 2)
-#define EXYNOS_DUALRGB_FRAMESPLIT (0x1 << 2)
-#define EXYNOS_DUALRGB_SUB_CNT(x) ((x & 0xfff) << 4)
-#define EXYNOS_DUALRGB_VDEN_EN_DISABLE (0x0 << 16)
-#define EXYNOS_DUALRGB_VDEN_EN_ENABLE (0x1 << 16)
-#define EXYNOS_DUALRGB_MAIN_CNT(x) ((x & 0xfff) << 18)
-
-/* I80IFCONA0 and I80IFCONA1 */
-#define EXYNOS_LCD_CS_SETUP(x) (((x) & 0xf) << 16)
-#define EXYNOS_LCD_WR_SETUP(x) (((x) & 0xf) << 12)
-#define EXYNOS_LCD_WR_ACT(x) (((x) & 0xf) << 8)
-#define EXYNOS_LCD_WR_HOLD(x) (((x) & 0xf) << 4)
-#define EXYNOS_RSPOL_LOW (0 << 2)
-#define EXYNOS_RSPOL_HIGH (1 << 2)
-#define EXYNOS_I80IFEN_DISABLE (0 << 0)
-#define EXYNOS_I80IFEN_ENABLE (1 << 0)
-
-/* TRIGCON */
-#define EXYNOS_I80SOFT_TRIG_EN (1 << 0)
-#define EXYNOS_I80START_TRIG (1 << 1)
-#define EXYNOS_I80STATUS_TRIG_DONE (1 << 2)
-
-/* DP_MIE_CLKCON */
-#define EXYNOS_DP_MIE_DISABLE (0 << 0)
-#define EXYNOS_DP_CLK_ENABLE (1 << 1)
-#define EXYNOS_MIE_CLK_ENABLE (3 << 0)
-
-#endif /* _REGS_FB_H */
+++ /dev/null
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#ifndef __ASSEMBLY__
-struct s5p_gpio_bank {
- unsigned int con;
- unsigned int dat;
- unsigned int pull;
- unsigned int drv;
- unsigned int pdn_con;
- unsigned int pdn_pull;
- unsigned char res1[8];
-};
-
-/* GPIO pins per bank */
-#define GPIO_PER_BANK 8
-
-/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
-enum exynos4_gpio_pin {
- /* GPIO_PART1_STARTS */
- EXYNOS4_GPIO_A00, /* 0 */
- EXYNOS4_GPIO_A01,
- EXYNOS4_GPIO_A02,
- EXYNOS4_GPIO_A03,
- EXYNOS4_GPIO_A04,
- EXYNOS4_GPIO_A05,
- EXYNOS4_GPIO_A06,
- EXYNOS4_GPIO_A07,
- EXYNOS4_GPIO_A10, /* 8 */
- EXYNOS4_GPIO_A11,
- EXYNOS4_GPIO_A12,
- EXYNOS4_GPIO_A13,
- EXYNOS4_GPIO_A14,
- EXYNOS4_GPIO_A15,
- EXYNOS4_GPIO_A16,
- EXYNOS4_GPIO_A17,
- EXYNOS4_GPIO_B0, /* 16 0x10 */
- EXYNOS4_GPIO_B1,
- EXYNOS4_GPIO_B2,
- EXYNOS4_GPIO_B3,
- EXYNOS4_GPIO_B4,
- EXYNOS4_GPIO_B5,
- EXYNOS4_GPIO_B6,
- EXYNOS4_GPIO_B7,
- EXYNOS4_GPIO_C00, /* 24 0x18 */
- EXYNOS4_GPIO_C01,
- EXYNOS4_GPIO_C02,
- EXYNOS4_GPIO_C03,
- EXYNOS4_GPIO_C04,
- EXYNOS4_GPIO_C05,
- EXYNOS4_GPIO_C06,
- EXYNOS4_GPIO_C07,
- EXYNOS4_GPIO_C10, /* 32 0x20*/
- EXYNOS4_GPIO_C11,
- EXYNOS4_GPIO_C12,
- EXYNOS4_GPIO_C13,
- EXYNOS4_GPIO_C14,
- EXYNOS4_GPIO_C15,
- EXYNOS4_GPIO_C16,
- EXYNOS4_GPIO_C17,
- EXYNOS4_GPIO_D00, /* 40 0x28 */
- EXYNOS4_GPIO_D01,
- EXYNOS4_GPIO_D02,
- EXYNOS4_GPIO_D03,
- EXYNOS4_GPIO_D04,
- EXYNOS4_GPIO_D05,
- EXYNOS4_GPIO_D06,
- EXYNOS4_GPIO_D07,
- EXYNOS4_GPIO_D10, /* 48 0x30 */
- EXYNOS4_GPIO_D11,
- EXYNOS4_GPIO_D12,
- EXYNOS4_GPIO_D13,
- EXYNOS4_GPIO_D14,
- EXYNOS4_GPIO_D15,
- EXYNOS4_GPIO_D16,
- EXYNOS4_GPIO_D17,
- EXYNOS4_GPIO_E00, /* 56 0x38 */
- EXYNOS4_GPIO_E01,
- EXYNOS4_GPIO_E02,
- EXYNOS4_GPIO_E03,
- EXYNOS4_GPIO_E04,
- EXYNOS4_GPIO_E05,
- EXYNOS4_GPIO_E06,
- EXYNOS4_GPIO_E07,
- EXYNOS4_GPIO_E10, /* 64 0x40 */
- EXYNOS4_GPIO_E11,
- EXYNOS4_GPIO_E12,
- EXYNOS4_GPIO_E13,
- EXYNOS4_GPIO_E14,
- EXYNOS4_GPIO_E15,
- EXYNOS4_GPIO_E16,
- EXYNOS4_GPIO_E17,
- EXYNOS4_GPIO_E20, /* 72 0x48 */
- EXYNOS4_GPIO_E21,
- EXYNOS4_GPIO_E22,
- EXYNOS4_GPIO_E23,
- EXYNOS4_GPIO_E24,
- EXYNOS4_GPIO_E25,
- EXYNOS4_GPIO_E26,
- EXYNOS4_GPIO_E27,
- EXYNOS4_GPIO_E30, /* 80 0x50 */
- EXYNOS4_GPIO_E31,
- EXYNOS4_GPIO_E32,
- EXYNOS4_GPIO_E33,
- EXYNOS4_GPIO_E34,
- EXYNOS4_GPIO_E35,
- EXYNOS4_GPIO_E36,
- EXYNOS4_GPIO_E37,
- EXYNOS4_GPIO_E40, /* 88 0x58 */
- EXYNOS4_GPIO_E41,
- EXYNOS4_GPIO_E42,
- EXYNOS4_GPIO_E43,
- EXYNOS4_GPIO_E44,
- EXYNOS4_GPIO_E45,
- EXYNOS4_GPIO_E46,
- EXYNOS4_GPIO_E47,
- EXYNOS4_GPIO_F00, /* 96 0x60 */
- EXYNOS4_GPIO_F01,
- EXYNOS4_GPIO_F02,
- EXYNOS4_GPIO_F03,
- EXYNOS4_GPIO_F04,
- EXYNOS4_GPIO_F05,
- EXYNOS4_GPIO_F06,
- EXYNOS4_GPIO_F07,
- EXYNOS4_GPIO_F10, /* 104 0x68 */
- EXYNOS4_GPIO_F11,
- EXYNOS4_GPIO_F12,
- EXYNOS4_GPIO_F13,
- EXYNOS4_GPIO_F14,
- EXYNOS4_GPIO_F15,
- EXYNOS4_GPIO_F16,
- EXYNOS4_GPIO_F17,
- EXYNOS4_GPIO_F20, /* 112 0x70 */
- EXYNOS4_GPIO_F21,
- EXYNOS4_GPIO_F22,
- EXYNOS4_GPIO_F23,
- EXYNOS4_GPIO_F24,
- EXYNOS4_GPIO_F25,
- EXYNOS4_GPIO_F26,
- EXYNOS4_GPIO_F27,
- EXYNOS4_GPIO_F30, /* 120 0x78 */
- EXYNOS4_GPIO_F31,
- EXYNOS4_GPIO_F32,
- EXYNOS4_GPIO_F33,
- EXYNOS4_GPIO_F34,
- EXYNOS4_GPIO_F35,
- EXYNOS4_GPIO_F36,
- EXYNOS4_GPIO_F37,
-
- /* GPIO_PART2_STARTS */
- EXYNOS4_GPIO_MAX_PORT_PART_1, /* 128 0x80 */
- EXYNOS4_GPIO_J00 = EXYNOS4_GPIO_MAX_PORT_PART_1,
- EXYNOS4_GPIO_J01,
- EXYNOS4_GPIO_J02,
- EXYNOS4_GPIO_J03,
- EXYNOS4_GPIO_J04,
- EXYNOS4_GPIO_J05,
- EXYNOS4_GPIO_J06,
- EXYNOS4_GPIO_J07,
- EXYNOS4_GPIO_J10, /* 136 0x88 */
- EXYNOS4_GPIO_J11,
- EXYNOS4_GPIO_J12,
- EXYNOS4_GPIO_J13,
- EXYNOS4_GPIO_J14,
- EXYNOS4_GPIO_J15,
- EXYNOS4_GPIO_J16,
- EXYNOS4_GPIO_J17,
- EXYNOS4_GPIO_K00, /* 144 0x90 */
- EXYNOS4_GPIO_K01,
- EXYNOS4_GPIO_K02,
- EXYNOS4_GPIO_K03,
- EXYNOS4_GPIO_K04,
- EXYNOS4_GPIO_K05,
- EXYNOS4_GPIO_K06,
- EXYNOS4_GPIO_K07,
- EXYNOS4_GPIO_K10, /* 152 0x98 */
- EXYNOS4_GPIO_K11,
- EXYNOS4_GPIO_K12,
- EXYNOS4_GPIO_K13,
- EXYNOS4_GPIO_K14,
- EXYNOS4_GPIO_K15,
- EXYNOS4_GPIO_K16,
- EXYNOS4_GPIO_K17,
- EXYNOS4_GPIO_K20, /* 160 0xA0 */
- EXYNOS4_GPIO_K21,
- EXYNOS4_GPIO_K22,
- EXYNOS4_GPIO_K23,
- EXYNOS4_GPIO_K24,
- EXYNOS4_GPIO_K25,
- EXYNOS4_GPIO_K26,
- EXYNOS4_GPIO_K27,
- EXYNOS4_GPIO_K30, /* 168 0xA8 */
- EXYNOS4_GPIO_K31,
- EXYNOS4_GPIO_K32,
- EXYNOS4_GPIO_K33,
- EXYNOS4_GPIO_K34,
- EXYNOS4_GPIO_K35,
- EXYNOS4_GPIO_K36,
- EXYNOS4_GPIO_K37,
- EXYNOS4_GPIO_L00, /* 176 0xB0 */
- EXYNOS4_GPIO_L01,
- EXYNOS4_GPIO_L02,
- EXYNOS4_GPIO_L03,
- EXYNOS4_GPIO_L04,
- EXYNOS4_GPIO_L05,
- EXYNOS4_GPIO_L06,
- EXYNOS4_GPIO_L07,
- EXYNOS4_GPIO_L10, /* 184 0xB8 */
- EXYNOS4_GPIO_L11,
- EXYNOS4_GPIO_L12,
- EXYNOS4_GPIO_L13,
- EXYNOS4_GPIO_L14,
- EXYNOS4_GPIO_L15,
- EXYNOS4_GPIO_L16,
- EXYNOS4_GPIO_L17,
- EXYNOS4_GPIO_L20, /* 192 0xC0 */
- EXYNOS4_GPIO_L21,
- EXYNOS4_GPIO_L22,
- EXYNOS4_GPIO_L23,
- EXYNOS4_GPIO_L24,
- EXYNOS4_GPIO_L25,
- EXYNOS4_GPIO_L26,
- EXYNOS4_GPIO_L27,
- EXYNOS4_GPIO_Y00, /* 200 0xC8 */
- EXYNOS4_GPIO_Y01,
- EXYNOS4_GPIO_Y02,
- EXYNOS4_GPIO_Y03,
- EXYNOS4_GPIO_Y04,
- EXYNOS4_GPIO_Y05,
- EXYNOS4_GPIO_Y06,
- EXYNOS4_GPIO_Y07,
- EXYNOS4_GPIO_Y10, /* 208 0xD0 */
- EXYNOS4_GPIO_Y11,
- EXYNOS4_GPIO_Y12,
- EXYNOS4_GPIO_Y13,
- EXYNOS4_GPIO_Y14,
- EXYNOS4_GPIO_Y15,
- EXYNOS4_GPIO_Y16,
- EXYNOS4_GPIO_Y17,
- EXYNOS4_GPIO_Y20, /* 216 0xD8 */
- EXYNOS4_GPIO_Y21,
- EXYNOS4_GPIO_Y22,
- EXYNOS4_GPIO_Y23,
- EXYNOS4_GPIO_Y24,
- EXYNOS4_GPIO_Y25,
- EXYNOS4_GPIO_Y26,
- EXYNOS4_GPIO_Y27,
- EXYNOS4_GPIO_Y30, /* 224 0xE0 */
- EXYNOS4_GPIO_Y31,
- EXYNOS4_GPIO_Y32,
- EXYNOS4_GPIO_Y33,
- EXYNOS4_GPIO_Y34,
- EXYNOS4_GPIO_Y35,
- EXYNOS4_GPIO_Y36,
- EXYNOS4_GPIO_Y37,
- EXYNOS4_GPIO_Y40, /* 232 0xE8 */
- EXYNOS4_GPIO_Y41,
- EXYNOS4_GPIO_Y42,
- EXYNOS4_GPIO_Y43,
- EXYNOS4_GPIO_Y44,
- EXYNOS4_GPIO_Y45,
- EXYNOS4_GPIO_Y46,
- EXYNOS4_GPIO_Y47,
- EXYNOS4_GPIO_Y50, /* 240 0xF0 */
- EXYNOS4_GPIO_Y51,
- EXYNOS4_GPIO_Y52,
- EXYNOS4_GPIO_Y53,
- EXYNOS4_GPIO_Y54,
- EXYNOS4_GPIO_Y55,
- EXYNOS4_GPIO_Y56,
- EXYNOS4_GPIO_Y57,
- EXYNOS4_GPIO_Y60, /* 248 0xF8 */
- EXYNOS4_GPIO_Y61,
- EXYNOS4_GPIO_Y62,
- EXYNOS4_GPIO_Y63,
- EXYNOS4_GPIO_Y64,
- EXYNOS4_GPIO_Y65,
- EXYNOS4_GPIO_Y66,
- EXYNOS4_GPIO_Y67,
-
- /* GPIO_PART2_1 STARTS */
- EXYNOS4_GPIO_MAX_PORT_PART_2_0, /* 256 0x100 */
- EXYNOS4_GPIO_X00 = EXYNOS4_GPIO_MAX_PORT_PART_2_0,
- EXYNOS4_GPIO_X01,
- EXYNOS4_GPIO_X02,
- EXYNOS4_GPIO_X03,
- EXYNOS4_GPIO_X04,
- EXYNOS4_GPIO_X05,
- EXYNOS4_GPIO_X06,
- EXYNOS4_GPIO_X07,
- EXYNOS4_GPIO_X10, /* 264 0x108 */
- EXYNOS4_GPIO_X11,
- EXYNOS4_GPIO_X12,
- EXYNOS4_GPIO_X13,
- EXYNOS4_GPIO_X14,
- EXYNOS4_GPIO_X15,
- EXYNOS4_GPIO_X16,
- EXYNOS4_GPIO_X17,
- EXYNOS4_GPIO_X20, /* 272 0x110 */
- EXYNOS4_GPIO_X21,
- EXYNOS4_GPIO_X22,
- EXYNOS4_GPIO_X23,
- EXYNOS4_GPIO_X24,
- EXYNOS4_GPIO_X25,
- EXYNOS4_GPIO_X26,
- EXYNOS4_GPIO_X27,
- EXYNOS4_GPIO_X30, /* 280 0x118 */
- EXYNOS4_GPIO_X31,
- EXYNOS4_GPIO_X32,
- EXYNOS4_GPIO_X33,
- EXYNOS4_GPIO_X34,
- EXYNOS4_GPIO_X35,
- EXYNOS4_GPIO_X36,
- EXYNOS4_GPIO_X37,
-
- /* GPIO_PART3_STARTS */
- EXYNOS4_GPIO_MAX_PORT_PART_2_1, /* 288 0x120 */
- EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2_1,
- EXYNOS4_GPIO_Z1,
- EXYNOS4_GPIO_Z2,
- EXYNOS4_GPIO_Z3,
- EXYNOS4_GPIO_Z4,
- EXYNOS4_GPIO_Z5,
- EXYNOS4_GPIO_Z6,
- EXYNOS4_GPIO_Z7,
-
- EXYNOS4_GPIO_MAX_PORT
-};
-
-enum exynos4X12_gpio_pin {
- /* EXYNOS4X12_GPIO_PART1_0 starts here */
- EXYNOS4X12_GPIO_A00, /* 0 */
- EXYNOS4X12_GPIO_A01,
- EXYNOS4X12_GPIO_A02,
- EXYNOS4X12_GPIO_A03,
- EXYNOS4X12_GPIO_A04,
- EXYNOS4X12_GPIO_A05,
- EXYNOS4X12_GPIO_A06,
- EXYNOS4X12_GPIO_A07,
- EXYNOS4X12_GPIO_A10, /* 8 */
- EXYNOS4X12_GPIO_A11,
- EXYNOS4X12_GPIO_A12,
- EXYNOS4X12_GPIO_A13,
- EXYNOS4X12_GPIO_A14,
- EXYNOS4X12_GPIO_A15,
- EXYNOS4X12_GPIO_A16,
- EXYNOS4X12_GPIO_A17,
- EXYNOS4X12_GPIO_B0, /* 16 0x10 */
- EXYNOS4X12_GPIO_B1,
- EXYNOS4X12_GPIO_B2,
- EXYNOS4X12_GPIO_B3,
- EXYNOS4X12_GPIO_B4,
- EXYNOS4X12_GPIO_B5,
- EXYNOS4X12_GPIO_B6,
- EXYNOS4X12_GPIO_B7,
- EXYNOS4X12_GPIO_C00, /* 24 0x18 */
- EXYNOS4X12_GPIO_C01,
- EXYNOS4X12_GPIO_C02,
- EXYNOS4X12_GPIO_C03,
- EXYNOS4X12_GPIO_C04,
- EXYNOS4X12_GPIO_C05,
- EXYNOS4X12_GPIO_C06,
- EXYNOS4X12_GPIO_C07,
- EXYNOS4X12_GPIO_C10, /* 32 0x20 */
- EXYNOS4X12_GPIO_C11,
- EXYNOS4X12_GPIO_C12,
- EXYNOS4X12_GPIO_C13,
- EXYNOS4X12_GPIO_C14,
- EXYNOS4X12_GPIO_C15,
- EXYNOS4X12_GPIO_C16,
- EXYNOS4X12_GPIO_C17,
- EXYNOS4X12_GPIO_D00, /* 40 0x28 */
- EXYNOS4X12_GPIO_D01,
- EXYNOS4X12_GPIO_D02,
- EXYNOS4X12_GPIO_D03,
- EXYNOS4X12_GPIO_D04,
- EXYNOS4X12_GPIO_D05,
- EXYNOS4X12_GPIO_D06,
- EXYNOS4X12_GPIO_D07,
- EXYNOS4X12_GPIO_D10, /* 48 0x30 */
- EXYNOS4X12_GPIO_D11,
- EXYNOS4X12_GPIO_D12,
- EXYNOS4X12_GPIO_D13,
- EXYNOS4X12_GPIO_D14,
- EXYNOS4X12_GPIO_D15,
- EXYNOS4X12_GPIO_D16,
- EXYNOS4X12_GPIO_D17,
- EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, /* 56 0x38 */
- /* EXYNOS4X12_GPIO_PART1_1 starts here */
- EXYNOS4X12_GPIO_F00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_0,
- EXYNOS4X12_GPIO_F01,
- EXYNOS4X12_GPIO_F02,
- EXYNOS4X12_GPIO_F03,
- EXYNOS4X12_GPIO_F04,
- EXYNOS4X12_GPIO_F05,
- EXYNOS4X12_GPIO_F06,
- EXYNOS4X12_GPIO_F07,
- EXYNOS4X12_GPIO_F10, /* 64 0x40 */
- EXYNOS4X12_GPIO_F11,
- EXYNOS4X12_GPIO_F12,
- EXYNOS4X12_GPIO_F13,
- EXYNOS4X12_GPIO_F14,
- EXYNOS4X12_GPIO_F15,
- EXYNOS4X12_GPIO_F16,
- EXYNOS4X12_GPIO_F17,
- EXYNOS4X12_GPIO_F20, /* 72 0x48 */
- EXYNOS4X12_GPIO_F21,
- EXYNOS4X12_GPIO_F22,
- EXYNOS4X12_GPIO_F23,
- EXYNOS4X12_GPIO_F24,
- EXYNOS4X12_GPIO_F25,
- EXYNOS4X12_GPIO_F26,
- EXYNOS4X12_GPIO_F27,
- EXYNOS4X12_GPIO_F30, /* 80 0x50 */
- EXYNOS4X12_GPIO_F31,
- EXYNOS4X12_GPIO_F32,
- EXYNOS4X12_GPIO_F33,
- EXYNOS4X12_GPIO_F34,
- EXYNOS4X12_GPIO_F35,
- EXYNOS4X12_GPIO_F36,
- EXYNOS4X12_GPIO_F37,
- EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, /* 88 0x58 */
- /* EXYNOS4X12_GPIO_PART1_2 starts here */
- EXYNOS4X12_GPIO_J00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_1,
- EXYNOS4X12_GPIO_J01,
- EXYNOS4X12_GPIO_J02,
- EXYNOS4X12_GPIO_J03,
- EXYNOS4X12_GPIO_J04,
- EXYNOS4X12_GPIO_J05,
- EXYNOS4X12_GPIO_J06,
- EXYNOS4X12_GPIO_J07,
- EXYNOS4X12_GPIO_J10, /* 96 0x60 */
- EXYNOS4X12_GPIO_J11,
- EXYNOS4X12_GPIO_J12,
- EXYNOS4X12_GPIO_J13,
- EXYNOS4X12_GPIO_J14,
- EXYNOS4X12_GPIO_J15,
- EXYNOS4X12_GPIO_J16,
- EXYNOS4X12_GPIO_J17,
-
- /**
- * EXYNOS4X12_GPIO_PART2_0 is not used
- * EXYNOS4X12_GPIO_PART2_1 starts here
- */
- EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, /* 104 0x66 */
- EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_2,
- EXYNOS4X12_GPIO_K01,
- EXYNOS4X12_GPIO_K02,
- EXYNOS4X12_GPIO_K03,
- EXYNOS4X12_GPIO_K04,
- EXYNOS4X12_GPIO_K05,
- EXYNOS4X12_GPIO_K06,
- EXYNOS4X12_GPIO_K07,
- EXYNOS4X12_GPIO_K10, /* 112 0x70 */
- EXYNOS4X12_GPIO_K11,
- EXYNOS4X12_GPIO_K12,
- EXYNOS4X12_GPIO_K13,
- EXYNOS4X12_GPIO_K14,
- EXYNOS4X12_GPIO_K15,
- EXYNOS4X12_GPIO_K16,
- EXYNOS4X12_GPIO_K17,
- EXYNOS4X12_GPIO_K20, /* 120 0x78 */
- EXYNOS4X12_GPIO_K21,
- EXYNOS4X12_GPIO_K22,
- EXYNOS4X12_GPIO_K23,
- EXYNOS4X12_GPIO_K24,
- EXYNOS4X12_GPIO_K25,
- EXYNOS4X12_GPIO_K26,
- EXYNOS4X12_GPIO_K27,
- EXYNOS4X12_GPIO_K30, /* 128 0x80 */
- EXYNOS4X12_GPIO_K31,
- EXYNOS4X12_GPIO_K32,
- EXYNOS4X12_GPIO_K33,
- EXYNOS4X12_GPIO_K34,
- EXYNOS4X12_GPIO_K35,
- EXYNOS4X12_GPIO_K36,
- EXYNOS4X12_GPIO_K37,
- EXYNOS4X12_GPIO_L00, /* 136 0x88 */
- EXYNOS4X12_GPIO_L01,
- EXYNOS4X12_GPIO_L02,
- EXYNOS4X12_GPIO_L03,
- EXYNOS4X12_GPIO_L04,
- EXYNOS4X12_GPIO_L05,
- EXYNOS4X12_GPIO_L06,
- EXYNOS4X12_GPIO_L07,
- EXYNOS4X12_GPIO_L10, /* 144 0x90 */
- EXYNOS4X12_GPIO_L11,
- EXYNOS4X12_GPIO_L12,
- EXYNOS4X12_GPIO_L13,
- EXYNOS4X12_GPIO_L14,
- EXYNOS4X12_GPIO_L15,
- EXYNOS4X12_GPIO_L16,
- EXYNOS4X12_GPIO_L17,
- EXYNOS4X12_GPIO_L20, /* 152 0x98 */
- EXYNOS4X12_GPIO_L21,
- EXYNOS4X12_GPIO_L22,
- EXYNOS4X12_GPIO_L23,
- EXYNOS4X12_GPIO_L24,
- EXYNOS4X12_GPIO_L25,
- EXYNOS4X12_GPIO_L26,
- EXYNOS4X12_GPIO_L27,
- EXYNOS4X12_GPIO_Y00, /* 160 0xa0 */
- EXYNOS4X12_GPIO_Y01,
- EXYNOS4X12_GPIO_Y02,
- EXYNOS4X12_GPIO_Y03,
- EXYNOS4X12_GPIO_Y04,
- EXYNOS4X12_GPIO_Y05,
- EXYNOS4X12_GPIO_Y06,
- EXYNOS4X12_GPIO_Y07,
- EXYNOS4X12_GPIO_Y10, /* 168 0xa8 */
- EXYNOS4X12_GPIO_Y11,
- EXYNOS4X12_GPIO_Y12,
- EXYNOS4X12_GPIO_Y13,
- EXYNOS4X12_GPIO_Y14,
- EXYNOS4X12_GPIO_Y15,
- EXYNOS4X12_GPIO_Y16,
- EXYNOS4X12_GPIO_Y17,
- EXYNOS4X12_GPIO_Y20, /* 176 0xb0 */
- EXYNOS4X12_GPIO_Y21,
- EXYNOS4X12_GPIO_Y22,
- EXYNOS4X12_GPIO_Y23,
- EXYNOS4X12_GPIO_Y24,
- EXYNOS4X12_GPIO_Y25,
- EXYNOS4X12_GPIO_Y26,
- EXYNOS4X12_GPIO_Y27,
- EXYNOS4X12_GPIO_Y30, /* 184 0xb8 */
- EXYNOS4X12_GPIO_Y31,
- EXYNOS4X12_GPIO_Y32,
- EXYNOS4X12_GPIO_Y33,
- EXYNOS4X12_GPIO_Y34,
- EXYNOS4X12_GPIO_Y35,
- EXYNOS4X12_GPIO_Y36,
- EXYNOS4X12_GPIO_Y37,
- EXYNOS4X12_GPIO_Y40, /* 192 0xc0 */
- EXYNOS4X12_GPIO_Y41,
- EXYNOS4X12_GPIO_Y42,
- EXYNOS4X12_GPIO_Y43,
- EXYNOS4X12_GPIO_Y44,
- EXYNOS4X12_GPIO_Y45,
- EXYNOS4X12_GPIO_Y46,
- EXYNOS4X12_GPIO_Y47,
- EXYNOS4X12_GPIO_Y50, /* 200 0xc8 */
- EXYNOS4X12_GPIO_Y51,
- EXYNOS4X12_GPIO_Y52,
- EXYNOS4X12_GPIO_Y53,
- EXYNOS4X12_GPIO_Y54,
- EXYNOS4X12_GPIO_Y55,
- EXYNOS4X12_GPIO_Y56,
- EXYNOS4X12_GPIO_Y57,
- EXYNOS4X12_GPIO_Y60, /* 208 0xd0 */
- EXYNOS4X12_GPIO_Y61,
- EXYNOS4X12_GPIO_Y62,
- EXYNOS4X12_GPIO_Y63,
- EXYNOS4X12_GPIO_Y64,
- EXYNOS4X12_GPIO_Y65,
- EXYNOS4X12_GPIO_Y66,
- EXYNOS4X12_GPIO_Y67,
- EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, /* 216 0xd8 */
- /* EXYNOS4X12_GPIO_PART2_2 starts here */
- EXYNOS4X12_GPIO_M00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_1,
- EXYNOS4X12_GPIO_M01,
- EXYNOS4X12_GPIO_M02,
- EXYNOS4X12_GPIO_M03,
- EXYNOS4X12_GPIO_M04,
- EXYNOS4X12_GPIO_M05,
- EXYNOS4X12_GPIO_M06,
- EXYNOS4X12_GPIO_M07,
- EXYNOS4X12_GPIO_M10, /* 224 0xe0 */
- EXYNOS4X12_GPIO_M11,
- EXYNOS4X12_GPIO_M12,
- EXYNOS4X12_GPIO_M13,
- EXYNOS4X12_GPIO_M14,
- EXYNOS4X12_GPIO_M15,
- EXYNOS4X12_GPIO_M16,
- EXYNOS4X12_GPIO_M17,
- EXYNOS4X12_GPIO_M20, /* 232 0xe8 */
- EXYNOS4X12_GPIO_M21,
- EXYNOS4X12_GPIO_M22,
- EXYNOS4X12_GPIO_M23,
- EXYNOS4X12_GPIO_M24,
- EXYNOS4X12_GPIO_M25,
- EXYNOS4X12_GPIO_M26,
- EXYNOS4X12_GPIO_M27,
- EXYNOS4X12_GPIO_M30, /* 240 0xf0 */
- EXYNOS4X12_GPIO_M31,
- EXYNOS4X12_GPIO_M32,
- EXYNOS4X12_GPIO_M33,
- EXYNOS4X12_GPIO_M34,
- EXYNOS4X12_GPIO_M35,
- EXYNOS4X12_GPIO_M36,
- EXYNOS4X12_GPIO_M37,
- EXYNOS4X12_GPIO_M40, /* 248 0xf8 */
- EXYNOS4X12_GPIO_M41,
- EXYNOS4X12_GPIO_M42,
- EXYNOS4X12_GPIO_M43,
- EXYNOS4X12_GPIO_M44,
- EXYNOS4X12_GPIO_M45,
- EXYNOS4X12_GPIO_M46,
- EXYNOS4X12_GPIO_M47,
- EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, /* 256 0x100 */
- /* EXYNOS4X12_GPIO_PART2_3 starts here */
- EXYNOS4X12_GPIO_X00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_2,
- EXYNOS4X12_GPIO_X01,
- EXYNOS4X12_GPIO_X02,
- EXYNOS4X12_GPIO_X03,
- EXYNOS4X12_GPIO_X04,
- EXYNOS4X12_GPIO_X05,
- EXYNOS4X12_GPIO_X06,
- EXYNOS4X12_GPIO_X07,
- EXYNOS4X12_GPIO_X10, /* 264 0x108 */
- EXYNOS4X12_GPIO_X11,
- EXYNOS4X12_GPIO_X12,
- EXYNOS4X12_GPIO_X13,
- EXYNOS4X12_GPIO_X14,
- EXYNOS4X12_GPIO_X15,
- EXYNOS4X12_GPIO_X16,
- EXYNOS4X12_GPIO_X17,
- EXYNOS4X12_GPIO_X20, /* 272 0x110 */
- EXYNOS4X12_GPIO_X21,
- EXYNOS4X12_GPIO_X22,
- EXYNOS4X12_GPIO_X23,
- EXYNOS4X12_GPIO_X24,
- EXYNOS4X12_GPIO_X25,
- EXYNOS4X12_GPIO_X26,
- EXYNOS4X12_GPIO_X27,
- EXYNOS4X12_GPIO_X30, /* 280 0x118 */
- EXYNOS4X12_GPIO_X31,
- EXYNOS4X12_GPIO_X32,
- EXYNOS4X12_GPIO_X33,
- EXYNOS4X12_GPIO_X34,
- EXYNOS4X12_GPIO_X35,
- EXYNOS4X12_GPIO_X36,
- EXYNOS4X12_GPIO_X37,
-
- /* EXYNOS4X12_GPIO_PART3 starts here */
- EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, /* 288 0x120 */
- EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_3,
- EXYNOS4X12_GPIO_Z1,
- EXYNOS4X12_GPIO_Z2,
- EXYNOS4X12_GPIO_Z3,
- EXYNOS4X12_GPIO_Z4,
- EXYNOS4X12_GPIO_Z5,
- EXYNOS4X12_GPIO_Z6,
- EXYNOS4X12_GPIO_Z7,
-
- /* EXYNOS4X12_GPIO_PART4 starts here */
- EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */
- EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3,
- EXYNOS4X12_GPIO_V01,
- EXYNOS4X12_GPIO_V02,
- EXYNOS4X12_GPIO_V03,
- EXYNOS4X12_GPIO_V04,
- EXYNOS4X12_GPIO_V05,
- EXYNOS4X12_GPIO_V06,
- EXYNOS4X12_GPIO_V07,
- EXYNOS4X12_GPIO_V10, /* 304 0x130 */
- EXYNOS4X12_GPIO_V11,
- EXYNOS4X12_GPIO_V12,
- EXYNOS4X12_GPIO_V13,
- EXYNOS4X12_GPIO_V14,
- EXYNOS4X12_GPIO_V15,
- EXYNOS4X12_GPIO_V16,
- EXYNOS4X12_GPIO_V17,
- EXYNOS4X12_GPIO_V20, /* 312 0x138 */
- EXYNOS4X12_GPIO_V21,
- EXYNOS4X12_GPIO_V22,
- EXYNOS4X12_GPIO_V23,
- EXYNOS4X12_GPIO_V24,
- EXYNOS4X12_GPIO_V25,
- EXYNOS4X12_GPIO_V26,
- EXYNOS4X12_GPIO_V27,
- EXYNOS4X12_GPIO_V30, /* 320 0x140 */
- EXYNOS4X12_GPIO_V31,
- EXYNOS4X12_GPIO_V32,
- EXYNOS4X12_GPIO_V33,
- EXYNOS4X12_GPIO_V34,
- EXYNOS4X12_GPIO_V35,
- EXYNOS4X12_GPIO_V36,
- EXYNOS4X12_GPIO_V37,
- EXYNOS4X12_GPIO_V40, /* 328 0x148 */
- EXYNOS4X12_GPIO_V41,
- EXYNOS4X12_GPIO_V42,
- EXYNOS4X12_GPIO_V43,
- EXYNOS4X12_GPIO_V44,
- EXYNOS4X12_GPIO_V45,
- EXYNOS4X12_GPIO_V46,
- EXYNOS4X12_GPIO_V47,
-
- EXYNOS4X12_GPIO_MAX_PORT
-};
-
-enum exynos5_gpio_pin {
- /* GPIO_PART1_STARTS */
- EXYNOS5_GPIO_A00, /* 0 */
- EXYNOS5_GPIO_A01,
- EXYNOS5_GPIO_A02,
- EXYNOS5_GPIO_A03,
- EXYNOS5_GPIO_A04,
- EXYNOS5_GPIO_A05,
- EXYNOS5_GPIO_A06,
- EXYNOS5_GPIO_A07,
- EXYNOS5_GPIO_A10, /* 8 */
- EXYNOS5_GPIO_A11,
- EXYNOS5_GPIO_A12,
- EXYNOS5_GPIO_A13,
- EXYNOS5_GPIO_A14,
- EXYNOS5_GPIO_A15,
- EXYNOS5_GPIO_A16,
- EXYNOS5_GPIO_A17,
- EXYNOS5_GPIO_A20, /* 16 0x10 */
- EXYNOS5_GPIO_A21,
- EXYNOS5_GPIO_A22,
- EXYNOS5_GPIO_A23,
- EXYNOS5_GPIO_A24,
- EXYNOS5_GPIO_A25,
- EXYNOS5_GPIO_A26,
- EXYNOS5_GPIO_A27,
- EXYNOS5_GPIO_B00, /* 24 0x18 */
- EXYNOS5_GPIO_B01,
- EXYNOS5_GPIO_B02,
- EXYNOS5_GPIO_B03,
- EXYNOS5_GPIO_B04,
- EXYNOS5_GPIO_B05,
- EXYNOS5_GPIO_B06,
- EXYNOS5_GPIO_B07,
- EXYNOS5_GPIO_B10, /* 32 0x20 */
- EXYNOS5_GPIO_B11,
- EXYNOS5_GPIO_B12,
- EXYNOS5_GPIO_B13,
- EXYNOS5_GPIO_B14,
- EXYNOS5_GPIO_B15,
- EXYNOS5_GPIO_B16,
- EXYNOS5_GPIO_B17,
- EXYNOS5_GPIO_B20, /* 40 0x28 */
- EXYNOS5_GPIO_B21,
- EXYNOS5_GPIO_B22,
- EXYNOS5_GPIO_B23,
- EXYNOS5_GPIO_B24,
- EXYNOS5_GPIO_B25,
- EXYNOS5_GPIO_B26,
- EXYNOS5_GPIO_B27,
- EXYNOS5_GPIO_B30, /* 48 0x39 */
- EXYNOS5_GPIO_B31,
- EXYNOS5_GPIO_B32,
- EXYNOS5_GPIO_B33,
- EXYNOS5_GPIO_B34,
- EXYNOS5_GPIO_B35,
- EXYNOS5_GPIO_B36,
- EXYNOS5_GPIO_B37,
- EXYNOS5_GPIO_C00, /* 56 0x38 */
- EXYNOS5_GPIO_C01,
- EXYNOS5_GPIO_C02,
- EXYNOS5_GPIO_C03,
- EXYNOS5_GPIO_C04,
- EXYNOS5_GPIO_C05,
- EXYNOS5_GPIO_C06,
- EXYNOS5_GPIO_C07,
- EXYNOS5_GPIO_C10, /* 64 0x40 */
- EXYNOS5_GPIO_C11,
- EXYNOS5_GPIO_C12,
- EXYNOS5_GPIO_C13,
- EXYNOS5_GPIO_C14,
- EXYNOS5_GPIO_C15,
- EXYNOS5_GPIO_C16,
- EXYNOS5_GPIO_C17,
- EXYNOS5_GPIO_C20, /* 72 0x48 */
- EXYNOS5_GPIO_C21,
- EXYNOS5_GPIO_C22,
- EXYNOS5_GPIO_C23,
- EXYNOS5_GPIO_C24,
- EXYNOS5_GPIO_C25,
- EXYNOS5_GPIO_C26,
- EXYNOS5_GPIO_C27,
- EXYNOS5_GPIO_C30, /* 80 0x50 */
- EXYNOS5_GPIO_C31,
- EXYNOS5_GPIO_C32,
- EXYNOS5_GPIO_C33,
- EXYNOS5_GPIO_C34,
- EXYNOS5_GPIO_C35,
- EXYNOS5_GPIO_C36,
- EXYNOS5_GPIO_C37,
- EXYNOS5_GPIO_D00, /* 88 0x58 */
- EXYNOS5_GPIO_D01,
- EXYNOS5_GPIO_D02,
- EXYNOS5_GPIO_D03,
- EXYNOS5_GPIO_D04,
- EXYNOS5_GPIO_D05,
- EXYNOS5_GPIO_D06,
- EXYNOS5_GPIO_D07,
- EXYNOS5_GPIO_D10, /* 96 0x60 */
- EXYNOS5_GPIO_D11,
- EXYNOS5_GPIO_D12,
- EXYNOS5_GPIO_D13,
- EXYNOS5_GPIO_D14,
- EXYNOS5_GPIO_D15,
- EXYNOS5_GPIO_D16,
- EXYNOS5_GPIO_D17,
- EXYNOS5_GPIO_Y00, /* 104 0x68 */
- EXYNOS5_GPIO_Y01,
- EXYNOS5_GPIO_Y02,
- EXYNOS5_GPIO_Y03,
- EXYNOS5_GPIO_Y04,
- EXYNOS5_GPIO_Y05,
- EXYNOS5_GPIO_Y06,
- EXYNOS5_GPIO_Y07,
- EXYNOS5_GPIO_Y10, /* 112 0x70 */
- EXYNOS5_GPIO_Y11,
- EXYNOS5_GPIO_Y12,
- EXYNOS5_GPIO_Y13,
- EXYNOS5_GPIO_Y14,
- EXYNOS5_GPIO_Y15,
- EXYNOS5_GPIO_Y16,
- EXYNOS5_GPIO_Y17,
- EXYNOS5_GPIO_Y20, /* 120 0x78 */
- EXYNOS5_GPIO_Y21,
- EXYNOS5_GPIO_Y22,
- EXYNOS5_GPIO_Y23,
- EXYNOS5_GPIO_Y24,
- EXYNOS5_GPIO_Y25,
- EXYNOS5_GPIO_Y26,
- EXYNOS5_GPIO_Y27,
- EXYNOS5_GPIO_Y30, /* 128 0x80 */
- EXYNOS5_GPIO_Y31,
- EXYNOS5_GPIO_Y32,
- EXYNOS5_GPIO_Y33,
- EXYNOS5_GPIO_Y34,
- EXYNOS5_GPIO_Y35,
- EXYNOS5_GPIO_Y36,
- EXYNOS5_GPIO_Y37,
- EXYNOS5_GPIO_Y40, /* 136 0x88 */
- EXYNOS5_GPIO_Y41,
- EXYNOS5_GPIO_Y42,
- EXYNOS5_GPIO_Y43,
- EXYNOS5_GPIO_Y44,
- EXYNOS5_GPIO_Y45,
- EXYNOS5_GPIO_Y46,
- EXYNOS5_GPIO_Y47,
- EXYNOS5_GPIO_Y50, /* 144 0x90 */
- EXYNOS5_GPIO_Y51,
- EXYNOS5_GPIO_Y52,
- EXYNOS5_GPIO_Y53,
- EXYNOS5_GPIO_Y54,
- EXYNOS5_GPIO_Y55,
- EXYNOS5_GPIO_Y56,
- EXYNOS5_GPIO_Y57,
- EXYNOS5_GPIO_Y60, /* 152 0x98 */
- EXYNOS5_GPIO_Y61,
- EXYNOS5_GPIO_Y62,
- EXYNOS5_GPIO_Y63,
- EXYNOS5_GPIO_Y64,
- EXYNOS5_GPIO_Y65,
- EXYNOS5_GPIO_Y66,
- EXYNOS5_GPIO_Y67,
-
- /* GPIO_PART2_STARTS */
- EXYNOS5_GPIO_MAX_PORT_PART_1, /* 160 0xa0 */
- EXYNOS5_GPIO_C40 = EXYNOS5_GPIO_MAX_PORT_PART_1,
- EXYNOS5_GPIO_C41,
- EXYNOS5_GPIO_C42,
- EXYNOS5_GPIO_C43,
- EXYNOS5_GPIO_C44,
- EXYNOS5_GPIO_C45,
- EXYNOS5_GPIO_C46,
- EXYNOS5_GPIO_C47,
-
- /* GPIO_PART3_STARTS */
- EXYNOS5_GPIO_MAX_PORT_PART_2, /* 168 0xa8 */
- EXYNOS5_GPIO_X00 = EXYNOS5_GPIO_MAX_PORT_PART_2,
- EXYNOS5_GPIO_X01,
- EXYNOS5_GPIO_X02,
- EXYNOS5_GPIO_X03,
- EXYNOS5_GPIO_X04,
- EXYNOS5_GPIO_X05,
- EXYNOS5_GPIO_X06,
- EXYNOS5_GPIO_X07,
- EXYNOS5_GPIO_X10, /* 176 0xb0 */
- EXYNOS5_GPIO_X11,
- EXYNOS5_GPIO_X12,
- EXYNOS5_GPIO_X13,
- EXYNOS5_GPIO_X14,
- EXYNOS5_GPIO_X15,
- EXYNOS5_GPIO_X16,
- EXYNOS5_GPIO_X17,
- EXYNOS5_GPIO_X20, /* 184 0xb8 */
- EXYNOS5_GPIO_X21,
- EXYNOS5_GPIO_X22,
- EXYNOS5_GPIO_X23,
- EXYNOS5_GPIO_X24,
- EXYNOS5_GPIO_X25,
- EXYNOS5_GPIO_X26,
- EXYNOS5_GPIO_X27,
- EXYNOS5_GPIO_X30, /* 192 0xc0 */
- EXYNOS5_GPIO_X31,
- EXYNOS5_GPIO_X32,
- EXYNOS5_GPIO_X33,
- EXYNOS5_GPIO_X34,
- EXYNOS5_GPIO_X35,
- EXYNOS5_GPIO_X36,
- EXYNOS5_GPIO_X37,
-
- /* GPIO_PART4_STARTS */
- EXYNOS5_GPIO_MAX_PORT_PART_3, /* 200 0xc8 */
- EXYNOS5_GPIO_E00 = EXYNOS5_GPIO_MAX_PORT_PART_3,
- EXYNOS5_GPIO_E01,
- EXYNOS5_GPIO_E02,
- EXYNOS5_GPIO_E03,
- EXYNOS5_GPIO_E04,
- EXYNOS5_GPIO_E05,
- EXYNOS5_GPIO_E06,
- EXYNOS5_GPIO_E07,
- EXYNOS5_GPIO_E10, /* 208 0xd0 */
- EXYNOS5_GPIO_E11,
- EXYNOS5_GPIO_E12,
- EXYNOS5_GPIO_E13,
- EXYNOS5_GPIO_E14,
- EXYNOS5_GPIO_E15,
- EXYNOS5_GPIO_E16,
- EXYNOS5_GPIO_E17,
- EXYNOS5_GPIO_F00, /* 216 0xd8 */
- EXYNOS5_GPIO_F01,
- EXYNOS5_GPIO_F02,
- EXYNOS5_GPIO_F03,
- EXYNOS5_GPIO_F04,
- EXYNOS5_GPIO_F05,
- EXYNOS5_GPIO_F06,
- EXYNOS5_GPIO_F07,
- EXYNOS5_GPIO_F10, /* 224 0xe0 */
- EXYNOS5_GPIO_F11,
- EXYNOS5_GPIO_F12,
- EXYNOS5_GPIO_F13,
- EXYNOS5_GPIO_F14,
- EXYNOS5_GPIO_F15,
- EXYNOS5_GPIO_F16,
- EXYNOS5_GPIO_F17,
- EXYNOS5_GPIO_G00, /* 232 0xe8 */
- EXYNOS5_GPIO_G01,
- EXYNOS5_GPIO_G02,
- EXYNOS5_GPIO_G03,
- EXYNOS5_GPIO_G04,
- EXYNOS5_GPIO_G05,
- EXYNOS5_GPIO_G06,
- EXYNOS5_GPIO_G07,
- EXYNOS5_GPIO_G10, /* 240 0xf0 */
- EXYNOS5_GPIO_G11,
- EXYNOS5_GPIO_G12,
- EXYNOS5_GPIO_G13,
- EXYNOS5_GPIO_G14,
- EXYNOS5_GPIO_G15,
- EXYNOS5_GPIO_G16,
- EXYNOS5_GPIO_G17,
- EXYNOS5_GPIO_G20, /* 248 0xf8 */
- EXYNOS5_GPIO_G21,
- EXYNOS5_GPIO_G22,
- EXYNOS5_GPIO_G23,
- EXYNOS5_GPIO_G24,
- EXYNOS5_GPIO_G25,
- EXYNOS5_GPIO_G26,
- EXYNOS5_GPIO_G27,
- EXYNOS5_GPIO_H00, /* 256 0x100 */
- EXYNOS5_GPIO_H01,
- EXYNOS5_GPIO_H02,
- EXYNOS5_GPIO_H03,
- EXYNOS5_GPIO_H04,
- EXYNOS5_GPIO_H05,
- EXYNOS5_GPIO_H06,
- EXYNOS5_GPIO_H07,
- EXYNOS5_GPIO_H10, /* 264 0x108 */
- EXYNOS5_GPIO_H11,
- EXYNOS5_GPIO_H12,
- EXYNOS5_GPIO_H13,
- EXYNOS5_GPIO_H14,
- EXYNOS5_GPIO_H15,
- EXYNOS5_GPIO_H16,
- EXYNOS5_GPIO_H17,
-
- /* GPIO_PART4_STARTS */
- EXYNOS5_GPIO_MAX_PORT_PART_4, /* 272 0x110 */
- EXYNOS5_GPIO_V00 = EXYNOS5_GPIO_MAX_PORT_PART_4,
- EXYNOS5_GPIO_V01,
- EXYNOS5_GPIO_V02,
- EXYNOS5_GPIO_V03,
- EXYNOS5_GPIO_V04,
- EXYNOS5_GPIO_V05,
- EXYNOS5_GPIO_V06,
- EXYNOS5_GPIO_V07,
- EXYNOS5_GPIO_V10, /* 280 0x118 */
- EXYNOS5_GPIO_V11,
- EXYNOS5_GPIO_V12,
- EXYNOS5_GPIO_V13,
- EXYNOS5_GPIO_V14,
- EXYNOS5_GPIO_V15,
- EXYNOS5_GPIO_V16,
- EXYNOS5_GPIO_V17,
-
- /* GPIO_PART5_STARTS */
- EXYNOS5_GPIO_MAX_PORT_PART_5, /* 288 0x120 */
- EXYNOS5_GPIO_V20 = EXYNOS5_GPIO_MAX_PORT_PART_5,
- EXYNOS5_GPIO_V21,
- EXYNOS5_GPIO_V22,
- EXYNOS5_GPIO_V23,
- EXYNOS5_GPIO_V24,
- EXYNOS5_GPIO_V25,
- EXYNOS5_GPIO_V26,
- EXYNOS5_GPIO_V27,
- EXYNOS5_GPIO_V30, /* 296 0x128 */
- EXYNOS5_GPIO_V31,
- EXYNOS5_GPIO_V32,
- EXYNOS5_GPIO_V33,
- EXYNOS5_GPIO_V34,
- EXYNOS5_GPIO_V35,
- EXYNOS5_GPIO_V36,
- EXYNOS5_GPIO_V37,
-
- /* GPIO_PART6_STARTS */
- EXYNOS5_GPIO_MAX_PORT_PART_6, /* 304 0x130 */
- EXYNOS5_GPIO_V40 = EXYNOS5_GPIO_MAX_PORT_PART_6,
- EXYNOS5_GPIO_V41,
- EXYNOS5_GPIO_V42,
- EXYNOS5_GPIO_V43,
- EXYNOS5_GPIO_V44,
- EXYNOS5_GPIO_V45,
- EXYNOS5_GPIO_V46,
- EXYNOS5_GPIO_V47,
-
- /* GPIO_PART7_STARTS */ /* 312 0x138 */
- EXYNOS5_GPIO_MAX_PORT_PART_7,
- EXYNOS5_GPIO_Z0 = EXYNOS5_GPIO_MAX_PORT_PART_7,
- EXYNOS5_GPIO_Z1,
- EXYNOS5_GPIO_Z2,
- EXYNOS5_GPIO_Z3,
- EXYNOS5_GPIO_Z4,
- EXYNOS5_GPIO_Z5,
- EXYNOS5_GPIO_Z6,
- EXYNOS5_GPIO_MAX_PORT
-};
-
-enum exynos5420_gpio_pin {
- /* GPIO_PART1_STARTS */
- EXYNOS5420_GPIO_A00, /* 0 */
- EXYNOS5420_GPIO_A01,
- EXYNOS5420_GPIO_A02,
- EXYNOS5420_GPIO_A03,
- EXYNOS5420_GPIO_A04,
- EXYNOS5420_GPIO_A05,
- EXYNOS5420_GPIO_A06,
- EXYNOS5420_GPIO_A07,
- EXYNOS5420_GPIO_A10, /* 8 */
- EXYNOS5420_GPIO_A11,
- EXYNOS5420_GPIO_A12,
- EXYNOS5420_GPIO_A13,
- EXYNOS5420_GPIO_A14,
- EXYNOS5420_GPIO_A15,
- EXYNOS5420_GPIO_A16,
- EXYNOS5420_GPIO_A17,
- EXYNOS5420_GPIO_A20, /* 16 0x10 */
- EXYNOS5420_GPIO_A21,
- EXYNOS5420_GPIO_A22,
- EXYNOS5420_GPIO_A23,
- EXYNOS5420_GPIO_A24,
- EXYNOS5420_GPIO_A25,
- EXYNOS5420_GPIO_A26,
- EXYNOS5420_GPIO_A27,
- EXYNOS5420_GPIO_B00, /* 24 0x18 */
- EXYNOS5420_GPIO_B01,
- EXYNOS5420_GPIO_B02,
- EXYNOS5420_GPIO_B03,
- EXYNOS5420_GPIO_B04,
- EXYNOS5420_GPIO_B05,
- EXYNOS5420_GPIO_B06,
- EXYNOS5420_GPIO_B07,
- EXYNOS5420_GPIO_B10, /* 32 0x20 */
- EXYNOS5420_GPIO_B11,
- EXYNOS5420_GPIO_B12,
- EXYNOS5420_GPIO_B13,
- EXYNOS5420_GPIO_B14,
- EXYNOS5420_GPIO_B15,
- EXYNOS5420_GPIO_B16,
- EXYNOS5420_GPIO_B17,
- EXYNOS5420_GPIO_B20, /* 40 0x28 */
- EXYNOS5420_GPIO_B21,
- EXYNOS5420_GPIO_B22,
- EXYNOS5420_GPIO_B23,
- EXYNOS5420_GPIO_B24,
- EXYNOS5420_GPIO_B25,
- EXYNOS5420_GPIO_B26,
- EXYNOS5420_GPIO_B27,
- EXYNOS5420_GPIO_B30, /* 48 0x30 */
- EXYNOS5420_GPIO_B31,
- EXYNOS5420_GPIO_B32,
- EXYNOS5420_GPIO_B33,
- EXYNOS5420_GPIO_B34,
- EXYNOS5420_GPIO_B35,
- EXYNOS5420_GPIO_B36,
- EXYNOS5420_GPIO_B37,
- EXYNOS5420_GPIO_B40, /* 56 0x38 */
- EXYNOS5420_GPIO_B41,
- EXYNOS5420_GPIO_B42,
- EXYNOS5420_GPIO_B43,
- EXYNOS5420_GPIO_B44,
- EXYNOS5420_GPIO_B45,
- EXYNOS5420_GPIO_B46,
- EXYNOS5420_GPIO_B47,
- EXYNOS5420_GPIO_H00, /* 64 0x40 */
- EXYNOS5420_GPIO_H01,
- EXYNOS5420_GPIO_H02,
- EXYNOS5420_GPIO_H03,
- EXYNOS5420_GPIO_H04,
- EXYNOS5420_GPIO_H05,
- EXYNOS5420_GPIO_H06,
- EXYNOS5420_GPIO_H07,
-
- /* GPIO PART 2 STARTS*/
- EXYNOS5420_GPIO_MAX_PORT_PART_1,/* 72 0x48 */
- EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1,
- EXYNOS5420_GPIO_Y71,
- EXYNOS5420_GPIO_Y72,
- EXYNOS5420_GPIO_Y73,
- EXYNOS5420_GPIO_Y74,
- EXYNOS5420_GPIO_Y75,
- EXYNOS5420_GPIO_Y76,
- EXYNOS5420_GPIO_Y77,
-
- /* GPIO PART 3 STARTS*/
- EXYNOS5420_GPIO_MAX_PORT_PART_2,/* 80 0x50 */
- EXYNOS5420_GPIO_X00 = EXYNOS5420_GPIO_MAX_PORT_PART_2,
- EXYNOS5420_GPIO_X01,
- EXYNOS5420_GPIO_X02,
- EXYNOS5420_GPIO_X03,
- EXYNOS5420_GPIO_X04,
- EXYNOS5420_GPIO_X05,
- EXYNOS5420_GPIO_X06,
- EXYNOS5420_GPIO_X07,
- EXYNOS5420_GPIO_X10, /* 88 0x58 */
- EXYNOS5420_GPIO_X11,
- EXYNOS5420_GPIO_X12,
- EXYNOS5420_GPIO_X13,
- EXYNOS5420_GPIO_X14,
- EXYNOS5420_GPIO_X15,
- EXYNOS5420_GPIO_X16,
- EXYNOS5420_GPIO_X17,
- EXYNOS5420_GPIO_X20, /* 96 0x60 */
- EXYNOS5420_GPIO_X21,
- EXYNOS5420_GPIO_X22,
- EXYNOS5420_GPIO_X23,
- EXYNOS5420_GPIO_X24,
- EXYNOS5420_GPIO_X25,
- EXYNOS5420_GPIO_X26,
- EXYNOS5420_GPIO_X27,
- EXYNOS5420_GPIO_X30, /* 104 0x68 */
- EXYNOS5420_GPIO_X31,
- EXYNOS5420_GPIO_X32,
- EXYNOS5420_GPIO_X33,
- EXYNOS5420_GPIO_X34,
- EXYNOS5420_GPIO_X35,
- EXYNOS5420_GPIO_X36,
- EXYNOS5420_GPIO_X37,
-
- /* GPIO PART 4 STARTS*/
- EXYNOS5420_GPIO_MAX_PORT_PART_3,/* 112 0x70 */
- EXYNOS5420_GPIO_C00 = EXYNOS5420_GPIO_MAX_PORT_PART_3,
- EXYNOS5420_GPIO_C01,
- EXYNOS5420_GPIO_C02,
- EXYNOS5420_GPIO_C03,
- EXYNOS5420_GPIO_C04,
- EXYNOS5420_GPIO_C05,
- EXYNOS5420_GPIO_C06,
- EXYNOS5420_GPIO_C07,
- EXYNOS5420_GPIO_C10, /* 120 0x78 */
- EXYNOS5420_GPIO_C11,
- EXYNOS5420_GPIO_C12,
- EXYNOS5420_GPIO_C13,
- EXYNOS5420_GPIO_C14,
- EXYNOS5420_GPIO_C15,
- EXYNOS5420_GPIO_C16,
- EXYNOS5420_GPIO_C17,
- EXYNOS5420_GPIO_C20, /* 128 0x80 */
- EXYNOS5420_GPIO_C21,
- EXYNOS5420_GPIO_C22,
- EXYNOS5420_GPIO_C23,
- EXYNOS5420_GPIO_C24,
- EXYNOS5420_GPIO_C25,
- EXYNOS5420_GPIO_C26,
- EXYNOS5420_GPIO_C27,
- EXYNOS5420_GPIO_C30, /* 136 0x88 */
- EXYNOS5420_GPIO_C31,
- EXYNOS5420_GPIO_C32,
- EXYNOS5420_GPIO_C33,
- EXYNOS5420_GPIO_C34,
- EXYNOS5420_GPIO_C35,
- EXYNOS5420_GPIO_C36,
- EXYNOS5420_GPIO_C37,
- EXYNOS5420_GPIO_C40, /* 144 0x90 */
- EXYNOS5420_GPIO_C41,
- EXYNOS5420_GPIO_C42,
- EXYNOS5420_GPIO_C43,
- EXYNOS5420_GPIO_C44,
- EXYNOS5420_GPIO_C45,
- EXYNOS5420_GPIO_C46,
- EXYNOS5420_GPIO_C47,
- EXYNOS5420_GPIO_D10, /* 152 0x98 */
- EXYNOS5420_GPIO_D11,
- EXYNOS5420_GPIO_D12,
- EXYNOS5420_GPIO_D13,
- EXYNOS5420_GPIO_D14,
- EXYNOS5420_GPIO_D15,
- EXYNOS5420_GPIO_D16,
- EXYNOS5420_GPIO_D17,
- EXYNOS5420_GPIO_Y00, /* 160 0xa0 */
- EXYNOS5420_GPIO_Y01,
- EXYNOS5420_GPIO_Y02,
- EXYNOS5420_GPIO_Y03,
- EXYNOS5420_GPIO_Y04,
- EXYNOS5420_GPIO_Y05,
- EXYNOS5420_GPIO_Y06,
- EXYNOS5420_GPIO_Y07,
- EXYNOS5420_GPIO_Y10, /* 168 0xa8 */
- EXYNOS5420_GPIO_Y11,
- EXYNOS5420_GPIO_Y12,
- EXYNOS5420_GPIO_Y13,
- EXYNOS5420_GPIO_Y14,
- EXYNOS5420_GPIO_Y15,
- EXYNOS5420_GPIO_Y16,
- EXYNOS5420_GPIO_Y17,
- EXYNOS5420_GPIO_Y20, /* 176 0xb0 */
- EXYNOS5420_GPIO_Y21,
- EXYNOS5420_GPIO_Y22,
- EXYNOS5420_GPIO_Y23,
- EXYNOS5420_GPIO_Y24,
- EXYNOS5420_GPIO_Y25,
- EXYNOS5420_GPIO_Y26,
- EXYNOS5420_GPIO_Y27,
- EXYNOS5420_GPIO_Y30, /* 184 0xb8 */
- EXYNOS5420_GPIO_Y31,
- EXYNOS5420_GPIO_Y32,
- EXYNOS5420_GPIO_Y33,
- EXYNOS5420_GPIO_Y34,
- EXYNOS5420_GPIO_Y35,
- EXYNOS5420_GPIO_Y36,
- EXYNOS5420_GPIO_Y37,
- EXYNOS5420_GPIO_Y40, /* 192 0xc0 */
- EXYNOS5420_GPIO_Y41,
- EXYNOS5420_GPIO_Y42,
- EXYNOS5420_GPIO_Y43,
- EXYNOS5420_GPIO_Y44,
- EXYNOS5420_GPIO_Y45,
- EXYNOS5420_GPIO_Y46,
- EXYNOS5420_GPIO_Y47,
- EXYNOS5420_GPIO_Y50, /* 200 0xc8 */
- EXYNOS5420_GPIO_Y51,
- EXYNOS5420_GPIO_Y52,
- EXYNOS5420_GPIO_Y53,
- EXYNOS5420_GPIO_Y54,
- EXYNOS5420_GPIO_Y55,
- EXYNOS5420_GPIO_Y56,
- EXYNOS5420_GPIO_Y57,
- EXYNOS5420_GPIO_Y60, /* 208 0xd0 */
- EXYNOS5420_GPIO_Y61,
- EXYNOS5420_GPIO_Y62,
- EXYNOS5420_GPIO_Y63,
- EXYNOS5420_GPIO_Y64,
- EXYNOS5420_GPIO_Y65,
- EXYNOS5420_GPIO_Y66,
- EXYNOS5420_GPIO_Y67,
-
- /* GPIO_PART5_STARTS */
- EXYNOS5420_GPIO_MAX_PORT_PART_4,/* 216 0xd8 */
- EXYNOS5420_GPIO_E00 = EXYNOS5420_GPIO_MAX_PORT_PART_4,
- EXYNOS5420_GPIO_E01,
- EXYNOS5420_GPIO_E02,
- EXYNOS5420_GPIO_E03,
- EXYNOS5420_GPIO_E04,
- EXYNOS5420_GPIO_E05,
- EXYNOS5420_GPIO_E06,
- EXYNOS5420_GPIO_E07,
- EXYNOS5420_GPIO_E10, /* 224 0xe0 */
- EXYNOS5420_GPIO_E11,
- EXYNOS5420_GPIO_E12,
- EXYNOS5420_GPIO_E13,
- EXYNOS5420_GPIO_E14,
- EXYNOS5420_GPIO_E15,
- EXYNOS5420_GPIO_E16,
- EXYNOS5420_GPIO_E17,
- EXYNOS5420_GPIO_F00, /* 232 0xe8 */
- EXYNOS5420_GPIO_F01,
- EXYNOS5420_GPIO_F02,
- EXYNOS5420_GPIO_F03,
- EXYNOS5420_GPIO_F04,
- EXYNOS5420_GPIO_F05,
- EXYNOS5420_GPIO_F06,
- EXYNOS5420_GPIO_F07,
- EXYNOS5420_GPIO_F10, /* 240 0xf0 */
- EXYNOS5420_GPIO_F11,
- EXYNOS5420_GPIO_F12,
- EXYNOS5420_GPIO_F13,
- EXYNOS5420_GPIO_F14,
- EXYNOS5420_GPIO_F15,
- EXYNOS5420_GPIO_F16,
- EXYNOS5420_GPIO_F17,
- EXYNOS5420_GPIO_G00, /* 248 0xf8 */
- EXYNOS5420_GPIO_G01,
- EXYNOS5420_GPIO_G02,
- EXYNOS5420_GPIO_G03,
- EXYNOS5420_GPIO_G04,
- EXYNOS5420_GPIO_G05,
- EXYNOS5420_GPIO_G06,
- EXYNOS5420_GPIO_G07,
- EXYNOS5420_GPIO_G10, /* 256 0x100 */
- EXYNOS5420_GPIO_G11,
- EXYNOS5420_GPIO_G12,
- EXYNOS5420_GPIO_G13,
- EXYNOS5420_GPIO_G14,
- EXYNOS5420_GPIO_G15,
- EXYNOS5420_GPIO_G16,
- EXYNOS5420_GPIO_G17,
- EXYNOS5420_GPIO_G20, /* 264 0x108 */
- EXYNOS5420_GPIO_G21,
- EXYNOS5420_GPIO_G22,
- EXYNOS5420_GPIO_G23,
- EXYNOS5420_GPIO_G24,
- EXYNOS5420_GPIO_G25,
- EXYNOS5420_GPIO_G26,
- EXYNOS5420_GPIO_G27,
- EXYNOS5420_GPIO_J40, /* 272 0x110 */
- EXYNOS5420_GPIO_J41,
- EXYNOS5420_GPIO_J42,
- EXYNOS5420_GPIO_J43,
- EXYNOS5420_GPIO_J44,
- EXYNOS5420_GPIO_J45,
- EXYNOS5420_GPIO_J46,
- EXYNOS5420_GPIO_J47,
-
- /* GPIO_PART6_STARTS */
- EXYNOS5420_GPIO_MAX_PORT_PART_5,/* 280 0x118 */
- EXYNOS5420_GPIO_Z0 = EXYNOS5420_GPIO_MAX_PORT_PART_5,
- EXYNOS5420_GPIO_Z1,
- EXYNOS5420_GPIO_Z2,
- EXYNOS5420_GPIO_Z3,
- EXYNOS5420_GPIO_Z4,
- EXYNOS5420_GPIO_Z5,
- EXYNOS5420_GPIO_Z6,
- EXYNOS5420_GPIO_MAX_PORT
-};
-
-struct gpio_info {
- unsigned int reg_addr; /* Address of register for this part */
- unsigned int max_gpio; /* Maximum GPIO in this part */
-};
-
-#define EXYNOS4_GPIO_NUM_PARTS 4
-static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = {
- { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
- { EXYNOS4_GPIO_PART2_0, EXYNOS4_GPIO_MAX_PORT_PART_2_0 },
- { EXYNOS4_GPIO_PART2_1, EXYNOS4_GPIO_MAX_PORT_PART_2_1 },
- { EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT },
-};
-
-#define EXYNOS4X12_GPIO_NUM_PARTS 8
-static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = {
- { EXYNOS4X12_GPIO_PART1_0, EXYNOS4X12_GPIO_MAX_PORT_PART_1_0 },
- { EXYNOS4X12_GPIO_PART1_1, EXYNOS4X12_GPIO_MAX_PORT_PART_1_1 },
- { EXYNOS4X12_GPIO_PART1_2, EXYNOS4X12_GPIO_MAX_PORT_PART_1_2 },
- { EXYNOS4X12_GPIO_PART2_1, EXYNOS4X12_GPIO_MAX_PORT_PART_2_1 },
- { EXYNOS4X12_GPIO_PART2_2, EXYNOS4X12_GPIO_MAX_PORT_PART_2_2 },
- { EXYNOS4X12_GPIO_PART2_3, EXYNOS4X12_GPIO_MAX_PORT_PART_2_3 },
- { EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 },
- { EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT },
-};
-
-#define EXYNOS5_GPIO_NUM_PARTS 8
-static struct gpio_info exynos5_gpio_data[EXYNOS5_GPIO_NUM_PARTS] = {
- { EXYNOS5_GPIO_PART1_BASE, EXYNOS5_GPIO_MAX_PORT_PART_1 },
- { EXYNOS5_GPIO_PART2_BASE, EXYNOS5_GPIO_MAX_PORT_PART_2 },
- { EXYNOS5_GPIO_PART3_BASE, EXYNOS5_GPIO_MAX_PORT_PART_3 },
- { EXYNOS5_GPIO_PART4_BASE, EXYNOS5_GPIO_MAX_PORT_PART_4 },
- { EXYNOS5_GPIO_PART5_BASE, EXYNOS5_GPIO_MAX_PORT_PART_5 },
- { EXYNOS5_GPIO_PART6_BASE, EXYNOS5_GPIO_MAX_PORT_PART_6 },
- { EXYNOS5_GPIO_PART7_BASE, EXYNOS5_GPIO_MAX_PORT_PART_7 },
- { EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT },
-};
-
-#define EXYNOS5420_GPIO_NUM_PARTS 6
-static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = {
- { EXYNOS5420_GPIO_PART1_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_1 },
- { EXYNOS5420_GPIO_PART2_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_2 },
- { EXYNOS5420_GPIO_PART3_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_3 },
- { EXYNOS5420_GPIO_PART4_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_4 },
- { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_5 },
- { EXYNOS5420_GPIO_PART6_BASE, EXYNOS5420_GPIO_MAX_PORT },
-};
-
-static inline struct gpio_info *get_gpio_data(void)
-{
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_gpio_data;
- else
- return exynos5_gpio_data;
- } else if (cpu_is_exynos4()) {
- if (proid_is_exynos4412())
- return exynos4x12_gpio_data;
- else
- return exynos4_gpio_data;
- }
-
- return NULL;
-}
-
-static inline unsigned int get_bank_num(void)
-{
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return EXYNOS5420_GPIO_NUM_PARTS;
- else
- return EXYNOS5_GPIO_NUM_PARTS;
- } else if (cpu_is_exynos4()) {
- if (proid_is_exynos4412())
- return EXYNOS4X12_GPIO_NUM_PARTS;
- else
- return EXYNOS4_GPIO_NUM_PARTS;
- }
-
- return 0;
-}
-
-/*
- * This structure helps mapping symbolic GPIO names into indices from
- * exynos5_gpio_pin/exynos5420_gpio_pin enums.
- *
- * By convention, symbolic GPIO name is defined as follows:
- *
- * g[p]<bank><set><bit>, where
- * p is optional
- * <bank> - a single character bank name, as defined by the SOC
- * <set> - a single digit set number
- * <bit> - bit number within the set (in 0..7 range).
- *
- * <set><bit> essentially form an octal number of the GPIO pin within the bank
- * space. On the 5420 architecture some banks' sets do not start not from zero
- * ('d' starts from 1 and 'j' starts from 4). To compensate for that and
- * maintain flat number space withoout holes, those banks use offsets to be
- * deducted from the pin number.
- */
-struct gpio_name_num_table {
- char bank; /* bank name symbol */
- unsigned int bank_size; /* total number of pins in the bank */
- char bank_offset; /* offset of the first bank's pin */
- unsigned int base; /* index of the first bank's pin in the enum */
-};
-
-#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base }
-static const struct gpio_name_num_table exynos4_gpio_table[] = {
- GPIO_ENTRY('a', EXYNOS4_GPIO_A00, EXYNOS4_GPIO_B0, 0),
- GPIO_ENTRY('b', EXYNOS4_GPIO_B0, EXYNOS4_GPIO_C00, 0),
- GPIO_ENTRY('c', EXYNOS4_GPIO_C00, EXYNOS4_GPIO_D00, 0),
- GPIO_ENTRY('d', EXYNOS4_GPIO_D00, EXYNOS4_GPIO_E00, 0),
- GPIO_ENTRY('e', EXYNOS4_GPIO_E00, EXYNOS4_GPIO_F00, 0),
- GPIO_ENTRY('f', EXYNOS4_GPIO_F00, EXYNOS4_GPIO_J00, 0),
- GPIO_ENTRY('j', EXYNOS4_GPIO_J00, EXYNOS4_GPIO_K00, 0),
- GPIO_ENTRY('k', EXYNOS4_GPIO_K00, EXYNOS4_GPIO_L00, 0),
- GPIO_ENTRY('l', EXYNOS4_GPIO_L00, EXYNOS4_GPIO_Y00, 0),
- GPIO_ENTRY('y', EXYNOS4_GPIO_Y00, EXYNOS4_GPIO_X00, 0),
- GPIO_ENTRY('x', EXYNOS4_GPIO_X00, EXYNOS4_GPIO_Z0, 0),
- GPIO_ENTRY('z', EXYNOS4_GPIO_Z0, EXYNOS4_GPIO_MAX_PORT, 0),
- { 0 }
-};
-
-static const struct gpio_name_num_table exynos4x12_gpio_table[] = {
- GPIO_ENTRY('a', EXYNOS4X12_GPIO_A00, EXYNOS4X12_GPIO_B0, 0),
- GPIO_ENTRY('b', EXYNOS4X12_GPIO_B0, EXYNOS4X12_GPIO_C00, 0),
- GPIO_ENTRY('c', EXYNOS4X12_GPIO_C00, EXYNOS4X12_GPIO_D00, 0),
- GPIO_ENTRY('d', EXYNOS4X12_GPIO_D00, EXYNOS4X12_GPIO_F00, 0),
- GPIO_ENTRY('f', EXYNOS4X12_GPIO_F00, EXYNOS4X12_GPIO_J00, 0),
- GPIO_ENTRY('j', EXYNOS4X12_GPIO_J00, EXYNOS4X12_GPIO_K00, 0),
- GPIO_ENTRY('k', EXYNOS4X12_GPIO_K00, EXYNOS4X12_GPIO_L00, 0),
- GPIO_ENTRY('l', EXYNOS4X12_GPIO_L00, EXYNOS4X12_GPIO_Y00, 0),
- GPIO_ENTRY('y', EXYNOS4X12_GPIO_Y00, EXYNOS4X12_GPIO_M00, 0),
- GPIO_ENTRY('m', EXYNOS4X12_GPIO_M00, EXYNOS4X12_GPIO_X00, 0),
- GPIO_ENTRY('x', EXYNOS4X12_GPIO_X00, EXYNOS4X12_GPIO_Z0, 0),
- GPIO_ENTRY('z', EXYNOS4X12_GPIO_Z0, EXYNOS4X12_GPIO_V00, 0),
- GPIO_ENTRY('v', EXYNOS4X12_GPIO_V00, EXYNOS4X12_GPIO_MAX_PORT, 0),
- { 0 }
-};
-
-static const struct gpio_name_num_table exynos5_gpio_table[] = {
- GPIO_ENTRY('a', EXYNOS5_GPIO_A00, EXYNOS5_GPIO_B00, 0),
- GPIO_ENTRY('b', EXYNOS5_GPIO_B00, EXYNOS5_GPIO_C00, 0),
- GPIO_ENTRY('c', EXYNOS5_GPIO_C00, EXYNOS5_GPIO_D00, 0),
- GPIO_ENTRY('d', EXYNOS5_GPIO_D00, EXYNOS5_GPIO_Y00, 0),
- GPIO_ENTRY('y', EXYNOS5_GPIO_Y00, EXYNOS5_GPIO_C40, 0),
- GPIO_ENTRY('x', EXYNOS5_GPIO_X00, EXYNOS5_GPIO_E00, 0),
- GPIO_ENTRY('e', EXYNOS5_GPIO_E00, EXYNOS5_GPIO_F00, 0),
- GPIO_ENTRY('f', EXYNOS5_GPIO_F00, EXYNOS5_GPIO_G00, 0),
- GPIO_ENTRY('g', EXYNOS5_GPIO_G00, EXYNOS5_GPIO_H00, 0),
- GPIO_ENTRY('h', EXYNOS5_GPIO_H00, EXYNOS5_GPIO_V00, 0),
- GPIO_ENTRY('v', EXYNOS5_GPIO_V00, EXYNOS5_GPIO_Z0, 0),
- GPIO_ENTRY('z', EXYNOS5_GPIO_Z0, EXYNOS5_GPIO_MAX_PORT, 0),
- { 0 }
-};
-
-static const struct gpio_name_num_table exynos5420_gpio_table[] = {
- GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0),
- GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0),
- GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Y70, 0),
- GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0),
- GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0),
- GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 010),
- GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0),
- GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0),
- GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0),
- GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0),
- GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_Z0, 040),
- GPIO_ENTRY('z', EXYNOS5420_GPIO_Z0, EXYNOS5420_GPIO_MAX_PORT, 0),
- { 0 }
-};
-
-void gpio_cfg_pin(int gpio, int cfg);
-void gpio_set_pull(int gpio, int mode);
-void gpio_set_drv(int gpio, int mode);
-void gpio_set_rate(int gpio, int mode);
-int s5p_gpio_get_pin(unsigned gpio);
-#endif
-
-/* Pin configurations */
-#define S5P_GPIO_INPUT 0x0
-#define S5P_GPIO_OUTPUT 0x1
-#define S5P_GPIO_IRQ 0xf
-#define S5P_GPIO_FUNC(x) (x)
-
-/* Pull mode */
-#define S5P_GPIO_PULL_NONE 0x0
-#define S5P_GPIO_PULL_DOWN 0x1
-#define S5P_GPIO_PULL_UP 0x3
-
-/* Drive Strength level */
-#define S5P_GPIO_DRV_1X 0x0
-#define S5P_GPIO_DRV_3X 0x1
-#define S5P_GPIO_DRV_2X 0x2
-#define S5P_GPIO_DRV_4X 0x3
-#define S5P_GPIO_DRV_FAST 0x0
-#define S5P_GPIO_DRV_SLOW 0x1
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- * R. Chandrasekar <rcsekar@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __I2S_REGS_H__
-#define __I2S_REGS_H__
-
-#define CON_RESET (1 << 31)
-#define CON_TXFIFO_FULL (1 << 8)
-#define CON_TXCH_PAUSE (1 << 4)
-#define CON_ACTIVE (1 << 0)
-
-#define MOD_OP_CLK (3 << 30)
-#define MOD_BLCP_SHIFT 24
-#define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT)
-#define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT)
-#define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT)
-#define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT)
-
-#define MOD_BLC_16BIT (0 << 13)
-#define MOD_BLC_8BIT (1 << 13)
-#define MOD_BLC_24BIT (2 << 13)
-#define MOD_BLC_MASK (3 << 13)
-
-#define MOD_SLAVE (1 << 11)
-#define MOD_RCLKSRC (0 << 10)
-#define MOD_MASK (3 << 8)
-#define MOD_LR_LLOW (0 << 7)
-#define MOD_LR_RLOW (1 << 7)
-#define MOD_SDF_IIS (0 << 5)
-#define MOD_SDF_MSB (1 << 5)
-#define MOD_SDF_LSB (2 << 5)
-#define MOD_SDF_MASK (3 << 5)
-#define MOD_RCLK_256FS (0 << 3)
-#define MOD_RCLK_512FS (1 << 3)
-#define MOD_RCLK_384FS (2 << 3)
-#define MOD_RCLK_768FS (3 << 3)
-#define MOD_RCLK_MASK (3 << 3)
-#define MOD_BCLK_32FS (0 << 1)
-#define MOD_BCLK_48FS (1 << 1)
-#define MOD_BCLK_16FS (2 << 1)
-#define MOD_BCLK_24FS (3 << 1)
-#define MOD_BCLK_MASK (3 << 1)
-
-#define MOD_CDCLKCON (1 << 12)
-
-#define FIC_TXFLUSH (1 << 15)
-#define FIC_RXFLUSH (1 << 7)
-
-#define PSREN (1 << 15)
-#define PSVAL (3 << 8)
-
-#endif /* __I2S_REGS_H__ */
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: InKi Dae <inki.dae@samsung.com>
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _DSIM_H
-#define _DSIM_H
-
-#include <linux/list.h>
-#include <linux/fb.h>
-#include <lcd.h>
-
-#define PANEL_NAME_SIZE (32)
-
-enum mipi_dsim_interface_type {
- DSIM_COMMAND,
- DSIM_VIDEO
-};
-
-enum mipi_dsim_virtual_ch_no {
- DSIM_VIRTUAL_CH_0,
- DSIM_VIRTUAL_CH_1,
- DSIM_VIRTUAL_CH_2,
- DSIM_VIRTUAL_CH_3
-};
-
-enum mipi_dsim_burst_mode_type {
- DSIM_NON_BURST_SYNC_EVENT,
- DSIM_BURST_SYNC_EVENT,
- DSIM_NON_BURST_SYNC_PULSE,
- DSIM_BURST,
- DSIM_NON_VIDEO_MODE
-};
-
-enum mipi_dsim_no_of_data_lane {
- DSIM_DATA_LANE_1,
- DSIM_DATA_LANE_2,
- DSIM_DATA_LANE_3,
- DSIM_DATA_LANE_4
-};
-
-enum mipi_dsim_byte_clk_src {
- DSIM_PLL_OUT_DIV8,
- DSIM_EXT_CLK_DIV8,
- DSIM_EXT_CLK_BYPASS
-};
-
-enum mipi_dsim_pixel_format {
- DSIM_CMD_3BPP,
- DSIM_CMD_8BPP,
- DSIM_CMD_12BPP,
- DSIM_CMD_16BPP,
- DSIM_VID_16BPP_565,
- DSIM_VID_18BPP_666PACKED,
- DSIM_18BPP_666LOOSELYPACKED,
- DSIM_24BPP_888
-};
-
-/* MIPI DSI Processor-to-Peripheral transaction types */
-enum {
- MIPI_DSI_V_SYNC_START = 0x01,
- MIPI_DSI_V_SYNC_END = 0x11,
- MIPI_DSI_H_SYNC_START = 0x21,
- MIPI_DSI_H_SYNC_END = 0x31,
-
- MIPI_DSI_COLOR_MODE_OFF = 0x02,
- MIPI_DSI_COLOR_MODE_ON = 0x12,
- MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
- MIPI_DSI_TURN_ON_PERIPHERAL = 0x32,
-
- MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03,
- MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13,
- MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23,
-
- MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04,
- MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14,
- MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24,
-
- MIPI_DSI_DCS_SHORT_WRITE = 0x05,
- MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
-
- MIPI_DSI_DCS_READ = 0x06,
-
- MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
-
- MIPI_DSI_END_OF_TRANSMISSION = 0x08,
-
- MIPI_DSI_NULL_PACKET = 0x09,
- MIPI_DSI_BLANKING_PACKET = 0x19,
- MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
- MIPI_DSI_DCS_LONG_WRITE = 0x39,
-
- MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
- MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
- MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
-
- MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d,
- MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d,
- MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d,
-
- MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e,
- MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e,
- MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e,
- MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e,
-};
-
-/*
- * struct mipi_dsim_config - interface for configuring mipi-dsi controller.
- *
- * @auto_flush: enable or disable Auto flush of MD FIFO using VSYNC pulse.
- * @eot_disable: enable or disable EoT packet in HS mode.
- * @auto_vertical_cnt: specifies auto vertical count mode.
- * in Video mode, the vertical line transition uses line counter
- * configured by VSA, VBP, and Vertical resolution.
- * If this bit is set to '1', the line counter does not use VSA and VBP
- * registers.(in command mode, this variable is ignored)
- * @hse: set horizontal sync event mode.
- * In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC
- * start packet to MIPI DSI slave at MIPI DSI spec1.1r02.
- * this bit transfers HSYNC end packet in VSYNC pulse and Vporch area
- * (in mommand mode, this variable is ignored)
- * @hfp: specifies HFP disable mode.
- * if this variable is set, DSI master ignores HFP area in VIDEO mode.
- * (in command mode, this variable is ignored)
- * @hbp: specifies HBP disable mode.
- * if this variable is set, DSI master ignores HBP area in VIDEO mode.
- * (in command mode, this variable is ignored)
- * @hsa: specifies HSA disable mode.
- * if this variable is set, DSI master ignores HSA area in VIDEO mode.
- * (in command mode, this variable is ignored)
- * @e_interface: specifies interface to be used.(CPU or RGB interface)
- * @e_virtual_ch: specifies virtual channel number that main or
- * sub diaplsy uses.
- * @e_pixel_format: specifies pixel stream format for main or sub display.
- * @e_burst_mode: selects Burst mode in Video mode.
- * in Non-burst mode, RGB data area is filled with RGB data and NULL
- * packets, according to input bandwidth of RGB interface.
- * In Burst mode, RGB data area is filled with RGB data only.
- * @e_no_data_lane: specifies data lane count to be used by Master.
- * @e_byte_clk: select byte clock source. (it must be DSIM_PLL_OUT_DIV8)
- * DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported.
- * @pll_stable_time: specifies the PLL Timer for stability of the ganerated
- * clock(System clock cycle base)
- * if the timer value goes to 0x00000000, the clock stable bit of status
- * and interrupt register is set.
- * @esc_clk: specifies escape clock frequency for getting the escape clock
- * prescaler value.
- * @stop_holding_cnt: specifies the interval value between transmitting
- * read packet(or write "set_tear_on" command) and BTA request.
- * after transmitting read packet or write "set_tear_on" command,
- * BTA requests to D-PHY automatically. this counter value specifies
- * the interval between them.
- * @bta_timeout: specifies the timer for BTA.
- * this register specifies time out from BTA request to change
- * the direction with respect to Tx escape clock.
- * @rx_timeout: specifies the timer for LP Rx mode timeout.
- * this register specifies time out on how long RxValid deasserts,
- * after RxLpdt asserts with respect to Tx escape clock.
- * - RxValid specifies Rx data valid indicator.
- * - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode.
- * - RxValid and RxLpdt specifies signal from D-PHY.
- */
-struct mipi_dsim_config {
- unsigned char auto_flush;
- unsigned char eot_disable;
-
- unsigned char auto_vertical_cnt;
- unsigned char hse;
- unsigned char hfp;
- unsigned char hbp;
- unsigned char hsa;
-
- enum mipi_dsim_interface_type e_interface;
- enum mipi_dsim_virtual_ch_no e_virtual_ch;
- enum mipi_dsim_pixel_format e_pixel_format;
- enum mipi_dsim_burst_mode_type e_burst_mode;
- enum mipi_dsim_no_of_data_lane e_no_data_lane;
- enum mipi_dsim_byte_clk_src e_byte_clk;
-
- /*
- * ===========================================
- * | P | M | S | MHz |
- * -------------------------------------------
- * | 3 | 100 | 3 | 100 |
- * | 3 | 100 | 2 | 200 |
- * | 3 | 63 | 1 | 252 |
- * | 4 | 100 | 1 | 300 |
- * | 4 | 110 | 1 | 330 |
- * | 12 | 350 | 1 | 350 |
- * | 3 | 100 | 1 | 400 |
- * | 4 | 150 | 1 | 450 |
- * | 6 | 118 | 1 | 472 |
- * | 3 | 120 | 1 | 480 |
- * | 12 | 250 | 0 | 500 |
- * | 4 | 100 | 0 | 600 |
- * | 3 | 81 | 0 | 648 |
- * | 3 | 88 | 0 | 704 |
- * | 3 | 90 | 0 | 720 |
- * | 3 | 100 | 0 | 800 |
- * | 12 | 425 | 0 | 850 |
- * | 4 | 150 | 0 | 900 |
- * | 12 | 475 | 0 | 950 |
- * | 6 | 250 | 0 | 1000 |
- * -------------------------------------------
- */
-
- /*
- * pms could be calculated as the following.
- * M * 24 / P * 2 ^ S = MHz
- */
- unsigned char p;
- unsigned short m;
- unsigned char s;
-
- unsigned int pll_stable_time;
- unsigned long esc_clk;
-
- unsigned short stop_holding_cnt;
- unsigned char bta_timeout;
- unsigned short rx_timeout;
-};
-
-/*
- * struct mipi_dsim_device - global interface for mipi-dsi driver.
- *
- * @dsim_config: infomation for configuring mipi-dsi controller.
- * @master_ops: callbacks to mipi-dsi operations.
- * @dsim_lcd_dev: pointer to activated ddi device.
- * (it would be registered by mipi-dsi driver.)
- * @dsim_lcd_drv: pointer to activated_ddi driver.
- * (it would be registered by mipi-dsi driver.)
- * @state: specifies status of MIPI-DSI controller.
- * the status could be RESET, INIT, STOP, HSCLKEN and ULPS.
- * @data_lane: specifiec enabled data lane number.
- * this variable would be set by driver according to e_no_data_lane
- * automatically.
- * @e_clk_src: select byte clock source.
- * @pd: pointer to MIPI-DSI driver platform data.
- */
-struct mipi_dsim_device {
- struct mipi_dsim_config *dsim_config;
- struct mipi_dsim_master_ops *master_ops;
- struct mipi_dsim_lcd_device *dsim_lcd_dev;
- struct mipi_dsim_lcd_driver *dsim_lcd_drv;
-
- unsigned int state;
- unsigned int data_lane;
- enum mipi_dsim_byte_clk_src e_clk_src;
-
- struct exynos_platform_mipi_dsim *pd;
-};
-
-/*
- * struct exynos_platform_mipi_dsim - interface to platform data
- * for mipi-dsi driver.
- *
- * @lcd_panel_name: specifies lcd panel name registered to mipi-dsi driver.
- * lcd panel driver searched would be actived.
- * @dsim_config: pointer of structure for configuring mipi-dsi controller.
- * @lcd_panel_info: pointer for lcd panel specific structure.
- * this structure specifies width, height, timing and polarity and so on.
- * @lcd_power: callback pointer for enabling or disabling lcd power.
- * @mipi_power: callback pointer for enabling or disabling mipi power.
- * @phy_enable: pointer to a callback controlling D-PHY enable/reset
- */
-struct exynos_platform_mipi_dsim {
- char lcd_panel_name[PANEL_NAME_SIZE];
-
- struct mipi_dsim_config *dsim_config;
- void *lcd_panel_info;
-
- int (*lcd_power)(void);
- int (*mipi_power)(void);
- void (*phy_enable)(unsigned int dev_index, unsigned int enable);
-};
-
-/*
- * struct mipi_dsim_master_ops - callbacks to mipi-dsi operations.
- *
- * @cmd_write: transfer command to lcd panel at LP mode.
- * @cmd_read: read command from rx register.
- * @get_dsim_frame_done: get the status that all screen data have been
- * transferred to mipi-dsi.
- * @clear_dsim_frame_done: clear frame done status.
- * @get_fb_frame_done: get frame done status of display controller.
- * @trigger: trigger display controller.
- * - this one would be used only in case of CPU mode.
- */
-struct mipi_dsim_master_ops {
- int (*cmd_write)(struct mipi_dsim_device *dsim, unsigned int data_id,
- const unsigned char *data0, unsigned int data1);
- int (*cmd_read)(struct mipi_dsim_device *dsim, unsigned int data_id,
- unsigned int data0, unsigned int data1);
- int (*get_dsim_frame_done)(struct mipi_dsim_device *dsim);
- int (*clear_dsim_frame_done)(struct mipi_dsim_device *dsim);
-
- int (*get_fb_frame_done)(void);
- void (*trigger)(struct fb_info *info);
-};
-
-/*
- * device structure for mipi-dsi based lcd panel.
- *
- * @name: name of the device to use with this device, or an
- * alias for that name.
- * @id: id of device to be registered.
- * @bus_id: bus id for identifing connected bus
- * and this bus id should be same as id of mipi_dsim_device.
- * @master: pointer to mipi-dsi master device object.
- * @platform_data: lcd panel specific platform data.
- */
-struct mipi_dsim_lcd_device {
- char *name;
- int id;
- int bus_id;
- int reverse_panel;
-
- struct mipi_dsim_device *master;
- void *platform_data;
-};
-
-/*
- * driver structure for mipi-dsi based lcd panel.
- *
- * this structure should be registered by lcd panel driver.
- * mipi-dsi driver seeks lcd panel registered through name field
- * and calls these callback functions in appropriate time.
- *
- * @name: name of the driver to use with this device, or an
- * alias for that name.
- * @id: id of driver to be registered.
- * this id would be used for finding device object registered.
- * @mipi_panel_init: callback pointer for initializing lcd panel based on mipi
- * dsi interface.
- * @mipi_display_on: callback pointer for lcd panel display on.
- */
-struct mipi_dsim_lcd_driver {
- char *name;
- int id;
-
- int (*mipi_panel_init)(struct mipi_dsim_device *dsim_dev);
- void (*mipi_display_on)(struct mipi_dsim_device *dsim_dev);
-};
-
-#ifdef CONFIG_EXYNOS_MIPI_DSIM
-int exynos_mipi_dsi_init(void);
-#else
-static inline int exynos_mipi_dsi_init(void)
-{
- return 0;
-}
-#endif
-
-/*
- * register mipi_dsim_lcd_driver object defined by lcd panel driver
- * to mipi-dsi driver.
- */
-int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver
- *lcd_drv);
-
-/*
- * register mipi_dsim_lcd_device to mipi-dsi master.
- */
-int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device
- *lcd_dev);
-
-void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd);
-void exynos_init_dsim_platform_data(vidinfo_t *vid);
-
-/* panel driver init based on mipi dsi interface */
-void s6e8ax0_init(void);
-
-#ifdef CONFIG_OF_CONTROL
-extern int mipi_power(void);
-#endif
-#endif /* _DSIM_H */
+++ /dev/null
-/*
- * (C) Copyright 2009 SAMSUNG Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_MMC_H_
-#define __ASM_ARCH_MMC_H_
-
-#define S5P_MMC_DEV_OFFSET 0x10000
-
-#define SDHCI_CONTROL2 0x80
-#define SDHCI_CONTROL3 0x84
-#define SDHCI_CONTROL4 0x8C
-
-#define SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31)
-#define SDHCI_CTRL2_ENCMDCNFMSK (1 << 30)
-#define SDHCI_CTRL2_CDINVRXD3 (1 << 29)
-#define SDHCI_CTRL2_SLCARDOUT (1 << 28)
-
-#define SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
-#define SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
-#define SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
-
-#define SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
-#define SDHCI_CTRL2_LVLDAT_SHIFT (16)
-#define SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
-
-#define SDHCI_CTRL2_ENFBCLKTX (1 << 15)
-#define SDHCI_CTRL2_ENFBCLKRX (1 << 14)
-#define SDHCI_CTRL2_SDCDSEL (1 << 13)
-#define SDHCI_CTRL2_SDSIGPC (1 << 12)
-#define SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11)
-
-#define SDHCI_CTRL2_DFCNT_MASK(_x) ((_x) << 9)
-#define SDHCI_CTRL2_DFCNT_SHIFT (9)
-
-#define SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8)
-#define SDHCI_CTRL2_RWAITMODE (1 << 7)
-#define SDHCI_CTRL2_DISBUFRD (1 << 6)
-#define SDHCI_CTRL2_SELBASECLK_MASK(_x) ((_x) << 4)
-#define SDHCI_CTRL2_SELBASECLK_SHIFT (4)
-#define SDHCI_CTRL2_PWRSYNC (1 << 3)
-#define SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1)
-#define SDHCI_CTRL2_HWINITFIN (1 << 0)
-
-#define SDHCI_CTRL3_FCSEL3 (1 << 31)
-#define SDHCI_CTRL3_FCSEL2 (1 << 23)
-#define SDHCI_CTRL3_FCSEL1 (1 << 15)
-#define SDHCI_CTRL3_FCSEL0 (1 << 7)
-
-#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16)
-#define SDHCI_CTRL4_DRIVE_SHIFT (16)
-
-#define SDHCI_MAX_HOSTS 4
-
-int s5p_sdhci_init(u32 regbase, int index, int bus_width);
-
-static inline int s5p_mmc_init(int index, int bus_width)
-{
- unsigned int base = samsung_get_base_mmc() +
- (S5P_MMC_DEV_OFFSET * index);
-
- return s5p_sdhci_init(base, index, bus_width);
-}
-
-#ifdef CONFIG_OF_CONTROL
-int exynos_mmc_init(const void *blob);
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- * Rajeshwari Shinde <rajeshwari.s@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_PERIPH_H
-#define __ASM_ARM_ARCH_PERIPH_H
-
-/*
- * Peripherals required for pinmux configuration. List will
- * grow with support for more devices getting added.
- * Numbering based on interrupt table.
- *
- */
-enum periph_id {
- PERIPH_ID_UART0 = 51,
- PERIPH_ID_UART1,
- PERIPH_ID_UART2,
- PERIPH_ID_UART3,
- PERIPH_ID_I2C0 = 56,
- PERIPH_ID_I2C1,
- PERIPH_ID_I2C2,
- PERIPH_ID_I2C3,
- PERIPH_ID_I2C4,
- PERIPH_ID_I2C5,
- PERIPH_ID_I2C6,
- PERIPH_ID_I2C7,
- PERIPH_ID_SPI0 = 68,
- PERIPH_ID_SPI1,
- PERIPH_ID_SPI2,
- PERIPH_ID_SDMMC0 = 75,
- PERIPH_ID_SDMMC1,
- PERIPH_ID_SDMMC2,
- PERIPH_ID_SDMMC3,
- PERIPH_ID_I2C8 = 87,
- PERIPH_ID_I2C9,
- PERIPH_ID_I2S0 = 98,
- PERIPH_ID_I2S1 = 99,
-
- /* Since following peripherals do
- * not have shared peripheral interrupts (SPIs)
- * they are numbered arbitiraly after the maximum
- * SPIs Exynos has (128)
- */
- PERIPH_ID_SROMC = 128,
- PERIPH_ID_SPI3,
- PERIPH_ID_SPI4,
- PERIPH_ID_SDMMC4,
- PERIPH_ID_PWM0,
- PERIPH_ID_PWM1,
- PERIPH_ID_PWM2,
- PERIPH_ID_PWM3,
- PERIPH_ID_PWM4,
- PERIPH_ID_DPHPD,
- PERIPH_ID_I2C10 = 203,
-
- PERIPH_ID_NONE = -1,
-};
-
-#endif /* __ASM_ARM_ARCH_PERIPH_H */
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- * Abhilash Kesavan <a.kesavan@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_PINMUX_H
-#define __ASM_ARM_ARCH_PINMUX_H
-
-#include "periph.h"
-
-/*
- * Flags for setting specific configarations of peripherals.
- * List will grow with support for more devices getting added.
- */
-enum {
- PINMUX_FLAG_NONE = 0x00000000,
-
- /* Flags for eMMC */
- PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */
-
- /* Flags for SROM controller */
- PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */
- PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
-
- /* Flags for I2C */
- PINMUX_FLAG_HS_MODE = 1 << 1, /* I2C High Speed Mode */
-};
-
-/**
- * Configures the pinmux for a particular peripheral.
- *
- * Each gpio can be configured in many different ways (4 bits on exynos)
- * such as "input", "output", "special function", "external interrupt"
- * etc. This function will configure the peripheral pinmux along with
- * pull-up/down and drive strength.
- *
- * @param peripheral peripheral to be configured
- * @param flags configure flags
- * @return 0 if ok, -1 on error (e.g. unsupported peripheral)
- */
-int exynos_pinmux_config(int peripheral, int flags);
-
-/**
- * Decode the peripheral id using the interrpt numbers.
- *
- * @param blob Device tree blob
- * @param node FDT I2C node to find
- * @return peripheral id if ok, PERIPH_ID_NONE on error
- */
-int pinmux_decode_periph_id(const void *blob, int node);
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2011 Samsung Electronics
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_POWER_H_
-#define __ASM_ARM_ARCH_POWER_H_
-
-#ifndef __ASSEMBLY__
-struct exynos4_power {
- unsigned int om_stat;
- unsigned char res1[0x8];
- unsigned int rtc_clko_sel;
- unsigned int gnss_rtc_out_ctrl;
- unsigned char res2[0x1ec];
- unsigned int system_power_down_ctrl;
- unsigned int res3;
- unsigned int system_power_down_option;
- unsigned char res4[0x1f4];
- unsigned int swreset;
- unsigned int rst_stat;
- unsigned char res5[0x1f8];
- unsigned int wakeup_stat;
- unsigned int eint_wakeup_mask;
- unsigned int wakeup_mask;
- unsigned char res6[0xf4];
- unsigned int hdmi_phy_control;
- unsigned int usbdevice_phy_control;
- unsigned int usbhost_phy_control;
- unsigned int dac_phy_control;
- unsigned int mipi_phy0_control;
- unsigned int mipi_phy1_control;
- unsigned int adc_phy_control;
- unsigned int pcie_phy_control;
- unsigned int sata_phy_control;
- unsigned char res7[0xdc];
- unsigned int inform0;
- unsigned int inform1;
- unsigned int inform2;
- unsigned int inform3;
- unsigned int inform4;
- unsigned int inform5;
- unsigned int inform6;
- unsigned int inform7;
- unsigned char res8[0x1e0];
- unsigned int pmu_debug;
- unsigned char res9[0x5fc];
- unsigned int arm_core0_sys_pwr_reg;
- unsigned char res10[0xc];
- unsigned int arm_core1_sys_pwr_reg;
- unsigned char res11[0x6c];
- unsigned int arm_common_sys_pwr_reg;
- unsigned char res12[0x3c];
- unsigned int arm_cpu_l2_0_sys_pwr_reg;
- unsigned int arm_cpu_l2_1_sys_pwr_reg;
- unsigned char res13[0x38];
- unsigned int cmu_aclkstop_sys_pwr_reg;
- unsigned int cmu_sclkstop_sys_pwr_reg;
- unsigned char res14[0x4];
- unsigned int cmu_reset_sys_pwr_reg;
- unsigned char res15[0x10];
- unsigned int apll_sysclk_sys_pwr_reg;
- unsigned int mpll_sysclk_sys_pwr_reg;
- unsigned int vpll_sysclk_sys_pwr_reg;
- unsigned int epll_sysclk_sys_pwr_reg;
- unsigned char res16[0x8];
- unsigned int cmu_clkstop_gps_alive_sys_pwr_reg;
- unsigned int cmu_reset_gps_alive_sys_pwr_reg;
- unsigned int cmu_clkstop_cam_sys_pwr_reg;
- unsigned int cmu_clkstop_tv_sys_pwr_reg;
- unsigned int cmu_clkstop_mfc_sys_pwr_reg;
- unsigned int cmu_clkstop_g3d_sys_pwr_reg;
- unsigned int cmu_clkstop_lcd0_sys_pwr_reg;
- unsigned int cmu_clkstop_lcd1_sys_pwr_reg;
- unsigned int cmu_clkstop_maudio_sys_pwr_reg;
- unsigned int cmu_clkstop_gps_sys_pwr_reg;
- unsigned int cmu_reset_cam_sys_pwr_reg;
- unsigned int cmu_reset_tv_sys_pwr_reg;
- unsigned int cmu_reset_mfc_sys_pwr_reg;
- unsigned int cmu_reset_g3d_sys_pwr_reg;
- unsigned int cmu_reset_lcd0_sys_pwr_reg;
- unsigned int cmu_reset_lcd1_sys_pwr_reg;
- unsigned int cmu_reset_maudio_sys_pwr_reg;
- unsigned int cmu_reset_gps_sys_pwr_reg;
- unsigned int top_bus_sys_pwr_reg;
- unsigned int top_retention_sys_pwr_reg;
- unsigned int top_pwr_sys_pwr_reg;
- unsigned char res17[0x1c];
- unsigned int logic_reset_sys_pwr_reg;
- unsigned char res18[0x14];
- unsigned int onenandxl_mem_sys_pwr_reg;
- unsigned int modemif_mem_sys_pwr_reg;
- unsigned char res19[0x4];
- unsigned int usbdevice_mem_sys_pwr_reg;
- unsigned int sdmmc_mem_sys_pwr_reg;
- unsigned int cssys_mem_sys_pwr_reg;
- unsigned int secss_mem_sys_pwr_reg;
- unsigned char res20[0x4];
- unsigned int pcie_mem_sys_pwr_reg;
- unsigned int sata_mem_sys_pwr_reg;
- unsigned char res21[0x18];
- unsigned int pad_retention_dram_sys_pwr_reg;
- unsigned int pad_retention_maudio_sys_pwr_reg;
- unsigned char res22[0x18];
- unsigned int pad_retention_gpio_sys_pwr_reg;
- unsigned int pad_retention_uart_sys_pwr_reg;
- unsigned int pad_retention_mmca_sys_pwr_reg;
- unsigned int pad_retention_mmcb_sys_pwr_reg;
- unsigned int pad_retention_ebia_sys_pwr_reg;
- unsigned int pad_retention_ebib_sys_pwr_reg;
- unsigned char res23[0x8];
- unsigned int pad_isolation_sys_pwr_reg;
- unsigned char res24[0x1c];
- unsigned int pad_alv_sel_sys_pwr_reg;
- unsigned char res25[0x1c];
- unsigned int xusbxti_sys_pwr_reg;
- unsigned int xxti_sys_pwr_reg;
- unsigned char res26[0x38];
- unsigned int ext_regulator_sys_pwr_reg;
- unsigned char res27[0x3c];
- unsigned int gpio_mode_sys_pwr_reg;
- unsigned char res28[0x3c];
- unsigned int gpio_mode_maudio_sys_pwr_reg;
- unsigned char res29[0x3c];
- unsigned int cam_sys_pwr_reg;
- unsigned int tv_sys_pwr_reg;
- unsigned int mfc_sys_pwr_reg;
- unsigned int g3d_sys_pwr_reg;
- unsigned int lcd0_sys_pwr_reg;
- unsigned int lcd1_sys_pwr_reg;
- unsigned int maudio_sys_pwr_reg;
- unsigned int gps_sys_pwr_reg;
- unsigned int gps_alive_sys_pwr_reg;
- unsigned char res30[0xc5c];
- unsigned int arm_core0_configuration;
- unsigned int arm_core0_status;
- unsigned int arm_core0_option;
- unsigned char res31[0x74];
- unsigned int arm_core1_configuration;
- unsigned int arm_core1_status;
- unsigned int arm_core1_option;
- unsigned char res32[0x37c];
- unsigned int arm_common_option;
- unsigned char res33[0x1f4];
- unsigned int arm_cpu_l2_0_configuration;
- unsigned int arm_cpu_l2_0_status;
- unsigned char res34[0x18];
- unsigned int arm_cpu_l2_1_configuration;
- unsigned int arm_cpu_l2_1_status;
- unsigned char res35[0xa00];
- unsigned int pad_retention_maudio_option;
- unsigned char res36[0xdc];
- unsigned int pad_retention_gpio_option;
- unsigned char res37[0x1c];
- unsigned int pad_retention_uart_option;
- unsigned char res38[0x1c];
- unsigned int pad_retention_mmca_option;
- unsigned char res39[0x1c];
- unsigned int pad_retention_mmcb_option;
- unsigned char res40[0x1c];
- unsigned int pad_retention_ebia_option;
- unsigned char res41[0x1c];
- unsigned int pad_retention_ebib_option;
- unsigned char res42[0x160];
- unsigned int ps_hold_control;
- unsigned char res43[0xf0];
- unsigned int xusbxti_configuration;
- unsigned int xusbxti_status;
- unsigned char res44[0x14];
- unsigned int xusbxti_duration;
- unsigned int xxti_configuration;
- unsigned int xxti_status;
- unsigned char res45[0x14];
- unsigned int xxti_duration;
- unsigned char res46[0x1dc];
- unsigned int ext_regulator_duration;
- unsigned char res47[0x5e0];
- unsigned int cam_configuration;
- unsigned int cam_status;
- unsigned int cam_option;
- unsigned char res48[0x14];
- unsigned int tv_configuration;
- unsigned int tv_status;
- unsigned int tv_option;
- unsigned char res49[0x14];
- unsigned int mfc_configuration;
- unsigned int mfc_status;
- unsigned int mfc_option;
- unsigned char res50[0x14];
- unsigned int g3d_configuration;
- unsigned int g3d_status;
- unsigned int g3d_option;
- unsigned char res51[0x14];
- unsigned int lcd0_configuration;
- unsigned int lcd0_status;
- unsigned int lcd0_option;
- unsigned char res52[0x14];
- unsigned int lcd1_configuration;
- unsigned int lcd1_status;
- unsigned int lcd1_option;
- unsigned char res53[0x34];
- unsigned int gps_configuration;
- unsigned int gps_status;
- unsigned int gps_option;
- unsigned char res54[0x14];
- unsigned int gps_alive_configuration;
- unsigned int gps_alive_status;
- unsigned int gps_alive_option;
-};
-
-struct exynos4412_power {
- unsigned char res1[0x0704];
- unsigned int usbhost_phy_control;
- unsigned int hsic1_phy_control;
- unsigned int hsic2_phy_control;
-};
-
-struct exynos5_power {
- unsigned int om_stat;
- unsigned char res1[0x18];
- unsigned int rtc_clko_sel;
- unsigned int gnss_rtc_out_ctrl;
- unsigned char res2[0x1dc];
- unsigned int central_seq_configuration;
- unsigned int central_seq_status;
- unsigned int central_seq_option;
- unsigned char res3[0x14];
- unsigned int seq_transition0;
- unsigned int seq_transition1;
- unsigned int seq_transition2;
- unsigned int seq_transition3;
- unsigned int seq_transition4;
- unsigned int seq_transition5;
- unsigned int seq_transition6;
- unsigned int seq_transition7;
- unsigned int central_seq_dmc_configuration;
- unsigned int central_seq_dmc_status;
- unsigned int central_seq_dmc_option;
- unsigned char res4[0x14];
- unsigned int seq_dmc_transition0;
- unsigned int seq_dmc_transition1;
- unsigned int seq_dmc_transition2;
- unsigned int seq_dmc_transition3;
- unsigned int seq_dmc_transition4;
- unsigned int seq_dmc_transition5;
- unsigned int seq_dmc_transition6;
- unsigned int seq_dmc_transition7;
- unsigned char res5[0x180];
- unsigned int swreset;
- unsigned int rst_stat;
- unsigned int automatic_wdt_reset_disable;
- unsigned int mask_wdt_reset_request;
- unsigned int mask_wreset_request;
- unsigned char res6[0xec];
- unsigned int reset_sequencer_configuration;
- unsigned int reset_sequencer_status;
- unsigned int reset_sequencer_option;
- unsigned char res7[0xf4];
- unsigned int wakeup_stat;
- unsigned int eint_wakeup_mask;
- unsigned int wakeup_mask;
- unsigned int wakeup_interrupt;
- unsigned char res8[0x10];
- unsigned int wakeup_stat_dmc;
- unsigned int eint_wakeup_mask_dmc;
- unsigned int wakeup_mask_dmc;
- unsigned int wakeup_interrupt_dmc;
- unsigned char res9[0xd0];
- unsigned int hdmi_phy_control;
- unsigned int usbdrd_phy_control;
- unsigned int usbhost_phy_control;
- unsigned int efnand_phy_control;
- unsigned int mipi_phy0_control;
- unsigned int mipi_phy1_control;
- unsigned int adc_phy_control;
- unsigned int mtcadc_phy_control;
- unsigned int dptx_phy_control;
- unsigned int sata_phy_control;
- unsigned char res10[0xd8];
- unsigned int inform0;
- unsigned int inform1;
- unsigned int inform2;
- unsigned int inform3;
- unsigned int sysip_dat0;
- unsigned int sysip_dat1;
- unsigned int sysip_dat2;
- unsigned int sysip_dat3;
- unsigned char res11[0xe0];
- unsigned int pmu_spare0;
- unsigned int pmu_spare1;
- unsigned int pmu_spare2;
- unsigned int pmu_spare3;
- unsigned char res12[0x70];
- unsigned int irom_data_reg0;
- unsigned int irom_data_reg1;
- unsigned int irom_data_reg2;
- unsigned int irom_data_reg3;
- unsigned char res13[0x70];
- unsigned int pmu_debug;
- unsigned char res14[0x5fc];
- unsigned int arm_core0_sys_pwr_reg;
- unsigned int dis_irq_arm_core0_local_sys_pwr_reg;
- unsigned int dis_irq_arm_core0_central_sys_pwr_reg;
- unsigned char res15[0x4];
- unsigned int arm_core1_sys_pwr_reg;
- unsigned int dis_irq_arm_core1_local_sys_pwr_reg;
- unsigned int dis_irq_arm_core1_central_sys_pwr_reg;
- unsigned char res16[0x24];
- unsigned int fsys_arm_sys_pwr_reg;
- unsigned int dis_irq_fsys_arm_local_sys_pwr_reg;
- unsigned int dis_irq_fsys_arm_central_sys_pwr_reg;
- unsigned char res17[0x4];
- unsigned int isp_arm_sys_pwr_reg;
- unsigned int dis_irq_isp_arm_local_sys_pwr_reg;
- unsigned int dis_irq_isp_arm_central_sys_pwr_reg;
- unsigned char res18[0x24];
- unsigned int arm_common_sys_pwr_reg;
- unsigned char res19[0x3c];
- unsigned int arm_l2_sys_pwr_reg;
- unsigned char res20[0x3c];
- unsigned int cmu_aclkstop_sys_pwr_reg;
- unsigned int cmu_sclkstop_sys_pwr_reg;
- unsigned char res21[0x4];
- unsigned int cmu_reset_sys_pwr_reg;
- unsigned char res22[0x10];
- unsigned int cmu_aclkstop_dmc_sys_pwr_reg;
- unsigned int cmu_sclkstop_dmc_sys_pwr_reg;
- unsigned char res23[0x4];
- unsigned int cmu_reset_dmc_sys_pwr_reg;
- unsigned char res24[0x8];
- unsigned int ddrphy_dlllock_sys_pwr_reg;
- unsigned char res25[0x4];
- unsigned int apll_sysclk_sys_pwr_reg;
- unsigned int mpll_sysclk_sys_pwr_reg;
- unsigned int vpll_sysclk_sys_pwr_reg;
- unsigned int epll_sysclk_sys_pwr_reg;
- unsigned int bpll_sysclk_sys_pwr_reg;
- unsigned int cpll_sysclk_sys_pwr_reg;
- unsigned int gpll_sysclk_sys_pwr_reg;
- unsigned char res26[0x8];
- unsigned int mplluser_sysclk_sys_pwr_reg;
- unsigned char res27[0x8];
- unsigned int bplluser_sysclk_sys_pwr_reg;
- unsigned char res28[0xc];
- unsigned int top_bus_sys_pwr_reg;
- unsigned int top_retention_sys_pwr_reg;
- unsigned int top_pwr_sys_pwr_reg;
- unsigned char res29[0x4];
- unsigned int top_bus_dmc_sys_pwr_reg;
- unsigned int top_retention_dmc_sys_pwr_reg;
- unsigned int top_pwr_dmc_sys_pwr_reg;
- unsigned char res30[0x4];
- unsigned int logic_reset_sys_pwr_reg;
- unsigned int oscclk_gate_sys_pwr_reg;
- unsigned char res31[0x8];
- unsigned int logic_reset_dmc_sys_pwr_reg;
- unsigned int oscclk_gate_dmc_sys_pwr_reg;
- unsigned char res32[0x8];
- unsigned int usbotg_mem_sys_pwr_reg;
- unsigned char res33[0x4];
- unsigned int g2d_mem_sys_pwr_reg;
- unsigned int usbdrd_mem_sys_pwr_reg;
- unsigned int efnand_mem_sys_pwr_reg;
- unsigned int cssys_mem_sys_pwr_reg;
- unsigned int secss_mem_sys_pwr_reg;
- unsigned int rotator_mem_sys_pwr_reg;
- unsigned int intram_mem_sys_pwr_reg;
- unsigned int introm_mem_sys_pwr_reg;
- unsigned int jpeg_mem_sys_pwr_reg;
- unsigned int hsi_mem_sys_pwr_reg;
- unsigned char res34[0x4];
- unsigned int mcuiop_mem_sys_pwr_reg;
- unsigned char res35[0x4];
- unsigned int sata_mem_sys_pwr_reg;
- unsigned int pad_retention_dram_sys_pwr_reg;
- unsigned int pad_retention_mau_sys_pwr_reg;
- unsigned int pad_retention_jtag_sys_pwr_reg;
- unsigned char res36[0xc];
- unsigned int pad_retention_mmc2_sys_pwr_reg;
- unsigned int pad_retention_mmc3_sys_pwr_reg;
- unsigned int pad_retention_gpio_sys_pwr_reg;
- unsigned int pad_retention_uart_sys_pwr_reg;
- unsigned int pad_retention_mmc0_sys_pwr_reg;
- unsigned int pad_retention_mmc1_sys_pwr_reg;
- unsigned int pad_retention_ebia_sys_pwr_reg;
- unsigned int pad_retention_ebib_sys_pwr_reg;
- unsigned int pad_retention_spi_sys_pwr_reg;
- unsigned int pad_retention_gpio_dmc_sys_pwr_reg;
- unsigned int pad_isolation_sys_pwr_reg;
- unsigned char res37[0xc];
- unsigned int pad_isolation_dmc_sys_pwr_reg;
- unsigned char res38[0xc];
- unsigned int pad_alv_sel_sys_pwr_reg;
- unsigned char res39[0x20];
- unsigned int xxti_sys_pwr_reg;
- unsigned char res40[0x38];
- unsigned int ext_regulator_sys_pwr_reg;
- unsigned char res41[0x3c];
- unsigned int gpio_mode_sys_pwr_reg;
- unsigned char res42[0x1c];
- unsigned int gpio_mode_dmc_sys_pwr_reg;
- unsigned char res43[0x1c];
- unsigned int gpio_mode_mau_sys_pwr_reg;
- unsigned int top_asb_reset_sys_pwr_reg;
- unsigned int top_asb_isolation_sys_pwr_reg;
- unsigned char res44[0xb4];
- unsigned int gscl_sys_pwr_reg;
- unsigned int isp_sys_pwr_reg;
- unsigned int mfc_sys_pwr_reg;
- unsigned int g3d_sys_pwr_reg;
- unsigned char res45[0x4];
- unsigned int disp1_sys_pwr_reg;
- unsigned int mau_sys_pwr_reg;
- unsigned char res46[0x64];
- unsigned int cmu_clkstop_gscl_sys_pwr_reg;
- unsigned int cmu_clkstop_isp_sys_pwr_reg;
- unsigned int cmu_clkstop_mfc_sys_pwr_reg;
- unsigned int cmu_clkstop_g3d_sys_pwr_reg;
- unsigned char res47[0x4];
- unsigned int cmu_clkstop_disp1_sys_pwr_reg;
- unsigned int cmu_clkstop_mau_sys_pwr_reg;
- unsigned char res48[0x24];
- unsigned int cmu_sysclk_gscl_sys_pwr_reg;
- unsigned int cmu_sysclk_isp_sys_pwr_reg;
- unsigned int cmu_sysclk_mfc_sys_pwr_reg;
- unsigned int cmu_sysclk_g3d_sys_pwr_reg;
- unsigned char res49[0x4];
- unsigned int cmu_sysclk_disp1_sys_pwr_reg;
- unsigned int cmu_sysclk_mau_sys_pwr_reg;
- unsigned char res50[0xa4];
- unsigned int cmu_reset_gscl_sys_pwr_reg;
- unsigned int cmu_reset_isp_sys_pwr_reg;
- unsigned int cmu_reset_mfc_sys_pwr_reg;
- unsigned int cmu_reset_g3d_sys_pwr_reg;
- unsigned char res51[0x4];
- unsigned int cmu_reset_disp1_sys_pwr_reg;
- unsigned int cmu_reset_mau_sys_pwr_reg;
- unsigned char res52[0xa64];
- unsigned int arm_core0_configuration;
- unsigned int arm_core0_status;
- unsigned int arm_core0_option;
- unsigned char res53[0x14];
- unsigned int dis_irq_arm_core0_local_configuration;
- unsigned int dis_irq_arm_core0_local_status;
- unsigned int dis_irq_arm_core0_local_option;
- unsigned char res54[0x14];
- unsigned int dis_irq_arm_core0_central_configuration;
- unsigned int dis_irq_arm_core0_central_status;
- unsigned int dis_irq_arm_core0_central_option;
- unsigned char res55[0x34];
- unsigned int arm_core1_configuration;
- unsigned int arm_core1_status;
- unsigned int arm_core1_option;
- unsigned char res56[0x14];
- unsigned int dis_irq_arm_core1_local_configuration;
- unsigned int dis_irq_arm_core1_local_status;
- unsigned int dis_irq_arm_core1_local_option;
- unsigned char res57[0x14];
- unsigned int dis_irq_arm_core1_central_configuration;
- unsigned int dis_irq_arm_core1_central_status;
- unsigned int dis_irq_arm_core1_central_option;
- unsigned char res58[0x134];
- unsigned int fsys_arm_configuration;
- unsigned int fsys_arm_status;
- unsigned int fsys_arm_option;
- unsigned char res59[0x14];
- unsigned int dis_irq_fsys_arm_local_configuration;
- unsigned int dis_irq_fsys_arm_local_status;
- unsigned int dis_irq_fsys_arm_local_option;
- unsigned char res60[0x14];
- unsigned int dis_irq_fsys_arm_central_configuration;
- unsigned int dis_irq_fsys_arm_central_status;
- unsigned int dis_irq_fsys_arm_central_option;
- unsigned char res61[0x34];
- unsigned int isp_arm_configuration;
- unsigned int isp_arm_status;
- unsigned int isp_arm_option;
- unsigned char res62[0x14];
- unsigned int dis_irq_isp_arm_local_configuration;
- unsigned int dis_irq_isp_arm_local_status;
- unsigned int dis_irq_isp_arm_local_option;
- unsigned char res63[0x14];
- unsigned int dis_irq_isp_arm_central_configuration;
- unsigned int dis_irq_isp_arm_central_status;
- unsigned int dis_irq_isp_arm_central_option;
- unsigned char res64[0x134];
- unsigned int arm_common_configuration;
- unsigned int arm_common_status;
- unsigned int arm_common_option;
- unsigned char res65[0x1f4];
- unsigned int arm_l2_configuration;
- unsigned int arm_l2_status;
- unsigned int arm_l2_option;
- unsigned char res66[0x1f4];
- unsigned int cmu_aclkstop_configuration;
- unsigned int cmu_aclkstop_status;
- unsigned int cmu_aclkstop_option;
- unsigned char res67[0x14];
- unsigned int cmu_sclkstop_configuration;
- unsigned int cmu_sclkstop_status;
- unsigned int cmu_sclkstop_option;
- unsigned char res68[0x34];
- unsigned int cmu_reset_configuration;
- unsigned int cmu_reset_status;
- unsigned int cmu_reset_option;
- unsigned char res69[0x94];
- unsigned int cmu_aclkstop_dmc_configuration;
- unsigned int cmu_aclkstop_dmc_status;
- unsigned int cmu_aclkstop_dmc_option;
- unsigned char res70[0x14];
- unsigned int cmu_sclkstop_dmc_configuration;
- unsigned int cmu_sclkstop_dmc_status;
- unsigned int cmu_sclkstop_dmc_option;
- unsigned char res71[0x34];
- unsigned int cmu_reset_dmc_configuration;
- unsigned int cmu_reset_dmc_status;
- unsigned int cmu_reset_dmc_option;
- unsigned char res72[0x54];
- unsigned int ddrphy_dlllock_configuration;
- unsigned int ddrphy_dlllock_status;
- unsigned int ddrphy_dlllock_option;
- unsigned char res73[0x34];
- unsigned int apll_sysclk_configuration;
- unsigned int apll_sysclk_status;
- unsigned int apll_sysclk_option;
- unsigned char res74[0x18];
- unsigned int mpll_sysclk_status;
- unsigned int mpll_sysclk_option;
- unsigned char res75[0x14];
- unsigned int vpll_sysclk_configuration;
- unsigned int vpll_sysclk_status;
- unsigned int vpll_sysclk_option;
- unsigned char res76[0x14];
- unsigned int epll_sysclk_configuration;
- unsigned int epll_sysclk_status;
- unsigned int epll_sysclk_option;
- unsigned char res77[0x14];
- unsigned int bpll_sysclk_configuration;
- unsigned int bpll_sysclk_status;
- unsigned int bpll_sysclk_option;
- unsigned char res78[0x14];
- unsigned int cpll_sysclk_configuration;
- unsigned int cpll_sysclk_status;
- unsigned int cpll_sysclk_option;
- unsigned char res79[0x14];
- unsigned int gpll_sysclk_configuration;
- unsigned int gpll_sysclk_status;
- unsigned int gpll_sysclk_option;
- unsigned char res80[0x54];
- unsigned int mplluser_sysclk_configuration;
- unsigned int mplluser_sysclk_status;
- unsigned int mplluser_sysclk_option;
- unsigned char res81[0x54];
- unsigned int bplluser_sysclk_configuration;
- unsigned int bplluser_sysclk_status;
- unsigned int bplluser_sysclk_option;
- unsigned char res82[0x74];
- unsigned int top_bus_configuration;
- unsigned int top_bus_status;
- unsigned int top_bus_option;
- unsigned char res83[0x14];
- unsigned int top_retention_configuration;
- unsigned int top_retention_status;
- unsigned int top_retention_option;
- unsigned char res84[0x14];
- unsigned int top_pwr_configuration;
- unsigned int top_pwr_status;
- unsigned int top_pwr_option;
- unsigned char res85[0x34];
- unsigned int top_bus_dmc_configuration;
- unsigned int top_bus_dmc_status;
- unsigned int top_bus_dmc_option;
- unsigned char res86[0x14];
- unsigned int top_retention_dmc_configuration;
- unsigned int top_retention_dmc_status;
- unsigned int top_retention_dmc_option;
- unsigned char res87[0x14];
- unsigned int top_pwr_dmc_configuration;
- unsigned int top_pwr_dmc_status;
- unsigned int top_pwr_dmc_option;
- unsigned char res88[0x34];
- unsigned int logic_reset_configuration;
- unsigned int logic_reset_status;
- unsigned int logic_reset_option;
- unsigned char res89[0x14];
- unsigned int oscclk_gate_configuration;
- unsigned int oscclk_gate_status;
- unsigned int oscclk_gate_option;
- unsigned char res90[0x54];
- unsigned int logic_reset_dmc_configuration;
- unsigned int logic_reset_dmc_status;
- unsigned int logic_reset_dmc_option;
- unsigned char res91[0x14];
- unsigned int oscclk_gate_dmc_configuration;
- unsigned int oscclk_gate_dmc_status;
- unsigned int oscclk_gate_dmc_option;
- unsigned char res92[0x54];
- unsigned int usbotg_mem_configuration;
- unsigned int usbotg_mem_status;
- unsigned int usbotg_mem_option;
- unsigned char res93[0x34];
- unsigned int g2d_mem_configuration;
- unsigned int g2d_mem_status;
- unsigned int g2d_mem_option;
- unsigned char res94[0x14];
- unsigned int usbdrd_mem_configuration;
- unsigned int usbdrd_mem_status;
- unsigned int usbdrd_mem_option;
- unsigned char res95[0x14];
- unsigned int efnand_mem_configuration;
- unsigned int efnand_mem_status;
- unsigned int efnand_mem_option;
- unsigned char res96[0x14];
- unsigned int cssys_mem_configuration;
- unsigned int cssys_mem_status;
- unsigned int cssys_mem_option;
- unsigned char res97[0x14];
- unsigned int secss_mem_configuration;
- unsigned int secss_mem_status;
- unsigned int secss_mem_option;
- unsigned char res98[0x14];
- unsigned int rotator_mem_configuration;
- unsigned int rotator_mem_status;
- unsigned int rotator_mem_option;
- unsigned char res99[0x14];
- unsigned int intram_mem_configuration;
- unsigned int intram_mem_status;
- unsigned int intram_mem_option;
- unsigned char res100[0x14];
- unsigned int introm_mem_configuration;
- unsigned int introm_mem_status;
- unsigned int introm_mem_option;
- unsigned char res101[0x14];
- unsigned int jpeg_mem_configuration;
- unsigned int jpeg_mem_status;
- unsigned int jpeg_mem_option;
- unsigned char res102[0x14];
- unsigned int hsi_mem_configuration;
- unsigned int hsi_mem_status;
- unsigned int hsi_mem_option;
- unsigned char res103[0x34];
- unsigned int mcuiop_mem_configuration;
- unsigned int mcuiop_mem_status;
- unsigned int mcuiop_mem_option;
- unsigned char res104[0x14];
- unsigned int sata_mem_configuration;
- unsigned int sata_mem_status;
- unsigned int sata_mem_option;
- unsigned char res105[0x34];
- unsigned int pad_retention_dram_configuration;
- unsigned int pad_retention_dram_status;
- unsigned int pad_retention_dram_option;
- unsigned char res106[0x14];
- unsigned int pad_retention_mau_configuration;
- unsigned int pad_retention_mau_status;
- unsigned int pad_retention_mau_option;
- unsigned char res107[0x14];
- unsigned int pad_retention_jtag_configuration;
- unsigned int pad_retention_jtag_status;
- unsigned int pad_retention_jtag_option;
- unsigned char res108[0x74];
- unsigned int pad_retention_mmc2_configuration;
- unsigned int pad_retention_mmc2_status;
- unsigned int pad_retention_mmc2_option;
- unsigned char res109[0x14];
- unsigned int pad_retention_mmc3_configuration;
- unsigned int pad_retention_mmc3_status;
- unsigned int pad_retention_mmc3_option;
- unsigned char res110[0x14];
- unsigned int pad_retention_gpio_configuration;
- unsigned int pad_retention_gpio_status;
- unsigned int pad_retention_gpio_option;
- unsigned char res111[0x14];
- unsigned int pad_retention_uart_configuration;
- unsigned int pad_retention_uart_status;
- unsigned int pad_retention_uart_option;
- unsigned char res112[0x14];
- unsigned int pad_retention_mmc0_configuration;
- unsigned int pad_retention_mmc0_status;
- unsigned int pad_retention_mmc0_option;
- unsigned char res113[0x14];
- unsigned int pad_retention_mmc1_configuration;
- unsigned int pad_retention_mmc1_status;
- unsigned int pad_retention_mmc1_option;
- unsigned char res114[0x14];
- unsigned int pad_retention_ebia_configuration;
- unsigned int pad_retention_ebia_status;
- unsigned int pad_retention_ebia_option;
- unsigned char res115[0x14];
- unsigned int pad_retention_ebib_configuration;
- unsigned int pad_retention_ebib_status;
- unsigned int pad_retention_ebib_option;
- unsigned char res116[0x14];
- unsigned int pad_retention_spi_configuration;
- unsigned int pad_retention_spi_status;
- unsigned int pad_retention_spi_option;
- unsigned char res117[0x14];
- unsigned int pad_retention_gpio_dmc_configuration;
- unsigned int pad_retention_gpio_dmc_status;
- unsigned int pad_retention_gpio_dmc_option;
- unsigned char res118[0x14];
- unsigned int pad_isolation_configuration;
- unsigned int pad_isolation_status;
- unsigned int pad_isolation_option;
- unsigned char res119[0x74];
- unsigned int pad_isolation_dmc_configuration;
- unsigned int pad_isolation_dmc_status;
- unsigned int pad_isolation_dmc_option;
- unsigned char res120[0x74];
- unsigned int pad_alv_sel_configuration;
- unsigned int pad_alv_sel_status;
- unsigned int pad_alv_sel_option0;
- unsigned int ps_hold_control;
- unsigned char res130[0x110];
- unsigned int xxti_configuration;
- unsigned int xxti_status;
- unsigned int xxti_option;
- unsigned char res131[0x10];
- unsigned int xxti_duration3;
- unsigned char res132[0x1c0];
- unsigned int ext_regulator_configuration;
- unsigned int ext_regulator_status;
- unsigned int ext_regulator_option;
- unsigned char res133[0x10];
- unsigned int ext_regulator_duration3;
- unsigned char res134[0x1e0];
- unsigned int gpio_mode_configuration;
- unsigned int gpio_mode_status;
- unsigned int gpio_mode_option;
- unsigned char res135[0xf4];
- unsigned int gpio_mode_dmc_configuration;
- unsigned int gpio_mode_dmc_status;
- unsigned int gpio_mode_dmc_option;
- unsigned char res136[0xd4];
- unsigned int gpio_mode_mau_configuration;
- unsigned int gpio_mode_mau_status;
- unsigned int gpio_mode_mau_option;
- unsigned char res137[0x14];
- unsigned int top_asb_reset_configuration;
- unsigned int top_asb_reset_status;
- unsigned int top_asb_reset_option;
- unsigned char res138[0x14];
- unsigned int top_asb_isolation_configuration;
- unsigned int top_asb_isolation_status;
- unsigned int top_asb_isolation_option;
- unsigned char res139[0x5d4];
- unsigned int gscl_configuration;
- unsigned int gscl_status;
- unsigned int gscl_option;
- unsigned char res140[0x14];
- unsigned int isp_configuration;
- unsigned int isp_status;
- unsigned int isp_option;
- unsigned char res141[0x14];
- unsigned int mfc_configuration;
- unsigned int mfc_status;
- unsigned int mfc_option;
- unsigned char res142[0x14];
- unsigned int g3d_configuration;
- unsigned int g3d_status;
- unsigned int g3d_option;
- unsigned char res143[0x34];
- unsigned int disp1_configuration;
- unsigned int disp1_status;
- unsigned int disp1_option;
- unsigned char res144[0x14];
- unsigned int mau_configuration;
- unsigned int mau_status;
- unsigned int mau_option;
- unsigned char res145[0x334];
- unsigned int cmu_clkstop_gscl_configuration;
- unsigned int cmu_clkstop_gscl_status;
- unsigned int cmu_clkstop_gscl_option;
- unsigned char res146[0x14];
- unsigned int cmu_clkstop_isp_configuration;
- unsigned int cmu_clkstop_isp_status;
- unsigned int cmu_clkstop_isp_option;
- unsigned char res147[0x14];
- unsigned int cmu_clkstop_mfc_configuration;
- unsigned int cmu_clkstop_mfc_status;
- unsigned int cmu_clkstop_mfc_option;
- unsigned char res148[0x14];
- unsigned int cmu_clkstop_g3d_configuration;
- unsigned int cmu_clkstop_g3d_status;
- unsigned int cmu_clkstop_g3d_option;
- unsigned char res149[0x34];
- unsigned int cmu_clkstop_disp1_configuration;
- unsigned int cmu_clkstop_disp1_status;
- unsigned int cmu_clkstop_disp1_option;
- unsigned char res150[0x14];
- unsigned int cmu_clkstop_mau_configuration;
- unsigned int cmu_clkstop_mau_status;
- unsigned int cmu_clkstop_mau_option;
- unsigned char res151[0x134];
- unsigned int cmu_sysclk_gscl_configuration;
- unsigned int cmu_sysclk_gscl_status;
- unsigned int cmu_sysclk_gscl_option;
- unsigned char res152[0x18];
- unsigned int cmu_sysclk_isp_status;
- unsigned int cmu_sysclk_isp_option;
- unsigned char res153[0x18];
- unsigned int cmu_sysclk_mfc_status;
- unsigned int cmu_sysclk_mfc_option;
- unsigned char res154[0x18];
- unsigned int cmu_sysclk_g3d_status;
- unsigned int cmu_sysclk_g3d_option;
- unsigned char res155[0x38];
- unsigned int cmu_sysclk_disp1_status;
- unsigned int cmu_sysclk_disp1_option;
- unsigned char res156[0x18];
- unsigned int cmu_sysclk_mau_status;
- unsigned int cmu_sysclk_mau_option;
- unsigned char res157[0x534];
- unsigned int cmu_reset_gscl_configuration;
- unsigned int cmu_reset_gscl_status;
- unsigned int cmu_reset_gscl_option;
- unsigned char res158[0x14];
- unsigned int cmu_reset_isp_configuration;
- unsigned int cmu_reset_isp_status;
- unsigned int cmu_reset_isp_option;
- unsigned char res159[0x14];
- unsigned int cmu_reset_mfc_configuration;
- unsigned int cmu_reset_mfc_status;
- unsigned int cmu_reset_mfc_option;
- unsigned char res160[0x14];
- unsigned int cmu_reset_g3d_configuration;
- unsigned int cmu_reset_g3d_status;
- unsigned int cmu_reset_g3d_option;
- unsigned char res161[0x34];
- unsigned int cmu_reset_disp1_configuration;
- unsigned int cmu_reset_disp1_status;
- unsigned int cmu_reset_disp1_option;
- unsigned char res162[0x14];
- unsigned int cmu_reset_mau_configuration;
- unsigned int cmu_reset_mau_status;
- unsigned int cmu_reset_mau_option;
- unsigned char res163[0x24];
-};
-
-struct exynos5420_power {
- unsigned int om_stat;
- unsigned int lpi_mask0;
- unsigned int lpi_mask1;
- unsigned char res1[0x10];
- unsigned int rtc_clko_sel;
- unsigned char res2[0x1e0];
- unsigned int central_seq_configuration;
- unsigned int central_seq_status;
- unsigned int central_seq_option;
- unsigned char res3[0x14];
- unsigned int seq_transition0;
- unsigned int seq_transition1;
- unsigned int seq_transition2;
- unsigned int seq_transition3;
- unsigned int seq_transition4;
- unsigned int seq_transition5;
- unsigned int seq_transition6;
- unsigned int seq_transition7;
- unsigned int central_seq_coreblk_configuration;
- unsigned int central_seq_coreblk_status;
- unsigned int central_seq_coreblk_option;
- unsigned char res4[0x14];
- unsigned int seq_coreblk_transition0;
- unsigned int seq_coreblk_transition1;
- unsigned int seq_coreblk_transition2;
- unsigned int seq_coreblk_transition3;
- unsigned int seq_coreblk_transition4;
- unsigned int seq_coreblk_transition5;
- unsigned int seq_coreblk_transition6;
- unsigned int seq_coreblk_transition7;
- unsigned char res5[0x180];
- unsigned int swreset;
- unsigned int rst_stat;
- unsigned int automatic_wdt_reset_disable;
- unsigned int mask_wdt_reset_request;
- unsigned int mask_wreset_request;
- unsigned char res6[0xec];
- unsigned int reset_sequencer_configuration;
- unsigned int reset_sequencer_status;
- unsigned int reset_sequencer_option;
- unsigned char res7[0xf4];
- unsigned int wakeup_stat;
- unsigned int eint_wakeup_mask;
- unsigned int wakeup_mask;
- unsigned int wakeup_interrupt;
- unsigned char res8[0x10];
- unsigned int wakeup_stat_coreblk;
- unsigned int eint_wakeup_mask_coreblk;
- unsigned int wakeup_mask_coreblk;
- unsigned int wakeup_interrupt_coreblk;
- unsigned char res9[0xd0];
- unsigned int hdmi_phy_control;
- unsigned int usbdev_phy_control;
- unsigned int usbdev1_phy_control;
- unsigned int usbhost_phy_control;
- unsigned char res104[0x4];
- unsigned int mipi_phy0_control;
- unsigned int mipi_phy1_control;
- unsigned int mipi_phy2_control;
- unsigned int adc_phy_control;
- unsigned int mtcadc_phy_control;
- unsigned int dptx_phy_control;
- unsigned char res10[0xd4];
- unsigned int inform0;
- unsigned int inform1;
- unsigned int inform2;
- unsigned int inform3;
- unsigned int sysip_dat0;
- unsigned int sysip_dat1;
- unsigned int sysip_dat2;
- unsigned int sysip_dat3;
- unsigned char res11[0xe0];
- unsigned int pmu_spare0;
- unsigned int pmu_spare1; /* Store PHY0_CON4 for read leveling */
- unsigned int pmu_spare2; /* Store PHY1_CON4 for read leveling */
- unsigned int pmu_spare3;
- unsigned char res12[0x4];
- unsigned int cg_status0;
- unsigned int cg_status1;
- unsigned int cg_status2;
- unsigned int cg_status3;
- unsigned int cg_status4;
- unsigned char res200[0x58];
- unsigned int irom_data_reg0;
- unsigned int irom_data_reg1;
- unsigned int irom_data_reg2;
- unsigned int irom_data_reg3;
- unsigned char res13[0x70];
- unsigned int pmu_debug;
- unsigned char res14[0x5fc];
- unsigned int arm_core0_sys_pwr_reg;
- unsigned char res500[0xc];
- unsigned int arm_core1_sys_pwr_reg;
- unsigned char res501[0xc];
- unsigned int arm_core2_sys_pwr_reg;
- unsigned char res502[0xc];
- unsigned int arm_core3_sys_pwr_reg;
- unsigned char res503[0xc];
- unsigned int kfc_core0_sys_pwr_reg;
- unsigned char res504[0xc];
- unsigned int kfc_core1_sys_pwr_reg;
- unsigned char res505[0xc];
- unsigned int kfc_core2_sys_pwr_reg;
- unsigned char res506[0xc];
- unsigned int kfc_core3_sys_pwr_reg;
- unsigned char res507[0x1c];
- unsigned int isp_arm_sys_pwr_reg;
- unsigned char res18[0xc];
- unsigned int arm_common_sys_pwr_reg;
- unsigned char res508[0xc];
- unsigned int kfc_common_sys_pwr_reg;
- unsigned char res19[0xc];
- unsigned int arm_l2_sys_pwr_reg;
- unsigned char res509[0xc];
- unsigned int kfc_l2_sys_pwr_reg;
- unsigned char res20[0xc];
- unsigned int cmu_cpu_aclkstop_sys_pwr_reg;
- unsigned int cmu_cpu_sclkstop_sys_pwr_reg;
- unsigned char res510[0x8];
- unsigned int cmu_kfc_aclkstop_sys_pwr_reg;
- unsigned char res511[0xc];
- unsigned int cmu_aclkstop_sys_pwr_reg;
- unsigned int cmu_sclkstop_sys_pwr_reg;
- unsigned char res21[0x4];
- unsigned int cmu_reset_sys_pwr_reg;
- unsigned char res22[0x10];
- unsigned int cmu_aclkstop_coreblk_sys_pwr_reg;
- unsigned int cmu_sclkstop_coreblk_sys_pwr_reg;
- unsigned char res23[0x4];
- unsigned int cmu_reset_coreblk_sys_pwr_reg;
- unsigned int dram_freq_down_sys_pwr_reg;
- unsigned int ddrphy_dlloff_sys_pwr_reg;
- unsigned int ddrphy_dlllock_sys_pwr_reg;
- unsigned char res25[0x4];
- unsigned int apll_sysclk_sys_pwr_reg;
- unsigned int mpll_sysclk_sys_pwr_reg;
- unsigned int vpll_sysclk_sys_pwr_reg;
- unsigned int epll_sysclk_sys_pwr_reg;
- unsigned int bpll_sysclk_sys_pwr_reg;
- unsigned int cpll_sysclk_sys_pwr_reg;
- unsigned int dpll_sysclk_sys_pwr_reg;
- unsigned int ipll_sysclk_sys_pwr_reg;
- unsigned int kpll_sysclk_sys_pwr_reg;
- unsigned int mplluser_sysclk_sys_pwr_reg;
- unsigned char res512[0x8];
- unsigned int bplluser_sysclk_sys_pwr_reg;
- unsigned int rpll_sysclk_sys_pwr_reg;
- unsigned int spll_sysclk_sys_pwr_reg;
- unsigned char res26[0x4];
- unsigned int top_bus_sys_pwr_reg;
- unsigned int top_retention_sys_pwr_reg;
- unsigned int top_pwr_sys_pwr_reg;
- unsigned char res29[0x4];
- unsigned int top_bus_coreblk_sys_pwr_reg;
- unsigned int top_retention_coreblk_sys_pwr_reg;
- unsigned int top_pwr_coreblk_sys_pwr_reg;
- unsigned char res30[0x4];
- unsigned int logic_reset_sys_pwr_reg;
- unsigned int oscclk_gate_sys_pwr_reg;
- unsigned char res31[0x8];
- unsigned int logic_reset_coreblk_sys_pwr_reg;
- unsigned int oscclk_gate_coreblk_sys_pwr_reg;
- unsigned int intram_mem_sys_pwr_reg;
- unsigned int introm_mem_sys_pwr_reg;
- unsigned char res32[0x44];
- unsigned int pad_retention_mau_sys_pwr_reg;
- unsigned int pad_retention_jtag_sys_pwr_reg;
- unsigned char res36[0x4];
- unsigned int pad_retention_dram_sys_pwr_reg;
- unsigned int pad_retention_uart_sys_pwr_reg;
- unsigned int pad_retention_mmca_sys_pwr_reg;
- unsigned int pad_retention_mmcb_sys_pwr_reg;
- unsigned int pad_retention_mmcc_sys_pwr_reg;
- unsigned int pad_retention_hsi_sys_pwr_reg;
- unsigned int pad_retention_ebia_sys_pwr_reg;
- unsigned int pad_retention_ebib_sys_pwr_reg;
- unsigned int pad_retention_spi_sys_pwr_reg;
- unsigned int pad_retention_dram_coreblk_sys_pwr_reg;
- unsigned char res28[0x8];
- unsigned int pad_isolation_sys_pwr_reg;
- unsigned char res37[0xc];
- unsigned int pad_isolation_coreblk_sys_pwr_reg;
- unsigned char res38[0xc];
- unsigned int pad_alv_sel_sys_pwr_reg;
- unsigned char res39[0x1c];
- unsigned int xusbxti_sys_pwr_reg;
- unsigned int xxti_sys_pwr_reg;
- unsigned char res40[0x38];
- unsigned int ext_regulator_sys_pwr_reg;
- unsigned char res41[0x3c];
- unsigned int gpio_mode_sys_pwr_reg;
- unsigned char res42[0x1c];
- unsigned int gpio_mode_coreblk_sys_pwr_reg;
- unsigned char res43[0x1c];
- unsigned int gpio_mode_mau_sys_pwr_reg;
- unsigned int top_asb_reset_sys_pwr_reg;
- unsigned int top_asb_isolation_sys_pwr_reg;
- unsigned char res44[0xb4];
- unsigned int gscl_sys_pwr_reg;
- unsigned int isp_sys_pwr_reg;
- unsigned int mfc_sys_pwr_reg;
- unsigned int g3d_sys_pwr_reg;
- unsigned int disp1_sys_pwr_reg;
- unsigned int mau_sys_pwr_reg;
- unsigned int g2d_sys_pwr_reg;
- unsigned int msc_sys_pwr_reg;
- unsigned int fsys_sys_pwr_reg;
- unsigned int fsys2_sys_pwr_reg;
- unsigned int psgen_sys_pwr_reg;
- unsigned int peric_sys_pwr_reg;
- unsigned int wcore_sys_pwr_reg;
- unsigned char res46[0x4c];
- unsigned int cmu_clkstop_gscl_sys_pwr_reg;
- unsigned int cmu_clkstop_isp_sys_pwr_reg;
- unsigned int cmu_clkstop_mfc_sys_pwr_reg;
- unsigned int cmu_clkstop_g3d_sys_pwr_reg;
- unsigned int cmu_clkstop_disp1_sys_pwr_reg;
- unsigned int cmu_clkstop_mau_sys_pwr_reg;
- unsigned int cmu_clkstop_g2d_sys_pwr_reg;
- unsigned int cmu_clkstop_msc_sys_pwr_reg;
- unsigned int cmu_clkstop_fsys_sys_pwr_reg;
- unsigned int cmu_clkstop_fsys2_sys_pwr_reg;
- unsigned int cmu_clkstop_psgen_sys_pwr_reg;
- unsigned int cmu_clkstop_peric_sys_pwr_reg;
- unsigned int cmu_clkstop_wcore_sys_pwr_reg;
- unsigned char res48[0x8];
- unsigned int cmu_sysclk_toppwr_sys_pwr_reg;
- unsigned int cmu_sysclk_gscl_sys_pwr_reg;
- unsigned int cmu_sysclk_isp_sys_pwr_reg;
- unsigned int cmu_sysclk_mfc_sys_pwr_reg;
- unsigned int cmu_sysclk_g3d_sys_pwr_reg;
- unsigned int cmu_sysclk_disp1_sys_pwr_reg;
- unsigned int cmu_sysclk_mau_sys_pwr_reg;
- unsigned int cmu_sysclk_g2d_sys_pwr_reg;
- unsigned int cmu_sysclk_msc_sys_pwr_reg;
- unsigned int cmu_sysclk_fsys_sys_pwr_reg;
- unsigned int cmu_sysclk_fsys2_sys_pwr_reg;
- unsigned int cmu_sysclk_psgen_sys_pwr_reg;
- unsigned int cmu_sysclk_peric_sys_pwr_reg;
- unsigned int cmu_sysclk_wcore_sys_pwr_reg;
- unsigned int cmu_sysclk_coreblk_toppwr_sys_pwr_reg;
- unsigned char res50[0x78];
- unsigned int cmu_reset_fsys2_sys_pwr_reg;
- unsigned int cmu_reset_psgen_sys_pwr_reg;
- unsigned int cmu_reset_peric_sys_pwr_reg;
- unsigned int cmu_reset_wcore_sys_pwr_reg;
- unsigned int cmu_reset_gscl_sys_pwr_reg;
- unsigned int cmu_reset_isp_sys_pwr_reg;
- unsigned int cmu_reset_mfc_sys_pwr_reg;
- unsigned int cmu_reset_g3d_sys_pwr_reg;
- unsigned int cmu_reset_disp1_sys_pwr_reg;
- unsigned int cmu_reset_mau_sys_pwr_reg;
- unsigned int cmu_reset_g2d_sys_pwr_reg;
- unsigned int cmu_reset_msc_sys_pwr_reg;
- unsigned int cmu_reset_fsys_sys_pwr_reg;
- unsigned char res52[0xa5c];
- unsigned int arm_core0_configuration;
- unsigned int arm_core0_status;
- unsigned int arm_core0_option;
- unsigned char res53[0x14];
- unsigned int dis_irq_arm_core0_local_configuration;
- unsigned int dis_irq_arm_core0_local_status;
- unsigned int dis_irq_arm_core0_local_option;
- unsigned char res54[0x14];
- unsigned int dis_irq_arm_core0_central_configuration;
- unsigned int dis_irq_arm_core0_central_status;
- unsigned int dis_irq_arm_core0_central_option;
- unsigned char res55[0x34];
- unsigned int arm_core1_configuration;
- unsigned int arm_core1_status;
- unsigned int arm_core1_option;
- unsigned char res56[0x14];
- unsigned int dis_irq_arm_core1_local_configuration;
- unsigned int dis_irq_arm_core1_local_status;
- unsigned int dis_irq_arm_core1_local_option;
- unsigned char res57[0x14];
- unsigned int dis_irq_arm_core1_central_configuration;
- unsigned int dis_irq_arm_core1_central_status;
- unsigned int dis_irq_arm_core1_central_option;
- unsigned char res600[0x34];
- unsigned int arm_core2_configuration;
- unsigned int arm_core2_status;
- unsigned int arm_core2_option;
- unsigned char res601[0x14];
- unsigned int dis_irq_arm_core2_local_configuration;
- unsigned int dis_irq_arm_core2_local_status;
- unsigned int dis_irq_arm_core2_local_option;
- unsigned char res602[0x14];
- unsigned int dis_irq_arm_core2_central_configuration;
- unsigned int dis_irq_arm_core2_central_status;
- unsigned int dis_irq_arm_core2_central_option;
- unsigned char res603[0x34];
- unsigned int arm_core3_configuration;
- unsigned int arm_core3_status;
- unsigned int arm_core3_option;
- unsigned char res900[0x14];
- unsigned int dis_irq_arm_core3_local_configuration;
- unsigned int dis_irq_arm_core3_local_status;
- unsigned int dis_irq_arm_core3_local_option;
- unsigned char res901[0x14];
- unsigned int dis_irq_arm_core3_central_configuration;
- unsigned int dis_irq_arm_core3_central_status;
- unsigned int dis_irq_arm_core3_central_option;
- unsigned char res604[0x34];
- unsigned int kfc_core0_configuration;
- unsigned int kfc_core0_status;
- unsigned int kfc_core0_option;
- unsigned char res605[0x14];
- unsigned int dis_irq_kfc_core0_local_configuration;
- unsigned int dis_irq_kfc_core0_local_status;
- unsigned int dis_irq_kfc_core0_local_option;
- unsigned char res606[0x14];
- unsigned int dis_irq_kfc_core0_central_configuration;
- unsigned int dis_irq_kfc_core0_central_status;
- unsigned int dis_irq_kfc_core0_central_option;
- unsigned char res607[0x34];
- unsigned int kfc_core1_configuration;
- unsigned int kfc_core1_status;
- unsigned int kfc_core1_option;
- unsigned char res608[0x14];
- unsigned int dis_irq_kfc_core1_local_configuration;
- unsigned int dis_irq_kfc_core1_local_status;
- unsigned int dis_irq_kfc_core1_local_option;
- unsigned char res609[0x14];
- unsigned int dis_irq_kfc_core1_central_configuration;
- unsigned int dis_irq_kfc_core1_central_status;
- unsigned int dis_irq_kfc_core1_central_option;
- unsigned char res610[0x34];
- unsigned int kfc_core2_configuration;
- unsigned int kfc_core2_status;
- unsigned int kfc_core2_option;
- unsigned char res611[0x14];
- unsigned int dis_irq_kfc_core2_local_configuration;
- unsigned int dis_irq_kfc_core2_local_status;
- unsigned int dis_irq_kfc_core2_local_option;
- unsigned char res612[0x14];
- unsigned int dis_irq_kfc_core2_central_configuration;
- unsigned int dis_irq_kfc_core2_central_status;
- unsigned int dis_irq_kfc_core2_central_option;
- unsigned char res613[0x34];
- unsigned int kfc_core3_configuration;
- unsigned int kfc_core3_status;
- unsigned int kfc_core3_option;
- unsigned char res614[0x14];
- unsigned int dis_irq_kfc_core3_local_configuration;
- unsigned int dis_irq_kfc_core3_local_status;
- unsigned int dis_irq_kfc_core3_local_option;
- unsigned char res615[0x14];
- unsigned int dis_irq_kfc_core3_central_configuration;
- unsigned int dis_irq_kfc_core3_central_status;
- unsigned int dis_irq_kfc_core3_central_option;
- unsigned char res61[0xb4];
- unsigned int isp_arm_configuration;
- unsigned int isp_arm_status;
- unsigned int isp_arm_option;
- unsigned char res62[0x14];
- unsigned int dis_irq_isp_arm_local_configuration;
- unsigned int dis_irq_isp_arm_local_status;
- unsigned int dis_irq_isp_arm_local_option;
- unsigned char res63[0x14];
- unsigned int dis_irq_isp_arm_central_configuration;
- unsigned int dis_irq_isp_arm_central_status;
- unsigned int dis_irq_isp_arm_central_option;
- unsigned char res64[0x34];
- unsigned int arm_common_configuration;
- unsigned int arm_common_status;
- unsigned int arm_common_option;
- unsigned char res616[0x74];
- unsigned int kfc_common_configuration;
- unsigned int kfc_common_status;
- unsigned int kfc_common_option;
- unsigned char res65[0x74];
- unsigned int arm_l2_configuration;
- unsigned int arm_l2_status;
- unsigned int arm_l2_option;
- unsigned char res617[0x74];
- unsigned int kfc_l2_configuration;
- unsigned int kfc_l2_status;
- unsigned int kfc_l2_option;
- unsigned char res66[0x74];
- unsigned int cmu_cpu_aclkstop_configuration;
- unsigned int cmu_cpu_aclkstop_status;
- unsigned int cmu_cpu_aclkstop_option;
- unsigned char res67[0x14];
- unsigned int cmu_cpu_sclkstop_configuration;
- unsigned int cmu_cpu_sclkstop_status;
- unsigned int cmu_cpu_sclkstop_option;
- unsigned char res618[0x4];
- unsigned int cmu_kfc_aclkstop_configuration;
- unsigned int cmu_kfc_aclkstop_status;
- unsigned int cmu_kfc_aclkstop_option;
- unsigned char res619[0xc4];
- unsigned int cmu_aclkstop_configuration;
- unsigned int cmu_aclkstop_status;
- unsigned int cmu_aclkstop_option;
- unsigned char res620[0x14];
- unsigned int cmu_sclkstop_configuration;
- unsigned int cmu_sclkstop_status;
- unsigned int cmu_sclkstop_option;
- unsigned char res68[0x34];
- unsigned int cmu_reset_configuration;
- unsigned int cmu_reset_status;
- unsigned int cmu_reset_option;
- unsigned char res69[0x94];
- unsigned int cmu_aclkstop_coreblk_configuration;
- unsigned int cmu_aclkstop_coreblk_status;
- unsigned int cmu_aclkstop_coreblk_option;
- unsigned char res70[0x14];
- unsigned int cmu_sclkstop_coreblk_configuration;
- unsigned int cmu_sclkstop_coreblk_status;
- unsigned int cmu_sclkstop_coreblk_option;
- unsigned char res71[0x34];
- unsigned int cmu_reset_coreblk_configuration;
- unsigned int cmu_reset_coreblk_status;
- unsigned int cmu_reset_coreblk_option;
- unsigned char res621[0x14];
- unsigned int dram_freq_down_configuration;
- unsigned int dram_freq_down_status;
- unsigned int dram_freq_down_option;
- unsigned char res622[0x14];
- unsigned int ddrphy_dlloff_configuration;
- unsigned int ddrphy_dlloff_status;
- unsigned int ddrphy_dlloff_option;
- unsigned char res72[0x14];
- unsigned int ddrphy_dlllock_configuration;
- unsigned int ddrphy_dlllock_status;
- unsigned int ddrphy_dlllock_option;
- unsigned char res73[0x34];
- unsigned int apll_sysclk_configuration;
- unsigned int apll_sysclk_status;
- unsigned int apll_sysclk_option;
- unsigned char res74[0x18];
- unsigned int mpll_sysclk_status;
- unsigned int mpll_sysclk_option;
- unsigned char res75[0x14];
- unsigned int vpll_sysclk_configuration;
- unsigned int vpll_sysclk_status;
- unsigned int vpll_sysclk_option;
- unsigned char res76[0x14];
- unsigned int epll_sysclk_configuration;
- unsigned int epll_sysclk_status;
- unsigned int epll_sysclk_option;
- unsigned char res77[0x14];
- unsigned int bpll_sysclk_configuration;
- unsigned int bpll_sysclk_status;
- unsigned int bpll_sysclk_option;
- unsigned char res78[0x14];
- unsigned int cpll_sysclk_configuration;
- unsigned int cpll_sysclk_status;
- unsigned int cpll_sysclk_option;
- unsigned char res79[0x14];
- unsigned int dpll_sysclk_configuration;
- unsigned int dpll_sysclk_status;
- unsigned int dpll_sysclk_option;
- unsigned char res700[0x14];
- unsigned int ipll_sysclk_configuration;
- unsigned int ipll_sysclk_status;
- unsigned int ipll_sysclk_option;
- unsigned char res903[0x14];
- unsigned int kpll_sysclk_configuration;
- unsigned int kpll_sysclk_status;
- unsigned int kpll_sysclk_option;
- unsigned char res80[0x14];
- unsigned int mplluser_sysclk_configuration;
- unsigned int mplluser_sysclk_status;
- unsigned int mplluser_sysclk_option;
- unsigned char res81[0x54];
- unsigned int bplluser_sysclk_configuration;
- unsigned int bplluser_sysclk_status;
- unsigned int bplluser_sysclk_option;
- unsigned char res701[0x14];
- unsigned int rplluser_sysclk_configuration;
- unsigned int rplluser_sysclk_status;
- unsigned int rplluser_sysclk_option;
- unsigned char res702[0x14];
- unsigned int splluser_sysclk_configuration;
- unsigned int splluser_sysclk_status;
- unsigned int splluser_sysclk_option;
- unsigned char res82[0x34];
- unsigned int top_bus_configuration;
- unsigned int top_bus_status;
- unsigned int top_bus_option;
- unsigned char res83[0x14];
- unsigned int top_retention_configuration;
- unsigned int top_retention_status;
- unsigned int top_retention_option;
- unsigned char res84[0x14];
- unsigned int top_pwr_configuration;
- unsigned int top_pwr_status;
- unsigned int top_pwr_option;
- unsigned char res85[0x34];
- unsigned int top_bus_coreblk_configuration;
- unsigned int top_bus_coreblk_status;
- unsigned int top_bus_coreblk_option;
- unsigned char res86[0x14];
- unsigned int top_retention_coreblk_configuration;
- unsigned int top_retention_coreblk_status;
- unsigned int top_retention_coreblk_option;
- unsigned char res87[0x14];
- unsigned int top_pwr_coreblk_configuration;
- unsigned int top_pwr_coreblk_status;
- unsigned int top_pwr_coreblk_option;
- unsigned char res88[0x34];
- unsigned int logic_reset_configuration;
- unsigned int logic_reset_status;
- unsigned int logic_reset_option;
- unsigned char res89[0x14];
- unsigned int oscclk_gate_configuration;
- unsigned int oscclk_gate_status;
- unsigned int oscclk_gate_option;
- unsigned char res90[0x54];
- unsigned int logic_reset_coreblk_configuration;
- unsigned int logic_reset_coreblk_status;
- unsigned int logic_reset_coreblk_option;
- unsigned char res91[0x14];
- unsigned int oscclk_gate_coreblk_configuration;
- unsigned int oscclk_gate_coreblk_status;
- unsigned int oscclk_gate_coreblk_option;
- unsigned char res99[0x174];
- unsigned int intram_mem_configuration;
- unsigned int intram_mem_status;
- unsigned int intram_mem_option;
- unsigned char res100[0x14];
- unsigned int introm_mem_configuration;
- unsigned int introm_mem_status;
- unsigned int introm_mem_option;
- unsigned char res101[0xb4];
- unsigned int pad_retention_dram_configuration;
- unsigned int pad_retention_dram_status;
- unsigned int pad_retention_dram_option;
- unsigned char res106[0x14];
- unsigned int pad_retention_mau_configuration;
- unsigned int pad_retention_mau_status;
- unsigned int pad_retention_mau_option;
- unsigned char res107[0x14];
- unsigned int pad_retention_jtag_configuration;
- unsigned int pad_retention_jtag_status;
- unsigned int pad_retention_jtag_option;
- unsigned char res92[0x74];
- unsigned int pad_retention_dram_configuration_2;
- unsigned int pad_retention_dram_status_2;
- unsigned int pad_retention_dram_option_2;
- unsigned char res111[0x14];
- unsigned int pad_retention_uart_configuration;
- unsigned int pad_retention_uart_status;
- unsigned int pad_retention_uart_option;
- unsigned char res112[0x14];
- unsigned int pad_retention_mmca_configuration;
- unsigned int pad_retention_mmca_status;
- unsigned int pad_retention_mmca_option;
- unsigned char res113[0x14];
- unsigned int pad_retention_mmcb_configuration;
- unsigned int pad_retention_mmcb_status;
- unsigned int pad_retention_mmcb_option;
- unsigned char res93[0x14];
- unsigned int pad_retention_mmcc_configuration;
- unsigned int pad_retention_mmcc_status;
- unsigned int pad_retention_mmcc_option;
- unsigned char res94[0x14];
- unsigned int pad_retention_hsi_configuration;
- unsigned int pad_retention_hsi_status;
- unsigned int pad_retention_hsi_option;
- unsigned char res114[0x14];
- unsigned int pad_retention_ebia_configuration;
- unsigned int pad_retention_ebia_status;
- unsigned int pad_retention_ebia_option;
- unsigned char res115[0x14];
- unsigned int pad_retention_ebib_configuration;
- unsigned int pad_retention_ebib_status;
- unsigned int pad_retention_ebib_option;
- unsigned char res116[0x14];
- unsigned int pad_retention_spi_configuration;
- unsigned int pad_retention_spi_status;
- unsigned int pad_retention_spi_option;
- unsigned char res117[0x14];
- unsigned int pad_retention_dram_coreblk_configuration;
- unsigned int pad_retention_dram_coreblk_status;
- unsigned int pad_retention_dram_coreblk_option;
- unsigned char res118[0x14];
- unsigned int pad_isolation_configuration;
- unsigned int pad_isolation_status;
- unsigned int pad_isolation_option;
- unsigned char res119[0x74];
- unsigned int pad_isolation_coreblk_configuration;
- unsigned int pad_isolation_coreblk_status;
- unsigned int pad_isolation_coreblk_option;
- unsigned char res120[0x74];
- unsigned int pad_alv_sel_configuration;
- unsigned int pad_alv_sel_status;
- unsigned int pad_alv_sel_option0;
- unsigned int ps_hold_control;
- unsigned char res130[0xf0];
- unsigned int xusbxti_configuration;
- unsigned int xusbxti_status;
- unsigned int xusbxti_option;
- unsigned char res910[0x10];
- unsigned int xusbxti_duration3;
- unsigned int xxti_configuration;
- unsigned int xxti_status;
- unsigned int xxti_option;
- unsigned char res131[0x10];
- unsigned int xxti_duration3;
- unsigned char res132[0x1c0];
- unsigned int ext_regulator_configuration;
- unsigned int ext_regulator_status;
- unsigned int ext_regulator_option;
- unsigned char res133[0x10];
- unsigned int ext_regulator_duration3;
- unsigned char res134[0x1e0];
- unsigned int gpio_mode_configuration;
- unsigned int gpio_mode_status;
- unsigned int gpio_mode_option;
- unsigned char res135[0xf4];
- unsigned int gpio_mode_coreblk_configuration;
- unsigned int gpio_mode_coreblk_status;
- unsigned int gpio_mode_coreblk_option;
- unsigned char res136[0xd4];
- unsigned int gpio_mode_mau_configuration;
- unsigned int gpio_mode_mau_status;
- unsigned int gpio_mode_mau_option;
- unsigned char res137[0x14];
- unsigned int top_asb_reset_configuration;
- unsigned int top_asb_reset_status;
- unsigned int top_asb_reset_option;
- unsigned char res138[0x14];
- unsigned int top_asb_isolation_configuration;
- unsigned int top_asb_isolation_status;
- unsigned int top_asb_isolation_option;
- unsigned char res139[0x5d4];
- unsigned int gscl_configuration;
- unsigned int gscl_status;
- unsigned int gscl_option;
- unsigned char res140[0x14];
- unsigned int isp_configuration;
- unsigned int isp_status;
- unsigned int isp_option;
- unsigned char res141[0x34];
- unsigned int mfc_configuration;
- unsigned int mfc_status;
- unsigned int mfc_option;
- unsigned char res142[0x14];
- unsigned int g3d_configuration;
- unsigned int g3d_status;
- unsigned int g3d_option;
- unsigned char res143[0x34];
- unsigned int disp1_configuration;
- unsigned int disp1_status;
- unsigned int disp1_option;
- unsigned char res144[0x14];
- unsigned int mau_configuration;
- unsigned int mau_status;
- unsigned int mau_option;
- unsigned char res800[0x14];
- unsigned int g2d_configuration;
- unsigned int g2d_status;
- unsigned int g2d_option;
- unsigned char res801[0x14];
- unsigned int msc_configuration;
- unsigned int msc_status;
- unsigned int msc_option;
- unsigned char res802[0x14];
- unsigned int fsys_configuration;
- unsigned int fsys_status;
- unsigned int fsys_option;
- unsigned char res803[0x14];
- unsigned int fsys2_configuration;
- unsigned int fsys2_status;
- unsigned int fsys2_option;
- unsigned char res804[0x14];
- unsigned int psgen_configuration;
- unsigned int psgen_status;
- unsigned int psgen_option;
- unsigned char res805[0x14];
- unsigned int peric_configuration;
- unsigned int peric_status;
- unsigned int peric_option;
- unsigned char res806[0x14];
- unsigned int wcore_configuration;
- unsigned int wcore_status;
- unsigned int wcore_option;
- unsigned char res145[0x234];
- unsigned int cmu_clkstop_gscl_configuration;
- unsigned int cmu_clkstop_gscl_status;
- unsigned int cmu_clkstop_gscl_option;
- unsigned char res146[0x14];
- unsigned int cmu_clkstop_isp_configuration;
- unsigned int cmu_clkstop_isp_status;
- unsigned int cmu_clkstop_isp_option;
- unsigned char res147[0x34];
- unsigned int cmu_clkstop_mfc_configuration;
- unsigned int cmu_clkstop_mfc_status;
- unsigned int cmu_clkstop_mfc_option;
- unsigned char res148[0x14];
- unsigned int cmu_clkstop_g3d_configuration;
- unsigned int cmu_clkstop_g3d_status;
- unsigned int cmu_clkstop_g3d_option;
- unsigned char res149[0x34];
- unsigned int cmu_clkstop_disp1_configuration;
- unsigned int cmu_clkstop_disp1_status;
- unsigned int cmu_clkstop_disp1_option;
- unsigned char res150[0x14];
- unsigned int cmu_clkstop_mau_configuration;
- unsigned int cmu_clkstop_mau_status;
- unsigned int cmu_clkstop_mau_option;
- unsigned char res807[0x14];
- unsigned int cmu_clkstop_g2d_configuration;
- unsigned int cmu_clkstop_g2d_status;
- unsigned int cmu_clkstop_g2d_option;
- unsigned char res808[0x14];
- unsigned int cmu_clkstop_msc_configuration;
- unsigned int cmu_clkstop_msc_status;
- unsigned int cmu_clkstop_msc_option;
- unsigned char res809[0x14];
- unsigned int cmu_clkstop_fsys_configuration;
- unsigned int cmu_clkstop_fsys_status;
- unsigned int cmu_clkstop_fsys_option;
- unsigned char res810[0x14];
- unsigned int cmu_clkstop_fsys2_configuration;
- unsigned int cmu_clkstop_fsys2_status;
- unsigned int cmu_clkstop_fsys2_option;
- unsigned char res811[0x14];
- unsigned int cmu_clkstop_psgen_configuration;
- unsigned int cmu_clkstop_psgen_status;
- unsigned int cmu_clkstop_psgen_option;
- unsigned char res812[0x14];
- unsigned int cmu_clkstop_peric_configuration;
- unsigned int cmu_clkstop_peric_status;
- unsigned int cmu_clkstop_peric_option;
- unsigned char res813[0x14];
- unsigned int cmu_clkstop_wcore_configuration;
- unsigned int cmu_clkstop_wcore_status;
- unsigned int cmu_clkstop_wcore_option;
- unsigned char res151[0x14];
- unsigned int cmu_sysclk_toppwr_configuration;
- unsigned int cmu_sysclk_toppwr_status;
- unsigned int cmu_sysclk_toppwr_option;
- unsigned char res920[0x18];
- unsigned int cmu_sysclk_gscl_status;
- unsigned int cmu_sysclk_gscl_option;
- unsigned char res152[0x18];
- unsigned int cmu_sysclk_isp_status;
- unsigned int cmu_sysclk_isp_option;
- unsigned char res153[0x38];
- unsigned int cmu_sysclk_mfc_status;
- unsigned int cmu_sysclk_mfc_option;
- unsigned char res154[0x18];
- unsigned int cmu_sysclk_g3d_status;
- unsigned int cmu_sysclk_g3d_option;
- unsigned char res155[0x38];
- unsigned int cmu_sysclk_disp1_status;
- unsigned int cmu_sysclk_disp1_option;
- unsigned char res156[0x18];
- unsigned int cmu_sysclk_mau_status;
- unsigned int cmu_sysclk_mau_option;
- unsigned char res814[0x18];
- unsigned int cmu_sysclk_g2d_status;
- unsigned int cmu_sysclk_g2d_option;
- unsigned char res815[0x18];
- unsigned int cmu_sysclk_msc_status;
- unsigned int cmu_sysclk_msc_option;
- unsigned char res922[0x18];
- unsigned int cmu_sysclk_fsys_status;
- unsigned int cmu_sysclk_fsys_option;
- unsigned char res816[0x18];
- unsigned int cmu_sysclk_fsys2_status;
- unsigned int cmu_sysclk_fsys2_option;
- unsigned char res817[0x18];
- unsigned int cmu_sysclk_psgen_status;
- unsigned int cmu_sysclk_psgen_option;
- unsigned char res950[0x18];
- unsigned int cmu_sysclk_peric_status;
- unsigned int cmu_sysclk_peric_option;
- unsigned char res818[0x18];
- unsigned int cmu_sysclk_wcore_status;
- unsigned int cmu_sysclk_wcore_option;
- unsigned char res819[0x18];
- unsigned int cmu_sysclk_coreblk_toppwr_status;
- unsigned int cmu_sysclk_coreblk_toppwr_option;
- unsigned char res157[0x414];
- unsigned int cmu_reset_gscl_configuration;
- unsigned int cmu_reset_gscl_status;
- unsigned int cmu_reset_gscl_option;
- unsigned char res158[0x14];
- unsigned int cmu_reset_isp_configuration;
- unsigned int cmu_reset_isp_status;
- unsigned int cmu_reset_isp_option;
- unsigned char res159[0x34];
- unsigned int cmu_reset_mfc_configuration;
- unsigned int cmu_reset_mfc_status;
- unsigned int cmu_reset_mfc_option;
- unsigned char res160[0x14];
- unsigned int cmu_reset_g3d_configuration;
- unsigned int cmu_reset_g3d_status;
- unsigned int cmu_reset_g3d_option;
- unsigned char res161[0x34];
- unsigned int cmu_reset_disp1_configuration;
- unsigned int cmu_reset_disp1_status;
- unsigned int cmu_reset_disp1_option;
- unsigned char res162[0x14];
- unsigned int cmu_reset_mau_configuration;
- unsigned int cmu_reset_mau_status;
- unsigned int cmu_reset_mau_option;
- unsigned char res163[0x14];
- unsigned int version_info;
- unsigned int i2s_bypass;
- unsigned int kfc_swreset_mask_from_eagle;
- unsigned char res164[0xf4];
- unsigned int cmu_reset_g2d_configuration;
- unsigned int cmu_reset_g2d_status;
- unsigned int cmu_reset_g2d_option;
- unsigned char res165[0x14];
- unsigned int cmu_reset_msc_configuration;
- unsigned int cmu_reset_msc_status;
- unsigned int cmu_reset_msc_option;
- unsigned char res166[0x14];
- unsigned int cmu_reset_fsys_configuration;
- unsigned int cmu_reset_fsys_status;
- unsigned int cmu_reset_fsys_option;
- unsigned char res167[0x14];
- unsigned int cmu_reset_fsys2_configuration;
- unsigned int cmu_reset_fsys2_status;
- unsigned int cmu_reset_fsys2_option;
- unsigned char res168[0x14];
- unsigned int cmu_reset_psgen_configuration;
- unsigned int cmu_reset_psgen_status;
- unsigned int cmu_reset_psgen_option;
- unsigned char res169[0x14];
- unsigned int cmu_reset_peric_configuration;
- unsigned int cmu_reset_peric_status;
- unsigned int cmu_reset_peric_option;
- unsigned char res170[0x14];
- unsigned int cmu_reset_wcore_configuration;
- unsigned int cmu_reset_wcore_status;
- unsigned int cmu_reset_wcore_option;
-};
-#endif /* __ASSEMBLY__ */
-
-#define OM_PIN_BITS 0x1f
-#define OM_PIN_SHIFT 0x1
-#define OM_PIN_MASK (OM_PIN_BITS << OM_PIN_SHIFT)
-
-enum {
- /*
- * Assign the OM pin values for respective boot modes.
- * Exynos4 does not support spi boot and the mmc boot OM
- * pin values are the same across Exynos4 and Exynos5.
- */
- BOOT_MODE_SD = 4, /* SD_CH2 | USB */
- BOOT_MODE_EMMC = 8, /* EMMC4.4 | USB */
- BOOT_MODE_EMMC_SD = 40, /* EMMC4.4 | SD_CH2 */
- BOOT_MODE_SERIAL = 20,
- /* Boot based on Operating Mode pin settings */
- BOOT_MODE_OM = 32,
- BOOT_MODE_USB, /* Boot using USB download */
-};
-
-unsigned int get_boot_mode(void);
-
-void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable);
-
-#define EXYNOS_MIPI_PHY_ENABLE (1 << 0)
-#define EXYNOS_MIPI_PHY_SRESETN (1 << 1)
-#define EXYNOS_MIPI_PHY_MRESETN (1 << 2)
-
-void set_usbhost_phy_ctrl(unsigned int enable);
-
-/* Enables hardware tripping to power off the system when TMU fails */
-void set_hw_thermal_trip(void);
-
-#define POWER_USB_HOST_PHY_CTRL_EN (1 << 0)
-#define POWER_USB_HOST_PHY_CTRL_DISABLE (0 << 0)
-
-void set_usbdrd_phy_ctrl(unsigned int enable);
-
-#define POWER_USB_DRD_PHY_CTRL_EN (1 << 0)
-#define POWER_USB_DRD_PHY_CTRL_DISABLE (0 << 0)
-
-void set_dp_phy_ctrl(unsigned int enable);
-
-#define EXYNOS_DP_PHY_ENABLE (1 << 0)
-
-#define EXYNOS_PS_HOLD_CONTROL_DATA_HIGH (1 << 8)
-#define POWER_ENABLE_HW_TRIP (1UL << 31)
-
-/*
- * Set ps_hold data driving value high
- * This enables the machine to stay powered on
- * after the initial power-on condition goes away
- * (e.g. power button).
- */
-void set_ps_hold_ctrl(void);
-
-/* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI clock source */
-#define PMU_DEBUG_XXTI 0x1000
-/* Mask bit[12:8] for xxti clock selection */
-#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00
-
-/*
- * Pmu debug is used for xclkout, enable xclkout with
- * source as XXTI
- */
-void set_xclkout(void);
-
-/*
- * Read inform1 to get the reset status.
- * @return: the value can be either S5P_CHECK_SLEEP or
- * S5P_CHECK_DIDLE or S5P_CHECK_LPA as stored in inform1
- * if none of these then its normal booting.
- */
-uint32_t get_reset_status(void);
-
-
-/* Read the resume function and call it */
-void power_exit_wakeup(void);
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_PWM_H_
-#define __ASM_ARM_ARCH_PWM_H_
-
-#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */
-#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
-
-/* Divider MUX */
-#define MUX_DIV_1 0 /* 1/1 period */
-#define MUX_DIV_2 1 /* 1/2 period */
-#define MUX_DIV_4 2 /* 1/4 period */
-#define MUX_DIV_8 3 /* 1/8 period */
-#define MUX_DIV_16 4 /* 1/16 period */
-
-#define MUX_DIV_SHIFT(x) (x * 4)
-
-#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2)
-
-#define TCON_START(x) (1 << TCON_OFFSET(x))
-#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1))
-#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2))
-#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
-#define TCON4_AUTO_RELOAD (1 << 22)
-
-#ifndef __ASSEMBLY__
-struct s5p_timer {
- unsigned int tcfg0;
- unsigned int tcfg1;
- unsigned int tcon;
- unsigned int tcntb0;
- unsigned int tcmpb0;
- unsigned int tcnto0;
- unsigned int tcntb1;
- unsigned int tcmpb1;
- unsigned int tcnto1;
- unsigned int tcntb2;
- unsigned int tcmpb2;
- unsigned int tcnto2;
- unsigned int tcntb3;
- unsigned int tcmpb3;
- unsigned int tcnto3;
- unsigned int tcntb4;
- unsigned int tcnto4;
- unsigned int tintcstat;
-};
-#endif /* __ASSEMBLY__ */
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PWM_BACKLIGHT_H_
-#define _PWM_BACKLIGHT_H_
-
-struct pwm_backlight_data {
- int pwm_id;
- int period;
- int max_brightness;
- int brightness;
-};
-
-extern int exynos_pwm_backlight_init(struct pwm_backlight_data *pd);
-
-#endif /* _PWM_BACKLIGHT_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- * Rajeshwari Shinde <rajeshwari.s@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#ifndef __SOUND_ARCH_H__
-#define __SOUND_ARCH_H__
-
-/* I2S values */
-#define I2S_PLL_CLK 192000000
-#define I2S_SAMPLING_RATE 48000
-#define I2S_BITS_PER_SAMPLE 16
-#define I2S_CHANNELS 2
-#define I2S_RFS 256
-#define I2S_BFS 32
-
-/* I2C values */
-#define AUDIO_I2C_BUS 1
-#define AUDIO_I2C_REG 0x1a
-
-/* Audio Codec */
-#define AUDIO_CODEC "wm8994"
-
-#define AUDIO_COMPAT 1
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2012 SAMSUNG Electronics
- * Padmavathi Venna <padma.v@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
-#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
-
-#ifndef __ASSEMBLY__
-
-/* SPI peripheral register map; padded to 64KB */
-struct exynos_spi {
- unsigned int ch_cfg; /* 0x00 */
- unsigned char reserved0[4];
- unsigned int mode_cfg; /* 0x08 */
- unsigned int cs_reg; /* 0x0c */
- unsigned char reserved1[4];
- unsigned int spi_sts; /* 0x14 */
- unsigned int tx_data; /* 0x18 */
- unsigned int rx_data; /* 0x1c */
- unsigned int pkt_cnt; /* 0x20 */
- unsigned char reserved2[4];
- unsigned int swap_cfg; /* 0x28 */
- unsigned int fb_clk; /* 0x2c */
- unsigned char padding[0xffd0];
-};
-
-#define EXYNOS_SPI_MAX_FREQ 50000000
-
-#define SPI_TIMEOUT_MS 10
-#define SF_READ_DATA_CMD 0x3
-
-/* SPI_CHCFG */
-#define SPI_CH_HS_EN (1 << 6)
-#define SPI_CH_RST (1 << 5)
-#define SPI_SLAVE_MODE (1 << 4)
-#define SPI_CH_CPOL_L (1 << 3)
-#define SPI_CH_CPHA_B (1 << 2)
-#define SPI_RX_CH_ON (1 << 1)
-#define SPI_TX_CH_ON (1 << 0)
-
-/* SPI_MODECFG */
-#define SPI_MODE_CH_WIDTH_WORD (0x2 << 29)
-#define SPI_MODE_BUS_WIDTH_WORD (0x2 << 17)
-
-/* SPI_CSREG */
-#define SPI_SLAVE_SIG_INACT (1 << 0)
-
-/* SPI_STS */
-#define SPI_ST_TX_DONE (1 << 25)
-#define SPI_FIFO_LVL_MASK 0x1ff
-#define SPI_TX_LVL_OFFSET 6
-#define SPI_RX_LVL_OFFSET 15
-
-/* Feedback Delay */
-#define SPI_CLK_BYPASS (0 << 0)
-#define SPI_FB_DELAY_90 (1 << 0)
-#define SPI_FB_DELAY_180 (2 << 0)
-#define SPI_FB_DELAY_270 (3 << 0)
-
-/* Packet Count */
-#define SPI_PACKET_CNT_EN (1 << 16)
-
-/* Swap config */
-#define SPI_TX_SWAP_EN (1 << 0)
-#define SPI_TX_BYTE_SWAP (1 << 2)
-#define SPI_TX_HWORD_SWAP (1 << 3)
-#define SPI_TX_BYTE_SWAP (1 << 2)
-#define SPI_RX_SWAP_EN (1 << 4)
-#define SPI_RX_BYTE_SWAP (1 << 6)
-#define SPI_RX_HWORD_SWAP (1 << 7)
-
-#endif /* __ASSEMBLY__ */
-#endif
+++ /dev/null
-/*
- * Copyright (c) 2012 The Chromium OS Authors.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_EXYNOS_SPL_H__
-#define __ASM_ARCH_EXYNOS_SPL_H__
-
-#include <asm/arch-exynos/dmc.h>
-#include <asm/arch/power.h>
-
-#ifndef __ASSEMBLY__
-/* Parameters of early board initialization in SPL */
-struct spl_machine_param {
- /* Add fields as and when required */
- u32 signature;
- u32 version; /* Version number */
- u32 size; /* Size of block */
- /**
- * Parameters we expect, in order, terminated with \0. Each parameter
- * is a single character representing one 32-bit word in this
- * structure.
- *
- * Valid characters in this string are:
- *
- * Code Name
- * v mem_iv_size
- * m mem_type
- * u uboot_size
- * b boot_source
- * f frequency_mhz (memory frequency in MHz)
- * a ARM clock frequency in MHz
- * s serial base address
- * i i2c base address for early access (meant for PMIC)
- * r board rev GPIO numbers used to read board revision
- * (lower halfword=bit 0, upper=bit 1)
- * M Memory Manufacturer name
- * \0 termination
- */
- char params[12]; /* Length must be word-aligned */
- u32 mem_iv_size; /* Memory channel interleaving size */
- enum ddr_mode mem_type; /* Type of on-board memory */
- /*
- * U-boot size - The iROM mmc copy function used by the SPL takes a
- * block count paramter to describe the u-boot size unlike the spi
- * boot copy function which just uses the u-boot size directly. Align
- * the u-boot size to block size (512 bytes) when populating the SPL
- * table only for mmc boot.
- */
- u32 uboot_size;
- unsigned boot_source; /* Boot device */
- unsigned frequency_mhz; /* Frequency of memory in MHz */
- unsigned arm_freq_mhz; /* ARM Frequency in MHz */
- u32 serial_base; /* Serial base address */
- u32 i2c_base; /* i2c base address */
- u32 board_rev_gpios; /* Board revision GPIOs */
- enum mem_manuf mem_manuf; /* Memory Manufacturer */
-} __attribute__((__packed__));
-#endif
-
-/**
- * Validate signature and return a pointer to the parameter table. If the
- * signature is invalid, call panic() and never return.
- *
- * @return pointer to the parameter table if signature matched or never return.
- */
-struct spl_machine_param *spl_get_machine_params(void);
-
-#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Naveen Krishna Ch <ch.naveen@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Note: This file contains the register description for SROMC
- */
-
-#ifndef __ASM_ARCH_SROMC_H_
-#define __ASM_ARCH_SROMC_H_
-
-#define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0))
-#define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
- /* 1-> Byte base address*/
-#define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2))
-#define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3))
-
-#define SROMC_BC_TACS(x) (x << 28) /* address set-up */
-#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */
-#define SROMC_BC_TACC(x) (x << 16) /* access cycle */
-#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */
-#define SROMC_BC_TAH(x) (x << 8) /* address holding time */
-#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */
-#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
-
-#ifndef __ASSEMBLY__
-struct s5p_sromc {
- unsigned int bw;
- unsigned int bc[4];
-};
-#endif /* __ASSEMBLY__ */
-
-/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
-void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
-
-enum {
- FDT_SROM_PMC,
- FDT_SROM_TACP,
- FDT_SROM_TAH,
- FDT_SROM_TCOH,
- FDT_SROM_TACC,
- FDT_SROM_TCOS,
- FDT_SROM_TACS,
-
- FDT_SROM_TIMING_COUNT,
-};
-
-struct fdt_sromc {
- u8 bank; /* srom bank number */
- u8 width; /* bus width in bytes */
- unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */
-};
-
-#endif /* __ASM_ARCH_SROMC_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2010 Samsung Electrnoics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-u32 get_device_type(void);
-void invalidate_dcache(u32);
-void l2_cache_disable(void);
-void l2_cache_enable(void);
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2012 Samsung Electronics
- * Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_SYSTEM_H_
-#define __ASM_ARM_ARCH_SYSTEM_H_
-
-#ifndef __ASSEMBLY__
-struct exynos4_sysreg {
- unsigned char res1[0x210];
- unsigned int display_ctrl;
- unsigned int display_ctrl2;
- unsigned int camera_control;
- unsigned int audio_endian;
- unsigned int jtag_con;
-};
-
-struct exynos5_sysreg {
- unsigned char res1[0x214];
- unsigned int disp1blk_cfg;
- unsigned int disp2blk_cfg;
- unsigned int hdcp_e_fuse;
- unsigned int gsclblk_cfg0;
- unsigned int gsclblk_cfg1;
- unsigned int reserved;
- unsigned int ispblk_cfg;
- unsigned int usb20phy_cfg;
- unsigned char res2[0x29c];
- unsigned int mipi_dphy;
- unsigned int dptx_dphy;
- unsigned int phyclk_sel;
-};
-#endif
-
-#define USB20_PHY_CFG_HOST_LINK_EN (1 << 0)
-
-/*
- * Data Synchronization Barrier acts as a special kind of memory barrier.
- * No instruction in program order after this instruction executes until
- * this instruction completes. This instruction completes when:
- * - All explicit memory accesses before this instruction complete.
- * - All Cache, Branch predictor and TLB maintenance operations before
- * this instruction complete.
- */
-#define dsb() __asm__ __volatile__ ("dsb\n\t" : : );
-
-/*
- * This instruction causes an event to be signaled to all cores
- * within a multiprocessor system. If SEV is implemented,
- * WFE must also be implemented.
- */
-#define sev() __asm__ __volatile__ ("sev\n\t" : : );
-/*
- * If the Event Register is not set, WFE suspends execution until
- * one of the following events occurs:
- * - an IRQ interrupt, unless masked by the CPSR I-bit
- * - an FIQ interrupt, unless masked by the CPSR F-bit
- * - an Imprecise Data abort, unless masked by the CPSR A-bit
- * - a Debug Entry request, if Debug is enabled
- * - an Event signaled by another processor using the SEV instruction.
- * If the Event Register is set, WFE clears it and returns immediately.
- * If WFE is implemented, SEV must also be implemented.
- */
-#define wfe() __asm__ __volatile__ ("wfe\n\t" : : );
-
-/* Move 0xd3 value to CPSR register to enable SVC mode */
-#define svc32_mode_en() __asm__ __volatile__ \
- ("@ I&F disable, Mode: 0x13 - SVC\n\t" \
- "msr cpsr_c, #0x13|0xC0\n\t" : : )
-
-/* Set program counter with the given value */
-#define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x))
-
-/* Branch to the given location */
-#define branch_bx(x) __asm__ __volatile__ ("bx %0\n\t" : : "r"(x))
-
-/* Read Main Id register */
-#define mrc_midr(x) __asm__ __volatile__ \
- ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(x) : )
-
-/* Read Multiprocessor Affinity Register */
-#define mrc_mpafr(x) __asm__ __volatile__ \
- ("mrc p15, 0, %0, c0, c0, 5\n\t" : "=r"(x) : )
-
-/* Read System Control Register */
-#define mrc_sctlr(x) __asm__ __volatile__ \
- ("mrc p15, 0, %0, c1, c0, 0\n\t" : "=r"(x) : )
-
-/* Read Auxiliary Control Register */
-#define mrc_auxr(x) __asm__ __volatile__ \
- ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(x) : )
-
-/* Read L2 Control register */
-#define mrc_l2_ctlr(x) __asm__ __volatile__ \
- ("mrc p15, 1, %0, c9, c0, 2\n\t" : "=r"(x) : )
-
-/* Read L2 Auxilliary Control register */
-#define mrc_l2_aux_ctlr(x) __asm__ __volatile__ \
- ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(x) : )
-
-/* Write System Control Register */
-#define mcr_sctlr(x) __asm__ __volatile__ \
- ("mcr p15, 0, %0, c1, c0, 0\n\t" : : "r"(x))
-
-/* Write Auxiliary Control Register */
-#define mcr_auxr(x) __asm__ __volatile__ \
- ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(x))
-
-/* Invalidate all instruction caches to PoU */
-#define mcr_icache(x) __asm__ __volatile__ \
- ("mcr p15, 0, %0, c7, c5, 0\n\t" : : "r"(x))
-
-/* Invalidate unified TLB */
-#define mcr_tlb(x) __asm__ __volatile__ \
- ("mcr p15, 0, %0, c8, c7, 0\n\t" : : "r"(x))
-
-/* Write L2 Control register */
-#define mcr_l2_ctlr(x) __asm__ __volatile__ \
- ("mcr p15, 1, %0, c9, c0, 2\n\t" : : "r"(x))
-
-/* Write L2 Auxilliary Control register */
-#define mcr_l2_aux_ctlr(x) __asm__ __volatile__ \
- ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(x))
-
-void set_usbhost_mode(unsigned int mode);
-void set_system_display_ctrl(void);
-int exynos_lcd_early_init(const void *blob);
-
-#endif /* _EXYNOS4_SYSTEM_H */
+++ /dev/null
-/*
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- * Akshay Saraswat <akshay.s@samsung.com>
- *
- * EXYNOS - Thermal Management Unit
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_TMU_H
-#define __ASM_ARCH_TMU_H
-
-struct exynos5_tmu_reg {
- u32 triminfo;
- u32 rsvd1[4];
- u32 triminfo_control;
- u32 rsvd5[2];
- u32 tmu_control;
- u32 rsvd7;
- u32 tmu_status;
- u32 sampling_internal;
- u32 counter_value0;
- u32 counter_value1;
- u32 rsvd8[2];
- u32 current_temp;
- u32 rsvd10[3];
- u32 threshold_temp_rise;
- u32 threshold_temp_fall;
- u32 rsvd13[2];
- u32 past_temp3_0;
- u32 past_temp7_4;
- u32 past_temp11_8;
- u32 past_temp15_12;
- u32 inten;
- u32 intstat;
- u32 intclear;
- u32 rsvd15;
- u32 emul_con;
-};
-#endif /* __ASM_ARCH_TMU_H */
+++ /dev/null
-/*
- * (C) Copyright 2012 Samsung Electronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __TZPC_H_
-#define __TZPC_H_
-
-#ifndef __ASSEMBLY__
-struct exynos_tzpc {
- unsigned int r0size;
- char res1[0x7FC];
- unsigned int decprot0stat;
- unsigned int decprot0set;
- unsigned int decprot0clr;
- unsigned int decprot1stat;
- unsigned int decprot1set;
- unsigned int decprot1clr;
- unsigned int decprot2stat;
- unsigned int decprot2set;
- unsigned int decprot2clr;
- unsigned int decprot3stat;
- unsigned int decprot3set;
- unsigned int decprot3clr;
- char res2[0x7B0];
- unsigned int periphid0;
- unsigned int periphid1;
- unsigned int periphid2;
- unsigned int periphid3;
- unsigned int pcellid0;
- unsigned int pcellid1;
- unsigned int pcellid2;
- unsigned int pcellid3;
-};
-
-#define EXYNOS4_NR_TZPC_BANKS 6
-#define EXYNOS5_NR_TZPC_BANKS 10
-
-/* TZPC : Register Offsets */
-#define TZPC_BASE_OFFSET 0x10000
-
-/*
- * TZPC Register Value :
- * R0SIZE: 0x0 : Size of secured ram
- */
-#define R0SIZE 0x0
-
-/*
- * TZPC Decode Protection Register Value :
- * DECPROTXSET: 0xFF : Set Decode region to non-secure
- */
-#define DECPROTXSET 0xFF
-void tzpc_init(void);
-
-#endif
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_UART_H_
-#define __ASM_ARCH_UART_H_
-
-#ifndef __ASSEMBLY__
-/* baudrate rest value */
-union br_rest {
- unsigned short slot; /* udivslot */
- unsigned char value; /* ufracval */
-};
-
-struct s5p_uart {
- unsigned int ulcon;
- unsigned int ucon;
- unsigned int ufcon;
- unsigned int umcon;
- unsigned int utrstat;
- unsigned int uerstat;
- unsigned int ufstat;
- unsigned int umstat;
- unsigned char utxh;
- unsigned char res1[3];
- unsigned char urxh;
- unsigned char res2[3];
- unsigned int ubrdiv;
- union br_rest rest;
- unsigned char res3[0xffd0];
-};
-
-static inline int s5p_uart_divslot(void)
-{
- return 0;
-}
-
-#endif /* __ASSEMBLY__ */
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2011 Samsung Electronics
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_WATCHDOG_H_
-#define __ASM_ARM_ARCH_WATCHDOG_H_
-
-#define WTCON_RESET_OFFSET 0
-#define WTCON_INTEN_OFFSET 2
-#define WTCON_CLKSEL_OFFSET 3
-#define WTCON_EN_OFFSET 5
-#define WTCON_PRE_OFFSET 8
-
-#define WTCON_CLK_16 0x0
-#define WTCON_CLK_32 0x1
-#define WTCON_CLK_64 0x2
-#define WTCON_CLK_128 0x3
-
-#define WTCON_CLK(x) ((x & 0x3) << WTCON_CLKSEL_OFFSET)
-#define WTCON_PRESCALER(x) ((x) << WTCON_PRE_OFFSET)
-#define WTCON_EN (0x1 << WTCON_EN_OFFSET)
-#define WTCON_RESET (0x1 << WTCON_RESET_OFFSET)
-#define WTCON_INT (0x1 << WTCON_INTEN_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct s5p_watchdog {
- unsigned int wtcon;
- unsigned int wtdat;
- unsigned int wtcnt;
- unsigned int wtclrint;
-};
-
-/* functions */
-void wdt_stop(void);
-void wdt_start(unsigned int timeout);
-#endif /* __ASSEMBLY__ */
-
-#endif
+++ /dev/null
-/* Copyright (c) 2012 Samsung Electronics Co. Ltd
- *
- * Exynos Phy register definitions
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_XHCI_EXYNOS_H_
-#define _ASM_ARCH_XHCI_EXYNOS_H_
-
-/* Phy register MACRO definitions */
-
-#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
-#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
-#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
-
-#define PHYUTMI_OTGDISABLE (1 << 6)
-#define PHYUTMI_FORCESUSPEND (1 << 1)
-#define PHYUTMI_FORCESLEEP (1 << 0)
-
-#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
-#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
-
-#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
-#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
-
-#define PHYCLKRST_SSC_EN (0x1 << 20)
-#define PHYCLKRST_REF_SSP_EN (0x1 << 19)
-#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
-
-#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
-#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
-#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
-#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
-#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
-#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
-
-#define PHYCLKRST_FSEL_MASK (0x3f << 5)
-#define PHYCLKRST_FSEL(_x) ((_x) << 5)
-#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
-#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
-#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
-#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
-
-#define PHYCLKRST_RETENABLEN (0x1 << 4)
-
-#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
-#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
-#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
-
-#define PHYCLKRST_PORTRESET (0x1 << 1)
-#define PHYCLKRST_COMMONONN (0x1 << 0)
-
-#define PHYPARAM0_REF_USE_PAD (0x1 << 31)
-#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
-#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
-
-#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
-#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
-
-#define PHYTEST_POWERDOWN_SSP (0x1 << 3)
-#define PHYTEST_POWERDOWN_HSP (0x1 << 2)
-
-#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
-
-#define FSEL_CLKSEL_24M (0x5)
-
-/* XHCI PHY register structure */
-struct exynos_usb3_phy {
- unsigned int reserve1;
- unsigned int link_system;
- unsigned int phy_utmi;
- unsigned int phy_pipe;
- unsigned int phy_clk_rst;
- unsigned int phy_reg0;
- unsigned int phy_reg1;
- unsigned int phy_param0;
- unsigned int phy_param1;
- unsigned int phy_term;
- unsigned int phy_test;
- unsigned int phy_adp;
- unsigned int phy_batchg;
- unsigned int phy_resume;
- unsigned int reserve2[3];
- unsigned int link_port;
-};
-
-#endif /* _ASM_ARCH_XHCI_EXYNOS_H_ */
--- /dev/null
+if ARCH_EXYNOS
+
+choice
+ prompt "EXYNOS board select"
+ optional
+
+config TARGET_SMDKV310
+ select SUPPORT_SPL
+ bool "Exynos4210 SMDKV310 board"
+ select OF_CONTROL
+ select SPL_DISABLE_OF_CONTROL
+
+config TARGET_TRATS
+ bool "Exynos4210 Trats board"
+
+config TARGET_S5PC210_UNIVERSAL
+ bool "EXYNOS4210 Universal C210 board"
+
+config TARGET_ORIGEN
+ bool "Exynos4412 Origen board"
+ select SUPPORT_SPL
+
+config TARGET_TRATS2
+ bool "Exynos4412 Trat2 board"
+
+config TARGET_ODROID
+ bool "Exynos4412 Odroid board"
+
+config TARGET_ODROID_XU3
+ bool "Exynos5422 Odroid board"
+ select OF_CONTROL
+ select SPL_DISABLE_OF_CONTROL
+
+config TARGET_ARNDALE
+ bool "Exynos5250 Arndale board"
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+ select SUPPORT_SPL
+ select OF_CONTROL
+ select SPL_DISABLE_OF_CONTROL
+
+config TARGET_SMDK5250
+ bool "SMDK5250 board"
+ select SUPPORT_SPL
+ select OF_CONTROL
+ select SPL_DISABLE_OF_CONTROL
+
+config TARGET_SNOW
+ bool "Snow board"
+ select SUPPORT_SPL
+ select OF_CONTROL
+ select SPL_DISABLE_OF_CONTROL
+
+config TARGET_SPRING
+ bool "Spring board"
+ select SUPPORT_SPL
+ select OF_CONTROL
+ select SPL_DISABLE_OF_CONTROL
+
+config TARGET_SMDK5420
+ bool "SMDK5420 board"
+ select SUPPORT_SPL
+ select OF_CONTROL
+ select SPL_DISABLE_OF_CONTROL
+
+config TARGET_PEACH_PI
+ bool "Peach Pi board"
+ select SUPPORT_SPL
+ select OF_CONTROL
+ select SPL_DISABLE_OF_CONTROL
+
+config TARGET_PEACH_PIT
+ bool "Peach Pit board"
+ select SUPPORT_SPL
+ select OF_CONTROL
+ select SPL_DISABLE_OF_CONTROL
+
+endchoice
+
+config SYS_SOC
+ default "exynos"
+
+source "board/samsung/smdkv310/Kconfig"
+source "board/samsung/trats/Kconfig"
+source "board/samsung/universal_c210/Kconfig"
+source "board/samsung/origen/Kconfig"
+source "board/samsung/trats2/Kconfig"
+source "board/samsung/odroid/Kconfig"
+source "board/samsung/arndale/Kconfig"
+source "board/samsung/smdk5250/Kconfig"
+source "board/samsung/smdk5420/Kconfig"
+
+endif
--- /dev/null
+#
+# Copyright (C) 2009 Samsung Electronics
+# Minkyu Kang <mk7.kang@samsung.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o
+
+obj-$(CONFIG_EXYNOS5420) += sec_boot.o
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
+obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
+obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
+obj-y += spl_boot.o
+obj-y += lowlevel_init.o
+endif
--- /dev/null
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/periph.h>
+
+#define PLL_DIV_1024 1024
+#define PLL_DIV_65535 65535
+#define PLL_DIV_65536 65536
+/* *
+ * This structure is to store the src bit, div bit and prediv bit
+ * positions of the peripheral clocks of the src and div registers
+ */
+struct clk_bit_info {
+ enum periph_id id;
+ int32_t src_mask;
+ int32_t div_mask;
+ int32_t prediv_mask;
+ int8_t src_bit;
+ int8_t div_bit;
+ int8_t prediv_bit;
+};
+
+static struct clk_bit_info exynos5_bit_info[] = {
+ /* periph id s_mask d_mask p_mask s_bit d_bit p_bit */
+ {PERIPH_ID_UART0, 0xf, 0xf, -1, 0, 0, -1},
+ {PERIPH_ID_UART1, 0xf, 0xf, -1, 4, 4, -1},
+ {PERIPH_ID_UART2, 0xf, 0xf, -1, 8, 8, -1},
+ {PERIPH_ID_UART3, 0xf, 0xf, -1, 12, 12, -1},
+ {PERIPH_ID_I2C0, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C1, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C2, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C3, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C4, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C5, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C6, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C7, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 16, 0, 8},
+ {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 20, 16, 24},
+ {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 24, 0, 8},
+ {PERIPH_ID_SDMMC0, 0xf, 0xf, 0xff, 0, 0, 8},
+ {PERIPH_ID_SDMMC1, 0xf, 0xf, 0xff, 4, 16, 24},
+ {PERIPH_ID_SDMMC2, 0xf, 0xf, 0xff, 8, 0, 8},
+ {PERIPH_ID_SDMMC3, 0xf, 0xf, 0xff, 12, 16, 24},
+ {PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4},
+ {PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16},
+ {PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 0, 0, 4},
+ {PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 4, 12, 16},
+ {PERIPH_ID_SDMMC4, 0xf, 0xf, 0xff, 16, 0, 8},
+ {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 0, -1},
+ {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 0, -1},
+ {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 0, -1},
+ {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 0, -1},
+ {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 0, -1},
+
+ {PERIPH_ID_NONE, -1, -1, -1, -1, -1, -1},
+};
+
+static struct clk_bit_info exynos542x_bit_info[] = {
+ /* periph id s_mask d_mask p_mask s_bit d_bit p_bit */
+ {PERIPH_ID_UART0, 0xf, 0xf, -1, 4, 8, -1},
+ {PERIPH_ID_UART1, 0xf, 0xf, -1, 8, 12, -1},
+ {PERIPH_ID_UART2, 0xf, 0xf, -1, 12, 16, -1},
+ {PERIPH_ID_UART3, 0xf, 0xf, -1, 16, 20, -1},
+ {PERIPH_ID_I2C0, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C1, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C2, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C3, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C4, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C5, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C6, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C7, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 20, 20, 8},
+ {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 24, 24, 16},
+ {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 28, 28, 24},
+ {PERIPH_ID_SDMMC0, 0x7, 0x3ff, -1, 8, 0, -1},
+ {PERIPH_ID_SDMMC1, 0x7, 0x3ff, -1, 12, 10, -1},
+ {PERIPH_ID_SDMMC2, 0x7, 0x3ff, -1, 16, 20, -1},
+ {PERIPH_ID_I2C8, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C9, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4},
+ {PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16},
+ {PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 12, 16, 0},
+ {PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 16, 20, 8},
+ {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 28, -1},
+ {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 28, -1},
+ {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 28, -1},
+ {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 28, -1},
+ {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 28, -1},
+ {PERIPH_ID_I2C10, -1, 0x3f, -1, -1, 8, -1},
+
+ {PERIPH_ID_NONE, -1, -1, -1, -1, -1, -1},
+};
+
+/* Epll Clock division values to achive different frequency output */
+static struct set_epll_con_val exynos5_epll_div[] = {
+ { 192000000, 0, 48, 3, 1, 0 },
+ { 180000000, 0, 45, 3, 1, 0 },
+ { 73728000, 1, 73, 3, 3, 47710 },
+ { 67737600, 1, 90, 4, 3, 20762 },
+ { 49152000, 0, 49, 3, 3, 9961 },
+ { 45158400, 0, 45, 3, 3, 10381 },
+ { 180633600, 0, 45, 3, 1, 10381 }
+};
+
+/* exynos: return pll clock frequency */
+static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
+{
+ unsigned long m, p, s = 0, mask, fout;
+ unsigned int div;
+ unsigned int freq;
+ /*
+ * APLL_CON: MIDV [25:16]
+ * MPLL_CON: MIDV [25:16]
+ * EPLL_CON: MIDV [24:16]
+ * VPLL_CON: MIDV [24:16]
+ * BPLL_CON: MIDV [25:16]: Exynos5
+ */
+ if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
+ pllreg == SPLL)
+ mask = 0x3ff;
+ else
+ mask = 0x1ff;
+
+ m = (r >> 16) & mask;
+
+ /* PDIV [13:8] */
+ p = (r >> 8) & 0x3f;
+ /* SDIV [2:0] */
+ s = r & 0x7;
+
+ freq = CONFIG_SYS_CLK_FREQ;
+
+ if (pllreg == EPLL || pllreg == RPLL) {
+ k = k & 0xffff;
+ /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
+ fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
+ } else if (pllreg == VPLL) {
+ k = k & 0xfff;
+
+ /*
+ * Exynos4210
+ * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
+ *
+ * Exynos4412
+ * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
+ *
+ * Exynos5250
+ * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
+ */
+ if (proid_is_exynos4210())
+ div = PLL_DIV_1024;
+ else if (proid_is_exynos4412())
+ div = PLL_DIV_65535;
+ else if (proid_is_exynos5250() || proid_is_exynos5420()
+ || proid_is_exynos5800())
+ div = PLL_DIV_65536;
+ else
+ return 0;
+
+ fout = (m + k / div) * (freq / (p * (1 << s)));
+ } else {
+ /*
+ * Exynos4412 / Exynos5250
+ * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
+ *
+ * Exynos4210
+ * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
+ */
+ if (proid_is_exynos4210())
+ fout = m * (freq / (p * (1 << (s - 1))));
+ else
+ fout = m * (freq / (p * (1 << s)));
+ }
+ return fout;
+}
+
+/* exynos4: return pll clock frequency */
+static unsigned long exynos4_get_pll_clk(int pllreg)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned long r, k = 0;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con0);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con0);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con0);
+ k = readl(&clk->epll_con1);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con0);
+ k = readl(&clk->vpll_con1);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ return exynos_get_pll_clk(pllreg, r, k);
+}
+
+/* exynos4x12: return pll clock frequency */
+static unsigned long exynos4x12_get_pll_clk(int pllreg)
+{
+ struct exynos4x12_clock *clk =
+ (struct exynos4x12_clock *)samsung_get_base_clock();
+ unsigned long r, k = 0;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con0);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con0);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con0);
+ k = readl(&clk->epll_con1);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con0);
+ k = readl(&clk->vpll_con1);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ return exynos_get_pll_clk(pllreg, r, k);
+}
+
+/* exynos5: return pll clock frequency */
+static unsigned long exynos5_get_pll_clk(int pllreg)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long r, k = 0, fout;
+ unsigned int pll_div2_sel, fout_sel;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con0);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con0);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con0);
+ k = readl(&clk->epll_con1);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con0);
+ k = readl(&clk->vpll_con1);
+ break;
+ case BPLL:
+ r = readl(&clk->bpll_con0);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ fout = exynos_get_pll_clk(pllreg, r, k);
+
+ /* According to the user manual, in EVT1 MPLL and BPLL always gives
+ * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
+ if (pllreg == MPLL || pllreg == BPLL) {
+ pll_div2_sel = readl(&clk->pll_div2_sel);
+
+ switch (pllreg) {
+ case MPLL:
+ fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
+ & MPLL_FOUT_SEL_MASK;
+ break;
+ case BPLL:
+ fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
+ & BPLL_FOUT_SEL_MASK;
+ break;
+ default:
+ fout_sel = -1;
+ break;
+ }
+
+ if (fout_sel == 0)
+ fout /= 2;
+ }
+
+ return fout;
+}
+
+/* exynos542x: return pll clock frequency */
+static unsigned long exynos542x_get_pll_clk(int pllreg)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long r, k = 0;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con0);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con0);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con0);
+ k = readl(&clk->epll_con1);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con0);
+ k = readl(&clk->vpll_con1);
+ break;
+ case BPLL:
+ r = readl(&clk->bpll_con0);
+ break;
+ case RPLL:
+ r = readl(&clk->rpll_con0);
+ k = readl(&clk->rpll_con1);
+ break;
+ case SPLL:
+ r = readl(&clk->spll_con0);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ return exynos_get_pll_clk(pllreg, r, k);
+}
+
+static struct clk_bit_info *get_clk_bit_info(int peripheral)
+{
+ int i;
+ struct clk_bit_info *info;
+
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ info = exynos542x_bit_info;
+ else
+ info = exynos5_bit_info;
+
+ for (i = 0; info[i].id != PERIPH_ID_NONE; i++) {
+ if (info[i].id == peripheral)
+ break;
+ }
+
+ if (info[i].id == PERIPH_ID_NONE)
+ debug("ERROR: Peripheral ID %d not found\n", peripheral);
+
+ return &info[i];
+}
+
+static unsigned long exynos5_get_periph_rate(int peripheral)
+{
+ struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
+ unsigned long sclk = 0;
+ unsigned int src = 0, div = 0, sub_div = 0;
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ src = readl(&clk->src_peric0);
+ div = readl(&clk->div_peric0);
+ break;
+ case PERIPH_ID_PWM0:
+ case PERIPH_ID_PWM1:
+ case PERIPH_ID_PWM2:
+ case PERIPH_ID_PWM3:
+ case PERIPH_ID_PWM4:
+ src = readl(&clk->src_peric0);
+ div = readl(&clk->div_peric3);
+ break;
+ case PERIPH_ID_I2S0:
+ src = readl(&clk->src_mau);
+ div = sub_div = readl(&clk->div_mau);
+ case PERIPH_ID_SPI0:
+ case PERIPH_ID_SPI1:
+ src = readl(&clk->src_peric1);
+ div = sub_div = readl(&clk->div_peric1);
+ break;
+ case PERIPH_ID_SPI2:
+ src = readl(&clk->src_peric1);
+ div = sub_div = readl(&clk->div_peric2);
+ break;
+ case PERIPH_ID_SPI3:
+ case PERIPH_ID_SPI4:
+ src = readl(&clk->sclk_src_isp);
+ div = sub_div = readl(&clk->sclk_div_isp);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ src = readl(&clk->src_fsys);
+ div = sub_div = readl(&clk->div_fsys1);
+ break;
+ case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC3:
+ src = readl(&clk->src_fsys);
+ div = sub_div = readl(&clk->div_fsys2);
+ break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ src = EXYNOS_SRC_MPLL;
+ div = readl(&clk->div_top1);
+ sub_div = readl(&clk->div_top0);
+ break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ };
+
+ if (bit_info->src_bit >= 0)
+ src = (src >> bit_info->src_bit) & bit_info->src_mask;
+
+ switch (src) {
+ case EXYNOS_SRC_MPLL:
+ sclk = exynos5_get_pll_clk(MPLL);
+ break;
+ case EXYNOS_SRC_EPLL:
+ sclk = exynos5_get_pll_clk(EPLL);
+ break;
+ case EXYNOS_SRC_VPLL:
+ sclk = exynos5_get_pll_clk(VPLL);
+ break;
+ default:
+ debug("%s: EXYNOS_SRC %d not supported\n", __func__, src);
+ return 0;
+ }
+
+ /* Clock divider ratio for this peripheral */
+ if (bit_info->div_bit >= 0)
+ div = (div >> bit_info->div_bit) & bit_info->div_mask;
+
+ /* Clock pre-divider ratio for this peripheral */
+ if (bit_info->prediv_bit >= 0)
+ sub_div = (sub_div >> bit_info->prediv_bit)
+ & bit_info->prediv_mask;
+
+ /* Calculate and return required clock rate */
+ return (sclk / (div + 1)) / (sub_div + 1);
+}
+
+static unsigned long exynos542x_get_periph_rate(int peripheral)
+{
+ struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
+ unsigned long sclk = 0;
+ unsigned int src = 0, div = 0, sub_div = 0;
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ case PERIPH_ID_PWM0:
+ case PERIPH_ID_PWM1:
+ case PERIPH_ID_PWM2:
+ case PERIPH_ID_PWM3:
+ case PERIPH_ID_PWM4:
+ src = readl(&clk->src_peric0);
+ div = readl(&clk->div_peric0);
+ break;
+ case PERIPH_ID_SPI0:
+ case PERIPH_ID_SPI1:
+ case PERIPH_ID_SPI2:
+ src = readl(&clk->src_peric1);
+ div = readl(&clk->div_peric1);
+ sub_div = readl(&clk->div_peric4);
+ break;
+ case PERIPH_ID_SPI3:
+ case PERIPH_ID_SPI4:
+ src = readl(&clk->src_isp);
+ div = readl(&clk->div_isp1);
+ sub_div = readl(&clk->div_isp1);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC3:
+ src = readl(&clk->src_fsys);
+ div = readl(&clk->div_fsys1);
+ break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ case PERIPH_ID_I2C8:
+ case PERIPH_ID_I2C9:
+ case PERIPH_ID_I2C10:
+ src = EXYNOS542X_SRC_MPLL;
+ div = readl(&clk->div_top1);
+ break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ };
+
+ if (bit_info->src_bit >= 0)
+ src = (src >> bit_info->src_bit) & bit_info->src_mask;
+
+ switch (src) {
+ case EXYNOS542X_SRC_MPLL:
+ sclk = exynos542x_get_pll_clk(MPLL);
+ break;
+ case EXYNOS542X_SRC_SPLL:
+ sclk = exynos542x_get_pll_clk(SPLL);
+ break;
+ case EXYNOS542X_SRC_EPLL:
+ sclk = exynos542x_get_pll_clk(EPLL);
+ break;
+ case EXYNOS542X_SRC_RPLL:
+ sclk = exynos542x_get_pll_clk(RPLL);
+ break;
+ default:
+ debug("%s: EXYNOS542X_SRC %d not supported", __func__, src);
+ return 0;
+ }
+
+ /* Clock divider ratio for this peripheral */
+ if (bit_info->div_bit >= 0)
+ div = (div >> bit_info->div_bit) & bit_info->div_mask;
+
+ /* Clock pre-divider ratio for this peripheral */
+ if (bit_info->prediv_bit >= 0)
+ sub_div = (sub_div >> bit_info->prediv_bit)
+ & bit_info->prediv_mask;
+
+ /* Calculate and return required clock rate */
+ return (sclk / (div + 1)) / (sub_div + 1);
+}
+
+unsigned long clock_get_periph_rate(int peripheral)
+{
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ return exynos542x_get_periph_rate(peripheral);
+ return exynos5_get_periph_rate(peripheral);
+ } else {
+ return 0;
+ }
+}
+
+/* exynos4: return ARM clock frequency */
+static unsigned long exynos4_get_arm_clk(void)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned long div;
+ unsigned long armclk;
+ unsigned int core_ratio;
+ unsigned int core2_ratio;
+
+ div = readl(&clk->div_cpu0);
+
+ /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
+ core_ratio = (div >> 0) & 0x7;
+ core2_ratio = (div >> 28) & 0x7;
+
+ armclk = get_pll_clk(APLL) / (core_ratio + 1);
+ armclk /= (core2_ratio + 1);
+
+ return armclk;
+}
+
+/* exynos4x12: return ARM clock frequency */
+static unsigned long exynos4x12_get_arm_clk(void)
+{
+ struct exynos4x12_clock *clk =
+ (struct exynos4x12_clock *)samsung_get_base_clock();
+ unsigned long div;
+ unsigned long armclk;
+ unsigned int core_ratio;
+ unsigned int core2_ratio;
+
+ div = readl(&clk->div_cpu0);
+
+ /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
+ core_ratio = (div >> 0) & 0x7;
+ core2_ratio = (div >> 28) & 0x7;
+
+ armclk = get_pll_clk(APLL) / (core_ratio + 1);
+ armclk /= (core2_ratio + 1);
+
+ return armclk;
+}
+
+/* exynos5: return ARM clock frequency */
+static unsigned long exynos5_get_arm_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long div;
+ unsigned long armclk;
+ unsigned int arm_ratio;
+ unsigned int arm2_ratio;
+
+ div = readl(&clk->div_cpu0);
+
+ /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
+ arm_ratio = (div >> 0) & 0x7;
+ arm2_ratio = (div >> 28) & 0x7;
+
+ armclk = get_pll_clk(APLL) / (arm_ratio + 1);
+ armclk /= (arm2_ratio + 1);
+
+ return armclk;
+}
+
+/* exynos4: return pwm clock frequency */
+static unsigned long exynos4_get_pwm_clk(void)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned long pclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ if (s5p_get_cpu_rev() == 0) {
+ /*
+ * CLK_SRC_PERIL0
+ * PWM_SEL [27:24]
+ */
+ sel = readl(&clk->src_peril0);
+ sel = (sel >> 24) & 0xf;
+
+ if (sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ /*
+ * CLK_DIV_PERIL3
+ * PWM_RATIO [3:0]
+ */
+ ratio = readl(&clk->div_peril3);
+ ratio = ratio & 0xf;
+ } else if (s5p_get_cpu_rev() == 1) {
+ sclk = get_pll_clk(MPLL);
+ ratio = 8;
+ } else
+ return 0;
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
+/* exynos4x12: return pwm clock frequency */
+static unsigned long exynos4x12_get_pwm_clk(void)
+{
+ unsigned long pclk, sclk;
+ unsigned int ratio;
+
+ sclk = get_pll_clk(MPLL);
+ ratio = 8;
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
+/* exynos4: return uart clock frequency */
+static unsigned long exynos4_get_uart_clk(int dev_index)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned long uclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+ * CLK_SRC_PERIL0
+ * UART0_SEL [3:0]
+ * UART1_SEL [7:4]
+ * UART2_SEL [8:11]
+ * UART3_SEL [12:15]
+ * UART4_SEL [16:19]
+ * UART5_SEL [23:20]
+ */
+ sel = readl(&clk->src_peril0);
+ sel = (sel >> (dev_index << 2)) & 0xf;
+
+ if (sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ /*
+ * CLK_DIV_PERIL0
+ * UART0_RATIO [3:0]
+ * UART1_RATIO [7:4]
+ * UART2_RATIO [8:11]
+ * UART3_RATIO [12:15]
+ * UART4_RATIO [16:19]
+ * UART5_RATIO [23:20]
+ */
+ ratio = readl(&clk->div_peril0);
+ ratio = (ratio >> (dev_index << 2)) & 0xf;
+
+ uclk = sclk / (ratio + 1);
+
+ return uclk;
+}
+
+/* exynos4x12: return uart clock frequency */
+static unsigned long exynos4x12_get_uart_clk(int dev_index)
+{
+ struct exynos4x12_clock *clk =
+ (struct exynos4x12_clock *)samsung_get_base_clock();
+ unsigned long uclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+ * CLK_SRC_PERIL0
+ * UART0_SEL [3:0]
+ * UART1_SEL [7:4]
+ * UART2_SEL [8:11]
+ * UART3_SEL [12:15]
+ * UART4_SEL [16:19]
+ */
+ sel = readl(&clk->src_peril0);
+ sel = (sel >> (dev_index << 2)) & 0xf;
+
+ if (sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ /*
+ * CLK_DIV_PERIL0
+ * UART0_RATIO [3:0]
+ * UART1_RATIO [7:4]
+ * UART2_RATIO [8:11]
+ * UART3_RATIO [12:15]
+ * UART4_RATIO [16:19]
+ */
+ ratio = readl(&clk->div_peril0);
+ ratio = (ratio >> (dev_index << 2)) & 0xf;
+
+ uclk = sclk / (ratio + 1);
+
+ return uclk;
+}
+
+static unsigned long exynos4_get_mmc_clk(int dev_index)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned long uclk, sclk;
+ unsigned int sel, ratio, pre_ratio;
+ int shift = 0;
+
+ sel = readl(&clk->src_fsys);
+ sel = (sel >> (dev_index << 2)) & 0xf;
+
+ if (sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ switch (dev_index) {
+ case 0:
+ case 1:
+ ratio = readl(&clk->div_fsys1);
+ pre_ratio = readl(&clk->div_fsys1);
+ break;
+ case 2:
+ case 3:
+ ratio = readl(&clk->div_fsys2);
+ pre_ratio = readl(&clk->div_fsys2);
+ break;
+ case 4:
+ ratio = readl(&clk->div_fsys3);
+ pre_ratio = readl(&clk->div_fsys3);
+ break;
+ default:
+ return 0;
+ }
+
+ if (dev_index == 1 || dev_index == 3)
+ shift = 16;
+
+ ratio = (ratio >> shift) & 0xf;
+ pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
+ uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
+
+ return uclk;
+}
+
+/* exynos4: set the mmc clock */
+static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned int addr, clear_bit, set_bit;
+
+ /*
+ * CLK_DIV_FSYS1
+ * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
+ * CLK_DIV_FSYS2
+ * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
+ * CLK_DIV_FSYS3
+ * MMC4_RATIO [3:0]
+ */
+ if (dev_index < 2) {
+ addr = (unsigned int)&clk->div_fsys1;
+ clear_bit = MASK_PRE_RATIO(dev_index);
+ set_bit = SET_PRE_RATIO(dev_index, div);
+ } else if (dev_index == 4) {
+ addr = (unsigned int)&clk->div_fsys3;
+ dev_index -= 4;
+ /* MMC4 is controlled with the MMC4_RATIO value */
+ clear_bit = MASK_RATIO(dev_index);
+ set_bit = SET_RATIO(dev_index, div);
+ } else {
+ addr = (unsigned int)&clk->div_fsys2;
+ dev_index -= 2;
+ clear_bit = MASK_PRE_RATIO(dev_index);
+ set_bit = SET_PRE_RATIO(dev_index, div);
+ }
+
+ clrsetbits_le32(addr, clear_bit, set_bit);
+}
+
+/* exynos5: set the mmc clock */
+static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned int addr;
+
+ /*
+ * CLK_DIV_FSYS1
+ * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
+ * CLK_DIV_FSYS2
+ * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
+ */
+ if (dev_index < 2) {
+ addr = (unsigned int)&clk->div_fsys1;
+ } else {
+ addr = (unsigned int)&clk->div_fsys2;
+ dev_index -= 2;
+ }
+
+ clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+ (div & 0xff) << ((dev_index << 4) + 8));
+}
+
+/* exynos5: set the mmc clock */
+static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned int addr;
+ unsigned int shift;
+
+ /*
+ * CLK_DIV_FSYS1
+ * MMC0_RATIO [9:0]
+ * MMC1_RATIO [19:10]
+ * MMC2_RATIO [29:20]
+ */
+ addr = (unsigned int)&clk->div_fsys1;
+ shift = dev_index * 10;
+
+ clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
+}
+
+/* get_lcd_clk: return lcd clock frequency */
+static unsigned long exynos4_get_lcd_clk(void)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned long pclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+ * CLK_SRC_LCD0
+ * FIMD0_SEL [3:0]
+ */
+ sel = readl(&clk->src_lcd0);
+ sel = sel & 0xf;
+
+ /*
+ * 0x6: SCLK_MPLL
+ * 0x7: SCLK_EPLL
+ * 0x8: SCLK_VPLL
+ */
+ if (sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ /*
+ * CLK_DIV_LCD0
+ * FIMD0_RATIO [3:0]
+ */
+ ratio = readl(&clk->div_lcd0);
+ ratio = ratio & 0xf;
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
+/* get_lcd_clk: return lcd clock frequency */
+static unsigned long exynos5_get_lcd_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long pclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+ * CLK_SRC_LCD0
+ * FIMD0_SEL [3:0]
+ */
+ sel = readl(&clk->src_disp1_0);
+ sel = sel & 0xf;
+
+ /*
+ * 0x6: SCLK_MPLL
+ * 0x7: SCLK_EPLL
+ * 0x8: SCLK_VPLL
+ */
+ if (sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ /*
+ * CLK_DIV_LCD0
+ * FIMD0_RATIO [3:0]
+ */
+ ratio = readl(&clk->div_disp1_0);
+ ratio = ratio & 0xf;
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
+static unsigned long exynos5420_get_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long pclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+ * CLK_SRC_DISP10
+ * FIMD1_SEL [4]
+ * 0: SCLK_RPLL
+ * 1: SCLK_SPLL
+ */
+ sel = readl(&clk->src_disp10);
+ sel &= (1 << 4);
+
+ if (sel)
+ sclk = get_pll_clk(SPLL);
+ else
+ sclk = get_pll_clk(RPLL);
+
+ /*
+ * CLK_DIV_DISP10
+ * FIMD1_RATIO [3:0]
+ */
+ ratio = readl(&clk->div_disp10);
+ ratio = ratio & 0xf;
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
+static unsigned long exynos5800_get_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+ * CLK_SRC_DISP10
+ * CLKMUX_FIMD1 [6:4]
+ */
+ sel = (readl(&clk->src_disp10) >> 4) & 0x7;
+
+ if (sel) {
+ /*
+ * Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into
+ * PLLs. The first element is a placeholder to bypass the
+ * default settig.
+ */
+ const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL,
+ RPLL};
+ sclk = get_pll_clk(reg_map[sel]);
+ } else
+ sclk = CONFIG_SYS_CLK_FREQ;
+ /*
+ * CLK_DIV_DISP10
+ * FIMD1_RATIO [3:0]
+ */
+ ratio = readl(&clk->div_disp10) & 0xf;
+
+ return sclk / (ratio + 1);
+}
+
+void exynos4_set_lcd_clk(void)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+
+ /*
+ * CLK_GATE_BLOCK
+ * CLK_CAM [0]
+ * CLK_TV [1]
+ * CLK_MFC [2]
+ * CLK_G3D [3]
+ * CLK_LCD0 [4]
+ * CLK_LCD1 [5]
+ * CLK_GPS [7]
+ */
+ setbits_le32(&clk->gate_block, 1 << 4);
+
+ /*
+ * CLK_SRC_LCD0
+ * FIMD0_SEL [3:0]
+ * MDNIE0_SEL [7:4]
+ * MDNIE_PWM0_SEL [8:11]
+ * MIPI0_SEL [12:15]
+ * set lcd0 src clock 0x6: SCLK_MPLL
+ */
+ clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
+
+ /*
+ * CLK_GATE_IP_LCD0
+ * CLK_FIMD0 [0]
+ * CLK_MIE0 [1]
+ * CLK_MDNIE0 [2]
+ * CLK_DSIM0 [3]
+ * CLK_SMMUFIMD0 [4]
+ * CLK_PPMULCD0 [5]
+ * Gating all clocks for FIMD0
+ */
+ setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
+
+ /*
+ * CLK_DIV_LCD0
+ * FIMD0_RATIO [3:0]
+ * MDNIE0_RATIO [7:4]
+ * MDNIE_PWM0_RATIO [11:8]
+ * MDNIE_PWM_PRE_RATIO [15:12]
+ * MIPI0_RATIO [19:16]
+ * MIPI0_PRE_RATIO [23:20]
+ * set fimd ratio
+ */
+ clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
+}
+
+void exynos5_set_lcd_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+
+ /*
+ * CLK_GATE_BLOCK
+ * CLK_CAM [0]
+ * CLK_TV [1]
+ * CLK_MFC [2]
+ * CLK_G3D [3]
+ * CLK_LCD0 [4]
+ * CLK_LCD1 [5]
+ * CLK_GPS [7]
+ */
+ setbits_le32(&clk->gate_block, 1 << 4);
+
+ /*
+ * CLK_SRC_LCD0
+ * FIMD0_SEL [3:0]
+ * MDNIE0_SEL [7:4]
+ * MDNIE_PWM0_SEL [8:11]
+ * MIPI0_SEL [12:15]
+ * set lcd0 src clock 0x6: SCLK_MPLL
+ */
+ clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);
+
+ /*
+ * CLK_GATE_IP_LCD0
+ * CLK_FIMD0 [0]
+ * CLK_MIE0 [1]
+ * CLK_MDNIE0 [2]
+ * CLK_DSIM0 [3]
+ * CLK_SMMUFIMD0 [4]
+ * CLK_PPMULCD0 [5]
+ * Gating all clocks for FIMD0
+ */
+ setbits_le32(&clk->gate_ip_disp1, 1 << 0);
+
+ /*
+ * CLK_DIV_LCD0
+ * FIMD0_RATIO [3:0]
+ * MDNIE0_RATIO [7:4]
+ * MDNIE_PWM0_RATIO [11:8]
+ * MDNIE_PWM_PRE_RATIO [15:12]
+ * MIPI0_RATIO [19:16]
+ * MIPI0_PRE_RATIO [23:20]
+ * set fimd ratio
+ */
+ clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
+}
+
+void exynos5420_set_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned int cfg;
+
+ /*
+ * CLK_SRC_DISP10
+ * FIMD1_SEL [4]
+ * 0: SCLK_RPLL
+ * 1: SCLK_SPLL
+ */
+ cfg = readl(&clk->src_disp10);
+ cfg &= ~(0x1 << 4);
+ cfg |= (0 << 4);
+ writel(cfg, &clk->src_disp10);
+
+ /*
+ * CLK_DIV_DISP10
+ * FIMD1_RATIO [3:0]
+ */
+ cfg = readl(&clk->div_disp10);
+ cfg &= ~(0xf << 0);
+ cfg |= (0 << 0);
+ writel(cfg, &clk->div_disp10);
+}
+
+void exynos5800_set_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned int cfg;
+
+ /*
+ * Use RPLL for pixel clock
+ * CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]
+ * ==================
+ * 111: SCLK_RPLL
+ */
+ cfg = readl(&clk->src_disp10) | (0x7 << 4);
+ writel(cfg, &clk->src_disp10);
+
+ /*
+ * CLK_DIV_DISP10
+ * FIMD1_RATIO [3:0]
+ */
+ clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0);
+}
+
+void exynos4_set_mipi_clk(void)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+
+ /*
+ * CLK_SRC_LCD0
+ * FIMD0_SEL [3:0]
+ * MDNIE0_SEL [7:4]
+ * MDNIE_PWM0_SEL [8:11]
+ * MIPI0_SEL [12:15]
+ * set mipi0 src clock 0x6: SCLK_MPLL
+ */
+ clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);
+
+ /*
+ * CLK_SRC_MASK_LCD0
+ * FIMD0_MASK [0]
+ * MDNIE0_MASK [4]
+ * MDNIE_PWM0_MASK [8]
+ * MIPI0_MASK [12]
+ * set src mask mipi0 0x1: Unmask
+ */
+ setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
+
+ /*
+ * CLK_GATE_IP_LCD0
+ * CLK_FIMD0 [0]
+ * CLK_MIE0 [1]
+ * CLK_MDNIE0 [2]
+ * CLK_DSIM0 [3]
+ * CLK_SMMUFIMD0 [4]
+ * CLK_PPMULCD0 [5]
+ * Gating all clocks for MIPI0
+ */
+ setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
+
+ /*
+ * CLK_DIV_LCD0
+ * FIMD0_RATIO [3:0]
+ * MDNIE0_RATIO [7:4]
+ * MDNIE_PWM0_RATIO [11:8]
+ * MDNIE_PWM_PRE_RATIO [15:12]
+ * MIPI0_RATIO [19:16]
+ * MIPI0_PRE_RATIO [23:20]
+ * set mipi ratio
+ */
+ clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
+}
+
+int exynos5_set_epll_clk(unsigned long rate)
+{
+ unsigned int epll_con, epll_con_k;
+ unsigned int i;
+ unsigned int lockcnt;
+ unsigned int start;
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+
+ epll_con = readl(&clk->epll_con0);
+ epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
+ EPLL_CON0_LOCK_DET_EN_SHIFT) |
+ EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
+ EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
+ EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
+
+ for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
+ if (exynos5_epll_div[i].freq_out == rate)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(exynos5_epll_div))
+ return -1;
+
+ epll_con_k = exynos5_epll_div[i].k_dsm << 0;
+ epll_con |= exynos5_epll_div[i].en_lock_det <<
+ EPLL_CON0_LOCK_DET_EN_SHIFT;
+ epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
+ epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
+ epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
+
+ /*
+ * Required period ( in cycles) to genarate a stable clock output.
+ * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
+ * frequency input (as per spec)
+ */
+ lockcnt = 3000 * exynos5_epll_div[i].p_div;
+
+ writel(lockcnt, &clk->epll_lock);
+ writel(epll_con, &clk->epll_con0);
+ writel(epll_con_k, &clk->epll_con1);
+
+ start = get_timer(0);
+
+ while (!(readl(&clk->epll_con0) &
+ (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
+ if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
+ debug("%s: Timeout waiting for EPLL lock\n", __func__);
+ return -1;
+ }
+ }
+ return 0;
+}
+
+int exynos5_set_i2s_clk_source(unsigned int i2s_id)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned int *audio_ass = (unsigned int *)samsung_get_base_audio_ass();
+
+ if (i2s_id == 0) {
+ setbits_le32(&clk->src_top2, CLK_SRC_MOUT_EPLL);
+ clrsetbits_le32(&clk->src_mau, AUDIO0_SEL_MASK,
+ (CLK_SRC_SCLK_EPLL));
+ setbits_le32(audio_ass, AUDIO_CLKMUX_ASS);
+ } else if (i2s_id == 1) {
+ clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
+ (CLK_SRC_SCLK_EPLL));
+ } else {
+ return -1;
+ }
+ return 0;
+}
+
+int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
+ unsigned int dst_frq,
+ unsigned int i2s_id)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned int div;
+
+ if ((dst_frq == 0) || (src_frq == 0)) {
+ debug("%s: Invalid requency input for prescaler\n", __func__);
+ debug("src frq = %d des frq = %d ", src_frq, dst_frq);
+ return -1;
+ }
+
+ div = (src_frq / dst_frq);
+ if (i2s_id == 0) {
+ if (div > AUDIO_0_RATIO_MASK) {
+ debug("%s: Frequency ratio is out of range\n",
+ __func__);
+ debug("src frq = %d des frq = %d ", src_frq, dst_frq);
+ return -1;
+ }
+ clrsetbits_le32(&clk->div_mau, AUDIO_0_RATIO_MASK,
+ (div & AUDIO_0_RATIO_MASK));
+ } else if (i2s_id == 1) {
+ if (div > AUDIO_1_RATIO_MASK) {
+ debug("%s: Frequency ratio is out of range\n",
+ __func__);
+ debug("src frq = %d des frq = %d ", src_frq, dst_frq);
+ return -1;
+ }
+ clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
+ (div & AUDIO_1_RATIO_MASK));
+ } else {
+ return -1;
+ }
+ return 0;
+}
+
+/**
+ * Linearly searches for the most accurate main and fine stage clock scalars
+ * (divisors) for a specified target frequency and scalar bit sizes by checking
+ * all multiples of main_scalar_bits values. Will always return scalars up to or
+ * slower than target.
+ *
+ * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
+ * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
+ * @param input_freq Clock frequency to be scaled in Hz
+ * @param target_freq Desired clock frequency in Hz
+ * @param best_fine_scalar Pointer to store the fine stage divisor
+ *
+ * @return best_main_scalar Main scalar for desired frequency or -1 if none
+ * found
+ */
+static int clock_calc_best_scalar(unsigned int main_scaler_bits,
+ unsigned int fine_scalar_bits, unsigned int input_rate,
+ unsigned int target_rate, unsigned int *best_fine_scalar)
+{
+ int i;
+ int best_main_scalar = -1;
+ unsigned int best_error = target_rate;
+ const unsigned int cap = (1 << fine_scalar_bits) - 1;
+ const unsigned int loops = 1 << main_scaler_bits;
+
+ debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
+ target_rate, cap);
+
+ assert(best_fine_scalar != NULL);
+ assert(main_scaler_bits <= fine_scalar_bits);
+
+ *best_fine_scalar = 1;
+
+ if (input_rate == 0 || target_rate == 0)
+ return -1;
+
+ if (target_rate >= input_rate)
+ return 1;
+
+ for (i = 1; i <= loops; i++) {
+ const unsigned int effective_div =
+ max(min(input_rate / i / target_rate, cap), 1U);
+ const unsigned int effective_rate = input_rate / i /
+ effective_div;
+ const int error = target_rate - effective_rate;
+
+ debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
+ effective_rate, error);
+
+ if (error >= 0 && error <= best_error) {
+ best_error = error;
+ best_main_scalar = i;
+ *best_fine_scalar = effective_div;
+ }
+ }
+
+ return best_main_scalar;
+}
+
+static int exynos5_set_spi_clk(enum periph_id periph_id,
+ unsigned int rate)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ int main;
+ unsigned int fine;
+ unsigned shift, pre_shift;
+ unsigned mask = 0xff;
+ u32 *reg;
+
+ main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
+ if (main < 0) {
+ debug("%s: Cannot set clock rate for periph %d",
+ __func__, periph_id);
+ return -1;
+ }
+ main = main - 1;
+ fine = fine - 1;
+
+ switch (periph_id) {
+ case PERIPH_ID_SPI0:
+ reg = &clk->div_peric1;
+ shift = 0;
+ pre_shift = 8;
+ break;
+ case PERIPH_ID_SPI1:
+ reg = &clk->div_peric1;
+ shift = 16;
+ pre_shift = 24;
+ break;
+ case PERIPH_ID_SPI2:
+ reg = &clk->div_peric2;
+ shift = 0;
+ pre_shift = 8;
+ break;
+ case PERIPH_ID_SPI3:
+ reg = &clk->sclk_div_isp;
+ shift = 0;
+ pre_shift = 4;
+ break;
+ case PERIPH_ID_SPI4:
+ reg = &clk->sclk_div_isp;
+ shift = 12;
+ pre_shift = 16;
+ break;
+ default:
+ debug("%s: Unsupported peripheral ID %d\n", __func__,
+ periph_id);
+ return -1;
+ }
+ clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
+ clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
+
+ return 0;
+}
+
+static int exynos5420_set_spi_clk(enum periph_id periph_id,
+ unsigned int rate)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ int main;
+ unsigned int fine;
+ unsigned shift, pre_shift;
+ unsigned div_mask = 0xf, pre_div_mask = 0xff;
+ u32 *reg;
+ u32 *pre_reg;
+
+ main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
+ if (main < 0) {
+ debug("%s: Cannot set clock rate for periph %d",
+ __func__, periph_id);
+ return -1;
+ }
+ main = main - 1;
+ fine = fine - 1;
+
+ switch (periph_id) {
+ case PERIPH_ID_SPI0:
+ reg = &clk->div_peric1;
+ shift = 20;
+ pre_reg = &clk->div_peric4;
+ pre_shift = 8;
+ break;
+ case PERIPH_ID_SPI1:
+ reg = &clk->div_peric1;
+ shift = 24;
+ pre_reg = &clk->div_peric4;
+ pre_shift = 16;
+ break;
+ case PERIPH_ID_SPI2:
+ reg = &clk->div_peric1;
+ shift = 28;
+ pre_reg = &clk->div_peric4;
+ pre_shift = 24;
+ break;
+ case PERIPH_ID_SPI3:
+ reg = &clk->div_isp1;
+ shift = 16;
+ pre_reg = &clk->div_isp1;
+ pre_shift = 0;
+ break;
+ case PERIPH_ID_SPI4:
+ reg = &clk->div_isp1;
+ shift = 20;
+ pre_reg = &clk->div_isp1;
+ pre_shift = 8;
+ break;
+ default:
+ debug("%s: Unsupported peripheral ID %d\n", __func__,
+ periph_id);
+ return -1;
+ }
+
+ clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift);
+ clrsetbits_le32(pre_reg, pre_div_mask << pre_shift,
+ (fine & pre_div_mask) << pre_shift);
+
+ return 0;
+}
+
+static unsigned long exynos4_get_i2c_clk(void)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned long sclk, aclk_100;
+ unsigned int ratio;
+
+ sclk = get_pll_clk(APLL);
+
+ ratio = (readl(&clk->div_top)) >> 4;
+ ratio &= 0xf;
+ aclk_100 = sclk / (ratio + 1);
+ return aclk_100;
+}
+
+unsigned long get_pll_clk(int pllreg)
+{
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ return exynos542x_get_pll_clk(pllreg);
+ return exynos5_get_pll_clk(pllreg);
+ } else if (cpu_is_exynos4()) {
+ if (proid_is_exynos4412())
+ return exynos4x12_get_pll_clk(pllreg);
+ return exynos4_get_pll_clk(pllreg);
+ }
+
+ return 0;
+}
+
+unsigned long get_arm_clk(void)
+{
+ if (cpu_is_exynos5()) {
+ return exynos5_get_arm_clk();
+ } else if (cpu_is_exynos4()) {
+ if (proid_is_exynos4412())
+ return exynos4x12_get_arm_clk();
+ return exynos4_get_arm_clk();
+ }
+
+ return 0;
+}
+
+unsigned long get_i2c_clk(void)
+{
+ if (cpu_is_exynos5())
+ return clock_get_periph_rate(PERIPH_ID_I2C0);
+ else if (cpu_is_exynos4())
+ return exynos4_get_i2c_clk();
+
+ return 0;
+}
+
+unsigned long get_pwm_clk(void)
+{
+ if (cpu_is_exynos5()) {
+ return clock_get_periph_rate(PERIPH_ID_PWM0);
+ } else if (cpu_is_exynos4()) {
+ if (proid_is_exynos4412())
+ return exynos4x12_get_pwm_clk();
+ return exynos4_get_pwm_clk();
+ }
+
+ return 0;
+}
+
+unsigned long get_uart_clk(int dev_index)
+{
+ enum periph_id id;
+
+ switch (dev_index) {
+ case 0:
+ id = PERIPH_ID_UART0;
+ break;
+ case 1:
+ id = PERIPH_ID_UART1;
+ break;
+ case 2:
+ id = PERIPH_ID_UART2;
+ break;
+ case 3:
+ id = PERIPH_ID_UART3;
+ break;
+ default:
+ debug("%s: invalid UART index %d", __func__, dev_index);
+ return -1;
+ }
+
+ if (cpu_is_exynos5()) {
+ return clock_get_periph_rate(id);
+ } else if (cpu_is_exynos4()) {
+ if (proid_is_exynos4412())
+ return exynos4x12_get_uart_clk(dev_index);
+ return exynos4_get_uart_clk(dev_index);
+ }
+
+ return 0;
+}
+
+unsigned long get_mmc_clk(int dev_index)
+{
+ enum periph_id id;
+
+ switch (dev_index) {
+ case 0:
+ id = PERIPH_ID_SDMMC0;
+ break;
+ case 1:
+ id = PERIPH_ID_SDMMC1;
+ break;
+ case 2:
+ id = PERIPH_ID_SDMMC2;
+ break;
+ case 3:
+ id = PERIPH_ID_SDMMC3;
+ break;
+ default:
+ debug("%s: invalid MMC index %d", __func__, dev_index);
+ return -1;
+ }
+
+ if (cpu_is_exynos5())
+ return clock_get_periph_rate(id);
+ else if (cpu_is_exynos4())
+ return exynos4_get_mmc_clk(dev_index);
+
+ return 0;
+}
+
+void set_mmc_clk(int dev_index, unsigned int div)
+{
+ /* If want to set correct value, it needs to substract one from div.*/
+ if (div > 0)
+ div -= 1;
+
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ exynos5420_set_mmc_clk(dev_index, div);
+ else
+ exynos5_set_mmc_clk(dev_index, div);
+ } else if (cpu_is_exynos4()) {
+ exynos4_set_mmc_clk(dev_index, div);
+ }
+}
+
+unsigned long get_lcd_clk(void)
+{
+ if (cpu_is_exynos4()) {
+ return exynos4_get_lcd_clk();
+ } else if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420())
+ return exynos5420_get_lcd_clk();
+ else if (proid_is_exynos5800())
+ return exynos5800_get_lcd_clk();
+ else
+ return exynos5_get_lcd_clk();
+ }
+
+ return 0;
+}
+
+void set_lcd_clk(void)
+{
+ if (cpu_is_exynos4()) {
+ exynos4_set_lcd_clk();
+ } else if (cpu_is_exynos5()) {
+ if (proid_is_exynos5250())
+ exynos5_set_lcd_clk();
+ else if (proid_is_exynos5420())
+ exynos5420_set_lcd_clk();
+ else
+ exynos5800_set_lcd_clk();
+ }
+}
+
+void set_mipi_clk(void)
+{
+ if (cpu_is_exynos4())
+ exynos4_set_mipi_clk();
+}
+
+int set_spi_clk(int periph_id, unsigned int rate)
+{
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ return exynos5420_set_spi_clk(periph_id, rate);
+ return exynos5_set_spi_clk(periph_id, rate);
+ }
+
+ return 0;
+}
+
+int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
+ unsigned int i2s_id)
+{
+ if (cpu_is_exynos5())
+ return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq, i2s_id);
+
+ return 0;
+}
+
+int set_i2s_clk_source(unsigned int i2s_id)
+{
+ if (cpu_is_exynos5())
+ return exynos5_set_i2s_clk_source(i2s_id);
+
+ return 0;
+}
+
+int set_epll_clk(unsigned long rate)
+{
+ if (cpu_is_exynos5())
+ return exynos5_set_epll_clk(rate);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Clock initialization routines
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __EXYNOS_CLOCK_INIT_H
+#define __EXYNOS_CLOCK_INIT_H
+
+enum {
+#ifdef CONFIG_EXYNOS5420
+ MEM_TIMINGS_MSR_COUNT = 5,
+#else
+ MEM_TIMINGS_MSR_COUNT = 4,
+#endif
+};
+
+/* These are the ratio's for configuring ARM clock */
+struct arm_clk_ratios {
+ unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */
+
+ unsigned apll_mdiv;
+ unsigned apll_pdiv;
+ unsigned apll_sdiv;
+
+ unsigned arm2_ratio;
+ unsigned apll_ratio;
+ unsigned pclk_dbg_ratio;
+ unsigned atb_ratio;
+ unsigned periph_ratio;
+ unsigned acp_ratio;
+ unsigned cpud_ratio;
+ unsigned arm_ratio;
+};
+
+/* These are the memory timings for a particular memory type and speed */
+struct mem_timings {
+ enum mem_manuf mem_manuf; /* Memory manufacturer */
+ enum ddr_mode mem_type; /* Memory type */
+ unsigned frequency_mhz; /* Frequency of memory in MHz */
+
+ /* Here follow the timing parameters for the selected memory */
+ unsigned apll_mdiv;
+ unsigned apll_pdiv;
+ unsigned apll_sdiv;
+ unsigned mpll_mdiv;
+ unsigned mpll_pdiv;
+ unsigned mpll_sdiv;
+ unsigned cpll_mdiv;
+ unsigned cpll_pdiv;
+ unsigned cpll_sdiv;
+ unsigned gpll_mdiv;
+ unsigned gpll_pdiv;
+ unsigned gpll_sdiv;
+ unsigned epll_mdiv;
+ unsigned epll_pdiv;
+ unsigned epll_sdiv;
+ unsigned vpll_mdiv;
+ unsigned vpll_pdiv;
+ unsigned vpll_sdiv;
+ unsigned bpll_mdiv;
+ unsigned bpll_pdiv;
+ unsigned bpll_sdiv;
+ unsigned kpll_mdiv;
+ unsigned kpll_pdiv;
+ unsigned kpll_sdiv;
+ unsigned dpll_mdiv;
+ unsigned dpll_pdiv;
+ unsigned dpll_sdiv;
+ unsigned ipll_mdiv;
+ unsigned ipll_pdiv;
+ unsigned ipll_sdiv;
+ unsigned spll_mdiv;
+ unsigned spll_pdiv;
+ unsigned spll_sdiv;
+ unsigned rpll_mdiv;
+ unsigned rpll_pdiv;
+ unsigned rpll_sdiv;
+ unsigned pclk_cdrex_ratio;
+ unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
+
+ unsigned timing_ref;
+ unsigned timing_row;
+ unsigned timing_data;
+ unsigned timing_power;
+
+ /* DQS, DQ, DEBUG offsets */
+ unsigned phy0_dqs;
+ unsigned phy1_dqs;
+ unsigned phy0_dq;
+ unsigned phy1_dq;
+ unsigned phy0_tFS;
+ unsigned phy1_tFS;
+ unsigned phy0_pulld_dqs;
+ unsigned phy1_pulld_dqs;
+
+ unsigned lpddr3_ctrl_phy_reset;
+ unsigned ctrl_start_point;
+ unsigned ctrl_inc;
+ unsigned ctrl_start;
+ unsigned ctrl_dll_on;
+ unsigned ctrl_ref;
+
+ unsigned ctrl_force;
+ unsigned ctrl_rdlat;
+ unsigned ctrl_bstlen;
+
+ unsigned fp_resync;
+ unsigned iv_size;
+ unsigned dfi_init_start;
+ unsigned aref_en;
+
+ unsigned rd_fetch;
+
+ unsigned zq_mode_dds;
+ unsigned zq_mode_term;
+ unsigned zq_mode_noterm; /* 1 to allow termination disable */
+
+ unsigned memcontrol;
+ unsigned memconfig;
+
+ unsigned membaseconfig0;
+ unsigned membaseconfig1;
+ unsigned prechconfig_tp_cnt;
+ unsigned dpwrdn_cyc;
+ unsigned dsref_cyc;
+ unsigned concontrol;
+ /* Channel and Chip Selection */
+ uint8_t dmc_channels; /* number of memory channels */
+ uint8_t chips_per_channel; /* number of chips per channel */
+ uint8_t chips_to_configure; /* number of chips to configure */
+ uint8_t send_zq_init; /* 1 to send this command */
+ unsigned impedance; /* drive strength impedeance */
+ uint8_t gate_leveling_enable; /* check gate leveling is enabled */
+ uint8_t read_leveling_enable; /* check h/w read leveling is enabled */
+};
+
+/**
+ * Get the correct memory timings for our selected memory type and speed.
+ *
+ * This function can be called from SPL or the main U-Boot.
+ *
+ * @return pointer to the memory timings that we should use
+ */
+struct mem_timings *clock_get_mem_timings(void);
+
+/*
+ * Initialize clock for the device
+ */
+void system_clock_init(void);
+
+/*
+ * Set clock divisor value for booting from EMMC.
+ */
+void emmc_boot_clk_div_set(void);
+#endif
--- /dev/null
+/*
+ * Clock Initialization for board based on EXYNOS4210
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/clock.h>
+#include "common_setup.h"
+#include "exynos4_setup.h"
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+void system_clock_init(void)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+
+ writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
+
+ sdelay(0x10000);
+
+ writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+ writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+ writel(CLK_SRC_DMC_VAL, &clk->src_dmc);
+ writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus);
+ writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus);
+ writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
+ writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0);
+ writel(CLK_SRC_CAM_VAL, &clk->src_cam);
+ writel(CLK_SRC_MFC_VAL, &clk->src_mfc);
+ writel(CLK_SRC_G3D_VAL, &clk->src_g3d);
+ writel(CLK_SRC_LCD0_VAL, &clk->src_lcd0);
+
+ sdelay(0x10000);
+
+ writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
+ writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
+ writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0);
+ writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1);
+ writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus);
+ writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus);
+ writel(CLK_DIV_TOP_VAL, &clk->div_top);
+ writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
+ writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
+ writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
+ writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0);
+ writel(CLK_DIV_CAM_VAL, &clk->div_cam);
+ writel(CLK_DIV_MFC_VAL, &clk->div_mfc);
+ writel(CLK_DIV_G3D_VAL, &clk->div_g3d);
+ writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0);
+
+ /* Set PLL locktime */
+ writel(PLL_LOCKTIME, &clk->apll_lock);
+ writel(PLL_LOCKTIME, &clk->mpll_lock);
+ writel(PLL_LOCKTIME, &clk->epll_lock);
+ writel(PLL_LOCKTIME, &clk->vpll_lock);
+
+ writel(APLL_CON1_VAL, &clk->apll_con1);
+ writel(APLL_CON0_VAL, &clk->apll_con0);
+ writel(MPLL_CON1_VAL, &clk->mpll_con1);
+ writel(MPLL_CON0_VAL, &clk->mpll_con0);
+ writel(EPLL_CON1_VAL, &clk->epll_con1);
+ writel(EPLL_CON0_VAL, &clk->epll_con0);
+ writel(VPLL_CON1_VAL, &clk->vpll_con1);
+ writel(VPLL_CON0_VAL, &clk->vpll_con0);
+
+ sdelay(0x30000);
+}
--- /dev/null
+/*
+ * Clock setup for SMDK5250 board based on EXYNOS5
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/dwmmc.h>
+
+#include "clock_init.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
+
+#define FSYS1_MMC0_DIV_MASK 0xff0f
+#define FSYS1_MMC0_DIV_VAL 0x0701
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct arm_clk_ratios arm_clk_ratios[] = {
+#ifdef CONFIG_EXYNOS5420
+ {
+ .arm_freq_mhz = 900,
+
+ .apll_mdiv = 0x96,
+ .apll_pdiv = 0x2,
+ .apll_sdiv = 0x1,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x3,
+ .pclk_dbg_ratio = 0x6,
+ .atb_ratio = 0x6,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x0,
+ .cpud_ratio = 0x2,
+ .arm_ratio = 0x0,
+ }
+#else
+ {
+ .arm_freq_mhz = 600,
+
+ .apll_mdiv = 0xc8,
+ .apll_pdiv = 0x4,
+ .apll_sdiv = 0x1,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x1,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x2,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x1,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 800,
+
+ .apll_mdiv = 0x64,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x1,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x3,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x2,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1000,
+
+ .apll_mdiv = 0x7d,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x1,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x4,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x2,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1200,
+
+ .apll_mdiv = 0x96,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x3,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x5,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x3,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1400,
+
+ .apll_mdiv = 0xaf,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x3,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x6,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x3,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1700,
+
+ .apll_mdiv = 0x1a9,
+ .apll_pdiv = 0x6,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x3,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x6,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x3,
+ .arm_ratio = 0x0,
+ }
+#endif
+};
+
+struct mem_timings mem_timings[] = {
+#ifdef CONFIG_EXYNOS5420
+ {
+ .mem_manuf = MEM_MANUF_SAMSUNG,
+ .mem_type = DDR_MODE_DDR3,
+ .frequency_mhz = 800,
+
+ /* MPLL @800MHz*/
+ .mpll_mdiv = 0xc8,
+ .mpll_pdiv = 0x3,
+ .mpll_sdiv = 0x1,
+ /* CPLL @666MHz */
+ .cpll_mdiv = 0xde,
+ .cpll_pdiv = 0x4,
+ .cpll_sdiv = 0x1,
+ /* EPLL @600MHz */
+ .epll_mdiv = 0x64,
+ .epll_pdiv = 0x2,
+ .epll_sdiv = 0x1,
+ /* VPLL @430MHz */
+ .vpll_mdiv = 0xd7,
+ .vpll_pdiv = 0x3,
+ .vpll_sdiv = 0x2,
+ /* BPLL @800MHz */
+ .bpll_mdiv = 0xc8,
+ .bpll_pdiv = 0x3,
+ .bpll_sdiv = 0x1,
+ /* KPLL @600MHz */
+ .kpll_mdiv = 0x190,
+ .kpll_pdiv = 0x4,
+ .kpll_sdiv = 0x2,
+ /* DPLL @600MHz */
+ .dpll_mdiv = 0x190,
+ .dpll_pdiv = 0x4,
+ .dpll_sdiv = 0x2,
+ /* IPLL @370MHz */
+ .ipll_mdiv = 0xb9,
+ .ipll_pdiv = 0x3,
+ .ipll_sdiv = 0x2,
+ /* SPLL @400MHz */
+ .spll_mdiv = 0xc8,
+ .spll_pdiv = 0x3,
+ .spll_sdiv = 0x2,
+ /* RPLL @141Mhz */
+ .rpll_mdiv = 0x5E,
+ .rpll_pdiv = 0x2,
+ .rpll_sdiv = 0x3,
+
+ .direct_cmd_msr = {
+ 0x00020018, 0x00030000, 0x00010046, 0x00000d70,
+ 0x00000c70
+ },
+ .timing_ref = 0x000000bb,
+ .timing_row = 0x6836650f,
+ .timing_data = 0x3630580b,
+ .timing_power = 0x41000a26,
+ .phy0_dqs = 0x08080808,
+ .phy1_dqs = 0x08080808,
+ .phy0_dq = 0x08080808,
+ .phy1_dq = 0x08080808,
+ .phy0_tFS = 0x8,
+ .phy1_tFS = 0x8,
+ .phy0_pulld_dqs = 0xf,
+ .phy1_pulld_dqs = 0xf,
+
+ .lpddr3_ctrl_phy_reset = 0x1,
+ .ctrl_start_point = 0x10,
+ .ctrl_inc = 0x10,
+ .ctrl_start = 0x1,
+ .ctrl_dll_on = 0x1,
+ .ctrl_ref = 0x8,
+
+ .ctrl_force = 0x1a,
+ .ctrl_rdlat = 0x0b,
+ .ctrl_bstlen = 0x08,
+
+ .fp_resync = 0x8,
+ .iv_size = 0x7,
+ .dfi_init_start = 1,
+ .aref_en = 1,
+
+ .rd_fetch = 0x3,
+
+ .zq_mode_dds = 0x7,
+ .zq_mode_term = 0x1,
+ .zq_mode_noterm = 1,
+
+ /*
+ * Dynamic Clock: Always Running
+ * Memory Burst length: 8
+ * Number of chips: 1
+ * Memory Bus width: 32 bit
+ * Memory Type: DDR3
+ * Additional Latancy for PLL: 0 Cycle
+ */
+ .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
+ DMC_MEMCONTROL_DPWRDN_DISABLE |
+ DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
+ DMC_MEMCONTROL_TP_DISABLE |
+ DMC_MEMCONTROL_DSREF_DISABLE |
+ DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
+ DMC_MEMCONTROL_MEM_TYPE_DDR3 |
+ DMC_MEMCONTROL_MEM_WIDTH_32BIT |
+ DMC_MEMCONTROL_NUM_CHIP_1 |
+ DMC_MEMCONTROL_BL_8 |
+ DMC_MEMCONTROL_PZQ_DISABLE |
+ DMC_MEMCONTROL_MRR_BYTE_7_0,
+ .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
+ DMC_MEMCONFIGX_CHIP_COL_10 |
+ DMC_MEMCONFIGX_CHIP_ROW_15 |
+ DMC_MEMCONFIGX_CHIP_BANK_8,
+ .prechconfig_tp_cnt = 0xff,
+ .dpwrdn_cyc = 0xff,
+ .dsref_cyc = 0xffff,
+ .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
+ DMC_CONCONTROL_TIMEOUT_LEVEL0 |
+ DMC_CONCONTROL_RD_FETCH_DISABLE |
+ DMC_CONCONTROL_EMPTY_DISABLE |
+ DMC_CONCONTROL_AREF_EN_DISABLE |
+ DMC_CONCONTROL_IO_PD_CON_DISABLE,
+ .dmc_channels = 1,
+ .chips_per_channel = 1,
+ .chips_to_configure = 1,
+ .send_zq_init = 1,
+ .gate_leveling_enable = 1,
+ .read_leveling_enable = 0,
+ }
+#else
+ {
+ .mem_manuf = MEM_MANUF_ELPIDA,
+ .mem_type = DDR_MODE_DDR3,
+ .frequency_mhz = 800,
+ .mpll_mdiv = 0xc8,
+ .mpll_pdiv = 0x3,
+ .mpll_sdiv = 0x0,
+ .cpll_mdiv = 0xde,
+ .cpll_pdiv = 0x4,
+ .cpll_sdiv = 0x2,
+ .gpll_mdiv = 0x215,
+ .gpll_pdiv = 0xc,
+ .gpll_sdiv = 0x1,
+ .epll_mdiv = 0x60,
+ .epll_pdiv = 0x3,
+ .epll_sdiv = 0x3,
+ .vpll_mdiv = 0x96,
+ .vpll_pdiv = 0x3,
+ .vpll_sdiv = 0x2,
+
+ .bpll_mdiv = 0x64,
+ .bpll_pdiv = 0x3,
+ .bpll_sdiv = 0x0,
+ .pclk_cdrex_ratio = 0x5,
+ .direct_cmd_msr = {
+ 0x00020018, 0x00030000, 0x00010042, 0x00000d70
+ },
+ .timing_ref = 0x000000bb,
+ .timing_row = 0x8c36650e,
+ .timing_data = 0x3630580b,
+ .timing_power = 0x41000a44,
+ .phy0_dqs = 0x08080808,
+ .phy1_dqs = 0x08080808,
+ .phy0_dq = 0x08080808,
+ .phy1_dq = 0x08080808,
+ .phy0_tFS = 0x4,
+ .phy1_tFS = 0x4,
+ .phy0_pulld_dqs = 0xf,
+ .phy1_pulld_dqs = 0xf,
+
+ .lpddr3_ctrl_phy_reset = 0x1,
+ .ctrl_start_point = 0x10,
+ .ctrl_inc = 0x10,
+ .ctrl_start = 0x1,
+ .ctrl_dll_on = 0x1,
+ .ctrl_ref = 0x8,
+
+ .ctrl_force = 0x1a,
+ .ctrl_rdlat = 0x0b,
+ .ctrl_bstlen = 0x08,
+
+ .fp_resync = 0x8,
+ .iv_size = 0x7,
+ .dfi_init_start = 1,
+ .aref_en = 1,
+
+ .rd_fetch = 0x3,
+
+ .zq_mode_dds = 0x7,
+ .zq_mode_term = 0x1,
+ .zq_mode_noterm = 0,
+
+ /*
+ * Dynamic Clock: Always Running
+ * Memory Burst length: 8
+ * Number of chips: 1
+ * Memory Bus width: 32 bit
+ * Memory Type: DDR3
+ * Additional Latancy for PLL: 0 Cycle
+ */
+ .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
+ DMC_MEMCONTROL_DPWRDN_DISABLE |
+ DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
+ DMC_MEMCONTROL_TP_DISABLE |
+ DMC_MEMCONTROL_DSREF_ENABLE |
+ DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
+ DMC_MEMCONTROL_MEM_TYPE_DDR3 |
+ DMC_MEMCONTROL_MEM_WIDTH_32BIT |
+ DMC_MEMCONTROL_NUM_CHIP_1 |
+ DMC_MEMCONTROL_BL_8 |
+ DMC_MEMCONTROL_PZQ_DISABLE |
+ DMC_MEMCONTROL_MRR_BYTE_7_0,
+ .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
+ DMC_MEMCONFIGX_CHIP_COL_10 |
+ DMC_MEMCONFIGX_CHIP_ROW_15 |
+ DMC_MEMCONFIGX_CHIP_BANK_8,
+ .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
+ .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
+ .prechconfig_tp_cnt = 0xff,
+ .dpwrdn_cyc = 0xff,
+ .dsref_cyc = 0xffff,
+ .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
+ DMC_CONCONTROL_TIMEOUT_LEVEL0 |
+ DMC_CONCONTROL_RD_FETCH_DISABLE |
+ DMC_CONCONTROL_EMPTY_DISABLE |
+ DMC_CONCONTROL_AREF_EN_DISABLE |
+ DMC_CONCONTROL_IO_PD_CON_DISABLE,
+ .dmc_channels = 2,
+ .chips_per_channel = 2,
+ .chips_to_configure = 1,
+ .send_zq_init = 1,
+ .impedance = IMP_OUTPUT_DRV_30_OHM,
+ .gate_leveling_enable = 0,
+ }, {
+ .mem_manuf = MEM_MANUF_SAMSUNG,
+ .mem_type = DDR_MODE_DDR3,
+ .frequency_mhz = 800,
+ .mpll_mdiv = 0xc8,
+ .mpll_pdiv = 0x3,
+ .mpll_sdiv = 0x0,
+ .cpll_mdiv = 0xde,
+ .cpll_pdiv = 0x4,
+ .cpll_sdiv = 0x2,
+ .gpll_mdiv = 0x215,
+ .gpll_pdiv = 0xc,
+ .gpll_sdiv = 0x1,
+ .epll_mdiv = 0x60,
+ .epll_pdiv = 0x3,
+ .epll_sdiv = 0x3,
+ .vpll_mdiv = 0x96,
+ .vpll_pdiv = 0x3,
+ .vpll_sdiv = 0x2,
+
+ .bpll_mdiv = 0x64,
+ .bpll_pdiv = 0x3,
+ .bpll_sdiv = 0x0,
+ .pclk_cdrex_ratio = 0x5,
+ .direct_cmd_msr = {
+ 0x00020018, 0x00030000, 0x00010000, 0x00000d70
+ },
+ .timing_ref = 0x000000bb,
+ .timing_row = 0x8c36650e,
+ .timing_data = 0x3630580b,
+ .timing_power = 0x41000a44,
+ .phy0_dqs = 0x08080808,
+ .phy1_dqs = 0x08080808,
+ .phy0_dq = 0x08080808,
+ .phy1_dq = 0x08080808,
+ .phy0_tFS = 0x8,
+ .phy1_tFS = 0x8,
+ .phy0_pulld_dqs = 0xf,
+ .phy1_pulld_dqs = 0xf,
+
+ .lpddr3_ctrl_phy_reset = 0x1,
+ .ctrl_start_point = 0x10,
+ .ctrl_inc = 0x10,
+ .ctrl_start = 0x1,
+ .ctrl_dll_on = 0x1,
+ .ctrl_ref = 0x8,
+
+ .ctrl_force = 0x1a,
+ .ctrl_rdlat = 0x0b,
+ .ctrl_bstlen = 0x08,
+
+ .fp_resync = 0x8,
+ .iv_size = 0x7,
+ .dfi_init_start = 1,
+ .aref_en = 1,
+
+ .rd_fetch = 0x3,
+
+ .zq_mode_dds = 0x5,
+ .zq_mode_term = 0x1,
+ .zq_mode_noterm = 1,
+
+ /*
+ * Dynamic Clock: Always Running
+ * Memory Burst length: 8
+ * Number of chips: 1
+ * Memory Bus width: 32 bit
+ * Memory Type: DDR3
+ * Additional Latancy for PLL: 0 Cycle
+ */
+ .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
+ DMC_MEMCONTROL_DPWRDN_DISABLE |
+ DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
+ DMC_MEMCONTROL_TP_DISABLE |
+ DMC_MEMCONTROL_DSREF_ENABLE |
+ DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
+ DMC_MEMCONTROL_MEM_TYPE_DDR3 |
+ DMC_MEMCONTROL_MEM_WIDTH_32BIT |
+ DMC_MEMCONTROL_NUM_CHIP_1 |
+ DMC_MEMCONTROL_BL_8 |
+ DMC_MEMCONTROL_PZQ_DISABLE |
+ DMC_MEMCONTROL_MRR_BYTE_7_0,
+ .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
+ DMC_MEMCONFIGX_CHIP_COL_10 |
+ DMC_MEMCONFIGX_CHIP_ROW_15 |
+ DMC_MEMCONFIGX_CHIP_BANK_8,
+ .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
+ .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
+ .prechconfig_tp_cnt = 0xff,
+ .dpwrdn_cyc = 0xff,
+ .dsref_cyc = 0xffff,
+ .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
+ DMC_CONCONTROL_TIMEOUT_LEVEL0 |
+ DMC_CONCONTROL_RD_FETCH_DISABLE |
+ DMC_CONCONTROL_EMPTY_DISABLE |
+ DMC_CONCONTROL_AREF_EN_DISABLE |
+ DMC_CONCONTROL_IO_PD_CON_DISABLE,
+ .dmc_channels = 2,
+ .chips_per_channel = 2,
+ .chips_to_configure = 1,
+ .send_zq_init = 1,
+ .impedance = IMP_OUTPUT_DRV_40_OHM,
+ .gate_leveling_enable = 1,
+ }
+#endif
+};
+
+/**
+ * Get the required memory type and speed (SPL version).
+ *
+ * In SPL we have no device tree, so we use the machine parameters
+ *
+ * @param mem_type Returns memory type
+ * @param frequency_mhz Returns memory speed in MHz
+ * @param arm_freq Returns ARM clock speed in MHz
+ * @param mem_manuf Return Memory Manufacturer name
+ */
+static void clock_get_mem_selection(enum ddr_mode *mem_type,
+ unsigned *frequency_mhz, unsigned *arm_freq,
+ enum mem_manuf *mem_manuf)
+{
+ struct spl_machine_param *params;
+
+ params = spl_get_machine_params();
+ *mem_type = params->mem_type;
+ *frequency_mhz = params->frequency_mhz;
+ *arm_freq = params->arm_freq_mhz;
+ *mem_manuf = params->mem_manuf;
+}
+
+/* Get the ratios for setting ARM clock */
+struct arm_clk_ratios *get_arm_ratios(void)
+{
+ struct arm_clk_ratios *arm_ratio;
+ enum ddr_mode mem_type;
+ enum mem_manuf mem_manuf;
+ unsigned frequency_mhz, arm_freq;
+ int i;
+
+ clock_get_mem_selection(&mem_type, &frequency_mhz,
+ &arm_freq, &mem_manuf);
+
+ for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
+ i++, arm_ratio++) {
+ if (arm_ratio->arm_freq_mhz == arm_freq)
+ return arm_ratio;
+ }
+
+ /* will hang if failed to find clock ratio */
+ while (1)
+ ;
+
+ return NULL;
+}
+
+struct mem_timings *clock_get_mem_timings(void)
+{
+ struct mem_timings *mem;
+ enum ddr_mode mem_type;
+ enum mem_manuf mem_manuf;
+ unsigned frequency_mhz, arm_freq;
+ int i;
+
+ clock_get_mem_selection(&mem_type, &frequency_mhz,
+ &arm_freq, &mem_manuf);
+ for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
+ i++, mem++) {
+ if (mem->mem_type == mem_type &&
+ mem->frequency_mhz == frequency_mhz &&
+ mem->mem_manuf == mem_manuf)
+ return mem;
+ }
+
+ /* will hang if failed to find memory timings */
+ while (1)
+ ;
+
+ return NULL;
+}
+
+static void exynos5250_system_clock_init(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ struct mem_timings *mem;
+ struct arm_clk_ratios *arm_clk_ratio;
+ u32 val, tmp;
+
+ mem = clock_get_mem_timings();
+ arm_clk_ratio = get_arm_ratios();
+
+ clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
+ do {
+ val = readl(&clk->mux_stat_cpu);
+ } while ((val | MUX_APLL_SEL_MASK) != val);
+
+ clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
+ do {
+ val = readl(&clk->mux_stat_core1);
+ } while ((val | MUX_MPLL_SEL_MASK) != val);
+
+ clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
+ clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
+ clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
+ clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
+ tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
+ | MUX_GPLL_SEL_MASK;
+ do {
+ val = readl(&clk->mux_stat_top2);
+ } while ((val | tmp) != val);
+
+ clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
+ do {
+ val = readl(&clk->mux_stat_cdrex);
+ } while ((val | MUX_BPLL_SEL_MASK) != val);
+
+ /* PLL locktime */
+ writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
+ writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
+ writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
+ writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
+ writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock);
+ writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
+ writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock);
+
+ writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
+
+ writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
+ do {
+ val = readl(&clk->mux_stat_cpu);
+ } while ((val | HPM_SEL_SCLK_MPLL) != val);
+
+ val = arm_clk_ratio->arm2_ratio << 28
+ | arm_clk_ratio->apll_ratio << 24
+ | arm_clk_ratio->pclk_dbg_ratio << 20
+ | arm_clk_ratio->atb_ratio << 16
+ | arm_clk_ratio->periph_ratio << 12
+ | arm_clk_ratio->acp_ratio << 8
+ | arm_clk_ratio->cpud_ratio << 4
+ | arm_clk_ratio->arm_ratio;
+ writel(val, &clk->div_cpu0);
+ do {
+ val = readl(&clk->div_stat_cpu0);
+ } while (0 != val);
+
+ writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
+ do {
+ val = readl(&clk->div_stat_cpu1);
+ } while (0 != val);
+
+ /* Set APLL */
+ writel(APLL_CON1_VAL, &clk->apll_con1);
+ val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
+ arm_clk_ratio->apll_sdiv);
+ writel(val, &clk->apll_con0);
+ while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
+ ;
+
+ /* Set MPLL */
+ writel(MPLL_CON1_VAL, &clk->mpll_con1);
+ val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
+ writel(val, &clk->mpll_con0);
+ while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
+ ;
+
+ /* Set BPLL */
+ writel(BPLL_CON1_VAL, &clk->bpll_con1);
+ val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
+ writel(val, &clk->bpll_con0);
+ while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
+ ;
+
+ /* Set CPLL */
+ writel(CPLL_CON1_VAL, &clk->cpll_con1);
+ val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
+ writel(val, &clk->cpll_con0);
+ while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
+ ;
+
+ /* Set GPLL */
+ writel(GPLL_CON1_VAL, &clk->gpll_con1);
+ val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
+ writel(val, &clk->gpll_con0);
+ while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
+ ;
+
+ /* Set EPLL */
+ writel(EPLL_CON2_VAL, &clk->epll_con2);
+ writel(EPLL_CON1_VAL, &clk->epll_con1);
+ val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
+ writel(val, &clk->epll_con0);
+ while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
+ ;
+
+ /* Set VPLL */
+ writel(VPLL_CON2_VAL, &clk->vpll_con2);
+ writel(VPLL_CON1_VAL, &clk->vpll_con1);
+ val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
+ writel(val, &clk->vpll_con0);
+ while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
+ ;
+
+ writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
+ writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
+ while (readl(&clk->div_stat_core0) != 0)
+ ;
+
+ writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
+ while (readl(&clk->div_stat_core1) != 0)
+ ;
+
+ writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
+ while (readl(&clk->div_stat_sysrgt) != 0)
+ ;
+
+ writel(CLK_DIV_ACP_VAL, &clk->div_acp);
+ while (readl(&clk->div_stat_acp) != 0)
+ ;
+
+ writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
+ while (readl(&clk->div_stat_syslft) != 0)
+ ;
+
+ writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+ writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+ writel(TOP2_VAL, &clk->src_top2);
+ writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
+
+ writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
+ while (readl(&clk->div_stat_top0))
+ ;
+
+ writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
+ while (readl(&clk->div_stat_top1))
+ ;
+
+ writel(CLK_SRC_LEX_VAL, &clk->src_lex);
+ while (1) {
+ val = readl(&clk->mux_stat_lex);
+ if (val == (val | 1))
+ break;
+ }
+
+ writel(CLK_DIV_LEX_VAL, &clk->div_lex);
+ while (readl(&clk->div_stat_lex))
+ ;
+
+ writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
+ while (readl(&clk->div_stat_r0x))
+ ;
+
+ writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
+ while (readl(&clk->div_stat_r0x))
+ ;
+
+ writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
+ while (readl(&clk->div_stat_r1x))
+ ;
+
+ writel(CLK_REG_DISABLE, &clk->src_cdrex);
+
+ writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
+ while (readl(&clk->div_stat_cdrex))
+ ;
+
+ val = readl(&clk->src_cpu);
+ val |= CLK_SRC_CPU_VAL;
+ writel(val, &clk->src_cpu);
+
+ val = readl(&clk->src_top2);
+ val |= CLK_SRC_TOP2_VAL;
+ writel(val, &clk->src_top2);
+
+ val = readl(&clk->src_core1);
+ val |= CLK_SRC_CORE1_VAL;
+ writel(val, &clk->src_core1);
+
+ writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
+ writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
+ while (readl(&clk->div_stat_fsys0))
+ ;
+
+ writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
+ writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
+ writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
+ writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
+ writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
+ writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
+ writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
+ writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
+
+ writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
+ writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
+
+ writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
+ writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
+ writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
+ writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
+
+ writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
+ writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
+ writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
+ writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
+ writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
+
+ /* FIMD1 SRC CLK SELECTION */
+ writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
+
+ val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
+ | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
+ | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
+ | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
+ writel(val, &clk->div_fsys2);
+}
+
+static void exynos5420_system_clock_init(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ struct mem_timings *mem;
+ struct arm_clk_ratios *arm_clk_ratio;
+ u32 val;
+
+ mem = clock_get_mem_timings();
+ arm_clk_ratio = get_arm_ratios();
+
+ /* PLL locktime */
+ writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
+ writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
+ writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
+ writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
+ writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock);
+ writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
+ writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock);
+ writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
+ writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
+ writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
+ writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
+
+ setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
+
+ writel(0, &clk->src_top6);
+
+ writel(0, &clk->src_cdrex);
+ writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
+ writel(HPM_RATIO, &clk->div_cpu1);
+ writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
+
+ /* switch A15 clock source to OSC clock before changing APLL */
+ clrbits_le32(&clk->src_cpu, APLL_FOUT);
+
+ /* Set APLL */
+ writel(APLL_CON1_VAL, &clk->apll_con1);
+ val = set_pll(arm_clk_ratio->apll_mdiv,
+ arm_clk_ratio->apll_pdiv,
+ arm_clk_ratio->apll_sdiv);
+ writel(val, &clk->apll_con0);
+ while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* now it is safe to switch to APLL */
+ setbits_le32(&clk->src_cpu, APLL_FOUT);
+
+ writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
+ writel(CLK_DIV_KFC_VAL, &clk->div_kfc0);
+
+ /* switch A7 clock source to OSC clock before changing KPLL */
+ clrbits_le32(&clk->src_kfc, KPLL_FOUT);
+
+ /* Set KPLL*/
+ writel(KPLL_CON1_VAL, &clk->kpll_con1);
+ val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv);
+ writel(val, &clk->kpll_con0);
+ while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* now it is safe to switch to KPLL */
+ setbits_le32(&clk->src_kfc, KPLL_FOUT);
+
+ /* Set MPLL */
+ writel(MPLL_CON1_VAL, &clk->mpll_con1);
+ val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
+ writel(val, &clk->mpll_con0);
+ while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* Set DPLL */
+ writel(DPLL_CON1_VAL, &clk->dpll_con1);
+ val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv);
+ writel(val, &clk->dpll_con0);
+ while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* Set EPLL */
+ writel(EPLL_CON2_VAL, &clk->epll_con2);
+ writel(EPLL_CON1_VAL, &clk->epll_con1);
+ val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
+ writel(val, &clk->epll_con0);
+ while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* Set CPLL */
+ writel(CPLL_CON1_VAL, &clk->cpll_con1);
+ val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
+ writel(val, &clk->cpll_con0);
+ while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* Set IPLL */
+ writel(IPLL_CON1_VAL, &clk->ipll_con1);
+ val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv);
+ writel(val, &clk->ipll_con0);
+ while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* Set VPLL */
+ writel(VPLL_CON1_VAL, &clk->vpll_con1);
+ val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
+ writel(val, &clk->vpll_con0);
+ while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* Set BPLL */
+ writel(BPLL_CON1_VAL, &clk->bpll_con1);
+ val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
+ writel(val, &clk->bpll_con0);
+ while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* Set SPLL */
+ writel(SPLL_CON1_VAL, &clk->spll_con1);
+ val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv);
+ writel(val, &clk->spll_con0);
+ while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* Set RPLL */
+ writel(RPLL_CON2_VAL, &clk->rpll_con2);
+ writel(RPLL_CON1_VAL, &clk->rpll_con1);
+ val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv);
+ writel(val, &clk->rpll_con0);
+ while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
+ writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
+
+ writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+ writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+ writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
+ writel(CLK_SRC_TOP7_VAL, &clk->src_top7);
+
+ writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
+ writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
+ writel(CLK_DIV_TOP2_VAL, &clk->div_top2);
+
+ writel(0, &clk->src_top10);
+ writel(0, &clk->src_top11);
+ writel(0, &clk->src_top12);
+
+ writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
+ writel(CLK_SRC_TOP4_VAL, &clk->src_top4);
+ writel(CLK_SRC_TOP5_VAL, &clk->src_top5);
+
+ /* DISP1 BLK CLK SELECTION */
+ writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10);
+ writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10);
+
+ /* AUDIO BLK */
+ writel(AUDIO0_SEL_EPLL, &clk->src_mau);
+ writel(DIV_MAU_VAL, &clk->div_mau);
+
+ /* FSYS */
+ writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
+ writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
+ writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
+ writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
+
+ writel(CLK_SRC_ISP_VAL, &clk->src_isp);
+ writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
+ writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
+
+ writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
+ writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
+
+ writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
+ writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
+ writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
+ writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
+ writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4);
+
+ writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1);
+
+ writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
+ writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
+ writel(CLK_DIV_G2D, &clk->div_g2d);
+
+ writel(CLK_SRC_TOP6_VAL, &clk->src_top6);
+ writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
+ writel(CLK_SRC_KFC_VAL, &clk->src_kfc);
+}
+
+void system_clock_init(void)
+{
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ exynos5420_system_clock_init();
+ else
+ exynos5250_system_clock_init();
+}
+
+void clock_init_dp_clock(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+
+ /* DP clock enable */
+ setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
+
+ /* We run DP at 267 Mhz */
+ setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
+}
+
+/*
+ * Set clock divisor value for booting from EMMC.
+ * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
+ */
+void emmc_boot_clk_div_set(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned int div_mmc;
+
+ div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK;
+ div_mmc |= FSYS1_MMC0_DIV_VAL;
+ writel(div_mmc, (unsigned int) &clk->div_fsys1);
+}
--- /dev/null
+/*
+ * Common APIs for EXYNOS based board
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/system.h>
+
+#define DMC_OFFSET 0x10000
+
+/*
+ * Memory initialization
+ *
+ * @param reset Reset PHY during initialization.
+ */
+void mem_ctrl_init(int reset);
+
+ /* System Clock initialization */
+void system_clock_init(void);
+
+/*
+ * Init subsystems according to the reset status
+ *
+ * @return 0 for a normal boot, non-zero for a resume
+ */
+int do_lowlevel_init(void);
+
+void sdelay(unsigned long);
+
+enum l2_cache_params {
+ CACHE_DATA_RAM_LATENCY_2_CYCLES = (2 << 0),
+ CACHE_DATA_RAM_LATENCY_3_CYCLES = (3 << 0),
+ CACHE_DISABLE_CLEAN_EVICT = (1 << 3),
+ CACHE_DATA_RAM_SETUP = (1 << 5),
+ CACHE_TAG_RAM_LATENCY_2_CYCLES = (2 << 6),
+ CACHE_TAG_RAM_LATENCY_3_CYCLES = (3 << 6),
+ CACHE_ENABLE_HAZARD_DETECT = (1 << 7),
+ CACHE_TAG_RAM_SETUP = (1 << 9),
+ CACHE_ECC_AND_PARITY = (1 << 21),
+ CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27)
+};
+
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+/*
+ * Configure L2CTLR to get timings that keep us from hanging/crashing.
+ *
+ * Must be inline here since low_power_start() is called without a
+ * stack (!).
+ */
+static inline void configure_l2_ctlr(void)
+{
+ uint32_t val;
+
+ mrc_l2_ctlr(val);
+
+ val |= CACHE_TAG_RAM_SETUP |
+ CACHE_DATA_RAM_SETUP |
+ CACHE_TAG_RAM_LATENCY_2_CYCLES |
+ CACHE_DATA_RAM_LATENCY_2_CYCLES;
+
+ if (proid_is_exynos5420() || proid_is_exynos5800()) {
+ val |= CACHE_ECC_AND_PARITY |
+ CACHE_TAG_RAM_LATENCY_3_CYCLES |
+ CACHE_DATA_RAM_LATENCY_3_CYCLES;
+ }
+
+ mcr_l2_ctlr(val);
+}
+
+/*
+ * Configure L2ACTLR.
+ *
+ * Must be inline here since low_power_start() is called without a
+ * stack (!).
+ */
+static inline void configure_l2_actlr(void)
+{
+ uint32_t val;
+
+ if (proid_is_exynos5420() || proid_is_exynos5800()) {
+ mrc_l2_aux_ctlr(val);
+ val |= CACHE_ENABLE_FORCE_L2_LOGIC |
+ CACHE_DISABLE_CLEAN_EVICT;
+ mcr_l2_aux_ctlr(val);
+ }
+}
+#endif
--- /dev/null
+#
+# Copyright (C) Albert ARIBAUD <albert.u.boot@aribaud.net>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+SPL_OBJCFLAGS += -j .machine_param
--- /dev/null
+/*
+ * Mem setup common file for different types of DDR present on Exynos boards.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/spl.h>
+
+#include "clock_init.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
+
+#define ZQ_INIT_TIMEOUT 10000
+
+int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16,
+ uint32_t *phy1_con16, uint32_t *phy0_con17,
+ uint32_t *phy1_con17)
+{
+ unsigned long val = 0;
+ int i;
+
+ /*
+ * ZQ Calibration:
+ * Select Driver Strength,
+ * long calibration for manual calibration
+ */
+ val = PHY_CON16_RESET_VAL;
+ val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT;
+ val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT;
+ val |= ZQ_CLK_DIV_EN;
+ writel(val, phy0_con16);
+ writel(val, phy1_con16);
+
+ /* Disable termination */
+ if (mem->zq_mode_noterm)
+ val |= PHY_CON16_ZQ_MODE_NOTERM_MASK;
+ writel(val, phy0_con16);
+ writel(val, phy1_con16);
+
+ /* ZQ_MANUAL_START: Enable */
+ val |= ZQ_MANUAL_STR;
+ writel(val, phy0_con16);
+ writel(val, phy1_con16);
+
+ /* ZQ_MANUAL_START: Disable */
+ val &= ~ZQ_MANUAL_STR;
+
+ /*
+ * Since we are manaully calibrating the ZQ values,
+ * we are looping for the ZQ_init to complete.
+ */
+ i = ZQ_INIT_TIMEOUT;
+ while ((readl(phy0_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
+ sdelay(100);
+ i--;
+ }
+ if (!i)
+ return -1;
+ writel(val, phy0_con16);
+
+ i = ZQ_INIT_TIMEOUT;
+ while ((readl(phy1_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
+ sdelay(100);
+ i--;
+ }
+ if (!i)
+ return -1;
+ writel(val, phy1_con16);
+
+ return 0;
+}
+
+void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode mode)
+{
+ unsigned long val;
+
+ if (mode == DDR_MODE_DDR3) {
+ val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE;
+ writel(val, phycontrol0);
+ }
+
+ /* Update DLL Information: Force DLL Resyncronization */
+ val = readl(phycontrol0);
+ val |= FP_RSYNC;
+ writel(val, phycontrol0);
+
+ /* Reset Force DLL Resyncronization */
+ val = readl(phycontrol0);
+ val &= ~FP_RSYNC;
+ writel(val, phycontrol0);
+}
+
+void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd)
+{
+ int channel, chip;
+
+ for (channel = 0; channel < mem->dmc_channels; channel++) {
+ unsigned long mask;
+
+ mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
+ for (chip = 0; chip < mem->chips_to_configure; chip++) {
+ int i;
+
+ mask |= chip << DIRECT_CMD_CHIP_SHIFT;
+
+ /* Sending NOP command */
+ writel(DIRECT_CMD_NOP | mask, directcmd);
+
+ /*
+ * TODO(alim.akhtar@samsung.com): Do we need these
+ * delays? This one and the next were not there for
+ * DDR3.
+ */
+ sdelay(0x10000);
+
+ /* Sending EMRS/MRS commands */
+ for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
+ writel(mem->direct_cmd_msr[i] | mask,
+ directcmd);
+ sdelay(0x10000);
+ }
+
+ if (mem->send_zq_init) {
+ /* Sending ZQINIT command */
+ writel(DIRECT_CMD_ZQINIT | mask,
+ directcmd);
+
+ sdelay(10000);
+ }
+ }
+ }
+}
+
+void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd)
+{
+ int channel, chip;
+
+ for (channel = 0; channel < mem->dmc_channels; channel++) {
+ unsigned long mask;
+
+ mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
+ for (chip = 0; chip < mem->chips_per_channel; chip++) {
+ mask |= chip << DIRECT_CMD_CHIP_SHIFT;
+
+ /* PALL (all banks precharge) CMD */
+ writel(DIRECT_CMD_PALL | mask, directcmd);
+ sdelay(0x10000);
+ }
+ }
+}
+
+void mem_ctrl_init(int reset)
+{
+ struct spl_machine_param *param = spl_get_machine_params();
+ struct mem_timings *mem;
+ int ret;
+
+ mem = clock_get_mem_timings();
+
+ /* If there are any other memory variant, add their init call below */
+ if (param->mem_type == DDR_MODE_DDR3) {
+ ret = ddr3_mem_ctrl_init(mem, reset);
+ if (ret) {
+ /* will hang if failed to init memory control */
+ while (1)
+ ;
+ }
+ } else {
+ /* will hang if unknow memory type */
+ while (1)
+ ;
+ }
+}
--- /dev/null
+/*
+ * DDR3 mem setup file for board based on EXYNOS5
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dmc.h>
+#include <asm/arch/power.h>
+#include "common_setup.h"
+#include "exynos5_setup.h"
+#include "clock_init.h"
+
+#define TIMEOUT_US 10000
+#define NUM_BYTE_LANES 4
+#define DEFAULT_DQS 8
+#define DEFAULT_DQS_X4 (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
+ || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)
+
+#ifdef CONFIG_EXYNOS5250
+static void reset_phy_ctrl(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+
+ writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
+ writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
+}
+
+int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
+{
+ unsigned int val;
+ struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
+ struct exynos5_dmc *dmc;
+ int i;
+
+ phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy();
+ phy1_ctrl = (struct exynos5_phy_control *)(samsung_get_base_dmc_phy()
+ + DMC_OFFSET);
+ dmc = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl();
+
+ if (reset)
+ reset_phy_ctrl();
+
+ /* Set Impedance Output Driver */
+ val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |
+ (mem->impedance << CA_CKE_DRVR_DS_OFFSET) |
+ (mem->impedance << CA_CS_DRVR_DS_OFFSET) |
+ (mem->impedance << CA_ADR_DRVR_DS_OFFSET);
+ writel(val, &phy0_ctrl->phy_con39);
+ writel(val, &phy1_ctrl->phy_con39);
+
+ /* Set Read Latency and Burst Length for PHY0 and PHY1 */
+ val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
+ (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
+ writel(val, &phy0_ctrl->phy_con42);
+ writel(val, &phy1_ctrl->phy_con42);
+
+ /* ZQ Calibration */
+ if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
+ &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
+ return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
+
+ /* DQ Signal */
+ writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14);
+ writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14);
+
+ writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
+ | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT),
+ &dmc->concontrol);
+
+ update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
+
+ /* DQS Signal */
+ writel(mem->phy0_dqs, &phy0_ctrl->phy_con4);
+ writel(mem->phy1_dqs, &phy1_ctrl->phy_con4);
+
+ writel(mem->phy0_dq, &phy0_ctrl->phy_con6);
+ writel(mem->phy1_dq, &phy1_ctrl->phy_con6);
+
+ writel(mem->phy0_tFS, &phy0_ctrl->phy_con10);
+ writel(mem->phy1_tFS, &phy1_ctrl->phy_con10);
+
+ val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) |
+ (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
+ (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
+ (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
+ writel(val, &phy0_ctrl->phy_con12);
+ writel(val, &phy1_ctrl->phy_con12);
+
+ /* Start DLL locking */
+ writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
+ &phy0_ctrl->phy_con12);
+ writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
+ &phy1_ctrl->phy_con12);
+
+ update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
+
+ writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
+ &dmc->concontrol);
+
+ /* Memory Channel Inteleaving Size */
+ writel(mem->iv_size, &dmc->ivcontrol);
+
+ writel(mem->memconfig, &dmc->memconfig0);
+ writel(mem->memconfig, &dmc->memconfig1);
+ writel(mem->membaseconfig0, &dmc->membaseconfig0);
+ writel(mem->membaseconfig1, &dmc->membaseconfig1);
+
+ /* Precharge Configuration */
+ writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
+ &dmc->prechconfig);
+
+ /* Power Down mode Configuration */
+ writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
+ mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT,
+ &dmc->pwrdnconfig);
+
+ /* TimingRow, TimingData, TimingPower and Timingaref
+ * values as per Memory AC parameters
+ */
+ writel(mem->timing_ref, &dmc->timingref);
+ writel(mem->timing_row, &dmc->timingrow);
+ writel(mem->timing_data, &dmc->timingdata);
+ writel(mem->timing_power, &dmc->timingpower);
+
+ /* Send PALL command */
+ dmc_config_prech(mem, &dmc->directcmd);
+
+ /* Send NOP, MRS and ZQINIT commands */
+ dmc_config_mrs(mem, &dmc->directcmd);
+
+ if (mem->gate_leveling_enable) {
+ val = PHY_CON0_RESET_VAL;
+ val |= P0_CMD_EN;
+ writel(val, &phy0_ctrl->phy_con0);
+ writel(val, &phy1_ctrl->phy_con0);
+
+ val = PHY_CON2_RESET_VAL;
+ val |= INIT_DESKEW_EN;
+ writel(val, &phy0_ctrl->phy_con2);
+ writel(val, &phy1_ctrl->phy_con2);
+
+ val = PHY_CON0_RESET_VAL;
+ val |= P0_CMD_EN;
+ val |= BYTE_RDLVL_EN;
+ writel(val, &phy0_ctrl->phy_con0);
+ writel(val, &phy1_ctrl->phy_con0);
+
+ val = (mem->ctrl_start_point <<
+ PHY_CON12_CTRL_START_POINT_SHIFT) |
+ (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
+ (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
+ (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
+ (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
+ writel(val, &phy0_ctrl->phy_con12);
+ writel(val, &phy1_ctrl->phy_con12);
+
+ val = PHY_CON2_RESET_VAL;
+ val |= INIT_DESKEW_EN;
+ val |= RDLVL_GATE_EN;
+ writel(val, &phy0_ctrl->phy_con2);
+ writel(val, &phy1_ctrl->phy_con2);
+
+ val = PHY_CON0_RESET_VAL;
+ val |= P0_CMD_EN;
+ val |= BYTE_RDLVL_EN;
+ val |= CTRL_SHGATE;
+ writel(val, &phy0_ctrl->phy_con0);
+ writel(val, &phy1_ctrl->phy_con0);
+
+ val = PHY_CON1_RESET_VAL;
+ val &= ~(CTRL_GATEDURADJ_MASK);
+ writel(val, &phy0_ctrl->phy_con1);
+ writel(val, &phy1_ctrl->phy_con1);
+
+ writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
+ i = TIMEOUT_US;
+ while ((readl(&dmc->phystatus) &
+ (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
+ (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
+ /*
+ * TODO(waihong): Comment on how long this take to
+ * timeout
+ */
+ sdelay(100);
+ i--;
+ }
+ if (!i)
+ return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
+ writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config);
+
+ writel(0, &phy0_ctrl->phy_con14);
+ writel(0, &phy1_ctrl->phy_con14);
+
+ val = (mem->ctrl_start_point <<
+ PHY_CON12_CTRL_START_POINT_SHIFT) |
+ (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
+ (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
+ (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
+ (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
+ (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
+ writel(val, &phy0_ctrl->phy_con12);
+ writel(val, &phy1_ctrl->phy_con12);
+
+ update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
+ }
+
+ /* Send PALL command */
+ dmc_config_prech(mem, &dmc->directcmd);
+
+ writel(mem->memcontrol, &dmc->memcontrol);
+
+ /* Set DMC Concontrol and enable auto-refresh counter */
+ writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
+ | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_EXYNOS5420
+/**
+ * RAM address to use in the test.
+ *
+ * We'll use 4 words at this address and 4 at this address + 0x80 (Ares
+ * interleaves channels every 128 bytes). This will allow us to evaluate all of
+ * the chips in a 1 chip per channel (2GB) system and half the chips in a 2
+ * chip per channel (4GB) system. We can't test the 2nd chip since we need to
+ * do tests before the 2nd chip is enabled. Looking at the 2nd chip isn't
+ * critical because the 1st and 2nd chip have very similar timings (they'd
+ * better have similar timings, since there's only a single adjustment that is
+ * shared by both chips).
+ */
+const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE;
+
+/* Test pattern with which RAM will be tested */
+static const unsigned int test_pattern[] = {
+ 0x5a5a5a5a,
+ 0xa5a5a5a5,
+ 0xf0f0f0f0,
+ 0x0f0f0f0f,
+};
+
+/**
+ * This function is a test vector for sw read leveling,
+ * it compares the read data with the written data.
+ *
+ * @param ch DMC channel number
+ * @param byte_lane which DQS byte offset,
+ * possible values are 0,1,2,3
+ * @return TRUE if memory was good, FALSE if not.
+ */
+static bool dmc_valid_window_test_vector(int ch, int byte_lane)
+{
+ unsigned int read_data;
+ unsigned int mask;
+ int i;
+
+ mask = 0xFF << (8 * byte_lane);
+
+ for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
+ read_data = readl(test_addr + i * 4 + ch * 0x80);
+ if ((read_data & mask) != (test_pattern[i] & mask))
+ return false;
+ }
+
+ return true;
+}
+
+/**
+ * This function returns current read offset value.
+ *
+ * @param phy_ctrl pointer to the current phy controller
+ */
+static unsigned int dmc_get_read_offset_value(struct exynos5420_phy_control
+ *phy_ctrl)
+{
+ return readl(&phy_ctrl->phy_con4);
+}
+
+/**
+ * This function performs resync, so that slave DLL is updated.
+ *
+ * @param phy_ctrl pointer to the current phy controller
+ */
+static void ddr_phy_set_do_resync(struct exynos5420_phy_control *phy_ctrl)
+{
+ setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3);
+ clrbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3);
+}
+
+/**
+ * This function sets read offset value register with 'offset'.
+ *
+ * ...we also call call ddr_phy_set_do_resync().
+ *
+ * @param phy_ctrl pointer to the current phy controller
+ * @param offset offset to read DQS
+ */
+static void dmc_set_read_offset_value(struct exynos5420_phy_control *phy_ctrl,
+ unsigned int offset)
+{
+ writel(offset, &phy_ctrl->phy_con4);
+ ddr_phy_set_do_resync(phy_ctrl);
+}
+
+/**
+ * Convert a 2s complement byte to a byte with a sign bit.
+ *
+ * NOTE: you shouldn't use normal math on the number returned by this function.
+ * As an example, -10 = 0xf6. After this function -10 = 0x8a. If you wanted
+ * to do math and get the average of 10 and -10 (should be 0):
+ * 0x8a + 0xa = 0x94 (-108)
+ * 0x94 / 2 = 0xca (-54)
+ * ...and 0xca = sign bit plus 0x4a, or -74
+ *
+ * Also note that you lose the ability to represent -128 since there are two
+ * representations of 0.
+ *
+ * @param b The byte to convert in two's complement.
+ * @return The 7-bit value + sign bit.
+ */
+
+unsigned char make_signed_byte(signed char b)
+{
+ if (b < 0)
+ return 0x80 | -b;
+ else
+ return b;
+}
+
+/**
+ * Test various shifts starting at 'start' and going to 'end'.
+ *
+ * For each byte lane, we'll walk through shift starting at 'start' and going
+ * to 'end' (inclusive). When we are finally able to read the test pattern
+ * we'll store the value in the results array.
+ *
+ * @param phy_ctrl pointer to the current phy controller
+ * @param ch channel number
+ * @param start the start shift. -127 to 127
+ * @param end the end shift. -127 to 127
+ * @param results we'll store results for each byte lane.
+ */
+
+void test_shifts(struct exynos5420_phy_control *phy_ctrl, int ch,
+ int start, int end, int results[NUM_BYTE_LANES])
+{
+ int incr = (start < end) ? 1 : -1;
+ int byte_lane;
+
+ for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) {
+ int shift;
+
+ dmc_set_read_offset_value(phy_ctrl, DEFAULT_DQS_X4);
+ results[byte_lane] = DEFAULT_DQS;
+
+ for (shift = start; shift != (end + incr); shift += incr) {
+ unsigned int byte_offsetr;
+ unsigned int offsetr;
+
+ byte_offsetr = make_signed_byte(shift);
+
+ offsetr = dmc_get_read_offset_value(phy_ctrl);
+ offsetr &= ~(0xFF << (8 * byte_lane));
+ offsetr |= (byte_offsetr << (8 * byte_lane));
+ dmc_set_read_offset_value(phy_ctrl, offsetr);
+
+ if (dmc_valid_window_test_vector(ch, byte_lane)) {
+ results[byte_lane] = shift;
+ break;
+ }
+ }
+ }
+}
+
+/**
+ * This function performs SW read leveling to compensate DQ-DQS skew at
+ * receiver it first finds the optimal read offset value on each DQS
+ * then applies the value to PHY.
+ *
+ * Read offset value has its min margin and max margin. If read offset
+ * value exceeds its min or max margin, read data will have corruption.
+ * To avoid this we are doing sw read leveling.
+ *
+ * SW read leveling is:
+ * 1> Finding offset value's left_limit and right_limit
+ * 2> and calculate its center value
+ * 3> finally programs that center value to PHY
+ * 4> then PHY gets its optimal offset value.
+ *
+ * @param phy_ctrl pointer to the current phy controller
+ * @param ch channel number
+ * @param coarse_lock_val The coarse lock value read from PHY_CON13.
+ * (0 - 0x7f)
+ */
+static void software_find_read_offset(struct exynos5420_phy_control *phy_ctrl,
+ int ch, unsigned int coarse_lock_val)
+{
+ unsigned int offsetr_cent;
+ int byte_lane;
+ int left_limit;
+ int right_limit;
+ int left[NUM_BYTE_LANES];
+ int right[NUM_BYTE_LANES];
+ int i;
+
+ /* Fill the memory with test patterns */
+ for (i = 0; i < ARRAY_SIZE(test_pattern); i++)
+ writel(test_pattern[i], test_addr + i * 4 + ch * 0x80);
+
+ /* Figure out the limits we'll test with; keep -127 < limit < 127 */
+ left_limit = DEFAULT_DQS - coarse_lock_val;
+ right_limit = DEFAULT_DQS + coarse_lock_val;
+ if (right_limit > 127)
+ right_limit = 127;
+
+ /* Fill in the location where reads were OK from left and right */
+ test_shifts(phy_ctrl, ch, left_limit, right_limit, left);
+ test_shifts(phy_ctrl, ch, right_limit, left_limit, right);
+
+ /* Make a final value by taking the center between the left and right */
+ offsetr_cent = 0;
+ for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) {
+ int temp_center;
+ unsigned int vmwc;
+
+ temp_center = (left[byte_lane] + right[byte_lane]) / 2;
+ vmwc = make_signed_byte(temp_center);
+ offsetr_cent |= vmwc << (8 * byte_lane);
+ }
+ dmc_set_read_offset_value(phy_ctrl, offsetr_cent);
+}
+
+int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ struct exynos5420_power *power =
+ (struct exynos5420_power *)samsung_get_base_power();
+ struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl;
+ struct exynos5420_dmc *drex0, *drex1;
+ struct exynos5420_tzasc *tzasc0, *tzasc1;
+ struct exynos5_power *pmu;
+ uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
+ uint32_t lock0_info, lock1_info;
+ int chip;
+ int i;
+
+ phy0_ctrl = (struct exynos5420_phy_control *)samsung_get_base_dmc_phy();
+ phy1_ctrl = (struct exynos5420_phy_control *)(samsung_get_base_dmc_phy()
+ + DMC_OFFSET);
+ drex0 = (struct exynos5420_dmc *)samsung_get_base_dmc_ctrl();
+ drex1 = (struct exynos5420_dmc *)(samsung_get_base_dmc_ctrl()
+ + DMC_OFFSET);
+ tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc();
+ tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc()
+ + DMC_OFFSET);
+ pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
+
+ if (CONFIG_NR_DRAM_BANKS > 4) {
+ /* Need both controllers. */
+ mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2;
+ mem->chips_per_channel = 2;
+ mem->chips_to_configure = 2;
+ } else {
+ /* 2GB requires a single controller */
+ mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1;
+ }
+
+ /* Enable PAUSE for DREX */
+ setbits_le32(&clk->pause, ENABLE_BIT);
+
+ /* Enable BYPASS mode */
+ setbits_le32(&clk->bpll_con1, BYPASS_EN);
+
+ writel(MUX_BPLL_SEL_FOUTBPLL, &clk->src_cdrex);
+ do {
+ val = readl(&clk->mux_stat_cdrex);
+ val &= BPLL_SEL_MASK;
+ } while (val != FOUTBPLL);
+
+ clrbits_le32(&clk->bpll_con1, BYPASS_EN);
+
+ /* Specify the DDR memory type as DDR3 */
+ val = readl(&phy0_ctrl->phy_con0);
+ val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
+ val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
+ writel(val, &phy0_ctrl->phy_con0);
+
+ val = readl(&phy1_ctrl->phy_con0);
+ val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
+ val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
+ writel(val, &phy1_ctrl->phy_con0);
+
+ /* Set Read Latency and Burst Length for PHY0 and PHY1 */
+ val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
+ (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
+ writel(val, &phy0_ctrl->phy_con42);
+ writel(val, &phy1_ctrl->phy_con42);
+
+ val = readl(&phy0_ctrl->phy_con26);
+ val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
+ val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
+ writel(val, &phy0_ctrl->phy_con26);
+
+ val = readl(&phy1_ctrl->phy_con26);
+ val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
+ val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
+ writel(val, &phy1_ctrl->phy_con26);
+
+ /*
+ * Set Driver strength for CK, CKE, CS & CA to 0x7
+ * Set Driver strength for Data Slice 0~3 to 0x7
+ */
+ val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) |
+ (0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET);
+ val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) |
+ (0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET);
+ writel(val, &phy0_ctrl->phy_con39);
+ writel(val, &phy1_ctrl->phy_con39);
+
+ /* ZQ Calibration */
+ if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
+ &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
+ return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
+
+ clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN);
+ clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN);
+
+ /* DQ Signal */
+ val = readl(&phy0_ctrl->phy_con14);
+ val |= mem->phy0_pulld_dqs;
+ writel(val, &phy0_ctrl->phy_con14);
+ val = readl(&phy1_ctrl->phy_con14);
+ val |= mem->phy1_pulld_dqs;
+ writel(val, &phy1_ctrl->phy_con14);
+
+ val = MEM_TERM_EN | PHY_TERM_EN;
+ writel(val, &drex0->phycontrol0);
+ writel(val, &drex1->phycontrol0);
+
+ writel(mem->concontrol |
+ (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
+ (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
+ &drex0->concontrol);
+ writel(mem->concontrol |
+ (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
+ (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
+ &drex1->concontrol);
+
+ do {
+ val = readl(&drex0->phystatus);
+ } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
+ do {
+ val = readl(&drex1->phystatus);
+ } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
+
+ clrbits_le32(&drex0->concontrol, DFI_INIT_START);
+ clrbits_le32(&drex1->concontrol, DFI_INIT_START);
+
+ update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);
+ update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);
+
+ /*
+ * Set Base Address:
+ * 0x2000_0000 ~ 0x5FFF_FFFF
+ * 0x6000_0000 ~ 0x9FFF_FFFF
+ */
+ /* MEMBASECONFIG0 */
+ val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_0) |
+ DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
+ writel(val, &tzasc0->membaseconfig0);
+ writel(val, &tzasc1->membaseconfig0);
+
+ /* MEMBASECONFIG1 */
+ val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_1) |
+ DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
+ writel(val, &tzasc0->membaseconfig1);
+ writel(val, &tzasc1->membaseconfig1);
+
+ /*
+ * Memory Channel Inteleaving Size
+ * Ares Channel interleaving = 128 bytes
+ */
+ /* MEMCONFIG0/1 */
+ writel(mem->memconfig, &tzasc0->memconfig0);
+ writel(mem->memconfig, &tzasc1->memconfig0);
+ writel(mem->memconfig, &tzasc0->memconfig1);
+ writel(mem->memconfig, &tzasc1->memconfig1);
+
+ /* Precharge Configuration */
+ writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
+ &drex0->prechconfig0);
+ writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
+ &drex1->prechconfig0);
+
+ /*
+ * TimingRow, TimingData, TimingPower and Timingaref
+ * values as per Memory AC parameters
+ */
+ writel(mem->timing_ref, &drex0->timingref);
+ writel(mem->timing_ref, &drex1->timingref);
+ writel(mem->timing_row, &drex0->timingrow0);
+ writel(mem->timing_row, &drex1->timingrow0);
+ writel(mem->timing_data, &drex0->timingdata0);
+ writel(mem->timing_data, &drex1->timingdata0);
+ writel(mem->timing_power, &drex0->timingpower0);
+ writel(mem->timing_power, &drex1->timingpower0);
+
+ if (reset) {
+ /*
+ * Send NOP, MRS and ZQINIT commands
+ * Sending MRS command will reset the DRAM. We should not be
+ * reseting the DRAM after resume, this will lead to memory
+ * corruption as DRAM content is lost after DRAM reset
+ */
+ dmc_config_mrs(mem, &drex0->directcmd);
+ dmc_config_mrs(mem, &drex1->directcmd);
+ }
+
+ /*
+ * Get PHY_CON13 from both phys. Gate CLKM around reading since
+ * PHY_CON13 is glitchy when CLKM is running. We're paranoid and
+ * wait until we get a "fine lock", though a coarse lock is probably
+ * OK (we only use the coarse numbers below). We try to gate the
+ * clock for as short a time as possible in case SDRAM is somehow
+ * sensitive. sdelay(10) in the loop is arbitrary to make sure
+ * there is some time for PHY_CON13 to get updated. In practice
+ * no delay appears to be needed.
+ */
+ val = readl(&clk->gate_bus_cdrex);
+ while (true) {
+ writel(val & ~0x1, &clk->gate_bus_cdrex);
+ lock0_info = readl(&phy0_ctrl->phy_con13);
+ writel(val, &clk->gate_bus_cdrex);
+
+ if ((lock0_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED)
+ break;
+
+ sdelay(10);
+ }
+ while (true) {
+ writel(val & ~0x2, &clk->gate_bus_cdrex);
+ lock1_info = readl(&phy1_ctrl->phy_con13);
+ writel(val, &clk->gate_bus_cdrex);
+
+ if ((lock1_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED)
+ break;
+
+ sdelay(10);
+ }
+
+ if (!reset) {
+ /*
+ * During Suspend-Resume & S/W-Reset, as soon as PMU releases
+ * pad retention, CKE goes high. This causes memory contents
+ * not to be retained during DRAM initialization. Therfore,
+ * there is a new control register(0x100431e8[28]) which lets us
+ * release pad retention and retain the memory content until the
+ * initialization is complete.
+ */
+ writel(PAD_RETENTION_DRAM_COREBLK_VAL,
+ &power->pad_retention_dram_coreblk_option);
+ do {
+ val = readl(&power->pad_retention_dram_status);
+ } while (val != 0x1);
+
+ /*
+ * CKE PAD retention disables DRAM self-refresh mode.
+ * Send auto refresh command for DRAM refresh.
+ */
+ for (i = 0; i < 128; i++) {
+ for (chip = 0; chip < mem->chips_to_configure; chip++) {
+ writel(DIRECT_CMD_REFA |
+ (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex0->directcmd);
+ writel(DIRECT_CMD_REFA |
+ (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex1->directcmd);
+ }
+ }
+ }
+
+ if (mem->gate_leveling_enable) {
+ writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0);
+ writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0);
+
+ setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN);
+ setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN);
+
+ val = PHY_CON2_RESET_VAL;
+ val |= INIT_DESKEW_EN;
+ writel(val, &phy0_ctrl->phy_con2);
+ writel(val, &phy1_ctrl->phy_con2);
+
+ val = readl(&phy0_ctrl->phy_con1);
+ val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
+ writel(val, &phy0_ctrl->phy_con1);
+
+ val = readl(&phy1_ctrl->phy_con1);
+ val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
+ writel(val, &phy1_ctrl->phy_con1);
+
+ n_lock_w_phy0 = (lock0_info & CTRL_LOCK_COARSE_MASK) >> 2;
+ n_lock_r = readl(&phy0_ctrl->phy_con12);
+ n_lock_r &= ~CTRL_DLL_ON;
+ n_lock_r |= n_lock_w_phy0;
+ writel(n_lock_r, &phy0_ctrl->phy_con12);
+
+ n_lock_w_phy1 = (lock1_info & CTRL_LOCK_COARSE_MASK) >> 2;
+ n_lock_r = readl(&phy1_ctrl->phy_con12);
+ n_lock_r &= ~CTRL_DLL_ON;
+ n_lock_r |= n_lock_w_phy1;
+ writel(n_lock_r, &phy1_ctrl->phy_con12);
+
+ val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
+ for (chip = 0; chip < mem->chips_to_configure; chip++) {
+ writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex0->directcmd);
+ writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex1->directcmd);
+ }
+
+ setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
+ setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
+
+ setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE);
+ setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE);
+
+ val = readl(&phy0_ctrl->phy_con1);
+ val &= ~(CTRL_GATEDURADJ_MASK);
+ writel(val, &phy0_ctrl->phy_con1);
+
+ val = readl(&phy1_ctrl->phy_con1);
+ val &= ~(CTRL_GATEDURADJ_MASK);
+ writel(val, &phy1_ctrl->phy_con1);
+
+ writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config);
+ i = TIMEOUT_US;
+ while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=
+ RDLVL_COMPLETE_CHO) && (i > 0)) {
+ /*
+ * TODO(waihong): Comment on how long this take to
+ * timeout
+ */
+ sdelay(100);
+ i--;
+ }
+ if (!i)
+ return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
+ writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config);
+
+ writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config);
+ i = TIMEOUT_US;
+ while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=
+ RDLVL_COMPLETE_CHO) && (i > 0)) {
+ /*
+ * TODO(waihong): Comment on how long this take to
+ * timeout
+ */
+ sdelay(100);
+ i--;
+ }
+ if (!i)
+ return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
+ writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config);
+
+ writel(0, &phy0_ctrl->phy_con14);
+ writel(0, &phy1_ctrl->phy_con14);
+
+ val = (0x3 << DIRECT_CMD_BANK_SHIFT);
+ for (chip = 0; chip < mem->chips_to_configure; chip++) {
+ writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex0->directcmd);
+ writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex1->directcmd);
+ }
+
+ /* Common Settings for Leveling */
+ val = PHY_CON12_RESET_VAL;
+ writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12);
+ writel((val + n_lock_w_phy1), &phy1_ctrl->phy_con12);
+
+ setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN);
+ setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN);
+ }
+
+ /*
+ * Do software read leveling
+ *
+ * Do this before we turn on auto refresh since the auto refresh can
+ * be in conflict with the resync operation that's part of setting
+ * read leveling.
+ */
+ if (!reset) {
+ /* restore calibrated value after resume */
+ dmc_set_read_offset_value(phy0_ctrl, readl(&pmu->pmu_spare1));
+ dmc_set_read_offset_value(phy1_ctrl, readl(&pmu->pmu_spare2));
+ } else {
+ software_find_read_offset(phy0_ctrl, 0,
+ CTRL_LOCK_COARSE(lock0_info));
+ software_find_read_offset(phy1_ctrl, 1,
+ CTRL_LOCK_COARSE(lock1_info));
+ /* save calibrated value to restore after resume */
+ writel(dmc_get_read_offset_value(phy0_ctrl), &pmu->pmu_spare1);
+ writel(dmc_get_read_offset_value(phy1_ctrl), &pmu->pmu_spare2);
+ }
+
+ /* Send PALL command */
+ dmc_config_prech(mem, &drex0->directcmd);
+ dmc_config_prech(mem, &drex1->directcmd);
+
+ writel(mem->memcontrol, &drex0->memcontrol);
+ writel(mem->memcontrol, &drex1->memcontrol);
+
+ /*
+ * Set DMC Concontrol: Enable auto-refresh counter, provide
+ * read data fetch cycles and enable DREX auto set powerdown
+ * for input buffer of I/O in none read memory state.
+ */
+ writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
+ (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
+ DMC_CONCONTROL_IO_PD_CON(0x2),
+ &drex0->concontrol);
+ writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
+ (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
+ DMC_CONCONTROL_IO_PD_CON(0x2),
+ &drex1->concontrol);
+
+ /*
+ * Enable Clock Gating Control for DMC
+ * this saves around 25 mw dmc power as compared to the power
+ * consumption without these bits enabled
+ */
+ setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
+ setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
+
+ /*
+ * As per Exynos5800 UM ver 0.00 section 17.13.2.1
+ * CONCONTROL register bit 3 [update_mode], Exynos5800 does not
+ * support the PHY initiated update. And it is recommended to set
+ * this field to 1'b1 during initialization
+ *
+ * When we apply PHY-initiated mode, DLL lock value is determined
+ * once at DMC init time and not updated later when we change the MIF
+ * voltage based on ASV group in kernel. Applying MC-initiated mode
+ * makes sure that DLL tracing is ON so that silicon is able to
+ * compensate the voltage variation.
+ */
+ val = readl(&drex0->concontrol);
+ val |= CONCONTROL_UPDATE_MODE;
+ writel(val , &drex0->concontrol);
+ val = readl(&drex1->concontrol);
+ val |= CONCONTROL_UPDATE_MODE;
+ writel(val , &drex1->concontrol);
+
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * Memory setup for board based on EXYNOS4210
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/dmc.h>
+#include "common_setup.h"
+#include "exynos4_setup.h"
+
+struct mem_timings mem = {
+ .direct_cmd_msr = {
+ DIRECT_CMD1, DIRECT_CMD2, DIRECT_CMD3, DIRECT_CMD4
+ },
+ .timingref = TIMINGREF_VAL,
+ .timingrow = TIMINGROW_VAL,
+ .timingdata = TIMINGDATA_VAL,
+ .timingpower = TIMINGPOWER_VAL,
+ .zqcontrol = ZQ_CONTROL_VAL,
+ .control0 = CONTROL0_VAL,
+ .control1 = CONTROL1_VAL,
+ .control2 = CONTROL2_VAL,
+ .concontrol = CONCONTROL_VAL,
+ .prechconfig = PRECHCONFIG,
+ .memcontrol = MEMCONTROL_VAL,
+ .memconfig0 = MEMCONFIG0_VAL,
+ .memconfig1 = MEMCONFIG1_VAL,
+ .dll_resync = FORCE_DLL_RESYNC,
+ .dll_on = DLL_CONTROL_ON,
+};
+static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc)
+{
+ if (ctrl_no) {
+ writel((mem.control1 | (1 << mem.dll_resync)),
+ &dmc->phycontrol1);
+ writel((mem.control1 | (0 << mem.dll_resync)),
+ &dmc->phycontrol1);
+ } else {
+ writel((mem.control0 | (0 << mem.dll_on)),
+ &dmc->phycontrol0);
+ writel((mem.control0 | (1 << mem.dll_on)),
+ &dmc->phycontrol0);
+ }
+}
+
+static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip)
+{
+ int i;
+ unsigned long mask = 0;
+
+ if (chip)
+ mask = DIRECT_CMD_CHIP1_SHIFT;
+
+ for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
+ writel(mem.direct_cmd_msr[i] | mask,
+ &dmc->directcmd);
+ }
+}
+
+static void dmc_init(struct exynos4_dmc *dmc)
+{
+ /*
+ * DLL Parameter Setting:
+ * Termination: Enable R/W
+ * Phase Delay for DQS Cleaning: 180' Shift
+ */
+ writel(mem.control1, &dmc->phycontrol1);
+
+ /*
+ * ZQ Calibration
+ * Termination: Disable
+ * Auto Calibration Start: Enable
+ */
+ writel(mem.zqcontrol, &dmc->phyzqcontrol);
+ sdelay(0x100000);
+
+ /*
+ * Update DLL Information:
+ * Force DLL Resyncronization
+ */
+ phy_control_reset(1, dmc);
+ phy_control_reset(0, dmc);
+
+ /* Set DLL Parameters */
+ writel(mem.control1, &dmc->phycontrol1);
+
+ /* DLL Start */
+ writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc->phycontrol0);
+
+ writel(mem.control2, &dmc->phycontrol2);
+
+ /* Set Clock Ratio of Bus clock to Memory Clock */
+ writel(mem.concontrol, &dmc->concontrol);
+
+ /*
+ * Memor Burst length: 8
+ * Number of chips: 2
+ * Memory Bus width: 32 bit
+ * Memory Type: DDR3
+ * Additional Latancy for PLL: 1 Cycle
+ */
+ writel(mem.memcontrol, &dmc->memcontrol);
+
+ writel(mem.memconfig0, &dmc->memconfig0);
+ writel(mem.memconfig1, &dmc->memconfig1);
+
+ /* Config Precharge Policy */
+ writel(mem.prechconfig, &dmc->prechconfig);
+ /*
+ * TimingAref, TimingRow, TimingData, TimingPower Setting:
+ * Values as per Memory AC Parameters
+ */
+ writel(mem.timingref, &dmc->timingref);
+ writel(mem.timingrow, &dmc->timingrow);
+ writel(mem.timingdata, &dmc->timingdata);
+ writel(mem.timingpower, &dmc->timingpower);
+
+ /* Chip0: NOP Command: Assert and Hold CKE to high level */
+ writel(DIRECT_CMD_NOP, &dmc->directcmd);
+ sdelay(0x100000);
+
+ /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+ dmc_config_mrs(dmc, 0);
+ sdelay(0x100000);
+
+ /* Chip0: ZQINIT */
+ writel(DIRECT_CMD_ZQ, &dmc->directcmd);
+ sdelay(0x100000);
+
+ writel((DIRECT_CMD_NOP | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd);
+ sdelay(0x100000);
+
+ /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+ dmc_config_mrs(dmc, 1);
+ sdelay(0x100000);
+
+ /* Chip1: ZQINIT */
+ writel((DIRECT_CMD_ZQ | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd);
+ sdelay(0x100000);
+
+ phy_control_reset(1, dmc);
+ sdelay(0x100000);
+
+ /* turn on DREX0, DREX1 */
+ writel((mem.concontrol | AREF_EN), &dmc->concontrol);
+}
+
+void mem_ctrl_init(int reset)
+{
+ struct exynos4_dmc *dmc;
+
+ /*
+ * Async bridge configuration at CPU_core:
+ * 1: half_sync
+ * 0: full_sync
+ */
+ writel(1, ASYNC_CONFIG);
+#ifdef CONFIG_ORIGEN
+ /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
+ writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
+ APB_SFR_INTERLEAVE_CONF_OFFSET);
+ /* Update MIU Configuration */
+ writel(APB_SFR_ARBRITATION_CONF_VAL, EXYNOS4_MIU_BASE +
+ APB_SFR_ARBRITATION_CONF_OFFSET);
+#else
+ writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
+ APB_SFR_INTERLEAVE_CONF_OFFSET);
+ writel(INTERLEAVE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
+ ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET);
+ writel(INTERLEAVE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
+ ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET);
+ writel(INTERLEAVE_ADDR_MAP_EN, EXYNOS4_MIU_BASE +
+ ABP_SFR_SLV_ADDRMAP_CONF_OFFSET);
+#ifdef CONFIG_MIU_LINEAR
+ writel(SLAVE0_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
+ ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET);
+ writel(SLAVE0_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
+ ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET);
+ writel(SLAVE1_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
+ ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET);
+ writel(SLAVE1_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
+ ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET);
+ writel(APB_SFR_SLV_ADDR_MAP_CONF_VAL, EXYNOS4_MIU_BASE +
+ ABP_SFR_SLV_ADDRMAP_CONF_OFFSET);
+#endif
+#endif
+ /* DREX0 */
+ dmc = (struct exynos4_dmc *)samsung_get_base_dmc_ctrl();
+ dmc_init(dmc);
+ dmc = (struct exynos4_dmc *)(samsung_get_base_dmc_ctrl()
+ + DMC_OFFSET);
+ dmc_init(dmc);
+}
--- /dev/null
+/*
+ * Machine Specific Values for EXYNOS4012 based board
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ORIGEN_SETUP_H
+#define _ORIGEN_SETUP_H
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+
+#ifdef CONFIG_CLK_800_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_200_200
+#define DRAM_CLK_200
+#endif
+#ifdef CONFIG_CLK_1000_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_400_200
+#define DRAM_CLK_400
+#endif
+
+/* Bus Configuration Register Address */
+#define ASYNC_CONFIG 0x10010350
+
+/* CLK_SRC_CPU */
+#define MUX_HPM_SEL_MOUTAPLL 0x0
+#define MUX_HPM_SEL_SCLKMPLL 0x1
+#define MUX_CORE_SEL_MOUTAPLL 0x0
+#define MUX_CORE_SEL_SCLKMPLL 0x1
+#define MUX_MPLL_SEL_FILPLL 0x0
+#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
+#define MUX_APLL_SEL_FILPLL 0x0
+#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
+#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \
+ | (MUX_CORE_SEL_MOUTAPLL << 16) \
+ | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
+ | (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
+
+/* CLK_DIV_CPU0 */
+#define APLL_RATIO 0x0
+#define PCLK_DBG_RATIO 0x1
+#define ATB_RATIO 0x3
+#define PERIPH_RATIO 0x3
+#define COREM1_RATIO 0x7
+#define COREM0_RATIO 0x3
+#define CORE_RATIO 0x0
+#define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \
+ | (PCLK_DBG_RATIO << 20) \
+ | (ATB_RATIO << 16) \
+ | (PERIPH_RATIO << 12) \
+ | (COREM1_RATIO << 8) \
+ | (COREM0_RATIO << 4) \
+ | (CORE_RATIO << 0))
+
+/* CLK_DIV_CPU1 */
+#define HPM_RATIO 0x0
+#define COPY_RATIO 0x3
+#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO))
+
+/* CLK_SRC_DMC */
+#define MUX_PWI_SEL_XXTI 0x0
+#define MUX_PWI_SEL_XUSBXTI 0x1
+#define MUX_PWI_SEL_SCLK_HDMI24M 0x2
+#define MUX_PWI_SEL_SCLK_USBPHY0 0x3
+#define MUX_PWI_SEL_SCLK_USBPHY1 0x4
+#define MUX_PWI_SEL_SCLK_HDMIPHY 0x5
+#define MUX_PWI_SEL_SCLKMPLL 0x6
+#define MUX_PWI_SEL_SCLKEPLL 0x7
+#define MUX_PWI_SEL_SCLKVPLL 0x8
+#define MUX_DPHY_SEL_SCLKMPLL 0x0
+#define MUX_DPHY_SEL_SCLKAPLL 0x1
+#define MUX_DMC_BUS_SEL_SCLKMPLL 0x0
+#define MUX_DMC_BUS_SEL_SCLKAPLL 0x1
+#define CLK_SRC_DMC_VAL ((MUX_PWI_SEL_XUSBXTI << 16) \
+ | (MUX_DPHY_SEL_SCLKMPLL << 8) \
+ | (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
+
+/* CLK_DIV_DMC0 */
+#define CORE_TIMERS_RATIO 0x1
+#define COPY2_RATIO 0x3
+#define DMCP_RATIO 0x1
+#define DMCD_RATIO 0x1
+#define DMC_RATIO 0x1
+#define DPHY_RATIO 0x1
+#define ACP_PCLK_RATIO 0x1
+#define ACP_RATIO 0x3
+#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
+ | (COPY2_RATIO << 24) \
+ | (DMCP_RATIO << 20) \
+ | (DMCD_RATIO << 16) \
+ | (DMC_RATIO << 12) \
+ | (DPHY_RATIO << 8) \
+ | (ACP_PCLK_RATIO << 4) \
+ | (ACP_RATIO << 0))
+
+/* CLK_DIV_DMC1 */
+#define DPM_RATIO 0x1
+#define DVSEM_RATIO 0x1
+#define PWI_RATIO 0x1
+#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \
+ | (DVSEM_RATIO << 16) \
+ | (PWI_RATIO << 8))
+
+/* CLK_SRC_TOP0 */
+#define MUX_ONENAND_SEL_ACLK_133 0x0
+#define MUX_ONENAND_SEL_ACLK_160 0x1
+#define MUX_ACLK_133_SEL_SCLKMPLL 0x0
+#define MUX_ACLK_133_SEL_SCLKAPLL 0x1
+#define MUX_ACLK_160_SEL_SCLKMPLL 0x0
+#define MUX_ACLK_160_SEL_SCLKAPLL 0x1
+#define MUX_ACLK_100_SEL_SCLKMPLL 0x0
+#define MUX_ACLK_100_SEL_SCLKAPLL 0x1
+#define MUX_ACLK_200_SEL_SCLKMPLL 0x0
+#define MUX_ACLK_200_SEL_SCLKAPLL 0x1
+#define MUX_VPLL_SEL_FINPLL 0x0
+#define MUX_VPLL_SEL_FOUTVPLL 0x1
+#define MUX_EPLL_SEL_FINPLL 0x0
+#define MUX_EPLL_SEL_FOUTEPLL 0x1
+#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
+#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
+#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_133 << 28) \
+ | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
+ | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
+ | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
+ | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
+ | (MUX_VPLL_SEL_FINPLL << 8) \
+ | (MUX_EPLL_SEL_FINPLL << 4)\
+ | (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
+
+/* CLK_SRC_TOP1 */
+#define VPLLSRC_SEL_FINPLL 0x0
+#define VPLLSRC_SEL_SCLKHDMI24M 0x1
+#define CLK_SRC_TOP1_VAL (VPLLSRC_SEL_FINPLL)
+
+/* CLK_DIV_TOP */
+#define ONENAND_RATIO 0x0
+#define ACLK_133_RATIO 0x5
+#define ACLK_160_RATIO 0x4
+#define ACLK_100_RATIO 0x7
+#define ACLK_200_RATIO 0x3
+#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \
+ | (ACLK_133_RATIO << 12)\
+ | (ACLK_160_RATIO << 8) \
+ | (ACLK_100_RATIO << 4) \
+ | (ACLK_200_RATIO << 0))
+
+/* CLK_SRC_LEFTBUS */
+#define MUX_GDL_SEL_SCLKMPLL 0x0
+#define MUX_GDL_SEL_SCLKAPLL 0x1
+#define CLK_SRC_LEFTBUS_VAL (MUX_GDL_SEL_SCLKMPLL)
+
+/* CLK_DIV_LEFTBUS */
+#define GPL_RATIO 0x1
+#define GDL_RATIO 0x3
+#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO))
+
+/* CLK_SRC_RIGHTBUS */
+#define MUX_GDR_SEL_SCLKMPLL 0x0
+#define MUX_GDR_SEL_SCLKAPLL 0x1
+#define CLK_SRC_RIGHTBUS_VAL (MUX_GDR_SEL_SCLKMPLL)
+
+/* CLK_DIV_RIGHTBUS */
+#define GPR_RATIO 0x1
+#define GDR_RATIO 0x3
+#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO))
+
+/* CLK_SRS_FSYS: 6 = SCLKMPLL */
+#define SATA_SEL_SCLKMPLL 0
+#define SATA_SEL_SCLKAPLL 1
+
+#define MMC_SEL_XXTI 0
+#define MMC_SEL_XUSBXTI 1
+#define MMC_SEL_SCLK_HDMI24M 2
+#define MMC_SEL_SCLK_USBPHY0 3
+#define MMC_SEL_SCLK_USBPHY1 4
+#define MMC_SEL_SCLK_HDMIPHY 5
+#define MMC_SEL_SCLKMPLL 6
+#define MMC_SEL_SCLKEPLL 7
+#define MMC_SEL_SCLKVPLL 8
+
+#define MMCC0_SEL MMC_SEL_SCLKMPLL
+#define MMCC1_SEL MMC_SEL_SCLKMPLL
+#define MMCC2_SEL MMC_SEL_SCLKMPLL
+#define MMCC3_SEL MMC_SEL_SCLKMPLL
+#define MMCC4_SEL MMC_SEL_SCLKMPLL
+#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
+ | (MMCC4_SEL << 16) \
+ | (MMCC3_SEL << 12) \
+ | (MMCC2_SEL << 8) \
+ | (MMCC1_SEL << 4) \
+ | (MMCC0_SEL << 0))
+
+/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
+/* CLK_DIV_FSYS1 */
+#define MMC0_RATIO 0xF
+#define MMC0_PRE_RATIO 0x0
+#define MMC1_RATIO 0xF
+#define MMC1_PRE_RATIO 0x0
+#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
+ | (MMC1_RATIO << 16) \
+ | (MMC0_PRE_RATIO << 8) \
+ | (MMC0_RATIO << 0))
+
+/* CLK_DIV_FSYS2 */
+#define MMC2_RATIO 0xF
+#define MMC2_PRE_RATIO 0x0
+#define MMC3_RATIO 0xF
+#define MMC3_PRE_RATIO 0x0
+#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
+ | (MMC3_RATIO << 16) \
+ | (MMC2_PRE_RATIO << 8) \
+ | (MMC2_RATIO << 0))
+
+/* CLK_DIV_FSYS3 */
+#define MMC4_RATIO 0xF
+#define MMC4_PRE_RATIO 0x0
+#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
+ | (MMC4_RATIO << 0))
+
+/* CLK_SRC_PERIL0 */
+#define UART_SEL_XXTI 0
+#define UART_SEL_XUSBXTI 1
+#define UART_SEL_SCLK_HDMI24M 2
+#define UART_SEL_SCLK_USBPHY0 3
+#define UART_SEL_SCLK_USBPHY1 4
+#define UART_SEL_SCLK_HDMIPHY 5
+#define UART_SEL_SCLKMPLL 6
+#define UART_SEL_SCLKEPLL 7
+#define UART_SEL_SCLKVPLL 8
+
+#define UART0_SEL UART_SEL_SCLKMPLL
+#define UART1_SEL UART_SEL_SCLKMPLL
+#define UART2_SEL UART_SEL_SCLKMPLL
+#define UART3_SEL UART_SEL_SCLKMPLL
+#define UART4_SEL UART_SEL_SCLKMPLL
+#define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \
+ | (UART3_SEL << 12) \
+ | (UART2_SEL << 8) \
+ | (UART1_SEL << 4) \
+ | (UART0_SEL << 0))
+
+/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
+/* CLK_DIV_PERIL0 */
+#define UART0_RATIO 7
+#define UART1_RATIO 7
+#define UART2_RATIO 7
+#define UART3_RATIO 7
+#define UART4_RATIO 7
+#define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \
+ | (UART3_RATIO << 12) \
+ | (UART2_RATIO << 8) \
+ | (UART1_RATIO << 4) \
+ | (UART0_RATIO << 0))
+
+/* Clock Source CAM/FIMC */
+/* CLK_SRC_CAM */
+#define CAM0_SEL_XUSBXTI 1
+#define CAM1_SEL_XUSBXTI 1
+#define CSIS0_SEL_XUSBXTI 1
+#define CSIS1_SEL_XUSBXTI 1
+
+#define FIMC_SEL_SCLKMPLL 6
+#define FIMC0_LCLK_SEL FIMC_SEL_SCLKMPLL
+#define FIMC1_LCLK_SEL FIMC_SEL_SCLKMPLL
+#define FIMC2_LCLK_SEL FIMC_SEL_SCLKMPLL
+#define FIMC3_LCLK_SEL FIMC_SEL_SCLKMPLL
+
+#define CLK_SRC_CAM_VAL ((CSIS1_SEL_XUSBXTI << 28) \
+ | (CSIS0_SEL_XUSBXTI << 24) \
+ | (CAM1_SEL_XUSBXTI << 20) \
+ | (CAM0_SEL_XUSBXTI << 16) \
+ | (FIMC3_LCLK_SEL << 12) \
+ | (FIMC2_LCLK_SEL << 8) \
+ | (FIMC1_LCLK_SEL << 4) \
+ | (FIMC0_LCLK_SEL << 0))
+
+/* SCLK CAM */
+/* CLK_DIV_CAM */
+#define FIMC0_LCLK_RATIO 4
+#define FIMC1_LCLK_RATIO 4
+#define FIMC2_LCLK_RATIO 4
+#define FIMC3_LCLK_RATIO 4
+#define CLK_DIV_CAM_VAL ((FIMC3_LCLK_RATIO << 12) \
+ | (FIMC2_LCLK_RATIO << 8) \
+ | (FIMC1_LCLK_RATIO << 4) \
+ | (FIMC0_LCLK_RATIO << 0))
+
+/* SCLK MFC */
+/* CLK_SRC_MFC */
+#define MFC_SEL_MPLL 0
+#define MOUTMFC_0 0
+#define MFC_SEL MOUTMFC_0
+#define MFC_0_SEL MFC_SEL_MPLL
+#define CLK_SRC_MFC_VAL ((MFC_SEL << 8) | (MFC_0_SEL))
+
+
+/* CLK_DIV_MFC */
+#define MFC_RATIO 3
+#define CLK_DIV_MFC_VAL (MFC_RATIO)
+
+/* SCLK G3D */
+/* CLK_SRC_G3D */
+#define G3D_SEL_MPLL 0
+#define MOUTG3D_0 0
+#define G3D_SEL MOUTG3D_0
+#define G3D_0_SEL G3D_SEL_MPLL
+#define CLK_SRC_G3D_VAL ((G3D_SEL << 8) | (G3D_0_SEL))
+
+/* CLK_DIV_G3D */
+#define G3D_RATIO 1
+#define CLK_DIV_G3D_VAL (G3D_RATIO)
+
+/* SCLK LCD0 */
+/* CLK_SRC_LCD0 */
+#define FIMD_SEL_SCLKMPLL 6
+#define MDNIE0_SEL_XUSBXTI 1
+#define MDNIE_PWM0_SEL_XUSBXTI 1
+#define MIPI0_SEL_XUSBXTI 1
+#define CLK_SRC_LCD0_VAL ((MIPI0_SEL_XUSBXTI << 12) \
+ | (MDNIE_PWM0_SEL_XUSBXTI << 8) \
+ | (MDNIE0_SEL_XUSBXTI << 4) \
+ | (FIMD_SEL_SCLKMPLL << 0))
+
+/* CLK_DIV_LCD0 */
+#define FIMD0_RATIO 4
+#define CLK_DIV_LCD0_VAL (FIMD0_RATIO)
+
+/* Required period to generate a stable clock output */
+/* PLL_LOCK_TIME */
+#define PLL_LOCKTIME 0x1C20
+
+/* PLL Values */
+#define DISABLE 0
+#define ENABLE 1
+#define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\
+ | (mdiv << 16) \
+ | (pdiv << 8) \
+ | (sdiv << 0))
+
+/* APLL_CON0 */
+#define APLL_MDIV 0xFA
+#define APLL_PDIV 0x6
+#define APLL_SDIV 0x1
+#define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
+
+/* APLL_CON1 */
+#define APLL_AFC_ENB 0x1
+#define APLL_AFC 0xC
+#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
+
+/* MPLL_CON0 */
+#define MPLL_MDIV 0xC8
+#define MPLL_PDIV 0x6
+#define MPLL_SDIV 0x1
+#define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
+
+/* MPLL_CON1 */
+#define MPLL_AFC_ENB 0x0
+#define MPLL_AFC 0x1C
+#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
+
+/* EPLL_CON0 */
+#define EPLL_MDIV 0x30
+#define EPLL_PDIV 0x3
+#define EPLL_SDIV 0x2
+#define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
+
+/* EPLL_CON1 */
+#define EPLL_K 0x0
+#define EPLL_CON1_VAL (EPLL_K >> 0)
+
+/* VPLL_CON0 */
+#define VPLL_MDIV 0x35
+#define VPLL_PDIV 0x3
+#define VPLL_SDIV 0x2
+#define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
+
+/* VPLL_CON1 */
+#define VPLL_SSCG_EN DISABLE
+#define VPLL_SEL_PF_DN_SPREAD 0x0
+#define VPLL_MRR 0x11
+#define VPLL_MFR 0x0
+#define VPLL_K 0x400
+#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
+ | (VPLL_SEL_PF_DN_SPREAD << 29) \
+ | (VPLL_MRR << 24) \
+ | (VPLL_MFR << 16) \
+ | (VPLL_K << 0))
+
+/* DMC */
+#define DIRECT_CMD_NOP 0x07000000
+#define DIRECT_CMD_ZQ 0x0a000000
+#define DIRECT_CMD_CHIP1_SHIFT (1 << 20)
+#define MEM_TIMINGS_MSR_COUNT 4
+#define CTRL_START (1 << 0)
+#define CTRL_DLL_ON (1 << 1)
+#define AREF_EN (1 << 5)
+#define DRV_TYPE (1 << 6)
+
+struct mem_timings {
+ unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
+ unsigned timingref;
+ unsigned timingrow;
+ unsigned timingdata;
+ unsigned timingpower;
+ unsigned zqcontrol;
+ unsigned control0;
+ unsigned control1;
+ unsigned control2;
+ unsigned concontrol;
+ unsigned prechconfig;
+ unsigned memcontrol;
+ unsigned memconfig0;
+ unsigned memconfig1;
+ unsigned dll_resync;
+ unsigned dll_on;
+};
+
+/* MIU */
+/* MIU Config Register Offsets*/
+#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400
+#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
+#define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET 0x800
+#define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET 0x808
+#define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET 0x810
+#define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET 0x818
+#define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET 0x820
+#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET 0x828
+#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET 0x830
+
+#ifdef CONFIG_ORIGEN
+/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
+#define APB_SFR_INTERLEAVE_CONF_VAL 0x20001507
+#define APB_SFR_ARBRITATION_CONF_VAL 0x00000001
+#endif
+
+#define INTERLEAVE_ADDR_MAP_START_ADDR 0x40000000
+#define INTERLEAVE_ADDR_MAP_END_ADDR 0xbfffffff
+#define INTERLEAVE_ADDR_MAP_EN 0x00000001
+
+#ifdef CONFIG_MIU_1BIT_INTERLEAVED
+/* Interleave_bit0: 0xC*/
+#define APB_SFR_INTERLEAVE_CONF_VAL 0x0000000c
+#endif
+#ifdef CONFIG_MIU_2BIT_INTERLEAVED
+/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */
+#define APB_SFR_INTERLEAVE_CONF_VAL 0x2000150c
+#endif
+#define SLAVE0_SINGLE_ADDR_MAP_START_ADDR 0x40000000
+#define SLAVE0_SINGLE_ADDR_MAP_END_ADDR 0x7fffffff
+#define SLAVE1_SINGLE_ADDR_MAP_START_ADDR 0x80000000
+#define SLAVE1_SINGLE_ADDR_MAP_END_ADDR 0xbfffffff
+/* Enable SME0 and SME1*/
+#define APB_SFR_SLV_ADDR_MAP_CONF_VAL 0x00000006
+
+#define FORCE_DLL_RESYNC 3
+#define DLL_CONTROL_ON 1
+
+#define DIRECT_CMD1 0x00020000
+#define DIRECT_CMD2 0x00030000
+#define DIRECT_CMD3 0x00010002
+#define DIRECT_CMD4 0x00000328
+
+#define CTRL_ZQ_MODE_NOTERM (0x1 << 0)
+#define CTRL_ZQ_START (0x1 << 1)
+#define CTRL_ZQ_DIV (0 << 4)
+#define CTRL_ZQ_MODE_DDS (0x7 << 8)
+#define CTRL_ZQ_MODE_TERM (0x2 << 11)
+#define CTRL_ZQ_FORCE_IMPN (0x5 << 14)
+#define CTRL_ZQ_FORCE_IMPP (0x6 << 17)
+#define CTRL_DCC (0xE38 << 20)
+#define ZQ_CONTROL_VAL (CTRL_ZQ_MODE_NOTERM | CTRL_ZQ_START\
+ | CTRL_ZQ_DIV | CTRL_ZQ_MODE_DDS\
+ | CTRL_ZQ_MODE_TERM | CTRL_ZQ_FORCE_IMPN\
+ | CTRL_ZQ_FORCE_IMPP | CTRL_DCC)
+
+#define ASYNC (0 << 0)
+#define CLK_RATIO (1 << 1)
+#define DIV_PIPE (1 << 3)
+#define AWR_ON (1 << 4)
+#define AREF_DISABLE (0 << 5)
+#define DRV_TYPE_DISABLE (0 << 6)
+#define CHIP0_NOT_EMPTY (0 << 8)
+#define CHIP1_NOT_EMPTY (0 << 9)
+#define DQ_SWAP_DISABLE (0 << 10)
+#define QOS_FAST_DISABLE (0 << 11)
+#define RD_FETCH (0x3 << 12)
+#define TIMEOUT_LEVEL0 (0xFFF << 16)
+#define CONCONTROL_VAL (ASYNC | CLK_RATIO | DIV_PIPE | AWR_ON\
+ | AREF_DISABLE | DRV_TYPE_DISABLE\
+ | CHIP0_NOT_EMPTY | CHIP1_NOT_EMPTY\
+ | DQ_SWAP_DISABLE | QOS_FAST_DISABLE\
+ | RD_FETCH | TIMEOUT_LEVEL0)
+
+#define CLK_STOP_DISABLE (0 << 1)
+#define DPWRDN_DISABLE (0 << 2)
+#define DPWRDN_TYPE (0 << 3)
+#define TP_DISABLE (0 << 4)
+#define DSREF_DIABLE (0 << 5)
+#define ADD_LAT_PALL (1 << 6)
+#define MEM_TYPE_DDR3 (0x6 << 8)
+#define MEM_WIDTH_32 (0x2 << 12)
+#define NUM_CHIP_2 (1 << 16)
+#define BL_8 (0x3 << 20)
+#define MEMCONTROL_VAL (CLK_STOP_DISABLE | DPWRDN_DISABLE\
+ | DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\
+ | ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\
+ | NUM_CHIP_2 | BL_8)
+
+
+#define CHIP_BANK_8 (0x3 << 0)
+#define CHIP_ROW_14 (0x2 << 4)
+#define CHIP_COL_10 (0x3 << 8)
+#define CHIP_MAP_INTERLEAVED (1 << 12)
+#define CHIP_MASK (0xe0 << 16)
+#ifdef CONFIG_MIU_LINEAR
+#define CHIP0_BASE (0x40 << 24)
+#define CHIP1_BASE (0x60 << 24)
+#else
+#define CHIP0_BASE (0x20 << 24)
+#define CHIP1_BASE (0x40 << 24)
+#endif
+#define MEMCONFIG0_VAL (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
+ | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP0_BASE)
+#define MEMCONFIG1_VAL (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
+ | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP1_BASE)
+
+#define TP_CNT (0xff << 24)
+#define PRECHCONFIG TP_CNT
+
+#define CTRL_OFF (0 << 0)
+#define CTRL_DLL_OFF (0 << 1)
+#define CTRL_HALF (0 << 2)
+#define CTRL_DFDQS (1 << 3)
+#define DQS_DELAY (0 << 4)
+#define CTRL_START_POINT (0x10 << 8)
+#define CTRL_INC (0x10 << 16)
+#define CTRL_FORCE (0x71 << 24)
+#define CONTROL0_VAL (CTRL_OFF | CTRL_DLL_OFF | CTRL_HALF\
+ | CTRL_DFDQS | DQS_DELAY | CTRL_START_POINT\
+ | CTRL_INC | CTRL_FORCE)
+
+#define CTRL_SHIFTC (0x6 << 0)
+#define CTRL_REF (8 << 4)
+#define CTRL_SHGATE (1 << 29)
+#define TERM_READ_EN (1 << 30)
+#define TERM_WRITE_EN (1 << 31)
+#define CONTROL1_VAL (CTRL_SHIFTC | CTRL_REF | CTRL_SHGATE\
+ | TERM_READ_EN | TERM_WRITE_EN)
+
+#define CONTROL2_VAL 0x00000000
+
+#ifdef CONFIG_ORIGEN
+#define TIMINGREF_VAL 0x000000BB
+#define TIMINGROW_VAL 0x4046654f
+#define TIMINGDATA_VAL 0x46400506
+#define TIMINGPOWER_VAL 0x52000A3C
+#else
+#define TIMINGREF_VAL 0x000000BC
+#ifdef DRAM_CLK_330
+#define TIMINGROW_VAL 0x3545548d
+#define TIMINGDATA_VAL 0x45430506
+#define TIMINGPOWER_VAL 0x4439033c
+#endif
+#ifdef DRAM_CLK_400
+#define TIMINGROW_VAL 0x45430506
+#define TIMINGDATA_VAL 0x56500506
+#define TIMINGPOWER_VAL 0x5444033d
+#endif
+#endif
+#endif
--- /dev/null
+/*
+ * Machine Specific Values for SMDK5250 board based on EXYNOS5
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SMDK5250_SETUP_H
+#define _SMDK5250_SETUP_H
+
+#include <config.h>
+#include <asm/arch/dmc.h>
+
+#define NOT_AVAILABLE 0
+#define DATA_MASK 0xFFFFF
+
+#define ENABLE_BIT 0x1
+#define DISABLE_BIT 0x0
+#define CA_SWAP_EN (1 << 0)
+
+/* Set PLL */
+#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
+
+/* MEMCONTROL register bit fields */
+#define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
+#define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
+#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)
+#define DMC_MEMCONTROL_TP_DISABLE (0 << 4)
+#define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)
+#define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5)
+#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)
+
+#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8)
+#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8)
+#define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)
+
+#define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)
+
+#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16)
+#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)
+
+#define DMC_MEMCONTROL_BL_8 (3 << 20)
+#define DMC_MEMCONTROL_BL_4 (2 << 20)
+
+#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)
+
+#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25)
+#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25)
+#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25)
+#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)
+
+/* MEMCONFIG0 register bit fields */
+#define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12)
+#define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12)
+#define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8)
+#define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4)
+#define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4)
+#define DMC_MEMCONFIGX_CHIP_BANK_8 (3 << 0)
+
+#define DMC_MEMBASECONFIGX_CHIP_BASE(x) (x << 16)
+#define DMC_MEMBASECONFIGX_CHIP_MASK(x) (x << 0)
+#define DMC_MEMBASECONFIG_VAL(x) ( \
+ DMC_MEMBASECONFIGX_CHIP_BASE(x) | \
+ DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \
+)
+
+/*
+ * As we use channel interleaving, therefore value of the base address
+ * register must be set as half of the bus base address
+ * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
+ * we need to set half 0x10 to the membaseconfigx registers
+ * see exynos5420 UM section 17.17.3.21 for more.
+ */
+#define DMC_CHIP_BASE_0 0x10
+#define DMC_CHIP_BASE_1 0x50
+#define DMC_CHIP_MASK 0x7C0
+
+#define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
+#define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
+
+#define DMC_PRECHCONFIG_VAL 0xFF000000
+#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
+
+#define DMC_CONCONTROL_RESET_VAL 0x0FFF0000
+#define DFI_INIT_START (1 << 28)
+#define EMPTY (1 << 8)
+#define AREF_EN (1 << 5)
+
+#define DFI_INIT_COMPLETE_CHO (1 << 2)
+#define DFI_INIT_COMPLETE_CH1 (1 << 3)
+
+#define RDLVL_COMPLETE_CHO (1 << 14)
+#define RDLVL_COMPLETE_CH1 (1 << 15)
+
+#define CLK_STOP_EN (1 << 0)
+#define DPWRDN_EN (1 << 1)
+#define DSREF_EN (1 << 5)
+
+/* COJCONTROL register bit fields */
+#define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
+#define DMC_CONCONTROL_IO_PD_CON_ENABLE (1 << 3)
+#define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
+#define DMC_CONCONTROL_AREF_EN_ENABLE (1 << 5)
+#define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
+#define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
+#define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
+#define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
+#define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
+
+#define DMC_CONCONTROL_VAL 0x1FFF2101
+
+#define DREX_CONCONTROL_VAL DMC_CONCONTROL_VAL \
+ | DMC_CONCONTROL_AREF_EN_ENABLE \
+ | DMC_CONCONTROL_IO_PD_CON_ENABLE
+
+#define DMC_CONCONTROL_IO_PD_CON(x) (x << 6)
+
+/* CLK_DIV_CPU1 */
+#define HPM_RATIO 0x2
+#define COPY_RATIO 0x0
+
+/* CLK_DIV_CPU1 = 0x00000003 */
+#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
+ | (COPY_RATIO))
+
+/* CLK_SRC_CORE0 */
+#define CLK_SRC_CORE0_VAL 0x00000000
+
+/* CLK_SRC_CORE1 */
+#define CLK_SRC_CORE1_VAL 0x100
+
+/* CLK_DIV_CORE0 */
+#define CLK_DIV_CORE0_VAL 0x00120000
+
+/* CLK_DIV_CORE1 */
+#define CLK_DIV_CORE1_VAL 0x07070700
+
+/* CLK_DIV_SYSRGT */
+#define CLK_DIV_SYSRGT_VAL 0x00000111
+
+/* CLK_DIV_ACP */
+#define CLK_DIV_ACP_VAL 0x12
+
+/* CLK_DIV_SYSLFT */
+#define CLK_DIV_SYSLFT_VAL 0x00000311
+
+#define MUX_APLL_SEL_MASK (1 << 0)
+#define MUX_MPLL_SEL_MASK (1 << 8)
+#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
+#define MUX_CPLL_SEL_MASK (1 << 8)
+#define MUX_EPLL_SEL_MASK (1 << 12)
+#define MUX_VPLL_SEL_MASK (1 << 16)
+#define MUX_GPLL_SEL_MASK (1 << 28)
+#define MUX_BPLL_SEL_MASK (1 << 0)
+#define MUX_HPM_SEL_MASK (1 << 20)
+#define HPM_SEL_SCLK_MPLL (1 << 21)
+#define PLL_LOCKED (1 << 29)
+#define APLL_CON0_LOCKED (1 << 29)
+#define MPLL_CON0_LOCKED (1 << 29)
+#define BPLL_CON0_LOCKED (1 << 29)
+#define CPLL_CON0_LOCKED (1 << 29)
+#define EPLL_CON0_LOCKED (1 << 29)
+#define GPLL_CON0_LOCKED (1 << 29)
+#define VPLL_CON0_LOCKED (1 << 29)
+#define CLK_REG_DISABLE 0x0
+#define TOP2_VAL 0x0110000
+
+/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
+#define SPI0_ISP_SEL 6
+#define SPI1_ISP_SEL 6
+#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
+ | (SPI0_ISP_SEL << 0)
+
+/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
+#define SPI0_ISP_RATIO 0xf
+#define SPI1_ISP_RATIO 0xf
+#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
+ | (SPI0_ISP_RATIO << 0)
+
+/* CLK_DIV_FSYS2 */
+#define MMC2_RATIO_MASK 0xf
+#define MMC2_RATIO_VAL 0x3
+#define MMC2_RATIO_OFFSET 0
+
+#define MMC2_PRE_RATIO_MASK 0xff
+#define MMC2_PRE_RATIO_VAL 0x9
+#define MMC2_PRE_RATIO_OFFSET 8
+
+#define MMC3_RATIO_MASK 0xf
+#define MMC3_RATIO_VAL 0x1
+#define MMC3_RATIO_OFFSET 16
+
+#define MMC3_PRE_RATIO_MASK 0xff
+#define MMC3_PRE_RATIO_VAL 0x0
+#define MMC3_PRE_RATIO_OFFSET 24
+
+/* CLK_SRC_LEX */
+#define CLK_SRC_LEX_VAL 0x0
+
+/* CLK_DIV_LEX */
+#define CLK_DIV_LEX_VAL 0x10
+
+/* CLK_DIV_R0X */
+#define CLK_DIV_R0X_VAL 0x10
+
+/* CLK_DIV_L0X */
+#define CLK_DIV_R1X_VAL 0x10
+
+/* CLK_DIV_ISP2 */
+#define CLK_DIV_ISP2_VAL 0x1
+
+/* CLK_SRC_KFC */
+#define SRC_KFC_HPM_SEL (1 << 15)
+
+/* CLK_SRC_KFC */
+#define CLK_SRC_KFC_VAL 0x00008001
+
+/* CLK_DIV_KFC */
+#define CLK_DIV_KFC_VAL 0x03300110
+
+/* CLK_DIV2_RATIO */
+#define CLK_DIV2_RATIO 0x10111150
+
+/* CLK_DIV4_RATIO */
+#define CLK_DIV4_RATIO 0x00000003
+
+/* CLK_DIV_G2D */
+#define CLK_DIV_G2D 0x00000010
+
+/*
+ * DIV_DISP1_0
+ * For DP, divisor should be 2
+ */
+#define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
+
+/* CLK_GATE_IP_DISP1 */
+#define CLK_GATE_DP1_ALLOW (1 << 4)
+
+/* AUDIO CLK SEL */
+#define AUDIO0_SEL_EPLL (0x6 << 28)
+#define AUDIO0_RATIO 0x5
+#define PCM0_RATIO 0x3
+#define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20)
+
+/* CLK_SRC_CDREX */
+#define MUX_MCLK_CDR_MSPLL (1 << 4)
+#define MUX_BPLL_SEL_FOUTBPLL (1 << 0)
+#define BPLL_SEL_MASK 0x7
+#define FOUTBPLL 2
+
+#define DDR3PHY_CTRL_PHY_RESET (1 << 0)
+#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
+
+#define PHY_CON0_RESET_VAL 0x17020a40
+#define P0_CMD_EN (1 << 14)
+#define BYTE_RDLVL_EN (1 << 13)
+#define CTRL_SHGATE (1 << 8)
+
+#define PHY_CON1_RESET_VAL 0x09210100
+#define RDLVL_PASS_ADJ_VAL 0x6
+#define RDLVL_PASS_ADJ_OFFSET 16
+#define CTRL_GATEDURADJ_MASK (0xf << 20)
+#define READ_LEVELLING_DDR3 0x0100
+
+#define PHY_CON2_RESET_VAL 0x00010004
+#define INIT_DESKEW_EN (1 << 6)
+#define DLL_DESKEW_EN (1 << 12)
+#define RDLVL_GATE_EN (1 << 24)
+#define RDLVL_EN (1 << 25)
+#define RDLVL_INCR_ADJ (0x1 << 16)
+
+/* DREX_PAUSE */
+#define DREX_PAUSE_EN (1 << 0)
+
+#define BYPASS_EN (1 << 22)
+
+/* MEMMORY VAL */
+#define PHY_CON0_VAL 0x17021A00
+
+#define PHY_CON12_RESET_VAL 0x10100070
+#define PHY_CON12_VAL 0x10107F50
+#define CTRL_START (1 << 6)
+#define CTRL_DLL_ON (1 << 5)
+#define CTRL_LOCK_COARSE_OFFSET 10
+#define CTRL_LOCK_COARSE_MASK (0x7F << CTRL_LOCK_COARSE_OFFSET)
+#define CTRL_LOCK_COARSE(x) (((x) & CTRL_LOCK_COARSE_MASK) >> \
+ CTRL_LOCK_COARSE_OFFSET)
+#define CTRL_FORCE_MASK (0x7F << 8)
+#define CTRL_FINE_LOCKED 0x7
+
+#define CTRL_OFFSETD_RESET_VAL 0x8
+#define CTRL_OFFSETD_VAL 0x7F
+
+#define CTRL_OFFSETR0 0x7F
+#define CTRL_OFFSETR1 0x7F
+#define CTRL_OFFSETR2 0x7F
+#define CTRL_OFFSETR3 0x7F
+#define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \
+ CTRL_OFFSETR1 << 8 | \
+ CTRL_OFFSETR2 << 16 | \
+ CTRL_OFFSETR3 << 24)
+#define PHY_CON4_RESET_VAL 0x08080808
+
+#define CTRL_OFFSETW0 0x7F
+#define CTRL_OFFSETW1 0x7F
+#define CTRL_OFFSETW2 0x7F
+#define CTRL_OFFSETW3 0x7F
+#define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \
+ CTRL_OFFSETW1 << 8 | \
+ CTRL_OFFSETW2 << 16 | \
+ CTRL_OFFSETW3 << 24)
+#define PHY_CON6_RESET_VAL 0x08080808
+
+#define PHY_CON14_RESET_VAL 0x001F0000
+#define CTRL_PULLD_DQS 0xF
+#define CTRL_PULLD_DQS_OFFSET 0
+
+/* ZQ Configurations */
+#define PHY_CON16_RESET_VAL 0x08000304
+
+#define ZQ_CLK_EN (1 << 27)
+#define ZQ_CLK_DIV_EN (1 << 18)
+#define ZQ_MANUAL_STR (1 << 1)
+#define ZQ_DONE (1 << 0)
+#define ZQ_MODE_DDS_OFFSET 24
+
+#define CTRL_RDLVL_GATE_ENABLE 1
+#define CTRL_RDLVL_GATE_DISABLE 0
+#define CTRL_RDLVL_DATA_ENABLE 2
+
+/* Direct Command */
+#define DIRECT_CMD_NOP 0x07000000
+#define DIRECT_CMD_PALL 0x01000000
+#define DIRECT_CMD_ZQINIT 0x0a000000
+#define DIRECT_CMD_CHANNEL_SHIFT 28
+#define DIRECT_CMD_CHIP_SHIFT 20
+#define DIRECT_CMD_BANK_SHIFT 16
+#define DIRECT_CMD_REFA (5 << 24)
+#define DIRECT_CMD_MRS1 0x71C00
+#define DIRECT_CMD_MRS2 0x10BFC
+#define DIRECT_CMD_MRS3 0x0050C
+#define DIRECT_CMD_MRS4 0x00868
+#define DIRECT_CMD_MRS5 0x00C04
+
+/* Drive Strength */
+#define IMPEDANCE_48_OHM 4
+#define IMPEDANCE_40_OHM 5
+#define IMPEDANCE_34_OHM 6
+#define IMPEDANCE_30_OHM 7
+#define PHY_CON39_VAL_48_OHM 0x09240924
+#define PHY_CON39_VAL_40_OHM 0x0B6D0B6D
+#define PHY_CON39_VAL_34_OHM 0x0DB60DB6
+#define PHY_CON39_VAL_30_OHM 0x0FFF0FFF
+
+#define CTRL_BSTLEN_OFFSET 8
+#define CTRL_RDLAT_OFFSET 0
+
+#define CMD_DEFAULT_LPDDR3 0xF
+#define CMD_DEFUALT_OFFSET 0
+#define T_WRDATA_EN 0x7
+#define T_WRDATA_EN_DDR3 0x8
+#define T_WRDATA_EN_OFFSET 16
+#define T_WRDATA_EN_MASK 0x1f
+
+#define PHY_CON31_VAL 0x0C183060
+#define PHY_CON32_VAL 0x60C18306
+#define PHY_CON33_VAL 0x00000030
+
+#define PHY_CON31_RESET_VAL 0x0
+#define PHY_CON32_RESET_VAL 0x0
+#define PHY_CON33_RESET_VAL 0x0
+
+#define SL_DLL_DYN_CON_EN (1 << 1)
+#define FP_RESYNC (1 << 3)
+#define CTRL_START (1 << 6)
+
+#define DMC_AREF_EN (1 << 5)
+#define DMC_CONCONTROL_EMPTY (1 << 8)
+#define DFI_INIT_START (1 << 28)
+
+#define DMC_MEMCONTROL_VAL 0x00312700
+#define CLK_STOP_EN (1 << 0)
+#define DPWRDN_EN (1 << 1)
+#define DSREF_EN (1 << 5)
+
+#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
+#define MEMBASECONFIG_CHIP_MASK_OFFSET 0
+#define MEMBASECONFIG0_CHIP_BASE_VAL 0x20
+#define MEMBASECONFIG1_CHIP_BASE_VAL 0x40
+#define CHIP_BASE_OFFSET 16
+
+#define MEMCONFIG_VAL 0x1323
+#define PRECHCONFIG_DEFAULT_VAL 0xFF000000
+#define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF
+
+#define TIMINGAREF_VAL 0x5d
+#define TIMINGROW_VAL 0x345A8692
+#define TIMINGDATA_VAL 0x3630065C
+#define TIMINGPOWER_VAL 0x50380336
+#define DFI_INIT_COMPLETE (1 << 3)
+
+#define BRBRSVCONTROL_VAL 0x00000033
+#define BRBRSVCONFIG_VAL 0x88778877
+
+/* Clock Gating Control (CGCONTROL) register */
+#define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */
+#define SCG_CG_EN (1 << 2) /* Scheduler clock gating */
+#define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */
+#define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */
+#define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \
+ BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)
+
+/* DMC PHY Control0 register */
+#define PHY_CONTROL0_RESET_VAL 0x0
+#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
+#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
+#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
+#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
+
+/* Driver strength for CK, CKE, CS & CA */
+#define IMP_OUTPUT_DRV_40_OHM 0x5
+#define IMP_OUTPUT_DRV_30_OHM 0x7
+#define DA_3_DS_OFFSET 25
+#define DA_2_DS_OFFSET 22
+#define DA_1_DS_OFFSET 19
+#define DA_0_DS_OFFSET 16
+#define CA_CK_DRVR_DS_OFFSET 9
+#define CA_CKE_DRVR_DS_OFFSET 6
+#define CA_CS_DRVR_DS_OFFSET 3
+#define CA_ADR_DRVR_DS_OFFSET 0
+
+#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
+#define PHY_CON42_CTRL_RDLAT_SHIFT 0
+
+/*
+ * Definitions that differ with SoC's.
+ * Below is the part defining macros for Exynos5250.
+ * Else part introduces macros for Exynos5420.
+ */
+#ifndef CONFIG_EXYNOS5420
+
+/* APLL_CON1 */
+#define APLL_CON1_VAL (0x00203800)
+
+/* MPLL_CON1 */
+#define MPLL_CON1_VAL (0x00203800)
+
+/* CPLL_CON1 */
+#define CPLL_CON1_VAL (0x00203800)
+
+/* DPLL_CON1 */
+#define DPLL_CON1_VAL (NOT_AVAILABLE)
+
+/* GPLL_CON1 */
+#define GPLL_CON1_VAL (0x00203800)
+
+/* EPLL_CON1, CON2 */
+#define EPLL_CON1_VAL 0x00000000
+#define EPLL_CON2_VAL 0x00000080
+
+/* VPLL_CON1, CON2 */
+#define VPLL_CON1_VAL 0x00000000
+#define VPLL_CON2_VAL 0x00000080
+
+/* RPLL_CON1, CON2 */
+#define RPLL_CON1_VAL NOT_AVAILABLE
+#define RPLL_CON2_VAL NOT_AVAILABLE
+
+/* BPLL_CON1 */
+#define BPLL_CON1_VAL 0x00203800
+
+/* SPLL_CON1 */
+#define SPLL_CON1_VAL NOT_AVAILABLE
+
+/* IPLL_CON1 */
+#define IPLL_CON1_VAL NOT_AVAILABLE
+
+/* KPLL_CON1 */
+#define KPLL_CON1_VAL NOT_AVAILABLE
+
+/* CLK_SRC_ISP */
+#define CLK_SRC_ISP_VAL NOT_AVAILABLE
+#define CLK_DIV_ISP0_VAL 0x31
+#define CLK_DIV_ISP1_VAL 0x0
+
+/* CLK_FSYS */
+#define CLK_SRC_FSYS0_VAL 0x66666
+#define CLK_DIV_FSYS0_VAL 0x0BB00000
+#define CLK_DIV_FSYS1_VAL NOT_AVAILABLE
+#define CLK_DIV_FSYS2_VAL NOT_AVAILABLE
+
+/* CLK_SRC_CPU */
+/* 0 = MOUTAPLL, 1 = SCLKMPLL */
+#define MUX_HPM_SEL 0
+#define MUX_CPU_SEL 0
+#define MUX_APLL_SEL 1
+
+#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
+ | (MUX_CPU_SEL << 16) \
+ | (MUX_APLL_SEL))
+
+/* CLK_SRC_CDREX */
+#define CLK_SRC_CDREX_VAL 0x1
+
+/* CLK_DIV_CDREX */
+#define CLK_DIV_CDREX0_VAL NOT_AVAILABLE
+#define CLK_DIV_CDREX1_VAL NOT_AVAILABLE
+
+/* CLK_DIV_CPU0_VAL */
+#define CLK_DIV_CPU0_VAL NOT_AVAILABLE
+
+#define MCLK_CDREX2_RATIO 0x0
+#define ACLK_EFCON_RATIO 0x1
+#define MCLK_DPHY_RATIO 0x1
+#define MCLK_CDREX_RATIO 0x1
+#define ACLK_C2C_200_RATIO 0x1
+#define C2C_CLK_400_RATIO 0x1
+#define PCLK_CDREX_RATIO 0x1
+#define ACLK_CDREX_RATIO 0x1
+
+#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \
+ | (C2C_CLK_400_RATIO << 6) \
+ | (PCLK_CDREX_RATIO << 4) \
+ | (ACLK_CDREX_RATIO))
+
+/* CLK_SRC_TOP0 */
+#define MUX_ACLK_300_GSCL_SEL 0x0
+#define MUX_ACLK_300_GSCL_MID_SEL 0x0
+#define MUX_ACLK_400_G3D_MID_SEL 0x0
+#define MUX_ACLK_333_SEL 0x0
+#define MUX_ACLK_300_DISP1_SEL 0x0
+#define MUX_ACLK_300_DISP1_MID_SEL 0x0
+#define MUX_ACLK_200_SEL 0x0
+#define MUX_ACLK_166_SEL 0x0
+#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
+ | (MUX_ACLK_300_GSCL_MID_SEL << 24) \
+ | (MUX_ACLK_400_G3D_MID_SEL << 20) \
+ | (MUX_ACLK_333_SEL << 16) \
+ | (MUX_ACLK_300_DISP1_SEL << 15) \
+ | (MUX_ACLK_300_DISP1_MID_SEL << 14) \
+ | (MUX_ACLK_200_SEL << 12) \
+ | (MUX_ACLK_166_SEL << 8))
+
+/* CLK_SRC_TOP1 */
+#define MUX_ACLK_400_G3D_SEL 0x1
+#define MUX_ACLK_400_ISP_SEL 0x0
+#define MUX_ACLK_400_IOP_SEL 0x0
+#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
+#define MUX_ACLK_300_GSCL_MID1_SEL 0x0
+#define MUX_ACLK_300_DISP1_MID1_SEL 0x0
+#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \
+ |(MUX_ACLK_400_ISP_SEL << 24) \
+ |(MUX_ACLK_400_IOP_SEL << 20) \
+ |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \
+ |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \
+ |(MUX_ACLK_300_DISP1_MID1_SEL << 8))
+
+/* CLK_SRC_TOP2 */
+#define MUX_GPLL_SEL 0x1
+#define MUX_BPLL_USER_SEL 0x0
+#define MUX_MPLL_USER_SEL 0x0
+#define MUX_VPLL_SEL 0x1
+#define MUX_EPLL_SEL 0x1
+#define MUX_CPLL_SEL 0x1
+#define VPLLSRC_SEL 0x0
+#define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \
+ | (MUX_BPLL_USER_SEL << 24) \
+ | (MUX_MPLL_USER_SEL << 20) \
+ | (MUX_VPLL_SEL << 16) \
+ | (MUX_EPLL_SEL << 12) \
+ | (MUX_CPLL_SEL << 8) \
+ | (VPLLSRC_SEL))
+/* CLK_SRC_TOP3 */
+#define MUX_ACLK_333_SUB_SEL 0x1
+#define MUX_ACLK_400_SUB_SEL 0x1
+#define MUX_ACLK_266_ISP_SUB_SEL 0x1
+#define MUX_ACLK_266_GPS_SUB_SEL 0x0
+#define MUX_ACLK_300_GSCL_SUB_SEL 0x1
+#define MUX_ACLK_266_GSCL_SUB_SEL 0x1
+#define MUX_ACLK_300_DISP1_SUB_SEL 0x1
+#define MUX_ACLK_200_DISP1_SUB_SEL 0x1
+#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
+ | (MUX_ACLK_400_SUB_SEL << 20) \
+ | (MUX_ACLK_266_ISP_SUB_SEL << 16) \
+ | (MUX_ACLK_266_GPS_SUB_SEL << 12) \
+ | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
+ | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
+ | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
+ | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
+
+#define CLK_SRC_TOP4_VAL NOT_AVAILABLE
+#define CLK_SRC_TOP5_VAL NOT_AVAILABLE
+#define CLK_SRC_TOP6_VAL NOT_AVAILABLE
+#define CLK_SRC_TOP7_VAL NOT_AVAILABLE
+
+/* CLK_DIV_TOP0 */
+#define ACLK_300_DISP1_RATIO 0x2
+#define ACLK_400_G3D_RATIO 0x0
+#define ACLK_333_RATIO 0x0
+#define ACLK_266_RATIO 0x2
+#define ACLK_200_RATIO 0x3
+#define ACLK_166_RATIO 0x1
+#define ACLK_133_RATIO 0x1
+#define ACLK_66_RATIO 0x5
+
+#define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \
+ | (ACLK_400_G3D_RATIO << 24) \
+ | (ACLK_333_RATIO << 20) \
+ | (ACLK_266_RATIO << 16) \
+ | (ACLK_200_RATIO << 12) \
+ | (ACLK_166_RATIO << 8) \
+ | (ACLK_133_RATIO << 4) \
+ | (ACLK_66_RATIO))
+
+/* CLK_DIV_TOP1 */
+#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
+#define ACLK_66_PRE_RATIO 0x1
+#define ACLK_400_ISP_RATIO 0x1
+#define ACLK_400_IOP_RATIO 0x1
+#define ACLK_300_GSCL_RATIO 0x2
+
+#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
+ | (ACLK_66_PRE_RATIO << 24) \
+ | (ACLK_400_ISP_RATIO << 20) \
+ | (ACLK_400_IOP_RATIO << 16) \
+ | (ACLK_300_GSCL_RATIO << 12))
+
+#define CLK_DIV_TOP2_VAL NOT_AVAILABLE
+
+/* PLL Lock Value Factor */
+#define PLL_LOCK_FACTOR 250
+#define PLL_X_LOCK_FACTOR 3000
+
+/* CLK_SRC_PERIC0 */
+#define PWM_SEL 6
+#define UART3_SEL 6
+#define UART2_SEL 6
+#define UART1_SEL 6
+#define UART0_SEL 6
+/* SRC_CLOCK = SCLK_MPLL */
+#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
+ | (UART3_SEL << 12) \
+ | (UART2_SEL << 8) \
+ | (UART1_SEL << 4) \
+ | (UART0_SEL))
+
+/* CLK_SRC_PERIC1 */
+/* SRC_CLOCK = SCLK_MPLL */
+#define SPI0_SEL 6
+#define SPI1_SEL 6
+#define SPI2_SEL 6
+#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \
+ | (SPI1_SEL << 20) \
+ | (SPI0_SEL << 16))
+
+/* CLK_DIV_PERIL0 */
+#define UART5_RATIO 7
+#define UART4_RATIO 7
+#define UART3_RATIO 7
+#define UART2_RATIO 7
+#define UART1_RATIO 7
+#define UART0_RATIO 7
+
+#define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \
+ | (UART2_RATIO << 8) \
+ | (UART1_RATIO << 4) \
+ | (UART0_RATIO))
+/* CLK_DIV_PERIC1 */
+#define SPI1_RATIO 0x7
+#define SPI0_RATIO 0xf
+#define SPI1_SUB_RATIO 0x0
+#define SPI0_SUB_RATIO 0x0
+#define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \
+ | ((SPI1_RATIO << 16) \
+ | (SPI0_SUB_RATIO << 8) \
+ | (SPI0_RATIO << 0)))
+
+/* CLK_DIV_PERIC2 */
+#define SPI2_RATIO 0xf
+#define SPI2_SUB_RATIO 0x0
+#define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \
+ | (SPI2_RATIO << 0))
+
+/* CLK_DIV_PERIC3 */
+#define PWM_RATIO 8
+#define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
+
+
+/* CLK_DIV_PERIC4 */
+#define CLK_DIV_PERIC4_VAL NOT_AVAILABLE
+
+/* CLK_SRC_DISP1_0 */
+#define CLK_SRC_DISP1_0_VAL 0x6
+#define CLK_DIV_DISP1_0_VAL NOT_AVAILABLE
+
+#define APLL_FOUT (1 << 0)
+#define KPLL_FOUT NOT_AVAILABLE
+
+#define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
+
+#else
+
+#define CPU_CONFIG_STATUS_OFFSET 0x80
+#define CPU_RST_FLAG_VAL 0xFCBA0D10
+#define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000
+
+/* APLL_CON1 */
+#define APLL_CON1_VAL (0x0020F300)
+
+/* MPLL_CON1 */
+#define MPLL_CON1_VAL (0x0020F300)
+
+
+/* CPLL_CON1 */
+#define CPLL_CON1_VAL 0x0020f300
+
+/* DPLL_CON1 */
+#define DPLL_CON1_VAL (0x0020F300)
+
+/* GPLL_CON1 */
+#define GPLL_CON1_VAL (NOT_AVAILABLE)
+
+
+/* EPLL_CON1, CON2 */
+#define EPLL_CON1_VAL 0x00000000
+#define EPLL_CON2_VAL 0x00000080
+
+/* VPLL_CON1, CON2 */
+#define VPLL_CON1_VAL 0x0020f300
+#define VPLL_CON2_VAL NOT_AVAILABLE
+
+/* RPLL_CON1, CON2 */
+#define RPLL_CON1_VAL 0x00000000
+#define RPLL_CON2_VAL 0x00000080
+
+/* BPLL_CON1 */
+#define BPLL_CON1_VAL 0x0020f300
+
+/* SPLL_CON1 */
+#define SPLL_CON1_VAL 0x0020f300
+
+/* IPLL_CON1 */
+#define IPLL_CON1_VAL 0x00000080
+
+/* KPLL_CON1 */
+#define KPLL_CON1_VAL 0x200000
+
+/* CLK_SRC_ISP */
+#define CLK_SRC_ISP_VAL 0x33366000
+#define CLK_DIV_ISP0_VAL 0x13131300
+#define CLK_DIV_ISP1_VAL 0xbb110202
+
+
+/* CLK_FSYS */
+#define CLK_SRC_FSYS0_VAL 0x33033300
+#define CLK_DIV_FSYS0_VAL 0x0
+#define CLK_DIV_FSYS1_VAL 0x04f13c4f
+#define CLK_DIV_FSYS2_VAL 0x041d0000
+
+/* CLK_SRC_CPU */
+/* 0 = MOUTAPLL, 1 = SCLKMPLL */
+#define MUX_HPM_SEL 1
+#define MUX_CPU_SEL 0
+#define MUX_APLL_SEL 1
+
+#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
+ | (MUX_CPU_SEL << 16) \
+ | (MUX_APLL_SEL))
+
+/* CLK_SRC_CDREX */
+#define CLK_SRC_CDREX_VAL 0x00000011
+
+/* CLK_DIV_CDREX */
+#define CLK_DIV_CDREX0_VAL 0x30010100
+#define CLK_DIV_CDREX1_VAL 0x300
+
+#define CLK_DIV_CDREX_VAL 0x17010100
+
+/* CLK_DIV_CPU0_VAL */
+#define CLK_DIV_CPU0_VAL 0x01440020
+
+/* CLK_SRC_TOP */
+#define CLK_SRC_TOP0_VAL 0x12221222
+#define CLK_SRC_TOP1_VAL 0x00100200
+#define CLK_SRC_TOP2_VAL 0x11101000
+#define CLK_SRC_TOP3_VAL 0x11111111
+#define CLK_SRC_TOP4_VAL 0x11110111
+#define CLK_SRC_TOP5_VAL 0x11111101
+#define CLK_SRC_TOP6_VAL 0x11110111
+#define CLK_SRC_TOP7_VAL 0x00022200
+
+/* CLK_DIV_TOP */
+#define CLK_DIV_TOP0_VAL 0x23712311
+#define CLK_DIV_TOP1_VAL 0x13100B00
+#define CLK_DIV_TOP2_VAL 0x11101100
+
+/* PLL Lock Value Factor */
+#define PLL_LOCK_FACTOR 200
+#define PLL_X_LOCK_FACTOR 3000
+
+/* CLK_SRC_PERIC0 */
+#define SPDIF_SEL 1
+#define PWM_SEL 3
+#define UART4_SEL 3
+#define UART3_SEL 3
+#define UART2_SEL 3
+#define UART1_SEL 3
+#define UART0_SEL 3
+/* SRC_CLOCK = SCLK_RPLL */
+#define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \
+ | (PWM_SEL << 24) \
+ | (UART4_SEL << 20) \
+ | (UART3_SEL << 16) \
+ | (UART2_SEL << 12) \
+ | (UART1_SEL << 8) \
+ | (UART0_SEL << 4))
+
+/* CLK_SRC_PERIC1 */
+/* SRC_CLOCK = SCLK_EPLL */
+#define SPI0_SEL 6
+#define SPI1_SEL 6
+#define SPI2_SEL 6
+#define AUDIO0_SEL 6
+#define AUDIO1_SEL 6
+#define AUDIO2_SEL 6
+#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \
+ | (SPI1_SEL << 24) \
+ | (SPI0_SEL << 20) \
+ | (AUDIO2_SEL << 16) \
+ | (AUDIO2_SEL << 12) \
+ | (AUDIO2_SEL << 8))
+
+/* CLK_DIV_PERIC0 */
+#define PWM_RATIO 8
+#define UART4_RATIO 9
+#define UART3_RATIO 9
+#define UART2_RATIO 9
+#define UART1_RATIO 9
+#define UART0_RATIO 9
+
+#define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \
+ | (UART4_RATIO << 24) \
+ | (UART3_RATIO << 20) \
+ | (UART2_RATIO << 16) \
+ | (UART1_RATIO << 12) \
+ | (UART0_RATIO << 8))
+/* CLK_DIV_PERIC1 */
+#define SPI2_RATIO 0x1
+#define SPI1_RATIO 0x1
+#define SPI0_RATIO 0x1
+#define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \
+ | (SPI1_RATIO << 24) \
+ | (SPI0_RATIO << 20))
+
+/* CLK_DIV_PERIC2 */
+#define PCM2_RATIO 0x3
+#define PCM1_RATIO 0x3
+#define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \
+ | (PCM1_RATIO << 16))
+
+/* CLK_DIV_PERIC3 */
+#define AUDIO2_RATIO 0x5
+#define AUDIO1_RATIO 0x5
+#define AUDIO0_RATIO 0x5
+#define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \
+ | (AUDIO1_RATIO << 24) \
+ | (AUDIO0_RATIO << 20))
+
+/* CLK_DIV_PERIC4 */
+#define SPI2_PRE_RATIO 0x2
+#define SPI1_PRE_RATIO 0x2
+#define SPI0_PRE_RATIO 0x2
+#define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \
+ | (SPI1_PRE_RATIO << 16) \
+ | (SPI0_PRE_RATIO << 8))
+
+/* CLK_SRC_DISP1_0 */
+#define CLK_SRC_DISP1_0_VAL 0x10666600
+#define CLK_DIV_DISP1_0_VAL 0x01050211
+
+#define APLL_FOUT (1 << 0)
+#define KPLL_FOUT (1 << 0)
+
+#define CLK_DIV_CPERI1_VAL 0x3f3f0000
+#endif
+
+struct mem_timings;
+
+/* Errors that we can encourter in low-level setup */
+enum {
+ SETUP_ERR_OK,
+ SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
+ SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
+};
+
+/*
+ * Memory variant specific initialization code for DDR3
+ *
+ * @param mem Memory timings for this memory type.
+ * @param reset Reset DDR PHY during initialization.
+ * @return 0 if ok, SETUP_ERR_... if there is a problem
+ */
+int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset);
+
+/* Memory variant specific initialization code for LPDDR3 */
+void lpddr3_mem_ctrl_init(void);
+
+/*
+ * Configure ZQ I/O interface
+ *
+ * @param mem Memory timings for this memory type.
+ * @param phy0_con16 Register address for dmc_phy0->phy_con16
+ * @param phy1_con16 Register address for dmc_phy1->phy_con16
+ * @param phy0_con17 Register address for dmc_phy0->phy_con17
+ * @param phy1_con17 Register address for dmc_phy1->phy_con17
+ * @return 0 if ok, -1 on error
+ */
+int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16,
+ uint32_t *phy1_con16, uint32_t *phy0_con17,
+ uint32_t *phy1_con17);
+/*
+ * Send NOP and MRS/EMRS Direct commands
+ *
+ * @param mem Memory timings for this memory type.
+ * @param directcmd Register address for dmc_phy->directcmd
+ */
+void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd);
+
+/*
+ * Send PALL Direct commands
+ *
+ * @param mem Memory timings for this memory type.
+ * @param directcmd Register address for dmc_phy->directcmd
+ */
+void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd);
+
+/*
+ * Reset the DLL. This function is common between DDR3 and LPDDR2.
+ * However, the reset value is different. So we are passing a flag
+ * ddr_mode to distinguish between LPDDR2 and DDR3.
+ *
+ * @param phycontrol0 Register address for dmc_phy->phycontrol0
+ * @param ddr_mode Type of DDR memory
+ */
+void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode);
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * MyungJoo Ham <myungjoo.ham@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_ADC_H_
+#define __ASM_ARM_ARCH_ADC_H_
+
+#ifndef __ASSEMBLY__
+struct s5p_adc {
+ unsigned int adccon;
+ unsigned int adctsc;
+ unsigned int adcdly;
+ unsigned int adcdat0;
+ unsigned int adcdat1;
+ unsigned int adcupdn;
+ unsigned int adcclrint;
+ unsigned int adcmux;
+ unsigned int adcclrintpndnup;
+};
+#endif
+
+#endif /* __ASM_ARM_ARCH_ADC_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2013 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _EXYNOS_BOARD_H
+#define _EXYNOS_BOARD_H
+
+/*
+ * Exynos baord specific changes for
+ * board_init
+ */
+int exynos_init(void);
+
+/*
+ * Exynos board specific changes for
+ * board_early_init_f
+ */
+int exynos_early_init_f(void);
+
+/*
+ * Exynos board specific changes for
+ * board_power_init
+ */
+int exynos_power_init(void);
+
+#endif /* EXYNOS_BOARD_H */
--- /dev/null
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_CLK_H_
+#define __ASM_ARM_ARCH_CLK_H_
+
+#define APLL 0
+#define MPLL 1
+#define EPLL 2
+#define HPLL 3
+#define VPLL 4
+#define BPLL 5
+#define RPLL 6
+#define SPLL 7
+#define CPLL 8
+#define DPLL 9
+#define IPLL 10
+
+#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8))
+#define MASK_RATIO(x) (0xf << (x << 4))
+#define SET_PRE_RATIO(x, y) ((y & 0xff) << ((x << 4) + 8))
+#define SET_RATIO(x, y) ((y & 0xf) << (x << 4))
+
+enum pll_src_bit {
+ EXYNOS_SRC_MPLL = 6,
+ EXYNOS_SRC_EPLL,
+ EXYNOS_SRC_VPLL,
+ EXYNOS542X_SRC_MPLL = 3,
+ EXYNOS542X_SRC_SPLL,
+ EXYNOS542X_SRC_EPLL = 6,
+ EXYNOS542X_SRC_RPLL,
+};
+
+unsigned long get_pll_clk(int pllreg);
+unsigned long get_arm_clk(void);
+unsigned long get_i2c_clk(void);
+unsigned long get_pwm_clk(void);
+unsigned long get_uart_clk(int dev_index);
+unsigned long get_mmc_clk(int dev_index);
+void set_mmc_clk(int dev_index, unsigned int div);
+unsigned long get_lcd_clk(void);
+void set_lcd_clk(void);
+void set_mipi_clk(void);
+int set_i2s_clk_source(unsigned int i2s_id);
+int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
+ unsigned int i2s_id);
+int set_epll_clk(unsigned long rate);
+int set_spi_clk(int periph_id, unsigned int rate);
+
+/**
+ * get the clk frequency of the required peripheral
+ *
+ * @param peripheral Peripheral id
+ *
+ * @return frequency of the peripheral clk
+ */
+unsigned long clock_get_periph_rate(int peripheral);
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_CLOCK_H_
+#define __ASM_ARM_ARCH_CLOCK_H_
+
+#ifndef __ASSEMBLY__
+struct exynos4_clock {
+ unsigned char res1[0x4200];
+ unsigned int src_leftbus;
+ unsigned char res2[0x1fc];
+ unsigned int mux_stat_leftbus;
+ unsigned char res4[0xfc];
+ unsigned int div_leftbus;
+ unsigned char res5[0xfc];
+ unsigned int div_stat_leftbus;
+ unsigned char res6[0x1fc];
+ unsigned int gate_ip_leftbus;
+ unsigned char res7[0x1fc];
+ unsigned int clkout_leftbus;
+ unsigned int clkout_leftbus_div_stat;
+ unsigned char res8[0x37f8];
+ unsigned int src_rightbus;
+ unsigned char res9[0x1fc];
+ unsigned int mux_stat_rightbus;
+ unsigned char res10[0xfc];
+ unsigned int div_rightbus;
+ unsigned char res11[0xfc];
+ unsigned int div_stat_rightbus;
+ unsigned char res12[0x1fc];
+ unsigned int gate_ip_rightbus;
+ unsigned char res13[0x1fc];
+ unsigned int clkout_rightbus;
+ unsigned int clkout_rightbus_div_stat;
+ unsigned char res14[0x3608];
+ unsigned int epll_lock;
+ unsigned char res15[0xc];
+ unsigned int vpll_lock;
+ unsigned char res16[0xec];
+ unsigned int epll_con0;
+ unsigned int epll_con1;
+ unsigned char res17[0x8];
+ unsigned int vpll_con0;
+ unsigned int vpll_con1;
+ unsigned char res18[0xe8];
+ unsigned int src_top0;
+ unsigned int src_top1;
+ unsigned char res19[0x8];
+ unsigned int src_cam;
+ unsigned int src_tv;
+ unsigned int src_mfc;
+ unsigned int src_g3d;
+ unsigned int src_image;
+ unsigned int src_lcd0;
+ unsigned int src_lcd1;
+ unsigned int src_maudio;
+ unsigned int src_fsys;
+ unsigned char res20[0xc];
+ unsigned int src_peril0;
+ unsigned int src_peril1;
+ unsigned char res21[0xb8];
+ unsigned int src_mask_top;
+ unsigned char res22[0xc];
+ unsigned int src_mask_cam;
+ unsigned int src_mask_tv;
+ unsigned char res23[0xc];
+ unsigned int src_mask_lcd0;
+ unsigned int src_mask_lcd1;
+ unsigned int src_mask_maudio;
+ unsigned int src_mask_fsys;
+ unsigned char res24[0xc];
+ unsigned int src_mask_peril0;
+ unsigned int src_mask_peril1;
+ unsigned char res25[0xb8];
+ unsigned int mux_stat_top;
+ unsigned char res26[0x14];
+ unsigned int mux_stat_mfc;
+ unsigned int mux_stat_g3d;
+ unsigned int mux_stat_image;
+ unsigned char res27[0xdc];
+ unsigned int div_top;
+ unsigned char res28[0xc];
+ unsigned int div_cam;
+ unsigned int div_tv;
+ unsigned int div_mfc;
+ unsigned int div_g3d;
+ unsigned int div_image;
+ unsigned int div_lcd0;
+ unsigned int div_lcd1;
+ unsigned int div_maudio;
+ unsigned int div_fsys0;
+ unsigned int div_fsys1;
+ unsigned int div_fsys2;
+ unsigned int div_fsys3;
+ unsigned int div_peril0;
+ unsigned int div_peril1;
+ unsigned int div_peril2;
+ unsigned int div_peril3;
+ unsigned int div_peril4;
+ unsigned int div_peril5;
+ unsigned char res29[0x18];
+ unsigned int div2_ratio;
+ unsigned char res30[0x8c];
+ unsigned int div_stat_top;
+ unsigned char res31[0xc];
+ unsigned int div_stat_cam;
+ unsigned int div_stat_tv;
+ unsigned int div_stat_mfc;
+ unsigned int div_stat_g3d;
+ unsigned int div_stat_image;
+ unsigned int div_stat_lcd0;
+ unsigned int div_stat_lcd1;
+ unsigned int div_stat_maudio;
+ unsigned int div_stat_fsys0;
+ unsigned int div_stat_fsys1;
+ unsigned int div_stat_fsys2;
+ unsigned int div_stat_fsys3;
+ unsigned int div_stat_peril0;
+ unsigned int div_stat_peril1;
+ unsigned int div_stat_peril2;
+ unsigned int div_stat_peril3;
+ unsigned int div_stat_peril4;
+ unsigned int div_stat_peril5;
+ unsigned char res32[0x18];
+ unsigned int div2_stat;
+ unsigned char res33[0x29c];
+ unsigned int gate_ip_cam;
+ unsigned int gate_ip_tv;
+ unsigned int gate_ip_mfc;
+ unsigned int gate_ip_g3d;
+ unsigned int gate_ip_image;
+ unsigned int gate_ip_lcd0;
+ unsigned int gate_ip_lcd1;
+ unsigned char res34[0x4];
+ unsigned int gate_ip_fsys;
+ unsigned char res35[0x8];
+ unsigned int gate_ip_gps;
+ unsigned int gate_ip_peril;
+ unsigned char res36[0xc];
+ unsigned int gate_ip_perir;
+ unsigned char res37[0xc];
+ unsigned int gate_block;
+ unsigned char res38[0x8c];
+ unsigned int clkout_cmu_top;
+ unsigned int clkout_cmu_top_div_stat;
+ unsigned char res39[0x37f8];
+ unsigned int src_dmc;
+ unsigned char res40[0xfc];
+ unsigned int src_mask_dmc;
+ unsigned char res41[0xfc];
+ unsigned int mux_stat_dmc;
+ unsigned char res42[0xfc];
+ unsigned int div_dmc0;
+ unsigned int div_dmc1;
+ unsigned char res43[0xf8];
+ unsigned int div_stat_dmc0;
+ unsigned int div_stat_dmc1;
+ unsigned char res44[0x2f8];
+ unsigned int gate_ip_dmc;
+ unsigned char res45[0xfc];
+ unsigned int clkout_cmu_dmc;
+ unsigned int clkout_cmu_dmc_div_stat;
+ unsigned char res46[0x5f8];
+ unsigned int dcgidx_map0;
+ unsigned int dcgidx_map1;
+ unsigned int dcgidx_map2;
+ unsigned char res47[0x14];
+ unsigned int dcgperf_map0;
+ unsigned int dcgperf_map1;
+ unsigned char res48[0x18];
+ unsigned int dvcidx_map;
+ unsigned char res49[0x1c];
+ unsigned int freq_cpu;
+ unsigned int freq_dpm;
+ unsigned char res50[0x18];
+ unsigned int dvsemclk_en;
+ unsigned int maxperf;
+ unsigned char res51[0x2f78];
+ unsigned int apll_lock;
+ unsigned char res52[0x4];
+ unsigned int mpll_lock;
+ unsigned char res53[0xf4];
+ unsigned int apll_con0;
+ unsigned int apll_con1;
+ unsigned int mpll_con0;
+ unsigned int mpll_con1;
+ unsigned char res54[0xf0];
+ unsigned int src_cpu;
+ unsigned char res55[0x1fc];
+ unsigned int mux_stat_cpu;
+ unsigned char res56[0xfc];
+ unsigned int div_cpu0;
+ unsigned int div_cpu1;
+ unsigned char res57[0xf8];
+ unsigned int div_stat_cpu0;
+ unsigned int div_stat_cpu1;
+ unsigned char res58[0x3f8];
+ unsigned int clkout_cmu_cpu;
+ unsigned int clkout_cmu_cpu_div_stat;
+ unsigned char res59[0x5f8];
+ unsigned int armclk_stopctrl;
+ unsigned int atclk_stopctrl;
+ unsigned char res60[0x8];
+ unsigned int parityfail_status;
+ unsigned int parityfail_clear;
+ unsigned char res61[0xe8];
+ unsigned int apll_con0_l8;
+ unsigned int apll_con0_l7;
+ unsigned int apll_con0_l6;
+ unsigned int apll_con0_l5;
+ unsigned int apll_con0_l4;
+ unsigned int apll_con0_l3;
+ unsigned int apll_con0_l2;
+ unsigned int apll_con0_l1;
+ unsigned int iem_control;
+ unsigned char res62[0xdc];
+ unsigned int apll_con1_l8;
+ unsigned int apll_con1_l7;
+ unsigned int apll_con1_l6;
+ unsigned int apll_con1_l5;
+ unsigned int apll_con1_l4;
+ unsigned int apll_con1_l3;
+ unsigned int apll_con1_l2;
+ unsigned int apll_con1_l1;
+ unsigned char res63[0xe0];
+ unsigned int div_iem_l8;
+ unsigned int div_iem_l7;
+ unsigned int div_iem_l6;
+ unsigned int div_iem_l5;
+ unsigned int div_iem_l4;
+ unsigned int div_iem_l3;
+ unsigned int div_iem_l2;
+ unsigned int div_iem_l1;
+};
+
+struct exynos4x12_clock {
+ unsigned char res1[0x4200];
+ unsigned int src_leftbus;
+ unsigned char res2[0x1fc];
+ unsigned int mux_stat_leftbus;
+ unsigned char res3[0xfc];
+ unsigned int div_leftbus;
+ unsigned char res4[0xfc];
+ unsigned int div_stat_leftbus;
+ unsigned char res5[0x1fc];
+ unsigned int gate_ip_leftbus;
+ unsigned char res6[0x12c];
+ unsigned int gate_ip_image;
+ unsigned char res7[0xcc];
+ unsigned int clkout_leftbus;
+ unsigned int clkout_leftbus_div_stat;
+ unsigned char res8[0x37f8];
+ unsigned int src_rightbus;
+ unsigned char res9[0x1fc];
+ unsigned int mux_stat_rightbus;
+ unsigned char res10[0xfc];
+ unsigned int div_rightbus;
+ unsigned char res11[0xfc];
+ unsigned int div_stat_rightbus;
+ unsigned char res12[0x1fc];
+ unsigned int gate_ip_rightbus;
+ unsigned char res13[0x15c];
+ unsigned int gate_ip_perir;
+ unsigned char res14[0x9c];
+ unsigned int clkout_rightbus;
+ unsigned int clkout_rightbus_div_stat;
+ unsigned char res15[0x3608];
+ unsigned int epll_lock;
+ unsigned char res16[0xc];
+ unsigned int vpll_lock;
+ unsigned char res17[0xec];
+ unsigned int epll_con0;
+ unsigned int epll_con1;
+ unsigned int epll_con2;
+ unsigned char res18[0x4];
+ unsigned int vpll_con0;
+ unsigned int vpll_con1;
+ unsigned int vpll_con2;
+ unsigned char res19[0xe4];
+ unsigned int src_top0;
+ unsigned int src_top1;
+ unsigned char res20[0x8];
+ unsigned int src_cam;
+ unsigned int src_tv;
+ unsigned int src_mfc;
+ unsigned int src_g3d;
+ unsigned char res21[0x4];
+ unsigned int src_lcd;
+ unsigned int src_isp;
+ unsigned int src_maudio;
+ unsigned int src_fsys;
+ unsigned char res22[0xc];
+ unsigned int src_peril0;
+ unsigned int src_peril1;
+ unsigned int src_cam1;
+ unsigned char res23[0xb4];
+ unsigned int src_mask_top;
+ unsigned char res24[0xc];
+ unsigned int src_mask_cam;
+ unsigned int src_mask_tv;
+ unsigned char res25[0xc];
+ unsigned int src_mask_lcd;
+ unsigned int src_mask_isp;
+ unsigned int src_mask_maudio;
+ unsigned int src_mask_fsys;
+ unsigned char res26[0xc];
+ unsigned int src_mask_peril0;
+ unsigned int src_mask_peril1;
+ unsigned char res27[0xb8];
+ unsigned int mux_stat_top0;
+ unsigned int mux_stat_top1;
+ unsigned char res28[0x10];
+ unsigned int mux_stat_mfc;
+ unsigned int mux_stat_g3d;
+ unsigned char res29[0x28];
+ unsigned int mux_stat_cam1;
+ unsigned char res30[0xb4];
+ unsigned int div_top;
+ unsigned char res31[0xc];
+ unsigned int div_cam;
+ unsigned int div_tv;
+ unsigned int div_mfc;
+ unsigned int div_g3d;
+ unsigned char res32[0x4];
+ unsigned int div_lcd;
+ unsigned int div_isp;
+ unsigned int div_maudio;
+ unsigned int div_fsys0;
+ unsigned int div_fsys1;
+ unsigned int div_fsys2;
+ unsigned int div_fsys3;
+ unsigned int div_peril0;
+ unsigned int div_peril1;
+ unsigned int div_peril2;
+ unsigned int div_peril3;
+ unsigned int div_peril4;
+ unsigned int div_peril5;
+ unsigned int div_cam1;
+ unsigned char res33[0x14];
+ unsigned int div2_ratio;
+ unsigned char res34[0x8c];
+ unsigned int div_stat_top;
+ unsigned char res35[0xc];
+ unsigned int div_stat_cam;
+ unsigned int div_stat_tv;
+ unsigned int div_stat_mfc;
+ unsigned int div_stat_g3d;
+ unsigned char res36[0x4];
+ unsigned int div_stat_lcd;
+ unsigned int div_stat_isp;
+ unsigned int div_stat_maudio;
+ unsigned int div_stat_fsys0;
+ unsigned int div_stat_fsys1;
+ unsigned int div_stat_fsys2;
+ unsigned int div_stat_fsys3;
+ unsigned int div_stat_peril0;
+ unsigned int div_stat_peril1;
+ unsigned int div_stat_peril2;
+ unsigned int div_stat_peril3;
+ unsigned int div_stat_peril4;
+ unsigned int div_stat_peril5;
+ unsigned int div_stat_cam1;
+ unsigned char res37[0x14];
+ unsigned int div2_stat;
+ unsigned char res38[0x29c];
+ unsigned int gate_ip_cam;
+ unsigned int gate_ip_tv;
+ unsigned int gate_ip_mfc;
+ unsigned int gate_ip_g3d;
+ unsigned char res39[0x4];
+ unsigned int gate_ip_lcd;
+ unsigned int gate_ip_isp;
+ unsigned char res40[0x4];
+ unsigned int gate_ip_fsys;
+ unsigned char res41[0x8];
+ unsigned int gate_ip_gps;
+ unsigned int gate_ip_peril;
+ unsigned char res42[0xc];
+ unsigned char res43[0x4];
+ unsigned char res44[0xc];
+ unsigned int gate_block;
+ unsigned char res45[0x8c];
+ unsigned int clkout_cmu_top;
+ unsigned int clkout_cmu_top_div_stat;
+ unsigned char res46[0x3600];
+ unsigned int mpll_lock;
+ unsigned char res47[0xfc];
+ unsigned int mpll_con0;
+ unsigned int mpll_con1;
+ unsigned char res48[0xf0];
+ unsigned int src_dmc;
+ unsigned char res49[0xfc];
+ unsigned int src_mask_dmc;
+ unsigned char res50[0xfc];
+ unsigned int mux_stat_dmc;
+ unsigned char res51[0xfc];
+ unsigned int div_dmc0;
+ unsigned int div_dmc1;
+ unsigned char res52[0xf8];
+ unsigned int div_stat_dmc0;
+ unsigned int div_stat_dmc1;
+ unsigned char res53[0xf8];
+ unsigned int gate_bus_dmc0;
+ unsigned int gate_bus_dmc1;
+ unsigned char res54[0x1f8];
+ unsigned int gate_ip_dmc0;
+ unsigned int gate_ip_dmc1;
+ unsigned char res55[0xf8];
+ unsigned int clkout_cmu_dmc;
+ unsigned int clkout_cmu_dmc_div_stat;
+ unsigned char res56[0x5f8];
+ unsigned int dcgidx_map0;
+ unsigned int dcgidx_map1;
+ unsigned int dcgidx_map2;
+ unsigned char res57[0x14];
+ unsigned int dcgperf_map0;
+ unsigned int dcgperf_map1;
+ unsigned char res58[0x18];
+ unsigned int dvcidx_map;
+ unsigned char res59[0x1c];
+ unsigned int freq_cpu;
+ unsigned int freq_dpm;
+ unsigned char res60[0x18];
+ unsigned int dvsemclk_en;
+ unsigned int maxperf;
+ unsigned char res61[0x8];
+ unsigned int dmc_freq_ctrl;
+ unsigned int dmc_pause_ctrl;
+ unsigned int dddrphy_lock_ctrl;
+ unsigned int c2c_state;
+ unsigned char res62[0x2f60];
+ unsigned int apll_lock;
+ unsigned char res63[0x8];
+ unsigned char res64[0xf4];
+ unsigned int apll_con0;
+ unsigned int apll_con1;
+ unsigned char res65[0xf8];
+ unsigned int src_cpu;
+ unsigned char res66[0x1fc];
+ unsigned int mux_stat_cpu;
+ unsigned char res67[0xfc];
+ unsigned int div_cpu0;
+ unsigned int div_cpu1;
+ unsigned char res68[0xf8];
+ unsigned int div_stat_cpu0;
+ unsigned int div_stat_cpu1;
+ unsigned char res69[0x2f8];
+ unsigned int clk_gate_ip_cpu;
+ unsigned char res70[0xfc];
+ unsigned int clkout_cmu_cpu;
+ unsigned int clkout_cmu_cpu_div_stat;
+ unsigned char res71[0x5f8];
+ unsigned int armclk_stopctrl;
+ unsigned int atclk_stopctrl;
+ unsigned char res72[0x10];
+ unsigned char res73[0x8];
+ unsigned int pwr_ctrl;
+ unsigned int pwr_ctrl2;
+ unsigned char res74[0xd8];
+ unsigned int apll_con0_l8;
+ unsigned int apll_con0_l7;
+ unsigned int apll_con0_l6;
+ unsigned int apll_con0_l5;
+ unsigned int apll_con0_l4;
+ unsigned int apll_con0_l3;
+ unsigned int apll_con0_l2;
+ unsigned int apll_con0_l1;
+ unsigned int iem_control;
+ unsigned char res75[0xdc];
+ unsigned int apll_con1_l8;
+ unsigned int apll_con1_l7;
+ unsigned int apll_con1_l6;
+ unsigned int apll_con1_l5;
+ unsigned int apll_con1_l4;
+ unsigned int apll_con1_l3;
+ unsigned int apll_con1_l2;
+ unsigned int apll_con1_l1;
+ unsigned char res76[0xe0];
+ unsigned int div_iem_l8;
+ unsigned int div_iem_l7;
+ unsigned int div_iem_l6;
+ unsigned int div_iem_l5;
+ unsigned int div_iem_l4;
+ unsigned int div_iem_l3;
+ unsigned int div_iem_l2;
+ unsigned int div_iem_l1;
+ unsigned char res77[0xe0];
+ unsigned int l2_status;
+ unsigned char res78[0xc];
+ unsigned int cpu_status;
+ unsigned char res79[0xc];
+ unsigned int ptm_status;
+ unsigned char res80[0x2edc];
+ unsigned int div_isp0;
+ unsigned int div_isp1;
+ unsigned char res81[0xf8];
+ unsigned int div_stat_isp0;
+ unsigned int div_stat_isp1;
+ unsigned char res82[0x3f8];
+ unsigned int gate_ip_isp0;
+ unsigned int gate_ip_isp1;
+ unsigned char res83[0x1f8];
+ unsigned int clkout_cmu_isp;
+ unsigned int clkout_cmu_ispd_div_stat;
+ unsigned char res84[0xf8];
+ unsigned int cmu_isp_spar0;
+ unsigned int cmu_isp_spar1;
+ unsigned int cmu_isp_spar2;
+ unsigned int cmu_isp_spar3;
+};
+
+struct exynos5_clock {
+ unsigned int apll_lock;
+ unsigned char res1[0xfc];
+ unsigned int apll_con0;
+ unsigned int apll_con1;
+ unsigned char res2[0xf8];
+ unsigned int src_cpu;
+ unsigned char res3[0x1fc];
+ unsigned int mux_stat_cpu;
+ unsigned char res4[0xfc];
+ unsigned int div_cpu0;
+ unsigned int div_cpu1;
+ unsigned char res5[0xf8];
+ unsigned int div_stat_cpu0;
+ unsigned int div_stat_cpu1;
+ unsigned char res6[0x1f8];
+ unsigned int gate_sclk_cpu;
+ unsigned char res7[0x1fc];
+ unsigned int clkout_cmu_cpu;
+ unsigned int clkout_cmu_cpu_div_stat;
+ unsigned char res8[0x5f8];
+ unsigned int armclk_stopctrl;
+ unsigned char res9[0x0c];
+ unsigned int parityfail_status;
+ unsigned int parityfail_clear;
+ unsigned char res10[0x8];
+ unsigned int pwr_ctrl;
+ unsigned int pwr_ctr2;
+ unsigned char res11[0xd8];
+ unsigned int apll_con0_l8;
+ unsigned int apll_con0_l7;
+ unsigned int apll_con0_l6;
+ unsigned int apll_con0_l5;
+ unsigned int apll_con0_l4;
+ unsigned int apll_con0_l3;
+ unsigned int apll_con0_l2;
+ unsigned int apll_con0_l1;
+ unsigned int iem_control;
+ unsigned char res12[0xdc];
+ unsigned int apll_con1_l8;
+ unsigned int apll_con1_l7;
+ unsigned int apll_con1_l6;
+ unsigned int apll_con1_l5;
+ unsigned int apll_con1_l4;
+ unsigned int apll_con1_l3;
+ unsigned int apll_con1_l2;
+ unsigned int apll_con1_l1;
+ unsigned char res13[0xe0];
+ unsigned int div_iem_l8;
+ unsigned int div_iem_l7;
+ unsigned int div_iem_l6;
+ unsigned int div_iem_l5;
+ unsigned int div_iem_l4;
+ unsigned int div_iem_l3;
+ unsigned int div_iem_l2;
+ unsigned int div_iem_l1;
+ unsigned char res14[0x2ce0];
+ unsigned int mpll_lock;
+ unsigned char res15[0xfc];
+ unsigned int mpll_con0;
+ unsigned int mpll_con1;
+ unsigned char res16[0xf8];
+ unsigned int src_core0;
+ unsigned int src_core1;
+ unsigned char res17[0xf8];
+ unsigned int src_mask_core;
+ unsigned char res18[0x100];
+ unsigned int mux_stat_core1;
+ unsigned char res19[0xf8];
+ unsigned int div_core0;
+ unsigned int div_core1;
+ unsigned int div_sysrgt;
+ unsigned char res20[0xf4];
+ unsigned int div_stat_core0;
+ unsigned int div_stat_core1;
+ unsigned int div_stat_sysrgt;
+ unsigned char res21[0x2f4];
+ unsigned int gate_ip_core;
+ unsigned int gate_ip_sysrgt;
+ unsigned char res22[0x8];
+ unsigned int c2c_monitor;
+ unsigned char res23[0xec];
+ unsigned int clkout_cmu_core;
+ unsigned int clkout_cmu_core_div_stat;
+ unsigned char res24[0x5f8];
+ unsigned int dcgidx_map0;
+ unsigned int dcgidx_map1;
+ unsigned int dcgidx_map2;
+ unsigned char res25[0x14];
+ unsigned int dcgperf_map0;
+ unsigned int dcgperf_map1;
+ unsigned char res26[0x18];
+ unsigned int dvcidx_map;
+ unsigned char res27[0x1c];
+ unsigned int freq_cpu;
+ unsigned int freq_dpm;
+ unsigned char res28[0x18];
+ unsigned int dvsemclk_en;
+ unsigned int maxperf;
+ unsigned char res29[0xf78];
+ unsigned int c2c_config;
+ unsigned char res30[0x24fc];
+ unsigned int div_acp;
+ unsigned char res31[0xfc];
+ unsigned int div_stat_acp;
+ unsigned char res32[0x1fc];
+ unsigned int gate_ip_acp;
+ unsigned char res33[0xfc];
+ unsigned int div_syslft;
+ unsigned char res34[0xc];
+ unsigned int div_stat_syslft;
+ unsigned char res35[0x1c];
+ unsigned int gate_ip_syslft;
+ unsigned char res36[0xcc];
+ unsigned int clkout_cmu_acp;
+ unsigned int clkout_cmu_acp_div_stat;
+ unsigned char res37[0x8];
+ unsigned int ufmc_config;
+ unsigned char res38[0x38ec];
+ unsigned int div_isp0;
+ unsigned int div_isp1;
+ unsigned int div_isp2;
+ unsigned char res39[0xf4];
+ unsigned int div_stat_isp0;
+ unsigned int div_stat_isp1;
+ unsigned int div_stat_isp2;
+ unsigned char res40[0x3f4];
+ unsigned int gate_ip_isp0;
+ unsigned int gate_ip_isp1;
+ unsigned char res41[0xf8];
+ unsigned int gate_sclk_isp;
+ unsigned char res42[0xc];
+ unsigned int mcuisp_pwr_ctrl;
+ unsigned char res43[0xec];
+ unsigned int clkout_cmu_isp;
+ unsigned int clkout_cmu_isp_div_stat;
+ unsigned char res44[0x3618];
+ unsigned int cpll_lock;
+ unsigned char res45[0xc];
+ unsigned int epll_lock;
+ unsigned char res46[0xc];
+ unsigned int vpll_lock;
+ unsigned char res47[0xc];
+ unsigned int gpll_lock;
+ unsigned char res48[0xcc];
+ unsigned int cpll_con0;
+ unsigned int cpll_con1;
+ unsigned char res49[0x8];
+ unsigned int epll_con0;
+ unsigned int epll_con1;
+ unsigned int epll_con2;
+ unsigned char res50[0x4];
+ unsigned int vpll_con0;
+ unsigned int vpll_con1;
+ unsigned int vpll_con2;
+ unsigned char res51[0x4];
+ unsigned int gpll_con0;
+ unsigned int gpll_con1;
+ unsigned char res52[0xb8];
+ unsigned int src_top0;
+ unsigned int src_top1;
+ unsigned int src_top2;
+ unsigned int src_top3;
+ unsigned int src_gscl;
+ unsigned char res53[0x8];
+ unsigned int src_disp1_0;
+ unsigned char res54[0x10];
+ unsigned int src_mau;
+ unsigned int src_fsys;
+ unsigned int src_gen;
+ unsigned char res55[0x4];
+ unsigned int src_peric0;
+ unsigned int src_peric1;
+ unsigned char res56[0x18];
+ unsigned int sclk_src_isp;
+ unsigned char res57[0x9c];
+ unsigned int src_mask_top;
+ unsigned char res58[0xc];
+ unsigned int src_mask_gscl;
+ unsigned char res59[0x8];
+ unsigned int src_mask_disp1_0;
+ unsigned char res60[0x4];
+ unsigned int src_mask_mau;
+ unsigned char res61[0x8];
+ unsigned int src_mask_fsys;
+ unsigned int src_mask_gen;
+ unsigned char res62[0x8];
+ unsigned int src_mask_peric0;
+ unsigned int src_mask_peric1;
+ unsigned char res63[0x18];
+ unsigned int src_mask_isp;
+ unsigned char res67[0x9c];
+ unsigned int mux_stat_top0;
+ unsigned int mux_stat_top1;
+ unsigned int mux_stat_top2;
+ unsigned int mux_stat_top3;
+ unsigned char res68[0xf0];
+ unsigned int div_top0;
+ unsigned int div_top1;
+ unsigned char res69[0x8];
+ unsigned int div_gscl;
+ unsigned char res70[0x8];
+ unsigned int div_disp1_0;
+ unsigned char res71[0xc];
+ unsigned int div_gen;
+ unsigned char res72[0x4];
+ unsigned int div_mau;
+ unsigned int div_fsys0;
+ unsigned int div_fsys1;
+ unsigned int div_fsys2;
+ unsigned char res73[0x4];
+ unsigned int div_peric0;
+ unsigned int div_peric1;
+ unsigned int div_peric2;
+ unsigned int div_peric3;
+ unsigned int div_peric4;
+ unsigned int div_peric5;
+ unsigned char res74[0x10];
+ unsigned int sclk_div_isp;
+ unsigned char res75[0xc];
+ unsigned int div2_ratio0;
+ unsigned int div2_ratio1;
+ unsigned char res76[0x8];
+ unsigned int div4_ratio;
+ unsigned char res77[0x6c];
+ unsigned int div_stat_top0;
+ unsigned int div_stat_top1;
+ unsigned char res78[0x8];
+ unsigned int div_stat_gscl;
+ unsigned char res79[0x8];
+ unsigned int div_stat_disp1_0;
+ unsigned char res80[0xc];
+ unsigned int div_stat_gen;
+ unsigned char res81[0x4];
+ unsigned int div_stat_mau;
+ unsigned int div_stat_fsys0;
+ unsigned int div_stat_fsys1;
+ unsigned int div_stat_fsys2;
+ unsigned char res82[0x4];
+ unsigned int div_stat_peric0;
+ unsigned int div_stat_peric1;
+ unsigned int div_stat_peric2;
+ unsigned int div_stat_peric3;
+ unsigned int div_stat_peric4;
+ unsigned int div_stat_peric5;
+ unsigned char res83[0x10];
+ unsigned int sclk_div_stat_isp;
+ unsigned char res84[0xc];
+ unsigned int div2_stat0;
+ unsigned int div2_stat1;
+ unsigned char res85[0x8];
+ unsigned int div4_stat;
+ unsigned char res86[0x184];
+ unsigned int gate_top_sclk_disp1;
+ unsigned int gate_top_sclk_gen;
+ unsigned char res87[0xc];
+ unsigned int gate_top_sclk_mau;
+ unsigned int gate_top_sclk_fsys;
+ unsigned char res88[0xc];
+ unsigned int gate_top_sclk_peric;
+ unsigned char res89[0x1c];
+ unsigned int gate_top_sclk_isp;
+ unsigned char res90[0xac];
+ unsigned int gate_ip_gscl;
+ unsigned char res91[0x4];
+ unsigned int gate_ip_disp1;
+ unsigned int gate_ip_mfc;
+ unsigned int gate_ip_g3d;
+ unsigned int gate_ip_gen;
+ unsigned char res92[0xc];
+ unsigned int gate_ip_fsys;
+ unsigned char res93[0x8];
+ unsigned int gate_ip_peric;
+ unsigned char res94[0xc];
+ unsigned int gate_ip_peris;
+ unsigned char res95[0x1c];
+ unsigned int gate_block;
+ unsigned char res96[0x1c];
+ unsigned int mcuiop_pwr_ctrl;
+ unsigned char res97[0x5c];
+ unsigned int clkout_cmu_top;
+ unsigned int clkout_cmu_top_div_stat;
+ unsigned char res98[0x37f8];
+ unsigned int src_lex;
+ unsigned char res99[0x1fc];
+ unsigned int mux_stat_lex;
+ unsigned char res100[0xfc];
+ unsigned int div_lex;
+ unsigned char res101[0xfc];
+ unsigned int div_stat_lex;
+ unsigned char res102[0x1fc];
+ unsigned int gate_ip_lex;
+ unsigned char res103[0x1fc];
+ unsigned int clkout_cmu_lex;
+ unsigned int clkout_cmu_lex_div_stat;
+ unsigned char res104[0x3af8];
+ unsigned int div_r0x;
+ unsigned char res105[0xfc];
+ unsigned int div_stat_r0x;
+ unsigned char res106[0x1fc];
+ unsigned int gate_ip_r0x;
+ unsigned char res107[0x1fc];
+ unsigned int clkout_cmu_r0x;
+ unsigned int clkout_cmu_r0x_div_stat;
+ unsigned char res108[0x3af8];
+ unsigned int div_r1x;
+ unsigned char res109[0xfc];
+ unsigned int div_stat_r1x;
+ unsigned char res110[0x1fc];
+ unsigned int gate_ip_r1x;
+ unsigned char res111[0x1fc];
+ unsigned int clkout_cmu_r1x;
+ unsigned int clkout_cmu_r1x_div_stat;
+ unsigned char res112[0x3608];
+ unsigned int bpll_lock;
+ unsigned char res113[0xfc];
+ unsigned int bpll_con0;
+ unsigned int bpll_con1;
+ unsigned char res114[0xe8];
+ unsigned int src_cdrex;
+ unsigned char res115[0x1fc];
+ unsigned int mux_stat_cdrex;
+ unsigned char res116[0xfc];
+ unsigned int div_cdrex;
+ unsigned char res117[0xfc];
+ unsigned int div_stat_cdrex;
+ unsigned char res118[0x2fc];
+ unsigned int gate_ip_cdrex;
+ unsigned char res119[0x10];
+ unsigned int dmc_freq_ctrl;
+ unsigned char res120[0x4];
+ unsigned int drex2_pause;
+ unsigned char res121[0xe0];
+ unsigned int clkout_cmu_cdrex;
+ unsigned int clkout_cmu_cdrex_div_stat;
+ unsigned char res122[0x8];
+ unsigned int lpddr3phy_ctrl;
+ unsigned int lpddr3phy_con0;
+ unsigned int lpddr3phy_con1;
+ unsigned int lpddr3phy_con2;
+ unsigned int lpddr3phy_con3;
+ unsigned int pll_div2_sel;
+ unsigned char res123[0xf5d8];
+};
+
+struct exynos5420_clock {
+ unsigned int apll_lock; /* 0x10010000 */
+ unsigned char res1[0xfc];
+ unsigned int apll_con0;
+ unsigned int apll_con1;
+ unsigned char res2[0xf8];
+ unsigned int src_cpu;
+ unsigned char res3[0x1fc];
+ unsigned int mux_stat_cpu;
+ unsigned char res4[0xfc];
+ unsigned int div_cpu0; /* 0x10010500 */
+ unsigned int div_cpu1;
+ unsigned char res5[0xf8];
+ unsigned int div_stat_cpu0;
+ unsigned int div_stat_cpu1;
+ unsigned char res6[0xf8];
+ unsigned int gate_bus_cpu;
+ unsigned char res7[0xfc];
+ unsigned int gate_sclk_cpu;
+ unsigned char res8[0x1fc];
+ unsigned int clkout_cmu_cpu; /* 0x10010a00 */
+ unsigned int clkout_cmu_cpu_div_stat;
+ unsigned char res9[0x5f8];
+ unsigned int armclk_stopctrl;
+ unsigned char res10[0x4];
+ unsigned int arm_ema_ctrl;
+ unsigned int arm_ema_status;
+ unsigned char res11[0x10];
+ unsigned int pwr_ctrl;
+ unsigned int pwr_ctrl2;
+ unsigned char res12[0xd8];
+ unsigned int apll_con0_l8; /* 0x1001100 */
+ unsigned int apll_con0_l7;
+ unsigned int apll_con0_l6;
+ unsigned int apll_con0_l5;
+ unsigned int apll_con0_l4;
+ unsigned int apll_con0_l3;
+ unsigned int apll_con0_l2;
+ unsigned int apll_con0_l1;
+ unsigned int iem_control;
+ unsigned char res13[0xdc];
+ unsigned int apll_con1_l8; /* 0x10011200 */
+ unsigned int apll_con1_l7;
+ unsigned int apll_con1_l6;
+ unsigned int apll_con1_l5;
+ unsigned int apll_con1_l4;
+ unsigned int apll_con1_l3;
+ unsigned int apll_con1_l2;
+ unsigned int apll_con1_l1;
+ unsigned char res14[0xe0];
+ unsigned int clkdiv_iem_l8;
+ unsigned int clkdiv_iem_l7; /* 0x10011304 */
+ unsigned int clkdiv_iem_l6;
+ unsigned int clkdiv_iem_l5;
+ unsigned int clkdiv_iem_l4;
+ unsigned int clkdiv_iem_l3;
+ unsigned int clkdiv_iem_l2;
+ unsigned int clkdiv_iem_l1;
+ unsigned char res15[0xe0];
+ unsigned int l2_status;
+ unsigned char res16[0x0c];
+ unsigned int cpu_status; /* 0x10011410 */
+ unsigned char res17[0x0c];
+ unsigned int ptm_status;
+ unsigned char res18[0xbdc];
+ unsigned int cmu_cpu_spare0;
+ unsigned int cmu_cpu_spare1;
+ unsigned int cmu_cpu_spare2;
+ unsigned int cmu_cpu_spare3;
+ unsigned int cmu_cpu_spare4;
+ unsigned char res19[0x1fdc];
+ unsigned int cmu_cpu_version;
+ unsigned char res20[0x20c];
+ unsigned int src_cperi0; /* 0x10014200 */
+ unsigned int src_cperi1;
+ unsigned char res21[0xf8];
+ unsigned int src_mask_cperi;
+ unsigned char res22[0x100];
+ unsigned int mux_stat_cperi1;
+ unsigned char res23[0xfc];
+ unsigned int div_cperi1;
+ unsigned char res24[0xfc];
+ unsigned int div_stat_cperi1;
+ unsigned char res25[0xf8];
+ unsigned int gate_bus_cperi0; /* 0x10014700 */
+ unsigned int gate_bus_cperi1;
+ unsigned char res26[0xf8];
+ unsigned int gate_sclk_cperi;
+ unsigned char res27[0xfc];
+ unsigned int gate_ip_cperi;
+ unsigned char res28[0xfc];
+ unsigned int clkout_cmu_cperi;
+ unsigned int clkout_cmu_cperi_div_stat;
+ unsigned char res29[0x5f8];
+ unsigned int dcgidx_map0; /* 0x10015000 */
+ unsigned int dcgidx_map1;
+ unsigned int dcgidx_map2;
+ unsigned char res30[0x14];
+ unsigned int dcgperf_map0;
+ unsigned int dcgperf_map1;
+ unsigned char res31[0x18];
+ unsigned int dvcidx_map;
+ unsigned char res32[0x1c];
+ unsigned int freq_cpu;
+ unsigned int freq_dpm;
+ unsigned char res33[0x18];
+ unsigned int dvsemclk_en; /* 0x10015080 */
+ unsigned int maxperf;
+ unsigned char res34[0x2e78];
+ unsigned int cmu_cperi_spare0;
+ unsigned int cmu_cperi_spare1;
+ unsigned int cmu_cperi_spare2;
+ unsigned int cmu_cperi_spare3;
+ unsigned int cmu_cperi_spare4;
+ unsigned int cmu_cperi_spare5;
+ unsigned int cmu_cperi_spare6;
+ unsigned int cmu_cperi_spare7;
+ unsigned int cmu_cperi_spare8;
+ unsigned char res35[0xcc];
+ unsigned int cmu_cperi_version; /* 0x10017ff0 */
+ unsigned char res36[0x50c];
+ unsigned int div_g2d;
+ unsigned char res37[0xfc];
+ unsigned int div_stat_g2d;
+ unsigned char res38[0xfc];
+ unsigned int gate_bus_g2d;
+ unsigned char res39[0xfc];
+ unsigned int gate_ip_g2d;
+ unsigned char res40[0x1fc];
+ unsigned int clkout_cmu_g2d;
+ unsigned int clkout_cmu_g2d_div_stat; /* 0x10018a04 */
+ unsigned char res41[0xf8];
+ unsigned int cmu_g2d_spare0;
+ unsigned int cmu_g2d_spare1;
+ unsigned int cmu_g2d_spare2;
+ unsigned int cmu_g2d_spare3;
+ unsigned int cmu_g2d_spare4;
+ unsigned char res42[0x34dc];
+ unsigned int cmu_g2d_version;
+ unsigned char res43[0x30c];
+ unsigned int div_cmu_isp0;
+ unsigned int div_cmu_isp1;
+ unsigned int div_isp2; /* 0x1001c308 */
+ unsigned char res44[0xf4];
+ unsigned int div_stat_cmu_isp0;
+ unsigned int div_stat_cmu_isp1;
+ unsigned int div_stat_isp2;
+ unsigned char res45[0x2f4];
+ unsigned int gate_bus_isp0;
+ unsigned int gate_bus_isp1;
+ unsigned int gate_bus_isp2;
+ unsigned int gate_bus_isp3;
+ unsigned char res46[0xf0];
+ unsigned int gate_ip_isp0;
+ unsigned int gate_ip_isp1;
+ unsigned char res47[0xf8];
+ unsigned int gate_sclk_isp;
+ unsigned char res48[0x0c];
+ unsigned int mcuisp_pwr_ctrl; /* 0x1001c910 */
+ unsigned char res49[0x0ec];
+ unsigned int clkout_cmu_isp;
+ unsigned int clkout_cmu_isp_div_stat;
+ unsigned char res50[0xf8];
+ unsigned int cmu_isp_spare0;
+ unsigned int cmu_isp_spare1;
+ unsigned int cmu_isp_spare2;
+ unsigned int cmu_isp_spare3;
+ unsigned char res51[0x34e0];
+ unsigned int cmu_isp_version;
+ unsigned char res52[0x2c];
+ unsigned int cpll_lock; /* 10020020 */
+ unsigned char res53[0xc];
+ unsigned int dpll_lock;
+ unsigned char res54[0xc];
+ unsigned int epll_lock;
+ unsigned char res55[0xc];
+ unsigned int rpll_lock;
+ unsigned char res56[0xc];
+ unsigned int ipll_lock;
+ unsigned char res57[0xc];
+ unsigned int spll_lock;
+ unsigned char res58[0xc];
+ unsigned int vpll_lock;
+ unsigned char res59[0xc];
+ unsigned int mpll_lock;
+ unsigned char res60[0x8c];
+ unsigned int cpll_con0; /* 10020120 */
+ unsigned int cpll_con1;
+ unsigned int dpll_con0;
+ unsigned int dpll_con1;
+ unsigned int epll_con0;
+ unsigned int epll_con1;
+ unsigned int epll_con2;
+ unsigned char res601[0x4];
+ unsigned int rpll_con0;
+ unsigned int rpll_con1;
+ unsigned int rpll_con2;
+ unsigned char res602[0x4];
+ unsigned int ipll_con0;
+ unsigned int ipll_con1;
+ unsigned char res61[0x8];
+ unsigned int spll_con0;
+ unsigned int spll_con1;
+ unsigned char res62[0x8];
+ unsigned int vpll_con0;
+ unsigned int vpll_con1;
+ unsigned char res63[0x8];
+ unsigned int mpll_con0;
+ unsigned int mpll_con1;
+ unsigned char res64[0x78];
+ unsigned int src_top0; /* 0x10020200 */
+ unsigned int src_top1;
+ unsigned int src_top2;
+ unsigned int src_top3;
+ unsigned int src_top4;
+ unsigned int src_top5;
+ unsigned int src_top6;
+ unsigned int src_top7;
+ unsigned char res65[0xc];
+ unsigned int src_disp10; /* 0x1002022c */
+ unsigned char res66[0x10];
+ unsigned int src_mau;
+ unsigned int src_fsys;
+ unsigned char res67[0x8];
+ unsigned int src_peric0;
+ unsigned int src_peric1;
+ unsigned char res68[0x18];
+ unsigned int src_isp;
+ unsigned char res69[0x0c];
+ unsigned int src_top10;
+ unsigned int src_top11;
+ unsigned int src_top12;
+ unsigned char res70[0x74];
+ unsigned int src_mask_top0;
+ unsigned int src_mask_top1;
+ unsigned int src_mask_top2;
+ unsigned char res71[0x10];
+ unsigned int src_mask_top7;
+ unsigned char res72[0xc];
+ unsigned int src_mask_disp10; /* 0x1002032c */
+ unsigned char res73[0x4];
+ unsigned int src_mask_mau;
+ unsigned char res74[0x8];
+ unsigned int src_mask_fsys;
+ unsigned char res75[0xc];
+ unsigned int src_mask_peric0;
+ unsigned int src_mask_peric1;
+ unsigned char res76[0x18];
+ unsigned int src_mask_isp;
+ unsigned char res77[0x8c];
+ unsigned int mux_stat_top0; /* 0x10020400 */
+ unsigned int mux_stat_top1;
+ unsigned int mux_stat_top2;
+ unsigned int mux_stat_top3;
+ unsigned int mux_stat_top4;
+ unsigned int mux_stat_top5;
+ unsigned int mux_stat_top6;
+ unsigned int mux_stat_top7;
+ unsigned char res78[0x60];
+ unsigned int mux_stat_top10;
+ unsigned int mux_stat_top11;
+ unsigned int mux_stat_top12;
+ unsigned char res79[0x74];
+ unsigned int div_top0; /* 0x10020500 */
+ unsigned int div_top1;
+ unsigned int div_top2;
+ unsigned char res80[0x20];
+ unsigned int div_disp10;
+ unsigned char res81[0x14];
+ unsigned int div_mau;
+ unsigned int div_fsys0;
+ unsigned int div_fsys1;
+ unsigned int div_fsys2;
+ unsigned char res82[0x4];
+ unsigned int div_peric0;
+ unsigned int div_peric1;
+ unsigned int div_peric2;
+ unsigned int div_peric3;
+ unsigned int div_peric4; /* 0x10020568 */
+ unsigned char res83[0x14];
+ unsigned int div_isp0;
+ unsigned int div_isp1;
+ unsigned char res84[0x8];
+ unsigned int clkdiv2_ratio;
+ unsigned char res850[0xc];
+ unsigned int clkdiv4_ratio;
+ unsigned char res85[0x5c];
+ unsigned int div_stat_top0;
+ unsigned int div_stat_top1;
+ unsigned int div_stat_top2;
+ unsigned char res86[0x20];
+ unsigned int div_stat_disp10;
+ unsigned char res87[0x14];
+ unsigned int div_stat_mau; /* 0x10020644 */
+ unsigned int div_stat_fsys0;
+ unsigned int div_stat_fsys1;
+ unsigned int div_stat_fsys2;
+ unsigned char res88[0x4];
+ unsigned int div_stat_peric0;
+ unsigned int div_stat_peric1;
+ unsigned int div_stat_peric2;
+ unsigned int div_stat_peric3;
+ unsigned int div_stat_peric4;
+ unsigned char res89[0x14];
+ unsigned int div_stat_isp0;
+ unsigned int div_stat_isp1;
+ unsigned char res90[0x8];
+ unsigned int clkdiv2_stat0;
+ unsigned char res91[0xc];
+ unsigned int clkdiv4_stat;
+ unsigned char res92[0x5c];
+ unsigned int gate_bus_top; /* 0x10020700 */
+ unsigned char res93[0xc];
+ unsigned int gate_bus_gscl0;
+ unsigned char res94[0xc];
+ unsigned int gate_bus_gscl1;
+ unsigned char res95[0x4];
+ unsigned int gate_bus_disp1;
+ unsigned char res96[0x4];
+ unsigned int gate_bus_wcore;
+ unsigned int gate_bus_mfc;
+ unsigned int gate_bus_g3d;
+ unsigned int gate_bus_gen;
+ unsigned int gate_bus_fsys0;
+ unsigned int gate_bus_fsys1;
+ unsigned int gate_bus_fsys2;
+ unsigned int gate_bus_mscl;
+ unsigned int gate_bus_peric;
+ unsigned int gate_bus_peric1;
+ unsigned char res97[0x8];
+ unsigned int gate_bus_peris0;
+ unsigned int gate_bus_peris1; /* 0x10020764 */
+ unsigned char res98[0x8];
+ unsigned int gate_bus_noc;
+ unsigned char res99[0xac];
+ unsigned int gate_top_sclk_gscl;
+ unsigned char res1000[0x4];
+ unsigned int gate_top_sclk_disp1;
+ unsigned char res100[0x10];
+ unsigned int gate_top_sclk_mau;
+ unsigned int gate_top_sclk_fsys;
+ unsigned char res101[0xc];
+ unsigned int gate_top_sclk_peric;
+ unsigned char res102[0xc];
+ unsigned int gate_top_sclk_cperi;
+ unsigned char res103[0xc];
+ unsigned int gate_top_sclk_isp;
+ unsigned char res104[0x9c];
+ unsigned int gate_ip_gscl0;
+ unsigned char res105[0xc];
+ unsigned int gate_ip_gscl1;
+ unsigned char res106[0x4];
+ unsigned int gate_ip_disp1;
+ unsigned int gate_ip_mfc;
+ unsigned int gate_ip_g3d;
+ unsigned int gate_ip_gen; /* 0x10020934 */
+ unsigned char res107[0xc];
+ unsigned int gate_ip_fsys;
+ unsigned char res108[0x8];
+ unsigned int gate_ip_peric;
+ unsigned char res109[0xc];
+ unsigned int gate_ip_peris;
+ unsigned char res110[0xc];
+ unsigned int gate_ip_mscl;
+ unsigned char res111[0xc];
+ unsigned int gate_ip_block;
+ unsigned char res112[0xc];
+ unsigned int bypass;
+ unsigned char res113[0x6c];
+ unsigned int clkout_cmu_top;
+ unsigned int clkout_cmu_top_div_stat;
+ unsigned char res114[0xf8];
+ unsigned int clkout_top_spare0;
+ unsigned int clkout_top_spare1;
+ unsigned int clkout_top_spare2;
+ unsigned int clkout_top_spare3;
+ unsigned char res115[0x34e0];
+ unsigned int clkout_top_version;
+ unsigned char res116[0xc01c];
+ unsigned int bpll_lock; /* 0x10030010 */
+ unsigned char res117[0xfc];
+ unsigned int bpll_con0;
+ unsigned int bpll_con1;
+ unsigned char res118[0xe8];
+ unsigned int src_cdrex;
+ unsigned char res119[0x1fc];
+ unsigned int mux_stat_cdrex;
+ unsigned char res120[0xfc];
+ unsigned int div_cdrex0;
+ unsigned int div_cdrex1;
+ unsigned char res121[0xf8];
+ unsigned int div_stat_cdrex;
+ unsigned char res1211[0xfc];
+ unsigned int gate_bus_cdrex;
+ unsigned int gate_bus_cdrex1;
+ unsigned char res122[0x1f8];
+ unsigned int gate_ip_cdrex;
+ unsigned char res123[0x10];
+ unsigned int dmc_freq_ctrl; /* 0x10030914 */
+ unsigned char res124[0x4];
+ unsigned int pause;
+ unsigned int ddrphy_lock_ctrl;
+ unsigned char res125[0xdc];
+ unsigned int clkout_cmu_cdrex;
+ unsigned int clkout_cmu_cdrex_div_stat;
+ unsigned char res126[0x8];
+ unsigned int lpddr3phy_ctrl;
+ unsigned int lpddr3phy_con0;
+ unsigned int lpddr3phy_con1;
+ unsigned int lpddr3phy_con2;
+ unsigned int lpddr3phy_con3;
+ unsigned int lpddr3phy_con4;
+ unsigned int lpddr3phy_con5; /* 0x10030a28 */
+ unsigned int pll_div2_sel;
+ unsigned char res127[0xd0];
+ unsigned int cmu_cdrex_spare0;
+ unsigned int cmu_cdrex_spare1;
+ unsigned int cmu_cdrex_spare2;
+ unsigned int cmu_cdrex_spare3;
+ unsigned int cmu_cdrex_spare4;
+ unsigned char res128[0x34dc];
+ unsigned int cmu_cdrex_version; /* 0x10033ff0 */
+ unsigned char res129[0x400c];
+ unsigned int kpll_lock;
+ unsigned char res130[0xfc];
+ unsigned int kpll_con0;
+ unsigned int kpll_con1;
+ unsigned char res131[0xf8];
+ unsigned int src_kfc;
+ unsigned char res132[0x1fc];
+ unsigned int mux_stat_kfc; /* 0x10038400 */
+ unsigned char res133[0xfc];
+ unsigned int div_kfc0;
+ unsigned char res134[0xfc];
+ unsigned int div_stat_kfc0;
+ unsigned char res135[0xfc];
+ unsigned int gate_bus_cpu_kfc;
+ unsigned char res136[0xfc];
+ unsigned int gate_sclk_cpu_kfc;
+ unsigned char res137[0x1fc];
+ unsigned int clkout_cmu_kfc;
+ unsigned int clkout_cmu_kfc_div_stat; /* 0x10038a04 */
+ unsigned char res138[0x5f8];
+ unsigned int armclk_stopctrl_kfc;
+ unsigned char res139[0x4];
+ unsigned int armclk_ema_ctrl_kfc;
+ unsigned int armclk_ema_status_kfc;
+ unsigned char res140[0x10];
+ unsigned int pwr_ctrl_kfc;
+ unsigned int pwr_ctrl2_kfc;
+ unsigned char res141[0xd8];
+ unsigned int kpll_con0_l8;
+ unsigned int kpll_con0_l7;
+ unsigned int kpll_con0_l6;
+ unsigned int kpll_con0_l5;
+ unsigned int kpll_con0_l4;
+ unsigned int kpll_con0_l3;
+ unsigned int kpll_con0_l2;
+ unsigned int kpll_con0_l1;
+ unsigned int iem_control_kfc; /* 0x10039120 */
+ unsigned char res142[0xdc];
+ unsigned int kpll_con1_l8;
+ unsigned int kpll_con1_l7;
+ unsigned int kpll_con1_l6;
+ unsigned int kpll_con1_l5;
+ unsigned int kpll_con1_l4;
+ unsigned int kpll_con1_l3;
+ unsigned int kpll_con1_l2;
+ unsigned int kpll_con1_l1;
+ unsigned char res143[0xe0];
+ unsigned int clkdiv_iem_l8_kfc; /* 0x10039300 */
+ unsigned int clkdiv_iem_l7_kfc;
+ unsigned int clkdiv_iem_l6_kfc;
+ unsigned int clkdiv_iem_l5_kfc;
+ unsigned int clkdiv_iem_l4_kfc;
+ unsigned int clkdiv_iem_l3_kfc;
+ unsigned int clkdiv_iem_l2_kfc;
+ unsigned int clkdiv_iem_l1_kfc;
+ unsigned char res144[0xe0];
+ unsigned int l2_status_kfc;
+ unsigned char res145[0xc];
+ unsigned int cpu_status_kfc; /* 0x10039410 */
+ unsigned char res146[0xc];
+ unsigned int ptm_status_kfc;
+ unsigned char res147[0xbdc];
+ unsigned int cmu_kfc_spare0;
+ unsigned int cmu_kfc_spare1;
+ unsigned int cmu_kfc_spare2;
+ unsigned int cmu_kfc_spare3;
+ unsigned int cmu_kfc_spare4;
+ unsigned char res148[0x1fdc];
+ unsigned int cmu_kfc_version; /* 0x1003bff0 */
+};
+
+/* structure for epll configuration used in audio clock configuration */
+struct set_epll_con_val {
+ unsigned int freq_out; /* frequency out */
+ unsigned int en_lock_det; /* enable lock detect */
+ unsigned int m_div; /* m divider value */
+ unsigned int p_div; /* p divider value */
+ unsigned int s_div; /* s divider value */
+ unsigned int k_dsm; /* k value of delta signal modulator */
+};
+#endif
+
+#define MPLL_FOUT_SEL_SHIFT 4
+#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/
+#define TIMEOUT_EPLL_LOCK 1000
+
+#define AUDIO_0_RATIO_MASK 0x0f
+#define AUDIO_1_RATIO_MASK 0x0f
+
+#define AUDIO0_SEL_MASK 0xf
+#define AUDIO1_SEL_MASK 0xf
+
+#define CLK_SRC_SCLK_EPLL 0x7
+#define CLK_SRC_MOUT_EPLL (1<<12)
+#define AUDIO_CLKMUX_ASS (1<<0)
+
+/* CON0 bit-fields */
+#define EPLL_CON0_MDIV_MASK 0x1ff
+#define EPLL_CON0_PDIV_MASK 0x3f
+#define EPLL_CON0_SDIV_MASK 0x7
+#define EPLL_CON0_MDIV_SHIFT 16
+#define EPLL_CON0_PDIV_SHIFT 8
+#define EPLL_CON0_SDIV_SHIFT 0
+#define EPLL_CON0_LOCK_DET_EN_SHIFT 28
+#define EPLL_CON0_LOCK_DET_EN_MASK 1
+
+#define MPLL_FOUT_SEL_MASK 0x1
+#define BPLL_FOUT_SEL_SHIFT 0
+#define BPLL_FOUT_SEL_MASK 0x1
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _EXYNOS4_CPU_H
+#define _EXYNOS4_CPU_H
+
+#define DEVICE_NOT_AVAILABLE 0
+
+#define EXYNOS_CPU_NAME "Exynos"
+#define EXYNOS4_ADDR_BASE 0x10000000
+
+/* EXYNOS4 Common*/
+#define EXYNOS4_I2C_SPACING 0x10000
+
+#define EXYNOS4_GPIO_PART3_BASE 0x03860000
+#define EXYNOS4_PRO_ID 0x10000000
+#define EXYNOS4_SYSREG_BASE 0x10010000
+#define EXYNOS4_POWER_BASE 0x10020000
+#define EXYNOS4_SWRESET 0x10020400
+#define EXYNOS4_CLOCK_BASE 0x10030000
+#define EXYNOS4_SYSTIMER_BASE 0x10050000
+#define EXYNOS4_WATCHDOG_BASE 0x10060000
+#define EXYNOS4_TZPC_BASE 0x10110000
+#define EXYNOS4_DMC_CTRL_BASE 0x10400000
+#define EXYNOS4_MIU_BASE 0x10600000
+#define EXYNOS4_ACE_SFR_BASE 0x10830000
+#define EXYNOS4_GPIO_PART2_BASE 0x11000000
+#define EXYNOS4_GPIO_PART2_0 0x11000000 /* GPJ0 */
+#define EXYNOS4_GPIO_PART2_1 0x11000c00 /* GPX0 */
+#define EXYNOS4_GPIO_PART1_BASE 0x11400000
+#define EXYNOS4_FIMD_BASE 0x11C00000
+#define EXYNOS4_MIPI_DSIM_BASE 0x11C80000
+#define EXYNOS4_USBOTG_BASE 0x12480000
+#define EXYNOS4_MMC_BASE 0x12510000
+#define EXYNOS4_SROMC_BASE 0x12570000
+#define EXYNOS4_USB_HOST_EHCI_BASE 0x12580000
+#define EXYNOS4_USBPHY_BASE 0x125B0000
+#define EXYNOS4_UART_BASE 0x13800000
+#define EXYNOS4_I2C_BASE 0x13860000
+#define EXYNOS4_ADC_BASE 0x13910000
+#define EXYNOS4_SPI_BASE 0x13920000
+#define EXYNOS4_PWMTIMER_BASE 0x139D0000
+#define EXYNOS4_MODEM_BASE 0x13A00000
+#define EXYNOS4_USBPHY_CONTROL 0x10020704
+#define EXYNOS4_I2S_BASE 0xE2100000
+
+#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4_USB3PHY_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE
+
+/* EXYNOS4X12 */
+#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000
+#define EXYNOS4X12_PRO_ID 0x10000000
+#define EXYNOS4X12_SYSREG_BASE 0x10010000
+#define EXYNOS4X12_POWER_BASE 0x10020000
+#define EXYNOS4X12_SWRESET 0x10020400
+#define EXYNOS4X12_USBPHY_CONTROL 0x10020704
+#define EXYNOS4X12_CLOCK_BASE 0x10030000
+#define EXYNOS4X12_SYSTIMER_BASE 0x10050000
+#define EXYNOS4X12_WATCHDOG_BASE 0x10060000
+#define EXYNOS4X12_TZPC_BASE 0x10110000
+#define EXYNOS4X12_DMC_CTRL_BASE 0x10600000
+#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
+#define EXYNOS4X12_ACE_SFR_BASE 0x10830000
+#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000
+#define EXYNOS4X12_GPIO_PART2_0 0x11000000
+#define EXYNOS4X12_GPIO_PART2_1 0x11000040 /* GPK0 */
+#define EXYNOS4X12_GPIO_PART2_2 0x11000260 /* GPM0 */
+#define EXYNOS4X12_GPIO_PART2_3 0x11000c00 /* GPX0 */
+#define EXYNOS4X12_GPIO_PART1_BASE 0x11400000
+#define EXYNOS4X12_GPIO_PART1_0 0x11400000 /* GPA0 */
+#define EXYNOS4X12_GPIO_PART1_1 0x11400180 /* GPF0 */
+#define EXYNOS4X12_GPIO_PART1_2 0x11400240 /* GPJ0 */
+#define EXYNOS4X12_FIMD_BASE 0x11C00000
+#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000
+#define EXYNOS4X12_USBOTG_BASE 0x12480000
+#define EXYNOS4X12_MMC_BASE 0x12510000
+#define EXYNOS4X12_SROMC_BASE 0x12570000
+#define EXYNOS4X12_USB_HOST_EHCI_BASE 0x12580000
+#define EXYNOS4X12_USBPHY_BASE 0x125B0000
+#define EXYNOS4X12_UART_BASE 0x13800000
+#define EXYNOS4X12_I2C_BASE 0x13860000
+#define EXYNOS4X12_PWMTIMER_BASE 0x139D0000
+
+#define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_USB3PHY_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE
+
+/* EXYNOS5 */
+#define EXYNOS5_I2C_SPACING 0x10000
+
+#define EXYNOS5_AUDIOSS_BASE 0x03810000
+#define EXYNOS5_GPIO_PART8_BASE 0x03860000
+#define EXYNOS5_PRO_ID 0x10000000
+#define EXYNOS5_CLOCK_BASE 0x10010000
+#define EXYNOS5_POWER_BASE 0x10040000
+#define EXYNOS5_SWRESET 0x10040400
+#define EXYNOS5_SYSREG_BASE 0x10050000
+#define EXYNOS5_TZPC_BASE 0x10100000
+#define EXYNOS5_WATCHDOG_BASE 0x101D0000
+#define EXYNOS5_ACE_SFR_BASE 0x10830000
+#define EXYNOS5_DMC_PHY_BASE 0x10C00000
+#define EXYNOS5_GPIO_PART5_BASE 0x10D10000
+#define EXYNOS5_GPIO_PART6_BASE 0x10D10060
+#define EXYNOS5_GPIO_PART7_BASE 0x10D100C0
+#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
+#define EXYNOS5_GPIO_PART1_BASE 0x11400000
+#define EXYNOS5_GPIO_PART2_BASE 0x114002E0
+#define EXYNOS5_GPIO_PART3_BASE 0x11400C00
+#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
+#define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000
+#define EXYNOS5_USB3PHY_BASE 0x12100000
+#define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000
+#define EXYNOS5_USBPHY_BASE 0x12130000
+#define EXYNOS5_USBOTG_BASE 0x12140000
+#define EXYNOS5_MMC_BASE 0x12200000
+#define EXYNOS5_SROMC_BASE 0x12250000
+#define EXYNOS5_UART_BASE 0x12C00000
+#define EXYNOS5_I2C_BASE 0x12C60000
+#define EXYNOS5_SPI_BASE 0x12D20000
+#define EXYNOS5_I2S_BASE 0x12D60000
+#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
+#define EXYNOS5_SPI_ISP_BASE 0x131A0000
+#define EXYNOS5_GPIO_PART4_BASE 0x13400000
+#define EXYNOS5_FIMD_BASE 0x14400000
+#define EXYNOS5_DP_BASE 0x145B0000
+
+#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE
+
+/* EXYNOS5420 */
+#define EXYNOS5420_AUDIOSS_BASE 0x03810000
+#define EXYNOS5420_GPIO_PART6_BASE 0x03860000
+#define EXYNOS5420_PRO_ID 0x10000000
+#define EXYNOS5420_CLOCK_BASE 0x10010000
+#define EXYNOS5420_POWER_BASE 0x10040000
+#define EXYNOS5420_SWRESET 0x10040400
+#define EXYNOS5420_INFORM_BASE 0x10040800
+#define EXYNOS5420_SPARE_BASE 0x10040900
+#define EXYNOS5420_CPU_CONFIG_BASE 0x10042000
+#define EXYNOS5420_CPU_STATUS_BASE 0x10042004
+#define EXYNOS5420_SYSREG_BASE 0x10050000
+#define EXYNOS5420_TZPC_BASE 0x100E0000
+#define EXYNOS5420_WATCHDOG_BASE 0x101D0000
+#define EXYNOS5420_ACE_SFR_BASE 0x10830000
+#define EXYNOS5420_DMC_PHY_BASE 0x10C00000
+#define EXYNOS5420_DMC_CTRL_BASE 0x10C20000
+#define EXYNOS5420_DMC_TZASC_BASE 0x10D40000
+#define EXYNOS5420_USB_HOST_EHCI_BASE 0x12110000
+#define EXYNOS5420_MMC_BASE 0x12200000
+#define EXYNOS5420_SROMC_BASE 0x12250000
+#define EXYNOS5420_USB3PHY_BASE 0x12500000
+#define EXYNOS5420_UART_BASE 0x12C00000
+#define EXYNOS5420_I2C_BASE 0x12C60000
+#define EXYNOS5420_I2C_8910_BASE 0x12E00000
+#define EXYNOS5420_SPI_BASE 0x12D20000
+#define EXYNOS5420_I2S_BASE 0x12D60000
+#define EXYNOS5420_PWMTIMER_BASE 0x12DD0000
+#define EXYNOS5420_SPI_ISP_BASE 0x131A0000
+#define EXYNOS5420_GPIO_PART2_BASE 0x13400000
+#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00
+#define EXYNOS5420_GPIO_PART4_BASE 0x13410000
+#define EXYNOS5420_GPIO_PART5_BASE 0x14000000
+#define EXYNOS5420_GPIO_PART1_BASE 0x14010000
+#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000
+#define EXYNOS5420_DP_BASE 0x145B0000
+
+#define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_FIMD_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_ADC_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
+
+
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+/* CPU detection macros */
+extern unsigned int s5p_cpu_id;
+extern unsigned int s5p_cpu_rev;
+
+static inline int s5p_get_cpu_rev(void)
+{
+ return s5p_cpu_rev;
+}
+
+static inline void s5p_set_cpu_id(void)
+{
+ unsigned int pro_id = readl(EXYNOS4_PRO_ID);
+ unsigned int cpu_id = (pro_id & 0x00FFF000) >> 12;
+ unsigned int cpu_rev = pro_id & 0x000000FF;
+
+ switch (cpu_id) {
+ case 0x200:
+ /* Exynos4210 EVT0 */
+ s5p_cpu_id = 0x4210;
+ s5p_cpu_rev = 0;
+ break;
+ case 0x210:
+ /* Exynos4210 EVT1 */
+ s5p_cpu_id = 0x4210;
+ s5p_cpu_rev = cpu_rev;
+ break;
+ case 0x412:
+ /* Exynos4412 */
+ s5p_cpu_id = 0x4412;
+ s5p_cpu_rev = cpu_rev;
+ break;
+ case 0x520:
+ /* Exynos5250 */
+ s5p_cpu_id = 0x5250;
+ break;
+ case 0x420:
+ /* Exynos5420 */
+ s5p_cpu_id = 0x5420;
+ break;
+ case 0x422:
+ /*
+ * Exynos5800 is a variant of Exynos5420
+ * and has product id 0x5422
+ */
+ s5p_cpu_id = 0x5800;
+ break;
+ }
+}
+
+static inline char *s5p_get_cpu_name(void)
+{
+ return EXYNOS_CPU_NAME;
+}
+
+#define IS_SAMSUNG_TYPE(type, id) \
+static inline int __attribute__((no_instrument_function)) cpu_is_##type(void) \
+{ \
+ return (s5p_cpu_id >> 12) == id; \
+}
+
+IS_SAMSUNG_TYPE(exynos4, 0x4)
+IS_SAMSUNG_TYPE(exynos5, 0x5)
+
+#define IS_EXYNOS_TYPE(type, id) \
+static inline int __attribute__((no_instrument_function)) \
+ proid_is_##type(void) \
+{ \
+ return s5p_cpu_id == id; \
+}
+
+IS_EXYNOS_TYPE(exynos4210, 0x4210)
+IS_EXYNOS_TYPE(exynos4412, 0x4412)
+IS_EXYNOS_TYPE(exynos5250, 0x5250)
+IS_EXYNOS_TYPE(exynos5420, 0x5420)
+IS_EXYNOS_TYPE(exynos5800, 0x5800)
+
+#define SAMSUNG_BASE(device, base) \
+static inline unsigned int __attribute__((no_instrument_function)) \
+ samsung_get_base_##device(void) \
+{ \
+ if (cpu_is_exynos4()) { \
+ if (proid_is_exynos4412()) \
+ return EXYNOS4X12_##base; \
+ return EXYNOS4_##base; \
+ } else if (cpu_is_exynos5()) { \
+ if (proid_is_exynos5420() || proid_is_exynos5800()) \
+ return EXYNOS5420_##base; \
+ return EXYNOS5_##base; \
+ } \
+ return 0; \
+}
+
+SAMSUNG_BASE(adc, ADC_BASE)
+SAMSUNG_BASE(clock, CLOCK_BASE)
+SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
+SAMSUNG_BASE(dp, DP_BASE)
+SAMSUNG_BASE(sysreg, SYSREG_BASE)
+SAMSUNG_BASE(fimd, FIMD_BASE)
+SAMSUNG_BASE(i2c, I2C_BASE)
+SAMSUNG_BASE(i2s, I2S_BASE)
+SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
+SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
+SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
+SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
+SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE)
+SAMSUNG_BASE(pro_id, PRO_ID)
+SAMSUNG_BASE(mmc, MMC_BASE)
+SAMSUNG_BASE(modem, MODEM_BASE)
+SAMSUNG_BASE(sromc, SROMC_BASE)
+SAMSUNG_BASE(swreset, SWRESET)
+SAMSUNG_BASE(timer, PWMTIMER_BASE)
+SAMSUNG_BASE(uart, UART_BASE)
+SAMSUNG_BASE(usb_phy, USBPHY_BASE)
+SAMSUNG_BASE(usb3_phy, USB3PHY_BASE)
+SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
+SAMSUNG_BASE(usb_xhci, USB_HOST_XHCI_BASE)
+SAMSUNG_BASE(usb_otg, USBOTG_BASE)
+SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
+SAMSUNG_BASE(power, POWER_BASE)
+SAMSUNG_BASE(spi, SPI_BASE)
+SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
+SAMSUNG_BASE(tzpc, TZPC_BASE)
+SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE)
+SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE)
+SAMSUNG_BASE(dmc_tzasc, DMC_TZASC_BASE)
+SAMSUNG_BASE(audio_ass, AUDIOSS_BASE)
+#endif
+
+#endif /* _EXYNOS4_CPU_H */
--- /dev/null
+#ifndef __DMC_H__
+#define __DMC_H__
+
+#ifndef __ASSEMBLY__
+struct exynos4_dmc {
+ unsigned int concontrol;
+ unsigned int memcontrol;
+ unsigned int memconfig0;
+ unsigned int memconfig1;
+ unsigned int directcmd;
+ unsigned int prechconfig;
+ unsigned int phycontrol0;
+ unsigned int phycontrol1;
+ unsigned int phycontrol2;
+ unsigned int phycontrol3;
+ unsigned int pwrdnconfig;
+ unsigned char res1[0x4];
+ unsigned int timingref;
+ unsigned int timingrow;
+ unsigned int timingdata;
+ unsigned int timingpower;
+ unsigned int phystatus;
+ unsigned int phyzqcontrol;
+ unsigned int chip0status;
+ unsigned int chip1status;
+ unsigned int arefstatus;
+ unsigned int mrstatus;
+ unsigned int phytest0;
+ unsigned int phytest1;
+ unsigned int qoscontrol0;
+ unsigned int qosconfig0;
+ unsigned int qoscontrol1;
+ unsigned int qosconfig1;
+ unsigned int qoscontrol2;
+ unsigned int qosconfig2;
+ unsigned int qoscontrol3;
+ unsigned int qosconfig3;
+ unsigned int qoscontrol4;
+ unsigned int qosconfig4;
+ unsigned int qoscontrol5;
+ unsigned int qosconfig5;
+ unsigned int qoscontrol6;
+ unsigned int qosconfig6;
+ unsigned int qoscontrol7;
+ unsigned int qosconfig7;
+ unsigned int qoscontrol8;
+ unsigned int qosconfig8;
+ unsigned int qoscontrol9;
+ unsigned int qosconfig9;
+ unsigned int qoscontrol10;
+ unsigned int qosconfig10;
+ unsigned int qoscontrol11;
+ unsigned int qosconfig11;
+ unsigned int qoscontrol12;
+ unsigned int qosconfig12;
+ unsigned int qoscontrol13;
+ unsigned int qosconfig13;
+ unsigned int qoscontrol14;
+ unsigned int qosconfig14;
+ unsigned int qoscontrol15;
+ unsigned int qosconfig15;
+ unsigned int qostimeout0;
+ unsigned int qostimeout1;
+ unsigned char res2[0x8];
+ unsigned int ivcontrol;
+ unsigned char res3[0x8];
+ unsigned int perevconfig;
+ unsigned char res4[0xDF00];
+ unsigned int pmnc_ppc_a;
+ unsigned char res5[0xC];
+ unsigned int cntens_ppc_a;
+ unsigned char res6[0xC];
+ unsigned int cntenc_ppc_a;
+ unsigned char res7[0xC];
+ unsigned int intens_ppc_a;
+ unsigned char res8[0xC];
+ unsigned int intenc_ppc_a;
+ unsigned char res9[0xC];
+ unsigned int flag_ppc_a;
+ unsigned char res10[0xAC];
+ unsigned int ccnt_ppc_a;
+ unsigned char res11[0xC];
+ unsigned int pmcnt0_ppc_a;
+ unsigned char res12[0xC];
+ unsigned int pmcnt1_ppc_a;
+ unsigned char res13[0xC];
+ unsigned int pmcnt2_ppc_a;
+ unsigned char res14[0xC];
+ unsigned int pmcnt3_ppc_a;
+ unsigned char res15[0xEBC];
+ unsigned int pmnc_ppc_m;
+ unsigned char res16[0xC];
+ unsigned int cntens_ppc_m;
+ unsigned char res17[0xC];
+ unsigned int cntenc_ppc_m;
+ unsigned char res18[0xC];
+ unsigned int intens_ppc_m;
+ unsigned char res19[0xC];
+ unsigned int intenc_ppc_m;
+ unsigned char res20[0xC];
+ unsigned int flag_ppc_m;
+ unsigned char res21[0xAC];
+ unsigned int ccnt_ppc_m;
+ unsigned char res22[0xC];
+ unsigned int pmcnt0_ppc_m;
+ unsigned char res23[0xC];
+ unsigned int pmcnt1_ppc_m;
+ unsigned char res24[0xC];
+ unsigned int pmcnt2_ppc_m;
+ unsigned char res25[0xC];
+ unsigned int pmcnt3_ppc_m;
+};
+
+struct exynos5_dmc {
+ unsigned int concontrol;
+ unsigned int memcontrol;
+ unsigned int memconfig0;
+ unsigned int memconfig1;
+ unsigned int directcmd;
+ unsigned int prechconfig;
+ unsigned int phycontrol0;
+ unsigned char res1[0xc];
+ unsigned int pwrdnconfig;
+ unsigned int timingpzq;
+ unsigned int timingref;
+ unsigned int timingrow;
+ unsigned int timingdata;
+ unsigned int timingpower;
+ unsigned int phystatus;
+ unsigned char res2[0x4];
+ unsigned int chipstatus_ch0;
+ unsigned int chipstatus_ch1;
+ unsigned char res3[0x4];
+ unsigned int mrstatus;
+ unsigned char res4[0x8];
+ unsigned int qoscontrol0;
+ unsigned char resr5[0x4];
+ unsigned int qoscontrol1;
+ unsigned char res6[0x4];
+ unsigned int qoscontrol2;
+ unsigned char res7[0x4];
+ unsigned int qoscontrol3;
+ unsigned char res8[0x4];
+ unsigned int qoscontrol4;
+ unsigned char res9[0x4];
+ unsigned int qoscontrol5;
+ unsigned char res10[0x4];
+ unsigned int qoscontrol6;
+ unsigned char res11[0x4];
+ unsigned int qoscontrol7;
+ unsigned char res12[0x4];
+ unsigned int qoscontrol8;
+ unsigned char res13[0x4];
+ unsigned int qoscontrol9;
+ unsigned char res14[0x4];
+ unsigned int qoscontrol10;
+ unsigned char res15[0x4];
+ unsigned int qoscontrol11;
+ unsigned char res16[0x4];
+ unsigned int qoscontrol12;
+ unsigned char res17[0x4];
+ unsigned int qoscontrol13;
+ unsigned char res18[0x4];
+ unsigned int qoscontrol14;
+ unsigned char res19[0x4];
+ unsigned int qoscontrol15;
+ unsigned char res20[0x14];
+ unsigned int ivcontrol;
+ unsigned int wrtra_config;
+ unsigned int rdlvl_config;
+ unsigned char res21[0x8];
+ unsigned int brbrsvconfig;
+ unsigned int brbqosconfig;
+ unsigned int membaseconfig0;
+ unsigned int membaseconfig1;
+ unsigned char res22[0xc];
+ unsigned int wrlvl_config;
+ unsigned char res23[0xc];
+ unsigned int perevcontrol;
+ unsigned int perev0config;
+ unsigned int perev1config;
+ unsigned int perev2config;
+ unsigned int perev3config;
+ unsigned char res24[0xdebc];
+ unsigned int pmnc_ppc_a;
+ unsigned char res25[0xc];
+ unsigned int cntens_ppc_a;
+ unsigned char res26[0xc];
+ unsigned int cntenc_ppc_a;
+ unsigned char res27[0xc];
+ unsigned int intens_ppc_a;
+ unsigned char res28[0xc];
+ unsigned int intenc_ppc_a;
+ unsigned char res29[0xc];
+ unsigned int flag_ppc_a;
+ unsigned char res30[0xac];
+ unsigned int ccnt_ppc_a;
+ unsigned char res31[0xc];
+ unsigned int pmcnt0_ppc_a;
+ unsigned char res32[0xc];
+ unsigned int pmcnt1_ppc_a;
+ unsigned char res33[0xc];
+ unsigned int pmcnt2_ppc_a;
+ unsigned char res34[0xc];
+ unsigned int pmcnt3_ppc_a;
+};
+
+struct exynos5420_dmc {
+ unsigned int concontrol;
+ unsigned int memcontrol;
+ unsigned int cgcontrol;
+ unsigned char res500[0x4];
+ unsigned int directcmd;
+ unsigned int prechconfig0;
+ unsigned int phycontrol0;
+ unsigned int prechconfig1;
+ unsigned char res1[0x8];
+ unsigned int pwrdnconfig;
+ unsigned int timingpzq;
+ unsigned int timingref;
+ unsigned int timingrow0;
+ unsigned int timingdata0;
+ unsigned int timingpower0;
+ unsigned int phystatus;
+ unsigned int etctiming;
+ unsigned int chipstatus;
+ unsigned char res3[0x8];
+ unsigned int mrstatus;
+ unsigned char res4[0x8];
+ unsigned int qoscontrol0;
+ unsigned char resr5[0x4];
+ unsigned int qoscontrol1;
+ unsigned char res6[0x4];
+ unsigned int qoscontrol2;
+ unsigned char res7[0x4];
+ unsigned int qoscontrol3;
+ unsigned char res8[0x4];
+ unsigned int qoscontrol4;
+ unsigned char res9[0x4];
+ unsigned int qoscontrol5;
+ unsigned char res10[0x4];
+ unsigned int qoscontrol6;
+ unsigned char res11[0x4];
+ unsigned int qoscontrol7;
+ unsigned char res12[0x4];
+ unsigned int qoscontrol8;
+ unsigned char res13[0x4];
+ unsigned int qoscontrol9;
+ unsigned char res14[0x4];
+ unsigned int qoscontrol10;
+ unsigned char res15[0x4];
+ unsigned int qoscontrol11;
+ unsigned char res16[0x4];
+ unsigned int qoscontrol12;
+ unsigned char res17[0x4];
+ unsigned int qoscontrol13;
+ unsigned char res18[0x4];
+ unsigned int qoscontrol14;
+ unsigned char res19[0x4];
+ unsigned int qoscontrol15;
+ unsigned char res20[0x4];
+ unsigned int timing_set_sw;
+ unsigned int timingrow1;
+ unsigned int timingdata1;
+ unsigned int timingpower1;
+ unsigned char res300[0x4];
+ unsigned int wrtra_config;
+ unsigned int rdlvl_config;
+ unsigned char res21[0x4];
+ unsigned int brbrsvcontrol;
+ unsigned int brbrsvconfig;
+ unsigned int brbqosconfig;
+ unsigned char res301[0x14];
+ unsigned int wrlvl_config0;
+ unsigned int wrlvl_config1;
+ unsigned int wrlvl_status;
+ unsigned char res23[0x4];
+ unsigned int ppcclockon;
+ unsigned int perevconfig0;
+ unsigned int perevconfig1;
+ unsigned int perevconfig2;
+ unsigned int perevconfig3;
+ unsigned char res24[0xc];
+ unsigned int control_io_rdata;
+ unsigned char res240[0xc];
+ unsigned int cacal_config0;
+ unsigned int cacal_config1;
+ unsigned int cacal_status;
+ unsigned char res302[0xa4];
+ unsigned int bp_control0;
+ unsigned int bp_config0_r;
+ unsigned int bp_config0_w;
+ unsigned char res303[0x4];
+ unsigned int bp_control1;
+ unsigned int bp_config1_r;
+ unsigned int bp_config1_w;
+ unsigned char res304[0x4];
+ unsigned int bp_control2;
+ unsigned int bp_config2_r;
+ unsigned int bp_config2_w;
+ unsigned char res305[0x4];
+ unsigned int bp_control3;
+ unsigned int bp_config3_r;
+ unsigned int bp_config3_w;
+ unsigned char res306[0xddb4];
+ unsigned int pmnc_ppc;
+ unsigned char res25[0xc];
+ unsigned int cntens_ppc;
+ unsigned char res26[0xc];
+ unsigned int cntenc_ppc;
+ unsigned char res27[0xc];
+ unsigned int intens_ppc;
+ unsigned char res28[0xc];
+ unsigned int intenc_ppc;
+ unsigned char res29[0xc];
+ unsigned int flag_ppc;
+ unsigned char res30[0xac];
+ unsigned int ccnt_ppc;
+ unsigned char res31[0xc];
+ unsigned int pmcnt0_ppc;
+ unsigned char res32[0xc];
+ unsigned int pmcnt1_ppc;
+ unsigned char res33[0xc];
+ unsigned int pmcnt2_ppc;
+ unsigned char res34[0xc];
+ unsigned int pmcnt3_ppc;
+};
+
+struct exynos5_phy_control {
+ unsigned int phy_con0;
+ unsigned int phy_con1;
+ unsigned int phy_con2;
+ unsigned int phy_con3;
+ unsigned int phy_con4;
+ unsigned char res1[4];
+ unsigned int phy_con6;
+ unsigned char res2[4];
+ unsigned int phy_con8;
+ unsigned int phy_con9;
+ unsigned int phy_con10;
+ unsigned char res3[4];
+ unsigned int phy_con12;
+ unsigned int phy_con13;
+ unsigned int phy_con14;
+ unsigned int phy_con15;
+ unsigned int phy_con16;
+ unsigned char res4[4];
+ unsigned int phy_con17;
+ unsigned int phy_con18;
+ unsigned int phy_con19;
+ unsigned int phy_con20;
+ unsigned int phy_con21;
+ unsigned int phy_con22;
+ unsigned int phy_con23;
+ unsigned int phy_con24;
+ unsigned int phy_con25;
+ unsigned int phy_con26;
+ unsigned int phy_con27;
+ unsigned int phy_con28;
+ unsigned int phy_con29;
+ unsigned int phy_con30;
+ unsigned int phy_con31;
+ unsigned int phy_con32;
+ unsigned int phy_con33;
+ unsigned int phy_con34;
+ unsigned int phy_con35;
+ unsigned int phy_con36;
+ unsigned int phy_con37;
+ unsigned int phy_con38;
+ unsigned int phy_con39;
+ unsigned int phy_con40;
+ unsigned int phy_con41;
+ unsigned int phy_con42;
+};
+
+struct exynos5420_phy_control {
+ unsigned int phy_con0;
+ unsigned int phy_con1;
+ unsigned int phy_con2;
+ unsigned int phy_con3;
+ unsigned int phy_con4;
+ unsigned int phy_con5;
+ unsigned int phy_con6;
+ unsigned char res2[0x4];
+ unsigned int phy_con8;
+ unsigned char res5[0x4];
+ unsigned int phy_con10;
+ unsigned int phy_con11;
+ unsigned int phy_con12;
+ unsigned int phy_con13;
+ unsigned int phy_con14;
+ unsigned int phy_con15;
+ unsigned int phy_con16;
+ unsigned char res4[0x4];
+ unsigned int phy_con17;
+ unsigned int phy_con18;
+ unsigned int phy_con19;
+ unsigned int phy_con20;
+ unsigned int phy_con21;
+ unsigned int phy_con22;
+ unsigned int phy_con23;
+ unsigned int phy_con24;
+ unsigned int phy_con25;
+ unsigned int phy_con26;
+ unsigned int phy_con27;
+ unsigned int phy_con28;
+ unsigned int phy_con29;
+ unsigned int phy_con30;
+ unsigned int phy_con31;
+ unsigned int phy_con32;
+ unsigned int phy_con33;
+ unsigned int phy_con34;
+ unsigned char res6[0x8];
+ unsigned int phy_con37;
+ unsigned char res7[0x4];
+ unsigned int phy_con39;
+ unsigned int phy_con40;
+ unsigned int phy_con41;
+ unsigned int phy_con42;
+};
+
+struct exynos5420_tzasc {
+ unsigned char res1[0xf00];
+ unsigned int membaseconfig0;
+ unsigned int membaseconfig1;
+ unsigned char res2[0x8];
+ unsigned int memconfig0;
+ unsigned int memconfig1;
+};
+
+enum ddr_mode {
+ DDR_MODE_DDR2,
+ DDR_MODE_DDR3,
+ DDR_MODE_LPDDR2,
+ DDR_MODE_LPDDR3,
+
+ DDR_MODE_COUNT,
+};
+
+enum mem_manuf {
+ MEM_MANUF_AUTODETECT,
+ MEM_MANUF_ELPIDA,
+ MEM_MANUF_SAMSUNG,
+
+ MEM_MANUF_COUNT,
+};
+
+/* CONCONTROL register fields */
+#define CONCONTROL_DFI_INIT_START_SHIFT 28
+#define CONCONTROL_RD_FETCH_SHIFT 12
+#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
+#define CONCONTROL_AREF_EN_SHIFT 5
+#define CONCONTROL_UPDATE_MODE (1 << 3)
+
+/* PRECHCONFIG register field */
+#define PRECHCONFIG_TP_CNT_SHIFT 24
+
+/* PWRDNCONFIG register field */
+#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0
+#define PWRDNCONFIG_DSREF_CYC_SHIFT 16
+
+/* PHY_CON0 register fields */
+#define PHY_CON0_T_WRRDCMD_SHIFT 17
+#define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
+#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
+#define PHY_CON0_CTRL_DDR_MODE_MASK 0x3
+
+/* PHY_CON1 register fields */
+#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0
+
+/* PHY_CON4 rgister fields */
+#define PHY_CON10_CTRL_OFFSETR3 (1 << 24)
+
+/* PHY_CON12 register fields */
+#define PHY_CON12_CTRL_START_POINT_SHIFT 24
+#define PHY_CON12_CTRL_INC_SHIFT 16
+#define PHY_CON12_CTRL_FORCE_SHIFT 8
+#define PHY_CON12_CTRL_START_SHIFT 6
+#define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT)
+#define PHY_CON12_CTRL_DLL_ON_SHIFT 5
+#define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
+#define PHY_CON12_CTRL_REF_SHIFT 1
+
+/* PHY_CON16 register fields */
+#define PHY_CON16_ZQ_MODE_DDS_SHIFT 24
+#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
+#define PHY_CON16_ZQ_MODE_TERM_MASK (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19)
+
+/* PHY_CON42 register fields */
+#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
+#define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
+
+#define PHY_CON42_CTRL_RDLAT_SHIFT 0
+#define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
+
+#endif
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_DP_H_
+#define __ASM_ARM_ARCH_DP_H_
+
+#ifndef __ASSEMBLY__
+
+struct exynos_dp {
+ unsigned char res1[0x10];
+ unsigned int tx_version;
+ unsigned int tx_sw_reset;
+ unsigned int func_en1;
+ unsigned int func_en2;
+ unsigned int video_ctl1;
+ unsigned int video_ctl2;
+ unsigned int video_ctl3;
+ unsigned int video_ctl4;
+ unsigned int color_blue_cb;
+ unsigned int color_green_y;
+ unsigned int color_red_cr;
+ unsigned int video_ctl8;
+ unsigned char res2[0x4];
+ unsigned int video_ctl10;
+ unsigned int total_ln_cfg_l;
+ unsigned int total_ln_cfg_h;
+ unsigned int active_ln_cfg_l;
+ unsigned int active_ln_cfg_h;
+ unsigned int vfp_cfg;
+ unsigned int vsw_cfg;
+ unsigned int vbp_cfg;
+ unsigned int total_pix_cfg_l;
+ unsigned int total_pix_cfg_h;
+ unsigned int active_pix_cfg_l;
+ unsigned int active_pix_cfg_h;
+ unsigned int hfp_cfg_l;
+ unsigned int hfp_cfg_h;
+ unsigned int hsw_cfg_l;
+ unsigned int hsw_cfg_h;
+ unsigned int hbp_cfg_l;
+ unsigned int hbp_cfg_h;
+ unsigned int video_status;
+ unsigned int total_ln_sta_l;
+ unsigned int total_ln_sta_h;
+ unsigned int active_ln_sta_l;
+ unsigned int active_ln_sta_h;
+
+ unsigned int vfp_sta;
+ unsigned int vsw_sta;
+ unsigned int vbp_sta;
+
+ unsigned int total_pix_sta_l;
+ unsigned int total_pix_sta_h;
+ unsigned int active_pix_sta_l;
+ unsigned int active_pix_sta_h;
+
+ unsigned int hfp_sta_l;
+ unsigned int hfp_sta_h;
+ unsigned int hsw_sta_l;
+ unsigned int hsw_sta_h;
+ unsigned int hbp_sta_l;
+ unsigned int hbp_sta_h;
+
+ unsigned char res3[0x288];
+
+ unsigned int lane_map;
+ unsigned char res4[0x10];
+ unsigned int analog_ctl1;
+ unsigned int analog_ctl2;
+ unsigned int analog_ctl3;
+
+ unsigned int pll_filter_ctl1;
+ unsigned int amp_tuning_ctl;
+ unsigned char res5[0xc];
+
+ unsigned int aux_hw_retry_ctl;
+ unsigned char res6[0x2c];
+ unsigned int int_state;
+ unsigned int common_int_sta1;
+ unsigned int common_int_sta2;
+ unsigned int common_int_sta3;
+ unsigned int common_int_sta4;
+ unsigned char res7[0x8];
+
+ unsigned int int_sta;
+ unsigned char res8[0x1c];
+ unsigned int int_ctl;
+ unsigned char res9[0x200];
+ unsigned int sys_ctl1;
+ unsigned int sys_ctl2;
+ unsigned int sys_ctl3;
+ unsigned int sys_ctl4;
+ unsigned int vid_ctl;
+ unsigned char res10[0x2c];
+ unsigned int pkt_send_ctl;
+ unsigned char res[0x4];
+ unsigned int hdcp_ctl;
+ unsigned char res11[0x34];
+ unsigned int link_bw_set;
+
+ unsigned int lane_count_set;
+ unsigned int training_ptn_set;
+ unsigned int ln0_link_training_ctl;
+ unsigned int ln1_link_training_ctl;
+ unsigned int ln2_link_training_ctl;
+ unsigned int ln3_link_training_ctl;
+ unsigned int dn_spread_ctl;
+ unsigned int hw_link_training_ctl;
+ unsigned char res12[0x1c];
+
+ unsigned int debug_ctl;
+ unsigned int hpd_deglitch_l;
+ unsigned int hpd_deglitch_h;
+
+ unsigned char res13[0x14];
+ unsigned int link_debug_ctl;
+
+ unsigned char res14[0x1c];
+
+ unsigned int m_vid0;
+ unsigned int m_vid1;
+ unsigned int m_vid2;
+ unsigned int n_vid0;
+ unsigned int n_vid1;
+ unsigned int n_vid2;
+ unsigned int m_vid_mon;
+ unsigned int pll_ctl;
+ unsigned int phy_pd;
+ unsigned int phy_test;
+ unsigned char res15[0x8];
+
+ unsigned int video_fifo_thrd;
+ unsigned char res16[0x8];
+ unsigned int audio_margin;
+
+ unsigned int dn_spread_ctl1;
+ unsigned int dn_spread_ctl2;
+ unsigned char res17[0x18];
+ unsigned int m_cal_ctl;
+ unsigned int m_vid_gen_filter_th;
+ unsigned char res18[0x10];
+ unsigned int m_aud_gen_filter_th;
+ unsigned char res50[0x4];
+
+ unsigned int aux_ch_sta;
+ unsigned int aux_err_num;
+ unsigned int aux_ch_defer_ctl;
+ unsigned int aux_rx_comm;
+ unsigned int buffer_data_ctl;
+
+ unsigned int aux_ch_ctl1;
+ unsigned int aux_addr_7_0;
+ unsigned int aux_addr_15_8;
+ unsigned int aux_addr_19_16;
+ unsigned int aux_ch_ctl2;
+ unsigned char res19[0x18];
+ unsigned int buf_data0;
+ unsigned char res20[0x3c];
+
+ unsigned int soc_general_ctl;
+ unsigned char res21[0x8c];
+ unsigned int crc_con;
+ unsigned int crc_result;
+ unsigned char res22[0x8];
+
+ unsigned int common_int_mask1;
+ unsigned int common_int_mask2;
+ unsigned int common_int_mask3;
+ unsigned int common_int_mask4;
+ unsigned int int_sta_mask1;
+ unsigned int int_sta_mask2;
+ unsigned int int_sta_mask3;
+ unsigned int int_sta_mask4;
+ unsigned int int_sta_mask;
+ unsigned int crc_result2;
+ unsigned int scrambler_reset_cnt;
+
+ unsigned int pn_inv;
+ unsigned int psr_config;
+ unsigned int psr_command0;
+ unsigned int psr_command1;
+ unsigned int psr_crc_mon0;
+ unsigned int psr_crc_mon1;
+
+ unsigned char res24[0x30];
+ unsigned int phy_bist_ctrl;
+ unsigned char res25[0xc];
+ unsigned int phy_ctrl;
+ unsigned char res26[0x1c];
+ unsigned int test_pattern_gen_en;
+ unsigned int test_pattern_gen_ctrl;
+};
+
+#endif /* __ASSEMBLY__ */
+
+/* For DP VIDEO CTL 1 */
+#define VIDEO_EN_MASK (0x01 << 7)
+#define VIDEO_MUTE_MASK (0x01 << 6)
+
+/* For DP VIDEO CTL 4 */
+#define VIDEO_BIST_MASK (0x1 << 3)
+
+/* EXYNOS_DP_ANALOG_CTL_1 */
+#define SEL_BG_NEW_BANDGAP (0x0 << 6)
+#define SEL_BG_INTERNAL_RESISTOR (0x1 << 6)
+#define TX_TERMINAL_CTRL_73_OHM (0x0 << 4)
+#define TX_TERMINAL_CTRL_61_OHM (0x1 << 4)
+#define TX_TERMINAL_CTRL_50_OHM (0x2 << 4)
+#define TX_TERMINAL_CTRL_45_OHM (0x3 << 4)
+#define SWING_A_30PER_G_INCREASE (0x1 << 3)
+#define SWING_A_30PER_G_NORMAL (0x0 << 3)
+
+/* EXYNOS_DP_ANALOG_CTL_2 */
+#define CPREG_BLEED (0x1 << 4)
+#define SEL_24M (0x1 << 3)
+#define TX_DVDD_BIT_1_0000V (0x3 << 0)
+#define TX_DVDD_BIT_1_0625V (0x4 << 0)
+#define TX_DVDD_BIT_1_1250V (0x5 << 0)
+
+/* EXYNOS_DP_ANALOG_CTL_3 */
+#define DRIVE_DVDD_BIT_1_0000V (0x3 << 5)
+#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5)
+#define DRIVE_DVDD_BIT_1_1250V (0x5 << 5)
+#define SEL_CURRENT_DEFAULT (0x0 << 3)
+#define VCO_BIT_000_MICRO (0x0 << 0)
+#define VCO_BIT_200_MICRO (0x1 << 0)
+#define VCO_BIT_300_MICRO (0x2 << 0)
+#define VCO_BIT_400_MICRO (0x3 << 0)
+#define VCO_BIT_500_MICRO (0x4 << 0)
+#define VCO_BIT_600_MICRO (0x5 << 0)
+#define VCO_BIT_700_MICRO (0x6 << 0)
+#define VCO_BIT_900_MICRO (0x7 << 0)
+
+/* EXYNOS_DP_PLL_FILTER_CTL_1 */
+#define PD_RING_OSC (0x1 << 6)
+#define AUX_TERMINAL_CTRL_52_OHM (0x3 << 4)
+#define AUX_TERMINAL_CTRL_69_OHM (0x2 << 4)
+#define AUX_TERMINAL_CTRL_102_OHM (0x1 << 4)
+#define AUX_TERMINAL_CTRL_200_OHM (0x0 << 4)
+#define TX_CUR1_1X (0x0 << 2)
+#define TX_CUR1_2X (0x1 << 2)
+#define TX_CUR1_3X (0x2 << 2)
+#define TX_CUR_1_MA (0x0 << 0)
+#define TX_CUR_2_MA (0x1 << 0)
+#define TX_CUR_3_MA (0x2 << 0)
+#define TX_CUR_4_MA (0x3 << 0)
+
+/* EXYNOS_DP_PLL_FILTER_CTL_2 */
+#define CH3_AMP_0_MV (0x3 << 12)
+#define CH2_AMP_0_MV (0x3 << 8)
+#define CH1_AMP_0_MV (0x3 << 4)
+#define CH0_AMP_0_MV (0x3 << 0)
+
+/* EXYNOS_DP_PLL_CTL */
+#define DP_PLL_PD (0x1 << 7)
+#define DP_PLL_RESET (0x1 << 6)
+#define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4)
+#define DP_PLL_REF_BIT_1_1250V (0x5 << 0)
+#define DP_PLL_REF_BIT_1_2500V (0x7 << 0)
+
+/* EXYNOS_DP_INT_CTL */
+#define SOFT_INT_CTRL (0x1 << 2)
+#define INT_POL (0x1 << 0)
+
+/* DP TX SW RESET */
+#define RESET_DP_TX (0x01 << 0)
+
+/* DP FUNC_EN_1 */
+#define MASTER_VID_FUNC_EN_N (0x1 << 7)
+#define SLAVE_VID_FUNC_EN_N (0x1 << 5)
+#define AUD_FIFO_FUNC_EN_N (0x1 << 4)
+#define AUD_FUNC_EN_N (0x1 << 3)
+#define HDCP_FUNC_EN_N (0x1 << 2)
+#define CRC_FUNC_EN_N (0x1 << 1)
+#define SW_FUNC_EN_N (0x1 << 0)
+
+/* DP FUNC_EN_2 */
+#define SSC_FUNC_EN_N (0x1 << 7)
+#define AUX_FUNC_EN_N (0x1 << 2)
+#define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
+#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
+
+/* EXYNOS_DP_PHY_PD */
+#define PHY_PD (0x1 << 5)
+#define AUX_PD (0x1 << 4)
+#define CH3_PD (0x1 << 3)
+#define CH2_PD (0x1 << 2)
+#define CH1_PD (0x1 << 1)
+#define CH0_PD (0x1 << 0)
+
+/* EXYNOS_DP_COMMON_INT_STA_1 */
+#define VSYNC_DET (0x1 << 7)
+#define PLL_LOCK_CHG (0x1 << 6)
+#define SPDIF_ERR (0x1 << 5)
+#define SPDIF_UNSTBL (0x1 << 4)
+#define VID_FORMAT_CHG (0x1 << 3)
+#define AUD_CLK_CHG (0x1 << 2)
+#define VID_CLK_CHG (0x1 << 1)
+#define SW_INT (0x1 << 0)
+
+/* EXYNOS_DP_DEBUG_CTL */
+#define PLL_LOCK (0x1 << 4)
+#define F_PLL_LOCK (0x1 << 3)
+#define PLL_LOCK_CTRL (0x1 << 2)
+
+/* EXYNOS_DP_FUNC_EN_2 */
+#define SSC_FUNC_EN_N (0x1 << 7)
+#define AUX_FUNC_EN_N (0x1 << 2)
+#define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
+#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
+
+/* EXYNOS_DP_COMMON_INT_STA_4 */
+#define PSR_ACTIVE (0x1 << 7)
+#define PSR_INACTIVE (0x1 << 6)
+#define SPDIF_BI_PHASE_ERR (0x1 << 5)
+#define HOTPLUG_CHG (0x1 << 2)
+#define HPD_LOST (0x1 << 1)
+#define PLUG (0x1 << 0)
+
+/* EXYNOS_DP_INT_STA */
+#define INT_HPD (0x1 << 6)
+#define HW_TRAINING_FINISH (0x1 << 5)
+#define RPLY_RECEIV (0x1 << 1)
+#define AUX_ERR (0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_3 */
+#define HPD_STATUS (0x1 << 6)
+#define F_HPD (0x1 << 5)
+#define HPD_CTRL (0x1 << 4)
+#define HDCP_RDY (0x1 << 3)
+#define STRM_VALID (0x1 << 2)
+#define F_VALID (0x1 << 1)
+#define VALID_CTRL (0x1 << 0)
+
+/* EXYNOS_DP_AUX_HW_RETRY_CTL */
+#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8)
+#define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3)
+#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3)
+#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3)
+#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3)
+#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3)
+#define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0)
+
+/* EXYNOS_DP_AUX_CH_DEFER_CTL */
+#define DEFER_CTRL_EN (0x1 << 7)
+#define DEFER_COUNT(x) (((x) & 0x7f) << 0)
+
+#define COMMON_INT_MASK_1 (0)
+#define COMMON_INT_MASK_2 (0)
+#define COMMON_INT_MASK_3 (0)
+#define COMMON_INT_MASK_4 (0)
+#define INT_STA_MASK (0)
+
+/* EXYNOS_DP_BUFFER_DATA_CTL */
+#define BUF_CLR (0x1 << 7)
+#define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0)
+
+/* EXYNOS_DP_AUX_ADDR_7_0 */
+#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
+
+/* EXYNOS_DP_AUX_ADDR_15_8 */
+#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
+
+/* EXYNOS_DP_AUX_ADDR_19_16 */
+#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
+
+/* EXYNOS_DP_AUX_CH_CTL_1 */
+#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4)
+#define AUX_TX_COMM_MASK (0xf << 0)
+#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3)
+#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3)
+#define AUX_TX_COMM_MOT (0x1 << 2)
+#define AUX_TX_COMM_WRITE (0x0 << 0)
+#define AUX_TX_COMM_READ (0x1 << 0)
+
+/* EXYNOS_DP_AUX_CH_CTL_2 */
+#define ADDR_ONLY (0x1 << 1)
+#define AUX_EN (0x1 << 0)
+
+/* EXYNOS_DP_AUX_CH_STA */
+#define AUX_BUSY (0x1 << 4)
+#define AUX_STATUS_MASK (0xf << 0)
+
+/* EXYNOS_DP_AUX_RX_COMM */
+#define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
+#define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
+
+/* EXYNOS_DP_PHY_TEST */
+#define MACRO_RST (0x1 << 5)
+#define CH1_TEST (0x1 << 1)
+#define CH0_TEST (0x1 << 0)
+
+/* EXYNOS_DP_TRAINING_PTN_SET */
+#define SCRAMBLER_TYPE (0x1 << 9)
+#define HW_LINK_TRAINING_PATTERN (0x1 << 8)
+#define SCRAMBLING_DISABLE (0x1 << 5)
+#define SCRAMBLING_ENABLE (0x0 << 5)
+#define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2)
+#define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2)
+#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2)
+#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2)
+#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0)
+#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0)
+#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0)
+#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0)
+
+/* EXYNOS_DP_TOTAL_LINE_CFG */
+#define TOTAL_LINE_CFG_L(x) ((x) & 0xff)
+#define TOTAL_LINE_CFG_H(x) ((((x) >> 8)) & 0xff)
+#define ACTIVE_LINE_CFG_L(x) ((x) & 0xff)
+#define ACTIVE_LINE_CFG_H(x) (((x) >> 8) & 0xff)
+#define TOTAL_PIXEL_CFG_L(x) ((x) & 0xff)
+#define TOTAL_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff)
+#define ACTIVE_PIXEL_CFG_L(x) ((x) & 0xff)
+#define ACTIVE_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff)
+
+#define H_F_PORCH_CFG_L(x) ((x) & 0xff)
+#define H_F_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
+#define H_SYNC_PORCH_CFG_L(x) ((x) & 0xff)
+#define H_SYNC_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
+#define H_B_PORCH_CFG_L(x) ((x) & 0xff)
+#define H_B_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
+
+/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
+#define MAX_PRE_EMPHASIS_REACH_0 (0x1 << 5)
+#define PRE_EMPHASIS_SET_0_SET(x) (((x) & 0x3) << 3)
+#define PRE_EMPHASIS_SET_0_GET(x) (((x) >> 3) & 0x3)
+#define PRE_EMPHASIS_SET_0_MASK (0x3 << 3)
+#define PRE_EMPHASIS_SET_0_SHIFT (3)
+#define PRE_EMPHASIS_SET_0_LEVEL_3 (0x3 << 3)
+#define PRE_EMPHASIS_SET_0_LEVEL_2 (0x2 << 3)
+#define PRE_EMPHASIS_SET_0_LEVEL_1 (0x1 << 3)
+#define PRE_EMPHASIS_SET_0_LEVEL_0 (0x0 << 3)
+#define MAX_DRIVE_CURRENT_REACH_0 (0x1 << 2)
+#define DRIVE_CURRENT_SET_0_MASK (0x3 << 0)
+#define DRIVE_CURRENT_SET_0_SET(x) (((x) & 0x3) << 0)
+#define DRIVE_CURRENT_SET_0_GET(x) (((x) >> 0) & 0x3)
+#define DRIVE_CURRENT_SET_0_LEVEL_3 (0x3 << 0)
+#define DRIVE_CURRENT_SET_0_LEVEL_2 (0x2 << 0)
+#define DRIVE_CURRENT_SET_0_LEVEL_1 (0x1 << 0)
+#define DRIVE_CURRENT_SET_0_LEVEL_0 (0x0 << 0)
+
+/* EXYNOS_DP_LN1_LINK_TRAINING_CTL */
+#define MAX_PRE_EMPHASIS_REACH_1 (0x1 << 5)
+#define PRE_EMPHASIS_SET_1_SET(x) (((x) & 0x3) << 3)
+#define PRE_EMPHASIS_SET_1_GET(x) (((x) >> 3) & 0x3)
+#define PRE_EMPHASIS_SET_1_MASK (0x3 << 3)
+#define PRE_EMPHASIS_SET_1_SHIFT (3)
+#define PRE_EMPHASIS_SET_1_LEVEL_3 (0x3 << 3)
+#define PRE_EMPHASIS_SET_1_LEVEL_2 (0x2 << 3)
+#define PRE_EMPHASIS_SET_1_LEVEL_1 (0x1 << 3)
+#define PRE_EMPHASIS_SET_1_LEVEL_0 (0x0 << 3)
+#define MAX_DRIVE_CURRENT_REACH_1 (0x1 << 2)
+#define DRIVE_CURRENT_SET_1_MASK (0x3 << 0)
+#define DRIVE_CURRENT_SET_1_SET(x) (((x) & 0x3) << 0)
+#define DRIVE_CURRENT_SET_1_GET(x) (((x) >> 0) & 0x3)
+#define DRIVE_CURRENT_SET_1_LEVEL_3 (0x3 << 0)
+#define DRIVE_CURRENT_SET_1_LEVEL_2 (0x2 << 0)
+#define DRIVE_CURRENT_SET_1_LEVEL_1 (0x1 << 0)
+#define DRIVE_CURRENT_SET_1_LEVEL_0 (0x0 << 0)
+
+/* EXYNOS_DP_LN2_LINK_TRAINING_CTL */
+#define MAX_PRE_EMPHASIS_REACH_2 (0x1 << 5)
+#define PRE_EMPHASIS_SET_2_SET(x) (((x) & 0x3) << 3)
+#define PRE_EMPHASIS_SET_2_GET(x) (((x) >> 3) & 0x3)
+#define PRE_EMPHASIS_SET_2_MASK (0x3 << 3)
+#define PRE_EMPHASIS_SET_2_SHIFT (3)
+#define PRE_EMPHASIS_SET_2_LEVEL_3 (0x3 << 3)
+#define PRE_EMPHASIS_SET_2_LEVEL_2 (0x2 << 3)
+#define PRE_EMPHASIS_SET_2_LEVEL_1 (0x1 << 3)
+#define PRE_EMPHASIS_SET_2_LEVEL_0 (0x0 << 3)
+#define MAX_DRIVE_CURRENT_REACH_2 (0x1 << 2)
+#define DRIVE_CURRENT_SET_2_MASK (0x3 << 0)
+#define DRIVE_CURRENT_SET_2_SET(x) (((x) & 0x3) << 0)
+#define DRIVE_CURRENT_SET_2_GET(x) (((x) >> 0) & 0x3)
+#define DRIVE_CURRENT_SET_2_LEVEL_3 (0x3 << 0)
+#define DRIVE_CURRENT_SET_2_LEVEL_2 (0x2 << 0)
+#define DRIVE_CURRENT_SET_2_LEVEL_1 (0x1 << 0)
+#define DRIVE_CURRENT_SET_2_LEVEL_0 (0x0 << 0)
+
+/* EXYNOS_DP_LN3_LINK_TRAINING_CTL */
+#define MAX_PRE_EMPHASIS_REACH_3 (0x1 << 5)
+#define PRE_EMPHASIS_SET_3_SET(x) (((x) & 0x3) << 3)
+#define PRE_EMPHASIS_SET_3_GET(x) (((x) >> 3) & 0x3)
+#define PRE_EMPHASIS_SET_3_MASK (0x3 << 3)
+#define PRE_EMPHASIS_SET_3_SHIFT (3)
+#define PRE_EMPHASIS_SET_3_LEVEL_3 (0x3 << 3)
+#define PRE_EMPHASIS_SET_3_LEVEL_2 (0x2 << 3)
+#define PRE_EMPHASIS_SET_3_LEVEL_1 (0x1 << 3)
+#define PRE_EMPHASIS_SET_3_LEVEL_0 (0x0 << 3)
+#define MAX_DRIVE_CURRENT_REACH_3 (0x1 << 2)
+#define DRIVE_CURRENT_SET_3_MASK (0x3 << 0)
+#define DRIVE_CURRENT_SET_3_SET(x) (((x) & 0x3) << 0)
+#define DRIVE_CURRENT_SET_3_GET(x) (((x) >> 0) & 0x3)
+#define DRIVE_CURRENT_SET_3_LEVEL_3 (0x3 << 0)
+#define DRIVE_CURRENT_SET_3_LEVEL_2 (0x2 << 0)
+#define DRIVE_CURRENT_SET_3_LEVEL_1 (0x1 << 0)
+#define DRIVE_CURRENT_SET_3_LEVEL_0 (0x0 << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_10 */
+#define FORMAT_SEL (0x1 << 4)
+#define INTERACE_SCAN_CFG (0x1 << 2)
+#define INTERACE_SCAN_CFG_SHIFT (2)
+#define VSYNC_POLARITY_CFG (0x1 << 1)
+#define V_S_POLARITY_CFG_SHIFT (1)
+#define HSYNC_POLARITY_CFG (0x1 << 0)
+#define H_S_POLARITY_CFG_SHIFT (0)
+
+/* EXYNOS_DP_SOC_GENERAL_CTL */
+#define AUDIO_MODE_SPDIF_MODE (0x1 << 8)
+#define AUDIO_MODE_MASTER_MODE (0x0 << 8)
+#define MASTER_VIDEO_INTERLACE_EN (0x1 << 4)
+#define VIDEO_MASTER_CLK_SEL (0x1 << 2)
+#define VIDEO_MASTER_MODE_EN (0x1 << 1)
+#define VIDEO_MODE_MASK (0x1 << 0)
+#define VIDEO_MODE_SLAVE_MODE (0x1 << 0)
+#define VIDEO_MODE_MASTER_MODE (0x0 << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_1 */
+#define VIDEO_EN (0x1 << 7)
+#define HDCP_VIDEO_MUTE (0x1 << 6)
+
+/* EXYNOS_DP_VIDEO_CTL_2 */
+#define IN_D_RANGE_MASK (0x1 << 7)
+#define IN_D_RANGE_SHIFT (7)
+#define IN_D_RANGE_CEA (0x1 << 7)
+#define IN_D_RANGE_VESA (0x0 << 7)
+#define IN_BPC_MASK (0x7 << 4)
+#define IN_BPC_SHIFT (4)
+#define IN_BPC_12_BITS (0x3 << 4)
+#define IN_BPC_10_BITS (0x2 << 4)
+#define IN_BPC_8_BITS (0x1 << 4)
+#define IN_BPC_6_BITS (0x0 << 4)
+#define IN_COLOR_F_MASK (0x3 << 0)
+#define IN_COLOR_F_SHIFT (0)
+#define IN_COLOR_F_YCBCR444 (0x2 << 0)
+#define IN_COLOR_F_YCBCR422 (0x1 << 0)
+#define IN_COLOR_F_RGB (0x0 << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_3 */
+#define IN_YC_COEFFI_MASK (0x1 << 7)
+#define IN_YC_COEFFI_SHIFT (7)
+#define IN_YC_COEFFI_ITU709 (0x1 << 7)
+#define IN_YC_COEFFI_ITU601 (0x0 << 7)
+#define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4)
+#define VID_CHK_UPDATE_TYPE_SHIFT (4)
+#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4)
+#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4)
+
+/* EXYNOS_DP_TEST_PATTERN_GEN_EN */
+#define TEST_PATTERN_GEN_EN (0x1 << 0)
+#define TEST_PATTERN_GEN_DIS (0x0 << 0)
+
+/* EXYNOS_DP_TEST_PATTERN_GEN_CTRL */
+#define TEST_PATTERN_MODE_COLOR_SQUARE (0x3 << 0)
+#define TEST_PATTERN_MODE_BALCK_WHITE_V_LINES (0x2 << 0)
+#define TEST_PATTERN_MODE_COLOR_RAMP (0x1 << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_4 */
+#define BIST_EN (0x1 << 3)
+#define BIST_WIDTH_MASK (0x1 << 2)
+#define BIST_WIDTH_BAR_32_PIXEL (0x0 << 2)
+#define BIST_WIDTH_BAR_64_PIXEL (0x1 << 2)
+#define BIST_TYPE_MASK (0x3 << 0)
+#define BIST_TYPE_COLOR_BAR (0x0 << 0)
+#define BIST_TYPE_WHITE_GRAY_BLACK_BAR (0x1 << 0)
+#define BIST_TYPE_MOBILE_WHITE_BAR (0x2 << 0)
+
+/* EXYNOS_DP_SYS_CTL_1 */
+#define DET_STA (0x1 << 2)
+#define FORCE_DET (0x1 << 1)
+#define DET_CTRL (0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_2 */
+#define CHA_CRI(x) (((x) & 0xf) << 4)
+#define CHA_STA (0x1 << 2)
+#define FORCE_CHA (0x1 << 1)
+#define CHA_CTRL (0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_3 */
+#define HPD_STATUS (0x1 << 6)
+#define F_HPD (0x1 << 5)
+#define HPD_CTRL (0x1 << 4)
+#define HDCP_RDY (0x1 << 3)
+#define STRM_VALID (0x1 << 2)
+#define F_VALID (0x1 << 1)
+#define VALID_CTRL (0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_4 */
+#define FIX_M_AUD (0x1 << 4)
+#define ENHANCED (0x1 << 3)
+#define FIX_M_VID (0x1 << 2)
+#define M_VID_UPDATE_CTRL (0x3 << 0)
+
+/* EXYNOS_M_VID_X */
+#define M_VID0_CFG(x) ((x) & 0xff)
+#define M_VID1_CFG(x) (((x) >> 8) & 0xff)
+#define M_VID2_CFG(x) (((x) >> 16) & 0xff)
+
+/* EXYNOS_M_VID_X */
+#define N_VID0_CFG(x) ((x) & 0xff)
+#define N_VID1_CFG(x) (((x) >> 8) & 0xff)
+#define N_VID2_CFG(x) (((x) >> 16) & 0xff)
+
+/* DPCD_TRAINING_PATTERN_SET */
+#define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
+#define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
+#define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
+#define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
+#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
+
+/* Definition for DPCD Register */
+#define DPCD_DPCD_REV (0x0000)
+#define DPCD_MAX_LINK_RATE (0x0001)
+#define DPCD_MAX_LANE_COUNT (0x0002)
+#define DPCD_LINK_BW_SET (0x0100)
+#define DPCD_LANE_COUNT_SET (0x0101)
+#define DPCD_TRAINING_PATTERN_SET (0x0102)
+#define DPCD_TRAINING_LANE0_SET (0x0103)
+#define DPCD_LANE0_1_STATUS (0x0202)
+#define DPCD_LN_ALIGN_UPDATED (0x0204)
+#define DPCD_ADJUST_REQUEST_LANE0_1 (0x0206)
+#define DPCD_ADJUST_REQUEST_LANE2_3 (0x0207)
+#define DPCD_TEST_REQUEST (0x0218)
+#define DPCD_TEST_RESPONSE (0x0260)
+#define DPCD_TEST_EDID_CHECKSUM (0x0261)
+#define DPCD_SINK_POWER_STATE (0x0600)
+
+/* DPCD_TEST_REQUEST */
+#define DPCD_TEST_EDID_READ (0x1 << 2)
+
+/* DPCD_TEST_RESPONSE */
+#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
+
+/* DPCD_SINK_POWER_STATE */
+#define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
+#define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
+
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR (0x50)
+#define I2C_E_EDID_DEVICE_ADDR (0x30)
+#define EDID_BLOCK_LENGTH (0x80)
+#define EDID_HEADER_PATTERN (0x00)
+#define EDID_EXTENSION_FLAG (0x7e)
+#define EDID_CHECKSUM (0x7f)
+
+/* DPCD_LANE0_1_STATUS */
+#define DPCD_LANE1_SYMBOL_LOCKED (0x1 << 6)
+#define DPCD_LANE1_CHANNEL_EQ_DONE (0x1 << 5)
+#define DPCD_LANE1_CR_DONE (0x1 << 4)
+#define DPCD_LANE0_SYMBOL_LOCKED (0x1 << 2)
+#define DPCD_LANE0_CHANNEL_EQ_DONE (0x1 << 1)
+#define DPCD_LANE0_CR_DONE (0x1 << 0)
+
+/* DPCD_ADJUST_REQUEST_LANE0_1 */
+#define DPCD_PRE_EMPHASIS_LANE1_MASK (0x3 << 6)
+#define DPCD_PRE_EMPHASIS_LANE1(x) (((x) >> 6) & 0x3)
+#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_3 (0x3 << 6)
+#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_2 (0x2 << 6)
+#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_1 (0x1 << 6)
+#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_0 (0x0 << 6)
+#define DPCD_VOLTAGE_SWING_LANE1_MASK (0x3 << 4)
+#define DPCD_VOLTAGE_SWING_LANE1(x) (((x) >> 4) & 0x3)
+#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_3 (0x3 << 4)
+#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_2 (0x2 << 4)
+#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_1 (0x1 << 4)
+#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_0 (0x0 << 4)
+#define DPCD_PRE_EMPHASIS_LANE0_MASK (0x3 << 2)
+#define DPCD_PRE_EMPHASIS_LANE0(x) (((x) >> 2) & 0x3)
+#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_3 (0x3 << 2)
+#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_2 (0x2 << 2)
+#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_1 (0x1 << 2)
+#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_0 (0x0 << 2)
+#define DPCD_VOLTAGE_SWING_LANE0_MASK (0x3 << 0)
+#define DPCD_VOLTAGE_SWING_LANE0(x) (((x) >> 0) & 0x3)
+#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_3 (0x3 << 0)
+#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_2 (0x2 << 0)
+#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_1 (0x1 << 0)
+#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_0 (0x0 << 0)
+
+/* DPCD_ADJUST_REQUEST_LANE2_3 */
+#define DPCD_PRE_EMPHASIS_LANE2_MASK (0x3 << 6)
+#define DPCD_PRE_EMPHASIS_LANE2(x) (((x) >> 6) & 0x3)
+#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_3 (0x3 << 6)
+#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_2 (0x2 << 6)
+#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_1 (0x1 << 6)
+#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_0 (0x0 << 6)
+#define DPCD_VOLTAGE_SWING_LANE2_MASK (0x3 << 4)
+#define DPCD_VOLTAGE_SWING_LANE2(x) (((x) >> 4) & 0x3)
+#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_3 (0x3 << 4)
+#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_2 (0x2 << 4)
+#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_1 (0x1 << 4)
+#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_0 (0x0 << 4)
+#define DPCD_PRE_EMPHASIS_LANE3_MASK (0x3 << 2)
+#define DPCD_PRE_EMPHASIS_LANE3(x) (((x) >> 2) & 0x3)
+#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_3 (0x3 << 2)
+#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_2 (0x2 << 2)
+#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_1 (0x1 << 2)
+#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_0 (0x0 << 2)
+#define DPCD_VOLTAGE_SWING_LANE3_MASK (0x3 << 0)
+#define DPCD_VOLTAGE_SWING_LANE3(x) (((x) >> 0) & 0x3)
+#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_3 (0x3 << 0)
+#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_2 (0x2 << 0)
+#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_1 (0x1 << 0)
+#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_0 (0x0 << 0)
+
+/* DPCD_LANE_COUNT_SET */
+#define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
+#define DPCD_LN_COUNT_SET(x) ((x) & 0x1f)
+
+/* DPCD_LANE_ALIGN__STATUS_UPDATED */
+#define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
+#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
+#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
+
+/* DPCD_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_3 (0x3 << 3)
+#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_2 (0x2 << 3)
+#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_1 (0x1 << 3)
+#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 (0x0 << 3)
+#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_3 (0x3 << 0)
+#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_2 (0x2 << 0)
+#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_1 (0x1 << 0)
+#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0 (0x0 << 0)
+
+#define DPCD_REQ_ADJ_SWING (0x00)
+#define DPCD_REQ_ADJ_EMPHASIS (0x01)
+
+#define DP_LANE_STAT_CR_DONE (0x01 << 0)
+#define DP_LANE_STAT_CE_DONE (0x01 << 1)
+#define DP_LANE_STAT_SYM_LOCK (0x01 << 2)
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DP_INFO_H
+#define _DP_INFO_H
+
+#define msleep(a) udelay(a * 1000)
+
+#define DP_TIMEOUT_LOOP_COUNT 100
+#define MAX_CR_LOOP 5
+#define MAX_EQ_LOOP 4
+
+#define EXYNOS_DP_SUCCESS 0
+
+enum {
+ DP_DISABLE,
+ DP_ENABLE,
+};
+
+struct edp_disp_info {
+ char *name;
+ unsigned int h_total;
+ unsigned int h_res;
+ unsigned int h_sync_width;
+ unsigned int h_back_porch;
+ unsigned int h_front_porch;
+ unsigned int v_total;
+ unsigned int v_res;
+ unsigned int v_sync_width;
+ unsigned int v_back_porch;
+ unsigned int v_front_porch;
+
+ unsigned int v_sync_rate;
+};
+
+struct edp_link_train_info {
+ unsigned int lt_status;
+
+ unsigned int ep_loop;
+ unsigned int cr_loop[4];
+
+};
+
+struct edp_video_info {
+ unsigned int master_mode;
+ unsigned int bist_mode;
+ unsigned int bist_pattern;
+
+ unsigned int h_sync_polarity;
+ unsigned int v_sync_polarity;
+ unsigned int interlaced;
+
+ unsigned int color_space;
+ unsigned int dynamic_range;
+ unsigned int ycbcr_coeff;
+ unsigned int color_depth;
+};
+
+struct edp_device_info {
+ struct edp_disp_info disp_info;
+ struct edp_link_train_info lt_info;
+ struct edp_video_info video_info;
+
+ /*below info get from panel during training*/
+ unsigned char lane_bw;
+ unsigned char lane_cnt;
+ unsigned char dpcd_rev;
+ /*support enhanced frame cap */
+ unsigned char dpcd_efc;
+};
+
+enum analog_power_block {
+ AUX_BLOCK,
+ CH0_BLOCK,
+ CH1_BLOCK,
+ CH2_BLOCK,
+ CH3_BLOCK,
+ ANALOG_TOTAL,
+ POWER_ALL
+};
+
+enum pll_status {
+ PLL_UNLOCKED = 0,
+ PLL_LOCKED
+};
+
+enum {
+ COLOR_RGB,
+ COLOR_YCBCR422,
+ COLOR_YCBCR444
+};
+
+enum {
+ VESA,
+ CEA
+};
+
+enum {
+ COLOR_YCBCR601,
+ COLOR_YCBCR709
+};
+
+enum {
+ COLOR_6,
+ COLOR_8,
+ COLOR_10,
+ COLOR_12
+};
+
+enum {
+ DP_LANE_BW_1_62 = 0x06,
+ DP_LANE_BW_2_70 = 0x0a,
+};
+
+enum {
+ DP_LANE_CNT_1 = 1,
+ DP_LANE_CNT_2 = 2,
+ DP_LANE_CNT_4 = 4,
+};
+
+enum {
+ DP_DPCD_REV_10 = 0x10,
+ DP_DPCD_REV_11 = 0x11,
+};
+
+enum {
+ DP_LT_NONE,
+ DP_LT_START,
+ DP_LT_CR,
+ DP_LT_ET,
+ DP_LT_FINISHED,
+ DP_LT_FAIL,
+};
+
+enum {
+ PRE_EMPHASIS_LEVEL_0,
+ PRE_EMPHASIS_LEVEL_1,
+ PRE_EMPHASIS_LEVEL_2,
+ PRE_EMPHASIS_LEVEL_3,
+};
+
+enum {
+ PRBS7,
+ D10_2,
+ TRAINING_PTN1,
+ TRAINING_PTN2,
+ DP_NONE
+};
+
+enum {
+ VOLTAGE_LEVEL_0,
+ VOLTAGE_LEVEL_1,
+ VOLTAGE_LEVEL_2,
+ VOLTAGE_LEVEL_3,
+};
+
+enum pattern_type {
+ NO_PATTERN,
+ COLOR_RAMP,
+ BALCK_WHITE_V_LINES,
+ COLOR_SQUARE,
+ INVALID_PATTERN,
+ COLORBAR_32,
+ COLORBAR_64,
+ WHITE_GRAY_BALCKBAR_32,
+ WHITE_GRAY_BALCKBAR_64,
+ MOBILE_WHITEBAR_32,
+ MOBILE_WHITEBAR_64
+};
+
+enum {
+ CALCULATED_M,
+ REGISTER_M
+};
+
+enum {
+ VIDEO_TIMING_FROM_CAPTURE,
+ VIDEO_TIMING_FROM_REGISTER
+};
+
+
+struct exynos_dp_platform_data {
+ struct edp_device_info *edp_dev_info;
+};
+
+#ifdef CONFIG_EXYNOS_DP
+unsigned int exynos_init_dp(void);
+#else
+unsigned int exynos_init_dp(void)
+{
+ return 0;
+}
+#endif
+
+#endif /* _DP_INFO_H */
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_DSIM_H_
+#define __ASM_ARM_ARCH_DSIM_H_
+
+#ifndef __ASSEMBLY__
+
+struct exynos_mipi_dsim {
+ unsigned int status;
+ unsigned int swrst;
+ unsigned int clkctrl;
+ unsigned int timeout;
+ unsigned int config;
+ unsigned int escmode;
+ unsigned int mdresol;
+ unsigned int mvporch;
+ unsigned int mhporch;
+ unsigned int msync;
+ unsigned int sdresol;
+ unsigned int intsrc;
+ unsigned int intmsk;
+ unsigned int pkthdr;
+ unsigned int payload;
+ unsigned int rxfifo;
+ unsigned int fifothld;
+ unsigned int fifoctrl;
+ unsigned int memacchr;
+ unsigned int pllctrl;
+ unsigned int plltmr;
+ unsigned int phyacchr;
+ unsigned int phyacchr1;
+};
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Bit Definitions
+ */
+/* DSIM_STATUS */
+#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
+#define DSIM_STOP_STATE_CLK (1 << 8)
+#define DSIM_TX_READY_HS_CLK (1 << 10)
+#define DSIM_PLL_STABLE (1 << 31)
+
+/* DSIM_SWRST */
+#define DSIM_FUNCRST (1 << 16)
+#define DSIM_SWRST (1 << 0)
+
+/* EXYNOS_DSIM_TIMEOUT */
+#define DSIM_LPDR_TOUT_SHIFT (0)
+#define DSIM_BTA_TOUT_SHIFT (16)
+
+/* EXYNOS_DSIM_CLKCTRL */
+#define DSIM_LANE_ESC_CLKEN_SHIFT (19)
+#define DSIM_BYTE_CLKEN_SHIFT (24)
+#define DSIM_BYTE_CLK_SRC_SHIFT (25)
+#define DSIM_PLL_BYPASS_SHIFT (27)
+#define DSIM_ESC_CLKEN_SHIFT (28)
+#define DSIM_TX_REQUEST_HSCLK_SHIFT (31)
+#define DSIM_LANE_ESC_CLKEN(x) (((x) & 0x1f) << \
+ DSIM_LANE_ESC_CLKEN_SHIFT)
+#define DSIM_BYTE_CLK_ENABLE (1 << DSIM_BYTE_CLKEN_SHIFT)
+#define DSIM_BYTE_CLK_DISABLE (0 << DSIM_BYTE_CLKEN_SHIFT)
+#define DSIM_PLL_BYPASS_EXTERNAL (1 << DSIM_PLL_BYPASS_SHIFT)
+#define DSIM_ESC_CLKEN_ENABLE (1 << DSIM_ESC_CLKEN_SHIFT)
+#define DSIM_ESC_CLKEN_DISABLE (0 << DSIM_ESC_CLKEN_SHIFT)
+
+/* EXYNOS_DSIM_CONFIG */
+#define DSIM_NUM_OF_DATALANE_SHIFT (5)
+#define DSIM_SUBPIX_SHIFT (8)
+#define DSIM_MAINPIX_SHIFT (12)
+#define DSIM_SUBVC_SHIFT (16)
+#define DSIM_MAINVC_SHIFT (18)
+#define DSIM_HSA_MODE_SHIFT (20)
+#define DSIM_HBP_MODE_SHIFT (21)
+#define DSIM_HFP_MODE_SHIFT (22)
+#define DSIM_HSE_MODE_SHIFT (23)
+#define DSIM_AUTO_MODE_SHIFT (24)
+#define DSIM_VIDEO_MODE_SHIFT (25)
+#define DSIM_BURST_MODE_SHIFT (26)
+#define DSIM_EOT_PACKET_SHIFT (28)
+#define DSIM_AUTO_FLUSH_SHIFT (29)
+#define DSIM_LANE_ENx(x) (((x) & 0x1f) << 0)
+
+#define DSIM_NUM_OF_DATA_LANE(x) ((x) << DSIM_NUM_OF_DATALANE_SHIFT)
+
+/* EXYNOS_DSIM_ESCMODE */
+#define DSIM_TX_LPDT_SHIFT (6)
+#define DSIM_CMD_LPDT_SHIFT (7)
+#define DSIM_TX_LPDT_LP (1 << DSIM_TX_LPDT_SHIFT)
+#define DSIM_CMD_LPDT_LP (1 << DSIM_CMD_LPDT_SHIFT)
+#define DSIM_STOP_STATE_CNT_SHIFT (21)
+#define DSIM_FORCE_STOP_STATE_SHIFT (20)
+
+/* EXYNOS_DSIM_MDRESOL */
+#define DSIM_MAIN_STAND_BY (1 << 31)
+#define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16)
+#define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0)
+
+/* EXYNOS_DSIM_MVPORCH */
+#define DSIM_CMD_ALLOW_SHIFT (28)
+#define DSIM_STABLE_VFP_SHIFT (16)
+#define DSIM_MAIN_VBP_SHIFT (0)
+#define DSIM_CMD_ALLOW_MASK (0xf << DSIM_CMD_ALLOW_SHIFT)
+#define DSIM_STABLE_VFP_MASK (0x7ff << DSIM_STABLE_VFP_SHIFT)
+#define DSIM_MAIN_VBP_MASK (0x7ff << DSIM_MAIN_VBP_SHIFT)
+
+/* EXYNOS_DSIM_MHPORCH */
+#define DSIM_MAIN_HFP_SHIFT (16)
+#define DSIM_MAIN_HBP_SHIFT (0)
+#define DSIM_MAIN_HFP_MASK ((0xffff) << DSIM_MAIN_HFP_SHIFT)
+#define DSIM_MAIN_HBP_MASK ((0xffff) << DSIM_MAIN_HBP_SHIFT)
+
+/* EXYNOS_DSIM_MSYNC */
+#define DSIM_MAIN_VSA_SHIFT (22)
+#define DSIM_MAIN_HSA_SHIFT (0)
+#define DSIM_MAIN_VSA_MASK ((0x3ff) << DSIM_MAIN_VSA_SHIFT)
+#define DSIM_MAIN_HSA_MASK ((0xffff) << DSIM_MAIN_HSA_SHIFT)
+
+/* EXYNOS_DSIM_SDRESOL */
+#define DSIM_SUB_STANDY_SHIFT (31)
+#define DSIM_SUB_VRESOL_SHIFT (16)
+#define DSIM_SUB_HRESOL_SHIFT (0)
+#define DSIM_SUB_STANDY_MASK ((0x1) << DSIM_SUB_STANDY_SHIFT)
+#define DSIM_SUB_VRESOL_MASK ((0x7ff) << DSIM_SUB_VRESOL_SHIFT)
+#define DSIM_SUB_HRESOL_MASK ((0x7ff) << DSIM_SUB_HRESOL_SHIFT)
+
+/* EXYNOS_DSIM_INTSRC */
+#define INTSRC_FRAME_DONE (1 << 24)
+#define INTSRC_PLL_STABLE (1 << 31)
+#define INTSRC_SWRST_RELEASE (1 << 30)
+
+/* EXYNOS_DSIM_INTMSK */
+#define INTMSK_FRAME_DONE (1 << 24)
+
+/* EXYNOS_DSIM_FIFOCTRL */
+#define SFR_HEADER_EMPTY (1 << 22)
+
+/* EXYNOS_DSIM_PKTHDR */
+#define DSIM_PKTHDR_DI(x) (((x) & 0x3f) << 0)
+#define DSIM_PKTHDR_DAT0(x) ((x) << 8)
+#define DSIM_PKTHDR_DAT1(x) ((x) << 16)
+
+/* EXYNOS_DSIM_PHYACCHR */
+#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
+#define DSIM_AFC_CTL_SHIFT (5)
+#define DSIM_AFC_EN (1 << 14)
+
+/* EXYNOS_DSIM_PHYACCHR1 */
+#define DSIM_DPDN_SWAP_DATA_SHIFT (0)
+
+/* EXYNOS_DSIM_PLLCTRL */
+#define DSIM_SCALER_SHIFT (1)
+#define DSIM_MAIN_SHIFT (4)
+#define DSIM_PREDIV_SHIFT (13)
+#define DSIM_PRECTRL_SHIFT (20)
+#define DSIM_PLL_EN_SHIFT (23)
+#define DSIM_FREQ_BAND_SHIFT (24)
+#define DSIM_ZEROCTRL_SHIFT (28)
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define DWMCI_CLKSEL 0x09C
+#define DWMCI_SET_SAMPLE_CLK(x) (x)
+#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
+#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
+
+#define EMMCP_MPSBEGIN0 0x1200
+#define EMMCP_SEND0 0x1204
+#define EMMCP_CTRL0 0x120C
+
+#define MPSCTRL_SECURE_READ_BIT (0x1<<7)
+#define MPSCTRL_SECURE_WRITE_BIT (0x1<<6)
+#define MPSCTRL_NON_SECURE_READ_BIT (0x1<<5)
+#define MPSCTRL_NON_SECURE_WRITE_BIT (0x1<<4)
+#define MPSCTRL_USE_FUSE_KEY (0x1<<3)
+#define MPSCTRL_ECB_MODE (0x1<<2)
+#define MPSCTRL_ENCRYPTION (0x1<<1)
+#define MPSCTRL_VALID (0x1<<0)
+
+/* CLKSEL Register */
+#define DWMCI_DIVRATIO_BIT 24
+#define DWMCI_DIVRATIO_MASK 0x7
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob);
+#endif
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel);
--- /dev/null
+/*
+ * SAMSUNG EXYNOS USB HOST EHCI Controller
+ *
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ * Vivek Gautam <gautam.vivek@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_EHCI_H__
+#define __ASM_ARM_ARCH_EHCI_H__
+
+#define CLK_24MHZ 5
+
+#define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0)
+#define PHYPWR_NORMAL_MASK_PHY1 (0x7 << 6)
+#define PHYPWR_NORMAL_MASK_HSIC0 (0x7 << 9)
+#define PHYPWR_NORMAL_MASK_HSIC1 (0x7 << 12)
+#define RSTCON_HOSTPHY_SWRST (0xf << 3)
+#define RSTCON_SWRST (0x1 << 0)
+
+#define HOST_CTRL0_PHYSWRSTALL (1 << 31)
+#define HOST_CTRL0_COMMONON_N (1 << 9)
+#define HOST_CTRL0_SIDDQ (1 << 6)
+#define HOST_CTRL0_FORCESLEEP (1 << 5)
+#define HOST_CTRL0_FORCESUSPEND (1 << 4)
+#define HOST_CTRL0_WORDINTERFACE (1 << 3)
+#define HOST_CTRL0_UTMISWRST (1 << 2)
+#define HOST_CTRL0_LINKSWRST (1 << 1)
+#define HOST_CTRL0_PHYSWRST (1 << 0)
+
+#define HOST_CTRL0_FSEL_MASK (7 << 16)
+
+#define EHCICTRL_ENAINCRXALIGN (1 << 29)
+#define EHCICTRL_ENAINCR4 (1 << 28)
+#define EHCICTRL_ENAINCR8 (1 << 27)
+#define EHCICTRL_ENAINCR16 (1 << 26)
+
+#define HSIC_CTRL_REFCLKSEL (0x2)
+#define HSIC_CTRL_REFCLKSEL_MASK (0x3)
+#define HSIC_CTRL_REFCLKSEL_SHIFT (23)
+
+#define HSIC_CTRL_REFCLKDIV_12 (0x24)
+#define HSIC_CTRL_REFCLKDIV_MASK (0x7f)
+#define HSIC_CTRL_REFCLKDIV_SHIFT (16)
+
+#define HSIC_CTRL_SIDDQ (0x1 << 6)
+#define HSIC_CTRL_FORCESLEEP (0x1 << 5)
+#define HSIC_CTRL_FORCESUSPEND (0x1 << 4)
+#define HSIC_CTRL_UTMISWRST (0x1 << 2)
+#define HSIC_CTRL_PHYSWRST (0x1 << 0)
+
+/* Register map for PHY control */
+struct exynos_usb_phy {
+ unsigned int usbphyctrl0;
+ unsigned int usbphytune0;
+ unsigned int reserved1[2];
+ unsigned int hsicphyctrl1;
+ unsigned int hsicphytune1;
+ unsigned int reserved2[2];
+ unsigned int hsicphyctrl2;
+ unsigned int hsicphytune2;
+ unsigned int reserved3[2];
+ unsigned int ehcictrl;
+ unsigned int ohcictrl;
+ unsigned int usbotgsys;
+ unsigned int reserved4;
+ unsigned int usbotgtune;
+};
+
+struct exynos4412_usb_phy {
+ unsigned int usbphyctrl;
+ unsigned int usbphyclk;
+ unsigned int usbphyrstcon;
+};
+
+/* Switch on the VBUS power. */
+int board_usb_vbus_init(void);
+
+#endif /* __ASM_ARM_ARCH_EHCI_H__ */
--- /dev/null
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_FB_H_
+#define __ASM_ARM_ARCH_FB_H_
+
+#ifndef __ASSEMBLY__
+struct exynos_fb {
+ unsigned int vidcon0;
+ unsigned int vidcon1;
+ unsigned int vidcon2;
+ unsigned int vidcon3;
+ unsigned int vidtcon0;
+ unsigned int vidtcon1;
+ unsigned int vidtcon2;
+ unsigned int vidtcon3;
+ unsigned int wincon0;
+ unsigned int wincon1;
+ unsigned int wincon2;
+ unsigned int wincon3;
+ unsigned int wincon4;
+
+ unsigned int winshmap;
+ unsigned int res1;
+
+ unsigned int winchmap2;
+ unsigned int vidosd0a;
+ unsigned int vidosd0b;
+ unsigned int vidosd0c;
+ unsigned int res2;
+
+ unsigned int vidosd1a;
+ unsigned int vidosd1b;
+ unsigned int vidosd1c;
+ unsigned int vidosd1d;
+
+ unsigned int vidosd2a;
+ unsigned int vidosd2b;
+ unsigned int vidosd2c;
+ unsigned int vidosd2d;
+
+ unsigned int vidosd3a;
+ unsigned int vidosd3b;
+ unsigned int vidosd3c;
+ unsigned int res3;
+
+ unsigned int vidosd4a;
+ unsigned int vidosd4b;
+ unsigned int vidosd4c;
+ unsigned int res4[5];
+
+ unsigned int vidw00add0b0;
+ unsigned int vidw00add0b1;
+ unsigned int vidw01add0b0;
+ unsigned int vidw01add0b1;
+
+ unsigned int vidw02add0b0;
+ unsigned int vidw02add0b1;
+ unsigned int vidw03add0b0;
+ unsigned int vidw03add0b1;
+ unsigned int vidw04add0b0;
+ unsigned int vidw04add0b1;
+ unsigned int res5[2];
+
+ unsigned int vidw00add1b0;
+ unsigned int vidw00add1b1;
+ unsigned int vidw01add1b0;
+ unsigned int vidw01add1b1;
+
+ unsigned int vidw02add1b0;
+ unsigned int vidw02add1b1;
+ unsigned int vidw03add1b0;
+ unsigned int vidw03add1b1;
+
+ unsigned int vidw04add1b0;
+ unsigned int vidw04add1b1;
+ unsigned int res7[2];
+
+ unsigned int vidw00add2;
+ unsigned int vidw01add2;
+ unsigned int vidw02add2;
+ unsigned int vidw03add2;
+ unsigned int vidw04add2;
+ unsigned int res8[7];
+
+ unsigned int vidintcon0;
+ unsigned int vidintcon1;
+ unsigned int res9[1];
+
+ unsigned int w1keycon0;
+ unsigned int w1keycon1;
+ unsigned int w2keycon0;
+ unsigned int w2keycon1;
+ unsigned int w3keycon0;
+ unsigned int w3keycon1;
+ unsigned int w4keycon0;
+ unsigned int w4keycon1;
+
+ unsigned int w1keyalpha;
+ unsigned int w2keyalpha;
+ unsigned int w3keyalpha;
+ unsigned int w4keyalpha;
+
+ unsigned int dithmode;
+ unsigned int res10[2];
+
+ unsigned int win0map;
+ unsigned int win1map;
+ unsigned int win2map;
+ unsigned int win3map;
+ unsigned int win4map;
+ unsigned int res11[1];
+
+ unsigned int wpalcon_h;
+ unsigned int wpalcon_l;
+
+ unsigned int trigcon;
+ unsigned int res12[2];
+
+ unsigned int i80ifcona0;
+ unsigned int i80ifcona1;
+ unsigned int i80ifconb0;
+ unsigned int i80ifconb1;
+
+ unsigned int colorgaincon;
+ unsigned int res13[2];
+
+ unsigned int ldi_cmdcon0;
+ unsigned int ldi_cmdcon1;
+ unsigned int res14[1];
+
+ /* To be updated */
+
+ unsigned char res15[156];
+ unsigned int dualrgb;
+ unsigned char res16[16];
+ unsigned int dp_mie_clkcon;
+};
+#endif
+
+/* LCD IF register offset */
+#define EXYNOS4_LCD_IF_BASE_OFFSET 0x0
+#define EXYNOS5_LCD_IF_BASE_OFFSET 0x20000
+
+static inline unsigned int exynos_fimd_get_base_offset(void)
+{
+ if (cpu_is_exynos5())
+ return EXYNOS5_LCD_IF_BASE_OFFSET;
+ else
+ return EXYNOS4_LCD_IF_BASE_OFFSET;
+}
+
+/*
+ * Register offsets
+*/
+#define EXYNOS_WINCON(x) (x * 0x04)
+#define EXYNOS_VIDOSD(x) (x * 0x10)
+#define EXYNOS_BUFFER_OFFSET(x) (x * 0x08)
+#define EXYNOS_BUFFER_SIZE(x) (x * 0x04)
+
+/*
+ * Bit Definitions
+*/
+
+/* VIDCON0 */
+#define EXYNOS_VIDCON0_DSI_DISABLE (0 << 30)
+#define EXYNOS_VIDCON0_DSI_ENABLE (1 << 30)
+#define EXYNOS_VIDCON0_SCAN_PROGRESSIVE (0 << 29)
+#define EXYNOS_VIDCON0_SCAN_INTERLACE (1 << 29)
+#define EXYNOS_VIDCON0_SCAN_MASK (1 << 29)
+#define EXYNOS_VIDCON0_VIDOUT_RGB (0 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_ITU (1 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_I80LDI0 (2 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_I80LDI1 (3 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_WB_RGB (4 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI0 (6 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI1 (7 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_MASK (7 << 26)
+#define EXYNOS_VIDCON0_PNRMODE_RGB_P (0 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_BGR_P (1 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_RGB_S (2 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_BGR_S (3 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_MASK (3 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_SHIFT (17)
+#define EXYNOS_VIDCON0_CLKVALUP_ALWAYS (0 << 16)
+#define EXYNOS_VIDCON0_CLKVALUP_START_FRAME (1 << 16)
+#define EXYNOS_VIDCON0_CLKVALUP_MASK (1 << 16)
+#define EXYNOS_VIDCON0_CLKVAL_F(x) (((x) & 0xff) << 6)
+#define EXYNOS_VIDCON0_VCLKEN_NORMAL (0 << 5)
+#define EXYNOS_VIDCON0_VCLKEN_FREERUN (1 << 5)
+#define EXYNOS_VIDCON0_VCLKEN_MASK (1 << 5)
+#define EXYNOS_VIDCON0_CLKDIR_DIRECTED (0 << 4)
+#define EXYNOS_VIDCON0_CLKDIR_DIVIDED (1 << 4)
+#define EXYNOS_VIDCON0_CLKDIR_MASK (1 << 4)
+#define EXYNOS_VIDCON0_CLKSEL_HCLK (0 << 2)
+#define EXYNOS_VIDCON0_CLKSEL_SCLK (1 << 2)
+#define EXYNOS_VIDCON0_CLKSEL_MASK (1 << 2)
+#define EXYNOS_VIDCON0_ENVID_ENABLE (1 << 1)
+#define EXYNOS_VIDCON0_ENVID_DISABLE (0 << 1)
+#define EXYNOS_VIDCON0_ENVID_F_ENABLE (1 << 0)
+#define EXYNOS_VIDCON0_ENVID_F_DISABLE (0 << 0)
+
+/* VIDCON1 */
+#define EXYNOS_VIDCON1_IVCLK_FALLING_EDGE (0 << 7)
+#define EXYNOS_VIDCON1_IVCLK_RISING_EDGE (1 << 7)
+#define EXYNOS_VIDCON1_IHSYNC_NORMAL (0 << 6)
+#define EXYNOS_VIDCON1_IHSYNC_INVERT (1 << 6)
+#define EXYNOS_VIDCON1_IVSYNC_NORMAL (0 << 5)
+#define EXYNOS_VIDCON1_IVSYNC_INVERT (1 << 5)
+#define EXYNOS_VIDCON1_IVDEN_NORMAL (0 << 4)
+#define EXYNOS_VIDCON1_IVDEN_INVERT (1 << 4)
+
+/* VIDCON2 */
+#define EXYNOS_VIDCON2_EN601_DISABLE (0 << 23)
+#define EXYNOS_VIDCON2_EN601_ENABLE (1 << 23)
+#define EXYNOS_VIDCON2_EN601_MASK (1 << 23)
+#define EXYNOS_VIDCON2_WB_DISABLE (0 << 15)
+#define EXYNOS_VIDCON2_WB_ENABLE (1 << 15)
+#define EXYNOS_VIDCON2_WB_MASK (1 << 15)
+#define EXYNOS_VIDCON2_TVFORMATSEL_HW (0 << 14)
+#define EXYNOS_VIDCON2_TVFORMATSEL_SW (1 << 14)
+#define EXYNOS_VIDCON2_TVFORMATSEL_MASK (1 << 14)
+#define EXYNOS_VIDCON2_TVFORMATSEL_YUV422 (1 << 12)
+#define EXYNOS_VIDCON2_TVFORMATSEL_YUV444 (2 << 12)
+#define EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK (3 << 12)
+#define EXYNOS_VIDCON2_ORGYUV_YCBCR (0 << 8)
+#define EXYNOS_VIDCON2_ORGYUV_CBCRY (1 << 8)
+#define EXYNOS_VIDCON2_ORGYUV_MASK (1 << 8)
+#define EXYNOS_VIDCON2_YUVORD_CBCR (0 << 7)
+#define EXYNOS_VIDCON2_YUVORD_CRCB (1 << 7)
+#define EXYNOS_VIDCON2_YUVORD_MASK (1 << 7)
+
+/* PRTCON */
+#define EXYNOS_PRTCON_UPDATABLE (0 << 11)
+#define EXYNOS_PRTCON_PROTECT (1 << 11)
+
+/* VIDTCON0 */
+#define EXYNOS_VIDTCON0_VBPDE(x) (((x) & 0xff) << 24)
+#define EXYNOS_VIDTCON0_VBPD(x) (((x) & 0xff) << 16)
+#define EXYNOS_VIDTCON0_VFPD(x) (((x) & 0xff) << 8)
+#define EXYNOS_VIDTCON0_VSPW(x) (((x) & 0xff) << 0)
+
+/* VIDTCON1 */
+#define EXYNOS_VIDTCON1_VFPDE(x) (((x) & 0xff) << 24)
+#define EXYNOS_VIDTCON1_HBPD(x) (((x) & 0xff) << 16)
+#define EXYNOS_VIDTCON1_HFPD(x) (((x) & 0xff) << 8)
+#define EXYNOS_VIDTCON1_HSPW(x) (((x) & 0xff) << 0)
+
+/* VIDTCON2 */
+#define EXYNOS_VIDTCON2_LINEVAL(x) (((x) & 0x7ff) << 11)
+#define EXYNOS_VIDTCON2_HOZVAL(x) (((x) & 0x7ff) << 0)
+#define EXYNOS_VIDTCON2_LINEVAL_E(x) ((((x) & 0x800) >> 11) << 23)
+#define EXYNOS_VIDTCON2_HOZVAL_E(x) ((((x) & 0x800) >> 11) << 22)
+
+/* Window 0~4 Control - WINCONx */
+#define EXYNOS_WINCON_DATAPATH_DMA (0 << 22)
+#define EXYNOS_WINCON_DATAPATH_LOCAL (1 << 22)
+#define EXYNOS_WINCON_DATAPATH_MASK (1 << 22)
+#define EXYNOS_WINCON_BUFSEL_0 (0 << 20)
+#define EXYNOS_WINCON_BUFSEL_1 (1 << 20)
+#define EXYNOS_WINCON_BUFSEL_MASK (1 << 20)
+#define EXYNOS_WINCON_BUFSEL_SHIFT (20)
+#define EXYNOS_WINCON_BUFAUTO_DISABLE (0 << 19)
+#define EXYNOS_WINCON_BUFAUTO_ENABLE (1 << 19)
+#define EXYNOS_WINCON_BUFAUTO_MASK (1 << 19)
+#define EXYNOS_WINCON_BITSWP_DISABLE (0 << 18)
+#define EXYNOS_WINCON_BITSWP_ENABLE (1 << 18)
+#define EXYNOS_WINCON_BITSWP_SHIFT (18)
+#define EXYNOS_WINCON_BYTESWP_DISABLE (0 << 17)
+#define EXYNOS_WINCON_BYTESWP_ENABLE (1 << 17)
+#define EXYNOS_WINCON_BYTESWP_SHIFT (17)
+#define EXYNOS_WINCON_HAWSWP_DISABLE (0 << 16)
+#define EXYNOS_WINCON_HAWSWP_ENABLE (1 << 16)
+#define EXYNOS_WINCON_HAWSWP_SHIFT (16)
+#define EXYNOS_WINCON_WSWP_DISABLE (0 << 15)
+#define EXYNOS_WINCON_WSWP_ENABLE (1 << 15)
+#define EXYNOS_WINCON_WSWP_SHIFT (15)
+#define EXYNOS_WINCON_INRGB_RGB (0 << 13)
+#define EXYNOS_WINCON_INRGB_YUV (1 << 13)
+#define EXYNOS_WINCON_INRGB_MASK (1 << 13)
+#define EXYNOS_WINCON_BURSTLEN_16WORD (0 << 9)
+#define EXYNOS_WINCON_BURSTLEN_8WORD (1 << 9)
+#define EXYNOS_WINCON_BURSTLEN_4WORD (2 << 9)
+#define EXYNOS_WINCON_BURSTLEN_MASK (3 << 9)
+#define EXYNOS_WINCON_ALPHA_MULTI_DISABLE (0 << 7)
+#define EXYNOS_WINCON_ALPHA_MULTI_ENABLE (1 << 7)
+#define EXYNOS_WINCON_BLD_PLANE (0 << 6)
+#define EXYNOS_WINCON_BLD_PIXEL (1 << 6)
+#define EXYNOS_WINCON_BLD_MASK (1 << 6)
+#define EXYNOS_WINCON_BPPMODE_1BPP (0 << 2)
+#define EXYNOS_WINCON_BPPMODE_2BPP (1 << 2)
+#define EXYNOS_WINCON_BPPMODE_4BPP (2 << 2)
+#define EXYNOS_WINCON_BPPMODE_8BPP_PAL (3 << 2)
+#define EXYNOS_WINCON_BPPMODE_8BPP (4 << 2)
+#define EXYNOS_WINCON_BPPMODE_16BPP_565 (5 << 2)
+#define EXYNOS_WINCON_BPPMODE_16BPP_A555 (6 << 2)
+#define EXYNOS_WINCON_BPPMODE_18BPP_666 (8 << 2)
+#define EXYNOS_WINCON_BPPMODE_18BPP_A665 (9 << 2)
+#define EXYNOS_WINCON_BPPMODE_24BPP_888 (0xb << 2)
+#define EXYNOS_WINCON_BPPMODE_24BPP_A887 (0xc << 2)
+#define EXYNOS_WINCON_BPPMODE_32BPP (0xd << 2)
+#define EXYNOS_WINCON_BPPMODE_16BPP_A444 (0xe << 2)
+#define EXYNOS_WINCON_BPPMODE_15BPP_555 (0xf << 2)
+#define EXYNOS_WINCON_BPPMODE_MASK (0xf << 2)
+#define EXYNOS_WINCON_BPPMODE_SHIFT (2)
+#define EXYNOS_WINCON_ALPHA0_SEL (0 << 1)
+#define EXYNOS_WINCON_ALPHA1_SEL (1 << 1)
+#define EXYNOS_WINCON_ALPHA_SEL_MASK (1 << 1)
+#define EXYNOS_WINCON_ENWIN_DISABLE (0 << 0)
+#define EXYNOS_WINCON_ENWIN_ENABLE (1 << 0)
+
+/* WINCON1 special */
+#define EXYNOS_WINCON1_VP_DISABLE (0 << 24)
+#define EXYNOS_WINCON1_VP_ENABLE (1 << 24)
+#define EXYNOS_WINCON1_LOCALSEL_FIMC1 (0 << 23)
+#define EXYNOS_WINCON1_LOCALSEL_VP (1 << 23)
+#define EXYNOS_WINCON1_LOCALSEL_MASK (1 << 23)
+
+/* WINSHMAP */
+#define EXYNOS_WINSHMAP_PROTECT(x) (((x) & 0x1f) << 10)
+#define EXYNOS_WINSHMAP_CH_ENABLE(x) (1 << (x))
+#define EXYNOS_WINSHMAP_CH_DISABLE(x) (1 << (x))
+#define EXYNOS_WINSHMAP_LOCAL_ENABLE(x) (0x20 << (x))
+#define EXYNOS_WINSHMAP_LOCAL_DISABLE(x) (0x20 << (x))
+
+/* VIDOSDxA, VIDOSDxB */
+#define EXYNOS_VIDOSD_LEFT_X(x) (((x) & 0x7ff) << 11)
+#define EXYNOS_VIDOSD_TOP_Y(x) (((x) & 0x7ff) << 0)
+#define EXYNOS_VIDOSD_RIGHT_X(x) (((x) & 0x7ff) << 11)
+#define EXYNOS_VIDOSD_BOTTOM_Y(x) (((x) & 0x7ff) << 0)
+#define EXYNOS_VIDOSD_RIGHT_X_E(x) (((x) & 0x1) << 23)
+#define EXYNOS_VIDOSD_BOTTOM_Y_E(x) (((x) & 0x1) << 22)
+
+/* VIDOSD0C, VIDOSDxD */
+#define EXYNOS_VIDOSD_SIZE(x) (((x) & 0xffffff) << 0)
+
+/* VIDOSDxC (1~4) */
+#define EXYNOS_VIDOSD_ALPHA0_R(x) (((x) & 0xf) << 20)
+#define EXYNOS_VIDOSD_ALPHA0_G(x) (((x) & 0xf) << 16)
+#define EXYNOS_VIDOSD_ALPHA0_B(x) (((x) & 0xf) << 12)
+#define EXYNOS_VIDOSD_ALPHA1_R(x) (((x) & 0xf) << 8)
+#define EXYNOS_VIDOSD_ALPHA1_G(x) (((x) & 0xf) << 4)
+#define EXYNOS_VIDOSD_ALPHA1_B(x) (((x) & 0xf) << 0)
+#define EXYNOS_VIDOSD_ALPHA0_SHIFT (12)
+#define EXYNOS_VIDOSD_ALPHA1_SHIFT (0)
+
+/* Start Address */
+#define EXYNOS_VIDADDR_START_VBANK(x) (((x) & 0xff) << 24)
+#define EXYNOS_VIDADDR_START_VBASEU(x) (((x) & 0xffffff) << 0)
+
+/* End Address */
+#define EXYNOS_VIDADDR_END_VBASEL(x) (((x) & 0xffffff) << 0)
+
+/* Buffer Size */
+#define EXYNOS_VIDADDR_OFFSIZE(x) (((x) & 0x1fff) << 13)
+#define EXYNOS_VIDADDR_PAGEWIDTH(x) (((x) & 0x1fff) << 0)
+#define EXYNOS_VIDADDR_OFFSIZE_E(x) ((((x) & 0x2000) >> 13) << 27)
+#define EXYNOS_VIDADDR_PAGEWIDTH_E(x) ((((x) & 0x2000) >> 13) << 26)
+
+/* WIN Color Map */
+#define EXYNOS_WINMAP_COLOR(x) ((x) & 0xffffff)
+
+/* VIDINTCON0 */
+#define EXYNOS_VIDINTCON0_SYSMAINCON_DISABLE (0 << 19)
+#define EXYNOS_VIDINTCON0_SYSMAINCON_ENABLE (1 << 19)
+#define EXYNOS_VIDINTCON0_SYSSUBCON_DISABLE (0 << 18)
+#define EXYNOS_VIDINTCON0_SYSSUBCON_ENABLE (1 << 18)
+#define EXYNOS_VIDINTCON0_SYSIFDONE_DISABLE (0 << 17)
+#define EXYNOS_VIDINTCON0_SYSIFDONE_ENABLE (1 << 17)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_BACK (0 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_VSYNC (1 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_ACTIVE (2 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_FRONT (3 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_MASK (3 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_NONE (0 << 13)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_BACK (1 << 13)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_VSYNC (2 << 13)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_FRONT (3 << 13)
+#define EXYNOS_VIDINTCON0_INTFRMEN_DISABLE (0 << 12)
+#define EXYNOS_VIDINTCON0_INTFRMEN_ENABLE (1 << 12)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN4 (1 << 11)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN3 (1 << 10)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN2 (1 << 9)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN1 (1 << 6)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN0 (1 << 5)
+#define EXYNOS_VIDINTCON0_FIFOSEL_ALL (0x73 << 5)
+#define EXYNOS_VIDINTCON0_FIFOSEL_MASK (0x73 << 5)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_25 (0 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_50 (1 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_75 (2 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_EMPTY (3 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_FULL (4 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_MASK (7 << 2)
+#define EXYNOS_VIDINTCON0_INTFIFO_DISABLE (0 << 1)
+#define EXYNOS_VIDINTCON0_INTFIFO_ENABLE (1 << 1)
+#define EXYNOS_VIDINTCON0_INT_DISABLE (0 << 0)
+#define EXYNOS_VIDINTCON0_INT_ENABLE (1 << 0)
+#define EXYNOS_VIDINTCON0_INT_MASK (1 << 0)
+
+/* VIDINTCON1 */
+#define EXYNOS_VIDINTCON1_INTVPPEND (1 << 5)
+#define EXYNOS_VIDINTCON1_INTI80PEND (1 << 2)
+#define EXYNOS_VIDINTCON1_INTFRMPEND (1 << 1)
+#define EXYNOS_VIDINTCON1_INTFIFOPEND (1 << 0)
+
+/* WINMAP */
+#define EXYNOS_WINMAP_ENABLE (1 << 24)
+
+/* WxKEYCON0 (1~4) */
+#define EXYNOS_KEYCON0_KEYBLEN_DISABLE (0 << 26)
+#define EXYNOS_KEYCON0_KEYBLEN_ENABLE (1 << 26)
+#define EXYNOS_KEYCON0_KEY_DISABLE (0 << 25)
+#define EXYNOS_KEYCON0_KEY_ENABLE (1 << 25)
+#define EXYNOS_KEYCON0_DIRCON_MATCH_FG (0 << 24)
+#define EXYNOS_KEYCON0_DIRCON_MATCH_BG (1 << 24)
+#define EXYNOS_KEYCON0_COMPKEY(x) (((x) & 0xffffff) << 0)
+
+/* WxKEYCON1 (1~4) */
+#define EXYNOS_KEYCON1_COLVAL(x) (((x) & 0xffffff) << 0)
+
+/* DUALRGB */
+#define EXYNOS_DUALRGB_BYPASS_SINGLE (0x00 << 0)
+#define EXYNOS_DUALRGB_BYPASS_DUAL (0x01 << 0)
+#define EXYNOS_DUALRGB_MIE_DUAL (0x10 << 0)
+#define EXYNOS_DUALRGB_MIE_SINGLE (0x11 << 0)
+#define EXYNOS_DUALRGB_LINESPLIT (0x0 << 2)
+#define EXYNOS_DUALRGB_FRAMESPLIT (0x1 << 2)
+#define EXYNOS_DUALRGB_SUB_CNT(x) ((x & 0xfff) << 4)
+#define EXYNOS_DUALRGB_VDEN_EN_DISABLE (0x0 << 16)
+#define EXYNOS_DUALRGB_VDEN_EN_ENABLE (0x1 << 16)
+#define EXYNOS_DUALRGB_MAIN_CNT(x) ((x & 0xfff) << 18)
+
+/* I80IFCONA0 and I80IFCONA1 */
+#define EXYNOS_LCD_CS_SETUP(x) (((x) & 0xf) << 16)
+#define EXYNOS_LCD_WR_SETUP(x) (((x) & 0xf) << 12)
+#define EXYNOS_LCD_WR_ACT(x) (((x) & 0xf) << 8)
+#define EXYNOS_LCD_WR_HOLD(x) (((x) & 0xf) << 4)
+#define EXYNOS_RSPOL_LOW (0 << 2)
+#define EXYNOS_RSPOL_HIGH (1 << 2)
+#define EXYNOS_I80IFEN_DISABLE (0 << 0)
+#define EXYNOS_I80IFEN_ENABLE (1 << 0)
+
+/* TRIGCON */
+#define EXYNOS_I80SOFT_TRIG_EN (1 << 0)
+#define EXYNOS_I80START_TRIG (1 << 1)
+#define EXYNOS_I80STATUS_TRIG_DONE (1 << 2)
+
+/* DP_MIE_CLKCON */
+#define EXYNOS_DP_MIE_DISABLE (0 << 0)
+#define EXYNOS_DP_CLK_ENABLE (1 << 1)
+#define EXYNOS_MIE_CLK_ENABLE (3 << 0)
+
+#endif /* _REGS_FB_H */
--- /dev/null
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#ifndef __ASSEMBLY__
+struct s5p_gpio_bank {
+ unsigned int con;
+ unsigned int dat;
+ unsigned int pull;
+ unsigned int drv;
+ unsigned int pdn_con;
+ unsigned int pdn_pull;
+ unsigned char res1[8];
+};
+
+/* GPIO pins per bank */
+#define GPIO_PER_BANK 8
+
+/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
+enum exynos4_gpio_pin {
+ /* GPIO_PART1_STARTS */
+ EXYNOS4_GPIO_A00, /* 0 */
+ EXYNOS4_GPIO_A01,
+ EXYNOS4_GPIO_A02,
+ EXYNOS4_GPIO_A03,
+ EXYNOS4_GPIO_A04,
+ EXYNOS4_GPIO_A05,
+ EXYNOS4_GPIO_A06,
+ EXYNOS4_GPIO_A07,
+ EXYNOS4_GPIO_A10, /* 8 */
+ EXYNOS4_GPIO_A11,
+ EXYNOS4_GPIO_A12,
+ EXYNOS4_GPIO_A13,
+ EXYNOS4_GPIO_A14,
+ EXYNOS4_GPIO_A15,
+ EXYNOS4_GPIO_A16,
+ EXYNOS4_GPIO_A17,
+ EXYNOS4_GPIO_B0, /* 16 0x10 */
+ EXYNOS4_GPIO_B1,
+ EXYNOS4_GPIO_B2,
+ EXYNOS4_GPIO_B3,
+ EXYNOS4_GPIO_B4,
+ EXYNOS4_GPIO_B5,
+ EXYNOS4_GPIO_B6,
+ EXYNOS4_GPIO_B7,
+ EXYNOS4_GPIO_C00, /* 24 0x18 */
+ EXYNOS4_GPIO_C01,
+ EXYNOS4_GPIO_C02,
+ EXYNOS4_GPIO_C03,
+ EXYNOS4_GPIO_C04,
+ EXYNOS4_GPIO_C05,
+ EXYNOS4_GPIO_C06,
+ EXYNOS4_GPIO_C07,
+ EXYNOS4_GPIO_C10, /* 32 0x20*/
+ EXYNOS4_GPIO_C11,
+ EXYNOS4_GPIO_C12,
+ EXYNOS4_GPIO_C13,
+ EXYNOS4_GPIO_C14,
+ EXYNOS4_GPIO_C15,
+ EXYNOS4_GPIO_C16,
+ EXYNOS4_GPIO_C17,
+ EXYNOS4_GPIO_D00, /* 40 0x28 */
+ EXYNOS4_GPIO_D01,
+ EXYNOS4_GPIO_D02,
+ EXYNOS4_GPIO_D03,
+ EXYNOS4_GPIO_D04,
+ EXYNOS4_GPIO_D05,
+ EXYNOS4_GPIO_D06,
+ EXYNOS4_GPIO_D07,
+ EXYNOS4_GPIO_D10, /* 48 0x30 */
+ EXYNOS4_GPIO_D11,
+ EXYNOS4_GPIO_D12,
+ EXYNOS4_GPIO_D13,
+ EXYNOS4_GPIO_D14,
+ EXYNOS4_GPIO_D15,
+ EXYNOS4_GPIO_D16,
+ EXYNOS4_GPIO_D17,
+ EXYNOS4_GPIO_E00, /* 56 0x38 */
+ EXYNOS4_GPIO_E01,
+ EXYNOS4_GPIO_E02,
+ EXYNOS4_GPIO_E03,
+ EXYNOS4_GPIO_E04,
+ EXYNOS4_GPIO_E05,
+ EXYNOS4_GPIO_E06,
+ EXYNOS4_GPIO_E07,
+ EXYNOS4_GPIO_E10, /* 64 0x40 */
+ EXYNOS4_GPIO_E11,
+ EXYNOS4_GPIO_E12,
+ EXYNOS4_GPIO_E13,
+ EXYNOS4_GPIO_E14,
+ EXYNOS4_GPIO_E15,
+ EXYNOS4_GPIO_E16,
+ EXYNOS4_GPIO_E17,
+ EXYNOS4_GPIO_E20, /* 72 0x48 */
+ EXYNOS4_GPIO_E21,
+ EXYNOS4_GPIO_E22,
+ EXYNOS4_GPIO_E23,
+ EXYNOS4_GPIO_E24,
+ EXYNOS4_GPIO_E25,
+ EXYNOS4_GPIO_E26,
+ EXYNOS4_GPIO_E27,
+ EXYNOS4_GPIO_E30, /* 80 0x50 */
+ EXYNOS4_GPIO_E31,
+ EXYNOS4_GPIO_E32,
+ EXYNOS4_GPIO_E33,
+ EXYNOS4_GPIO_E34,
+ EXYNOS4_GPIO_E35,
+ EXYNOS4_GPIO_E36,
+ EXYNOS4_GPIO_E37,
+ EXYNOS4_GPIO_E40, /* 88 0x58 */
+ EXYNOS4_GPIO_E41,
+ EXYNOS4_GPIO_E42,
+ EXYNOS4_GPIO_E43,
+ EXYNOS4_GPIO_E44,
+ EXYNOS4_GPIO_E45,
+ EXYNOS4_GPIO_E46,
+ EXYNOS4_GPIO_E47,
+ EXYNOS4_GPIO_F00, /* 96 0x60 */
+ EXYNOS4_GPIO_F01,
+ EXYNOS4_GPIO_F02,
+ EXYNOS4_GPIO_F03,
+ EXYNOS4_GPIO_F04,
+ EXYNOS4_GPIO_F05,
+ EXYNOS4_GPIO_F06,
+ EXYNOS4_GPIO_F07,
+ EXYNOS4_GPIO_F10, /* 104 0x68 */
+ EXYNOS4_GPIO_F11,
+ EXYNOS4_GPIO_F12,
+ EXYNOS4_GPIO_F13,
+ EXYNOS4_GPIO_F14,
+ EXYNOS4_GPIO_F15,
+ EXYNOS4_GPIO_F16,
+ EXYNOS4_GPIO_F17,
+ EXYNOS4_GPIO_F20, /* 112 0x70 */
+ EXYNOS4_GPIO_F21,
+ EXYNOS4_GPIO_F22,
+ EXYNOS4_GPIO_F23,
+ EXYNOS4_GPIO_F24,
+ EXYNOS4_GPIO_F25,
+ EXYNOS4_GPIO_F26,
+ EXYNOS4_GPIO_F27,
+ EXYNOS4_GPIO_F30, /* 120 0x78 */
+ EXYNOS4_GPIO_F31,
+ EXYNOS4_GPIO_F32,
+ EXYNOS4_GPIO_F33,
+ EXYNOS4_GPIO_F34,
+ EXYNOS4_GPIO_F35,
+ EXYNOS4_GPIO_F36,
+ EXYNOS4_GPIO_F37,
+
+ /* GPIO_PART2_STARTS */
+ EXYNOS4_GPIO_MAX_PORT_PART_1, /* 128 0x80 */
+ EXYNOS4_GPIO_J00 = EXYNOS4_GPIO_MAX_PORT_PART_1,
+ EXYNOS4_GPIO_J01,
+ EXYNOS4_GPIO_J02,
+ EXYNOS4_GPIO_J03,
+ EXYNOS4_GPIO_J04,
+ EXYNOS4_GPIO_J05,
+ EXYNOS4_GPIO_J06,
+ EXYNOS4_GPIO_J07,
+ EXYNOS4_GPIO_J10, /* 136 0x88 */
+ EXYNOS4_GPIO_J11,
+ EXYNOS4_GPIO_J12,
+ EXYNOS4_GPIO_J13,
+ EXYNOS4_GPIO_J14,
+ EXYNOS4_GPIO_J15,
+ EXYNOS4_GPIO_J16,
+ EXYNOS4_GPIO_J17,
+ EXYNOS4_GPIO_K00, /* 144 0x90 */
+ EXYNOS4_GPIO_K01,
+ EXYNOS4_GPIO_K02,
+ EXYNOS4_GPIO_K03,
+ EXYNOS4_GPIO_K04,
+ EXYNOS4_GPIO_K05,
+ EXYNOS4_GPIO_K06,
+ EXYNOS4_GPIO_K07,
+ EXYNOS4_GPIO_K10, /* 152 0x98 */
+ EXYNOS4_GPIO_K11,
+ EXYNOS4_GPIO_K12,
+ EXYNOS4_GPIO_K13,
+ EXYNOS4_GPIO_K14,
+ EXYNOS4_GPIO_K15,
+ EXYNOS4_GPIO_K16,
+ EXYNOS4_GPIO_K17,
+ EXYNOS4_GPIO_K20, /* 160 0xA0 */
+ EXYNOS4_GPIO_K21,
+ EXYNOS4_GPIO_K22,
+ EXYNOS4_GPIO_K23,
+ EXYNOS4_GPIO_K24,
+ EXYNOS4_GPIO_K25,
+ EXYNOS4_GPIO_K26,
+ EXYNOS4_GPIO_K27,
+ EXYNOS4_GPIO_K30, /* 168 0xA8 */
+ EXYNOS4_GPIO_K31,
+ EXYNOS4_GPIO_K32,
+ EXYNOS4_GPIO_K33,
+ EXYNOS4_GPIO_K34,
+ EXYNOS4_GPIO_K35,
+ EXYNOS4_GPIO_K36,
+ EXYNOS4_GPIO_K37,
+ EXYNOS4_GPIO_L00, /* 176 0xB0 */
+ EXYNOS4_GPIO_L01,
+ EXYNOS4_GPIO_L02,
+ EXYNOS4_GPIO_L03,
+ EXYNOS4_GPIO_L04,
+ EXYNOS4_GPIO_L05,
+ EXYNOS4_GPIO_L06,
+ EXYNOS4_GPIO_L07,
+ EXYNOS4_GPIO_L10, /* 184 0xB8 */
+ EXYNOS4_GPIO_L11,
+ EXYNOS4_GPIO_L12,
+ EXYNOS4_GPIO_L13,
+ EXYNOS4_GPIO_L14,
+ EXYNOS4_GPIO_L15,
+ EXYNOS4_GPIO_L16,
+ EXYNOS4_GPIO_L17,
+ EXYNOS4_GPIO_L20, /* 192 0xC0 */
+ EXYNOS4_GPIO_L21,
+ EXYNOS4_GPIO_L22,
+ EXYNOS4_GPIO_L23,
+ EXYNOS4_GPIO_L24,
+ EXYNOS4_GPIO_L25,
+ EXYNOS4_GPIO_L26,
+ EXYNOS4_GPIO_L27,
+ EXYNOS4_GPIO_Y00, /* 200 0xC8 */
+ EXYNOS4_GPIO_Y01,
+ EXYNOS4_GPIO_Y02,
+ EXYNOS4_GPIO_Y03,
+ EXYNOS4_GPIO_Y04,
+ EXYNOS4_GPIO_Y05,
+ EXYNOS4_GPIO_Y06,
+ EXYNOS4_GPIO_Y07,
+ EXYNOS4_GPIO_Y10, /* 208 0xD0 */
+ EXYNOS4_GPIO_Y11,
+ EXYNOS4_GPIO_Y12,
+ EXYNOS4_GPIO_Y13,
+ EXYNOS4_GPIO_Y14,
+ EXYNOS4_GPIO_Y15,
+ EXYNOS4_GPIO_Y16,
+ EXYNOS4_GPIO_Y17,
+ EXYNOS4_GPIO_Y20, /* 216 0xD8 */
+ EXYNOS4_GPIO_Y21,
+ EXYNOS4_GPIO_Y22,
+ EXYNOS4_GPIO_Y23,
+ EXYNOS4_GPIO_Y24,
+ EXYNOS4_GPIO_Y25,
+ EXYNOS4_GPIO_Y26,
+ EXYNOS4_GPIO_Y27,
+ EXYNOS4_GPIO_Y30, /* 224 0xE0 */
+ EXYNOS4_GPIO_Y31,
+ EXYNOS4_GPIO_Y32,
+ EXYNOS4_GPIO_Y33,
+ EXYNOS4_GPIO_Y34,
+ EXYNOS4_GPIO_Y35,
+ EXYNOS4_GPIO_Y36,
+ EXYNOS4_GPIO_Y37,
+ EXYNOS4_GPIO_Y40, /* 232 0xE8 */
+ EXYNOS4_GPIO_Y41,
+ EXYNOS4_GPIO_Y42,
+ EXYNOS4_GPIO_Y43,
+ EXYNOS4_GPIO_Y44,
+ EXYNOS4_GPIO_Y45,
+ EXYNOS4_GPIO_Y46,
+ EXYNOS4_GPIO_Y47,
+ EXYNOS4_GPIO_Y50, /* 240 0xF0 */
+ EXYNOS4_GPIO_Y51,
+ EXYNOS4_GPIO_Y52,
+ EXYNOS4_GPIO_Y53,
+ EXYNOS4_GPIO_Y54,
+ EXYNOS4_GPIO_Y55,
+ EXYNOS4_GPIO_Y56,
+ EXYNOS4_GPIO_Y57,
+ EXYNOS4_GPIO_Y60, /* 248 0xF8 */
+ EXYNOS4_GPIO_Y61,
+ EXYNOS4_GPIO_Y62,
+ EXYNOS4_GPIO_Y63,
+ EXYNOS4_GPIO_Y64,
+ EXYNOS4_GPIO_Y65,
+ EXYNOS4_GPIO_Y66,
+ EXYNOS4_GPIO_Y67,
+
+ /* GPIO_PART2_1 STARTS */
+ EXYNOS4_GPIO_MAX_PORT_PART_2_0, /* 256 0x100 */
+ EXYNOS4_GPIO_X00 = EXYNOS4_GPIO_MAX_PORT_PART_2_0,
+ EXYNOS4_GPIO_X01,
+ EXYNOS4_GPIO_X02,
+ EXYNOS4_GPIO_X03,
+ EXYNOS4_GPIO_X04,
+ EXYNOS4_GPIO_X05,
+ EXYNOS4_GPIO_X06,
+ EXYNOS4_GPIO_X07,
+ EXYNOS4_GPIO_X10, /* 264 0x108 */
+ EXYNOS4_GPIO_X11,
+ EXYNOS4_GPIO_X12,
+ EXYNOS4_GPIO_X13,
+ EXYNOS4_GPIO_X14,
+ EXYNOS4_GPIO_X15,
+ EXYNOS4_GPIO_X16,
+ EXYNOS4_GPIO_X17,
+ EXYNOS4_GPIO_X20, /* 272 0x110 */
+ EXYNOS4_GPIO_X21,
+ EXYNOS4_GPIO_X22,
+ EXYNOS4_GPIO_X23,
+ EXYNOS4_GPIO_X24,
+ EXYNOS4_GPIO_X25,
+ EXYNOS4_GPIO_X26,
+ EXYNOS4_GPIO_X27,
+ EXYNOS4_GPIO_X30, /* 280 0x118 */
+ EXYNOS4_GPIO_X31,
+ EXYNOS4_GPIO_X32,
+ EXYNOS4_GPIO_X33,
+ EXYNOS4_GPIO_X34,
+ EXYNOS4_GPIO_X35,
+ EXYNOS4_GPIO_X36,
+ EXYNOS4_GPIO_X37,
+
+ /* GPIO_PART3_STARTS */
+ EXYNOS4_GPIO_MAX_PORT_PART_2_1, /* 288 0x120 */
+ EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2_1,
+ EXYNOS4_GPIO_Z1,
+ EXYNOS4_GPIO_Z2,
+ EXYNOS4_GPIO_Z3,
+ EXYNOS4_GPIO_Z4,
+ EXYNOS4_GPIO_Z5,
+ EXYNOS4_GPIO_Z6,
+ EXYNOS4_GPIO_Z7,
+
+ EXYNOS4_GPIO_MAX_PORT
+};
+
+enum exynos4X12_gpio_pin {
+ /* EXYNOS4X12_GPIO_PART1_0 starts here */
+ EXYNOS4X12_GPIO_A00, /* 0 */
+ EXYNOS4X12_GPIO_A01,
+ EXYNOS4X12_GPIO_A02,
+ EXYNOS4X12_GPIO_A03,
+ EXYNOS4X12_GPIO_A04,
+ EXYNOS4X12_GPIO_A05,
+ EXYNOS4X12_GPIO_A06,
+ EXYNOS4X12_GPIO_A07,
+ EXYNOS4X12_GPIO_A10, /* 8 */
+ EXYNOS4X12_GPIO_A11,
+ EXYNOS4X12_GPIO_A12,
+ EXYNOS4X12_GPIO_A13,
+ EXYNOS4X12_GPIO_A14,
+ EXYNOS4X12_GPIO_A15,
+ EXYNOS4X12_GPIO_A16,
+ EXYNOS4X12_GPIO_A17,
+ EXYNOS4X12_GPIO_B0, /* 16 0x10 */
+ EXYNOS4X12_GPIO_B1,
+ EXYNOS4X12_GPIO_B2,
+ EXYNOS4X12_GPIO_B3,
+ EXYNOS4X12_GPIO_B4,
+ EXYNOS4X12_GPIO_B5,
+ EXYNOS4X12_GPIO_B6,
+ EXYNOS4X12_GPIO_B7,
+ EXYNOS4X12_GPIO_C00, /* 24 0x18 */
+ EXYNOS4X12_GPIO_C01,
+ EXYNOS4X12_GPIO_C02,
+ EXYNOS4X12_GPIO_C03,
+ EXYNOS4X12_GPIO_C04,
+ EXYNOS4X12_GPIO_C05,
+ EXYNOS4X12_GPIO_C06,
+ EXYNOS4X12_GPIO_C07,
+ EXYNOS4X12_GPIO_C10, /* 32 0x20 */
+ EXYNOS4X12_GPIO_C11,
+ EXYNOS4X12_GPIO_C12,
+ EXYNOS4X12_GPIO_C13,
+ EXYNOS4X12_GPIO_C14,
+ EXYNOS4X12_GPIO_C15,
+ EXYNOS4X12_GPIO_C16,
+ EXYNOS4X12_GPIO_C17,
+ EXYNOS4X12_GPIO_D00, /* 40 0x28 */
+ EXYNOS4X12_GPIO_D01,
+ EXYNOS4X12_GPIO_D02,
+ EXYNOS4X12_GPIO_D03,
+ EXYNOS4X12_GPIO_D04,
+ EXYNOS4X12_GPIO_D05,
+ EXYNOS4X12_GPIO_D06,
+ EXYNOS4X12_GPIO_D07,
+ EXYNOS4X12_GPIO_D10, /* 48 0x30 */
+ EXYNOS4X12_GPIO_D11,
+ EXYNOS4X12_GPIO_D12,
+ EXYNOS4X12_GPIO_D13,
+ EXYNOS4X12_GPIO_D14,
+ EXYNOS4X12_GPIO_D15,
+ EXYNOS4X12_GPIO_D16,
+ EXYNOS4X12_GPIO_D17,
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, /* 56 0x38 */
+ /* EXYNOS4X12_GPIO_PART1_1 starts here */
+ EXYNOS4X12_GPIO_F00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_0,
+ EXYNOS4X12_GPIO_F01,
+ EXYNOS4X12_GPIO_F02,
+ EXYNOS4X12_GPIO_F03,
+ EXYNOS4X12_GPIO_F04,
+ EXYNOS4X12_GPIO_F05,
+ EXYNOS4X12_GPIO_F06,
+ EXYNOS4X12_GPIO_F07,
+ EXYNOS4X12_GPIO_F10, /* 64 0x40 */
+ EXYNOS4X12_GPIO_F11,
+ EXYNOS4X12_GPIO_F12,
+ EXYNOS4X12_GPIO_F13,
+ EXYNOS4X12_GPIO_F14,
+ EXYNOS4X12_GPIO_F15,
+ EXYNOS4X12_GPIO_F16,
+ EXYNOS4X12_GPIO_F17,
+ EXYNOS4X12_GPIO_F20, /* 72 0x48 */
+ EXYNOS4X12_GPIO_F21,
+ EXYNOS4X12_GPIO_F22,
+ EXYNOS4X12_GPIO_F23,
+ EXYNOS4X12_GPIO_F24,
+ EXYNOS4X12_GPIO_F25,
+ EXYNOS4X12_GPIO_F26,
+ EXYNOS4X12_GPIO_F27,
+ EXYNOS4X12_GPIO_F30, /* 80 0x50 */
+ EXYNOS4X12_GPIO_F31,
+ EXYNOS4X12_GPIO_F32,
+ EXYNOS4X12_GPIO_F33,
+ EXYNOS4X12_GPIO_F34,
+ EXYNOS4X12_GPIO_F35,
+ EXYNOS4X12_GPIO_F36,
+ EXYNOS4X12_GPIO_F37,
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, /* 88 0x58 */
+ /* EXYNOS4X12_GPIO_PART1_2 starts here */
+ EXYNOS4X12_GPIO_J00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_1,
+ EXYNOS4X12_GPIO_J01,
+ EXYNOS4X12_GPIO_J02,
+ EXYNOS4X12_GPIO_J03,
+ EXYNOS4X12_GPIO_J04,
+ EXYNOS4X12_GPIO_J05,
+ EXYNOS4X12_GPIO_J06,
+ EXYNOS4X12_GPIO_J07,
+ EXYNOS4X12_GPIO_J10, /* 96 0x60 */
+ EXYNOS4X12_GPIO_J11,
+ EXYNOS4X12_GPIO_J12,
+ EXYNOS4X12_GPIO_J13,
+ EXYNOS4X12_GPIO_J14,
+ EXYNOS4X12_GPIO_J15,
+ EXYNOS4X12_GPIO_J16,
+ EXYNOS4X12_GPIO_J17,
+
+ /**
+ * EXYNOS4X12_GPIO_PART2_0 is not used
+ * EXYNOS4X12_GPIO_PART2_1 starts here
+ */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, /* 104 0x66 */
+ EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_2,
+ EXYNOS4X12_GPIO_K01,
+ EXYNOS4X12_GPIO_K02,
+ EXYNOS4X12_GPIO_K03,
+ EXYNOS4X12_GPIO_K04,
+ EXYNOS4X12_GPIO_K05,
+ EXYNOS4X12_GPIO_K06,
+ EXYNOS4X12_GPIO_K07,
+ EXYNOS4X12_GPIO_K10, /* 112 0x70 */
+ EXYNOS4X12_GPIO_K11,
+ EXYNOS4X12_GPIO_K12,
+ EXYNOS4X12_GPIO_K13,
+ EXYNOS4X12_GPIO_K14,
+ EXYNOS4X12_GPIO_K15,
+ EXYNOS4X12_GPIO_K16,
+ EXYNOS4X12_GPIO_K17,
+ EXYNOS4X12_GPIO_K20, /* 120 0x78 */
+ EXYNOS4X12_GPIO_K21,
+ EXYNOS4X12_GPIO_K22,
+ EXYNOS4X12_GPIO_K23,
+ EXYNOS4X12_GPIO_K24,
+ EXYNOS4X12_GPIO_K25,
+ EXYNOS4X12_GPIO_K26,
+ EXYNOS4X12_GPIO_K27,
+ EXYNOS4X12_GPIO_K30, /* 128 0x80 */
+ EXYNOS4X12_GPIO_K31,
+ EXYNOS4X12_GPIO_K32,
+ EXYNOS4X12_GPIO_K33,
+ EXYNOS4X12_GPIO_K34,
+ EXYNOS4X12_GPIO_K35,
+ EXYNOS4X12_GPIO_K36,
+ EXYNOS4X12_GPIO_K37,
+ EXYNOS4X12_GPIO_L00, /* 136 0x88 */
+ EXYNOS4X12_GPIO_L01,
+ EXYNOS4X12_GPIO_L02,
+ EXYNOS4X12_GPIO_L03,
+ EXYNOS4X12_GPIO_L04,
+ EXYNOS4X12_GPIO_L05,
+ EXYNOS4X12_GPIO_L06,
+ EXYNOS4X12_GPIO_L07,
+ EXYNOS4X12_GPIO_L10, /* 144 0x90 */
+ EXYNOS4X12_GPIO_L11,
+ EXYNOS4X12_GPIO_L12,
+ EXYNOS4X12_GPIO_L13,
+ EXYNOS4X12_GPIO_L14,
+ EXYNOS4X12_GPIO_L15,
+ EXYNOS4X12_GPIO_L16,
+ EXYNOS4X12_GPIO_L17,
+ EXYNOS4X12_GPIO_L20, /* 152 0x98 */
+ EXYNOS4X12_GPIO_L21,
+ EXYNOS4X12_GPIO_L22,
+ EXYNOS4X12_GPIO_L23,
+ EXYNOS4X12_GPIO_L24,
+ EXYNOS4X12_GPIO_L25,
+ EXYNOS4X12_GPIO_L26,
+ EXYNOS4X12_GPIO_L27,
+ EXYNOS4X12_GPIO_Y00, /* 160 0xa0 */
+ EXYNOS4X12_GPIO_Y01,
+ EXYNOS4X12_GPIO_Y02,
+ EXYNOS4X12_GPIO_Y03,
+ EXYNOS4X12_GPIO_Y04,
+ EXYNOS4X12_GPIO_Y05,
+ EXYNOS4X12_GPIO_Y06,
+ EXYNOS4X12_GPIO_Y07,
+ EXYNOS4X12_GPIO_Y10, /* 168 0xa8 */
+ EXYNOS4X12_GPIO_Y11,
+ EXYNOS4X12_GPIO_Y12,
+ EXYNOS4X12_GPIO_Y13,
+ EXYNOS4X12_GPIO_Y14,
+ EXYNOS4X12_GPIO_Y15,
+ EXYNOS4X12_GPIO_Y16,
+ EXYNOS4X12_GPIO_Y17,
+ EXYNOS4X12_GPIO_Y20, /* 176 0xb0 */
+ EXYNOS4X12_GPIO_Y21,
+ EXYNOS4X12_GPIO_Y22,
+ EXYNOS4X12_GPIO_Y23,
+ EXYNOS4X12_GPIO_Y24,
+ EXYNOS4X12_GPIO_Y25,
+ EXYNOS4X12_GPIO_Y26,
+ EXYNOS4X12_GPIO_Y27,
+ EXYNOS4X12_GPIO_Y30, /* 184 0xb8 */
+ EXYNOS4X12_GPIO_Y31,
+ EXYNOS4X12_GPIO_Y32,
+ EXYNOS4X12_GPIO_Y33,
+ EXYNOS4X12_GPIO_Y34,
+ EXYNOS4X12_GPIO_Y35,
+ EXYNOS4X12_GPIO_Y36,
+ EXYNOS4X12_GPIO_Y37,
+ EXYNOS4X12_GPIO_Y40, /* 192 0xc0 */
+ EXYNOS4X12_GPIO_Y41,
+ EXYNOS4X12_GPIO_Y42,
+ EXYNOS4X12_GPIO_Y43,
+ EXYNOS4X12_GPIO_Y44,
+ EXYNOS4X12_GPIO_Y45,
+ EXYNOS4X12_GPIO_Y46,
+ EXYNOS4X12_GPIO_Y47,
+ EXYNOS4X12_GPIO_Y50, /* 200 0xc8 */
+ EXYNOS4X12_GPIO_Y51,
+ EXYNOS4X12_GPIO_Y52,
+ EXYNOS4X12_GPIO_Y53,
+ EXYNOS4X12_GPIO_Y54,
+ EXYNOS4X12_GPIO_Y55,
+ EXYNOS4X12_GPIO_Y56,
+ EXYNOS4X12_GPIO_Y57,
+ EXYNOS4X12_GPIO_Y60, /* 208 0xd0 */
+ EXYNOS4X12_GPIO_Y61,
+ EXYNOS4X12_GPIO_Y62,
+ EXYNOS4X12_GPIO_Y63,
+ EXYNOS4X12_GPIO_Y64,
+ EXYNOS4X12_GPIO_Y65,
+ EXYNOS4X12_GPIO_Y66,
+ EXYNOS4X12_GPIO_Y67,
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, /* 216 0xd8 */
+ /* EXYNOS4X12_GPIO_PART2_2 starts here */
+ EXYNOS4X12_GPIO_M00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_1,
+ EXYNOS4X12_GPIO_M01,
+ EXYNOS4X12_GPIO_M02,
+ EXYNOS4X12_GPIO_M03,
+ EXYNOS4X12_GPIO_M04,
+ EXYNOS4X12_GPIO_M05,
+ EXYNOS4X12_GPIO_M06,
+ EXYNOS4X12_GPIO_M07,
+ EXYNOS4X12_GPIO_M10, /* 224 0xe0 */
+ EXYNOS4X12_GPIO_M11,
+ EXYNOS4X12_GPIO_M12,
+ EXYNOS4X12_GPIO_M13,
+ EXYNOS4X12_GPIO_M14,
+ EXYNOS4X12_GPIO_M15,
+ EXYNOS4X12_GPIO_M16,
+ EXYNOS4X12_GPIO_M17,
+ EXYNOS4X12_GPIO_M20, /* 232 0xe8 */
+ EXYNOS4X12_GPIO_M21,
+ EXYNOS4X12_GPIO_M22,
+ EXYNOS4X12_GPIO_M23,
+ EXYNOS4X12_GPIO_M24,
+ EXYNOS4X12_GPIO_M25,
+ EXYNOS4X12_GPIO_M26,
+ EXYNOS4X12_GPIO_M27,
+ EXYNOS4X12_GPIO_M30, /* 240 0xf0 */
+ EXYNOS4X12_GPIO_M31,
+ EXYNOS4X12_GPIO_M32,
+ EXYNOS4X12_GPIO_M33,
+ EXYNOS4X12_GPIO_M34,
+ EXYNOS4X12_GPIO_M35,
+ EXYNOS4X12_GPIO_M36,
+ EXYNOS4X12_GPIO_M37,
+ EXYNOS4X12_GPIO_M40, /* 248 0xf8 */
+ EXYNOS4X12_GPIO_M41,
+ EXYNOS4X12_GPIO_M42,
+ EXYNOS4X12_GPIO_M43,
+ EXYNOS4X12_GPIO_M44,
+ EXYNOS4X12_GPIO_M45,
+ EXYNOS4X12_GPIO_M46,
+ EXYNOS4X12_GPIO_M47,
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, /* 256 0x100 */
+ /* EXYNOS4X12_GPIO_PART2_3 starts here */
+ EXYNOS4X12_GPIO_X00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_2,
+ EXYNOS4X12_GPIO_X01,
+ EXYNOS4X12_GPIO_X02,
+ EXYNOS4X12_GPIO_X03,
+ EXYNOS4X12_GPIO_X04,
+ EXYNOS4X12_GPIO_X05,
+ EXYNOS4X12_GPIO_X06,
+ EXYNOS4X12_GPIO_X07,
+ EXYNOS4X12_GPIO_X10, /* 264 0x108 */
+ EXYNOS4X12_GPIO_X11,
+ EXYNOS4X12_GPIO_X12,
+ EXYNOS4X12_GPIO_X13,
+ EXYNOS4X12_GPIO_X14,
+ EXYNOS4X12_GPIO_X15,
+ EXYNOS4X12_GPIO_X16,
+ EXYNOS4X12_GPIO_X17,
+ EXYNOS4X12_GPIO_X20, /* 272 0x110 */
+ EXYNOS4X12_GPIO_X21,
+ EXYNOS4X12_GPIO_X22,
+ EXYNOS4X12_GPIO_X23,
+ EXYNOS4X12_GPIO_X24,
+ EXYNOS4X12_GPIO_X25,
+ EXYNOS4X12_GPIO_X26,
+ EXYNOS4X12_GPIO_X27,
+ EXYNOS4X12_GPIO_X30, /* 280 0x118 */
+ EXYNOS4X12_GPIO_X31,
+ EXYNOS4X12_GPIO_X32,
+ EXYNOS4X12_GPIO_X33,
+ EXYNOS4X12_GPIO_X34,
+ EXYNOS4X12_GPIO_X35,
+ EXYNOS4X12_GPIO_X36,
+ EXYNOS4X12_GPIO_X37,
+
+ /* EXYNOS4X12_GPIO_PART3 starts here */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, /* 288 0x120 */
+ EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_3,
+ EXYNOS4X12_GPIO_Z1,
+ EXYNOS4X12_GPIO_Z2,
+ EXYNOS4X12_GPIO_Z3,
+ EXYNOS4X12_GPIO_Z4,
+ EXYNOS4X12_GPIO_Z5,
+ EXYNOS4X12_GPIO_Z6,
+ EXYNOS4X12_GPIO_Z7,
+
+ /* EXYNOS4X12_GPIO_PART4 starts here */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */
+ EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3,
+ EXYNOS4X12_GPIO_V01,
+ EXYNOS4X12_GPIO_V02,
+ EXYNOS4X12_GPIO_V03,
+ EXYNOS4X12_GPIO_V04,
+ EXYNOS4X12_GPIO_V05,
+ EXYNOS4X12_GPIO_V06,
+ EXYNOS4X12_GPIO_V07,
+ EXYNOS4X12_GPIO_V10, /* 304 0x130 */
+ EXYNOS4X12_GPIO_V11,
+ EXYNOS4X12_GPIO_V12,
+ EXYNOS4X12_GPIO_V13,
+ EXYNOS4X12_GPIO_V14,
+ EXYNOS4X12_GPIO_V15,
+ EXYNOS4X12_GPIO_V16,
+ EXYNOS4X12_GPIO_V17,
+ EXYNOS4X12_GPIO_V20, /* 312 0x138 */
+ EXYNOS4X12_GPIO_V21,
+ EXYNOS4X12_GPIO_V22,
+ EXYNOS4X12_GPIO_V23,
+ EXYNOS4X12_GPIO_V24,
+ EXYNOS4X12_GPIO_V25,
+ EXYNOS4X12_GPIO_V26,
+ EXYNOS4X12_GPIO_V27,
+ EXYNOS4X12_GPIO_V30, /* 320 0x140 */
+ EXYNOS4X12_GPIO_V31,
+ EXYNOS4X12_GPIO_V32,
+ EXYNOS4X12_GPIO_V33,
+ EXYNOS4X12_GPIO_V34,
+ EXYNOS4X12_GPIO_V35,
+ EXYNOS4X12_GPIO_V36,
+ EXYNOS4X12_GPIO_V37,
+ EXYNOS4X12_GPIO_V40, /* 328 0x148 */
+ EXYNOS4X12_GPIO_V41,
+ EXYNOS4X12_GPIO_V42,
+ EXYNOS4X12_GPIO_V43,
+ EXYNOS4X12_GPIO_V44,
+ EXYNOS4X12_GPIO_V45,
+ EXYNOS4X12_GPIO_V46,
+ EXYNOS4X12_GPIO_V47,
+
+ EXYNOS4X12_GPIO_MAX_PORT
+};
+
+enum exynos5_gpio_pin {
+ /* GPIO_PART1_STARTS */
+ EXYNOS5_GPIO_A00, /* 0 */
+ EXYNOS5_GPIO_A01,
+ EXYNOS5_GPIO_A02,
+ EXYNOS5_GPIO_A03,
+ EXYNOS5_GPIO_A04,
+ EXYNOS5_GPIO_A05,
+ EXYNOS5_GPIO_A06,
+ EXYNOS5_GPIO_A07,
+ EXYNOS5_GPIO_A10, /* 8 */
+ EXYNOS5_GPIO_A11,
+ EXYNOS5_GPIO_A12,
+ EXYNOS5_GPIO_A13,
+ EXYNOS5_GPIO_A14,
+ EXYNOS5_GPIO_A15,
+ EXYNOS5_GPIO_A16,
+ EXYNOS5_GPIO_A17,
+ EXYNOS5_GPIO_A20, /* 16 0x10 */
+ EXYNOS5_GPIO_A21,
+ EXYNOS5_GPIO_A22,
+ EXYNOS5_GPIO_A23,
+ EXYNOS5_GPIO_A24,
+ EXYNOS5_GPIO_A25,
+ EXYNOS5_GPIO_A26,
+ EXYNOS5_GPIO_A27,
+ EXYNOS5_GPIO_B00, /* 24 0x18 */
+ EXYNOS5_GPIO_B01,
+ EXYNOS5_GPIO_B02,
+ EXYNOS5_GPIO_B03,
+ EXYNOS5_GPIO_B04,
+ EXYNOS5_GPIO_B05,
+ EXYNOS5_GPIO_B06,
+ EXYNOS5_GPIO_B07,
+ EXYNOS5_GPIO_B10, /* 32 0x20 */
+ EXYNOS5_GPIO_B11,
+ EXYNOS5_GPIO_B12,
+ EXYNOS5_GPIO_B13,
+ EXYNOS5_GPIO_B14,
+ EXYNOS5_GPIO_B15,
+ EXYNOS5_GPIO_B16,
+ EXYNOS5_GPIO_B17,
+ EXYNOS5_GPIO_B20, /* 40 0x28 */
+ EXYNOS5_GPIO_B21,
+ EXYNOS5_GPIO_B22,
+ EXYNOS5_GPIO_B23,
+ EXYNOS5_GPIO_B24,
+ EXYNOS5_GPIO_B25,
+ EXYNOS5_GPIO_B26,
+ EXYNOS5_GPIO_B27,
+ EXYNOS5_GPIO_B30, /* 48 0x39 */
+ EXYNOS5_GPIO_B31,
+ EXYNOS5_GPIO_B32,
+ EXYNOS5_GPIO_B33,
+ EXYNOS5_GPIO_B34,
+ EXYNOS5_GPIO_B35,
+ EXYNOS5_GPIO_B36,
+ EXYNOS5_GPIO_B37,
+ EXYNOS5_GPIO_C00, /* 56 0x38 */
+ EXYNOS5_GPIO_C01,
+ EXYNOS5_GPIO_C02,
+ EXYNOS5_GPIO_C03,
+ EXYNOS5_GPIO_C04,
+ EXYNOS5_GPIO_C05,
+ EXYNOS5_GPIO_C06,
+ EXYNOS5_GPIO_C07,
+ EXYNOS5_GPIO_C10, /* 64 0x40 */
+ EXYNOS5_GPIO_C11,
+ EXYNOS5_GPIO_C12,
+ EXYNOS5_GPIO_C13,
+ EXYNOS5_GPIO_C14,
+ EXYNOS5_GPIO_C15,
+ EXYNOS5_GPIO_C16,
+ EXYNOS5_GPIO_C17,
+ EXYNOS5_GPIO_C20, /* 72 0x48 */
+ EXYNOS5_GPIO_C21,
+ EXYNOS5_GPIO_C22,
+ EXYNOS5_GPIO_C23,
+ EXYNOS5_GPIO_C24,
+ EXYNOS5_GPIO_C25,
+ EXYNOS5_GPIO_C26,
+ EXYNOS5_GPIO_C27,
+ EXYNOS5_GPIO_C30, /* 80 0x50 */
+ EXYNOS5_GPIO_C31,
+ EXYNOS5_GPIO_C32,
+ EXYNOS5_GPIO_C33,
+ EXYNOS5_GPIO_C34,
+ EXYNOS5_GPIO_C35,
+ EXYNOS5_GPIO_C36,
+ EXYNOS5_GPIO_C37,
+ EXYNOS5_GPIO_D00, /* 88 0x58 */
+ EXYNOS5_GPIO_D01,
+ EXYNOS5_GPIO_D02,
+ EXYNOS5_GPIO_D03,
+ EXYNOS5_GPIO_D04,
+ EXYNOS5_GPIO_D05,
+ EXYNOS5_GPIO_D06,
+ EXYNOS5_GPIO_D07,
+ EXYNOS5_GPIO_D10, /* 96 0x60 */
+ EXYNOS5_GPIO_D11,
+ EXYNOS5_GPIO_D12,
+ EXYNOS5_GPIO_D13,
+ EXYNOS5_GPIO_D14,
+ EXYNOS5_GPIO_D15,
+ EXYNOS5_GPIO_D16,
+ EXYNOS5_GPIO_D17,
+ EXYNOS5_GPIO_Y00, /* 104 0x68 */
+ EXYNOS5_GPIO_Y01,
+ EXYNOS5_GPIO_Y02,
+ EXYNOS5_GPIO_Y03,
+ EXYNOS5_GPIO_Y04,
+ EXYNOS5_GPIO_Y05,
+ EXYNOS5_GPIO_Y06,
+ EXYNOS5_GPIO_Y07,
+ EXYNOS5_GPIO_Y10, /* 112 0x70 */
+ EXYNOS5_GPIO_Y11,
+ EXYNOS5_GPIO_Y12,
+ EXYNOS5_GPIO_Y13,
+ EXYNOS5_GPIO_Y14,
+ EXYNOS5_GPIO_Y15,
+ EXYNOS5_GPIO_Y16,
+ EXYNOS5_GPIO_Y17,
+ EXYNOS5_GPIO_Y20, /* 120 0x78 */
+ EXYNOS5_GPIO_Y21,
+ EXYNOS5_GPIO_Y22,
+ EXYNOS5_GPIO_Y23,
+ EXYNOS5_GPIO_Y24,
+ EXYNOS5_GPIO_Y25,
+ EXYNOS5_GPIO_Y26,
+ EXYNOS5_GPIO_Y27,
+ EXYNOS5_GPIO_Y30, /* 128 0x80 */
+ EXYNOS5_GPIO_Y31,
+ EXYNOS5_GPIO_Y32,
+ EXYNOS5_GPIO_Y33,
+ EXYNOS5_GPIO_Y34,
+ EXYNOS5_GPIO_Y35,
+ EXYNOS5_GPIO_Y36,
+ EXYNOS5_GPIO_Y37,
+ EXYNOS5_GPIO_Y40, /* 136 0x88 */
+ EXYNOS5_GPIO_Y41,
+ EXYNOS5_GPIO_Y42,
+ EXYNOS5_GPIO_Y43,
+ EXYNOS5_GPIO_Y44,
+ EXYNOS5_GPIO_Y45,
+ EXYNOS5_GPIO_Y46,
+ EXYNOS5_GPIO_Y47,
+ EXYNOS5_GPIO_Y50, /* 144 0x90 */
+ EXYNOS5_GPIO_Y51,
+ EXYNOS5_GPIO_Y52,
+ EXYNOS5_GPIO_Y53,
+ EXYNOS5_GPIO_Y54,
+ EXYNOS5_GPIO_Y55,
+ EXYNOS5_GPIO_Y56,
+ EXYNOS5_GPIO_Y57,
+ EXYNOS5_GPIO_Y60, /* 152 0x98 */
+ EXYNOS5_GPIO_Y61,
+ EXYNOS5_GPIO_Y62,
+ EXYNOS5_GPIO_Y63,
+ EXYNOS5_GPIO_Y64,
+ EXYNOS5_GPIO_Y65,
+ EXYNOS5_GPIO_Y66,
+ EXYNOS5_GPIO_Y67,
+
+ /* GPIO_PART2_STARTS */
+ EXYNOS5_GPIO_MAX_PORT_PART_1, /* 160 0xa0 */
+ EXYNOS5_GPIO_C40 = EXYNOS5_GPIO_MAX_PORT_PART_1,
+ EXYNOS5_GPIO_C41,
+ EXYNOS5_GPIO_C42,
+ EXYNOS5_GPIO_C43,
+ EXYNOS5_GPIO_C44,
+ EXYNOS5_GPIO_C45,
+ EXYNOS5_GPIO_C46,
+ EXYNOS5_GPIO_C47,
+
+ /* GPIO_PART3_STARTS */
+ EXYNOS5_GPIO_MAX_PORT_PART_2, /* 168 0xa8 */
+ EXYNOS5_GPIO_X00 = EXYNOS5_GPIO_MAX_PORT_PART_2,
+ EXYNOS5_GPIO_X01,
+ EXYNOS5_GPIO_X02,
+ EXYNOS5_GPIO_X03,
+ EXYNOS5_GPIO_X04,
+ EXYNOS5_GPIO_X05,
+ EXYNOS5_GPIO_X06,
+ EXYNOS5_GPIO_X07,
+ EXYNOS5_GPIO_X10, /* 176 0xb0 */
+ EXYNOS5_GPIO_X11,
+ EXYNOS5_GPIO_X12,
+ EXYNOS5_GPIO_X13,
+ EXYNOS5_GPIO_X14,
+ EXYNOS5_GPIO_X15,
+ EXYNOS5_GPIO_X16,
+ EXYNOS5_GPIO_X17,
+ EXYNOS5_GPIO_X20, /* 184 0xb8 */
+ EXYNOS5_GPIO_X21,
+ EXYNOS5_GPIO_X22,
+ EXYNOS5_GPIO_X23,
+ EXYNOS5_GPIO_X24,
+ EXYNOS5_GPIO_X25,
+ EXYNOS5_GPIO_X26,
+ EXYNOS5_GPIO_X27,
+ EXYNOS5_GPIO_X30, /* 192 0xc0 */
+ EXYNOS5_GPIO_X31,
+ EXYNOS5_GPIO_X32,
+ EXYNOS5_GPIO_X33,
+ EXYNOS5_GPIO_X34,
+ EXYNOS5_GPIO_X35,
+ EXYNOS5_GPIO_X36,
+ EXYNOS5_GPIO_X37,
+
+ /* GPIO_PART4_STARTS */
+ EXYNOS5_GPIO_MAX_PORT_PART_3, /* 200 0xc8 */
+ EXYNOS5_GPIO_E00 = EXYNOS5_GPIO_MAX_PORT_PART_3,
+ EXYNOS5_GPIO_E01,
+ EXYNOS5_GPIO_E02,
+ EXYNOS5_GPIO_E03,
+ EXYNOS5_GPIO_E04,
+ EXYNOS5_GPIO_E05,
+ EXYNOS5_GPIO_E06,
+ EXYNOS5_GPIO_E07,
+ EXYNOS5_GPIO_E10, /* 208 0xd0 */
+ EXYNOS5_GPIO_E11,
+ EXYNOS5_GPIO_E12,
+ EXYNOS5_GPIO_E13,
+ EXYNOS5_GPIO_E14,
+ EXYNOS5_GPIO_E15,
+ EXYNOS5_GPIO_E16,
+ EXYNOS5_GPIO_E17,
+ EXYNOS5_GPIO_F00, /* 216 0xd8 */
+ EXYNOS5_GPIO_F01,
+ EXYNOS5_GPIO_F02,
+ EXYNOS5_GPIO_F03,
+ EXYNOS5_GPIO_F04,
+ EXYNOS5_GPIO_F05,
+ EXYNOS5_GPIO_F06,
+ EXYNOS5_GPIO_F07,
+ EXYNOS5_GPIO_F10, /* 224 0xe0 */
+ EXYNOS5_GPIO_F11,
+ EXYNOS5_GPIO_F12,
+ EXYNOS5_GPIO_F13,
+ EXYNOS5_GPIO_F14,
+ EXYNOS5_GPIO_F15,
+ EXYNOS5_GPIO_F16,
+ EXYNOS5_GPIO_F17,
+ EXYNOS5_GPIO_G00, /* 232 0xe8 */
+ EXYNOS5_GPIO_G01,
+ EXYNOS5_GPIO_G02,
+ EXYNOS5_GPIO_G03,
+ EXYNOS5_GPIO_G04,
+ EXYNOS5_GPIO_G05,
+ EXYNOS5_GPIO_G06,
+ EXYNOS5_GPIO_G07,
+ EXYNOS5_GPIO_G10, /* 240 0xf0 */
+ EXYNOS5_GPIO_G11,
+ EXYNOS5_GPIO_G12,
+ EXYNOS5_GPIO_G13,
+ EXYNOS5_GPIO_G14,
+ EXYNOS5_GPIO_G15,
+ EXYNOS5_GPIO_G16,
+ EXYNOS5_GPIO_G17,
+ EXYNOS5_GPIO_G20, /* 248 0xf8 */
+ EXYNOS5_GPIO_G21,
+ EXYNOS5_GPIO_G22,
+ EXYNOS5_GPIO_G23,
+ EXYNOS5_GPIO_G24,
+ EXYNOS5_GPIO_G25,
+ EXYNOS5_GPIO_G26,
+ EXYNOS5_GPIO_G27,
+ EXYNOS5_GPIO_H00, /* 256 0x100 */
+ EXYNOS5_GPIO_H01,
+ EXYNOS5_GPIO_H02,
+ EXYNOS5_GPIO_H03,
+ EXYNOS5_GPIO_H04,
+ EXYNOS5_GPIO_H05,
+ EXYNOS5_GPIO_H06,
+ EXYNOS5_GPIO_H07,
+ EXYNOS5_GPIO_H10, /* 264 0x108 */
+ EXYNOS5_GPIO_H11,
+ EXYNOS5_GPIO_H12,
+ EXYNOS5_GPIO_H13,
+ EXYNOS5_GPIO_H14,
+ EXYNOS5_GPIO_H15,
+ EXYNOS5_GPIO_H16,
+ EXYNOS5_GPIO_H17,
+
+ /* GPIO_PART4_STARTS */
+ EXYNOS5_GPIO_MAX_PORT_PART_4, /* 272 0x110 */
+ EXYNOS5_GPIO_V00 = EXYNOS5_GPIO_MAX_PORT_PART_4,
+ EXYNOS5_GPIO_V01,
+ EXYNOS5_GPIO_V02,
+ EXYNOS5_GPIO_V03,
+ EXYNOS5_GPIO_V04,
+ EXYNOS5_GPIO_V05,
+ EXYNOS5_GPIO_V06,
+ EXYNOS5_GPIO_V07,
+ EXYNOS5_GPIO_V10, /* 280 0x118 */
+ EXYNOS5_GPIO_V11,
+ EXYNOS5_GPIO_V12,
+ EXYNOS5_GPIO_V13,
+ EXYNOS5_GPIO_V14,
+ EXYNOS5_GPIO_V15,
+ EXYNOS5_GPIO_V16,
+ EXYNOS5_GPIO_V17,
+
+ /* GPIO_PART5_STARTS */
+ EXYNOS5_GPIO_MAX_PORT_PART_5, /* 288 0x120 */
+ EXYNOS5_GPIO_V20 = EXYNOS5_GPIO_MAX_PORT_PART_5,
+ EXYNOS5_GPIO_V21,
+ EXYNOS5_GPIO_V22,
+ EXYNOS5_GPIO_V23,
+ EXYNOS5_GPIO_V24,
+ EXYNOS5_GPIO_V25,
+ EXYNOS5_GPIO_V26,
+ EXYNOS5_GPIO_V27,
+ EXYNOS5_GPIO_V30, /* 296 0x128 */
+ EXYNOS5_GPIO_V31,
+ EXYNOS5_GPIO_V32,
+ EXYNOS5_GPIO_V33,
+ EXYNOS5_GPIO_V34,
+ EXYNOS5_GPIO_V35,
+ EXYNOS5_GPIO_V36,
+ EXYNOS5_GPIO_V37,
+
+ /* GPIO_PART6_STARTS */
+ EXYNOS5_GPIO_MAX_PORT_PART_6, /* 304 0x130 */
+ EXYNOS5_GPIO_V40 = EXYNOS5_GPIO_MAX_PORT_PART_6,
+ EXYNOS5_GPIO_V41,
+ EXYNOS5_GPIO_V42,
+ EXYNOS5_GPIO_V43,
+ EXYNOS5_GPIO_V44,
+ EXYNOS5_GPIO_V45,
+ EXYNOS5_GPIO_V46,
+ EXYNOS5_GPIO_V47,
+
+ /* GPIO_PART7_STARTS */ /* 312 0x138 */
+ EXYNOS5_GPIO_MAX_PORT_PART_7,
+ EXYNOS5_GPIO_Z0 = EXYNOS5_GPIO_MAX_PORT_PART_7,
+ EXYNOS5_GPIO_Z1,
+ EXYNOS5_GPIO_Z2,
+ EXYNOS5_GPIO_Z3,
+ EXYNOS5_GPIO_Z4,
+ EXYNOS5_GPIO_Z5,
+ EXYNOS5_GPIO_Z6,
+ EXYNOS5_GPIO_MAX_PORT
+};
+
+enum exynos5420_gpio_pin {
+ /* GPIO_PART1_STARTS */
+ EXYNOS5420_GPIO_A00, /* 0 */
+ EXYNOS5420_GPIO_A01,
+ EXYNOS5420_GPIO_A02,
+ EXYNOS5420_GPIO_A03,
+ EXYNOS5420_GPIO_A04,
+ EXYNOS5420_GPIO_A05,
+ EXYNOS5420_GPIO_A06,
+ EXYNOS5420_GPIO_A07,
+ EXYNOS5420_GPIO_A10, /* 8 */
+ EXYNOS5420_GPIO_A11,
+ EXYNOS5420_GPIO_A12,
+ EXYNOS5420_GPIO_A13,
+ EXYNOS5420_GPIO_A14,
+ EXYNOS5420_GPIO_A15,
+ EXYNOS5420_GPIO_A16,
+ EXYNOS5420_GPIO_A17,
+ EXYNOS5420_GPIO_A20, /* 16 0x10 */
+ EXYNOS5420_GPIO_A21,
+ EXYNOS5420_GPIO_A22,
+ EXYNOS5420_GPIO_A23,
+ EXYNOS5420_GPIO_A24,
+ EXYNOS5420_GPIO_A25,
+ EXYNOS5420_GPIO_A26,
+ EXYNOS5420_GPIO_A27,
+ EXYNOS5420_GPIO_B00, /* 24 0x18 */
+ EXYNOS5420_GPIO_B01,
+ EXYNOS5420_GPIO_B02,
+ EXYNOS5420_GPIO_B03,
+ EXYNOS5420_GPIO_B04,
+ EXYNOS5420_GPIO_B05,
+ EXYNOS5420_GPIO_B06,
+ EXYNOS5420_GPIO_B07,
+ EXYNOS5420_GPIO_B10, /* 32 0x20 */
+ EXYNOS5420_GPIO_B11,
+ EXYNOS5420_GPIO_B12,
+ EXYNOS5420_GPIO_B13,
+ EXYNOS5420_GPIO_B14,
+ EXYNOS5420_GPIO_B15,
+ EXYNOS5420_GPIO_B16,
+ EXYNOS5420_GPIO_B17,
+ EXYNOS5420_GPIO_B20, /* 40 0x28 */
+ EXYNOS5420_GPIO_B21,
+ EXYNOS5420_GPIO_B22,
+ EXYNOS5420_GPIO_B23,
+ EXYNOS5420_GPIO_B24,
+ EXYNOS5420_GPIO_B25,
+ EXYNOS5420_GPIO_B26,
+ EXYNOS5420_GPIO_B27,
+ EXYNOS5420_GPIO_B30, /* 48 0x30 */
+ EXYNOS5420_GPIO_B31,
+ EXYNOS5420_GPIO_B32,
+ EXYNOS5420_GPIO_B33,
+ EXYNOS5420_GPIO_B34,
+ EXYNOS5420_GPIO_B35,
+ EXYNOS5420_GPIO_B36,
+ EXYNOS5420_GPIO_B37,
+ EXYNOS5420_GPIO_B40, /* 56 0x38 */
+ EXYNOS5420_GPIO_B41,
+ EXYNOS5420_GPIO_B42,
+ EXYNOS5420_GPIO_B43,
+ EXYNOS5420_GPIO_B44,
+ EXYNOS5420_GPIO_B45,
+ EXYNOS5420_GPIO_B46,
+ EXYNOS5420_GPIO_B47,
+ EXYNOS5420_GPIO_H00, /* 64 0x40 */
+ EXYNOS5420_GPIO_H01,
+ EXYNOS5420_GPIO_H02,
+ EXYNOS5420_GPIO_H03,
+ EXYNOS5420_GPIO_H04,
+ EXYNOS5420_GPIO_H05,
+ EXYNOS5420_GPIO_H06,
+ EXYNOS5420_GPIO_H07,
+
+ /* GPIO PART 2 STARTS*/
+ EXYNOS5420_GPIO_MAX_PORT_PART_1,/* 72 0x48 */
+ EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1,
+ EXYNOS5420_GPIO_Y71,
+ EXYNOS5420_GPIO_Y72,
+ EXYNOS5420_GPIO_Y73,
+ EXYNOS5420_GPIO_Y74,
+ EXYNOS5420_GPIO_Y75,
+ EXYNOS5420_GPIO_Y76,
+ EXYNOS5420_GPIO_Y77,
+
+ /* GPIO PART 3 STARTS*/
+ EXYNOS5420_GPIO_MAX_PORT_PART_2,/* 80 0x50 */
+ EXYNOS5420_GPIO_X00 = EXYNOS5420_GPIO_MAX_PORT_PART_2,
+ EXYNOS5420_GPIO_X01,
+ EXYNOS5420_GPIO_X02,
+ EXYNOS5420_GPIO_X03,
+ EXYNOS5420_GPIO_X04,
+ EXYNOS5420_GPIO_X05,
+ EXYNOS5420_GPIO_X06,
+ EXYNOS5420_GPIO_X07,
+ EXYNOS5420_GPIO_X10, /* 88 0x58 */
+ EXYNOS5420_GPIO_X11,
+ EXYNOS5420_GPIO_X12,
+ EXYNOS5420_GPIO_X13,
+ EXYNOS5420_GPIO_X14,
+ EXYNOS5420_GPIO_X15,
+ EXYNOS5420_GPIO_X16,
+ EXYNOS5420_GPIO_X17,
+ EXYNOS5420_GPIO_X20, /* 96 0x60 */
+ EXYNOS5420_GPIO_X21,
+ EXYNOS5420_GPIO_X22,
+ EXYNOS5420_GPIO_X23,
+ EXYNOS5420_GPIO_X24,
+ EXYNOS5420_GPIO_X25,
+ EXYNOS5420_GPIO_X26,
+ EXYNOS5420_GPIO_X27,
+ EXYNOS5420_GPIO_X30, /* 104 0x68 */
+ EXYNOS5420_GPIO_X31,
+ EXYNOS5420_GPIO_X32,
+ EXYNOS5420_GPIO_X33,
+ EXYNOS5420_GPIO_X34,
+ EXYNOS5420_GPIO_X35,
+ EXYNOS5420_GPIO_X36,
+ EXYNOS5420_GPIO_X37,
+
+ /* GPIO PART 4 STARTS*/
+ EXYNOS5420_GPIO_MAX_PORT_PART_3,/* 112 0x70 */
+ EXYNOS5420_GPIO_C00 = EXYNOS5420_GPIO_MAX_PORT_PART_3,
+ EXYNOS5420_GPIO_C01,
+ EXYNOS5420_GPIO_C02,
+ EXYNOS5420_GPIO_C03,
+ EXYNOS5420_GPIO_C04,
+ EXYNOS5420_GPIO_C05,
+ EXYNOS5420_GPIO_C06,
+ EXYNOS5420_GPIO_C07,
+ EXYNOS5420_GPIO_C10, /* 120 0x78 */
+ EXYNOS5420_GPIO_C11,
+ EXYNOS5420_GPIO_C12,
+ EXYNOS5420_GPIO_C13,
+ EXYNOS5420_GPIO_C14,
+ EXYNOS5420_GPIO_C15,
+ EXYNOS5420_GPIO_C16,
+ EXYNOS5420_GPIO_C17,
+ EXYNOS5420_GPIO_C20, /* 128 0x80 */
+ EXYNOS5420_GPIO_C21,
+ EXYNOS5420_GPIO_C22,
+ EXYNOS5420_GPIO_C23,
+ EXYNOS5420_GPIO_C24,
+ EXYNOS5420_GPIO_C25,
+ EXYNOS5420_GPIO_C26,
+ EXYNOS5420_GPIO_C27,
+ EXYNOS5420_GPIO_C30, /* 136 0x88 */
+ EXYNOS5420_GPIO_C31,
+ EXYNOS5420_GPIO_C32,
+ EXYNOS5420_GPIO_C33,
+ EXYNOS5420_GPIO_C34,
+ EXYNOS5420_GPIO_C35,
+ EXYNOS5420_GPIO_C36,
+ EXYNOS5420_GPIO_C37,
+ EXYNOS5420_GPIO_C40, /* 144 0x90 */
+ EXYNOS5420_GPIO_C41,
+ EXYNOS5420_GPIO_C42,
+ EXYNOS5420_GPIO_C43,
+ EXYNOS5420_GPIO_C44,
+ EXYNOS5420_GPIO_C45,
+ EXYNOS5420_GPIO_C46,
+ EXYNOS5420_GPIO_C47,
+ EXYNOS5420_GPIO_D10, /* 152 0x98 */
+ EXYNOS5420_GPIO_D11,
+ EXYNOS5420_GPIO_D12,
+ EXYNOS5420_GPIO_D13,
+ EXYNOS5420_GPIO_D14,
+ EXYNOS5420_GPIO_D15,
+ EXYNOS5420_GPIO_D16,
+ EXYNOS5420_GPIO_D17,
+ EXYNOS5420_GPIO_Y00, /* 160 0xa0 */
+ EXYNOS5420_GPIO_Y01,
+ EXYNOS5420_GPIO_Y02,
+ EXYNOS5420_GPIO_Y03,
+ EXYNOS5420_GPIO_Y04,
+ EXYNOS5420_GPIO_Y05,
+ EXYNOS5420_GPIO_Y06,
+ EXYNOS5420_GPIO_Y07,
+ EXYNOS5420_GPIO_Y10, /* 168 0xa8 */
+ EXYNOS5420_GPIO_Y11,
+ EXYNOS5420_GPIO_Y12,
+ EXYNOS5420_GPIO_Y13,
+ EXYNOS5420_GPIO_Y14,
+ EXYNOS5420_GPIO_Y15,
+ EXYNOS5420_GPIO_Y16,
+ EXYNOS5420_GPIO_Y17,
+ EXYNOS5420_GPIO_Y20, /* 176 0xb0 */
+ EXYNOS5420_GPIO_Y21,
+ EXYNOS5420_GPIO_Y22,
+ EXYNOS5420_GPIO_Y23,
+ EXYNOS5420_GPIO_Y24,
+ EXYNOS5420_GPIO_Y25,
+ EXYNOS5420_GPIO_Y26,
+ EXYNOS5420_GPIO_Y27,
+ EXYNOS5420_GPIO_Y30, /* 184 0xb8 */
+ EXYNOS5420_GPIO_Y31,
+ EXYNOS5420_GPIO_Y32,
+ EXYNOS5420_GPIO_Y33,
+ EXYNOS5420_GPIO_Y34,
+ EXYNOS5420_GPIO_Y35,
+ EXYNOS5420_GPIO_Y36,
+ EXYNOS5420_GPIO_Y37,
+ EXYNOS5420_GPIO_Y40, /* 192 0xc0 */
+ EXYNOS5420_GPIO_Y41,
+ EXYNOS5420_GPIO_Y42,
+ EXYNOS5420_GPIO_Y43,
+ EXYNOS5420_GPIO_Y44,
+ EXYNOS5420_GPIO_Y45,
+ EXYNOS5420_GPIO_Y46,
+ EXYNOS5420_GPIO_Y47,
+ EXYNOS5420_GPIO_Y50, /* 200 0xc8 */
+ EXYNOS5420_GPIO_Y51,
+ EXYNOS5420_GPIO_Y52,
+ EXYNOS5420_GPIO_Y53,
+ EXYNOS5420_GPIO_Y54,
+ EXYNOS5420_GPIO_Y55,
+ EXYNOS5420_GPIO_Y56,
+ EXYNOS5420_GPIO_Y57,
+ EXYNOS5420_GPIO_Y60, /* 208 0xd0 */
+ EXYNOS5420_GPIO_Y61,
+ EXYNOS5420_GPIO_Y62,
+ EXYNOS5420_GPIO_Y63,
+ EXYNOS5420_GPIO_Y64,
+ EXYNOS5420_GPIO_Y65,
+ EXYNOS5420_GPIO_Y66,
+ EXYNOS5420_GPIO_Y67,
+
+ /* GPIO_PART5_STARTS */
+ EXYNOS5420_GPIO_MAX_PORT_PART_4,/* 216 0xd8 */
+ EXYNOS5420_GPIO_E00 = EXYNOS5420_GPIO_MAX_PORT_PART_4,
+ EXYNOS5420_GPIO_E01,
+ EXYNOS5420_GPIO_E02,
+ EXYNOS5420_GPIO_E03,
+ EXYNOS5420_GPIO_E04,
+ EXYNOS5420_GPIO_E05,
+ EXYNOS5420_GPIO_E06,
+ EXYNOS5420_GPIO_E07,
+ EXYNOS5420_GPIO_E10, /* 224 0xe0 */
+ EXYNOS5420_GPIO_E11,
+ EXYNOS5420_GPIO_E12,
+ EXYNOS5420_GPIO_E13,
+ EXYNOS5420_GPIO_E14,
+ EXYNOS5420_GPIO_E15,
+ EXYNOS5420_GPIO_E16,
+ EXYNOS5420_GPIO_E17,
+ EXYNOS5420_GPIO_F00, /* 232 0xe8 */
+ EXYNOS5420_GPIO_F01,
+ EXYNOS5420_GPIO_F02,
+ EXYNOS5420_GPIO_F03,
+ EXYNOS5420_GPIO_F04,
+ EXYNOS5420_GPIO_F05,
+ EXYNOS5420_GPIO_F06,
+ EXYNOS5420_GPIO_F07,
+ EXYNOS5420_GPIO_F10, /* 240 0xf0 */
+ EXYNOS5420_GPIO_F11,
+ EXYNOS5420_GPIO_F12,
+ EXYNOS5420_GPIO_F13,
+ EXYNOS5420_GPIO_F14,
+ EXYNOS5420_GPIO_F15,
+ EXYNOS5420_GPIO_F16,
+ EXYNOS5420_GPIO_F17,
+ EXYNOS5420_GPIO_G00, /* 248 0xf8 */
+ EXYNOS5420_GPIO_G01,
+ EXYNOS5420_GPIO_G02,
+ EXYNOS5420_GPIO_G03,
+ EXYNOS5420_GPIO_G04,
+ EXYNOS5420_GPIO_G05,
+ EXYNOS5420_GPIO_G06,
+ EXYNOS5420_GPIO_G07,
+ EXYNOS5420_GPIO_G10, /* 256 0x100 */
+ EXYNOS5420_GPIO_G11,
+ EXYNOS5420_GPIO_G12,
+ EXYNOS5420_GPIO_G13,
+ EXYNOS5420_GPIO_G14,
+ EXYNOS5420_GPIO_G15,
+ EXYNOS5420_GPIO_G16,
+ EXYNOS5420_GPIO_G17,
+ EXYNOS5420_GPIO_G20, /* 264 0x108 */
+ EXYNOS5420_GPIO_G21,
+ EXYNOS5420_GPIO_G22,
+ EXYNOS5420_GPIO_G23,
+ EXYNOS5420_GPIO_G24,
+ EXYNOS5420_GPIO_G25,
+ EXYNOS5420_GPIO_G26,
+ EXYNOS5420_GPIO_G27,
+ EXYNOS5420_GPIO_J40, /* 272 0x110 */
+ EXYNOS5420_GPIO_J41,
+ EXYNOS5420_GPIO_J42,
+ EXYNOS5420_GPIO_J43,
+ EXYNOS5420_GPIO_J44,
+ EXYNOS5420_GPIO_J45,
+ EXYNOS5420_GPIO_J46,
+ EXYNOS5420_GPIO_J47,
+
+ /* GPIO_PART6_STARTS */
+ EXYNOS5420_GPIO_MAX_PORT_PART_5,/* 280 0x118 */
+ EXYNOS5420_GPIO_Z0 = EXYNOS5420_GPIO_MAX_PORT_PART_5,
+ EXYNOS5420_GPIO_Z1,
+ EXYNOS5420_GPIO_Z2,
+ EXYNOS5420_GPIO_Z3,
+ EXYNOS5420_GPIO_Z4,
+ EXYNOS5420_GPIO_Z5,
+ EXYNOS5420_GPIO_Z6,
+ EXYNOS5420_GPIO_MAX_PORT
+};
+
+struct gpio_info {
+ unsigned int reg_addr; /* Address of register for this part */
+ unsigned int max_gpio; /* Maximum GPIO in this part */
+};
+
+#define EXYNOS4_GPIO_NUM_PARTS 4
+static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = {
+ { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
+ { EXYNOS4_GPIO_PART2_0, EXYNOS4_GPIO_MAX_PORT_PART_2_0 },
+ { EXYNOS4_GPIO_PART2_1, EXYNOS4_GPIO_MAX_PORT_PART_2_1 },
+ { EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT },
+};
+
+#define EXYNOS4X12_GPIO_NUM_PARTS 8
+static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = {
+ { EXYNOS4X12_GPIO_PART1_0, EXYNOS4X12_GPIO_MAX_PORT_PART_1_0 },
+ { EXYNOS4X12_GPIO_PART1_1, EXYNOS4X12_GPIO_MAX_PORT_PART_1_1 },
+ { EXYNOS4X12_GPIO_PART1_2, EXYNOS4X12_GPIO_MAX_PORT_PART_1_2 },
+ { EXYNOS4X12_GPIO_PART2_1, EXYNOS4X12_GPIO_MAX_PORT_PART_2_1 },
+ { EXYNOS4X12_GPIO_PART2_2, EXYNOS4X12_GPIO_MAX_PORT_PART_2_2 },
+ { EXYNOS4X12_GPIO_PART2_3, EXYNOS4X12_GPIO_MAX_PORT_PART_2_3 },
+ { EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 },
+ { EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT },
+};
+
+#define EXYNOS5_GPIO_NUM_PARTS 8
+static struct gpio_info exynos5_gpio_data[EXYNOS5_GPIO_NUM_PARTS] = {
+ { EXYNOS5_GPIO_PART1_BASE, EXYNOS5_GPIO_MAX_PORT_PART_1 },
+ { EXYNOS5_GPIO_PART2_BASE, EXYNOS5_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS5_GPIO_PART3_BASE, EXYNOS5_GPIO_MAX_PORT_PART_3 },
+ { EXYNOS5_GPIO_PART4_BASE, EXYNOS5_GPIO_MAX_PORT_PART_4 },
+ { EXYNOS5_GPIO_PART5_BASE, EXYNOS5_GPIO_MAX_PORT_PART_5 },
+ { EXYNOS5_GPIO_PART6_BASE, EXYNOS5_GPIO_MAX_PORT_PART_6 },
+ { EXYNOS5_GPIO_PART7_BASE, EXYNOS5_GPIO_MAX_PORT_PART_7 },
+ { EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT },
+};
+
+#define EXYNOS5420_GPIO_NUM_PARTS 6
+static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = {
+ { EXYNOS5420_GPIO_PART1_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_1 },
+ { EXYNOS5420_GPIO_PART2_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS5420_GPIO_PART3_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_3 },
+ { EXYNOS5420_GPIO_PART4_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_4 },
+ { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_5 },
+ { EXYNOS5420_GPIO_PART6_BASE, EXYNOS5420_GPIO_MAX_PORT },
+};
+
+static inline struct gpio_info *get_gpio_data(void)
+{
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ return exynos5420_gpio_data;
+ else
+ return exynos5_gpio_data;
+ } else if (cpu_is_exynos4()) {
+ if (proid_is_exynos4412())
+ return exynos4x12_gpio_data;
+ else
+ return exynos4_gpio_data;
+ }
+
+ return NULL;
+}
+
+static inline unsigned int get_bank_num(void)
+{
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ return EXYNOS5420_GPIO_NUM_PARTS;
+ else
+ return EXYNOS5_GPIO_NUM_PARTS;
+ } else if (cpu_is_exynos4()) {
+ if (proid_is_exynos4412())
+ return EXYNOS4X12_GPIO_NUM_PARTS;
+ else
+ return EXYNOS4_GPIO_NUM_PARTS;
+ }
+
+ return 0;
+}
+
+/*
+ * This structure helps mapping symbolic GPIO names into indices from
+ * exynos5_gpio_pin/exynos5420_gpio_pin enums.
+ *
+ * By convention, symbolic GPIO name is defined as follows:
+ *
+ * g[p]<bank><set><bit>, where
+ * p is optional
+ * <bank> - a single character bank name, as defined by the SOC
+ * <set> - a single digit set number
+ * <bit> - bit number within the set (in 0..7 range).
+ *
+ * <set><bit> essentially form an octal number of the GPIO pin within the bank
+ * space. On the 5420 architecture some banks' sets do not start not from zero
+ * ('d' starts from 1 and 'j' starts from 4). To compensate for that and
+ * maintain flat number space withoout holes, those banks use offsets to be
+ * deducted from the pin number.
+ */
+struct gpio_name_num_table {
+ char bank; /* bank name symbol */
+ unsigned int bank_size; /* total number of pins in the bank */
+ char bank_offset; /* offset of the first bank's pin */
+ unsigned int base; /* index of the first bank's pin in the enum */
+};
+
+#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base }
+static const struct gpio_name_num_table exynos4_gpio_table[] = {
+ GPIO_ENTRY('a', EXYNOS4_GPIO_A00, EXYNOS4_GPIO_B0, 0),
+ GPIO_ENTRY('b', EXYNOS4_GPIO_B0, EXYNOS4_GPIO_C00, 0),
+ GPIO_ENTRY('c', EXYNOS4_GPIO_C00, EXYNOS4_GPIO_D00, 0),
+ GPIO_ENTRY('d', EXYNOS4_GPIO_D00, EXYNOS4_GPIO_E00, 0),
+ GPIO_ENTRY('e', EXYNOS4_GPIO_E00, EXYNOS4_GPIO_F00, 0),
+ GPIO_ENTRY('f', EXYNOS4_GPIO_F00, EXYNOS4_GPIO_J00, 0),
+ GPIO_ENTRY('j', EXYNOS4_GPIO_J00, EXYNOS4_GPIO_K00, 0),
+ GPIO_ENTRY('k', EXYNOS4_GPIO_K00, EXYNOS4_GPIO_L00, 0),
+ GPIO_ENTRY('l', EXYNOS4_GPIO_L00, EXYNOS4_GPIO_Y00, 0),
+ GPIO_ENTRY('y', EXYNOS4_GPIO_Y00, EXYNOS4_GPIO_X00, 0),
+ GPIO_ENTRY('x', EXYNOS4_GPIO_X00, EXYNOS4_GPIO_Z0, 0),
+ GPIO_ENTRY('z', EXYNOS4_GPIO_Z0, EXYNOS4_GPIO_MAX_PORT, 0),
+ { 0 }
+};
+
+static const struct gpio_name_num_table exynos4x12_gpio_table[] = {
+ GPIO_ENTRY('a', EXYNOS4X12_GPIO_A00, EXYNOS4X12_GPIO_B0, 0),
+ GPIO_ENTRY('b', EXYNOS4X12_GPIO_B0, EXYNOS4X12_GPIO_C00, 0),
+ GPIO_ENTRY('c', EXYNOS4X12_GPIO_C00, EXYNOS4X12_GPIO_D00, 0),
+ GPIO_ENTRY('d', EXYNOS4X12_GPIO_D00, EXYNOS4X12_GPIO_F00, 0),
+ GPIO_ENTRY('f', EXYNOS4X12_GPIO_F00, EXYNOS4X12_GPIO_J00, 0),
+ GPIO_ENTRY('j', EXYNOS4X12_GPIO_J00, EXYNOS4X12_GPIO_K00, 0),
+ GPIO_ENTRY('k', EXYNOS4X12_GPIO_K00, EXYNOS4X12_GPIO_L00, 0),
+ GPIO_ENTRY('l', EXYNOS4X12_GPIO_L00, EXYNOS4X12_GPIO_Y00, 0),
+ GPIO_ENTRY('y', EXYNOS4X12_GPIO_Y00, EXYNOS4X12_GPIO_M00, 0),
+ GPIO_ENTRY('m', EXYNOS4X12_GPIO_M00, EXYNOS4X12_GPIO_X00, 0),
+ GPIO_ENTRY('x', EXYNOS4X12_GPIO_X00, EXYNOS4X12_GPIO_Z0, 0),
+ GPIO_ENTRY('z', EXYNOS4X12_GPIO_Z0, EXYNOS4X12_GPIO_V00, 0),
+ GPIO_ENTRY('v', EXYNOS4X12_GPIO_V00, EXYNOS4X12_GPIO_MAX_PORT, 0),
+ { 0 }
+};
+
+static const struct gpio_name_num_table exynos5_gpio_table[] = {
+ GPIO_ENTRY('a', EXYNOS5_GPIO_A00, EXYNOS5_GPIO_B00, 0),
+ GPIO_ENTRY('b', EXYNOS5_GPIO_B00, EXYNOS5_GPIO_C00, 0),
+ GPIO_ENTRY('c', EXYNOS5_GPIO_C00, EXYNOS5_GPIO_D00, 0),
+ GPIO_ENTRY('d', EXYNOS5_GPIO_D00, EXYNOS5_GPIO_Y00, 0),
+ GPIO_ENTRY('y', EXYNOS5_GPIO_Y00, EXYNOS5_GPIO_C40, 0),
+ GPIO_ENTRY('x', EXYNOS5_GPIO_X00, EXYNOS5_GPIO_E00, 0),
+ GPIO_ENTRY('e', EXYNOS5_GPIO_E00, EXYNOS5_GPIO_F00, 0),
+ GPIO_ENTRY('f', EXYNOS5_GPIO_F00, EXYNOS5_GPIO_G00, 0),
+ GPIO_ENTRY('g', EXYNOS5_GPIO_G00, EXYNOS5_GPIO_H00, 0),
+ GPIO_ENTRY('h', EXYNOS5_GPIO_H00, EXYNOS5_GPIO_V00, 0),
+ GPIO_ENTRY('v', EXYNOS5_GPIO_V00, EXYNOS5_GPIO_Z0, 0),
+ GPIO_ENTRY('z', EXYNOS5_GPIO_Z0, EXYNOS5_GPIO_MAX_PORT, 0),
+ { 0 }
+};
+
+static const struct gpio_name_num_table exynos5420_gpio_table[] = {
+ GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0),
+ GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0),
+ GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Y70, 0),
+ GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0),
+ GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0),
+ GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 010),
+ GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0),
+ GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0),
+ GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0),
+ GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0),
+ GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_Z0, 040),
+ GPIO_ENTRY('z', EXYNOS5420_GPIO_Z0, EXYNOS5420_GPIO_MAX_PORT, 0),
+ { 0 }
+};
+
+void gpio_cfg_pin(int gpio, int cfg);
+void gpio_set_pull(int gpio, int mode);
+void gpio_set_drv(int gpio, int mode);
+void gpio_set_rate(int gpio, int mode);
+int s5p_gpio_get_pin(unsigned gpio);
+#endif
+
+/* Pin configurations */
+#define S5P_GPIO_INPUT 0x0
+#define S5P_GPIO_OUTPUT 0x1
+#define S5P_GPIO_IRQ 0xf
+#define S5P_GPIO_FUNC(x) (x)
+
+/* Pull mode */
+#define S5P_GPIO_PULL_NONE 0x0
+#define S5P_GPIO_PULL_DOWN 0x1
+#define S5P_GPIO_PULL_UP 0x3
+
+/* Drive Strength level */
+#define S5P_GPIO_DRV_1X 0x0
+#define S5P_GPIO_DRV_3X 0x1
+#define S5P_GPIO_DRV_2X 0x2
+#define S5P_GPIO_DRV_4X 0x3
+#define S5P_GPIO_DRV_FAST 0x0
+#define S5P_GPIO_DRV_SLOW 0x1
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar <rcsekar@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __I2S_REGS_H__
+#define __I2S_REGS_H__
+
+#define CON_RESET (1 << 31)
+#define CON_TXFIFO_FULL (1 << 8)
+#define CON_TXCH_PAUSE (1 << 4)
+#define CON_ACTIVE (1 << 0)
+
+#define MOD_OP_CLK (3 << 30)
+#define MOD_BLCP_SHIFT 24
+#define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT)
+
+#define MOD_BLC_16BIT (0 << 13)
+#define MOD_BLC_8BIT (1 << 13)
+#define MOD_BLC_24BIT (2 << 13)
+#define MOD_BLC_MASK (3 << 13)
+
+#define MOD_SLAVE (1 << 11)
+#define MOD_RCLKSRC (0 << 10)
+#define MOD_MASK (3 << 8)
+#define MOD_LR_LLOW (0 << 7)
+#define MOD_LR_RLOW (1 << 7)
+#define MOD_SDF_IIS (0 << 5)
+#define MOD_SDF_MSB (1 << 5)
+#define MOD_SDF_LSB (2 << 5)
+#define MOD_SDF_MASK (3 << 5)
+#define MOD_RCLK_256FS (0 << 3)
+#define MOD_RCLK_512FS (1 << 3)
+#define MOD_RCLK_384FS (2 << 3)
+#define MOD_RCLK_768FS (3 << 3)
+#define MOD_RCLK_MASK (3 << 3)
+#define MOD_BCLK_32FS (0 << 1)
+#define MOD_BCLK_48FS (1 << 1)
+#define MOD_BCLK_16FS (2 << 1)
+#define MOD_BCLK_24FS (3 << 1)
+#define MOD_BCLK_MASK (3 << 1)
+
+#define MOD_CDCLKCON (1 << 12)
+
+#define FIC_TXFLUSH (1 << 15)
+#define FIC_RXFLUSH (1 << 7)
+
+#define PSREN (1 << 15)
+#define PSVAL (3 << 8)
+
+#endif /* __I2S_REGS_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DSIM_H
+#define _DSIM_H
+
+#include <linux/list.h>
+#include <linux/fb.h>
+#include <lcd.h>
+
+#define PANEL_NAME_SIZE (32)
+
+enum mipi_dsim_interface_type {
+ DSIM_COMMAND,
+ DSIM_VIDEO
+};
+
+enum mipi_dsim_virtual_ch_no {
+ DSIM_VIRTUAL_CH_0,
+ DSIM_VIRTUAL_CH_1,
+ DSIM_VIRTUAL_CH_2,
+ DSIM_VIRTUAL_CH_3
+};
+
+enum mipi_dsim_burst_mode_type {
+ DSIM_NON_BURST_SYNC_EVENT,
+ DSIM_BURST_SYNC_EVENT,
+ DSIM_NON_BURST_SYNC_PULSE,
+ DSIM_BURST,
+ DSIM_NON_VIDEO_MODE
+};
+
+enum mipi_dsim_no_of_data_lane {
+ DSIM_DATA_LANE_1,
+ DSIM_DATA_LANE_2,
+ DSIM_DATA_LANE_3,
+ DSIM_DATA_LANE_4
+};
+
+enum mipi_dsim_byte_clk_src {
+ DSIM_PLL_OUT_DIV8,
+ DSIM_EXT_CLK_DIV8,
+ DSIM_EXT_CLK_BYPASS
+};
+
+enum mipi_dsim_pixel_format {
+ DSIM_CMD_3BPP,
+ DSIM_CMD_8BPP,
+ DSIM_CMD_12BPP,
+ DSIM_CMD_16BPP,
+ DSIM_VID_16BPP_565,
+ DSIM_VID_18BPP_666PACKED,
+ DSIM_18BPP_666LOOSELYPACKED,
+ DSIM_24BPP_888
+};
+
+/* MIPI DSI Processor-to-Peripheral transaction types */
+enum {
+ MIPI_DSI_V_SYNC_START = 0x01,
+ MIPI_DSI_V_SYNC_END = 0x11,
+ MIPI_DSI_H_SYNC_START = 0x21,
+ MIPI_DSI_H_SYNC_END = 0x31,
+
+ MIPI_DSI_COLOR_MODE_OFF = 0x02,
+ MIPI_DSI_COLOR_MODE_ON = 0x12,
+ MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
+ MIPI_DSI_TURN_ON_PERIPHERAL = 0x32,
+
+ MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03,
+ MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13,
+ MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23,
+
+ MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04,
+ MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14,
+ MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24,
+
+ MIPI_DSI_DCS_SHORT_WRITE = 0x05,
+ MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
+
+ MIPI_DSI_DCS_READ = 0x06,
+
+ MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
+
+ MIPI_DSI_END_OF_TRANSMISSION = 0x08,
+
+ MIPI_DSI_NULL_PACKET = 0x09,
+ MIPI_DSI_BLANKING_PACKET = 0x19,
+ MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
+ MIPI_DSI_DCS_LONG_WRITE = 0x39,
+
+ MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
+ MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
+ MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
+
+ MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d,
+ MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d,
+ MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d,
+
+ MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e,
+ MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e,
+ MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e,
+ MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e,
+};
+
+/*
+ * struct mipi_dsim_config - interface for configuring mipi-dsi controller.
+ *
+ * @auto_flush: enable or disable Auto flush of MD FIFO using VSYNC pulse.
+ * @eot_disable: enable or disable EoT packet in HS mode.
+ * @auto_vertical_cnt: specifies auto vertical count mode.
+ * in Video mode, the vertical line transition uses line counter
+ * configured by VSA, VBP, and Vertical resolution.
+ * If this bit is set to '1', the line counter does not use VSA and VBP
+ * registers.(in command mode, this variable is ignored)
+ * @hse: set horizontal sync event mode.
+ * In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC
+ * start packet to MIPI DSI slave at MIPI DSI spec1.1r02.
+ * this bit transfers HSYNC end packet in VSYNC pulse and Vporch area
+ * (in mommand mode, this variable is ignored)
+ * @hfp: specifies HFP disable mode.
+ * if this variable is set, DSI master ignores HFP area in VIDEO mode.
+ * (in command mode, this variable is ignored)
+ * @hbp: specifies HBP disable mode.
+ * if this variable is set, DSI master ignores HBP area in VIDEO mode.
+ * (in command mode, this variable is ignored)
+ * @hsa: specifies HSA disable mode.
+ * if this variable is set, DSI master ignores HSA area in VIDEO mode.
+ * (in command mode, this variable is ignored)
+ * @e_interface: specifies interface to be used.(CPU or RGB interface)
+ * @e_virtual_ch: specifies virtual channel number that main or
+ * sub diaplsy uses.
+ * @e_pixel_format: specifies pixel stream format for main or sub display.
+ * @e_burst_mode: selects Burst mode in Video mode.
+ * in Non-burst mode, RGB data area is filled with RGB data and NULL
+ * packets, according to input bandwidth of RGB interface.
+ * In Burst mode, RGB data area is filled with RGB data only.
+ * @e_no_data_lane: specifies data lane count to be used by Master.
+ * @e_byte_clk: select byte clock source. (it must be DSIM_PLL_OUT_DIV8)
+ * DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported.
+ * @pll_stable_time: specifies the PLL Timer for stability of the ganerated
+ * clock(System clock cycle base)
+ * if the timer value goes to 0x00000000, the clock stable bit of status
+ * and interrupt register is set.
+ * @esc_clk: specifies escape clock frequency for getting the escape clock
+ * prescaler value.
+ * @stop_holding_cnt: specifies the interval value between transmitting
+ * read packet(or write "set_tear_on" command) and BTA request.
+ * after transmitting read packet or write "set_tear_on" command,
+ * BTA requests to D-PHY automatically. this counter value specifies
+ * the interval between them.
+ * @bta_timeout: specifies the timer for BTA.
+ * this register specifies time out from BTA request to change
+ * the direction with respect to Tx escape clock.
+ * @rx_timeout: specifies the timer for LP Rx mode timeout.
+ * this register specifies time out on how long RxValid deasserts,
+ * after RxLpdt asserts with respect to Tx escape clock.
+ * - RxValid specifies Rx data valid indicator.
+ * - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode.
+ * - RxValid and RxLpdt specifies signal from D-PHY.
+ */
+struct mipi_dsim_config {
+ unsigned char auto_flush;
+ unsigned char eot_disable;
+
+ unsigned char auto_vertical_cnt;
+ unsigned char hse;
+ unsigned char hfp;
+ unsigned char hbp;
+ unsigned char hsa;
+
+ enum mipi_dsim_interface_type e_interface;
+ enum mipi_dsim_virtual_ch_no e_virtual_ch;
+ enum mipi_dsim_pixel_format e_pixel_format;
+ enum mipi_dsim_burst_mode_type e_burst_mode;
+ enum mipi_dsim_no_of_data_lane e_no_data_lane;
+ enum mipi_dsim_byte_clk_src e_byte_clk;
+
+ /*
+ * ===========================================
+ * | P | M | S | MHz |
+ * -------------------------------------------
+ * | 3 | 100 | 3 | 100 |
+ * | 3 | 100 | 2 | 200 |
+ * | 3 | 63 | 1 | 252 |
+ * | 4 | 100 | 1 | 300 |
+ * | 4 | 110 | 1 | 330 |
+ * | 12 | 350 | 1 | 350 |
+ * | 3 | 100 | 1 | 400 |
+ * | 4 | 150 | 1 | 450 |
+ * | 6 | 118 | 1 | 472 |
+ * | 3 | 120 | 1 | 480 |
+ * | 12 | 250 | 0 | 500 |
+ * | 4 | 100 | 0 | 600 |
+ * | 3 | 81 | 0 | 648 |
+ * | 3 | 88 | 0 | 704 |
+ * | 3 | 90 | 0 | 720 |
+ * | 3 | 100 | 0 | 800 |
+ * | 12 | 425 | 0 | 850 |
+ * | 4 | 150 | 0 | 900 |
+ * | 12 | 475 | 0 | 950 |
+ * | 6 | 250 | 0 | 1000 |
+ * -------------------------------------------
+ */
+
+ /*
+ * pms could be calculated as the following.
+ * M * 24 / P * 2 ^ S = MHz
+ */
+ unsigned char p;
+ unsigned short m;
+ unsigned char s;
+
+ unsigned int pll_stable_time;
+ unsigned long esc_clk;
+
+ unsigned short stop_holding_cnt;
+ unsigned char bta_timeout;
+ unsigned short rx_timeout;
+};
+
+/*
+ * struct mipi_dsim_device - global interface for mipi-dsi driver.
+ *
+ * @dsim_config: infomation for configuring mipi-dsi controller.
+ * @master_ops: callbacks to mipi-dsi operations.
+ * @dsim_lcd_dev: pointer to activated ddi device.
+ * (it would be registered by mipi-dsi driver.)
+ * @dsim_lcd_drv: pointer to activated_ddi driver.
+ * (it would be registered by mipi-dsi driver.)
+ * @state: specifies status of MIPI-DSI controller.
+ * the status could be RESET, INIT, STOP, HSCLKEN and ULPS.
+ * @data_lane: specifiec enabled data lane number.
+ * this variable would be set by driver according to e_no_data_lane
+ * automatically.
+ * @e_clk_src: select byte clock source.
+ * @pd: pointer to MIPI-DSI driver platform data.
+ */
+struct mipi_dsim_device {
+ struct mipi_dsim_config *dsim_config;
+ struct mipi_dsim_master_ops *master_ops;
+ struct mipi_dsim_lcd_device *dsim_lcd_dev;
+ struct mipi_dsim_lcd_driver *dsim_lcd_drv;
+
+ unsigned int state;
+ unsigned int data_lane;
+ enum mipi_dsim_byte_clk_src e_clk_src;
+
+ struct exynos_platform_mipi_dsim *pd;
+};
+
+/*
+ * struct exynos_platform_mipi_dsim - interface to platform data
+ * for mipi-dsi driver.
+ *
+ * @lcd_panel_name: specifies lcd panel name registered to mipi-dsi driver.
+ * lcd panel driver searched would be actived.
+ * @dsim_config: pointer of structure for configuring mipi-dsi controller.
+ * @lcd_panel_info: pointer for lcd panel specific structure.
+ * this structure specifies width, height, timing and polarity and so on.
+ * @lcd_power: callback pointer for enabling or disabling lcd power.
+ * @mipi_power: callback pointer for enabling or disabling mipi power.
+ * @phy_enable: pointer to a callback controlling D-PHY enable/reset
+ */
+struct exynos_platform_mipi_dsim {
+ char lcd_panel_name[PANEL_NAME_SIZE];
+
+ struct mipi_dsim_config *dsim_config;
+ void *lcd_panel_info;
+
+ int (*lcd_power)(void);
+ int (*mipi_power)(void);
+ void (*phy_enable)(unsigned int dev_index, unsigned int enable);
+};
+
+/*
+ * struct mipi_dsim_master_ops - callbacks to mipi-dsi operations.
+ *
+ * @cmd_write: transfer command to lcd panel at LP mode.
+ * @cmd_read: read command from rx register.
+ * @get_dsim_frame_done: get the status that all screen data have been
+ * transferred to mipi-dsi.
+ * @clear_dsim_frame_done: clear frame done status.
+ * @get_fb_frame_done: get frame done status of display controller.
+ * @trigger: trigger display controller.
+ * - this one would be used only in case of CPU mode.
+ */
+struct mipi_dsim_master_ops {
+ int (*cmd_write)(struct mipi_dsim_device *dsim, unsigned int data_id,
+ const unsigned char *data0, unsigned int data1);
+ int (*cmd_read)(struct mipi_dsim_device *dsim, unsigned int data_id,
+ unsigned int data0, unsigned int data1);
+ int (*get_dsim_frame_done)(struct mipi_dsim_device *dsim);
+ int (*clear_dsim_frame_done)(struct mipi_dsim_device *dsim);
+
+ int (*get_fb_frame_done)(void);
+ void (*trigger)(struct fb_info *info);
+};
+
+/*
+ * device structure for mipi-dsi based lcd panel.
+ *
+ * @name: name of the device to use with this device, or an
+ * alias for that name.
+ * @id: id of device to be registered.
+ * @bus_id: bus id for identifing connected bus
+ * and this bus id should be same as id of mipi_dsim_device.
+ * @master: pointer to mipi-dsi master device object.
+ * @platform_data: lcd panel specific platform data.
+ */
+struct mipi_dsim_lcd_device {
+ char *name;
+ int id;
+ int bus_id;
+ int reverse_panel;
+
+ struct mipi_dsim_device *master;
+ void *platform_data;
+};
+
+/*
+ * driver structure for mipi-dsi based lcd panel.
+ *
+ * this structure should be registered by lcd panel driver.
+ * mipi-dsi driver seeks lcd panel registered through name field
+ * and calls these callback functions in appropriate time.
+ *
+ * @name: name of the driver to use with this device, or an
+ * alias for that name.
+ * @id: id of driver to be registered.
+ * this id would be used for finding device object registered.
+ * @mipi_panel_init: callback pointer for initializing lcd panel based on mipi
+ * dsi interface.
+ * @mipi_display_on: callback pointer for lcd panel display on.
+ */
+struct mipi_dsim_lcd_driver {
+ char *name;
+ int id;
+
+ int (*mipi_panel_init)(struct mipi_dsim_device *dsim_dev);
+ void (*mipi_display_on)(struct mipi_dsim_device *dsim_dev);
+};
+
+#ifdef CONFIG_EXYNOS_MIPI_DSIM
+int exynos_mipi_dsi_init(void);
+#else
+static inline int exynos_mipi_dsi_init(void)
+{
+ return 0;
+}
+#endif
+
+/*
+ * register mipi_dsim_lcd_driver object defined by lcd panel driver
+ * to mipi-dsi driver.
+ */
+int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver
+ *lcd_drv);
+
+/*
+ * register mipi_dsim_lcd_device to mipi-dsi master.
+ */
+int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device
+ *lcd_dev);
+
+void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd);
+void exynos_init_dsim_platform_data(vidinfo_t *vid);
+
+/* panel driver init based on mipi dsi interface */
+void s6e8ax0_init(void);
+
+#ifdef CONFIG_OF_CONTROL
+extern int mipi_power(void);
+#endif
+#endif /* _DSIM_H */
--- /dev/null
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MMC_H_
+#define __ASM_ARCH_MMC_H_
+
+#define S5P_MMC_DEV_OFFSET 0x10000
+
+#define SDHCI_CONTROL2 0x80
+#define SDHCI_CONTROL3 0x84
+#define SDHCI_CONTROL4 0x8C
+
+#define SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31)
+#define SDHCI_CTRL2_ENCMDCNFMSK (1 << 30)
+#define SDHCI_CTRL2_CDINVRXD3 (1 << 29)
+#define SDHCI_CTRL2_SLCARDOUT (1 << 28)
+
+#define SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
+#define SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
+#define SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
+
+#define SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
+#define SDHCI_CTRL2_LVLDAT_SHIFT (16)
+#define SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
+
+#define SDHCI_CTRL2_ENFBCLKTX (1 << 15)
+#define SDHCI_CTRL2_ENFBCLKRX (1 << 14)
+#define SDHCI_CTRL2_SDCDSEL (1 << 13)
+#define SDHCI_CTRL2_SDSIGPC (1 << 12)
+#define SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11)
+
+#define SDHCI_CTRL2_DFCNT_MASK(_x) ((_x) << 9)
+#define SDHCI_CTRL2_DFCNT_SHIFT (9)
+
+#define SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8)
+#define SDHCI_CTRL2_RWAITMODE (1 << 7)
+#define SDHCI_CTRL2_DISBUFRD (1 << 6)
+#define SDHCI_CTRL2_SELBASECLK_MASK(_x) ((_x) << 4)
+#define SDHCI_CTRL2_SELBASECLK_SHIFT (4)
+#define SDHCI_CTRL2_PWRSYNC (1 << 3)
+#define SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1)
+#define SDHCI_CTRL2_HWINITFIN (1 << 0)
+
+#define SDHCI_CTRL3_FCSEL3 (1 << 31)
+#define SDHCI_CTRL3_FCSEL2 (1 << 23)
+#define SDHCI_CTRL3_FCSEL1 (1 << 15)
+#define SDHCI_CTRL3_FCSEL0 (1 << 7)
+
+#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16)
+#define SDHCI_CTRL4_DRIVE_SHIFT (16)
+
+#define SDHCI_MAX_HOSTS 4
+
+int s5p_sdhci_init(u32 regbase, int index, int bus_width);
+
+static inline int s5p_mmc_init(int index, int bus_width)
+{
+ unsigned int base = samsung_get_base_mmc() +
+ (S5P_MMC_DEV_OFFSET * index);
+
+ return s5p_sdhci_init(base, index, bus_width);
+}
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_mmc_init(const void *blob);
+#endif
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PERIPH_H
+#define __ASM_ARM_ARCH_PERIPH_H
+
+/*
+ * Peripherals required for pinmux configuration. List will
+ * grow with support for more devices getting added.
+ * Numbering based on interrupt table.
+ *
+ */
+enum periph_id {
+ PERIPH_ID_UART0 = 51,
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+ PERIPH_ID_UART3,
+ PERIPH_ID_I2C0 = 56,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_I2C4,
+ PERIPH_ID_I2C5,
+ PERIPH_ID_I2C6,
+ PERIPH_ID_I2C7,
+ PERIPH_ID_SPI0 = 68,
+ PERIPH_ID_SPI1,
+ PERIPH_ID_SPI2,
+ PERIPH_ID_SDMMC0 = 75,
+ PERIPH_ID_SDMMC1,
+ PERIPH_ID_SDMMC2,
+ PERIPH_ID_SDMMC3,
+ PERIPH_ID_I2C8 = 87,
+ PERIPH_ID_I2C9,
+ PERIPH_ID_I2S0 = 98,
+ PERIPH_ID_I2S1 = 99,
+
+ /* Since following peripherals do
+ * not have shared peripheral interrupts (SPIs)
+ * they are numbered arbitiraly after the maximum
+ * SPIs Exynos has (128)
+ */
+ PERIPH_ID_SROMC = 128,
+ PERIPH_ID_SPI3,
+ PERIPH_ID_SPI4,
+ PERIPH_ID_SDMMC4,
+ PERIPH_ID_PWM0,
+ PERIPH_ID_PWM1,
+ PERIPH_ID_PWM2,
+ PERIPH_ID_PWM3,
+ PERIPH_ID_PWM4,
+ PERIPH_ID_DPHPD,
+ PERIPH_ID_I2C10 = 203,
+
+ PERIPH_ID_NONE = -1,
+};
+
+#endif /* __ASM_ARM_ARCH_PERIPH_H */
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Abhilash Kesavan <a.kesavan@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PINMUX_H
+#define __ASM_ARM_ARCH_PINMUX_H
+
+#include "periph.h"
+
+/*
+ * Flags for setting specific configarations of peripherals.
+ * List will grow with support for more devices getting added.
+ */
+enum {
+ PINMUX_FLAG_NONE = 0x00000000,
+
+ /* Flags for eMMC */
+ PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */
+
+ /* Flags for SROM controller */
+ PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */
+ PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
+
+ /* Flags for I2C */
+ PINMUX_FLAG_HS_MODE = 1 << 1, /* I2C High Speed Mode */
+};
+
+/**
+ * Configures the pinmux for a particular peripheral.
+ *
+ * Each gpio can be configured in many different ways (4 bits on exynos)
+ * such as "input", "output", "special function", "external interrupt"
+ * etc. This function will configure the peripheral pinmux along with
+ * pull-up/down and drive strength.
+ *
+ * @param peripheral peripheral to be configured
+ * @param flags configure flags
+ * @return 0 if ok, -1 on error (e.g. unsupported peripheral)
+ */
+int exynos_pinmux_config(int peripheral, int flags);
+
+/**
+ * Decode the peripheral id using the interrpt numbers.
+ *
+ * @param blob Device tree blob
+ * @param node FDT I2C node to find
+ * @return peripheral id if ok, PERIPH_ID_NONE on error
+ */
+int pinmux_decode_periph_id(const void *blob, int node);
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_POWER_H_
+#define __ASM_ARM_ARCH_POWER_H_
+
+#ifndef __ASSEMBLY__
+struct exynos4_power {
+ unsigned int om_stat;
+ unsigned char res1[0x8];
+ unsigned int rtc_clko_sel;
+ unsigned int gnss_rtc_out_ctrl;
+ unsigned char res2[0x1ec];
+ unsigned int system_power_down_ctrl;
+ unsigned int res3;
+ unsigned int system_power_down_option;
+ unsigned char res4[0x1f4];
+ unsigned int swreset;
+ unsigned int rst_stat;
+ unsigned char res5[0x1f8];
+ unsigned int wakeup_stat;
+ unsigned int eint_wakeup_mask;
+ unsigned int wakeup_mask;
+ unsigned char res6[0xf4];
+ unsigned int hdmi_phy_control;
+ unsigned int usbdevice_phy_control;
+ unsigned int usbhost_phy_control;
+ unsigned int dac_phy_control;
+ unsigned int mipi_phy0_control;
+ unsigned int mipi_phy1_control;
+ unsigned int adc_phy_control;
+ unsigned int pcie_phy_control;
+ unsigned int sata_phy_control;
+ unsigned char res7[0xdc];
+ unsigned int inform0;
+ unsigned int inform1;
+ unsigned int inform2;
+ unsigned int inform3;
+ unsigned int inform4;
+ unsigned int inform5;
+ unsigned int inform6;
+ unsigned int inform7;
+ unsigned char res8[0x1e0];
+ unsigned int pmu_debug;
+ unsigned char res9[0x5fc];
+ unsigned int arm_core0_sys_pwr_reg;
+ unsigned char res10[0xc];
+ unsigned int arm_core1_sys_pwr_reg;
+ unsigned char res11[0x6c];
+ unsigned int arm_common_sys_pwr_reg;
+ unsigned char res12[0x3c];
+ unsigned int arm_cpu_l2_0_sys_pwr_reg;
+ unsigned int arm_cpu_l2_1_sys_pwr_reg;
+ unsigned char res13[0x38];
+ unsigned int cmu_aclkstop_sys_pwr_reg;
+ unsigned int cmu_sclkstop_sys_pwr_reg;
+ unsigned char res14[0x4];
+ unsigned int cmu_reset_sys_pwr_reg;
+ unsigned char res15[0x10];
+ unsigned int apll_sysclk_sys_pwr_reg;
+ unsigned int mpll_sysclk_sys_pwr_reg;
+ unsigned int vpll_sysclk_sys_pwr_reg;
+ unsigned int epll_sysclk_sys_pwr_reg;
+ unsigned char res16[0x8];
+ unsigned int cmu_clkstop_gps_alive_sys_pwr_reg;
+ unsigned int cmu_reset_gps_alive_sys_pwr_reg;
+ unsigned int cmu_clkstop_cam_sys_pwr_reg;
+ unsigned int cmu_clkstop_tv_sys_pwr_reg;
+ unsigned int cmu_clkstop_mfc_sys_pwr_reg;
+ unsigned int cmu_clkstop_g3d_sys_pwr_reg;
+ unsigned int cmu_clkstop_lcd0_sys_pwr_reg;
+ unsigned int cmu_clkstop_lcd1_sys_pwr_reg;
+ unsigned int cmu_clkstop_maudio_sys_pwr_reg;
+ unsigned int cmu_clkstop_gps_sys_pwr_reg;
+ unsigned int cmu_reset_cam_sys_pwr_reg;
+ unsigned int cmu_reset_tv_sys_pwr_reg;
+ unsigned int cmu_reset_mfc_sys_pwr_reg;
+ unsigned int cmu_reset_g3d_sys_pwr_reg;
+ unsigned int cmu_reset_lcd0_sys_pwr_reg;
+ unsigned int cmu_reset_lcd1_sys_pwr_reg;
+ unsigned int cmu_reset_maudio_sys_pwr_reg;
+ unsigned int cmu_reset_gps_sys_pwr_reg;
+ unsigned int top_bus_sys_pwr_reg;
+ unsigned int top_retention_sys_pwr_reg;
+ unsigned int top_pwr_sys_pwr_reg;
+ unsigned char res17[0x1c];
+ unsigned int logic_reset_sys_pwr_reg;
+ unsigned char res18[0x14];
+ unsigned int onenandxl_mem_sys_pwr_reg;
+ unsigned int modemif_mem_sys_pwr_reg;
+ unsigned char res19[0x4];
+ unsigned int usbdevice_mem_sys_pwr_reg;
+ unsigned int sdmmc_mem_sys_pwr_reg;
+ unsigned int cssys_mem_sys_pwr_reg;
+ unsigned int secss_mem_sys_pwr_reg;
+ unsigned char res20[0x4];
+ unsigned int pcie_mem_sys_pwr_reg;
+ unsigned int sata_mem_sys_pwr_reg;
+ unsigned char res21[0x18];
+ unsigned int pad_retention_dram_sys_pwr_reg;
+ unsigned int pad_retention_maudio_sys_pwr_reg;
+ unsigned char res22[0x18];
+ unsigned int pad_retention_gpio_sys_pwr_reg;
+ unsigned int pad_retention_uart_sys_pwr_reg;
+ unsigned int pad_retention_mmca_sys_pwr_reg;
+ unsigned int pad_retention_mmcb_sys_pwr_reg;
+ unsigned int pad_retention_ebia_sys_pwr_reg;
+ unsigned int pad_retention_ebib_sys_pwr_reg;
+ unsigned char res23[0x8];
+ unsigned int pad_isolation_sys_pwr_reg;
+ unsigned char res24[0x1c];
+ unsigned int pad_alv_sel_sys_pwr_reg;
+ unsigned char res25[0x1c];
+ unsigned int xusbxti_sys_pwr_reg;
+ unsigned int xxti_sys_pwr_reg;
+ unsigned char res26[0x38];
+ unsigned int ext_regulator_sys_pwr_reg;
+ unsigned char res27[0x3c];
+ unsigned int gpio_mode_sys_pwr_reg;
+ unsigned char res28[0x3c];
+ unsigned int gpio_mode_maudio_sys_pwr_reg;
+ unsigned char res29[0x3c];
+ unsigned int cam_sys_pwr_reg;
+ unsigned int tv_sys_pwr_reg;
+ unsigned int mfc_sys_pwr_reg;
+ unsigned int g3d_sys_pwr_reg;
+ unsigned int lcd0_sys_pwr_reg;
+ unsigned int lcd1_sys_pwr_reg;
+ unsigned int maudio_sys_pwr_reg;
+ unsigned int gps_sys_pwr_reg;
+ unsigned int gps_alive_sys_pwr_reg;
+ unsigned char res30[0xc5c];
+ unsigned int arm_core0_configuration;
+ unsigned int arm_core0_status;
+ unsigned int arm_core0_option;
+ unsigned char res31[0x74];
+ unsigned int arm_core1_configuration;
+ unsigned int arm_core1_status;
+ unsigned int arm_core1_option;
+ unsigned char res32[0x37c];
+ unsigned int arm_common_option;
+ unsigned char res33[0x1f4];
+ unsigned int arm_cpu_l2_0_configuration;
+ unsigned int arm_cpu_l2_0_status;
+ unsigned char res34[0x18];
+ unsigned int arm_cpu_l2_1_configuration;
+ unsigned int arm_cpu_l2_1_status;
+ unsigned char res35[0xa00];
+ unsigned int pad_retention_maudio_option;
+ unsigned char res36[0xdc];
+ unsigned int pad_retention_gpio_option;
+ unsigned char res37[0x1c];
+ unsigned int pad_retention_uart_option;
+ unsigned char res38[0x1c];
+ unsigned int pad_retention_mmca_option;
+ unsigned char res39[0x1c];
+ unsigned int pad_retention_mmcb_option;
+ unsigned char res40[0x1c];
+ unsigned int pad_retention_ebia_option;
+ unsigned char res41[0x1c];
+ unsigned int pad_retention_ebib_option;
+ unsigned char res42[0x160];
+ unsigned int ps_hold_control;
+ unsigned char res43[0xf0];
+ unsigned int xusbxti_configuration;
+ unsigned int xusbxti_status;
+ unsigned char res44[0x14];
+ unsigned int xusbxti_duration;
+ unsigned int xxti_configuration;
+ unsigned int xxti_status;
+ unsigned char res45[0x14];
+ unsigned int xxti_duration;
+ unsigned char res46[0x1dc];
+ unsigned int ext_regulator_duration;
+ unsigned char res47[0x5e0];
+ unsigned int cam_configuration;
+ unsigned int cam_status;
+ unsigned int cam_option;
+ unsigned char res48[0x14];
+ unsigned int tv_configuration;
+ unsigned int tv_status;
+ unsigned int tv_option;
+ unsigned char res49[0x14];
+ unsigned int mfc_configuration;
+ unsigned int mfc_status;
+ unsigned int mfc_option;
+ unsigned char res50[0x14];
+ unsigned int g3d_configuration;
+ unsigned int g3d_status;
+ unsigned int g3d_option;
+ unsigned char res51[0x14];
+ unsigned int lcd0_configuration;
+ unsigned int lcd0_status;
+ unsigned int lcd0_option;
+ unsigned char res52[0x14];
+ unsigned int lcd1_configuration;
+ unsigned int lcd1_status;
+ unsigned int lcd1_option;
+ unsigned char res53[0x34];
+ unsigned int gps_configuration;
+ unsigned int gps_status;
+ unsigned int gps_option;
+ unsigned char res54[0x14];
+ unsigned int gps_alive_configuration;
+ unsigned int gps_alive_status;
+ unsigned int gps_alive_option;
+};
+
+struct exynos4412_power {
+ unsigned char res1[0x0704];
+ unsigned int usbhost_phy_control;
+ unsigned int hsic1_phy_control;
+ unsigned int hsic2_phy_control;
+};
+
+struct exynos5_power {
+ unsigned int om_stat;
+ unsigned char res1[0x18];
+ unsigned int rtc_clko_sel;
+ unsigned int gnss_rtc_out_ctrl;
+ unsigned char res2[0x1dc];
+ unsigned int central_seq_configuration;
+ unsigned int central_seq_status;
+ unsigned int central_seq_option;
+ unsigned char res3[0x14];
+ unsigned int seq_transition0;
+ unsigned int seq_transition1;
+ unsigned int seq_transition2;
+ unsigned int seq_transition3;
+ unsigned int seq_transition4;
+ unsigned int seq_transition5;
+ unsigned int seq_transition6;
+ unsigned int seq_transition7;
+ unsigned int central_seq_dmc_configuration;
+ unsigned int central_seq_dmc_status;
+ unsigned int central_seq_dmc_option;
+ unsigned char res4[0x14];
+ unsigned int seq_dmc_transition0;
+ unsigned int seq_dmc_transition1;
+ unsigned int seq_dmc_transition2;
+ unsigned int seq_dmc_transition3;
+ unsigned int seq_dmc_transition4;
+ unsigned int seq_dmc_transition5;
+ unsigned int seq_dmc_transition6;
+ unsigned int seq_dmc_transition7;
+ unsigned char res5[0x180];
+ unsigned int swreset;
+ unsigned int rst_stat;
+ unsigned int automatic_wdt_reset_disable;
+ unsigned int mask_wdt_reset_request;
+ unsigned int mask_wreset_request;
+ unsigned char res6[0xec];
+ unsigned int reset_sequencer_configuration;
+ unsigned int reset_sequencer_status;
+ unsigned int reset_sequencer_option;
+ unsigned char res7[0xf4];
+ unsigned int wakeup_stat;
+ unsigned int eint_wakeup_mask;
+ unsigned int wakeup_mask;
+ unsigned int wakeup_interrupt;
+ unsigned char res8[0x10];
+ unsigned int wakeup_stat_dmc;
+ unsigned int eint_wakeup_mask_dmc;
+ unsigned int wakeup_mask_dmc;
+ unsigned int wakeup_interrupt_dmc;
+ unsigned char res9[0xd0];
+ unsigned int hdmi_phy_control;
+ unsigned int usbdrd_phy_control;
+ unsigned int usbhost_phy_control;
+ unsigned int efnand_phy_control;
+ unsigned int mipi_phy0_control;
+ unsigned int mipi_phy1_control;
+ unsigned int adc_phy_control;
+ unsigned int mtcadc_phy_control;
+ unsigned int dptx_phy_control;
+ unsigned int sata_phy_control;
+ unsigned char res10[0xd8];
+ unsigned int inform0;
+ unsigned int inform1;
+ unsigned int inform2;
+ unsigned int inform3;
+ unsigned int sysip_dat0;
+ unsigned int sysip_dat1;
+ unsigned int sysip_dat2;
+ unsigned int sysip_dat3;
+ unsigned char res11[0xe0];
+ unsigned int pmu_spare0;
+ unsigned int pmu_spare1;
+ unsigned int pmu_spare2;
+ unsigned int pmu_spare3;
+ unsigned char res12[0x70];
+ unsigned int irom_data_reg0;
+ unsigned int irom_data_reg1;
+ unsigned int irom_data_reg2;
+ unsigned int irom_data_reg3;
+ unsigned char res13[0x70];
+ unsigned int pmu_debug;
+ unsigned char res14[0x5fc];
+ unsigned int arm_core0_sys_pwr_reg;
+ unsigned int dis_irq_arm_core0_local_sys_pwr_reg;
+ unsigned int dis_irq_arm_core0_central_sys_pwr_reg;
+ unsigned char res15[0x4];
+ unsigned int arm_core1_sys_pwr_reg;
+ unsigned int dis_irq_arm_core1_local_sys_pwr_reg;
+ unsigned int dis_irq_arm_core1_central_sys_pwr_reg;
+ unsigned char res16[0x24];
+ unsigned int fsys_arm_sys_pwr_reg;
+ unsigned int dis_irq_fsys_arm_local_sys_pwr_reg;
+ unsigned int dis_irq_fsys_arm_central_sys_pwr_reg;
+ unsigned char res17[0x4];
+ unsigned int isp_arm_sys_pwr_reg;
+ unsigned int dis_irq_isp_arm_local_sys_pwr_reg;
+ unsigned int dis_irq_isp_arm_central_sys_pwr_reg;
+ unsigned char res18[0x24];
+ unsigned int arm_common_sys_pwr_reg;
+ unsigned char res19[0x3c];
+ unsigned int arm_l2_sys_pwr_reg;
+ unsigned char res20[0x3c];
+ unsigned int cmu_aclkstop_sys_pwr_reg;
+ unsigned int cmu_sclkstop_sys_pwr_reg;
+ unsigned char res21[0x4];
+ unsigned int cmu_reset_sys_pwr_reg;
+ unsigned char res22[0x10];
+ unsigned int cmu_aclkstop_dmc_sys_pwr_reg;
+ unsigned int cmu_sclkstop_dmc_sys_pwr_reg;
+ unsigned char res23[0x4];
+ unsigned int cmu_reset_dmc_sys_pwr_reg;
+ unsigned char res24[0x8];
+ unsigned int ddrphy_dlllock_sys_pwr_reg;
+ unsigned char res25[0x4];
+ unsigned int apll_sysclk_sys_pwr_reg;
+ unsigned int mpll_sysclk_sys_pwr_reg;
+ unsigned int vpll_sysclk_sys_pwr_reg;
+ unsigned int epll_sysclk_sys_pwr_reg;
+ unsigned int bpll_sysclk_sys_pwr_reg;
+ unsigned int cpll_sysclk_sys_pwr_reg;
+ unsigned int gpll_sysclk_sys_pwr_reg;
+ unsigned char res26[0x8];
+ unsigned int mplluser_sysclk_sys_pwr_reg;
+ unsigned char res27[0x8];
+ unsigned int bplluser_sysclk_sys_pwr_reg;
+ unsigned char res28[0xc];
+ unsigned int top_bus_sys_pwr_reg;
+ unsigned int top_retention_sys_pwr_reg;
+ unsigned int top_pwr_sys_pwr_reg;
+ unsigned char res29[0x4];
+ unsigned int top_bus_dmc_sys_pwr_reg;
+ unsigned int top_retention_dmc_sys_pwr_reg;
+ unsigned int top_pwr_dmc_sys_pwr_reg;
+ unsigned char res30[0x4];
+ unsigned int logic_reset_sys_pwr_reg;
+ unsigned int oscclk_gate_sys_pwr_reg;
+ unsigned char res31[0x8];
+ unsigned int logic_reset_dmc_sys_pwr_reg;
+ unsigned int oscclk_gate_dmc_sys_pwr_reg;
+ unsigned char res32[0x8];
+ unsigned int usbotg_mem_sys_pwr_reg;
+ unsigned char res33[0x4];
+ unsigned int g2d_mem_sys_pwr_reg;
+ unsigned int usbdrd_mem_sys_pwr_reg;
+ unsigned int efnand_mem_sys_pwr_reg;
+ unsigned int cssys_mem_sys_pwr_reg;
+ unsigned int secss_mem_sys_pwr_reg;
+ unsigned int rotator_mem_sys_pwr_reg;
+ unsigned int intram_mem_sys_pwr_reg;
+ unsigned int introm_mem_sys_pwr_reg;
+ unsigned int jpeg_mem_sys_pwr_reg;
+ unsigned int hsi_mem_sys_pwr_reg;
+ unsigned char res34[0x4];
+ unsigned int mcuiop_mem_sys_pwr_reg;
+ unsigned char res35[0x4];
+ unsigned int sata_mem_sys_pwr_reg;
+ unsigned int pad_retention_dram_sys_pwr_reg;
+ unsigned int pad_retention_mau_sys_pwr_reg;
+ unsigned int pad_retention_jtag_sys_pwr_reg;
+ unsigned char res36[0xc];
+ unsigned int pad_retention_mmc2_sys_pwr_reg;
+ unsigned int pad_retention_mmc3_sys_pwr_reg;
+ unsigned int pad_retention_gpio_sys_pwr_reg;
+ unsigned int pad_retention_uart_sys_pwr_reg;
+ unsigned int pad_retention_mmc0_sys_pwr_reg;
+ unsigned int pad_retention_mmc1_sys_pwr_reg;
+ unsigned int pad_retention_ebia_sys_pwr_reg;
+ unsigned int pad_retention_ebib_sys_pwr_reg;
+ unsigned int pad_retention_spi_sys_pwr_reg;
+ unsigned int pad_retention_gpio_dmc_sys_pwr_reg;
+ unsigned int pad_isolation_sys_pwr_reg;
+ unsigned char res37[0xc];
+ unsigned int pad_isolation_dmc_sys_pwr_reg;
+ unsigned char res38[0xc];
+ unsigned int pad_alv_sel_sys_pwr_reg;
+ unsigned char res39[0x20];
+ unsigned int xxti_sys_pwr_reg;
+ unsigned char res40[0x38];
+ unsigned int ext_regulator_sys_pwr_reg;
+ unsigned char res41[0x3c];
+ unsigned int gpio_mode_sys_pwr_reg;
+ unsigned char res42[0x1c];
+ unsigned int gpio_mode_dmc_sys_pwr_reg;
+ unsigned char res43[0x1c];
+ unsigned int gpio_mode_mau_sys_pwr_reg;
+ unsigned int top_asb_reset_sys_pwr_reg;
+ unsigned int top_asb_isolation_sys_pwr_reg;
+ unsigned char res44[0xb4];
+ unsigned int gscl_sys_pwr_reg;
+ unsigned int isp_sys_pwr_reg;
+ unsigned int mfc_sys_pwr_reg;
+ unsigned int g3d_sys_pwr_reg;
+ unsigned char res45[0x4];
+ unsigned int disp1_sys_pwr_reg;
+ unsigned int mau_sys_pwr_reg;
+ unsigned char res46[0x64];
+ unsigned int cmu_clkstop_gscl_sys_pwr_reg;
+ unsigned int cmu_clkstop_isp_sys_pwr_reg;
+ unsigned int cmu_clkstop_mfc_sys_pwr_reg;
+ unsigned int cmu_clkstop_g3d_sys_pwr_reg;
+ unsigned char res47[0x4];
+ unsigned int cmu_clkstop_disp1_sys_pwr_reg;
+ unsigned int cmu_clkstop_mau_sys_pwr_reg;
+ unsigned char res48[0x24];
+ unsigned int cmu_sysclk_gscl_sys_pwr_reg;
+ unsigned int cmu_sysclk_isp_sys_pwr_reg;
+ unsigned int cmu_sysclk_mfc_sys_pwr_reg;
+ unsigned int cmu_sysclk_g3d_sys_pwr_reg;
+ unsigned char res49[0x4];
+ unsigned int cmu_sysclk_disp1_sys_pwr_reg;
+ unsigned int cmu_sysclk_mau_sys_pwr_reg;
+ unsigned char res50[0xa4];
+ unsigned int cmu_reset_gscl_sys_pwr_reg;
+ unsigned int cmu_reset_isp_sys_pwr_reg;
+ unsigned int cmu_reset_mfc_sys_pwr_reg;
+ unsigned int cmu_reset_g3d_sys_pwr_reg;
+ unsigned char res51[0x4];
+ unsigned int cmu_reset_disp1_sys_pwr_reg;
+ unsigned int cmu_reset_mau_sys_pwr_reg;
+ unsigned char res52[0xa64];
+ unsigned int arm_core0_configuration;
+ unsigned int arm_core0_status;
+ unsigned int arm_core0_option;
+ unsigned char res53[0x14];
+ unsigned int dis_irq_arm_core0_local_configuration;
+ unsigned int dis_irq_arm_core0_local_status;
+ unsigned int dis_irq_arm_core0_local_option;
+ unsigned char res54[0x14];
+ unsigned int dis_irq_arm_core0_central_configuration;
+ unsigned int dis_irq_arm_core0_central_status;
+ unsigned int dis_irq_arm_core0_central_option;
+ unsigned char res55[0x34];
+ unsigned int arm_core1_configuration;
+ unsigned int arm_core1_status;
+ unsigned int arm_core1_option;
+ unsigned char res56[0x14];
+ unsigned int dis_irq_arm_core1_local_configuration;
+ unsigned int dis_irq_arm_core1_local_status;
+ unsigned int dis_irq_arm_core1_local_option;
+ unsigned char res57[0x14];
+ unsigned int dis_irq_arm_core1_central_configuration;
+ unsigned int dis_irq_arm_core1_central_status;
+ unsigned int dis_irq_arm_core1_central_option;
+ unsigned char res58[0x134];
+ unsigned int fsys_arm_configuration;
+ unsigned int fsys_arm_status;
+ unsigned int fsys_arm_option;
+ unsigned char res59[0x14];
+ unsigned int dis_irq_fsys_arm_local_configuration;
+ unsigned int dis_irq_fsys_arm_local_status;
+ unsigned int dis_irq_fsys_arm_local_option;
+ unsigned char res60[0x14];
+ unsigned int dis_irq_fsys_arm_central_configuration;
+ unsigned int dis_irq_fsys_arm_central_status;
+ unsigned int dis_irq_fsys_arm_central_option;
+ unsigned char res61[0x34];
+ unsigned int isp_arm_configuration;
+ unsigned int isp_arm_status;
+ unsigned int isp_arm_option;
+ unsigned char res62[0x14];
+ unsigned int dis_irq_isp_arm_local_configuration;
+ unsigned int dis_irq_isp_arm_local_status;
+ unsigned int dis_irq_isp_arm_local_option;
+ unsigned char res63[0x14];
+ unsigned int dis_irq_isp_arm_central_configuration;
+ unsigned int dis_irq_isp_arm_central_status;
+ unsigned int dis_irq_isp_arm_central_option;
+ unsigned char res64[0x134];
+ unsigned int arm_common_configuration;
+ unsigned int arm_common_status;
+ unsigned int arm_common_option;
+ unsigned char res65[0x1f4];
+ unsigned int arm_l2_configuration;
+ unsigned int arm_l2_status;
+ unsigned int arm_l2_option;
+ unsigned char res66[0x1f4];
+ unsigned int cmu_aclkstop_configuration;
+ unsigned int cmu_aclkstop_status;
+ unsigned int cmu_aclkstop_option;
+ unsigned char res67[0x14];
+ unsigned int cmu_sclkstop_configuration;
+ unsigned int cmu_sclkstop_status;
+ unsigned int cmu_sclkstop_option;
+ unsigned char res68[0x34];
+ unsigned int cmu_reset_configuration;
+ unsigned int cmu_reset_status;
+ unsigned int cmu_reset_option;
+ unsigned char res69[0x94];
+ unsigned int cmu_aclkstop_dmc_configuration;
+ unsigned int cmu_aclkstop_dmc_status;
+ unsigned int cmu_aclkstop_dmc_option;
+ unsigned char res70[0x14];
+ unsigned int cmu_sclkstop_dmc_configuration;
+ unsigned int cmu_sclkstop_dmc_status;
+ unsigned int cmu_sclkstop_dmc_option;
+ unsigned char res71[0x34];
+ unsigned int cmu_reset_dmc_configuration;
+ unsigned int cmu_reset_dmc_status;
+ unsigned int cmu_reset_dmc_option;
+ unsigned char res72[0x54];
+ unsigned int ddrphy_dlllock_configuration;
+ unsigned int ddrphy_dlllock_status;
+ unsigned int ddrphy_dlllock_option;
+ unsigned char res73[0x34];
+ unsigned int apll_sysclk_configuration;
+ unsigned int apll_sysclk_status;
+ unsigned int apll_sysclk_option;
+ unsigned char res74[0x18];
+ unsigned int mpll_sysclk_status;
+ unsigned int mpll_sysclk_option;
+ unsigned char res75[0x14];
+ unsigned int vpll_sysclk_configuration;
+ unsigned int vpll_sysclk_status;
+ unsigned int vpll_sysclk_option;
+ unsigned char res76[0x14];
+ unsigned int epll_sysclk_configuration;
+ unsigned int epll_sysclk_status;
+ unsigned int epll_sysclk_option;
+ unsigned char res77[0x14];
+ unsigned int bpll_sysclk_configuration;
+ unsigned int bpll_sysclk_status;
+ unsigned int bpll_sysclk_option;
+ unsigned char res78[0x14];
+ unsigned int cpll_sysclk_configuration;
+ unsigned int cpll_sysclk_status;
+ unsigned int cpll_sysclk_option;
+ unsigned char res79[0x14];
+ unsigned int gpll_sysclk_configuration;
+ unsigned int gpll_sysclk_status;
+ unsigned int gpll_sysclk_option;
+ unsigned char res80[0x54];
+ unsigned int mplluser_sysclk_configuration;
+ unsigned int mplluser_sysclk_status;
+ unsigned int mplluser_sysclk_option;
+ unsigned char res81[0x54];
+ unsigned int bplluser_sysclk_configuration;
+ unsigned int bplluser_sysclk_status;
+ unsigned int bplluser_sysclk_option;
+ unsigned char res82[0x74];
+ unsigned int top_bus_configuration;
+ unsigned int top_bus_status;
+ unsigned int top_bus_option;
+ unsigned char res83[0x14];
+ unsigned int top_retention_configuration;
+ unsigned int top_retention_status;
+ unsigned int top_retention_option;
+ unsigned char res84[0x14];
+ unsigned int top_pwr_configuration;
+ unsigned int top_pwr_status;
+ unsigned int top_pwr_option;
+ unsigned char res85[0x34];
+ unsigned int top_bus_dmc_configuration;
+ unsigned int top_bus_dmc_status;
+ unsigned int top_bus_dmc_option;
+ unsigned char res86[0x14];
+ unsigned int top_retention_dmc_configuration;
+ unsigned int top_retention_dmc_status;
+ unsigned int top_retention_dmc_option;
+ unsigned char res87[0x14];
+ unsigned int top_pwr_dmc_configuration;
+ unsigned int top_pwr_dmc_status;
+ unsigned int top_pwr_dmc_option;
+ unsigned char res88[0x34];
+ unsigned int logic_reset_configuration;
+ unsigned int logic_reset_status;
+ unsigned int logic_reset_option;
+ unsigned char res89[0x14];
+ unsigned int oscclk_gate_configuration;
+ unsigned int oscclk_gate_status;
+ unsigned int oscclk_gate_option;
+ unsigned char res90[0x54];
+ unsigned int logic_reset_dmc_configuration;
+ unsigned int logic_reset_dmc_status;
+ unsigned int logic_reset_dmc_option;
+ unsigned char res91[0x14];
+ unsigned int oscclk_gate_dmc_configuration;
+ unsigned int oscclk_gate_dmc_status;
+ unsigned int oscclk_gate_dmc_option;
+ unsigned char res92[0x54];
+ unsigned int usbotg_mem_configuration;
+ unsigned int usbotg_mem_status;
+ unsigned int usbotg_mem_option;
+ unsigned char res93[0x34];
+ unsigned int g2d_mem_configuration;
+ unsigned int g2d_mem_status;
+ unsigned int g2d_mem_option;
+ unsigned char res94[0x14];
+ unsigned int usbdrd_mem_configuration;
+ unsigned int usbdrd_mem_status;
+ unsigned int usbdrd_mem_option;
+ unsigned char res95[0x14];
+ unsigned int efnand_mem_configuration;
+ unsigned int efnand_mem_status;
+ unsigned int efnand_mem_option;
+ unsigned char res96[0x14];
+ unsigned int cssys_mem_configuration;
+ unsigned int cssys_mem_status;
+ unsigned int cssys_mem_option;
+ unsigned char res97[0x14];
+ unsigned int secss_mem_configuration;
+ unsigned int secss_mem_status;
+ unsigned int secss_mem_option;
+ unsigned char res98[0x14];
+ unsigned int rotator_mem_configuration;
+ unsigned int rotator_mem_status;
+ unsigned int rotator_mem_option;
+ unsigned char res99[0x14];
+ unsigned int intram_mem_configuration;
+ unsigned int intram_mem_status;
+ unsigned int intram_mem_option;
+ unsigned char res100[0x14];
+ unsigned int introm_mem_configuration;
+ unsigned int introm_mem_status;
+ unsigned int introm_mem_option;
+ unsigned char res101[0x14];
+ unsigned int jpeg_mem_configuration;
+ unsigned int jpeg_mem_status;
+ unsigned int jpeg_mem_option;
+ unsigned char res102[0x14];
+ unsigned int hsi_mem_configuration;
+ unsigned int hsi_mem_status;
+ unsigned int hsi_mem_option;
+ unsigned char res103[0x34];
+ unsigned int mcuiop_mem_configuration;
+ unsigned int mcuiop_mem_status;
+ unsigned int mcuiop_mem_option;
+ unsigned char res104[0x14];
+ unsigned int sata_mem_configuration;
+ unsigned int sata_mem_status;
+ unsigned int sata_mem_option;
+ unsigned char res105[0x34];
+ unsigned int pad_retention_dram_configuration;
+ unsigned int pad_retention_dram_status;
+ unsigned int pad_retention_dram_option;
+ unsigned char res106[0x14];
+ unsigned int pad_retention_mau_configuration;
+ unsigned int pad_retention_mau_status;
+ unsigned int pad_retention_mau_option;
+ unsigned char res107[0x14];
+ unsigned int pad_retention_jtag_configuration;
+ unsigned int pad_retention_jtag_status;
+ unsigned int pad_retention_jtag_option;
+ unsigned char res108[0x74];
+ unsigned int pad_retention_mmc2_configuration;
+ unsigned int pad_retention_mmc2_status;
+ unsigned int pad_retention_mmc2_option;
+ unsigned char res109[0x14];
+ unsigned int pad_retention_mmc3_configuration;
+ unsigned int pad_retention_mmc3_status;
+ unsigned int pad_retention_mmc3_option;
+ unsigned char res110[0x14];
+ unsigned int pad_retention_gpio_configuration;
+ unsigned int pad_retention_gpio_status;
+ unsigned int pad_retention_gpio_option;
+ unsigned char res111[0x14];
+ unsigned int pad_retention_uart_configuration;
+ unsigned int pad_retention_uart_status;
+ unsigned int pad_retention_uart_option;
+ unsigned char res112[0x14];
+ unsigned int pad_retention_mmc0_configuration;
+ unsigned int pad_retention_mmc0_status;
+ unsigned int pad_retention_mmc0_option;
+ unsigned char res113[0x14];
+ unsigned int pad_retention_mmc1_configuration;
+ unsigned int pad_retention_mmc1_status;
+ unsigned int pad_retention_mmc1_option;
+ unsigned char res114[0x14];
+ unsigned int pad_retention_ebia_configuration;
+ unsigned int pad_retention_ebia_status;
+ unsigned int pad_retention_ebia_option;
+ unsigned char res115[0x14];
+ unsigned int pad_retention_ebib_configuration;
+ unsigned int pad_retention_ebib_status;
+ unsigned int pad_retention_ebib_option;
+ unsigned char res116[0x14];
+ unsigned int pad_retention_spi_configuration;
+ unsigned int pad_retention_spi_status;
+ unsigned int pad_retention_spi_option;
+ unsigned char res117[0x14];
+ unsigned int pad_retention_gpio_dmc_configuration;
+ unsigned int pad_retention_gpio_dmc_status;
+ unsigned int pad_retention_gpio_dmc_option;
+ unsigned char res118[0x14];
+ unsigned int pad_isolation_configuration;
+ unsigned int pad_isolation_status;
+ unsigned int pad_isolation_option;
+ unsigned char res119[0x74];
+ unsigned int pad_isolation_dmc_configuration;
+ unsigned int pad_isolation_dmc_status;
+ unsigned int pad_isolation_dmc_option;
+ unsigned char res120[0x74];
+ unsigned int pad_alv_sel_configuration;
+ unsigned int pad_alv_sel_status;
+ unsigned int pad_alv_sel_option0;
+ unsigned int ps_hold_control;
+ unsigned char res130[0x110];
+ unsigned int xxti_configuration;
+ unsigned int xxti_status;
+ unsigned int xxti_option;
+ unsigned char res131[0x10];
+ unsigned int xxti_duration3;
+ unsigned char res132[0x1c0];
+ unsigned int ext_regulator_configuration;
+ unsigned int ext_regulator_status;
+ unsigned int ext_regulator_option;
+ unsigned char res133[0x10];
+ unsigned int ext_regulator_duration3;
+ unsigned char res134[0x1e0];
+ unsigned int gpio_mode_configuration;
+ unsigned int gpio_mode_status;
+ unsigned int gpio_mode_option;
+ unsigned char res135[0xf4];
+ unsigned int gpio_mode_dmc_configuration;
+ unsigned int gpio_mode_dmc_status;
+ unsigned int gpio_mode_dmc_option;
+ unsigned char res136[0xd4];
+ unsigned int gpio_mode_mau_configuration;
+ unsigned int gpio_mode_mau_status;
+ unsigned int gpio_mode_mau_option;
+ unsigned char res137[0x14];
+ unsigned int top_asb_reset_configuration;
+ unsigned int top_asb_reset_status;
+ unsigned int top_asb_reset_option;
+ unsigned char res138[0x14];
+ unsigned int top_asb_isolation_configuration;
+ unsigned int top_asb_isolation_status;
+ unsigned int top_asb_isolation_option;
+ unsigned char res139[0x5d4];
+ unsigned int gscl_configuration;
+ unsigned int gscl_status;
+ unsigned int gscl_option;
+ unsigned char res140[0x14];
+ unsigned int isp_configuration;
+ unsigned int isp_status;
+ unsigned int isp_option;
+ unsigned char res141[0x14];
+ unsigned int mfc_configuration;
+ unsigned int mfc_status;
+ unsigned int mfc_option;
+ unsigned char res142[0x14];
+ unsigned int g3d_configuration;
+ unsigned int g3d_status;
+ unsigned int g3d_option;
+ unsigned char res143[0x34];
+ unsigned int disp1_configuration;
+ unsigned int disp1_status;
+ unsigned int disp1_option;
+ unsigned char res144[0x14];
+ unsigned int mau_configuration;
+ unsigned int mau_status;
+ unsigned int mau_option;
+ unsigned char res145[0x334];
+ unsigned int cmu_clkstop_gscl_configuration;
+ unsigned int cmu_clkstop_gscl_status;
+ unsigned int cmu_clkstop_gscl_option;
+ unsigned char res146[0x14];
+ unsigned int cmu_clkstop_isp_configuration;
+ unsigned int cmu_clkstop_isp_status;
+ unsigned int cmu_clkstop_isp_option;
+ unsigned char res147[0x14];
+ unsigned int cmu_clkstop_mfc_configuration;
+ unsigned int cmu_clkstop_mfc_status;
+ unsigned int cmu_clkstop_mfc_option;
+ unsigned char res148[0x14];
+ unsigned int cmu_clkstop_g3d_configuration;
+ unsigned int cmu_clkstop_g3d_status;
+ unsigned int cmu_clkstop_g3d_option;
+ unsigned char res149[0x34];
+ unsigned int cmu_clkstop_disp1_configuration;
+ unsigned int cmu_clkstop_disp1_status;
+ unsigned int cmu_clkstop_disp1_option;
+ unsigned char res150[0x14];
+ unsigned int cmu_clkstop_mau_configuration;
+ unsigned int cmu_clkstop_mau_status;
+ unsigned int cmu_clkstop_mau_option;
+ unsigned char res151[0x134];
+ unsigned int cmu_sysclk_gscl_configuration;
+ unsigned int cmu_sysclk_gscl_status;
+ unsigned int cmu_sysclk_gscl_option;
+ unsigned char res152[0x18];
+ unsigned int cmu_sysclk_isp_status;
+ unsigned int cmu_sysclk_isp_option;
+ unsigned char res153[0x18];
+ unsigned int cmu_sysclk_mfc_status;
+ unsigned int cmu_sysclk_mfc_option;
+ unsigned char res154[0x18];
+ unsigned int cmu_sysclk_g3d_status;
+ unsigned int cmu_sysclk_g3d_option;
+ unsigned char res155[0x38];
+ unsigned int cmu_sysclk_disp1_status;
+ unsigned int cmu_sysclk_disp1_option;
+ unsigned char res156[0x18];
+ unsigned int cmu_sysclk_mau_status;
+ unsigned int cmu_sysclk_mau_option;
+ unsigned char res157[0x534];
+ unsigned int cmu_reset_gscl_configuration;
+ unsigned int cmu_reset_gscl_status;
+ unsigned int cmu_reset_gscl_option;
+ unsigned char res158[0x14];
+ unsigned int cmu_reset_isp_configuration;
+ unsigned int cmu_reset_isp_status;
+ unsigned int cmu_reset_isp_option;
+ unsigned char res159[0x14];
+ unsigned int cmu_reset_mfc_configuration;
+ unsigned int cmu_reset_mfc_status;
+ unsigned int cmu_reset_mfc_option;
+ unsigned char res160[0x14];
+ unsigned int cmu_reset_g3d_configuration;
+ unsigned int cmu_reset_g3d_status;
+ unsigned int cmu_reset_g3d_option;
+ unsigned char res161[0x34];
+ unsigned int cmu_reset_disp1_configuration;
+ unsigned int cmu_reset_disp1_status;
+ unsigned int cmu_reset_disp1_option;
+ unsigned char res162[0x14];
+ unsigned int cmu_reset_mau_configuration;
+ unsigned int cmu_reset_mau_status;
+ unsigned int cmu_reset_mau_option;
+ unsigned char res163[0x24];
+};
+
+struct exynos5420_power {
+ unsigned int om_stat;
+ unsigned int lpi_mask0;
+ unsigned int lpi_mask1;
+ unsigned char res1[0x10];
+ unsigned int rtc_clko_sel;
+ unsigned char res2[0x1e0];
+ unsigned int central_seq_configuration;
+ unsigned int central_seq_status;
+ unsigned int central_seq_option;
+ unsigned char res3[0x14];
+ unsigned int seq_transition0;
+ unsigned int seq_transition1;
+ unsigned int seq_transition2;
+ unsigned int seq_transition3;
+ unsigned int seq_transition4;
+ unsigned int seq_transition5;
+ unsigned int seq_transition6;
+ unsigned int seq_transition7;
+ unsigned int central_seq_coreblk_configuration;
+ unsigned int central_seq_coreblk_status;
+ unsigned int central_seq_coreblk_option;
+ unsigned char res4[0x14];
+ unsigned int seq_coreblk_transition0;
+ unsigned int seq_coreblk_transition1;
+ unsigned int seq_coreblk_transition2;
+ unsigned int seq_coreblk_transition3;
+ unsigned int seq_coreblk_transition4;
+ unsigned int seq_coreblk_transition5;
+ unsigned int seq_coreblk_transition6;
+ unsigned int seq_coreblk_transition7;
+ unsigned char res5[0x180];
+ unsigned int swreset;
+ unsigned int rst_stat;
+ unsigned int automatic_wdt_reset_disable;
+ unsigned int mask_wdt_reset_request;
+ unsigned int mask_wreset_request;
+ unsigned char res6[0xec];
+ unsigned int reset_sequencer_configuration;
+ unsigned int reset_sequencer_status;
+ unsigned int reset_sequencer_option;
+ unsigned char res7[0xf4];
+ unsigned int wakeup_stat;
+ unsigned int eint_wakeup_mask;
+ unsigned int wakeup_mask;
+ unsigned int wakeup_interrupt;
+ unsigned char res8[0x10];
+ unsigned int wakeup_stat_coreblk;
+ unsigned int eint_wakeup_mask_coreblk;
+ unsigned int wakeup_mask_coreblk;
+ unsigned int wakeup_interrupt_coreblk;
+ unsigned char res9[0xd0];
+ unsigned int hdmi_phy_control;
+ unsigned int usbdev_phy_control;
+ unsigned int usbdev1_phy_control;
+ unsigned int usbhost_phy_control;
+ unsigned char res104[0x4];
+ unsigned int mipi_phy0_control;
+ unsigned int mipi_phy1_control;
+ unsigned int mipi_phy2_control;
+ unsigned int adc_phy_control;
+ unsigned int mtcadc_phy_control;
+ unsigned int dptx_phy_control;
+ unsigned char res10[0xd4];
+ unsigned int inform0;
+ unsigned int inform1;
+ unsigned int inform2;
+ unsigned int inform3;
+ unsigned int sysip_dat0;
+ unsigned int sysip_dat1;
+ unsigned int sysip_dat2;
+ unsigned int sysip_dat3;
+ unsigned char res11[0xe0];
+ unsigned int pmu_spare0;
+ unsigned int pmu_spare1; /* Store PHY0_CON4 for read leveling */
+ unsigned int pmu_spare2; /* Store PHY1_CON4 for read leveling */
+ unsigned int pmu_spare3;
+ unsigned char res12[0x4];
+ unsigned int cg_status0;
+ unsigned int cg_status1;
+ unsigned int cg_status2;
+ unsigned int cg_status3;
+ unsigned int cg_status4;
+ unsigned char res200[0x58];
+ unsigned int irom_data_reg0;
+ unsigned int irom_data_reg1;
+ unsigned int irom_data_reg2;
+ unsigned int irom_data_reg3;
+ unsigned char res13[0x70];
+ unsigned int pmu_debug;
+ unsigned char res14[0x5fc];
+ unsigned int arm_core0_sys_pwr_reg;
+ unsigned char res500[0xc];
+ unsigned int arm_core1_sys_pwr_reg;
+ unsigned char res501[0xc];
+ unsigned int arm_core2_sys_pwr_reg;
+ unsigned char res502[0xc];
+ unsigned int arm_core3_sys_pwr_reg;
+ unsigned char res503[0xc];
+ unsigned int kfc_core0_sys_pwr_reg;
+ unsigned char res504[0xc];
+ unsigned int kfc_core1_sys_pwr_reg;
+ unsigned char res505[0xc];
+ unsigned int kfc_core2_sys_pwr_reg;
+ unsigned char res506[0xc];
+ unsigned int kfc_core3_sys_pwr_reg;
+ unsigned char res507[0x1c];
+ unsigned int isp_arm_sys_pwr_reg;
+ unsigned char res18[0xc];
+ unsigned int arm_common_sys_pwr_reg;
+ unsigned char res508[0xc];
+ unsigned int kfc_common_sys_pwr_reg;
+ unsigned char res19[0xc];
+ unsigned int arm_l2_sys_pwr_reg;
+ unsigned char res509[0xc];
+ unsigned int kfc_l2_sys_pwr_reg;
+ unsigned char res20[0xc];
+ unsigned int cmu_cpu_aclkstop_sys_pwr_reg;
+ unsigned int cmu_cpu_sclkstop_sys_pwr_reg;
+ unsigned char res510[0x8];
+ unsigned int cmu_kfc_aclkstop_sys_pwr_reg;
+ unsigned char res511[0xc];
+ unsigned int cmu_aclkstop_sys_pwr_reg;
+ unsigned int cmu_sclkstop_sys_pwr_reg;
+ unsigned char res21[0x4];
+ unsigned int cmu_reset_sys_pwr_reg;
+ unsigned char res22[0x10];
+ unsigned int cmu_aclkstop_coreblk_sys_pwr_reg;
+ unsigned int cmu_sclkstop_coreblk_sys_pwr_reg;
+ unsigned char res23[0x4];
+ unsigned int cmu_reset_coreblk_sys_pwr_reg;
+ unsigned int dram_freq_down_sys_pwr_reg;
+ unsigned int ddrphy_dlloff_sys_pwr_reg;
+ unsigned int ddrphy_dlllock_sys_pwr_reg;
+ unsigned char res25[0x4];
+ unsigned int apll_sysclk_sys_pwr_reg;
+ unsigned int mpll_sysclk_sys_pwr_reg;
+ unsigned int vpll_sysclk_sys_pwr_reg;
+ unsigned int epll_sysclk_sys_pwr_reg;
+ unsigned int bpll_sysclk_sys_pwr_reg;
+ unsigned int cpll_sysclk_sys_pwr_reg;
+ unsigned int dpll_sysclk_sys_pwr_reg;
+ unsigned int ipll_sysclk_sys_pwr_reg;
+ unsigned int kpll_sysclk_sys_pwr_reg;
+ unsigned int mplluser_sysclk_sys_pwr_reg;
+ unsigned char res512[0x8];
+ unsigned int bplluser_sysclk_sys_pwr_reg;
+ unsigned int rpll_sysclk_sys_pwr_reg;
+ unsigned int spll_sysclk_sys_pwr_reg;
+ unsigned char res26[0x4];
+ unsigned int top_bus_sys_pwr_reg;
+ unsigned int top_retention_sys_pwr_reg;
+ unsigned int top_pwr_sys_pwr_reg;
+ unsigned char res29[0x4];
+ unsigned int top_bus_coreblk_sys_pwr_reg;
+ unsigned int top_retention_coreblk_sys_pwr_reg;
+ unsigned int top_pwr_coreblk_sys_pwr_reg;
+ unsigned char res30[0x4];
+ unsigned int logic_reset_sys_pwr_reg;
+ unsigned int oscclk_gate_sys_pwr_reg;
+ unsigned char res31[0x8];
+ unsigned int logic_reset_coreblk_sys_pwr_reg;
+ unsigned int oscclk_gate_coreblk_sys_pwr_reg;
+ unsigned int intram_mem_sys_pwr_reg;
+ unsigned int introm_mem_sys_pwr_reg;
+ unsigned char res32[0x44];
+ unsigned int pad_retention_mau_sys_pwr_reg;
+ unsigned int pad_retention_jtag_sys_pwr_reg;
+ unsigned char res36[0x4];
+ unsigned int pad_retention_dram_sys_pwr_reg;
+ unsigned int pad_retention_uart_sys_pwr_reg;
+ unsigned int pad_retention_mmca_sys_pwr_reg;
+ unsigned int pad_retention_mmcb_sys_pwr_reg;
+ unsigned int pad_retention_mmcc_sys_pwr_reg;
+ unsigned int pad_retention_hsi_sys_pwr_reg;
+ unsigned int pad_retention_ebia_sys_pwr_reg;
+ unsigned int pad_retention_ebib_sys_pwr_reg;
+ unsigned int pad_retention_spi_sys_pwr_reg;
+ unsigned int pad_retention_dram_coreblk_sys_pwr_reg;
+ unsigned char res28[0x8];
+ unsigned int pad_isolation_sys_pwr_reg;
+ unsigned char res37[0xc];
+ unsigned int pad_isolation_coreblk_sys_pwr_reg;
+ unsigned char res38[0xc];
+ unsigned int pad_alv_sel_sys_pwr_reg;
+ unsigned char res39[0x1c];
+ unsigned int xusbxti_sys_pwr_reg;
+ unsigned int xxti_sys_pwr_reg;
+ unsigned char res40[0x38];
+ unsigned int ext_regulator_sys_pwr_reg;
+ unsigned char res41[0x3c];
+ unsigned int gpio_mode_sys_pwr_reg;
+ unsigned char res42[0x1c];
+ unsigned int gpio_mode_coreblk_sys_pwr_reg;
+ unsigned char res43[0x1c];
+ unsigned int gpio_mode_mau_sys_pwr_reg;
+ unsigned int top_asb_reset_sys_pwr_reg;
+ unsigned int top_asb_isolation_sys_pwr_reg;
+ unsigned char res44[0xb4];
+ unsigned int gscl_sys_pwr_reg;
+ unsigned int isp_sys_pwr_reg;
+ unsigned int mfc_sys_pwr_reg;
+ unsigned int g3d_sys_pwr_reg;
+ unsigned int disp1_sys_pwr_reg;
+ unsigned int mau_sys_pwr_reg;
+ unsigned int g2d_sys_pwr_reg;
+ unsigned int msc_sys_pwr_reg;
+ unsigned int fsys_sys_pwr_reg;
+ unsigned int fsys2_sys_pwr_reg;
+ unsigned int psgen_sys_pwr_reg;
+ unsigned int peric_sys_pwr_reg;
+ unsigned int wcore_sys_pwr_reg;
+ unsigned char res46[0x4c];
+ unsigned int cmu_clkstop_gscl_sys_pwr_reg;
+ unsigned int cmu_clkstop_isp_sys_pwr_reg;
+ unsigned int cmu_clkstop_mfc_sys_pwr_reg;
+ unsigned int cmu_clkstop_g3d_sys_pwr_reg;
+ unsigned int cmu_clkstop_disp1_sys_pwr_reg;
+ unsigned int cmu_clkstop_mau_sys_pwr_reg;
+ unsigned int cmu_clkstop_g2d_sys_pwr_reg;
+ unsigned int cmu_clkstop_msc_sys_pwr_reg;
+ unsigned int cmu_clkstop_fsys_sys_pwr_reg;
+ unsigned int cmu_clkstop_fsys2_sys_pwr_reg;
+ unsigned int cmu_clkstop_psgen_sys_pwr_reg;
+ unsigned int cmu_clkstop_peric_sys_pwr_reg;
+ unsigned int cmu_clkstop_wcore_sys_pwr_reg;
+ unsigned char res48[0x8];
+ unsigned int cmu_sysclk_toppwr_sys_pwr_reg;
+ unsigned int cmu_sysclk_gscl_sys_pwr_reg;
+ unsigned int cmu_sysclk_isp_sys_pwr_reg;
+ unsigned int cmu_sysclk_mfc_sys_pwr_reg;
+ unsigned int cmu_sysclk_g3d_sys_pwr_reg;
+ unsigned int cmu_sysclk_disp1_sys_pwr_reg;
+ unsigned int cmu_sysclk_mau_sys_pwr_reg;
+ unsigned int cmu_sysclk_g2d_sys_pwr_reg;
+ unsigned int cmu_sysclk_msc_sys_pwr_reg;
+ unsigned int cmu_sysclk_fsys_sys_pwr_reg;
+ unsigned int cmu_sysclk_fsys2_sys_pwr_reg;
+ unsigned int cmu_sysclk_psgen_sys_pwr_reg;
+ unsigned int cmu_sysclk_peric_sys_pwr_reg;
+ unsigned int cmu_sysclk_wcore_sys_pwr_reg;
+ unsigned int cmu_sysclk_coreblk_toppwr_sys_pwr_reg;
+ unsigned char res50[0x78];
+ unsigned int cmu_reset_fsys2_sys_pwr_reg;
+ unsigned int cmu_reset_psgen_sys_pwr_reg;
+ unsigned int cmu_reset_peric_sys_pwr_reg;
+ unsigned int cmu_reset_wcore_sys_pwr_reg;
+ unsigned int cmu_reset_gscl_sys_pwr_reg;
+ unsigned int cmu_reset_isp_sys_pwr_reg;
+ unsigned int cmu_reset_mfc_sys_pwr_reg;
+ unsigned int cmu_reset_g3d_sys_pwr_reg;
+ unsigned int cmu_reset_disp1_sys_pwr_reg;
+ unsigned int cmu_reset_mau_sys_pwr_reg;
+ unsigned int cmu_reset_g2d_sys_pwr_reg;
+ unsigned int cmu_reset_msc_sys_pwr_reg;
+ unsigned int cmu_reset_fsys_sys_pwr_reg;
+ unsigned char res52[0xa5c];
+ unsigned int arm_core0_configuration;
+ unsigned int arm_core0_status;
+ unsigned int arm_core0_option;
+ unsigned char res53[0x14];
+ unsigned int dis_irq_arm_core0_local_configuration;
+ unsigned int dis_irq_arm_core0_local_status;
+ unsigned int dis_irq_arm_core0_local_option;
+ unsigned char res54[0x14];
+ unsigned int dis_irq_arm_core0_central_configuration;
+ unsigned int dis_irq_arm_core0_central_status;
+ unsigned int dis_irq_arm_core0_central_option;
+ unsigned char res55[0x34];
+ unsigned int arm_core1_configuration;
+ unsigned int arm_core1_status;
+ unsigned int arm_core1_option;
+ unsigned char res56[0x14];
+ unsigned int dis_irq_arm_core1_local_configuration;
+ unsigned int dis_irq_arm_core1_local_status;
+ unsigned int dis_irq_arm_core1_local_option;
+ unsigned char res57[0x14];
+ unsigned int dis_irq_arm_core1_central_configuration;
+ unsigned int dis_irq_arm_core1_central_status;
+ unsigned int dis_irq_arm_core1_central_option;
+ unsigned char res600[0x34];
+ unsigned int arm_core2_configuration;
+ unsigned int arm_core2_status;
+ unsigned int arm_core2_option;
+ unsigned char res601[0x14];
+ unsigned int dis_irq_arm_core2_local_configuration;
+ unsigned int dis_irq_arm_core2_local_status;
+ unsigned int dis_irq_arm_core2_local_option;
+ unsigned char res602[0x14];
+ unsigned int dis_irq_arm_core2_central_configuration;
+ unsigned int dis_irq_arm_core2_central_status;
+ unsigned int dis_irq_arm_core2_central_option;
+ unsigned char res603[0x34];
+ unsigned int arm_core3_configuration;
+ unsigned int arm_core3_status;
+ unsigned int arm_core3_option;
+ unsigned char res900[0x14];
+ unsigned int dis_irq_arm_core3_local_configuration;
+ unsigned int dis_irq_arm_core3_local_status;
+ unsigned int dis_irq_arm_core3_local_option;
+ unsigned char res901[0x14];
+ unsigned int dis_irq_arm_core3_central_configuration;
+ unsigned int dis_irq_arm_core3_central_status;
+ unsigned int dis_irq_arm_core3_central_option;
+ unsigned char res604[0x34];
+ unsigned int kfc_core0_configuration;
+ unsigned int kfc_core0_status;
+ unsigned int kfc_core0_option;
+ unsigned char res605[0x14];
+ unsigned int dis_irq_kfc_core0_local_configuration;
+ unsigned int dis_irq_kfc_core0_local_status;
+ unsigned int dis_irq_kfc_core0_local_option;
+ unsigned char res606[0x14];
+ unsigned int dis_irq_kfc_core0_central_configuration;
+ unsigned int dis_irq_kfc_core0_central_status;
+ unsigned int dis_irq_kfc_core0_central_option;
+ unsigned char res607[0x34];
+ unsigned int kfc_core1_configuration;
+ unsigned int kfc_core1_status;
+ unsigned int kfc_core1_option;
+ unsigned char res608[0x14];
+ unsigned int dis_irq_kfc_core1_local_configuration;
+ unsigned int dis_irq_kfc_core1_local_status;
+ unsigned int dis_irq_kfc_core1_local_option;
+ unsigned char res609[0x14];
+ unsigned int dis_irq_kfc_core1_central_configuration;
+ unsigned int dis_irq_kfc_core1_central_status;
+ unsigned int dis_irq_kfc_core1_central_option;
+ unsigned char res610[0x34];
+ unsigned int kfc_core2_configuration;
+ unsigned int kfc_core2_status;
+ unsigned int kfc_core2_option;
+ unsigned char res611[0x14];
+ unsigned int dis_irq_kfc_core2_local_configuration;
+ unsigned int dis_irq_kfc_core2_local_status;
+ unsigned int dis_irq_kfc_core2_local_option;
+ unsigned char res612[0x14];
+ unsigned int dis_irq_kfc_core2_central_configuration;
+ unsigned int dis_irq_kfc_core2_central_status;
+ unsigned int dis_irq_kfc_core2_central_option;
+ unsigned char res613[0x34];
+ unsigned int kfc_core3_configuration;
+ unsigned int kfc_core3_status;
+ unsigned int kfc_core3_option;
+ unsigned char res614[0x14];
+ unsigned int dis_irq_kfc_core3_local_configuration;
+ unsigned int dis_irq_kfc_core3_local_status;
+ unsigned int dis_irq_kfc_core3_local_option;
+ unsigned char res615[0x14];
+ unsigned int dis_irq_kfc_core3_central_configuration;
+ unsigned int dis_irq_kfc_core3_central_status;
+ unsigned int dis_irq_kfc_core3_central_option;
+ unsigned char res61[0xb4];
+ unsigned int isp_arm_configuration;
+ unsigned int isp_arm_status;
+ unsigned int isp_arm_option;
+ unsigned char res62[0x14];
+ unsigned int dis_irq_isp_arm_local_configuration;
+ unsigned int dis_irq_isp_arm_local_status;
+ unsigned int dis_irq_isp_arm_local_option;
+ unsigned char res63[0x14];
+ unsigned int dis_irq_isp_arm_central_configuration;
+ unsigned int dis_irq_isp_arm_central_status;
+ unsigned int dis_irq_isp_arm_central_option;
+ unsigned char res64[0x34];
+ unsigned int arm_common_configuration;
+ unsigned int arm_common_status;
+ unsigned int arm_common_option;
+ unsigned char res616[0x74];
+ unsigned int kfc_common_configuration;
+ unsigned int kfc_common_status;
+ unsigned int kfc_common_option;
+ unsigned char res65[0x74];
+ unsigned int arm_l2_configuration;
+ unsigned int arm_l2_status;
+ unsigned int arm_l2_option;
+ unsigned char res617[0x74];
+ unsigned int kfc_l2_configuration;
+ unsigned int kfc_l2_status;
+ unsigned int kfc_l2_option;
+ unsigned char res66[0x74];
+ unsigned int cmu_cpu_aclkstop_configuration;
+ unsigned int cmu_cpu_aclkstop_status;
+ unsigned int cmu_cpu_aclkstop_option;
+ unsigned char res67[0x14];
+ unsigned int cmu_cpu_sclkstop_configuration;
+ unsigned int cmu_cpu_sclkstop_status;
+ unsigned int cmu_cpu_sclkstop_option;
+ unsigned char res618[0x4];
+ unsigned int cmu_kfc_aclkstop_configuration;
+ unsigned int cmu_kfc_aclkstop_status;
+ unsigned int cmu_kfc_aclkstop_option;
+ unsigned char res619[0xc4];
+ unsigned int cmu_aclkstop_configuration;
+ unsigned int cmu_aclkstop_status;
+ unsigned int cmu_aclkstop_option;
+ unsigned char res620[0x14];
+ unsigned int cmu_sclkstop_configuration;
+ unsigned int cmu_sclkstop_status;
+ unsigned int cmu_sclkstop_option;
+ unsigned char res68[0x34];
+ unsigned int cmu_reset_configuration;
+ unsigned int cmu_reset_status;
+ unsigned int cmu_reset_option;
+ unsigned char res69[0x94];
+ unsigned int cmu_aclkstop_coreblk_configuration;
+ unsigned int cmu_aclkstop_coreblk_status;
+ unsigned int cmu_aclkstop_coreblk_option;
+ unsigned char res70[0x14];
+ unsigned int cmu_sclkstop_coreblk_configuration;
+ unsigned int cmu_sclkstop_coreblk_status;
+ unsigned int cmu_sclkstop_coreblk_option;
+ unsigned char res71[0x34];
+ unsigned int cmu_reset_coreblk_configuration;
+ unsigned int cmu_reset_coreblk_status;
+ unsigned int cmu_reset_coreblk_option;
+ unsigned char res621[0x14];
+ unsigned int dram_freq_down_configuration;
+ unsigned int dram_freq_down_status;
+ unsigned int dram_freq_down_option;
+ unsigned char res622[0x14];
+ unsigned int ddrphy_dlloff_configuration;
+ unsigned int ddrphy_dlloff_status;
+ unsigned int ddrphy_dlloff_option;
+ unsigned char res72[0x14];
+ unsigned int ddrphy_dlllock_configuration;
+ unsigned int ddrphy_dlllock_status;
+ unsigned int ddrphy_dlllock_option;
+ unsigned char res73[0x34];
+ unsigned int apll_sysclk_configuration;
+ unsigned int apll_sysclk_status;
+ unsigned int apll_sysclk_option;
+ unsigned char res74[0x18];
+ unsigned int mpll_sysclk_status;
+ unsigned int mpll_sysclk_option;
+ unsigned char res75[0x14];
+ unsigned int vpll_sysclk_configuration;
+ unsigned int vpll_sysclk_status;
+ unsigned int vpll_sysclk_option;
+ unsigned char res76[0x14];
+ unsigned int epll_sysclk_configuration;
+ unsigned int epll_sysclk_status;
+ unsigned int epll_sysclk_option;
+ unsigned char res77[0x14];
+ unsigned int bpll_sysclk_configuration;
+ unsigned int bpll_sysclk_status;
+ unsigned int bpll_sysclk_option;
+ unsigned char res78[0x14];
+ unsigned int cpll_sysclk_configuration;
+ unsigned int cpll_sysclk_status;
+ unsigned int cpll_sysclk_option;
+ unsigned char res79[0x14];
+ unsigned int dpll_sysclk_configuration;
+ unsigned int dpll_sysclk_status;
+ unsigned int dpll_sysclk_option;
+ unsigned char res700[0x14];
+ unsigned int ipll_sysclk_configuration;
+ unsigned int ipll_sysclk_status;
+ unsigned int ipll_sysclk_option;
+ unsigned char res903[0x14];
+ unsigned int kpll_sysclk_configuration;
+ unsigned int kpll_sysclk_status;
+ unsigned int kpll_sysclk_option;
+ unsigned char res80[0x14];
+ unsigned int mplluser_sysclk_configuration;
+ unsigned int mplluser_sysclk_status;
+ unsigned int mplluser_sysclk_option;
+ unsigned char res81[0x54];
+ unsigned int bplluser_sysclk_configuration;
+ unsigned int bplluser_sysclk_status;
+ unsigned int bplluser_sysclk_option;
+ unsigned char res701[0x14];
+ unsigned int rplluser_sysclk_configuration;
+ unsigned int rplluser_sysclk_status;
+ unsigned int rplluser_sysclk_option;
+ unsigned char res702[0x14];
+ unsigned int splluser_sysclk_configuration;
+ unsigned int splluser_sysclk_status;
+ unsigned int splluser_sysclk_option;
+ unsigned char res82[0x34];
+ unsigned int top_bus_configuration;
+ unsigned int top_bus_status;
+ unsigned int top_bus_option;
+ unsigned char res83[0x14];
+ unsigned int top_retention_configuration;
+ unsigned int top_retention_status;
+ unsigned int top_retention_option;
+ unsigned char res84[0x14];
+ unsigned int top_pwr_configuration;
+ unsigned int top_pwr_status;
+ unsigned int top_pwr_option;
+ unsigned char res85[0x34];
+ unsigned int top_bus_coreblk_configuration;
+ unsigned int top_bus_coreblk_status;
+ unsigned int top_bus_coreblk_option;
+ unsigned char res86[0x14];
+ unsigned int top_retention_coreblk_configuration;
+ unsigned int top_retention_coreblk_status;
+ unsigned int top_retention_coreblk_option;
+ unsigned char res87[0x14];
+ unsigned int top_pwr_coreblk_configuration;
+ unsigned int top_pwr_coreblk_status;
+ unsigned int top_pwr_coreblk_option;
+ unsigned char res88[0x34];
+ unsigned int logic_reset_configuration;
+ unsigned int logic_reset_status;
+ unsigned int logic_reset_option;
+ unsigned char res89[0x14];
+ unsigned int oscclk_gate_configuration;
+ unsigned int oscclk_gate_status;
+ unsigned int oscclk_gate_option;
+ unsigned char res90[0x54];
+ unsigned int logic_reset_coreblk_configuration;
+ unsigned int logic_reset_coreblk_status;
+ unsigned int logic_reset_coreblk_option;
+ unsigned char res91[0x14];
+ unsigned int oscclk_gate_coreblk_configuration;
+ unsigned int oscclk_gate_coreblk_status;
+ unsigned int oscclk_gate_coreblk_option;
+ unsigned char res99[0x174];
+ unsigned int intram_mem_configuration;
+ unsigned int intram_mem_status;
+ unsigned int intram_mem_option;
+ unsigned char res100[0x14];
+ unsigned int introm_mem_configuration;
+ unsigned int introm_mem_status;
+ unsigned int introm_mem_option;
+ unsigned char res101[0xb4];
+ unsigned int pad_retention_dram_configuration;
+ unsigned int pad_retention_dram_status;
+ unsigned int pad_retention_dram_option;
+ unsigned char res106[0x14];
+ unsigned int pad_retention_mau_configuration;
+ unsigned int pad_retention_mau_status;
+ unsigned int pad_retention_mau_option;
+ unsigned char res107[0x14];
+ unsigned int pad_retention_jtag_configuration;
+ unsigned int pad_retention_jtag_status;
+ unsigned int pad_retention_jtag_option;
+ unsigned char res92[0x74];
+ unsigned int pad_retention_dram_configuration_2;
+ unsigned int pad_retention_dram_status_2;
+ unsigned int pad_retention_dram_option_2;
+ unsigned char res111[0x14];
+ unsigned int pad_retention_uart_configuration;
+ unsigned int pad_retention_uart_status;
+ unsigned int pad_retention_uart_option;
+ unsigned char res112[0x14];
+ unsigned int pad_retention_mmca_configuration;
+ unsigned int pad_retention_mmca_status;
+ unsigned int pad_retention_mmca_option;
+ unsigned char res113[0x14];
+ unsigned int pad_retention_mmcb_configuration;
+ unsigned int pad_retention_mmcb_status;
+ unsigned int pad_retention_mmcb_option;
+ unsigned char res93[0x14];
+ unsigned int pad_retention_mmcc_configuration;
+ unsigned int pad_retention_mmcc_status;
+ unsigned int pad_retention_mmcc_option;
+ unsigned char res94[0x14];
+ unsigned int pad_retention_hsi_configuration;
+ unsigned int pad_retention_hsi_status;
+ unsigned int pad_retention_hsi_option;
+ unsigned char res114[0x14];
+ unsigned int pad_retention_ebia_configuration;
+ unsigned int pad_retention_ebia_status;
+ unsigned int pad_retention_ebia_option;
+ unsigned char res115[0x14];
+ unsigned int pad_retention_ebib_configuration;
+ unsigned int pad_retention_ebib_status;
+ unsigned int pad_retention_ebib_option;
+ unsigned char res116[0x14];
+ unsigned int pad_retention_spi_configuration;
+ unsigned int pad_retention_spi_status;
+ unsigned int pad_retention_spi_option;
+ unsigned char res117[0x14];
+ unsigned int pad_retention_dram_coreblk_configuration;
+ unsigned int pad_retention_dram_coreblk_status;
+ unsigned int pad_retention_dram_coreblk_option;
+ unsigned char res118[0x14];
+ unsigned int pad_isolation_configuration;
+ unsigned int pad_isolation_status;
+ unsigned int pad_isolation_option;
+ unsigned char res119[0x74];
+ unsigned int pad_isolation_coreblk_configuration;
+ unsigned int pad_isolation_coreblk_status;
+ unsigned int pad_isolation_coreblk_option;
+ unsigned char res120[0x74];
+ unsigned int pad_alv_sel_configuration;
+ unsigned int pad_alv_sel_status;
+ unsigned int pad_alv_sel_option0;
+ unsigned int ps_hold_control;
+ unsigned char res130[0xf0];
+ unsigned int xusbxti_configuration;
+ unsigned int xusbxti_status;
+ unsigned int xusbxti_option;
+ unsigned char res910[0x10];
+ unsigned int xusbxti_duration3;
+ unsigned int xxti_configuration;
+ unsigned int xxti_status;
+ unsigned int xxti_option;
+ unsigned char res131[0x10];
+ unsigned int xxti_duration3;
+ unsigned char res132[0x1c0];
+ unsigned int ext_regulator_configuration;
+ unsigned int ext_regulator_status;
+ unsigned int ext_regulator_option;
+ unsigned char res133[0x10];
+ unsigned int ext_regulator_duration3;
+ unsigned char res134[0x1e0];
+ unsigned int gpio_mode_configuration;
+ unsigned int gpio_mode_status;
+ unsigned int gpio_mode_option;
+ unsigned char res135[0xf4];
+ unsigned int gpio_mode_coreblk_configuration;
+ unsigned int gpio_mode_coreblk_status;
+ unsigned int gpio_mode_coreblk_option;
+ unsigned char res136[0xd4];
+ unsigned int gpio_mode_mau_configuration;
+ unsigned int gpio_mode_mau_status;
+ unsigned int gpio_mode_mau_option;
+ unsigned char res137[0x14];
+ unsigned int top_asb_reset_configuration;
+ unsigned int top_asb_reset_status;
+ unsigned int top_asb_reset_option;
+ unsigned char res138[0x14];
+ unsigned int top_asb_isolation_configuration;
+ unsigned int top_asb_isolation_status;
+ unsigned int top_asb_isolation_option;
+ unsigned char res139[0x5d4];
+ unsigned int gscl_configuration;
+ unsigned int gscl_status;
+ unsigned int gscl_option;
+ unsigned char res140[0x14];
+ unsigned int isp_configuration;
+ unsigned int isp_status;
+ unsigned int isp_option;
+ unsigned char res141[0x34];
+ unsigned int mfc_configuration;
+ unsigned int mfc_status;
+ unsigned int mfc_option;
+ unsigned char res142[0x14];
+ unsigned int g3d_configuration;
+ unsigned int g3d_status;
+ unsigned int g3d_option;
+ unsigned char res143[0x34];
+ unsigned int disp1_configuration;
+ unsigned int disp1_status;
+ unsigned int disp1_option;
+ unsigned char res144[0x14];
+ unsigned int mau_configuration;
+ unsigned int mau_status;
+ unsigned int mau_option;
+ unsigned char res800[0x14];
+ unsigned int g2d_configuration;
+ unsigned int g2d_status;
+ unsigned int g2d_option;
+ unsigned char res801[0x14];
+ unsigned int msc_configuration;
+ unsigned int msc_status;
+ unsigned int msc_option;
+ unsigned char res802[0x14];
+ unsigned int fsys_configuration;
+ unsigned int fsys_status;
+ unsigned int fsys_option;
+ unsigned char res803[0x14];
+ unsigned int fsys2_configuration;
+ unsigned int fsys2_status;
+ unsigned int fsys2_option;
+ unsigned char res804[0x14];
+ unsigned int psgen_configuration;
+ unsigned int psgen_status;
+ unsigned int psgen_option;
+ unsigned char res805[0x14];
+ unsigned int peric_configuration;
+ unsigned int peric_status;
+ unsigned int peric_option;
+ unsigned char res806[0x14];
+ unsigned int wcore_configuration;
+ unsigned int wcore_status;
+ unsigned int wcore_option;
+ unsigned char res145[0x234];
+ unsigned int cmu_clkstop_gscl_configuration;
+ unsigned int cmu_clkstop_gscl_status;
+ unsigned int cmu_clkstop_gscl_option;
+ unsigned char res146[0x14];
+ unsigned int cmu_clkstop_isp_configuration;
+ unsigned int cmu_clkstop_isp_status;
+ unsigned int cmu_clkstop_isp_option;
+ unsigned char res147[0x34];
+ unsigned int cmu_clkstop_mfc_configuration;
+ unsigned int cmu_clkstop_mfc_status;
+ unsigned int cmu_clkstop_mfc_option;
+ unsigned char res148[0x14];
+ unsigned int cmu_clkstop_g3d_configuration;
+ unsigned int cmu_clkstop_g3d_status;
+ unsigned int cmu_clkstop_g3d_option;
+ unsigned char res149[0x34];
+ unsigned int cmu_clkstop_disp1_configuration;
+ unsigned int cmu_clkstop_disp1_status;
+ unsigned int cmu_clkstop_disp1_option;
+ unsigned char res150[0x14];
+ unsigned int cmu_clkstop_mau_configuration;
+ unsigned int cmu_clkstop_mau_status;
+ unsigned int cmu_clkstop_mau_option;
+ unsigned char res807[0x14];
+ unsigned int cmu_clkstop_g2d_configuration;
+ unsigned int cmu_clkstop_g2d_status;
+ unsigned int cmu_clkstop_g2d_option;
+ unsigned char res808[0x14];
+ unsigned int cmu_clkstop_msc_configuration;
+ unsigned int cmu_clkstop_msc_status;
+ unsigned int cmu_clkstop_msc_option;
+ unsigned char res809[0x14];
+ unsigned int cmu_clkstop_fsys_configuration;
+ unsigned int cmu_clkstop_fsys_status;
+ unsigned int cmu_clkstop_fsys_option;
+ unsigned char res810[0x14];
+ unsigned int cmu_clkstop_fsys2_configuration;
+ unsigned int cmu_clkstop_fsys2_status;
+ unsigned int cmu_clkstop_fsys2_option;
+ unsigned char res811[0x14];
+ unsigned int cmu_clkstop_psgen_configuration;
+ unsigned int cmu_clkstop_psgen_status;
+ unsigned int cmu_clkstop_psgen_option;
+ unsigned char res812[0x14];
+ unsigned int cmu_clkstop_peric_configuration;
+ unsigned int cmu_clkstop_peric_status;
+ unsigned int cmu_clkstop_peric_option;
+ unsigned char res813[0x14];
+ unsigned int cmu_clkstop_wcore_configuration;
+ unsigned int cmu_clkstop_wcore_status;
+ unsigned int cmu_clkstop_wcore_option;
+ unsigned char res151[0x14];
+ unsigned int cmu_sysclk_toppwr_configuration;
+ unsigned int cmu_sysclk_toppwr_status;
+ unsigned int cmu_sysclk_toppwr_option;
+ unsigned char res920[0x18];
+ unsigned int cmu_sysclk_gscl_status;
+ unsigned int cmu_sysclk_gscl_option;
+ unsigned char res152[0x18];
+ unsigned int cmu_sysclk_isp_status;
+ unsigned int cmu_sysclk_isp_option;
+ unsigned char res153[0x38];
+ unsigned int cmu_sysclk_mfc_status;
+ unsigned int cmu_sysclk_mfc_option;
+ unsigned char res154[0x18];
+ unsigned int cmu_sysclk_g3d_status;
+ unsigned int cmu_sysclk_g3d_option;
+ unsigned char res155[0x38];
+ unsigned int cmu_sysclk_disp1_status;
+ unsigned int cmu_sysclk_disp1_option;
+ unsigned char res156[0x18];
+ unsigned int cmu_sysclk_mau_status;
+ unsigned int cmu_sysclk_mau_option;
+ unsigned char res814[0x18];
+ unsigned int cmu_sysclk_g2d_status;
+ unsigned int cmu_sysclk_g2d_option;
+ unsigned char res815[0x18];
+ unsigned int cmu_sysclk_msc_status;
+ unsigned int cmu_sysclk_msc_option;
+ unsigned char res922[0x18];
+ unsigned int cmu_sysclk_fsys_status;
+ unsigned int cmu_sysclk_fsys_option;
+ unsigned char res816[0x18];
+ unsigned int cmu_sysclk_fsys2_status;
+ unsigned int cmu_sysclk_fsys2_option;
+ unsigned char res817[0x18];
+ unsigned int cmu_sysclk_psgen_status;
+ unsigned int cmu_sysclk_psgen_option;
+ unsigned char res950[0x18];
+ unsigned int cmu_sysclk_peric_status;
+ unsigned int cmu_sysclk_peric_option;
+ unsigned char res818[0x18];
+ unsigned int cmu_sysclk_wcore_status;
+ unsigned int cmu_sysclk_wcore_option;
+ unsigned char res819[0x18];
+ unsigned int cmu_sysclk_coreblk_toppwr_status;
+ unsigned int cmu_sysclk_coreblk_toppwr_option;
+ unsigned char res157[0x414];
+ unsigned int cmu_reset_gscl_configuration;
+ unsigned int cmu_reset_gscl_status;
+ unsigned int cmu_reset_gscl_option;
+ unsigned char res158[0x14];
+ unsigned int cmu_reset_isp_configuration;
+ unsigned int cmu_reset_isp_status;
+ unsigned int cmu_reset_isp_option;
+ unsigned char res159[0x34];
+ unsigned int cmu_reset_mfc_configuration;
+ unsigned int cmu_reset_mfc_status;
+ unsigned int cmu_reset_mfc_option;
+ unsigned char res160[0x14];
+ unsigned int cmu_reset_g3d_configuration;
+ unsigned int cmu_reset_g3d_status;
+ unsigned int cmu_reset_g3d_option;
+ unsigned char res161[0x34];
+ unsigned int cmu_reset_disp1_configuration;
+ unsigned int cmu_reset_disp1_status;
+ unsigned int cmu_reset_disp1_option;
+ unsigned char res162[0x14];
+ unsigned int cmu_reset_mau_configuration;
+ unsigned int cmu_reset_mau_status;
+ unsigned int cmu_reset_mau_option;
+ unsigned char res163[0x14];
+ unsigned int version_info;
+ unsigned int i2s_bypass;
+ unsigned int kfc_swreset_mask_from_eagle;
+ unsigned char res164[0xf4];
+ unsigned int cmu_reset_g2d_configuration;
+ unsigned int cmu_reset_g2d_status;
+ unsigned int cmu_reset_g2d_option;
+ unsigned char res165[0x14];
+ unsigned int cmu_reset_msc_configuration;
+ unsigned int cmu_reset_msc_status;
+ unsigned int cmu_reset_msc_option;
+ unsigned char res166[0x14];
+ unsigned int cmu_reset_fsys_configuration;
+ unsigned int cmu_reset_fsys_status;
+ unsigned int cmu_reset_fsys_option;
+ unsigned char res167[0x14];
+ unsigned int cmu_reset_fsys2_configuration;
+ unsigned int cmu_reset_fsys2_status;
+ unsigned int cmu_reset_fsys2_option;
+ unsigned char res168[0x14];
+ unsigned int cmu_reset_psgen_configuration;
+ unsigned int cmu_reset_psgen_status;
+ unsigned int cmu_reset_psgen_option;
+ unsigned char res169[0x14];
+ unsigned int cmu_reset_peric_configuration;
+ unsigned int cmu_reset_peric_status;
+ unsigned int cmu_reset_peric_option;
+ unsigned char res170[0x14];
+ unsigned int cmu_reset_wcore_configuration;
+ unsigned int cmu_reset_wcore_status;
+ unsigned int cmu_reset_wcore_option;
+};
+#endif /* __ASSEMBLY__ */
+
+#define OM_PIN_BITS 0x1f
+#define OM_PIN_SHIFT 0x1
+#define OM_PIN_MASK (OM_PIN_BITS << OM_PIN_SHIFT)
+
+enum {
+ /*
+ * Assign the OM pin values for respective boot modes.
+ * Exynos4 does not support spi boot and the mmc boot OM
+ * pin values are the same across Exynos4 and Exynos5.
+ */
+ BOOT_MODE_SD = 4, /* SD_CH2 | USB */
+ BOOT_MODE_EMMC = 8, /* EMMC4.4 | USB */
+ BOOT_MODE_EMMC_SD = 40, /* EMMC4.4 | SD_CH2 */
+ BOOT_MODE_SERIAL = 20,
+ /* Boot based on Operating Mode pin settings */
+ BOOT_MODE_OM = 32,
+ BOOT_MODE_USB, /* Boot using USB download */
+};
+
+unsigned int get_boot_mode(void);
+
+void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable);
+
+#define EXYNOS_MIPI_PHY_ENABLE (1 << 0)
+#define EXYNOS_MIPI_PHY_SRESETN (1 << 1)
+#define EXYNOS_MIPI_PHY_MRESETN (1 << 2)
+
+void set_usbhost_phy_ctrl(unsigned int enable);
+
+/* Enables hardware tripping to power off the system when TMU fails */
+void set_hw_thermal_trip(void);
+
+#define POWER_USB_HOST_PHY_CTRL_EN (1 << 0)
+#define POWER_USB_HOST_PHY_CTRL_DISABLE (0 << 0)
+
+void set_usbdrd_phy_ctrl(unsigned int enable);
+
+#define POWER_USB_DRD_PHY_CTRL_EN (1 << 0)
+#define POWER_USB_DRD_PHY_CTRL_DISABLE (0 << 0)
+
+void set_dp_phy_ctrl(unsigned int enable);
+
+#define EXYNOS_DP_PHY_ENABLE (1 << 0)
+
+#define EXYNOS_PS_HOLD_CONTROL_DATA_HIGH (1 << 8)
+#define POWER_ENABLE_HW_TRIP (1UL << 31)
+
+/*
+ * Set ps_hold data driving value high
+ * This enables the machine to stay powered on
+ * after the initial power-on condition goes away
+ * (e.g. power button).
+ */
+void set_ps_hold_ctrl(void);
+
+/* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI clock source */
+#define PMU_DEBUG_XXTI 0x1000
+/* Mask bit[12:8] for xxti clock selection */
+#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00
+
+/*
+ * Pmu debug is used for xclkout, enable xclkout with
+ * source as XXTI
+ */
+void set_xclkout(void);
+
+/*
+ * Read inform1 to get the reset status.
+ * @return: the value can be either S5P_CHECK_SLEEP or
+ * S5P_CHECK_DIDLE or S5P_CHECK_LPA as stored in inform1
+ * if none of these then its normal booting.
+ */
+uint32_t get_reset_status(void);
+
+
+/* Read the resume function and call it */
+void power_exit_wakeup(void);
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PWM_H_
+#define __ASM_ARM_ARCH_PWM_H_
+
+#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */
+#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
+
+/* Divider MUX */
+#define MUX_DIV_1 0 /* 1/1 period */
+#define MUX_DIV_2 1 /* 1/2 period */
+#define MUX_DIV_4 2 /* 1/4 period */
+#define MUX_DIV_8 3 /* 1/8 period */
+#define MUX_DIV_16 4 /* 1/16 period */
+
+#define MUX_DIV_SHIFT(x) (x * 4)
+
+#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2)
+
+#define TCON_START(x) (1 << TCON_OFFSET(x))
+#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1))
+#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2))
+#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
+#define TCON4_AUTO_RELOAD (1 << 22)
+
+#ifndef __ASSEMBLY__
+struct s5p_timer {
+ unsigned int tcfg0;
+ unsigned int tcfg1;
+ unsigned int tcon;
+ unsigned int tcntb0;
+ unsigned int tcmpb0;
+ unsigned int tcnto0;
+ unsigned int tcntb1;
+ unsigned int tcmpb1;
+ unsigned int tcnto1;
+ unsigned int tcntb2;
+ unsigned int tcmpb2;
+ unsigned int tcnto2;
+ unsigned int tcntb3;
+ unsigned int tcmpb3;
+ unsigned int tcnto3;
+ unsigned int tcntb4;
+ unsigned int tcnto4;
+ unsigned int tintcstat;
+};
+#endif /* __ASSEMBLY__ */
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PWM_BACKLIGHT_H_
+#define _PWM_BACKLIGHT_H_
+
+struct pwm_backlight_data {
+ int pwm_id;
+ int period;
+ int max_brightness;
+ int brightness;
+};
+
+extern int exynos_pwm_backlight_init(struct pwm_backlight_data *pd);
+
+#endif /* _PWM_BACKLIGHT_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#ifndef __SOUND_ARCH_H__
+#define __SOUND_ARCH_H__
+
+/* I2S values */
+#define I2S_PLL_CLK 192000000
+#define I2S_SAMPLING_RATE 48000
+#define I2S_BITS_PER_SAMPLE 16
+#define I2S_CHANNELS 2
+#define I2S_RFS 256
+#define I2S_BFS 32
+
+/* I2C values */
+#define AUDIO_I2C_BUS 1
+#define AUDIO_I2C_REG 0x1a
+
+/* Audio Codec */
+#define AUDIO_CODEC "wm8994"
+
+#define AUDIO_COMPAT 1
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Padmavathi Venna <padma.v@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
+#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
+
+#ifndef __ASSEMBLY__
+
+/* SPI peripheral register map; padded to 64KB */
+struct exynos_spi {
+ unsigned int ch_cfg; /* 0x00 */
+ unsigned char reserved0[4];
+ unsigned int mode_cfg; /* 0x08 */
+ unsigned int cs_reg; /* 0x0c */
+ unsigned char reserved1[4];
+ unsigned int spi_sts; /* 0x14 */
+ unsigned int tx_data; /* 0x18 */
+ unsigned int rx_data; /* 0x1c */
+ unsigned int pkt_cnt; /* 0x20 */
+ unsigned char reserved2[4];
+ unsigned int swap_cfg; /* 0x28 */
+ unsigned int fb_clk; /* 0x2c */
+ unsigned char padding[0xffd0];
+};
+
+#define EXYNOS_SPI_MAX_FREQ 50000000
+
+#define SPI_TIMEOUT_MS 10
+#define SF_READ_DATA_CMD 0x3
+
+/* SPI_CHCFG */
+#define SPI_CH_HS_EN (1 << 6)
+#define SPI_CH_RST (1 << 5)
+#define SPI_SLAVE_MODE (1 << 4)
+#define SPI_CH_CPOL_L (1 << 3)
+#define SPI_CH_CPHA_B (1 << 2)
+#define SPI_RX_CH_ON (1 << 1)
+#define SPI_TX_CH_ON (1 << 0)
+
+/* SPI_MODECFG */
+#define SPI_MODE_CH_WIDTH_WORD (0x2 << 29)
+#define SPI_MODE_BUS_WIDTH_WORD (0x2 << 17)
+
+/* SPI_CSREG */
+#define SPI_SLAVE_SIG_INACT (1 << 0)
+
+/* SPI_STS */
+#define SPI_ST_TX_DONE (1 << 25)
+#define SPI_FIFO_LVL_MASK 0x1ff
+#define SPI_TX_LVL_OFFSET 6
+#define SPI_RX_LVL_OFFSET 15
+
+/* Feedback Delay */
+#define SPI_CLK_BYPASS (0 << 0)
+#define SPI_FB_DELAY_90 (1 << 0)
+#define SPI_FB_DELAY_180 (2 << 0)
+#define SPI_FB_DELAY_270 (3 << 0)
+
+/* Packet Count */
+#define SPI_PACKET_CNT_EN (1 << 16)
+
+/* Swap config */
+#define SPI_TX_SWAP_EN (1 << 0)
+#define SPI_TX_BYTE_SWAP (1 << 2)
+#define SPI_TX_HWORD_SWAP (1 << 3)
+#define SPI_TX_BYTE_SWAP (1 << 2)
+#define SPI_RX_SWAP_EN (1 << 4)
+#define SPI_RX_BYTE_SWAP (1 << 6)
+#define SPI_RX_HWORD_SWAP (1 << 7)
+
+#endif /* __ASSEMBLY__ */
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_SPL_H__
+#define __ASM_ARCH_EXYNOS_SPL_H__
+
+#include <asm/arch/dmc.h>
+#include <asm/arch/power.h>
+
+#ifndef __ASSEMBLY__
+/* Parameters of early board initialization in SPL */
+struct spl_machine_param {
+ /* Add fields as and when required */
+ u32 signature;
+ u32 version; /* Version number */
+ u32 size; /* Size of block */
+ /**
+ * Parameters we expect, in order, terminated with \0. Each parameter
+ * is a single character representing one 32-bit word in this
+ * structure.
+ *
+ * Valid characters in this string are:
+ *
+ * Code Name
+ * v mem_iv_size
+ * m mem_type
+ * u uboot_size
+ * b boot_source
+ * f frequency_mhz (memory frequency in MHz)
+ * a ARM clock frequency in MHz
+ * s serial base address
+ * i i2c base address for early access (meant for PMIC)
+ * r board rev GPIO numbers used to read board revision
+ * (lower halfword=bit 0, upper=bit 1)
+ * M Memory Manufacturer name
+ * \0 termination
+ */
+ char params[12]; /* Length must be word-aligned */
+ u32 mem_iv_size; /* Memory channel interleaving size */
+ enum ddr_mode mem_type; /* Type of on-board memory */
+ /*
+ * U-boot size - The iROM mmc copy function used by the SPL takes a
+ * block count paramter to describe the u-boot size unlike the spi
+ * boot copy function which just uses the u-boot size directly. Align
+ * the u-boot size to block size (512 bytes) when populating the SPL
+ * table only for mmc boot.
+ */
+ u32 uboot_size;
+ unsigned boot_source; /* Boot device */
+ unsigned frequency_mhz; /* Frequency of memory in MHz */
+ unsigned arm_freq_mhz; /* ARM Frequency in MHz */
+ u32 serial_base; /* Serial base address */
+ u32 i2c_base; /* i2c base address */
+ u32 board_rev_gpios; /* Board revision GPIOs */
+ enum mem_manuf mem_manuf; /* Memory Manufacturer */
+} __attribute__((__packed__));
+#endif
+
+/**
+ * Validate signature and return a pointer to the parameter table. If the
+ * signature is invalid, call panic() and never return.
+ *
+ * @return pointer to the parameter table if signature matched or never return.
+ */
+struct spl_machine_param *spl_get_machine_params(void);
+
+#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */
--- /dev/null
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.naveen@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Note: This file contains the register description for SROMC
+ */
+
+#ifndef __ASM_ARCH_SROMC_H_
+#define __ASM_ARCH_SROMC_H_
+
+#define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0))
+#define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
+ /* 1-> Byte base address*/
+#define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2))
+#define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3))
+
+#define SROMC_BC_TACS(x) (x << 28) /* address set-up */
+#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */
+#define SROMC_BC_TACC(x) (x << 16) /* access cycle */
+#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */
+#define SROMC_BC_TAH(x) (x << 8) /* address holding time */
+#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */
+#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
+
+#ifndef __ASSEMBLY__
+struct s5p_sromc {
+ unsigned int bw;
+ unsigned int bc[4];
+};
+#endif /* __ASSEMBLY__ */
+
+/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
+void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
+
+enum {
+ FDT_SROM_PMC,
+ FDT_SROM_TACP,
+ FDT_SROM_TAH,
+ FDT_SROM_TCOH,
+ FDT_SROM_TACC,
+ FDT_SROM_TCOS,
+ FDT_SROM_TACS,
+
+ FDT_SROM_TIMING_COUNT,
+};
+
+struct fdt_sromc {
+ u8 bank; /* srom bank number */
+ u8 width; /* bus width in bytes */
+ unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */
+};
+
+#endif /* __ASM_ARCH_SROMC_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2010 Samsung Electrnoics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+u32 get_device_type(void);
+void invalidate_dcache(u32);
+void l2_cache_disable(void);
+void l2_cache_enable(void);
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_SYSTEM_H_
+#define __ASM_ARM_ARCH_SYSTEM_H_
+
+#ifndef __ASSEMBLY__
+struct exynos4_sysreg {
+ unsigned char res1[0x210];
+ unsigned int display_ctrl;
+ unsigned int display_ctrl2;
+ unsigned int camera_control;
+ unsigned int audio_endian;
+ unsigned int jtag_con;
+};
+
+struct exynos5_sysreg {
+ unsigned char res1[0x214];
+ unsigned int disp1blk_cfg;
+ unsigned int disp2blk_cfg;
+ unsigned int hdcp_e_fuse;
+ unsigned int gsclblk_cfg0;
+ unsigned int gsclblk_cfg1;
+ unsigned int reserved;
+ unsigned int ispblk_cfg;
+ unsigned int usb20phy_cfg;
+ unsigned char res2[0x29c];
+ unsigned int mipi_dphy;
+ unsigned int dptx_dphy;
+ unsigned int phyclk_sel;
+};
+#endif
+
+#define USB20_PHY_CFG_HOST_LINK_EN (1 << 0)
+
+/*
+ * Data Synchronization Barrier acts as a special kind of memory barrier.
+ * No instruction in program order after this instruction executes until
+ * this instruction completes. This instruction completes when:
+ * - All explicit memory accesses before this instruction complete.
+ * - All Cache, Branch predictor and TLB maintenance operations before
+ * this instruction complete.
+ */
+#define dsb() __asm__ __volatile__ ("dsb\n\t" : : );
+
+/*
+ * This instruction causes an event to be signaled to all cores
+ * within a multiprocessor system. If SEV is implemented,
+ * WFE must also be implemented.
+ */
+#define sev() __asm__ __volatile__ ("sev\n\t" : : );
+/*
+ * If the Event Register is not set, WFE suspends execution until
+ * one of the following events occurs:
+ * - an IRQ interrupt, unless masked by the CPSR I-bit
+ * - an FIQ interrupt, unless masked by the CPSR F-bit
+ * - an Imprecise Data abort, unless masked by the CPSR A-bit
+ * - a Debug Entry request, if Debug is enabled
+ * - an Event signaled by another processor using the SEV instruction.
+ * If the Event Register is set, WFE clears it and returns immediately.
+ * If WFE is implemented, SEV must also be implemented.
+ */
+#define wfe() __asm__ __volatile__ ("wfe\n\t" : : );
+
+/* Move 0xd3 value to CPSR register to enable SVC mode */
+#define svc32_mode_en() __asm__ __volatile__ \
+ ("@ I&F disable, Mode: 0x13 - SVC\n\t" \
+ "msr cpsr_c, #0x13|0xC0\n\t" : : )
+
+/* Set program counter with the given value */
+#define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x))
+
+/* Branch to the given location */
+#define branch_bx(x) __asm__ __volatile__ ("bx %0\n\t" : : "r"(x))
+
+/* Read Main Id register */
+#define mrc_midr(x) __asm__ __volatile__ \
+ ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(x) : )
+
+/* Read Multiprocessor Affinity Register */
+#define mrc_mpafr(x) __asm__ __volatile__ \
+ ("mrc p15, 0, %0, c0, c0, 5\n\t" : "=r"(x) : )
+
+/* Read System Control Register */
+#define mrc_sctlr(x) __asm__ __volatile__ \
+ ("mrc p15, 0, %0, c1, c0, 0\n\t" : "=r"(x) : )
+
+/* Read Auxiliary Control Register */
+#define mrc_auxr(x) __asm__ __volatile__ \
+ ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(x) : )
+
+/* Read L2 Control register */
+#define mrc_l2_ctlr(x) __asm__ __volatile__ \
+ ("mrc p15, 1, %0, c9, c0, 2\n\t" : "=r"(x) : )
+
+/* Read L2 Auxilliary Control register */
+#define mrc_l2_aux_ctlr(x) __asm__ __volatile__ \
+ ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(x) : )
+
+/* Write System Control Register */
+#define mcr_sctlr(x) __asm__ __volatile__ \
+ ("mcr p15, 0, %0, c1, c0, 0\n\t" : : "r"(x))
+
+/* Write Auxiliary Control Register */
+#define mcr_auxr(x) __asm__ __volatile__ \
+ ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(x))
+
+/* Invalidate all instruction caches to PoU */
+#define mcr_icache(x) __asm__ __volatile__ \
+ ("mcr p15, 0, %0, c7, c5, 0\n\t" : : "r"(x))
+
+/* Invalidate unified TLB */
+#define mcr_tlb(x) __asm__ __volatile__ \
+ ("mcr p15, 0, %0, c8, c7, 0\n\t" : : "r"(x))
+
+/* Write L2 Control register */
+#define mcr_l2_ctlr(x) __asm__ __volatile__ \
+ ("mcr p15, 1, %0, c9, c0, 2\n\t" : : "r"(x))
+
+/* Write L2 Auxilliary Control register */
+#define mcr_l2_aux_ctlr(x) __asm__ __volatile__ \
+ ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(x))
+
+void set_usbhost_mode(unsigned int mode);
+void set_system_display_ctrl(void);
+int exynos_lcd_early_init(const void *blob);
+
+#endif /* _EXYNOS4_SYSTEM_H */
--- /dev/null
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Akshay Saraswat <akshay.s@samsung.com>
+ *
+ * EXYNOS - Thermal Management Unit
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_TMU_H
+#define __ASM_ARCH_TMU_H
+
+struct exynos5_tmu_reg {
+ u32 triminfo;
+ u32 rsvd1[4];
+ u32 triminfo_control;
+ u32 rsvd5[2];
+ u32 tmu_control;
+ u32 rsvd7;
+ u32 tmu_status;
+ u32 sampling_internal;
+ u32 counter_value0;
+ u32 counter_value1;
+ u32 rsvd8[2];
+ u32 current_temp;
+ u32 rsvd10[3];
+ u32 threshold_temp_rise;
+ u32 threshold_temp_fall;
+ u32 rsvd13[2];
+ u32 past_temp3_0;
+ u32 past_temp7_4;
+ u32 past_temp11_8;
+ u32 past_temp15_12;
+ u32 inten;
+ u32 intstat;
+ u32 intclear;
+ u32 rsvd15;
+ u32 emul_con;
+};
+#endif /* __ASM_ARCH_TMU_H */
--- /dev/null
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __TZPC_H_
+#define __TZPC_H_
+
+#ifndef __ASSEMBLY__
+struct exynos_tzpc {
+ unsigned int r0size;
+ char res1[0x7FC];
+ unsigned int decprot0stat;
+ unsigned int decprot0set;
+ unsigned int decprot0clr;
+ unsigned int decprot1stat;
+ unsigned int decprot1set;
+ unsigned int decprot1clr;
+ unsigned int decprot2stat;
+ unsigned int decprot2set;
+ unsigned int decprot2clr;
+ unsigned int decprot3stat;
+ unsigned int decprot3set;
+ unsigned int decprot3clr;
+ char res2[0x7B0];
+ unsigned int periphid0;
+ unsigned int periphid1;
+ unsigned int periphid2;
+ unsigned int periphid3;
+ unsigned int pcellid0;
+ unsigned int pcellid1;
+ unsigned int pcellid2;
+ unsigned int pcellid3;
+};
+
+#define EXYNOS4_NR_TZPC_BANKS 6
+#define EXYNOS5_NR_TZPC_BANKS 10
+
+/* TZPC : Register Offsets */
+#define TZPC_BASE_OFFSET 0x10000
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE 0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET 0xFF
+void tzpc_init(void);
+
+#endif
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_UART_H_
+#define __ASM_ARCH_UART_H_
+
+#ifndef __ASSEMBLY__
+/* baudrate rest value */
+union br_rest {
+ unsigned short slot; /* udivslot */
+ unsigned char value; /* ufracval */
+};
+
+struct s5p_uart {
+ unsigned int ulcon;
+ unsigned int ucon;
+ unsigned int ufcon;
+ unsigned int umcon;
+ unsigned int utrstat;
+ unsigned int uerstat;
+ unsigned int ufstat;
+ unsigned int umstat;
+ unsigned char utxh;
+ unsigned char res1[3];
+ unsigned char urxh;
+ unsigned char res2[3];
+ unsigned int ubrdiv;
+ union br_rest rest;
+ unsigned char res3[0xffd0];
+};
+
+static inline int s5p_uart_divslot(void)
+{
+ return 0;
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_WATCHDOG_H_
+#define __ASM_ARM_ARCH_WATCHDOG_H_
+
+#define WTCON_RESET_OFFSET 0
+#define WTCON_INTEN_OFFSET 2
+#define WTCON_CLKSEL_OFFSET 3
+#define WTCON_EN_OFFSET 5
+#define WTCON_PRE_OFFSET 8
+
+#define WTCON_CLK_16 0x0
+#define WTCON_CLK_32 0x1
+#define WTCON_CLK_64 0x2
+#define WTCON_CLK_128 0x3
+
+#define WTCON_CLK(x) ((x & 0x3) << WTCON_CLKSEL_OFFSET)
+#define WTCON_PRESCALER(x) ((x) << WTCON_PRE_OFFSET)
+#define WTCON_EN (0x1 << WTCON_EN_OFFSET)
+#define WTCON_RESET (0x1 << WTCON_RESET_OFFSET)
+#define WTCON_INT (0x1 << WTCON_INTEN_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct s5p_watchdog {
+ unsigned int wtcon;
+ unsigned int wtdat;
+ unsigned int wtcnt;
+ unsigned int wtclrint;
+};
+
+/* functions */
+void wdt_stop(void);
+void wdt_start(unsigned int timeout);
+#endif /* __ASSEMBLY__ */
+
+#endif
--- /dev/null
+/* Copyright (c) 2012 Samsung Electronics Co. Ltd
+ *
+ * Exynos Phy register definitions
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_EXYNOS_H_
+#define _ASM_ARCH_XHCI_EXYNOS_H_
+
+/* Phy register MACRO definitions */
+
+#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
+#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
+#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
+
+#define PHYUTMI_OTGDISABLE (1 << 6)
+#define PHYUTMI_FORCESUSPEND (1 << 1)
+#define PHYUTMI_FORCESLEEP (1 << 0)
+
+#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
+#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
+
+#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
+#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
+
+#define PHYCLKRST_SSC_EN (0x1 << 20)
+#define PHYCLKRST_REF_SSP_EN (0x1 << 19)
+#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
+
+#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
+
+#define PHYCLKRST_FSEL_MASK (0x3f << 5)
+#define PHYCLKRST_FSEL(_x) ((_x) << 5)
+#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
+#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
+#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
+#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
+
+#define PHYCLKRST_RETENABLEN (0x1 << 4)
+
+#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
+#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
+#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
+
+#define PHYCLKRST_PORTRESET (0x1 << 1)
+#define PHYCLKRST_COMMONONN (0x1 << 0)
+
+#define PHYPARAM0_REF_USE_PAD (0x1 << 31)
+#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
+#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
+
+#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
+#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
+
+#define PHYTEST_POWERDOWN_SSP (0x1 << 3)
+#define PHYTEST_POWERDOWN_HSP (0x1 << 2)
+
+#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
+
+#define FSEL_CLKSEL_24M (0x5)
+
+/* XHCI PHY register structure */
+struct exynos_usb3_phy {
+ unsigned int reserve1;
+ unsigned int link_system;
+ unsigned int phy_utmi;
+ unsigned int phy_pipe;
+ unsigned int phy_clk_rst;
+ unsigned int phy_reg0;
+ unsigned int phy_reg1;
+ unsigned int phy_param0;
+ unsigned int phy_param1;
+ unsigned int phy_term;
+ unsigned int phy_test;
+ unsigned int phy_adp;
+ unsigned int phy_batchg;
+ unsigned int phy_resume;
+ unsigned int reserve2[3];
+ unsigned int link_port;
+};
+
+#endif /* _ASM_ARCH_XHCI_EXYNOS_H_ */
--- /dev/null
+/*
+ * Lowlevel setup for EXYNOS5 based board
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <debug_uart.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dmc.h>
+#include <asm/arch/power.h>
+#include <asm/arch/tzpc.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/system.h>
+#include <asm/armv7.h>
+#include "common_setup.h"
+#include "exynos5_setup.h"
+
+/* These are the things we can do during low-level init */
+enum {
+ DO_WAKEUP = 1 << 0,
+ DO_CLOCKS = 1 << 1,
+ DO_MEM_RESET = 1 << 2,
+ DO_UART = 1 << 3,
+ DO_POWER = 1 << 4,
+};
+
+#ifdef CONFIG_EXYNOS5420
+/*
+ * Power up secondary CPUs.
+ */
+static void secondary_cpu_start(void)
+{
+ v7_enable_smp(EXYNOS5420_INFORM_BASE);
+ svc32_mode_en();
+ branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
+}
+
+/*
+ * This is the entry point of hotplug-in and
+ * cluster switching.
+ */
+static void low_power_start(void)
+{
+ uint32_t val, reg_val;
+
+ reg_val = readl(EXYNOS5420_SPARE_BASE);
+ if (reg_val != CPU_RST_FLAG_VAL) {
+ writel(0x0, CONFIG_LOWPOWER_FLAG);
+ branch_bx(0x0);
+ }
+
+ reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4);
+ if (reg_val != (uint32_t)&low_power_start) {
+ /* Store jump address as low_power_start if not present */
+ writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4);
+ dsb();
+ sev();
+ }
+
+ /* Set the CPU to SVC32 mode */
+ svc32_mode_en();
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+ /* Read MIDR for Primary Part Number */
+ mrc_midr(val);
+ val = (val >> 4);
+ val &= 0xf;
+
+ if (val == 0xf) {
+ configure_l2_ctlr();
+ configure_l2_actlr();
+ v7_enable_l2_hazard_detect();
+ }
+#endif
+
+ /* Invalidate L1 & TLB */
+ val = 0x0;
+ mcr_tlb(val);
+ mcr_icache(val);
+
+ /* Disable MMU stuff and caches */
+ mrc_sctlr(val);
+
+ val &= ~((0x2 << 12) | 0x7);
+ val |= ((0x1 << 12) | (0x8 << 8) | 0x2);
+ mcr_sctlr(val);
+
+ /* CPU state is hotplug or reset */
+ secondary_cpu_start();
+
+ /* Core should not enter into WFI here */
+ wfi();
+}
+
+/*
+ * Pointer to this function is stored in iRam which is used
+ * for jump and power down of a specific core.
+ */
+static void power_down_core(void)
+{
+ uint32_t tmp, core_id, core_config;
+
+ /* Get the unique core id */
+ /*
+ * Multiprocessor Affinity Register
+ * [11:8] Cluster ID
+ * [1:0] CPU ID
+ */
+ mrc_mpafr(core_id);
+ tmp = core_id & 0x3;
+ core_id = (core_id >> 6) & ~3;
+ core_id |= tmp;
+ core_id &= 0x3f;
+
+ /* Set the status of the core to low */
+ core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
+ core_config += EXYNOS5420_CPU_CONFIG_BASE;
+ writel(0x0, core_config);
+
+ /* Core enter WFI */
+ wfi();
+}
+
+/*
+ * Configurations for secondary cores are inapt at this stage.
+ * Reconfigure secondary cores. Shutdown and change the status
+ * of all cores except the primary core.
+ */
+static void secondary_cores_configure(void)
+{
+ /* Clear secondary boot iRAM base */
+ writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
+
+ /* set lowpower flag and address */
+ writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);
+ writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR);
+ writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE);
+ /* Store jump address for power down */
+ writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
+
+ /* Need all core power down check */
+ dsb();
+ sev();
+}
+
+extern void relocate_wait_code(void);
+#endif
+
+int do_lowlevel_init(void)
+{
+ uint32_t reset_status;
+ int actions = 0;
+
+ arch_cpu_init();
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+ /*
+ * Init L2 cache parameters here for use by boot and resume
+ *
+ * These are here instead of in v7_outer_cache_enable() so that the
+ * L2 cache settings get properly set even at resume time or if we're
+ * running U-Boot with the cache off. The kernel still needs us to
+ * set these for it.
+ */
+ configure_l2_ctlr();
+ configure_l2_actlr();
+ dsb();
+ isb();
+#endif
+
+#ifdef CONFIG_EXYNOS5420
+ relocate_wait_code();
+
+ /* Reconfigure secondary cores */
+ secondary_cores_configure();
+#endif
+
+ reset_status = get_reset_status();
+
+ switch (reset_status) {
+ case S5P_CHECK_SLEEP:
+ actions = DO_CLOCKS | DO_WAKEUP;
+ break;
+ case S5P_CHECK_DIDLE:
+ case S5P_CHECK_LPA:
+ actions = DO_WAKEUP;
+ break;
+ default:
+ /* This is a normal boot (not a wake from sleep) */
+ actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
+ }
+
+ if (actions & DO_POWER)
+ set_ps_hold_ctrl();
+
+ if (actions & DO_CLOCKS) {
+ system_clock_init();
+#ifdef CONFIG_DEBUG_UART
+ exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
+ debug_uart_init();
+#endif
+ mem_ctrl_init(actions & DO_MEM_RESET);
+ tzpc_init();
+ }
+
+ return actions & DO_WAKEUP;
+}
--- /dev/null
+/*
+ * Copyright (c) 2012 Samsung Electronics.
+ * Abhilash Kesavan <a.kesavan@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/sromc.h>
+
+static void exynos5_uart_config(int peripheral)
+{
+ int i, start, count;
+
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ start = EXYNOS5_GPIO_A00;
+ count = 4;
+ break;
+ case PERIPH_ID_UART1:
+ start = EXYNOS5_GPIO_D00;
+ count = 4;
+ break;
+ case PERIPH_ID_UART2:
+ start = EXYNOS5_GPIO_A10;
+ count = 4;
+ break;
+ case PERIPH_ID_UART3:
+ start = EXYNOS5_GPIO_A14;
+ count = 2;
+ break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return;
+ }
+ for (i = start; i < start + count; i++) {
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ }
+}
+
+static void exynos5420_uart_config(int peripheral)
+{
+ int i, start, count;
+
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ start = EXYNOS5420_GPIO_A00;
+ count = 4;
+ break;
+ case PERIPH_ID_UART1:
+ start = EXYNOS5420_GPIO_A04;
+ count = 4;
+ break;
+ case PERIPH_ID_UART2:
+ start = EXYNOS5420_GPIO_A10;
+ count = 4;
+ break;
+ case PERIPH_ID_UART3:
+ start = EXYNOS5420_GPIO_A14;
+ count = 2;
+ break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return;
+ }
+
+ for (i = start; i < start + count; i++) {
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ }
+}
+
+static int exynos5_mmc_config(int peripheral, int flags)
+{
+ int i, start, start_ext, gpio_func = 0;
+
+ switch (peripheral) {
+ case PERIPH_ID_SDMMC0:
+ start = EXYNOS5_GPIO_C00;
+ start_ext = EXYNOS5_GPIO_C10;
+ gpio_func = S5P_GPIO_FUNC(0x2);
+ break;
+ case PERIPH_ID_SDMMC1:
+ start = EXYNOS5_GPIO_C20;
+ start_ext = 0;
+ break;
+ case PERIPH_ID_SDMMC2:
+ start = EXYNOS5_GPIO_C30;
+ start_ext = EXYNOS5_GPIO_C43;
+ gpio_func = S5P_GPIO_FUNC(0x3);
+ break;
+ case PERIPH_ID_SDMMC3:
+ start = EXYNOS5_GPIO_C40;
+ start_ext = 0;
+ break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ }
+ if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
+ debug("SDMMC device %d does not support 8bit mode",
+ peripheral);
+ return -1;
+ }
+ if (flags & PINMUX_FLAG_8BIT_MODE) {
+ for (i = start_ext; i <= (start_ext + 3); i++) {
+ gpio_cfg_pin(i, gpio_func);
+ gpio_set_pull(i, S5P_GPIO_PULL_UP);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
+ }
+ }
+ for (i = start; i < (start + 2); i++) {
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
+ }
+ for (i = (start + 3); i <= (start + 6); i++) {
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ gpio_set_pull(i, S5P_GPIO_PULL_UP);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
+ }
+
+ return 0;
+}
+
+static int exynos5420_mmc_config(int peripheral, int flags)
+{
+ int i, start = 0, start_ext = 0;
+
+ switch (peripheral) {
+ case PERIPH_ID_SDMMC0:
+ start = EXYNOS5420_GPIO_C00;
+ start_ext = EXYNOS5420_GPIO_C30;
+ break;
+ case PERIPH_ID_SDMMC1:
+ start = EXYNOS5420_GPIO_C10;
+ start_ext = EXYNOS5420_GPIO_D14;
+ break;
+ case PERIPH_ID_SDMMC2:
+ start = EXYNOS5420_GPIO_C20;
+ start_ext = 0;
+ break;
+ default:
+ start = 0;
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ }
+
+ if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
+ debug("SDMMC device %d does not support 8bit mode",
+ peripheral);
+ return -1;
+ }
+
+ if (flags & PINMUX_FLAG_8BIT_MODE) {
+ for (i = start_ext; i <= (start_ext + 3); i++) {
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ gpio_set_pull(i, S5P_GPIO_PULL_UP);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
+ }
+ }
+
+ for (i = start; i < (start + 3); i++) {
+ /*
+ * MMC0 is intended to be used for eMMC. The
+ * card detect pin is used as a VDDEN signal to
+ * power on the eMMC. The 5420 iROM makes
+ * this same assumption.
+ */
+ if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) {
+#ifndef CONFIG_SPL_BUILD
+ gpio_request(i, "sdmmc0_vdden");
+#endif
+ gpio_set_value(i, 1);
+ gpio_cfg_pin(i, S5P_GPIO_OUTPUT);
+ } else {
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ }
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
+ }
+
+ for (i = (start + 3); i <= (start + 6); i++) {
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ gpio_set_pull(i, S5P_GPIO_PULL_UP);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
+ }
+
+ return 0;
+}
+
+static void exynos5_sromc_config(int flags)
+{
+ int i;
+
+ /*
+ * SROM:CS1 and EBI
+ *
+ * GPY0[0] SROM_CSn[0]
+ * GPY0[1] SROM_CSn[1](2)
+ * GPY0[2] SROM_CSn[2]
+ * GPY0[3] SROM_CSn[3]
+ * GPY0[4] EBI_OEn(2)
+ * GPY0[5] EBI_EEn(2)
+ *
+ * GPY1[0] EBI_BEn[0](2)
+ * GPY1[1] EBI_BEn[1](2)
+ * GPY1[2] SROM_WAIT(2)
+ * GPY1[3] EBI_DATA_RDn(2)
+ */
+ gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
+ S5P_GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2));
+
+ for (i = 0; i < 4; i++)
+ gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2));
+
+ /*
+ * EBI: 8 Addrss Lines
+ *
+ * GPY3[0] EBI_ADDR[0](2)
+ * GPY3[1] EBI_ADDR[1](2)
+ * GPY3[2] EBI_ADDR[2](2)
+ * GPY3[3] EBI_ADDR[3](2)
+ * GPY3[4] EBI_ADDR[4](2)
+ * GPY3[5] EBI_ADDR[5](2)
+ * GPY3[6] EBI_ADDR[6](2)
+ * GPY3[7] EBI_ADDR[7](2)
+ *
+ * EBI: 16 Data Lines
+ *
+ * GPY5[0] EBI_DATA[0](2)
+ * GPY5[1] EBI_DATA[1](2)
+ * GPY5[2] EBI_DATA[2](2)
+ * GPY5[3] EBI_DATA[3](2)
+ * GPY5[4] EBI_DATA[4](2)
+ * GPY5[5] EBI_DATA[5](2)
+ * GPY5[6] EBI_DATA[6](2)
+ * GPY5[7] EBI_DATA[7](2)
+ *
+ * GPY6[0] EBI_DATA[8](2)
+ * GPY6[1] EBI_DATA[9](2)
+ * GPY6[2] EBI_DATA[10](2)
+ * GPY6[3] EBI_DATA[11](2)
+ * GPY6[4] EBI_DATA[12](2)
+ * GPY6[5] EBI_DATA[13](2)
+ * GPY6[6] EBI_DATA[14](2)
+ * GPY6[7] EBI_DATA[15](2)
+ */
+ for (i = 0; i < 8; i++) {
+ gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2));
+ gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP);
+
+ gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2));
+ gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP);
+
+ gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2));
+ gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP);
+ }
+}
+
+static void exynos5_i2c_config(int peripheral, int flags)
+{
+ int func01, func23;
+
+ /* High-Speed I2C */
+ if (flags & PINMUX_FLAG_HS_MODE) {
+ func01 = 4;
+ func23 = 4;
+ } else {
+ func01 = 2;
+ func23 = 3;
+ }
+
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(func01));
+ gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(func01));
+ break;
+ case PERIPH_ID_I2C1:
+ gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(func01));
+ gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(func01));
+ break;
+ case PERIPH_ID_I2C2:
+ gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(func23));
+ gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(func23));
+ break;
+ case PERIPH_ID_I2C3:
+ gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(func23));
+ gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(func23));
+ break;
+ case PERIPH_ID_I2C4:
+ gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C5:
+ gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C6:
+ gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4));
+ break;
+ case PERIPH_ID_I2C7:
+ gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3));
+ break;
+ }
+}
+
+static void exynos5420_i2c_config(int peripheral)
+{
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C1:
+ gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C2:
+ gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C3:
+ gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C4:
+ gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C5:
+ gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C6:
+ gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4));
+ break;
+ case PERIPH_ID_I2C7:
+ gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C8:
+ gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C9:
+ gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C10:
+ gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2));
+ break;
+ }
+}
+
+static void exynos5_i2s_config(int peripheral)
+{
+ int i;
+
+ switch (peripheral) {
+ case PERIPH_ID_I2S0:
+ for (i = 0; i < 5; i++)
+ gpio_cfg_pin(EXYNOS5_GPIO_Z0 + i, S5P_GPIO_FUNC(0x02));
+ break;
+ case PERIPH_ID_I2S1:
+ for (i = 0; i < 5; i++)
+ gpio_cfg_pin(EXYNOS5_GPIO_B00 + i, S5P_GPIO_FUNC(0x02));
+ break;
+ }
+}
+
+void exynos5_spi_config(int peripheral)
+{
+ int cfg = 0, pin = 0, i;
+
+ switch (peripheral) {
+ case PERIPH_ID_SPI0:
+ cfg = S5P_GPIO_FUNC(0x2);
+ pin = EXYNOS5_GPIO_A20;
+ break;
+ case PERIPH_ID_SPI1:
+ cfg = S5P_GPIO_FUNC(0x2);
+ pin = EXYNOS5_GPIO_A24;
+ break;
+ case PERIPH_ID_SPI2:
+ cfg = S5P_GPIO_FUNC(0x5);
+ pin = EXYNOS5_GPIO_B11;
+ break;
+ case PERIPH_ID_SPI3:
+ cfg = S5P_GPIO_FUNC(0x2);
+ pin = EXYNOS5_GPIO_F10;
+ break;
+ case PERIPH_ID_SPI4:
+ for (i = 0; i < 2; i++) {
+ gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4));
+ }
+ break;
+ }
+ if (peripheral != PERIPH_ID_SPI4) {
+ for (i = pin; i < pin + 4; i++)
+ gpio_cfg_pin(i, cfg);
+ }
+}
+
+void exynos5420_spi_config(int peripheral)
+{
+ int cfg, pin, i;
+
+ switch (peripheral) {
+ case PERIPH_ID_SPI0:
+ pin = EXYNOS5420_GPIO_A20;
+ cfg = S5P_GPIO_FUNC(0x2);
+ break;
+ case PERIPH_ID_SPI1:
+ pin = EXYNOS5420_GPIO_A24;
+ cfg = S5P_GPIO_FUNC(0x2);
+ break;
+ case PERIPH_ID_SPI2:
+ pin = EXYNOS5420_GPIO_B11;
+ cfg = S5P_GPIO_FUNC(0x5);
+ break;
+ case PERIPH_ID_SPI3:
+ pin = EXYNOS5420_GPIO_F10;
+ cfg = S5P_GPIO_FUNC(0x2);
+ break;
+ case PERIPH_ID_SPI4:
+ cfg = 0;
+ pin = 0;
+ break;
+ default:
+ cfg = 0;
+ pin = 0;
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return;
+ }
+
+ if (peripheral != PERIPH_ID_SPI4) {
+ for (i = pin; i < pin + 4; i++)
+ gpio_cfg_pin(i, cfg);
+ } else {
+ for (i = 0; i < 2; i++) {
+ gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i,
+ S5P_GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i,
+ S5P_GPIO_FUNC(0x4));
+ }
+ }
+}
+
+static int exynos5_pinmux_config(int peripheral, int flags)
+{
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ exynos5_uart_config(peripheral);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC3:
+ return exynos5_mmc_config(peripheral, flags);
+ case PERIPH_ID_SROMC:
+ exynos5_sromc_config(flags);
+ break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ exynos5_i2c_config(peripheral, flags);
+ break;
+ case PERIPH_ID_I2S0:
+ case PERIPH_ID_I2S1:
+ exynos5_i2s_config(peripheral);
+ break;
+ case PERIPH_ID_SPI0:
+ case PERIPH_ID_SPI1:
+ case PERIPH_ID_SPI2:
+ case PERIPH_ID_SPI3:
+ case PERIPH_ID_SPI4:
+ exynos5_spi_config(peripheral);
+ break;
+ case PERIPH_ID_DPHPD:
+ /* Set Hotplug detect for DP */
+ gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
+
+ /*
+ * Hotplug detect should have an external pullup; disable the
+ * internal pulldown so they don't fight.
+ */
+ gpio_set_pull(EXYNOS5_GPIO_X07, S5P_GPIO_PULL_NONE);
+ break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ }
+
+ return 0;
+}
+
+static int exynos5420_pinmux_config(int peripheral, int flags)
+{
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ exynos5420_uart_config(peripheral);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC3:
+ return exynos5420_mmc_config(peripheral, flags);
+ case PERIPH_ID_SPI0:
+ case PERIPH_ID_SPI1:
+ case PERIPH_ID_SPI2:
+ case PERIPH_ID_SPI3:
+ case PERIPH_ID_SPI4:
+ exynos5420_spi_config(peripheral);
+ break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ case PERIPH_ID_I2C8:
+ case PERIPH_ID_I2C9:
+ case PERIPH_ID_I2C10:
+ exynos5420_i2c_config(peripheral);
+ break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ }
+
+ return 0;
+}
+
+static void exynos4_i2c_config(int peripheral, int flags)
+{
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ gpio_cfg_pin(EXYNOS4_GPIO_D10, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS4_GPIO_D11, S5P_GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C1:
+ gpio_cfg_pin(EXYNOS4_GPIO_D12, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS4_GPIO_D13, S5P_GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C2:
+ gpio_cfg_pin(EXYNOS4_GPIO_A06, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4_GPIO_A07, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C3:
+ gpio_cfg_pin(EXYNOS4_GPIO_A12, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4_GPIO_A13, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C4:
+ gpio_cfg_pin(EXYNOS4_GPIO_B2, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4_GPIO_B3, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C5:
+ gpio_cfg_pin(EXYNOS4_GPIO_B6, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4_GPIO_B7, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C6:
+ gpio_cfg_pin(EXYNOS4_GPIO_C13, S5P_GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS4_GPIO_C14, S5P_GPIO_FUNC(0x4));
+ break;
+ case PERIPH_ID_I2C7:
+ gpio_cfg_pin(EXYNOS4_GPIO_D02, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4_GPIO_D03, S5P_GPIO_FUNC(0x3));
+ break;
+ }
+}
+
+static int exynos4_mmc_config(int peripheral, int flags)
+{
+ int i, start = 0, start_ext = 0;
+ unsigned int func, ext_func;
+
+ switch (peripheral) {
+ case PERIPH_ID_SDMMC0:
+ start = EXYNOS4_GPIO_K00;
+ start_ext = EXYNOS4_GPIO_K13;
+ func = S5P_GPIO_FUNC(0x2);
+ ext_func = S5P_GPIO_FUNC(0x3);
+ break;
+ case PERIPH_ID_SDMMC2:
+ start = EXYNOS4_GPIO_K20;
+ start_ext = EXYNOS4_GPIO_K33;
+ func = S5P_GPIO_FUNC(0x2);
+ ext_func = S5P_GPIO_FUNC(0x3);
+ break;
+ case PERIPH_ID_SDMMC4:
+ start = EXYNOS4_GPIO_K00;
+ start_ext = EXYNOS4_GPIO_K13;
+ func = S5P_GPIO_FUNC(0x3);
+ ext_func = S5P_GPIO_FUNC(0x4);
+ break;
+ default:
+ return -1;
+ }
+ for (i = start; i < (start + 7); i++) {
+ if (i == (start + 2))
+ continue;
+ gpio_cfg_pin(i, func);
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
+ }
+ /* SDMMC2 do not use 8bit mode at exynos4 */
+ if (flags & PINMUX_FLAG_8BIT_MODE) {
+ for (i = start_ext; i < (start_ext + 4); i++) {
+ gpio_cfg_pin(i, ext_func);
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
+ }
+ }
+
+ return 0;
+}
+
+static void exynos4_uart_config(int peripheral)
+{
+ int i, start, count;
+
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ start = EXYNOS4_GPIO_A00;
+ count = 4;
+ break;
+ case PERIPH_ID_UART1:
+ start = EXYNOS4_GPIO_A04;
+ count = 4;
+ break;
+ case PERIPH_ID_UART2:
+ start = EXYNOS4_GPIO_A10;
+ count = 4;
+ break;
+ case PERIPH_ID_UART3:
+ start = EXYNOS4_GPIO_A14;
+ count = 2;
+ break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return;
+ }
+ for (i = start; i < (start + count); i++) {
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ }
+}
+
+static void exynos4x12_i2c_config(int peripheral, int flags)
+{
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ gpio_cfg_pin(EXYNOS4X12_GPIO_D10, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS4X12_GPIO_D11, S5P_GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C1:
+ gpio_cfg_pin(EXYNOS4X12_GPIO_D12, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS4X12_GPIO_D13, S5P_GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C2:
+ gpio_cfg_pin(EXYNOS4X12_GPIO_A06, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4X12_GPIO_A07, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C3:
+ gpio_cfg_pin(EXYNOS4X12_GPIO_A12, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4X12_GPIO_A13, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C4:
+ gpio_cfg_pin(EXYNOS4X12_GPIO_B2, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4X12_GPIO_B3, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C5:
+ gpio_cfg_pin(EXYNOS4X12_GPIO_B6, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4X12_GPIO_B7, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C6:
+ gpio_cfg_pin(EXYNOS4X12_GPIO_C13, S5P_GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS4X12_GPIO_C14, S5P_GPIO_FUNC(0x4));
+ break;
+ case PERIPH_ID_I2C7:
+ gpio_cfg_pin(EXYNOS4X12_GPIO_D02, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4X12_GPIO_D03, S5P_GPIO_FUNC(0x3));
+ break;
+ }
+}
+
+static int exynos4x12_mmc_config(int peripheral, int flags)
+{
+ int i, start = 0, start_ext = 0;
+ unsigned int func, ext_func;
+
+ switch (peripheral) {
+ case PERIPH_ID_SDMMC0:
+ start = EXYNOS4X12_GPIO_K00;
+ start_ext = EXYNOS4X12_GPIO_K13;
+ func = S5P_GPIO_FUNC(0x2);
+ ext_func = S5P_GPIO_FUNC(0x3);
+ break;
+ case PERIPH_ID_SDMMC2:
+ start = EXYNOS4X12_GPIO_K20;
+ start_ext = EXYNOS4X12_GPIO_K33;
+ func = S5P_GPIO_FUNC(0x2);
+ ext_func = S5P_GPIO_FUNC(0x3);
+ break;
+ case PERIPH_ID_SDMMC4:
+ start = EXYNOS4X12_GPIO_K00;
+ start_ext = EXYNOS4X12_GPIO_K13;
+ func = S5P_GPIO_FUNC(0x3);
+ ext_func = S5P_GPIO_FUNC(0x4);
+ break;
+ default:
+ return -1;
+ }
+ for (i = start; i < (start + 7); i++) {
+ if (i == (start + 2))
+ continue;
+ gpio_cfg_pin(i, func);
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
+ }
+ if (flags & PINMUX_FLAG_8BIT_MODE) {
+ for (i = start_ext; i < (start_ext + 4); i++) {
+ gpio_cfg_pin(i, ext_func);
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
+ }
+ }
+
+ return 0;
+}
+
+static void exynos4x12_uart_config(int peripheral)
+{
+ int i, start, count;
+
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ start = EXYNOS4X12_GPIO_A00;
+ count = 4;
+ break;
+ case PERIPH_ID_UART1:
+ start = EXYNOS4X12_GPIO_A04;
+ count = 4;
+ break;
+ case PERIPH_ID_UART2:
+ start = EXYNOS4X12_GPIO_A10;
+ count = 4;
+ break;
+ case PERIPH_ID_UART3:
+ start = EXYNOS4X12_GPIO_A14;
+ count = 2;
+ break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return;
+ }
+ for (i = start; i < (start + count); i++) {
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ }
+}
+
+static int exynos4_pinmux_config(int peripheral, int flags)
+{
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ exynos4_uart_config(peripheral);
+ break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ exynos4_i2c_config(peripheral, flags);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC4:
+ return exynos4_mmc_config(peripheral, flags);
+ case PERIPH_ID_SDMMC1:
+ case PERIPH_ID_SDMMC3:
+ debug("SDMMC device %d not implemented\n", peripheral);
+ return -1;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ }
+
+ return 0;
+}
+
+static int exynos4x12_pinmux_config(int peripheral, int flags)
+{
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ exynos4x12_uart_config(peripheral);
+ break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ exynos4x12_i2c_config(peripheral, flags);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC4:
+ return exynos4x12_mmc_config(peripheral, flags);
+ case PERIPH_ID_SDMMC1:
+ case PERIPH_ID_SDMMC3:
+ debug("SDMMC device %d not implemented\n", peripheral);
+ return -1;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ }
+
+ return 0;
+}
+
+int exynos_pinmux_config(int peripheral, int flags)
+{
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ return exynos5420_pinmux_config(peripheral, flags);
+ else if (proid_is_exynos5250())
+ return exynos5_pinmux_config(peripheral, flags);
+ } else if (cpu_is_exynos4()) {
+ if (proid_is_exynos4412())
+ return exynos4x12_pinmux_config(peripheral, flags);
+ else
+ return exynos4_pinmux_config(peripheral, flags);
+ }
+
+ debug("pinmux functionality not supported\n");
+
+ return -1;
+}
+
+#ifdef CONFIG_OF_CONTROL
+static int exynos4_pinmux_decode_periph_id(const void *blob, int node)
+{
+ int err;
+ u32 cell[3];
+
+ err = fdtdec_get_int_array(blob, node, "interrupts", cell,
+ ARRAY_SIZE(cell));
+ if (err) {
+ debug(" invalid peripheral id\n");
+ return PERIPH_ID_NONE;
+ }
+
+ return cell[1];
+}
+
+static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
+{
+ int err;
+ u32 cell[3];
+
+ err = fdtdec_get_int_array(blob, node, "interrupts", cell,
+ ARRAY_SIZE(cell));
+ if (err)
+ return PERIPH_ID_NONE;
+
+ return cell[1];
+}
+
+int pinmux_decode_periph_id(const void *blob, int node)
+{
+ if (cpu_is_exynos5())
+ return exynos5_pinmux_decode_periph_id(blob, node);
+ else if (cpu_is_exynos4())
+ return exynos4_pinmux_decode_periph_id(blob, node);
+
+ return PERIPH_ID_NONE;
+}
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/power.h>
+
+static void exynos4_mipi_phy_control(unsigned int dev_index,
+ unsigned int enable)
+{
+ struct exynos4_power *pmu =
+ (struct exynos4_power *)samsung_get_base_power();
+ unsigned int addr, cfg = 0;
+
+ if (dev_index == 0)
+ addr = (unsigned int)&pmu->mipi_phy0_control;
+ else
+ addr = (unsigned int)&pmu->mipi_phy1_control;
+
+
+ cfg = readl(addr);
+ if (enable)
+ cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
+ else
+ cfg &= ~(EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
+
+ writel(cfg, addr);
+}
+
+void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
+{
+ if (cpu_is_exynos4())
+ exynos4_mipi_phy_control(dev_index, enable);
+}
+
+void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
+{
+ struct exynos5_power *power =
+ (struct exynos5_power *)samsung_get_base_power();
+
+ if (enable) {
+ /* Enabling USBHOST_PHY */
+ setbits_le32(&power->usbhost_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ } else {
+ /* Disabling USBHOST_PHY */
+ clrbits_le32(&power->usbhost_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ }
+}
+
+void exynos4412_set_usbhost_phy_ctrl(unsigned int enable)
+{
+ struct exynos4412_power *power =
+ (struct exynos4412_power *)samsung_get_base_power();
+
+ if (enable) {
+ /* Enabling USBHOST_PHY */
+ setbits_le32(&power->usbhost_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ setbits_le32(&power->hsic1_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ setbits_le32(&power->hsic2_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ } else {
+ /* Disabling USBHOST_PHY */
+ clrbits_le32(&power->usbhost_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ clrbits_le32(&power->hsic1_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ clrbits_le32(&power->hsic2_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ }
+}
+
+void set_usbhost_phy_ctrl(unsigned int enable)
+{
+ if (cpu_is_exynos5())
+ exynos5_set_usbhost_phy_ctrl(enable);
+ else if (cpu_is_exynos4())
+ if (proid_is_exynos4412())
+ exynos4412_set_usbhost_phy_ctrl(enable);
+}
+
+static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
+{
+ struct exynos5_power *power =
+ (struct exynos5_power *)samsung_get_base_power();
+
+ if (enable) {
+ /* Enabling USBDRD_PHY */
+ setbits_le32(&power->usbdrd_phy_control,
+ POWER_USB_DRD_PHY_CTRL_EN);
+ } else {
+ /* Disabling USBDRD_PHY */
+ clrbits_le32(&power->usbdrd_phy_control,
+ POWER_USB_DRD_PHY_CTRL_EN);
+ }
+}
+
+static void exynos5420_set_usbdev_phy_ctrl(unsigned int enable)
+{
+ struct exynos5420_power *power =
+ (struct exynos5420_power *)samsung_get_base_power();
+
+ if (enable) {
+ /* Enabling USBDEV_PHY */
+ setbits_le32(&power->usbdev_phy_control,
+ POWER_USB_DRD_PHY_CTRL_EN);
+ setbits_le32(&power->usbdev1_phy_control,
+ POWER_USB_DRD_PHY_CTRL_EN);
+ } else {
+ /* Disabling USBDEV_PHY */
+ clrbits_le32(&power->usbdev_phy_control,
+ POWER_USB_DRD_PHY_CTRL_EN);
+ clrbits_le32(&power->usbdev1_phy_control,
+ POWER_USB_DRD_PHY_CTRL_EN);
+ }
+}
+
+void set_usbdrd_phy_ctrl(unsigned int enable)
+{
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ exynos5420_set_usbdev_phy_ctrl(enable);
+ else
+ exynos5_set_usbdrd_phy_ctrl(enable);
+ }
+}
+
+static void exynos5_dp_phy_control(unsigned int enable)
+{
+ unsigned int cfg;
+ struct exynos5_power *power =
+ (struct exynos5_power *)samsung_get_base_power();
+
+ cfg = readl(&power->dptx_phy_control);
+ if (enable)
+ cfg |= EXYNOS_DP_PHY_ENABLE;
+ else
+ cfg &= ~EXYNOS_DP_PHY_ENABLE;
+
+ writel(cfg, &power->dptx_phy_control);
+}
+
+void set_dp_phy_ctrl(unsigned int enable)
+{
+ if (cpu_is_exynos5())
+ exynos5_dp_phy_control(enable);
+}
+
+static void exynos5_set_ps_hold_ctrl(void)
+{
+ struct exynos5_power *power =
+ (struct exynos5_power *)samsung_get_base_power();
+
+ /* Set PS-Hold high */
+ setbits_le32(&power->ps_hold_control,
+ EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
+}
+
+/*
+ * Set ps_hold data driving value high
+ * This enables the machine to stay powered on
+ * after the initial power-on condition goes away
+ * (e.g. power button).
+ */
+void set_ps_hold_ctrl(void)
+{
+ if (cpu_is_exynos5())
+ exynos5_set_ps_hold_ctrl();
+}
+
+
+static void exynos5_set_xclkout(void)
+{
+ struct exynos5_power *power =
+ (struct exynos5_power *)samsung_get_base_power();
+
+ /* use xxti for xclk out */
+ clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
+ PMU_DEBUG_XXTI);
+}
+
+void set_xclkout(void)
+{
+ if (cpu_is_exynos5())
+ exynos5_set_xclkout();
+}
+
+/* Enables hardware tripping to power off the system when TMU fails */
+void set_hw_thermal_trip(void)
+{
+ if (cpu_is_exynos5()) {
+ struct exynos5_power *power =
+ (struct exynos5_power *)samsung_get_base_power();
+
+ /* PS_HOLD_CONTROL register ENABLE_HW_TRIP bit*/
+ setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP);
+ }
+}
+
+static uint32_t exynos5_get_reset_status(void)
+{
+ struct exynos5_power *power =
+ (struct exynos5_power *)samsung_get_base_power();
+
+ return power->inform1;
+}
+
+static uint32_t exynos4_get_reset_status(void)
+{
+ struct exynos4_power *power =
+ (struct exynos4_power *)samsung_get_base_power();
+
+ return power->inform1;
+}
+
+uint32_t get_reset_status(void)
+{
+ if (cpu_is_exynos5())
+ return exynos5_get_reset_status();
+ else
+ return exynos4_get_reset_status();
+}
+
+static void exynos5_power_exit_wakeup(void)
+{
+ struct exynos5_power *power =
+ (struct exynos5_power *)samsung_get_base_power();
+ typedef void (*resume_func)(void);
+
+ ((resume_func)power->inform0)();
+}
+
+static void exynos4_power_exit_wakeup(void)
+{
+ struct exynos4_power *power =
+ (struct exynos4_power *)samsung_get_base_power();
+ typedef void (*resume_func)(void);
+
+ ((resume_func)power->inform0)();
+}
+
+void power_exit_wakeup(void)
+{
+ if (cpu_is_exynos5())
+ exynos5_power_exit_wakeup();
+ else
+ exynos4_power_exit_wakeup();
+}
+
+unsigned int get_boot_mode(void)
+{
+ unsigned int om_pin = samsung_get_base_power();
+
+ return readl(om_pin) & OM_PIN_MASK;
+}
--- /dev/null
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Akshay Saraswat <akshay.s@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+
+ .globl relocate_wait_code
+relocate_wait_code:
+ adr r0, code_base @ r0: source address (start)
+ adr r1, code_end @ r1: source address (end)
+ ldr r2, =0x02073000 @ r2: target address
+1:
+ ldmia r0!, {r3-r6}
+ stmia r2!, {r3-r6}
+ cmp r0, r1
+ blt 1b
+ b code_end
+ .ltorg
+/*
+ * Secondary core waits here until Primary wake it up.
+ * Below code is copied to CONFIG_EXYNOS_RELOCATE_CODE_BASE.
+ * This is a workaround code which is supposed to act as a
+ * substitute/supplement to the iROM code.
+ *
+ * This workaround code is relocated to the address 0x02073000
+ * because that comes out to be the last 4KB of the iRAM
+ * (Base Address - 0x02020000, Limit Address - 0x020740000).
+ *
+ * U-boot and kernel are aware of this code and flags by the simple
+ * fact that we are implementing a workaround in the last 4KB
+ * of the iRAM and we have already defined these flag and address
+ * values in both kernel and U-boot for our use.
+ */
+code_base:
+ b 1f
+/*
+ * These addresses are being used as flags in u-boot and kernel.
+ *
+ * Jump address for resume and flag to check for resume/reset:
+ * Resume address - 0x2073008
+ * Resume flag - 0x207300C
+ *
+ * Jump address for cluster switching:
+ * Switch address - 0x2073018
+ *
+ * Jump address for core hotplug:
+ * Hotplug address - 0x207301C
+ *
+ * Jump address for C2 state (Reserved for future not being used right now):
+ * C2 address - 0x2073024
+ *
+ * Managed per core status for the active cluster:
+ * CPU0 state - 0x2073028
+ * CPU1 state - 0x207302C
+ * CPU2 state - 0x2073030
+ * CPU3 state - 0x2073034
+ *
+ * Managed per core GIC status for the active cluster:
+ * CPU0 gic state - 0x2073038
+ * CPU1 gic state - 0x207303C
+ * CPU2 gic state - 0x2073040
+ * CPU3 gic state - 0x2073044
+ *
+ * Logic of the code:
+ * Step-1: Read current CPU status.
+ * Step-2: If it's a resume then continue, else jump to step 4.
+ * Step-3: Clear inform1 PMU register and jump to inform0 value.
+ * Step-4: If it's a switch, C2 or reset, get the hotplug address.
+ * Step-5: If address is not available, enter WFE.
+ * Step-6: If address is available, jump to that address.
+ */
+ nop @ for backward compatibility
+ .word 0x0 @ REG0: RESUME_ADDR
+ .word 0x0 @ REG1: RESUME_FLAG
+ .word 0x0 @ REG2
+ .word 0x0 @ REG3
+_switch_addr:
+ .word 0x0 @ REG4: SWITCH_ADDR
+_hotplug_addr:
+ .word 0x0 @ REG5: CPU1_BOOT_REG
+ .word 0x0 @ REG6
+_c2_addr:
+ .word 0x0 @ REG7: REG_C2_ADDR
+_cpu_state:
+ .word 0x1 @ CPU0_STATE : RESET
+ .word 0x2 @ CPU1_STATE : SECONDARY RESET
+ .word 0x2 @ CPU2_STATE : SECONDARY RESET
+ .word 0x2 @ CPU3_STATE : SECONDARY RESET
+_gic_state:
+ .word 0x0 @ CPU0 - GICD_IGROUPR0
+ .word 0x0 @ CPU1 - GICD_IGROUPR0
+ .word 0x0 @ CPU2 - GICD_IGROUPR0
+ .word 0x0 @ CPU3 - GICD_IGROUPR0
+1:
+ adr r0, _cpu_state
+ mrc p15, 0, r7, c0, c0, 5 @ read MPIDR
+ and r7, r7, #0xf @ r7 = cpu id
+/* Read the current cpu state */
+ ldr r10, [r0, r7, lsl #2]
+svc_entry:
+ tst r10, #(1 << 4)
+ adrne r0, _switch_addr
+ bne wait_for_addr
+/* Clear INFORM1 */
+ ldr r0, =(0x10040000 + 0x804)
+ ldr r1, [r0]
+ cmp r1, #0x0
+ movne r1, #0x0
+ strne r1, [r0]
+/* Get INFORM0 */
+ ldrne r1, =(0x10040000 + 0x800)
+ ldrne pc, [r1]
+ tst r10, #(1 << 0)
+ ldrne pc, =0x23e00000
+ adr r0, _hotplug_addr
+wait_for_addr:
+ ldr r1, [r0]
+ cmp r1, #0x0
+ bxne r1
+ wfe
+ b wait_for_addr
+ .ltorg
+code_end:
+ mov pc, lr
--- /dev/null
+/*
+ * Copyright (c) 2010 Samsung Electronics.
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/system.h>
+
+void reset_cpu(ulong addr)
+{
+ writel(0x1, samsung_get_base_swreset());
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/dmc.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/spi.h>
+
+#include "common_setup.h"
+#include "clock_init.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Index into irom ptr table */
+enum index {
+ MMC_INDEX,
+ EMMC44_INDEX,
+ EMMC44_END_INDEX,
+ SPI_INDEX,
+ USB_INDEX,
+};
+
+/* IROM Function Pointers Table */
+u32 irom_ptr_table[] = {
+ [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */
+ [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/
+ [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer
+ -EMMC4.4 end boot operation */
+ [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */
+ [USB_INDEX] = 0x02020070, /* iROM Function Pointer-USB boot*/
+ };
+
+void *get_irom_func(int index)
+{
+ return (void *)*(u32 *)irom_ptr_table[index];
+}
+
+#ifdef CONFIG_USB_BOOTING
+/*
+ * Set/clear program flow prediction and return the previous state.
+ */
+static int config_branch_prediction(int set_cr_z)
+{
+ unsigned int cr;
+
+ /* System Control Register: 11th bit Z Branch prediction enable */
+ cr = get_cr();
+ set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z);
+
+ return cr & CR_Z;
+}
+#endif
+
+#ifdef CONFIG_SPI_BOOTING
+static void spi_rx_tx(struct exynos_spi *regs, int todo,
+ void *dinp, void const *doutp, int i)
+{
+ uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
+ int rx_lvl, tx_lvl;
+ uint out_bytes, in_bytes;
+
+ out_bytes = todo;
+ in_bytes = todo;
+ setbits_le32(®s->ch_cfg, SPI_CH_RST);
+ clrbits_le32(®s->ch_cfg, SPI_CH_RST);
+ writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
+
+ while (in_bytes) {
+ uint32_t spi_sts;
+ int temp;
+
+ spi_sts = readl(®s->spi_sts);
+ rx_lvl = ((spi_sts >> 15) & 0x7f);
+ tx_lvl = ((spi_sts >> 6) & 0x7f);
+ while (tx_lvl < 32 && out_bytes) {
+ temp = 0xffffffff;
+ writel(temp, ®s->tx_data);
+ out_bytes -= 4;
+ tx_lvl += 4;
+ }
+ while (rx_lvl >= 4 && in_bytes) {
+ temp = readl(®s->rx_data);
+ if (rxp)
+ *rxp++ = temp;
+ in_bytes -= 4;
+ rx_lvl -= 4;
+ }
+ }
+}
+
+/*
+ * Copy uboot from spi flash to RAM
+ *
+ * @parma uboot_size size of u-boot to copy
+ * @param uboot_addr address in u-boot to copy
+ */
+static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
+{
+ int upto, todo;
+ int i, timeout = 100;
+ struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE;
+
+ set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
+ /* set the spi1 GPIO */
+ exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE);
+
+ /* set pktcnt and enable it */
+ writel(4 | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
+ /* set FB_CLK_SEL */
+ writel(SPI_FB_DELAY_180, ®s->fb_clk);
+ /* set CH_WIDTH and BUS_WIDTH as word */
+ setbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
+ SPI_MODE_BUS_WIDTH_WORD);
+ clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
+
+ /* clear rx and tx channel if set priveously */
+ clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
+
+ setbits_le32(®s->swap_cfg, SPI_RX_SWAP_EN |
+ SPI_RX_BYTE_SWAP |
+ SPI_RX_HWORD_SWAP);
+
+ /* do a soft reset */
+ setbits_le32(®s->ch_cfg, SPI_CH_RST);
+ clrbits_le32(®s->ch_cfg, SPI_CH_RST);
+
+ /* now set rx and tx channel ON */
+ setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
+ clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
+
+ /* Send read instruction (0x3h) followed by a 24 bit addr */
+ writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, ®s->tx_data);
+
+ /* waiting for TX done */
+ while (!(readl(®s->spi_sts) & SPI_ST_TX_DONE)) {
+ if (!timeout) {
+ debug("SPI TIMEOUT\n");
+ break;
+ }
+ timeout--;
+ }
+
+ for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
+ todo = min(uboot_size - upto, (unsigned int)(1 << 15));
+ spi_rx_tx(regs, todo, (void *)(uboot_addr),
+ (void *)(SPI_FLASH_UBOOT_POS), i);
+ }
+
+ setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
+
+ /*
+ * Let put controller mode to BYTE as
+ * SPI driver does not support WORD mode yet
+ */
+ clrbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
+ SPI_MODE_BUS_WIDTH_WORD);
+ writel(0, ®s->swap_cfg);
+
+ /*
+ * Flush spi tx, rx fifos and reset the SPI controller
+ * and clear rx/tx channel
+ */
+ clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
+ clrbits_le32(®s->ch_cfg, SPI_CH_RST);
+ clrbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
+}
+#endif
+
+/*
+* Copy U-boot from mmc to RAM:
+* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
+* Pointer to API (Data transfer from mmc to ram)
+*/
+void copy_uboot_to_ram(void)
+{
+ unsigned int bootmode = BOOT_MODE_OM;
+
+ u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
+ u32 offset = 0, size = 0;
+#ifdef CONFIG_SPI_BOOTING
+ struct spl_machine_param *param = spl_get_machine_params();
+#endif
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+ u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
+ void (*end_bootop_from_emmc)(void);
+#endif
+#ifdef CONFIG_USB_BOOTING
+ int is_cr_z_set;
+ unsigned int sec_boot_check;
+
+ /*
+ * Note that older hardware (before Exynos5800) does not expect any
+ * arguments, but it does not hurt to pass them, so a common function
+ * prototype is used.
+ */
+ u32 (*usb_copy)(u32 num_of_block, u32 *dst);
+
+ /* Read iRAM location to check for secondary USB boot mode */
+ sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
+ if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
+ bootmode = BOOT_MODE_USB;
+#endif
+
+ if (bootmode == BOOT_MODE_OM)
+ bootmode = get_boot_mode();
+
+ switch (bootmode) {
+#ifdef CONFIG_SPI_BOOTING
+ case BOOT_MODE_SERIAL:
+ /* Customised function to copy u-boot from SF */
+ exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE);
+ break;
+#endif
+ case BOOT_MODE_SD:
+ offset = BL2_START_OFFSET;
+ size = BL2_SIZE_BLOC_COUNT;
+ copy_bl2 = get_irom_func(MMC_INDEX);
+ break;
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+ case BOOT_MODE_EMMC:
+ /* Set the FSYS1 clock divisor value for EMMC boot */
+ emmc_boot_clk_div_set();
+
+ copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX);
+ end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX);
+
+ copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
+ end_bootop_from_emmc();
+ break;
+#endif
+#ifdef CONFIG_USB_BOOTING
+ case BOOT_MODE_USB:
+ /*
+ * iROM needs program flow prediction to be disabled
+ * before copy from USB device to RAM
+ */
+ is_cr_z_set = config_branch_prediction(0);
+ usb_copy = get_irom_func(USB_INDEX);
+ usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE);
+ config_branch_prediction(is_cr_z_set);
+ break;
+#endif
+ default:
+ break;
+ }
+
+ if (copy_bl2)
+ copy_bl2(offset, size, CONFIG_SYS_TEXT_BASE);
+}
+
+void memzero(void *s, size_t n)
+{
+ char *ptr = s;
+ size_t i;
+
+ for (i = 0; i < n; i++)
+ *ptr++ = '\0';
+}
+
+/**
+ * Set up the U-Boot global_data pointer
+ *
+ * This sets the address of the global data, and sets up basic values.
+ *
+ * @param gdp Value to give to gd
+ */
+static void setup_global_data(gd_t *gdp)
+{
+ gd = gdp;
+ memzero((void *)gd, sizeof(gd_t));
+ gd->flags |= GD_FLG_RELOC;
+ gd->baudrate = CONFIG_BAUDRATE;
+ gd->have_console = 1;
+}
+
+void board_init_f(unsigned long bootflag)
+{
+ __aligned(8) gd_t local_gd;
+ __attribute__((noreturn)) void (*uboot)(void);
+
+ setup_global_data(&local_gd);
+
+ if (do_lowlevel_init())
+ power_exit_wakeup();
+
+ copy_uboot_to_ram();
+
+ /* Jump to U-Boot image */
+ uboot = (void *)CONFIG_SYS_TEXT_BASE;
+ (*uboot)();
+ /* Never returns Here */
+}
+
+/* Place Holders */
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+ /* Function attribute is no-return */
+ /* This Function never executes */
+ while (1)
+ ;
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/system.h>
+
+static void exynos5_set_usbhost_mode(unsigned int mode)
+{
+ struct exynos5_sysreg *sysreg =
+ (struct exynos5_sysreg *)samsung_get_base_sysreg();
+
+ /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */
+ if (mode == USB20_PHY_CFG_HOST_LINK_EN) {
+ setbits_le32(&sysreg->usb20phy_cfg,
+ USB20_PHY_CFG_HOST_LINK_EN);
+ } else {
+ clrbits_le32(&sysreg->usb20phy_cfg,
+ USB20_PHY_CFG_HOST_LINK_EN);
+ }
+}
+
+void set_usbhost_mode(unsigned int mode)
+{
+ if (cpu_is_exynos5())
+ exynos5_set_usbhost_mode(mode);
+}
+
+static void exynos4_set_system_display(void)
+{
+ struct exynos4_sysreg *sysreg =
+ (struct exynos4_sysreg *)samsung_get_base_sysreg();
+ unsigned int cfg = 0;
+
+ /*
+ * system register path set
+ * 0: MIE/MDNIE
+ * 1: FIMD Bypass
+ */
+ cfg = readl(&sysreg->display_ctrl);
+ cfg |= (1 << 1);
+ writel(cfg, &sysreg->display_ctrl);
+}
+
+static void exynos5_set_system_display(void)
+{
+ struct exynos5_sysreg *sysreg =
+ (struct exynos5_sysreg *)samsung_get_base_sysreg();
+ unsigned int cfg = 0;
+
+ /*
+ * system register path set
+ * 0: MIE/MDNIE
+ * 1: FIMD Bypass
+ */
+ cfg = readl(&sysreg->disp1blk_cfg);
+ cfg |= (1 << 15);
+ writel(cfg, &sysreg->disp1blk_cfg);
+}
+
+void set_system_display_ctrl(void)
+{
+ if (cpu_is_exynos4())
+ exynos4_set_system_display();
+ else
+ exynos5_set_system_display();
+}
--- /dev/null
+/*
+ * Lowlevel setup for SMDK5250 board based on S5PC520
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/tzpc.h>
+#include <asm/io.h>
+
+/* Setting TZPC[TrustZone Protection Controller] */
+void tzpc_init(void)
+{
+ struct exynos_tzpc *tzpc;
+ unsigned int addr, start = 0, end = 0;
+
+ start = samsung_get_base_tzpc();
+
+ if (cpu_is_exynos5())
+ end = start + ((EXYNOS5_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET);
+ else if (cpu_is_exynos4())
+ end = start + ((EXYNOS4_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET);
+
+ for (addr = start; addr <= end; addr += TZPC_BASE_OFFSET) {
+ tzpc = (struct exynos_tzpc *)addr;
+
+ if (addr == start)
+ writel(R0SIZE, &tzpc->r0size);
+
+ writel(DECPROTXSET, &tzpc->decprot0set);
+ writel(DECPROTXSET, &tzpc->decprot1set);
+
+ if (cpu_is_exynos5() && (addr == end))
+ break;
+
+ writel(DECPROTXSET, &tzpc->decprot2set);
+ writel(DECPROTXSET, &tzpc->decprot3set);
+ }
+}
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch-exynos/spi.h>
+#include <asm/arch/spi.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
projects / u-boot / commitdiff