/* mr1 for ddr3 */
#define DDR3_DLL_DISABLE 1
-/*
- *TODO(sjg@chromium.org): We use a PMU register to store SDRAM information for
- * passing from SPL to U-Boot. It would probably be better to use a normal C
- * structure in SRAM.
- *
- * sys_reg bitfield struct
- * [31] row_3_4_ch1
- * [30] row_3_4_ch0
- * [29:28] chinfo
- * [27] rank_ch1
- * [26:25] col_ch1
- * [24] bk_ch1
- * [23:22] cs0_row_ch1
- * [21:20] cs1_row_ch1
- * [19:18] bw_ch1
- * [17:16] dbw_ch1;
- * [15:13] ddrtype
- * [12] channelnum
- * [11] rank_ch0
- * [10:9] col_ch0
- * [8] bk_ch0
- * [7:6] cs0_row_ch0
- * [5:4] cs1_row_ch0
- * [3:2] bw_ch0
- * [1:0] dbw_ch0
-*/
-#define SYS_REG_DDRTYPE_SHIFT 13
-#define SYS_REG_DDRTYPE_MASK 7
-#define SYS_REG_NUM_CH_SHIFT 12
-#define SYS_REG_NUM_CH_MASK 1
-#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
-#define SYS_REG_ROW_3_4_MASK 1
-#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
-#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
-#define SYS_REG_RANK_MASK 1
-#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
-#define SYS_REG_COL_MASK 3
-#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
-#define SYS_REG_BK_MASK 1
-#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
-#define SYS_REG_CS0_ROW_MASK 3
-#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
-#define SYS_REG_CS1_ROW_MASK 3
-#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
-#define SYS_REG_BW_MASK 3
-#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
-#define SYS_REG_DBW_MASK 3
-
#endif
return 0;
}
+#if !CONFIG_IS_ENABLED(RAM)
+/*
+ * When CONFIG_RAM is enabled, the dram_init() function is implemented
+ * in sdram_common.c.
+ */
int dram_init(void)
{
gd->ram_size = sdram_size();
return 0;
}
+#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
#endif
}
-int dram_init(void)
-{
- struct ram_info ram;
- struct udevice *dev;
- int ret;
-
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- debug("DRAM init failed: %d\n", ret);
- return ret;
- }
- ret = ram_get_info(dev, &ram);
- if (ret) {
- debug("Cannot get DRAM size: %d\n", ret);
- return ret;
- }
- debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
- gd->ram_size = ram.size;
-
- return 0;
-}
-
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
#include <asm/arch/grf_rk3188.h>
#include <asm/arch/pmu_rk3188.h>
#include <asm/arch/sdram.h>
+#include <asm/arch/sdram_common.h>
#include <linux/err.h>
DECLARE_GLOBAL_DATA_PTR;
printf("DRAM init failed!\n");
hang();
}
-#endif /* CONFIG_SPL_BUILD */
-
-size_t sdram_size_mb(struct rk3188_pmu *pmu)
-{
- u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
- size_t chipsize_mb = 0;
- size_t size_mb = 0;
- u32 ch;
- u32 sys_reg = readl(&pmu->sys_reg[2]);
- u32 chans;
-
- chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK);
-
- for (ch = 0; ch < chans; ch++) {
- rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
- SYS_REG_RANK_MASK);
- col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
- bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
- cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
- SYS_REG_CS0_ROW_MASK);
- cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
- SYS_REG_CS1_ROW_MASK);
- bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
- SYS_REG_BW_MASK));
- row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
- SYS_REG_ROW_3_4_MASK;
- chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
-
- if (rank > 1)
- chipsize_mb += chipsize_mb >>
- (cs0_row - cs1_row);
- if (row_3_4)
- chipsize_mb = chipsize_mb * 3 / 4;
- size_mb += chipsize_mb;
- }
-
- /* there can be no more than 2gb of memory */
- size_mb = min(size_mb, 0x80000000 >> 20);
-
- return size_mb;
-}
-#ifdef CONFIG_SPL_BUILD
static int setup_sdram(struct udevice *dev)
{
struct dram_info *priv = dev_get_priv(dev);
{
#ifdef CONFIG_SPL_BUILD
struct rk3188_sdram_params *plat = dev_get_platdata(dev);
-#endif
- struct dram_info *priv = dev_get_priv(dev);
struct regmap *map;
- int ret;
struct udevice *dev_clk;
+ int ret;
+#endif
+ struct dram_info *priv = dev_get_priv(dev);
+
+ priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
+#ifdef CONFIG_SPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
ret = conv_of_platdata(dev);
if (ret)
priv->chan[0].msch = regmap_get_range(map, 0);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
-#ifdef CONFIG_SPL_BUILD
priv->chan[0].pctl = regmap_get_range(plat->map, 0);
priv->chan[0].publ = regmap_get_range(plat->map, 1);
-#endif
ret = rockchip_get_clk(&dev_clk);
if (ret)
priv->cru = rockchip_get_cru();
if (IS_ERR(priv->cru))
return PTR_ERR(priv->cru);
-#ifdef CONFIG_SPL_BUILD
ret = setup_sdram(dev);
if (ret)
return ret;
-#endif
+#else
priv->info.base = CONFIG_SYS_SDRAM_BASE;
- priv->info.size = sdram_size_mb(priv->pmu) << 20;
+ priv->info.size = rockchip_sdram_size(
+ (phys_addr_t)&priv->pmu->sys_reg[2]);
+#endif
return 0;
}
#endif
}
-int dram_init(void)
-{
- struct ram_info ram;
- struct udevice *dev;
- int ret;
-
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- debug("DRAM init failed: %d\n", ret);
- return ret;
- }
- ret = ram_get_info(dev, &ram);
- if (ret) {
- debug("Cannot get DRAM size: %d\n", ret);
- return ret;
- }
- debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
- gd->ram_size = ram.size;
-
- return 0;
-}
-
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
#include <asm/arch/grf_rk3288.h>
#include <asm/arch/pmu_rk3288.h>
#include <asm/arch/sdram.h>
+#include <asm/arch/sdram_common.h>
#include <linux/err.h>
#include <power/regulator.h>
#include <power/rk8xx_pmic.h>
printf("DRAM init failed!\n");
hang();
}
-#endif /* CONFIG_SPL_BUILD */
-
-size_t sdram_size_mb(struct rk3288_pmu *pmu)
-{
- u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
- size_t chipsize_mb = 0;
- size_t size_mb = 0;
- u32 ch;
- u32 sys_reg = readl(&pmu->sys_reg[2]);
- u32 chans;
-
- chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK);
-
- for (ch = 0; ch < chans; ch++) {
- rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
- SYS_REG_RANK_MASK);
- col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
- bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
- cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
- SYS_REG_CS0_ROW_MASK);
- cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
- SYS_REG_CS1_ROW_MASK);
- bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
- SYS_REG_BW_MASK));
- row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
- SYS_REG_ROW_3_4_MASK;
- chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
-
- if (rank > 1)
- chipsize_mb += chipsize_mb >>
- (cs0_row - cs1_row);
- if (row_3_4)
- chipsize_mb = chipsize_mb * 3 / 4;
- size_mb += chipsize_mb;
- }
-
- /*
- * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
- * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
- * inaccessible for some IP controller.
- */
- size_mb = min(size_mb, 0xfe000000 >> 20);
- return size_mb;
-}
-
-#ifdef CONFIG_SPL_BUILD
# ifdef CONFIG_ROCKCHIP_FAST_SPL
static int veyron_init(struct dram_info *priv)
{
{
#ifdef CONFIG_SPL_BUILD
struct rk3288_sdram_params *plat = dev_get_platdata(dev);
-#endif
- struct dram_info *priv = dev_get_priv(dev);
+ struct udevice *dev_clk;
struct regmap *map;
int ret;
- struct udevice *dev_clk;
+#endif
+ struct dram_info *priv = dev_get_priv(dev);
+ priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
+#ifdef CONFIG_SPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
ret = conv_of_platdata(dev);
if (ret)
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
priv->sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
- priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
-#ifdef CONFIG_SPL_BUILD
priv->chan[0].pctl = regmap_get_range(plat->map, 0);
priv->chan[0].publ = regmap_get_range(plat->map, 1);
priv->chan[1].pctl = regmap_get_range(plat->map, 2);
priv->chan[1].publ = regmap_get_range(plat->map, 3);
-#endif
+
ret = rockchip_get_clk(&dev_clk);
if (ret)
return ret;
priv->cru = rockchip_get_cru();
if (IS_ERR(priv->cru))
return PTR_ERR(priv->cru);
-#ifdef CONFIG_SPL_BUILD
ret = setup_sdram(dev);
if (ret)
return ret;
+#else
+ priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.size = rockchip_sdram_size(
+ (phys_addr_t)&priv->pmu->sys_reg[2]);
#endif
- priv->info.base = 0;
- priv->info.size = sdram_size_mb(priv->pmu) << 20;
return 0;
}
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
+#include <asm/arch/sdram_common.h>
#include <asm/arch/sdram_rk3399.h>
#include <asm/arch/cru_rk3399.h>
#include <asm/arch/grf_rk3399.h>
struct rk3399_pmugrf_regs *pmugrf;
};
-/*
- * sys_reg bitfield struct
- * [31] row_3_4_ch1
- * [30] row_3_4_ch0
- * [29:28] chinfo
- * [27] rank_ch1
- * [26:25] col_ch1
- * [24] bk_ch1
- * [23:22] cs0_row_ch1
- * [21:20] cs1_row_ch1
- * [19:18] bw_ch1
- * [17:16] dbw_ch1;
- * [15:13] ddrtype
- * [12] channelnum
- * [11] rank_ch0
- * [10:9] col_ch0
- * [8] bk_ch0
- * [7:6] cs0_row_ch0
- * [5:4] cs1_row_ch0
- * [3:2] bw_ch0
- * [1:0] dbw_ch0
-*/
-#define SYS_REG_DDRTYPE_SHIFT 13
-#define SYS_REG_DDRTYPE_MASK 7
-#define SYS_REG_NUM_CH_SHIFT 12
-#define SYS_REG_NUM_CH_MASK 1
-#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
-#define SYS_REG_ROW_3_4_MASK 1
-#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
-#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
-#define SYS_REG_RANK_MASK 1
-#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
-#define SYS_REG_COL_MASK 3
-#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
-#define SYS_REG_BK_MASK 1
-#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
-#define SYS_REG_CS0_ROW_MASK 3
-#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
-#define SYS_REG_CS1_ROW_MASK 3
-#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
-#define SYS_REG_BW_MASK 3
-#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
-#define SYS_REG_DBW_MASK 3
-
#define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6))
#define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7))
#define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8))
}
#endif
-size_t sdram_size_mb(struct dram_info *dram)
-{
- u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
- size_t chipsize_mb = 0;
- size_t size_mb = 0;
- u32 ch;
-
- u32 sys_reg = readl(&dram->pmugrf->os_reg2);
- u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT)
- & SYS_REG_NUM_CH_MASK);
-
- for (ch = 0; ch < ch_num; ch++) {
- rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
- SYS_REG_RANK_MASK);
- col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
- bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
- cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
- SYS_REG_CS0_ROW_MASK);
- cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
- SYS_REG_CS1_ROW_MASK);
- bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
- SYS_REG_BW_MASK));
- row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
- SYS_REG_ROW_3_4_MASK;
-
- chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
-
- if (rank > 1)
- chipsize_mb += chipsize_mb >> (cs0_row - cs1_row);
- if (row_3_4)
- chipsize_mb = chipsize_mb * 3 / 4;
- size_mb += chipsize_mb;
- }
-
- /*
- * we use the 0x00000000~0xf7ffffff space
- * since 0xf8000000~0xffffffff is soc register space
- * so we reserve it
- */
- size_mb = min_t(size_t, size_mb, 0xf8000000/(1<<20));
-
- return size_mb;
-}
-
static int rk3399_dmc_probe(struct udevice *dev)
{
#ifdef CONFIG_SPL_BUILD
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
- priv->info.base = 0;
- priv->info.size = sdram_size_mb(priv) << 20;
+ priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.size = rockchip_sdram_size(
+ (phys_addr_t)&priv->pmugrf->os_reg2);
#endif
return 0;
}
return 0;
}
-int dram_init(void)
-{
- gd->ram_size = 0x80000000;
- return 0;
-}
-
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = 0;
return 0;
}
-int dram_init(void)
-{
- gd->ram_size = 0x40000000;
-
- return 0;
-}
-
int dram_init_banksize(void)
{
/* Reserve 0x200000 for ATF bl31 */
return 0;
}
-int dram_init(void)
-{
- gd->ram_size = 0x80000000;
- return 0;
-}
-
int dram_init_banksize(void)
{
/* Reserve 0x200000 for ATF bl31 */
return 0;
}
-int dram_init(void)
-{
- struct ram_info ram;
- struct udevice *dev;
- int ret;
-
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- debug("DRAM init failed: %d\n", ret);
- return ret;
- }
- ret = ram_get_info(dev, &ram);
- if (ret) {
- debug("Cannot get DRAM size: %d\n", ret);
- return ret;
- }
- debug("SDRAM base=%llx, size=%x\n", ram.base, (unsigned int)ram.size);
- gd->ram_size = ram.size;
-
- return 0;
-}
-
int dram_init_banksize(void)
{
/* Reserve 0x200000 for ATF bl31 */
return 0;
}
-int dram_init(void)
-{
- gd->ram_size = 0x80000000;
-
- return 0;
-}
-
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = 0x200000;
}
#endif
-int dram_init(void)
-{
- struct ram_info ram;
- struct udevice *dev;
- int ret;
-
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- debug("DRAM init failed: %d\n", ret);
- return ret;
- }
- ret = ram_get_info(dev, &ram);
- if (ret) {
- debug("Cannot get DRAM size: %d\n", ret);
- return ret;
- }
- debug("SDRAM base=%llx, size=%x\n", ram.base, (unsigned int)ram.size);
- gd->ram_size = ram.size;
-
- return 0;
-}
-
int dram_init_banksize(void)
{
/* Reserve 0x200000 for ATF bl31 */
projects / u-boot / commitdiff