fix: phy: marvell: cp110: sfi: update analog parameters according to latest ETP

Add SFI analog parameters initialization values according to
latest ETP.

Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 8ea5df22d896ee48de261e8e00175e7edbc0ad04..21de90c3a1dbbf4d23816110be7669f9ba240100 100644 (file)
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -1166,8 +1166,11 @@ static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base,
                data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET;
                mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK;
                data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET;
-               reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask);
+       } else {
+               mask = HPIPE_TXDIGCK_DIV_FORCE_MASK;
+               data = 0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET;
        }
+       reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask);
 
        /* Set analog paramters from ETP(HW) */
        debug("stage: Analog paramters from ETP(HW)\n");
@@ -1213,13 +1216,27 @@ static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base,
        data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET;
        reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask);
        /* 0xE-G1_Setting_1 */
-       mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
-       data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
-       mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
-       data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
-       mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
-       data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
+       mask = HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
+       data = 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
+       if (speed == PHY_SPEED_5_15625G) {
+               mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
+               data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
+               mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
+               data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+       } else {
+               mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
+               data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
+               mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
+               data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+               mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
+               data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
+               mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
+               data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET;
+               mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK;
+               data |= 0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET;
+       }
        reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
+
        /* 0xA-DFE_Reg3 */
        mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
        data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
@@ -1245,6 +1262,63 @@ static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base,
        }
        reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
 
+       /* Connfigure RX training timer */
+       mask = HPIPE_RX_TRAIN_TIMER_MASK;
+       data = 0x13 << HPIPE_RX_TRAIN_TIMER_OFFSET;
+       reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask);
+
+       /* Enable TX train peak to peak hold */
+       mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK;
+       data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET;
+       reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask);
+
+       /* Configure TX preset index */
+       mask = HPIPE_TX_PRESET_INDEX_MASK;
+       data = 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET;
+       reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask);
+
+       /* Disable pattern lock lost timeout */
+       mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK;
+       data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET;
+       reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
+
+       /* Configure TX training pattern and TX training 16bit auto */
+       mask = HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK;
+       data = 0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET;
+       mask |= HPIPE_TX_TRAIN_PAT_SEL_MASK;
+       data |= 0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET;
+       reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask);
+
+       /* Configure Training patten number */
+       mask = HPIPE_TRAIN_PAT_NUM_MASK;
+       data = 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET;
+       reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask);
+
+       /* Configure differencial manchester encoter to ethernet mode */
+       mask = HPIPE_DME_ETHERNET_MODE_MASK;
+       data = 0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET;
+       reg_set(hpipe_addr + HPIPE_DME_REG, data, mask);
+
+       /* Configure VDD Continuous Calibration */
+       mask = HPIPE_CAL_VDD_CONT_MODE_MASK;
+       data = 0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET;
+       reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask);
+
+       /* Trigger sampler enable pulse (by toggleing the bit) */
+       mask = HPIPE_RX_SAMPLER_OS_GAIN_MASK;
+       data = 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET;
+       mask |= HPIPE_SMAPLER_MASK;
+       data |= 0x1 << HPIPE_SMAPLER_OFFSET;
+       reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
+       mask = HPIPE_SMAPLER_MASK;
+       data = 0x0 << HPIPE_SMAPLER_OFFSET;
+       reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
+
+       /* Set External RX Regulator Control */
+       mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
+       data = 0x1A << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
+       reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
+
        debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
        /* SERDES External Configuration */
        mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;

diff --git a/drivers/phy/marvell/comphy_hpipe.h b/drivers/phy/marvell/comphy_hpipe.h
index 1e294fb8c02e28f28d3710562b3ca229300a285e..5edd0adf6cf99366c83bbf6f68e86239d92b6429 100644 (file)
--- a/drivers/phy/marvell/comphy_hpipe.h
+++ b/drivers/phy/marvell/comphy_hpipe.h
@@ -254,6 +254,11 @@
 #define HPIPE_EXT_SELLV_RXSAMPL_MASK           \
        (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)
 
+#define HPIPE_VDD_CAL_0_REG                    0x108
+#define HPIPE_CAL_VDD_CONT_MODE_OFFSET         15
+#define HPIPE_CAL_VDD_CONT_MODE_MASK           \
+       (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET)
+
 #define HPIPE_PCIE_REG0                         0x120
 #define HPIPE_PCIE_IDLE_SYNC_OFFSET            12
 #define HPIPE_PCIE_IDLE_SYNC_MASK              \
@@ -301,6 +306,9 @@
        (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
 
 #define HPIPE_SPD_DIV_FORCE_REG                                0x154
+#define HPIPE_TXDIGCK_DIV_FORCE_OFFSET                 7
+#define HPIPE_TXDIGCK_DIV_FORCE_MASK                   \
+       (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET)
 #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET          8
 #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK            \
        (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET)
@@ -317,6 +325,9 @@
 #define HPIPE_PLLINTP_REG1                     0x150
 
 #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG    0x16C
+#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET                6
+#define HPIPE_RX_SAMPLER_OS_GAIN_MASK          \
+       (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET)
 #define HPIPE_SMAPLER_OFFSET                   12
 #define HPIPE_SMAPLER_MASK                     \
        (0x1 << HPIPE_SMAPLER_OFFSET)
@@ -363,6 +374,21 @@
 #define HPIPE_OS_PH_VALID_MASK                 \
        (0x1 << HPIPE_OS_PH_VALID_OFFSET)
 
+#define HPIPE_FRAME_DETECT_CTRL_0_REG                  0x214
+#define HPIPE_TRAIN_PAT_NUM_OFFSET                     0x7
+#define HPIPE_TRAIN_PAT_NUM_MASK                       \
+       (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET)
+
+#define HPIPE_FRAME_DETECT_CTRL_3_REG                  0x220
+#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET      12
+#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK                \
+       (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET)
+
+#define HPIPE_DME_REG                                  0x228
+#define HPIPE_DME_ETHERNET_MODE_OFFSET                 7
+#define HPIPE_DME_ETHERNET_MODE_MASK                   \
+       (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET)
+
 #define HPIPE_TX_TRAIN_CTRL_0_REG              0x268
 #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET         15
 #define HPIPE_TX_TRAIN_P2P_HOLD_MASK           \
@@ -388,6 +414,9 @@
 #define HPIPE_PCIE_REG3                                0x290
 
 #define HPIPE_TX_TRAIN_CTRL_5_REG              0x2A4
+#define HPIPE_RX_TRAIN_TIMER_OFFSET            0
+#define HPIPE_RX_TRAIN_TIMER_MASK              \
+       (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET)
 #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET      11
 #define HPIPE_TX_TRAIN_START_SQ_EN_MASK                \
        (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
@@ -408,6 +437,12 @@
 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7
 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK   \
        (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
+#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET    8
+#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK      \
+       (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET)
+#define HPIPE_TX_TRAIN_PAT_SEL_OFFSET          9
+#define HPIPE_TX_TRAIN_PAT_SEL_MASK            \
+       (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)
 
 #define HPIPE_TX_TRAIN_CTRL_11_REG             0x438
 #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET      6
@@ -470,6 +505,11 @@
 #define HPIPE_G3_DFE_RES_MASK                  \
        (0x3 << HPIPE_G3_DFE_RES_OFFSET)
 
+#define HPIPE_TX_PRESET_INDEX_REG              0x468
+#define HPIPE_TX_PRESET_INDEX_OFFSET           0
+#define HPIPE_TX_PRESET_INDEX_MASK             \
+       (0xf << HPIPE_TX_PRESET_INDEX_OFFSET)
+
 #define HPIPE_DFE_CTRL_28_REG                  0x49C
 #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET         7
 #define HPIPE_DFE_CTRL_28_PIPE4_MASK           \