default 64 if SYS_CACHE_SHIFT_6
default 32 if SYS_CACHE_SHIFT_5
+config SYS_ARCH_TIMER
+ bool "ARM Generic Timer support"
+ depends on CPU_V7 || ARM64
+ default y if ARM64
+ help
+ The ARM Generic Timer (aka arch-timer) provides an architected
+ interface to a timer source on an SoC.
+ It is mandantory for ARMv8 implementation and widely available
+ on ARMv7 systems.
+
config ARM_SMCCC
bool "Support for ARM SMC Calling Convention (SMCCC)"
depends on CPU_V7 || ARM64
select SUPPORT_SPL
select SYS_THUMB_BUILD
select CMD_POWEROFF
+ select SYS_ARCH_TIMER
imply CMD_MTDPARTS
imply FIT
imply CMD_SAVES
obj-y += cpu.o
ifndef CONFIG_$(SPL_TPL_)TIMER
-obj-y += generic_timer.o
+obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o
endif
obj-y += cache_v8.o
obj-y += exceptions.o
config TARGET_MX7ULP_EVK
bool "Support mx7ulp EVK board"
+ select SYS_ARCH_TIMER
endchoice
depends on ARCH_QEMU
select CPU_V7
select ARCH_SUPPORT_PSCI
+ select SYS_ARCH_TIMER
config TARGET_QEMU_ARM_64BIT
bool "Support qemu_arm64"
select CPU_V7
select PINCTRL_STM32
select STM32_RESET
+ select SYS_ARCH_TIMER
select SYSRESET_SYSCON
help
target STMicroelectronics SOC STM32MP1 family
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG1_RBASE
-#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
#define CONFIG_INITRD_TAG
#define CONFIG_SYS_MALLOC_LEN SZ_16M
/* For timer, QEMU emulates an ARMv7/ARMv8 architected timer */
-#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SYS_HZ 1000
/* For block devices, QEMU emulates an ICH9 AHCI controller over PCI */
* Number of clock ticks in 1 sec
*/
#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_ARCH_TIMER
/*
* malloc() pool size
/* SoC Configuration */
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SPL_TARGET "u-boot-spi.gph"
#define CONFIG_SYS_DCACHE_OFF
CONFIG_SYS_APP1_SIZE
CONFIG_SYS_APP2_BASE
CONFIG_SYS_APP2_SIZE
-CONFIG_SYS_ARCH_TIMER
CONFIG_SYS_ARM_CACHE_WRITETHROUGH
CONFIG_SYS_AT91_CPU_NAME
CONFIG_SYS_AT91_MAIN_CLOCK