ARM FREESCALE IMX
M: Stefano Babic <sbabic@denx.de>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-imx.git
F: arch/arm/cpu/arm1136/mx*/
VERSION = 2017
PATCHLEVEL = 07
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
NAME =
# *DOCUMENTATION*
select OF_BOARD_SETUP
select OF_CONTROL
select OF_SEPARATE
- select SPL_STACK_R if SUPPORT_SPL
- select SPL_SYS_MALLOC_SIMPLE if SUPPORT_SPL
+ select SPL_STACK_R if SPL
+ select SPL_SYS_MALLOC_SIMPLE if SPL
select SYS_NS16550
select SPL_SYS_THUMB_BUILD if !ARM64
select USB if DISTRO_DEFAULTS
}
}
+#ifdef CONFIG_MACH_SUN8I_R40
+/* secondary core entry address is programmed differently on R40 */
+static void __secure sunxi_set_entry_address(void *entry)
+{
+ writel((u32)entry,
+ SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
+}
+#else
+static void __secure sunxi_set_entry_address(void *entry)
+{
+ struct sunxi_cpucfg_reg *cpucfg =
+ (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+
+ writel((u32)entry, &cpucfg->priv0);
+}
+#endif
+
#ifdef CONFIG_MACH_SUN7I
/* sun7i (A20) is different from other single cluster SoCs */
static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool on)
psci_save_target_pc(cpu, pc);
/* Set secondary core power on PC */
-#ifdef CONFIG_MACH_SUN8I_R40
- /* secondary core entry address is programmed differently */
- writel((u32)&psci_cpu_entry,
- SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
-#else
- writel((u32)&psci_cpu_entry, &cpucfg->priv0);
-#endif
+ sunxi_set_entry_address(&psci_cpu_entry);
/* Assert reset on target CPU */
writel(0, &cpucfg->cpu[cpu].rst);
sun8i-h3-orangepi-plus.dtb \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-h3-nanopi-m1.dtb \
+ sun8i-h3-nanopi-m1-plus.dtb \
sun8i-h3-nanopi-neo.dtb \
sun8i-h3-nanopi-neo-air.dtb
dtb-$(CONFIG_MACH_SUN8I_R40) += \
dtb-$(CONFIG_MACH_SUN8I_V3S) += \
sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \
+ sun50i-h5-nanopi-neo2.dtb \
sun50i-h5-orangepi-pc2.dtb \
- sun50i-h5-orangepi-prime.dtb
+ sun50i-h5-orangepi-prime.dtb \
+ sun50i-h5-orangepi-zero-plus2.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-bananapi-m64.dtb \
+ sun50i-a64-orangepi-win.dtb \
sun50i-a64-pine64-plus.dtb \
sun50i-a64-pine64.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \
logicpd-torpedo-37xx-devkit.dtb \
- logicpd-som-lv-37xx-devkit.dts
+ logicpd-som-lv-37xx-devkit.dtb
dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
at91-sama5d2_xplained.dtb
--- /dev/null
+/*
+ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "OrangePi Win/Win Plus";
+ compatible = "xunlong,orangepi-win", "allwinner,sun50i-a64";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "FriendlyARM NanoPi NEO 2";
+ compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&mmc0 {
+ compatible = "allwinner,sun50i-h5-mmc",
+ "allwinner,sun50i-a64-mmc",
+ "allwinner,sun5i-a13-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+
+/ {
+ model = "OrangePi Zero Plus2";
+ compatible = "xunlong,orangepi-zero-plus2", "allwinner,sun50i-h5";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&mmc0 {
+ compatible = "allwinner,sun50i-h5-mmc",
+ "allwinner,sun50i-a64-mmc",
+ "allwinner,sun5i-a13-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun8i-h3-nanopi.dtsi"
+
+/ {
+ model = "FriendlyArm NanoPi M1 Plus";
+ compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
#include <asm/arch/dram_sun8i_a33.h>
#elif defined(CONFIG_MACH_SUN8I_A83T)
#include <asm/arch/dram_sun8i_a83t.h>
-#elif defined(CONFIG_MACH_SUNXI_H3_H5) || \
- defined(CONFIG_MACH_SUN8I_R40) || \
- defined(CONFIG_MACH_SUN50I)
-#include <asm/arch/dram_sun8i_h3.h>
+#elif defined(CONFIG_SUNXI_DRAM_DW)
+#include <asm/arch/dram_sunxi_dw.h>
#elif defined(CONFIG_MACH_SUN9I)
#include <asm/arch/dram_sun9i.h>
#else
+++ /dev/null
-/*
- * sun8i H3 platform dram controller register and constant defines
- *
- * (C) Copyright 2007-2015 Allwinner Technology Co.
- * Jerry Wang <wangflord@allwinnertech.com>
- * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
- * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
- * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SUNXI_DRAM_SUN8I_H3_H
-#define _SUNXI_DRAM_SUN8I_H3_H
-
-struct sunxi_mctl_com_reg {
- u32 cr; /* 0x00 control register */
- u32 cr_r1; /* 0x04 rank 1 control register (R40 only) */
- u8 res0[0x4]; /* 0x08 */
- u32 tmr; /* 0x0c (unused on H3) */
- u32 mcr[16][2]; /* 0x10 */
- u32 bwcr; /* 0x90 bandwidth control register */
- u32 maer; /* 0x94 master enable register */
- u32 mapr; /* 0x98 master priority register */
- u32 mcgcr; /* 0x9c */
- u32 cpu_bwcr; /* 0xa0 */
- u32 gpu_bwcr; /* 0xa4 */
- u32 ve_bwcr; /* 0xa8 */
- u32 disp_bwcr; /* 0xac */
- u32 other_bwcr; /* 0xb0 */
- u32 total_bwcr; /* 0xb4 */
- u8 res1[0x8]; /* 0xb8 */
- u32 swonr; /* 0xc0 */
- u32 swoffr; /* 0xc4 */
- u8 res2[0x8]; /* 0xc8 */
- u32 cccr; /* 0xd0 */
- u8 res3[0x54]; /* 0xd4 */
- u32 mdfs_bwlr[3]; /* 0x128 (unused on H3) */
- u8 res4[0x6cc]; /* 0x134 */
- u32 protect; /* 0x800 */
-};
-
-#define MCTL_CR_BL8 (0x4 << 20)
-
-#define MCTL_CR_1T (0x1 << 19)
-#define MCTL_CR_2T (0x0 << 19)
-
-#define MCTL_CR_LPDDR3 (0x7 << 16)
-#define MCTL_CR_LPDDR2 (0x6 << 16)
-#define MCTL_CR_DDR3 (0x3 << 16)
-#define MCTL_CR_DDR2 (0x2 << 16)
-
-#define MCTL_CR_SEQUENTIAL (0x1 << 15)
-#define MCTL_CR_INTERLEAVED (0x0 << 15)
-
-#define MCTL_CR_32BIT (0x1 << 12)
-#define MCTL_CR_16BIT (0x0 << 12)
-#define MCTL_CR_BUS_WIDTH(x) ((x) == 32 ? MCTL_CR_32BIT : MCTL_CR_16BIT)
-
-#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8)
-#define MCTL_CR_ROW_BITS(x) (((x) - 1) << 4)
-#define MCTL_CR_EIGHT_BANKS (0x1 << 2)
-#define MCTL_CR_FOUR_BANKS (0x0 << 2)
-#define MCTL_CR_DUAL_RANK (0x1 << 0)
-#define MCTL_CR_SINGLE_RANK (0x0 << 0)
-
-/*
- * CR_R1 is a register found in the R40's DRAM controller. It sets various
- * parameters for rank 1. Bits [11:0] have the same meaning as the bits in
- * MCTL_CR, but they apply to rank 1 only. This implies we can have
- * different chips for rank 1 than rank 0.
- *
- * As address line A15 and CS1 chip select for rank 1 are muxed on the same
- * pin, if single rank is used, A15 must be muxed in.
- */
-#define MCTL_CR_R1_MUX_A15 (0x1 << 21)
-
-#define PROTECT_MAGIC (0x94be6fa3)
-
-struct sunxi_mctl_ctl_reg {
- u32 pir; /* 0x00 PHY initialization register */
- u32 pwrctl; /* 0x04 */
- u32 mrctrl; /* 0x08 */
- u32 clken; /* 0x0c */
- u32 pgsr[2]; /* 0x10 PHY general status registers */
- u32 statr; /* 0x18 */
- u8 res1[0x10]; /* 0x1c */
- u32 lp3mr11; /* 0x2c */
- u32 mr[4]; /* 0x30 mode registers */
- u32 pllgcr; /* 0x40 */
- u32 ptr[5]; /* 0x44 PHY timing registers */
- u32 dramtmg[9]; /* 0x58 DRAM timing registers */
- u32 odtcfg; /* 0x7c */
- u32 pitmg[2]; /* 0x80 PHY interface timing registers */
- u8 res2[0x4]; /* 0x88 */
- u32 rfshctl0; /* 0x8c */
- u32 rfshtmg; /* 0x90 refresh timing */
- u32 rfshctl1; /* 0x94 */
- u32 pwrtmg; /* 0x98 */
- u8 res3[0x1c]; /* 0x9c */
- u32 vtfcr; /* 0xb8 (unused on H3) */
- u32 dqsgmr; /* 0xbc */
- u32 dtcr; /* 0xc0 */
- u32 dtar[4]; /* 0xc4 */
- u32 dtdr[2]; /* 0xd4 */
- u32 dtmr[2]; /* 0xdc */
- u32 dtbmr; /* 0xe4 */
- u32 catr[2]; /* 0xe8 */
- u32 dtedr[2]; /* 0xf0 */
- u8 res4[0x8]; /* 0xf8 */
- u32 pgcr[4]; /* 0x100 PHY general configuration registers */
- u32 iovcr[2]; /* 0x110 */
- u32 dqsdr; /* 0x118 */
- u32 dxccr; /* 0x11c */
- u32 odtmap; /* 0x120 */
- u32 zqctl[2]; /* 0x124 */
- u8 res6[0x14]; /* 0x12c */
- u32 zqcr; /* 0x140 ZQ control register */
- u32 zqsr; /* 0x144 ZQ status register */
- u32 zqdr[3]; /* 0x148 ZQ data registers */
- u8 res7[0x6c]; /* 0x154 */
- u32 sched; /* 0x1c0 */
- u32 perfhpr[2]; /* 0x1c4 */
- u32 perflpr[2]; /* 0x1cc */
- u32 perfwr[2]; /* 0x1d4 */
- u8 res8[0x24]; /* 0x1dc */
- u32 acmdlr; /* 0x200 AC master delay line register */
- u32 aclcdlr; /* 0x204 AC local calibrated delay line register */
- u32 aciocr; /* 0x208 AC I/O configuration register */
- u8 res9[0x4]; /* 0x20c */
- u32 acbdlr[31]; /* 0x210 AC bit delay line registers */
- u8 res10[0x74]; /* 0x28c */
- struct { /* 0x300 DATX8 modules*/
- u32 mdlr; /* 0x00 master delay line register */
- u32 lcdlr[3]; /* 0x04 local calibrated delay line registers */
- u32 bdlr[11]; /* 0x10 bit delay line registers */
- u32 sdlr; /* 0x3c output enable bit delay registers */
- u32 gtr; /* 0x40 general timing register */
- u32 gcr; /* 0x44 general configuration register */
- u32 gsr[3]; /* 0x48 general status registers */
- u8 res0[0x2c]; /* 0x54 */
- } dx[4];
- u8 res11[0x388]; /* 0x500 */
- u32 upd2; /* 0x888 */
-};
-
-#define PTR3_TDINIT1(x) ((x) << 20)
-#define PTR3_TDINIT0(x) ((x) << 0)
-
-#define PTR4_TDINIT3(x) ((x) << 20)
-#define PTR4_TDINIT2(x) ((x) << 0)
-
-#define DRAMTMG0_TWTP(x) ((x) << 24)
-#define DRAMTMG0_TFAW(x) ((x) << 16)
-#define DRAMTMG0_TRAS_MAX(x) ((x) << 8)
-#define DRAMTMG0_TRAS(x) ((x) << 0)
-
-#define DRAMTMG1_TXP(x) ((x) << 16)
-#define DRAMTMG1_TRTP(x) ((x) << 8)
-#define DRAMTMG1_TRC(x) ((x) << 0)
-
-#define DRAMTMG2_TCWL(x) ((x) << 24)
-#define DRAMTMG2_TCL(x) ((x) << 16)
-#define DRAMTMG2_TRD2WR(x) ((x) << 8)
-#define DRAMTMG2_TWR2RD(x) ((x) << 0)
-
-#define DRAMTMG3_TMRW(x) ((x) << 16)
-#define DRAMTMG3_TMRD(x) ((x) << 12)
-#define DRAMTMG3_TMOD(x) ((x) << 0)
-
-#define DRAMTMG4_TRCD(x) ((x) << 24)
-#define DRAMTMG4_TCCD(x) ((x) << 16)
-#define DRAMTMG4_TRRD(x) ((x) << 8)
-#define DRAMTMG4_TRP(x) ((x) << 0)
-
-#define DRAMTMG5_TCKSRX(x) ((x) << 24)
-#define DRAMTMG5_TCKSRE(x) ((x) << 16)
-#define DRAMTMG5_TCKESR(x) ((x) << 8)
-#define DRAMTMG5_TCKE(x) ((x) << 0)
-
-#define RFSHTMG_TREFI(x) ((x) << 16)
-#define RFSHTMG_TRFC(x) ((x) << 0)
-
-#define PIR_CLRSR (0x1 << 27) /* clear status registers */
-#define PIR_QSGATE (0x1 << 10) /* Read DQS gate training */
-#define PIR_DRAMINIT (0x1 << 8) /* DRAM initialization */
-#define PIR_DRAMRST (0x1 << 7) /* DRAM reset */
-#define PIR_PHYRST (0x1 << 6) /* PHY reset */
-#define PIR_DCAL (0x1 << 5) /* DDL calibration */
-#define PIR_PLLINIT (0x1 << 4) /* PLL initialization */
-#define PIR_ZCAL (0x1 << 1) /* ZQ calibration */
-#define PIR_INIT (0x1 << 0) /* PHY initialization trigger */
-
-#define PGSR_INIT_DONE (0x1 << 0) /* PHY init done */
-
-#define ZQCR_PWRDOWN (1U << 31) /* ZQ power down */
-
-#define ACBDLR_WRITE_DELAY(x) ((x) << 8)
-
-#define DXBDLR_DQ(x) (x) /* DQ0-7 BDLR index */
-#define DXBDLR_DM 8 /* DM BDLR index */
-#define DXBDLR_DQS 9 /* DQS BDLR index */
-#define DXBDLR_DQSN 10 /* DQSN BDLR index */
-
-#define DXBDLR_WRITE_DELAY(x) ((x) << 8)
-#define DXBDLR_READ_DELAY(x) ((x) << 0)
-
-#endif /* _SUNXI_DRAM_SUN8I_H3_H */
--- /dev/null
+/*
+ * sun8i H3 platform dram controller register and constant defines
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ * Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_DRAM_SUN8I_H3_H
+#define _SUNXI_DRAM_SUN8I_H3_H
+
+struct sunxi_mctl_com_reg {
+ u32 cr; /* 0x00 control register */
+ u32 cr_r1; /* 0x04 rank 1 control register (R40 only) */
+ u8 res0[0x4]; /* 0x08 */
+ u32 tmr; /* 0x0c (unused on H3) */
+ u32 mcr[16][2]; /* 0x10 */
+ u32 bwcr; /* 0x90 bandwidth control register */
+ u32 maer; /* 0x94 master enable register */
+ u32 mapr; /* 0x98 master priority register */
+ u32 mcgcr; /* 0x9c */
+ u32 cpu_bwcr; /* 0xa0 */
+ u32 gpu_bwcr; /* 0xa4 */
+ u32 ve_bwcr; /* 0xa8 */
+ u32 disp_bwcr; /* 0xac */
+ u32 other_bwcr; /* 0xb0 */
+ u32 total_bwcr; /* 0xb4 */
+ u8 res1[0x8]; /* 0xb8 */
+ u32 swonr; /* 0xc0 */
+ u32 swoffr; /* 0xc4 */
+ u8 res2[0x8]; /* 0xc8 */
+ u32 cccr; /* 0xd0 */
+ u8 res3[0x54]; /* 0xd4 */
+ u32 mdfs_bwlr[3]; /* 0x128 (unused on H3) */
+ u8 res4[0x6cc]; /* 0x134 */
+ u32 protect; /* 0x800 */
+};
+
+#define MCTL_CR_BL8 (0x4 << 20)
+
+#define MCTL_CR_1T (0x1 << 19)
+#define MCTL_CR_2T (0x0 << 19)
+
+#define MCTL_CR_LPDDR3 (0x7 << 16)
+#define MCTL_CR_LPDDR2 (0x6 << 16)
+#define MCTL_CR_DDR3 (0x3 << 16)
+#define MCTL_CR_DDR2 (0x2 << 16)
+
+#define MCTL_CR_SEQUENTIAL (0x1 << 15)
+#define MCTL_CR_INTERLEAVED (0x0 << 15)
+
+#define MCTL_CR_FULL_WIDTH (0x1 << 12)
+#define MCTL_CR_HALF_WIDTH (0x0 << 12)
+#define MCTL_CR_BUS_FULL_WIDTH(x) ((x) << 12)
+
+#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8)
+#define MCTL_CR_ROW_BITS(x) (((x) - 1) << 4)
+#define MCTL_CR_EIGHT_BANKS (0x1 << 2)
+#define MCTL_CR_FOUR_BANKS (0x0 << 2)
+#define MCTL_CR_DUAL_RANK (0x1 << 0)
+#define MCTL_CR_SINGLE_RANK (0x0 << 0)
+
+/*
+ * CR_R1 is a register found in the R40's DRAM controller. It sets various
+ * parameters for rank 1. Bits [11:0] have the same meaning as the bits in
+ * MCTL_CR, but they apply to rank 1 only. This implies we can have
+ * different chips for rank 1 than rank 0.
+ *
+ * As address line A15 and CS1 chip select for rank 1 are muxed on the same
+ * pin, if single rank is used, A15 must be muxed in.
+ */
+#define MCTL_CR_R1_MUX_A15 (0x1 << 21)
+
+#define PROTECT_MAGIC (0x94be6fa3)
+
+struct sunxi_mctl_ctl_reg {
+ u32 pir; /* 0x00 PHY initialization register */
+ u32 pwrctl; /* 0x04 */
+ u32 mrctrl; /* 0x08 */
+ u32 clken; /* 0x0c */
+ u32 pgsr[2]; /* 0x10 PHY general status registers */
+ u32 statr; /* 0x18 */
+ u8 res1[0x10]; /* 0x1c */
+ u32 lp3mr11; /* 0x2c */
+ u32 mr[4]; /* 0x30 mode registers */
+ u32 pllgcr; /* 0x40 */
+ u32 ptr[5]; /* 0x44 PHY timing registers */
+ u32 dramtmg[9]; /* 0x58 DRAM timing registers */
+ u32 odtcfg; /* 0x7c */
+ u32 pitmg[2]; /* 0x80 PHY interface timing registers */
+ u8 res2[0x4]; /* 0x88 */
+ u32 rfshctl0; /* 0x8c */
+ u32 rfshtmg; /* 0x90 refresh timing */
+ u32 rfshctl1; /* 0x94 */
+ u32 pwrtmg; /* 0x98 */
+ u8 res3[0x1c]; /* 0x9c */
+ u32 vtfcr; /* 0xb8 (unused on H3) */
+ u32 dqsgmr; /* 0xbc */
+ u32 dtcr; /* 0xc0 */
+ u32 dtar[4]; /* 0xc4 */
+ u32 dtdr[2]; /* 0xd4 */
+ u32 dtmr[2]; /* 0xdc */
+ u32 dtbmr; /* 0xe4 */
+ u32 catr[2]; /* 0xe8 */
+ u32 dtedr[2]; /* 0xf0 */
+ u8 res4[0x8]; /* 0xf8 */
+ u32 pgcr[4]; /* 0x100 PHY general configuration registers */
+ u32 iovcr[2]; /* 0x110 */
+ u32 dqsdr; /* 0x118 */
+ u32 dxccr; /* 0x11c */
+ u32 odtmap; /* 0x120 */
+ u32 zqctl[2]; /* 0x124 */
+ u8 res6[0x14]; /* 0x12c */
+ u32 zqcr; /* 0x140 ZQ control register */
+ u32 zqsr; /* 0x144 ZQ status register */
+ u32 zqdr[3]; /* 0x148 ZQ data registers */
+ u8 res7[0x6c]; /* 0x154 */
+ u32 sched; /* 0x1c0 */
+ u32 perfhpr[2]; /* 0x1c4 */
+ u32 perflpr[2]; /* 0x1cc */
+ u32 perfwr[2]; /* 0x1d4 */
+ u8 res8[0x24]; /* 0x1dc */
+ u32 acmdlr; /* 0x200 AC master delay line register */
+ u32 aclcdlr; /* 0x204 AC local calibrated delay line register */
+ u32 aciocr; /* 0x208 AC I/O configuration register */
+ u8 res9[0x4]; /* 0x20c */
+ u32 acbdlr[31]; /* 0x210 AC bit delay line registers */
+ u8 res10[0x74]; /* 0x28c */
+ struct { /* 0x300 DATX8 modules*/
+ u32 mdlr; /* 0x00 master delay line register */
+ u32 lcdlr[3]; /* 0x04 local calibrated delay line registers */
+ u32 bdlr[11]; /* 0x10 bit delay line registers */
+ u32 sdlr; /* 0x3c output enable bit delay registers */
+ u32 gtr; /* 0x40 general timing register */
+ u32 gcr; /* 0x44 general configuration register */
+ u32 gsr[3]; /* 0x48 general status registers */
+ u8 res0[0x2c]; /* 0x54 */
+ } dx[4];
+ u8 res11[0x388]; /* 0x500 */
+ u32 upd2; /* 0x888 */
+};
+
+#define PTR3_TDINIT1(x) ((x) << 20)
+#define PTR3_TDINIT0(x) ((x) << 0)
+
+#define PTR4_TDINIT3(x) ((x) << 20)
+#define PTR4_TDINIT2(x) ((x) << 0)
+
+#define DRAMTMG0_TWTP(x) ((x) << 24)
+#define DRAMTMG0_TFAW(x) ((x) << 16)
+#define DRAMTMG0_TRAS_MAX(x) ((x) << 8)
+#define DRAMTMG0_TRAS(x) ((x) << 0)
+
+#define DRAMTMG1_TXP(x) ((x) << 16)
+#define DRAMTMG1_TRTP(x) ((x) << 8)
+#define DRAMTMG1_TRC(x) ((x) << 0)
+
+#define DRAMTMG2_TCWL(x) ((x) << 24)
+#define DRAMTMG2_TCL(x) ((x) << 16)
+#define DRAMTMG2_TRD2WR(x) ((x) << 8)
+#define DRAMTMG2_TWR2RD(x) ((x) << 0)
+
+#define DRAMTMG3_TMRW(x) ((x) << 16)
+#define DRAMTMG3_TMRD(x) ((x) << 12)
+#define DRAMTMG3_TMOD(x) ((x) << 0)
+
+#define DRAMTMG4_TRCD(x) ((x) << 24)
+#define DRAMTMG4_TCCD(x) ((x) << 16)
+#define DRAMTMG4_TRRD(x) ((x) << 8)
+#define DRAMTMG4_TRP(x) ((x) << 0)
+
+#define DRAMTMG5_TCKSRX(x) ((x) << 24)
+#define DRAMTMG5_TCKSRE(x) ((x) << 16)
+#define DRAMTMG5_TCKESR(x) ((x) << 8)
+#define DRAMTMG5_TCKE(x) ((x) << 0)
+
+#define RFSHTMG_TREFI(x) ((x) << 16)
+#define RFSHTMG_TRFC(x) ((x) << 0)
+
+#define PIR_CLRSR (0x1 << 27) /* clear status registers */
+#define PIR_QSGATE (0x1 << 10) /* Read DQS gate training */
+#define PIR_DRAMINIT (0x1 << 8) /* DRAM initialization */
+#define PIR_DRAMRST (0x1 << 7) /* DRAM reset */
+#define PIR_PHYRST (0x1 << 6) /* PHY reset */
+#define PIR_DCAL (0x1 << 5) /* DDL calibration */
+#define PIR_PLLINIT (0x1 << 4) /* PLL initialization */
+#define PIR_ZCAL (0x1 << 1) /* ZQ calibration */
+#define PIR_INIT (0x1 << 0) /* PHY initialization trigger */
+
+#define PGSR_INIT_DONE (0x1 << 0) /* PHY init done */
+
+#define ZQCR_PWRDOWN (1U << 31) /* ZQ power down */
+
+#define ACBDLR_WRITE_DELAY(x) ((x) << 8)
+
+#define DXBDLR_DQ(x) (x) /* DQ0-7 BDLR index */
+#define DXBDLR_DM 8 /* DM BDLR index */
+#define DXBDLR_DQS 9 /* DQS BDLR index */
+#define DXBDLR_DQSN 10 /* DQSN BDLR index */
+
+#define DXBDLR_WRITE_DELAY(x) ((x) << 8)
+#define DXBDLR_READ_DELAY(x) ((x) << 0)
+
+/*
+ * The delay parameters below allow to allegedly specify delay times of some
+ * unknown unit for each individual bit trace in each of the four data bytes
+ * the 32-bit wide access consists of. Also three control signals can be
+ * adjusted individually.
+ */
+#define BITS_PER_BYTE 8
+#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
+/* The eight data lines (DQn) plus DM, DQS and DQSN */
+#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3)
+struct dram_para {
+ u16 page_size;
+ u8 bus_full_width;
+ u8 dual_rank;
+ u8 row_bits;
+ u8 bank_bits;
+ const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
+ const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
+ const u8 ac_delays[31];
+};
+
+static inline int ns_to_t(int nanoseconds)
+{
+ const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
+
+ return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
+}
+
+void mctl_set_timing_params(uint16_t socid, struct dram_para *para);
+
+#endif /* _SUNXI_DRAM_SUN8I_H3_H */
separate ahb reset control registers, custom pmic bus, new style
watchdog, etc.
+config SUNXI_DRAM_DW
+ bool
+ ---help---
+ Select this for sunxi SoCs which uses a DRAM controller like the
+ DesignWare controller used in H3, mainly SoCs after H3, which do
+ not have official open-source DRAM initialization code, but can
+ use modified H3 DRAM initialization code.
+
+if SUNXI_DRAM_DW
+config SUNXI_DRAM_DW_16BIT
+ bool
+ ---help---
+ Select this for sunxi SoCs with DesignWare DRAM controller and
+ have only 16-bit memory buswidth.
+
+config SUNXI_DRAM_DW_32BIT
+ bool
+ ---help---
+ Select this for sunxi SoCs with DesignWare DRAM controller with
+ 32-bit memory buswidth.
+endif
config MACH_SUNXI_H3_H5
bool
select DM_I2C
select SUNXI_DE2
+ select SUNXI_DRAM_DW
+ select SUNXI_DRAM_DW_32BIT
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+ select SUNXI_DRAM_DW
+ select SUNXI_DRAM_DW_32BIT
config MACH_SUN8I_V3S
bool "sun8i (Allwinner V3s)"
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN6I
+ select SUNXI_DRAM_DW
+ select SUNXI_DRAM_DW_16BIT
+ select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
config MACH_SUN9I
select SUNXI_GEN_SUN6I
select SUNXI_HIGH_SRAM
select SUPPORT_SPL
+ select SUNXI_DRAM_DW
+ select SUNXI_DRAM_DW_32BIT
select FIT
select SPL_LOAD_FIT
This allows both the SPL and the U-Boot proper to be entered in
either mode and switch to AArch64 if needed.
+if SUNXI_DRAM_DW
+config SUNXI_DRAM_DDR3
+ bool
+
+config SUNXI_DRAM_DDR2
+ bool
+
+config SUNXI_DRAM_LPDDR3
+ bool
+
+choice
+ prompt "DRAM Type and Timing"
+ default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
+ default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
+
+config SUNXI_DRAM_DDR3_1333
+ bool "DDR3 1333"
+ select SUNXI_DRAM_DDR3
+ depends on !MACH_SUN8I_V3S
+ ---help---
+ This option is the original only supported memory type, which suits
+ many H3/H5/A64 boards available now.
+
+config SUNXI_DRAM_LPDDR3_STOCK
+ bool "LPDDR3 with Allwinner stock configuration"
+ select SUNXI_DRAM_LPDDR3
+ ---help---
+ This option is the LPDDR3 timing used by the stock boot0 by
+ Allwinner.
+
+config SUNXI_DRAM_DDR2_V3S
+ bool "DDR2 found in V3s chip"
+ select SUNXI_DRAM_DDR2
+ depends on MACH_SUN8I_V3S
+ ---help---
+ This option is only for the DDR2 memory chip which is co-packaged in
+ Allwinner V3s SoC.
+
+endchoice
+endif
+
config DRAM_TYPE
int "sunxi dram type"
depends on MACH_SUN8I_A83T
default 792 if MACH_SUN9I
default 648 if MACH_SUN8I_R40
default 312 if MACH_SUN6I || MACH_SUN8I
- default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
+ default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
+ MACH_SUN8I_V3S
default 672 if MACH_SUN50I
---help---
Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
int "sunxi dram zq value"
default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
default 127 if MACH_SUN7I
+ default 14779 if MACH_SUN8I_V3S
default 3881979 if MACH_SUN8I_R40
default 4145117 if MACH_SUN9I
default 3881915 if MACH_SUN50I
obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o
obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o
obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o
-obj-$(CONFIG_MACH_SUNXI_H3_H5) += dram_sun8i_h3.o
-obj-$(CONFIG_MACH_SUN8I_R40) += dram_sun8i_h3.o
+obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o
+obj-$(CONFIG_SUNXI_DRAM_DW) += dram_timings/
obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o
-obj-$(CONFIG_MACH_SUN50I) += dram_sun8i_h3.o
endif
+++ /dev/null
-/*
- * sun8i H3 platform dram controller init
- *
- * (C) Copyright 2007-2015 Allwinner Technology Co.
- * Jerry Wang <wangflord@allwinnertech.com>
- * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
- * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
- * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/dram.h>
-#include <asm/arch/cpu.h>
-#include <linux/kconfig.h>
-
-/*
- * The delay parameters below allow to allegedly specify delay times of some
- * unknown unit for each individual bit trace in each of the four data bytes
- * the 32-bit wide access consists of. Also three control signals can be
- * adjusted individually.
- */
-#define BITS_PER_BYTE 8
-#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
-/* The eight data lines (DQn) plus DM, DQS and DQSN */
-#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3)
-struct dram_para {
- u16 page_size;
- u8 bus_width;
- u8 dual_rank;
- u8 row_bits;
- const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
- const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
- const u8 ac_delays[31];
-};
-
-static inline int ns_to_t(int nanoseconds)
-{
- const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
-
- return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
-}
-
-static void mctl_phy_init(u32 val)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- writel(val | PIR_INIT, &mctl_ctl->pir);
- mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1);
-}
-
-static void mctl_set_bit_delays(struct dram_para *para)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
- int i, j;
-
- clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
-
- for (i = 0; i < NR_OF_BYTE_LANES; i++)
- for (j = 0; j < LINES_PER_BYTE_LANE; j++)
- writel(DXBDLR_WRITE_DELAY(para->dx_write_delays[i][j]) |
- DXBDLR_READ_DELAY(para->dx_read_delays[i][j]),
- &mctl_ctl->dx[i].bdlr[j]);
-
- for (i = 0; i < 31; i++)
- writel(ACBDLR_WRITE_DELAY(para->ac_delays[i]),
- &mctl_ctl->acbdlr[i]);
-
-#ifdef CONFIG_MACH_SUN8I_R40
- /* DQSn, DMn, DQn output enable bit delay */
- for (i = 0; i < 4; i++)
- writel(0x6 << 24, &mctl_ctl->dx[i].sdlr);
-#endif
-
- setbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
-}
-
-enum {
- MBUS_PORT_CPU = 0,
- MBUS_PORT_GPU = 1,
- MBUS_PORT_UNUSED = 2,
- MBUS_PORT_DMA = 3,
- MBUS_PORT_VE = 4,
- MBUS_PORT_CSI = 5,
- MBUS_PORT_NAND = 6,
- MBUS_PORT_SS = 7,
- MBUS_PORT_TS = 8,
- MBUS_PORT_DI = 9,
- MBUS_PORT_DE = 10,
- MBUS_PORT_DE_CFD = 11,
- MBUS_PORT_UNKNOWN1 = 12,
- MBUS_PORT_UNKNOWN2 = 13,
- MBUS_PORT_UNKNOWN3 = 14,
-};
-
-enum {
- MBUS_QOS_LOWEST = 0,
- MBUS_QOS_LOW,
- MBUS_QOS_HIGH,
- MBUS_QOS_HIGHEST
-};
-
-inline void mbus_configure_port(u8 port,
- bool bwlimit,
- bool priority,
- u8 qos, /* MBUS_QOS_LOWEST .. MBUS_QOS_HIGEST */
- u8 waittime, /* 0 .. 0xf */
- u8 acs, /* 0 .. 0xff */
- u16 bwl0, /* 0 .. 0xffff, bandwidth limit in MB/s */
- u16 bwl1,
- u16 bwl2)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
-
- const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0)
- | (priority ? (1 << 1) : 0)
- | ((qos & 0x3) << 2)
- | ((waittime & 0xf) << 4)
- | ((acs & 0xff) << 8)
- | (bwl0 << 16) );
- const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff);
-
- debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
- writel(cfg0, &mctl_com->mcr[port][0]);
- writel(cfg1, &mctl_com->mcr[port][1]);
-}
-
-#define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \
- mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
- MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
-
-static void mctl_set_master_priority_h3(void)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
-
- /* enable bandwidth limit windows and set windows size 1us */
- writel((1 << 16) | (400 << 0), &mctl_com->bwcr);
-
- /* set cpu high priority */
- writel(0x00000001, &mctl_com->mapr);
-
- MBUS_CONF( CPU, true, HIGHEST, 0, 512, 256, 128);
- MBUS_CONF( GPU, true, HIGH, 0, 1536, 1024, 256);
- MBUS_CONF(UNUSED, true, HIGHEST, 0, 512, 256, 96);
- MBUS_CONF( DMA, true, HIGHEST, 0, 256, 128, 32);
- MBUS_CONF( VE, true, HIGH, 0, 1792, 1600, 256);
- MBUS_CONF( CSI, true, HIGHEST, 0, 256, 128, 32);
- MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
- MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
- MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
- MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
- MBUS_CONF( DE, true, HIGHEST, 3, 8192, 6120, 1024);
- MBUS_CONF(DE_CFD, true, HIGH, 0, 1024, 288, 64);
-}
-
-static void mctl_set_master_priority_a64(void)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
-
- /* enable bandwidth limit windows and set windows size 1us */
- writel(399, &mctl_com->tmr);
- writel((1 << 16), &mctl_com->bwcr);
-
- /* Port 2 is reserved per Allwinner's linux-3.10 source, yet they
- * initialise it */
- MBUS_CONF( CPU, true, HIGHEST, 0, 160, 100, 80);
- MBUS_CONF( GPU, false, HIGH, 0, 1536, 1400, 256);
- MBUS_CONF(UNUSED, true, HIGHEST, 0, 512, 256, 96);
- MBUS_CONF( DMA, true, HIGH, 0, 256, 80, 100);
- MBUS_CONF( VE, true, HIGH, 0, 1792, 1600, 256);
- MBUS_CONF( CSI, true, HIGH, 0, 256, 128, 0);
- MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
- MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
- MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
- MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
- MBUS_CONF( DE, true, HIGH, 2, 8192, 6144, 2048);
- MBUS_CONF(DE_CFD, true, HIGH, 0, 1280, 144, 64);
-
- writel(0x81000004, &mctl_com->mdfs_bwlr[2]);
-}
-
-static void mctl_set_master_priority_h5(void)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
-
- /* enable bandwidth limit windows and set windows size 1us */
- writel(399, &mctl_com->tmr);
- writel((1 << 16), &mctl_com->bwcr);
-
- /* set cpu high priority */
- writel(0x00000001, &mctl_com->mapr);
-
- /* Port 2 is reserved per Allwinner's linux-3.10 source, yet
- * they initialise it */
- MBUS_CONF( CPU, true, HIGHEST, 0, 300, 260, 150);
- MBUS_CONF( GPU, true, HIGHEST, 0, 600, 400, 200);
- MBUS_CONF(UNUSED, true, HIGHEST, 0, 512, 256, 96);
- MBUS_CONF( DMA, true, HIGHEST, 0, 256, 128, 32);
- MBUS_CONF( VE, true, HIGHEST, 0, 1900, 1500, 1000);
- MBUS_CONF( CSI, true, HIGHEST, 0, 150, 120, 100);
- MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
- MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
- MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
- MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
- MBUS_CONF( DE, true, HIGHEST, 3, 3400, 2400, 1024);
- MBUS_CONF(DE_CFD, true, HIGHEST, 0, 600, 400, 200);
-}
-
-static void mctl_set_master_priority_r40(void)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
-
- /* enable bandwidth limit windows and set windows size 1us */
- writel(399, &mctl_com->tmr);
- writel((1 << 16), &mctl_com->bwcr);
-
- /* set cpu high priority */
- writel(0x00000001, &mctl_com->mapr);
-
- /* Port 2 is reserved per Allwinner's linux-3.10 source, yet
- * they initialise it */
- MBUS_CONF( CPU, true, HIGHEST, 0, 300, 260, 150);
- MBUS_CONF( GPU, true, HIGHEST, 0, 600, 400, 200);
- MBUS_CONF( UNUSED, true, HIGHEST, 0, 512, 256, 96);
- MBUS_CONF( DMA, true, HIGHEST, 0, 256, 128, 32);
- MBUS_CONF( VE, true, HIGHEST, 0, 1900, 1500, 1000);
- MBUS_CONF( CSI, true, HIGHEST, 0, 150, 120, 100);
- MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
- MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
- MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
- MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
-
- /*
- * The port names are probably wrong, but no correct sources
- * are available.
- */
- MBUS_CONF( DE, true, HIGH, 0, 128, 48, 0);
- MBUS_CONF( DE_CFD, true, HIGH, 0, 384, 256, 0);
- MBUS_CONF(UNKNOWN1, true, HIGHEST, 0, 512, 384, 256);
- MBUS_CONF(UNKNOWN2, true, HIGHEST, 2, 8192, 6144, 1024);
- MBUS_CONF(UNKNOWN3, true, HIGH, 0, 1280, 144, 64);
-}
-
-static void mctl_set_master_priority(uint16_t socid)
-{
- switch (socid) {
- case SOCID_H3:
- mctl_set_master_priority_h3();
- return;
- case SOCID_A64:
- mctl_set_master_priority_a64();
- return;
- case SOCID_H5:
- mctl_set_master_priority_h5();
- return;
- case SOCID_R40:
- mctl_set_master_priority_r40();
- return;
- }
-}
-
-static void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- u8 tccd = 2;
- u8 tfaw = ns_to_t(50);
- u8 trrd = max(ns_to_t(10), 4);
- u8 trcd = ns_to_t(15);
- u8 trc = ns_to_t(53);
- u8 txp = max(ns_to_t(8), 3);
- u8 twtr = max(ns_to_t(8), 4);
- u8 trtp = max(ns_to_t(8), 4);
- u8 twr = max(ns_to_t(15), 3);
- u8 trp = ns_to_t(15);
- u8 tras = ns_to_t(38);
- u16 trefi = ns_to_t(7800) / 32;
- u16 trfc = ns_to_t(350);
-
- u8 tmrw = 0;
- u8 tmrd = 4;
- u8 tmod = 12;
- u8 tcke = 3;
- u8 tcksrx = 5;
- u8 tcksre = 5;
- u8 tckesr = 4;
- u8 trasmax = 24;
-
- u8 tcl = 6; /* CL 12 */
- u8 tcwl = 4; /* CWL 8 */
- u8 t_rdata_en = 4;
- u8 wr_latency = 2;
-
- u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
- u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
- u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
- u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
-
- u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
- u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
- u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
-
- /* set mode register */
- writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */
- writel(0x40, &mctl_ctl->mr[1]);
- writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
- writel(0x0, &mctl_ctl->mr[3]);
-
- if (socid == SOCID_R40)
- writel(0x3, &mctl_ctl->lp3mr11); /* odt_en[7:4] */
-
- /* set DRAM timing */
- writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
- DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
- &mctl_ctl->dramtmg[0]);
- writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
- &mctl_ctl->dramtmg[1]);
- writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
- DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
- &mctl_ctl->dramtmg[2]);
- writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
- &mctl_ctl->dramtmg[3]);
- writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
- DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
- writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
- DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
- &mctl_ctl->dramtmg[5]);
-
- /* set two rank timing */
- clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
- ((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0));
-
- /* set PHY interface timing, write latency and read latency configure */
- writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
- (wr_latency << 0), &mctl_ctl->pitmg[0]);
-
- /* set PHY timing, PTR0-2 use default */
- writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
- writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
-
- /* set refresh timing */
- writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
-}
-
-static u32 bin_to_mgray(int val)
-{
- static const u8 lookup_table[32] = {
- 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
- 0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09,
- 0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d,
- 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11,
- };
-
- return lookup_table[clamp(val, 0, 31)];
-}
-
-static int mgray_to_bin(u32 val)
-{
- static const u8 lookup_table[32] = {
- 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
- 0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b,
- 0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b,
- 0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15,
- };
-
- return lookup_table[val & 0x1f];
-}
-
-static void mctl_h3_zq_calibration_quirk(struct dram_para *para)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 &&
- (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) {
- u32 reg_val;
-
- clrsetbits_le32(&mctl_ctl->zqcr, 0xffff,
- CONFIG_DRAM_ZQ & 0xffff);
-
- writel(PIR_CLRSR, &mctl_ctl->pir);
- mctl_phy_init(PIR_ZCAL);
-
- reg_val = readl(&mctl_ctl->zqdr[0]);
- reg_val &= (0x1f << 16) | (0x1f << 0);
- reg_val |= reg_val << 8;
- writel(reg_val, &mctl_ctl->zqdr[0]);
-
- reg_val = readl(&mctl_ctl->zqdr[1]);
- reg_val &= (0x1f << 16) | (0x1f << 0);
- reg_val |= reg_val << 8;
- writel(reg_val, &mctl_ctl->zqdr[1]);
- writel(reg_val, &mctl_ctl->zqdr[2]);
- } else {
- int i;
- u16 zq_val[6];
- u8 val;
-
- writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
-
- for (i = 0; i < 6; i++) {
- u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
-
- writel((zq << 20) | (zq << 16) | (zq << 12) |
- (zq << 8) | (zq << 4) | (zq << 0),
- &mctl_ctl->zqcr);
-
- writel(PIR_CLRSR, &mctl_ctl->pir);
- mctl_phy_init(PIR_ZCAL);
-
- zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
- writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
-
- writel(PIR_CLRSR, &mctl_ctl->pir);
- mctl_phy_init(PIR_ZCAL);
-
- val = readl(&mctl_ctl->zqdr[0]) >> 24;
- zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
- }
-
- writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
- writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
- writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
- }
-}
-
-static void mctl_set_cr(uint16_t socid, struct dram_para *para)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
-
- writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED |
- MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) |
- (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
- MCTL_CR_PAGE_SIZE(para->page_size) |
- MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
-
- if (socid == SOCID_R40) {
- if (para->dual_rank)
- panic("Dual rank memory not supported\n");
-
- /* Mux pin to A15 address line for single rank memory. */
- setbits_le32(&mctl_com->cr_r1, MCTL_CR_R1_MUX_A15);
- }
-}
-
-static void mctl_sys_init(uint16_t socid, struct dram_para *para)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
- clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
- clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
- clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
- clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
- if (socid == SOCID_A64 || socid == SOCID_R40)
- clrbits_le32(&ccm->pll11_cfg, CCM_PLL11_CTRL_EN);
- udelay(10);
-
- clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
- udelay(1000);
-
- if (socid == SOCID_A64 || socid == SOCID_R40) {
- clock_set_pll11(CONFIG_DRAM_CLK * 2 * 1000000, false);
- clrsetbits_le32(&ccm->dram_clk_cfg,
- CCM_DRAMCLK_CFG_DIV_MASK |
- CCM_DRAMCLK_CFG_SRC_MASK,
- CCM_DRAMCLK_CFG_DIV(1) |
- CCM_DRAMCLK_CFG_SRC_PLL11 |
- CCM_DRAMCLK_CFG_UPD);
- } else if (socid == SOCID_H3 || socid == SOCID_H5) {
- clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
- clrsetbits_le32(&ccm->dram_clk_cfg,
- CCM_DRAMCLK_CFG_DIV_MASK |
- CCM_DRAMCLK_CFG_SRC_MASK,
- CCM_DRAMCLK_CFG_DIV(1) |
- CCM_DRAMCLK_CFG_SRC_PLL5 |
- CCM_DRAMCLK_CFG_UPD);
- }
- mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
-
- setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
- setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
- setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
- setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
-
- setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
- udelay(10);
-
- writel(socid == SOCID_H5 ? 0x8000 : 0xc00e, &mctl_ctl->clken);
- udelay(500);
-}
-
-/* These are more guessed based on some Allwinner code. */
-#define DX_GCR_ODT_DYNAMIC (0x0 << 4)
-#define DX_GCR_ODT_ALWAYS_ON (0x1 << 4)
-#define DX_GCR_ODT_OFF (0x2 << 4)
-
-static int mctl_channel_init(uint16_t socid, struct dram_para *para)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- unsigned int i;
-
- mctl_set_cr(socid, para);
- mctl_set_timing_params(socid, para);
- mctl_set_master_priority(socid);
-
- /* setting VTC, default disable all VT */
- clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f);
- if (socid == SOCID_H5)
- setbits_le32(&mctl_ctl->pgcr[1], (1 << 24) | (1 << 26));
- else
- clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
-
- /* increase DFI_PHY_UPD clock */
- writel(PROTECT_MAGIC, &mctl_com->protect);
- udelay(100);
- clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16);
- writel(0x0, &mctl_com->protect);
- udelay(100);
-
- /* set dramc odt */
- for (i = 0; i < 4; i++) {
- u32 clearmask = (0x3 << 4) | (0x1 << 1) | (0x3 << 2) |
- (0x3 << 12) | (0x3 << 14);
- u32 setmask = IS_ENABLED(CONFIG_DRAM_ODT_EN) ?
- DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF;
-
- if (socid == SOCID_H5) {
- clearmask |= 0x2 << 8;
- setmask |= 0x4 << 8;
- }
- clrsetbits_le32(&mctl_ctl->dx[i].gcr, clearmask, setmask);
- }
-
- /* AC PDR should always ON */
- clrsetbits_le32(&mctl_ctl->aciocr, socid == SOCID_H5 ? (0x1 << 11) : 0,
- 0x1 << 1);
-
- /* set DQS auto gating PD mode */
- setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);
-
- if (socid == SOCID_H3) {
- /* dx ddr_clk & hdr_clk dynamic mode */
- clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
-
- /* dphy & aphy phase select 270 degree */
- clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
- (0x1 << 10) | (0x2 << 8));
- } else if (socid == SOCID_A64 || socid == SOCID_H5) {
- /* dphy & aphy phase select ? */
- clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
- (0x0 << 10) | (0x3 << 8));
- } else if (socid == SOCID_R40) {
- /* dx ddr_clk & hdr_clk dynamic mode (tpr13[9] == 0) */
- clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
-
- /* dphy & aphy phase select ? */
- clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
- (0x0 << 10) | (0x3 << 8));
- }
-
- /* set half DQ */
- if (para->bus_width != 32) {
- writel(0x0, &mctl_ctl->dx[2].gcr);
- writel(0x0, &mctl_ctl->dx[3].gcr);
- }
-
- /* data training configuration */
- clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24,
- (para->dual_rank ? 0x3 : 0x1) << 24);
-
- mctl_set_bit_delays(para);
- udelay(50);
-
- if (socid == SOCID_H3) {
- mctl_h3_zq_calibration_quirk(para);
-
- mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
- PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
- } else if (socid == SOCID_A64 || socid == SOCID_H5) {
- clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ);
-
- mctl_phy_init(PIR_ZCAL | PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
- PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
- /* no PIR_QSGATE for H5 ???? */
- } else if (socid == SOCID_R40) {
- clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ);
-
- mctl_phy_init(PIR_ZCAL | PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
- PIR_DRAMRST | PIR_DRAMINIT);
- }
-
- /* detect ranks and bus width */
- if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) {
- /* only one rank */
- if (((readl(&mctl_ctl->dx[0].gsr[0]) >> 24) & 0x2) ||
- ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x2)) {
- clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
- para->dual_rank = 0;
- }
-
- /* only half DQ width */
- if (((readl(&mctl_ctl->dx[2].gsr[0]) >> 24) & 0x1) ||
- ((readl(&mctl_ctl->dx[3].gsr[0]) >> 24) & 0x1)) {
- writel(0x0, &mctl_ctl->dx[2].gcr);
- writel(0x0, &mctl_ctl->dx[3].gcr);
- para->bus_width = 16;
- }
-
- mctl_set_cr(socid, para);
- udelay(20);
-
- /* re-train */
- mctl_phy_init(PIR_QSGATE);
- if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20))
- return 1;
- }
-
- /* check the dramc status */
- mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
-
- /* liuke added for refresh debug */
- setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
- udelay(10);
- clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
- udelay(10);
-
- /* set PGCR3, CKE polarity */
- if (socid == SOCID_H3)
- writel(0x00aa0060, &mctl_ctl->pgcr[3]);
- else if (socid == SOCID_A64 || socid == SOCID_H5 || socid == SOCID_R40)
- writel(0xc0aa0060, &mctl_ctl->pgcr[3]);
-
- /* power down zq calibration module for power save */
- setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN);
-
- /* enable master access */
- writel(0xffffffff, &mctl_com->maer);
-
- return 0;
-}
-
-static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
-{
- /* detect row address bits */
- para->page_size = 512;
- para->row_bits = 16;
- mctl_set_cr(socid, para);
-
- for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
- if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size))
- break;
-
- /* detect page size */
- para->page_size = 8192;
- mctl_set_cr(socid, para);
-
- for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2)
- if (mctl_mem_matches(para->page_size))
- break;
-}
-
-/*
- * The actual values used here are taken from Allwinner provided boot0
- * binaries, though they are probably board specific, so would likely benefit
- * from invidual tuning for each board. Apparently a lot of boards copy from
- * some Allwinner reference design, so we go with those generic values for now
- * in the hope that they are reasonable for most (all?) boards.
- */
-#define SUN8I_H3_DX_READ_DELAYS \
- {{ 18, 18, 18, 18, 18, 18, 18, 18, 18, 0, 0 }, \
- { 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }, \
- { 18, 18, 18, 18, 18, 18, 18, 18, 18, 0, 0 }, \
- { 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }}
-#define SUN8I_H3_DX_WRITE_DELAYS \
- {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10 }, \
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10 }, \
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10 }, \
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 6 }}
-#define SUN8I_H3_AC_DELAYS \
- { 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0 }
-
-#define SUN8I_R40_DX_READ_DELAYS \
- {{ 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }, \
- { 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }, \
- { 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }, \
- { 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 } }
-#define SUN8I_R40_DX_WRITE_DELAYS \
- {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0 }, \
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0 }, \
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0 }, \
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0 } }
-#define SUN8I_R40_AC_DELAYS \
- { 0, 0, 3, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0 }
-
-#define SUN50I_A64_DX_READ_DELAYS \
- {{ 16, 16, 16, 16, 17, 16, 16, 17, 16, 1, 0 }, \
- { 17, 17, 17, 17, 17, 17, 17, 17, 17, 1, 0 }, \
- { 16, 17, 17, 16, 16, 16, 16, 16, 16, 0, 0 }, \
- { 17, 17, 17, 17, 17, 17, 17, 17, 17, 1, 0 }}
-#define SUN50I_A64_DX_WRITE_DELAYS \
- {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 15 }, \
- { 0, 0, 0, 0, 1, 1, 1, 1, 0, 10, 10 }, \
- { 1, 0, 1, 1, 1, 1, 1, 1, 0, 11, 11 }, \
- { 1, 0, 0, 1, 1, 1, 1, 1, 0, 12, 12 }}
-#define SUN50I_A64_AC_DELAYS \
- { 5, 5, 13, 10, 2, 5, 3, 3, \
- 0, 3, 3, 3, 1, 0, 0, 0, \
- 3, 4, 0, 3, 4, 1, 4, 0, \
- 1, 1, 0, 1, 13, 5, 4 }
-
-#define SUN8I_H5_DX_READ_DELAYS \
- {{ 14, 15, 17, 17, 17, 17, 17, 18, 17, 3, 3 }, \
- { 21, 21, 12, 22, 21, 21, 21, 21, 21, 3, 3 }, \
- { 16, 19, 19, 17, 22, 22, 21, 22, 19, 3, 3 }, \
- { 21, 21, 22, 22, 20, 21, 19, 19, 19, 3, 3 } }
-#define SUN8I_H5_DX_WRITE_DELAYS \
- {{ 1, 2, 3, 4, 3, 4, 4, 4, 6, 6, 6 }, \
- { 6, 6, 6, 5, 5, 5, 5, 5, 6, 6, 6 }, \
- { 0, 2, 4, 2, 6, 5, 5, 5, 6, 6, 6 }, \
- { 3, 3, 3, 2, 2, 1, 1, 1, 4, 4, 4 } }
-#define SUN8I_H5_AC_DELAYS \
- { 0, 0, 5, 5, 0, 0, 0, 0, \
- 0, 0, 0, 0, 3, 3, 3, 3, \
- 3, 3, 3, 3, 3, 3, 3, 3, \
- 3, 3, 3, 3, 2, 0, 0 }
-
-unsigned long sunxi_dram_init(void)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- struct dram_para para = {
- .dual_rank = 0,
- .bus_width = 32,
- .row_bits = 15,
- .page_size = 4096,
-
-#if defined(CONFIG_MACH_SUN8I_H3)
- .dx_read_delays = SUN8I_H3_DX_READ_DELAYS,
- .dx_write_delays = SUN8I_H3_DX_WRITE_DELAYS,
- .ac_delays = SUN8I_H3_AC_DELAYS,
-#elif defined(CONFIG_MACH_SUN8I_R40)
- .dx_read_delays = SUN8I_R40_DX_READ_DELAYS,
- .dx_write_delays = SUN8I_R40_DX_WRITE_DELAYS,
- .ac_delays = SUN8I_R40_AC_DELAYS,
-#elif defined(CONFIG_MACH_SUN50I)
- .dx_read_delays = SUN50I_A64_DX_READ_DELAYS,
- .dx_write_delays = SUN50I_A64_DX_WRITE_DELAYS,
- .ac_delays = SUN50I_A64_AC_DELAYS,
-#elif defined(CONFIG_MACH_SUN50I_H5)
- .dx_read_delays = SUN8I_H5_DX_READ_DELAYS,
- .dx_write_delays = SUN8I_H5_DX_WRITE_DELAYS,
- .ac_delays = SUN8I_H5_AC_DELAYS,
-#endif
- };
-/*
- * Let the compiler optimize alternatives away by passing this value into
- * the static functions. This saves us #ifdefs, but still keeps the binary
- * small.
- */
-#if defined(CONFIG_MACH_SUN8I_H3)
- uint16_t socid = SOCID_H3;
-#elif defined(CONFIG_MACH_SUN8I_R40)
- uint16_t socid = SOCID_R40;
-#elif defined(CONFIG_MACH_SUN50I)
- uint16_t socid = SOCID_A64;
-#elif defined(CONFIG_MACH_SUN50I_H5)
- uint16_t socid = SOCID_H5;
-#endif
-
- mctl_sys_init(socid, ¶);
- if (mctl_channel_init(socid, ¶))
- return 0;
-
- if (para.dual_rank)
- writel(0x00000303, &mctl_ctl->odtmap);
- else
- writel(0x00000201, &mctl_ctl->odtmap);
- udelay(1);
-
- /* odt delay */
- if (socid == SOCID_H3)
- writel(0x0c000400, &mctl_ctl->odtcfg);
-
- if (socid == SOCID_A64 || socid == SOCID_H5 || socid == SOCID_R40) {
- /* VTF enable (tpr13[8] == 1) */
- setbits_le32(&mctl_ctl->vtfcr,
- (socid != SOCID_A64 ? 3 : 2) << 8);
- /* DQ hold disable (tpr13[26] == 1) */
- clrbits_le32(&mctl_ctl->pgcr[2], (1 << 13));
- }
-
- /* clear credit value */
- setbits_le32(&mctl_com->cccr, 1 << 31);
- udelay(10);
-
- mctl_auto_detect_dram_size(socid, ¶);
- mctl_set_cr(socid, ¶);
-
- return (1UL << (para.row_bits + 3)) * para.page_size *
- (para.dual_rank ? 2 : 1);
-}
--- /dev/null
+/*
+ * sun8i H3 platform dram controller init
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ * Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/cpu.h>
+#include <linux/kconfig.h>
+
+static void mctl_phy_init(u32 val)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ writel(val | PIR_INIT, &mctl_ctl->pir);
+ mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1);
+}
+
+static void mctl_set_bit_delays(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ int i, j;
+
+ clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
+
+ for (i = 0; i < NR_OF_BYTE_LANES; i++)
+ for (j = 0; j < LINES_PER_BYTE_LANE; j++)
+ writel(DXBDLR_WRITE_DELAY(para->dx_write_delays[i][j]) |
+ DXBDLR_READ_DELAY(para->dx_read_delays[i][j]),
+ &mctl_ctl->dx[i].bdlr[j]);
+
+ for (i = 0; i < 31; i++)
+ writel(ACBDLR_WRITE_DELAY(para->ac_delays[i]),
+ &mctl_ctl->acbdlr[i]);
+
+#ifdef CONFIG_MACH_SUN8I_R40
+ /* DQSn, DMn, DQn output enable bit delay */
+ for (i = 0; i < 4; i++)
+ writel(0x6 << 24, &mctl_ctl->dx[i].sdlr);
+#endif
+
+ setbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
+}
+
+enum {
+ MBUS_PORT_CPU = 0,
+ MBUS_PORT_GPU = 1,
+ MBUS_PORT_UNUSED = 2,
+ MBUS_PORT_DMA = 3,
+ MBUS_PORT_VE = 4,
+ MBUS_PORT_CSI = 5,
+ MBUS_PORT_NAND = 6,
+ MBUS_PORT_SS = 7,
+ MBUS_PORT_TS = 8,
+ MBUS_PORT_DI = 9,
+ MBUS_PORT_DE = 10,
+ MBUS_PORT_DE_CFD = 11,
+ MBUS_PORT_UNKNOWN1 = 12,
+ MBUS_PORT_UNKNOWN2 = 13,
+ MBUS_PORT_UNKNOWN3 = 14,
+};
+
+enum {
+ MBUS_QOS_LOWEST = 0,
+ MBUS_QOS_LOW,
+ MBUS_QOS_HIGH,
+ MBUS_QOS_HIGHEST
+};
+
+inline void mbus_configure_port(u8 port,
+ bool bwlimit,
+ bool priority,
+ u8 qos, /* MBUS_QOS_LOWEST .. MBUS_QOS_HIGEST */
+ u8 waittime, /* 0 .. 0xf */
+ u8 acs, /* 0 .. 0xff */
+ u16 bwl0, /* 0 .. 0xffff, bandwidth limit in MB/s */
+ u16 bwl1,
+ u16 bwl2)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0)
+ | (priority ? (1 << 1) : 0)
+ | ((qos & 0x3) << 2)
+ | ((waittime & 0xf) << 4)
+ | ((acs & 0xff) << 8)
+ | (bwl0 << 16) );
+ const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff);
+
+ debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
+ writel(cfg0, &mctl_com->mcr[port][0]);
+ writel(cfg1, &mctl_com->mcr[port][1]);
+}
+
+#define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \
+ mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
+ MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
+
+static void mctl_set_master_priority_h3(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ /* enable bandwidth limit windows and set windows size 1us */
+ writel((1 << 16) | (400 << 0), &mctl_com->bwcr);
+
+ /* set cpu high priority */
+ writel(0x00000001, &mctl_com->mapr);
+
+ MBUS_CONF( CPU, true, HIGHEST, 0, 512, 256, 128);
+ MBUS_CONF( GPU, true, HIGH, 0, 1536, 1024, 256);
+ MBUS_CONF(UNUSED, true, HIGHEST, 0, 512, 256, 96);
+ MBUS_CONF( DMA, true, HIGHEST, 0, 256, 128, 32);
+ MBUS_CONF( VE, true, HIGH, 0, 1792, 1600, 256);
+ MBUS_CONF( CSI, true, HIGHEST, 0, 256, 128, 32);
+ MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
+ MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
+ MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
+ MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
+ MBUS_CONF( DE, true, HIGHEST, 3, 8192, 6120, 1024);
+ MBUS_CONF(DE_CFD, true, HIGH, 0, 1024, 288, 64);
+}
+
+static void mctl_set_master_priority_a64(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ /* enable bandwidth limit windows and set windows size 1us */
+ writel(399, &mctl_com->tmr);
+ writel((1 << 16), &mctl_com->bwcr);
+
+ /* Port 2 is reserved per Allwinner's linux-3.10 source, yet they
+ * initialise it */
+ MBUS_CONF( CPU, true, HIGHEST, 0, 160, 100, 80);
+ MBUS_CONF( GPU, false, HIGH, 0, 1536, 1400, 256);
+ MBUS_CONF(UNUSED, true, HIGHEST, 0, 512, 256, 96);
+ MBUS_CONF( DMA, true, HIGH, 0, 256, 80, 100);
+ MBUS_CONF( VE, true, HIGH, 0, 1792, 1600, 256);
+ MBUS_CONF( CSI, true, HIGH, 0, 256, 128, 0);
+ MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
+ MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
+ MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
+ MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
+ MBUS_CONF( DE, true, HIGH, 2, 8192, 6144, 2048);
+ MBUS_CONF(DE_CFD, true, HIGH, 0, 1280, 144, 64);
+
+ writel(0x81000004, &mctl_com->mdfs_bwlr[2]);
+}
+
+static void mctl_set_master_priority_h5(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ /* enable bandwidth limit windows and set windows size 1us */
+ writel(399, &mctl_com->tmr);
+ writel((1 << 16), &mctl_com->bwcr);
+
+ /* set cpu high priority */
+ writel(0x00000001, &mctl_com->mapr);
+
+ /* Port 2 is reserved per Allwinner's linux-3.10 source, yet
+ * they initialise it */
+ MBUS_CONF( CPU, true, HIGHEST, 0, 300, 260, 150);
+ MBUS_CONF( GPU, true, HIGHEST, 0, 600, 400, 200);
+ MBUS_CONF(UNUSED, true, HIGHEST, 0, 512, 256, 96);
+ MBUS_CONF( DMA, true, HIGHEST, 0, 256, 128, 32);
+ MBUS_CONF( VE, true, HIGHEST, 0, 1900, 1500, 1000);
+ MBUS_CONF( CSI, true, HIGHEST, 0, 150, 120, 100);
+ MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
+ MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
+ MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
+ MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
+ MBUS_CONF( DE, true, HIGHEST, 3, 3400, 2400, 1024);
+ MBUS_CONF(DE_CFD, true, HIGHEST, 0, 600, 400, 200);
+}
+
+static void mctl_set_master_priority_r40(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ /* enable bandwidth limit windows and set windows size 1us */
+ writel(399, &mctl_com->tmr);
+ writel((1 << 16), &mctl_com->bwcr);
+
+ /* set cpu high priority */
+ writel(0x00000001, &mctl_com->mapr);
+
+ /* Port 2 is reserved per Allwinner's linux-3.10 source, yet
+ * they initialise it */
+ MBUS_CONF( CPU, true, HIGHEST, 0, 300, 260, 150);
+ MBUS_CONF( GPU, true, HIGHEST, 0, 600, 400, 200);
+ MBUS_CONF( UNUSED, true, HIGHEST, 0, 512, 256, 96);
+ MBUS_CONF( DMA, true, HIGHEST, 0, 256, 128, 32);
+ MBUS_CONF( VE, true, HIGHEST, 0, 1900, 1500, 1000);
+ MBUS_CONF( CSI, true, HIGHEST, 0, 150, 120, 100);
+ MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
+ MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
+ MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
+ MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
+
+ /*
+ * The port names are probably wrong, but no correct sources
+ * are available.
+ */
+ MBUS_CONF( DE, true, HIGH, 0, 128, 48, 0);
+ MBUS_CONF( DE_CFD, true, HIGH, 0, 384, 256, 0);
+ MBUS_CONF(UNKNOWN1, true, HIGHEST, 0, 512, 384, 256);
+ MBUS_CONF(UNKNOWN2, true, HIGHEST, 2, 8192, 6144, 1024);
+ MBUS_CONF(UNKNOWN3, true, HIGH, 0, 1280, 144, 64);
+}
+
+static void mctl_set_master_priority(uint16_t socid)
+{
+ switch (socid) {
+ case SOCID_H3:
+ mctl_set_master_priority_h3();
+ return;
+ case SOCID_A64:
+ mctl_set_master_priority_a64();
+ return;
+ case SOCID_H5:
+ mctl_set_master_priority_h5();
+ return;
+ case SOCID_R40:
+ mctl_set_master_priority_r40();
+ return;
+ }
+}
+
+static u32 bin_to_mgray(int val)
+{
+ static const u8 lookup_table[32] = {
+ 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
+ 0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09,
+ 0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d,
+ 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11,
+ };
+
+ return lookup_table[clamp(val, 0, 31)];
+}
+
+static int mgray_to_bin(u32 val)
+{
+ static const u8 lookup_table[32] = {
+ 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
+ 0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b,
+ 0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b,
+ 0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15,
+ };
+
+ return lookup_table[val & 0x1f];
+}
+
+static void mctl_h3_zq_calibration_quirk(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ int zq_count;
+
+#if defined CONFIG_SUNXI_DRAM_DW_16BIT
+ zq_count = 4;
+#else
+ zq_count = 6;
+#endif
+
+ if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 &&
+ (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) {
+ u32 reg_val;
+
+ clrsetbits_le32(&mctl_ctl->zqcr, 0xffff,
+ CONFIG_DRAM_ZQ & 0xffff);
+
+ writel(PIR_CLRSR, &mctl_ctl->pir);
+ mctl_phy_init(PIR_ZCAL);
+
+ reg_val = readl(&mctl_ctl->zqdr[0]);
+ reg_val &= (0x1f << 16) | (0x1f << 0);
+ reg_val |= reg_val << 8;
+ writel(reg_val, &mctl_ctl->zqdr[0]);
+
+ reg_val = readl(&mctl_ctl->zqdr[1]);
+ reg_val &= (0x1f << 16) | (0x1f << 0);
+ reg_val |= reg_val << 8;
+ writel(reg_val, &mctl_ctl->zqdr[1]);
+ writel(reg_val, &mctl_ctl->zqdr[2]);
+ } else {
+ int i;
+ u16 zq_val[6];
+ u8 val;
+
+ writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
+
+ for (i = 0; i < zq_count; i++) {
+ u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
+
+ writel((zq << 20) | (zq << 16) | (zq << 12) |
+ (zq << 8) | (zq << 4) | (zq << 0),
+ &mctl_ctl->zqcr);
+
+ writel(PIR_CLRSR, &mctl_ctl->pir);
+ mctl_phy_init(PIR_ZCAL);
+
+ zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
+ writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
+
+ writel(PIR_CLRSR, &mctl_ctl->pir);
+ mctl_phy_init(PIR_ZCAL);
+
+ val = readl(&mctl_ctl->zqdr[0]) >> 24;
+ zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
+ }
+
+ writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
+ writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
+ if (zq_count > 4)
+ writel((zq_val[5] << 16) | zq_val[4],
+ &mctl_ctl->zqdr[2]);
+ }
+}
+
+static void mctl_set_cr(uint16_t socid, struct dram_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ writel(MCTL_CR_BL8 | MCTL_CR_INTERLEAVED |
+#if defined CONFIG_SUNXI_DRAM_DDR3
+ MCTL_CR_DDR3 | MCTL_CR_2T |
+#elif defined CONFIG_SUNXI_DRAM_DDR2
+ MCTL_CR_DDR2 | MCTL_CR_2T |
+#elif defined CONFIG_SUNXI_DRAM_LPDDR3
+ MCTL_CR_LPDDR3 | MCTL_CR_1T |
+#else
+#error Unsupported DRAM type!
+#endif
+ (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) |
+ MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
+ (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
+ MCTL_CR_PAGE_SIZE(para->page_size) |
+ MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
+
+ if (socid == SOCID_R40) {
+ if (para->dual_rank)
+ panic("Dual rank memory not supported\n");
+
+ /* Mux pin to A15 address line for single rank memory. */
+ setbits_le32(&mctl_com->cr_r1, MCTL_CR_R1_MUX_A15);
+ }
+}
+
+static void mctl_sys_init(uint16_t socid, struct dram_para *para)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
+ clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
+ clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+ clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+ clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
+ if (socid == SOCID_A64 || socid == SOCID_R40)
+ clrbits_le32(&ccm->pll11_cfg, CCM_PLL11_CTRL_EN);
+ udelay(10);
+
+ clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
+ udelay(1000);
+
+ if (socid == SOCID_A64 || socid == SOCID_R40) {
+ clock_set_pll11(CONFIG_DRAM_CLK * 2 * 1000000, false);
+ clrsetbits_le32(&ccm->dram_clk_cfg,
+ CCM_DRAMCLK_CFG_DIV_MASK |
+ CCM_DRAMCLK_CFG_SRC_MASK,
+ CCM_DRAMCLK_CFG_DIV(1) |
+ CCM_DRAMCLK_CFG_SRC_PLL11 |
+ CCM_DRAMCLK_CFG_UPD);
+ } else if (socid == SOCID_H3 || socid == SOCID_H5) {
+ clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
+ clrsetbits_le32(&ccm->dram_clk_cfg,
+ CCM_DRAMCLK_CFG_DIV_MASK |
+ CCM_DRAMCLK_CFG_SRC_MASK,
+ CCM_DRAMCLK_CFG_DIV(1) |
+ CCM_DRAMCLK_CFG_SRC_PLL5 |
+ CCM_DRAMCLK_CFG_UPD);
+ }
+ mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
+
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+ setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
+ setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
+
+ setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
+ udelay(10);
+
+ writel(socid == SOCID_H5 ? 0x8000 : 0xc00e, &mctl_ctl->clken);
+ udelay(500);
+}
+
+/* These are more guessed based on some Allwinner code. */
+#define DX_GCR_ODT_DYNAMIC (0x0 << 4)
+#define DX_GCR_ODT_ALWAYS_ON (0x1 << 4)
+#define DX_GCR_ODT_OFF (0x2 << 4)
+
+static int mctl_channel_init(uint16_t socid, struct dram_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ unsigned int i;
+
+ mctl_set_cr(socid, para);
+ mctl_set_timing_params(socid, para);
+ mctl_set_master_priority(socid);
+
+ /* setting VTC, default disable all VT */
+ clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f);
+ if (socid == SOCID_H5)
+ setbits_le32(&mctl_ctl->pgcr[1], (1 << 24) | (1 << 26));
+ else
+ clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
+
+ /* increase DFI_PHY_UPD clock */
+ writel(PROTECT_MAGIC, &mctl_com->protect);
+ udelay(100);
+ clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16);
+ writel(0x0, &mctl_com->protect);
+ udelay(100);
+
+ /* set dramc odt */
+ for (i = 0; i < 4; i++) {
+ u32 clearmask = (0x3 << 4) | (0x1 << 1) | (0x3 << 2) |
+ (0x3 << 12) | (0x3 << 14);
+ u32 setmask = IS_ENABLED(CONFIG_DRAM_ODT_EN) ?
+ DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF;
+
+ if (socid == SOCID_H5) {
+ clearmask |= 0x2 << 8;
+ setmask |= 0x4 << 8;
+ }
+ clrsetbits_le32(&mctl_ctl->dx[i].gcr, clearmask, setmask);
+ }
+
+ /* AC PDR should always ON */
+ clrsetbits_le32(&mctl_ctl->aciocr, socid == SOCID_H5 ? (0x1 << 11) : 0,
+ 0x1 << 1);
+
+ /* set DQS auto gating PD mode */
+ setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);
+
+ if (socid == SOCID_H3) {
+ /* dx ddr_clk & hdr_clk dynamic mode */
+ clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
+
+ /* dphy & aphy phase select 270 degree */
+ clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
+ (0x1 << 10) | (0x2 << 8));
+ } else if (socid == SOCID_A64 || socid == SOCID_H5) {
+ /* dphy & aphy phase select ? */
+ clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
+ (0x0 << 10) | (0x3 << 8));
+ } else if (socid == SOCID_R40) {
+ /* dx ddr_clk & hdr_clk dynamic mode (tpr13[9] == 0) */
+ clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
+
+ /* dphy & aphy phase select ? */
+ clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
+ (0x0 << 10) | (0x3 << 8));
+ }
+
+ /* set half DQ */
+ if (!para->bus_full_width) {
+#if defined CONFIG_SUNXI_DRAM_DW_32BIT
+ writel(0x0, &mctl_ctl->dx[2].gcr);
+ writel(0x0, &mctl_ctl->dx[3].gcr);
+#elif defined CONFIG_SUNXI_DRAM_DW_16BIT
+ writel(0x0, &mctl_ctl->dx[1].gcr);
+#else
+#error Unsupported DRAM bus width!
+#endif
+ }
+
+ /* data training configuration */
+ clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24,
+ (para->dual_rank ? 0x3 : 0x1) << 24);
+
+ mctl_set_bit_delays(para);
+ udelay(50);
+
+ if (socid == SOCID_H3) {
+ mctl_h3_zq_calibration_quirk(para);
+
+ mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
+ PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
+ } else if (socid == SOCID_A64 || socid == SOCID_H5) {
+ clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ);
+
+ mctl_phy_init(PIR_ZCAL | PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
+ PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
+ /* no PIR_QSGATE for H5 ???? */
+ } else if (socid == SOCID_R40) {
+ clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ);
+
+ mctl_phy_init(PIR_ZCAL | PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
+ PIR_DRAMRST | PIR_DRAMINIT);
+ }
+
+ /* detect ranks and bus width */
+ if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) {
+ /* only one rank */
+ if (((readl(&mctl_ctl->dx[0].gsr[0]) >> 24) & 0x2)
+#if defined CONFIG_SUNXI_DRAM_DW_32BIT
+ || ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x2)
+#endif
+ ) {
+ clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
+ para->dual_rank = 0;
+ }
+
+ /* only half DQ width */
+#if defined CONFIG_SUNXI_DRAM_DW_32BIT
+ if (((readl(&mctl_ctl->dx[2].gsr[0]) >> 24) & 0x1) ||
+ ((readl(&mctl_ctl->dx[3].gsr[0]) >> 24) & 0x1)) {
+ writel(0x0, &mctl_ctl->dx[2].gcr);
+ writel(0x0, &mctl_ctl->dx[3].gcr);
+ para->bus_full_width = 0;
+ }
+#elif defined CONFIG_SUNXI_DRAM_DW_16BIT
+ if ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x1) {
+ writel(0x0, &mctl_ctl->dx[1].gcr);
+ para->bus_full_width = 0;
+ }
+#endif
+
+ mctl_set_cr(socid, para);
+ udelay(20);
+
+ /* re-train */
+ mctl_phy_init(PIR_QSGATE);
+ if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20))
+ return 1;
+ }
+
+ /* check the dramc status */
+ mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
+
+ /* liuke added for refresh debug */
+ setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
+ udelay(10);
+ clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
+ udelay(10);
+
+ /* set PGCR3, CKE polarity */
+ if (socid == SOCID_H3)
+ writel(0x00aa0060, &mctl_ctl->pgcr[3]);
+ else if (socid == SOCID_A64 || socid == SOCID_H5 || socid == SOCID_R40)
+ writel(0xc0aa0060, &mctl_ctl->pgcr[3]);
+
+ /* power down zq calibration module for power save */
+ setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN);
+
+ /* enable master access */
+ writel(0xffffffff, &mctl_com->maer);
+
+ return 0;
+}
+
+static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
+{
+ /* detect row address bits */
+ para->page_size = 512;
+ para->row_bits = 16;
+ para->bank_bits = 2;
+ mctl_set_cr(socid, para);
+
+ for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
+ if (mctl_mem_matches((1 << (para->row_bits + para->bank_bits)) * para->page_size))
+ break;
+
+ /* detect bank address bits */
+ para->bank_bits = 3;
+ mctl_set_cr(socid, para);
+
+ for (para->bank_bits = 2; para->bank_bits < 3; para->bank_bits++)
+ if (mctl_mem_matches((1 << para->bank_bits) * para->page_size))
+ break;
+
+ /* detect page size */
+ para->page_size = 8192;
+ mctl_set_cr(socid, para);
+
+ for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2)
+ if (mctl_mem_matches(para->page_size))
+ break;
+}
+
+/*
+ * The actual values used here are taken from Allwinner provided boot0
+ * binaries, though they are probably board specific, so would likely benefit
+ * from invidual tuning for each board. Apparently a lot of boards copy from
+ * some Allwinner reference design, so we go with those generic values for now
+ * in the hope that they are reasonable for most (all?) boards.
+ */
+#define SUN8I_H3_DX_READ_DELAYS \
+ {{ 18, 18, 18, 18, 18, 18, 18, 18, 18, 0, 0 }, \
+ { 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }, \
+ { 18, 18, 18, 18, 18, 18, 18, 18, 18, 0, 0 }, \
+ { 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }}
+#define SUN8I_H3_DX_WRITE_DELAYS \
+ {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 6 }}
+#define SUN8I_H3_AC_DELAYS \
+ { 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0 }
+
+#define SUN8I_R40_DX_READ_DELAYS \
+ {{ 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }, \
+ { 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }, \
+ { 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }, \
+ { 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 } }
+#define SUN8I_R40_DX_WRITE_DELAYS \
+ {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0 } }
+#define SUN8I_R40_AC_DELAYS \
+ { 0, 0, 3, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0 }
+
+#define SUN50I_A64_DX_READ_DELAYS \
+ {{ 16, 16, 16, 16, 17, 16, 16, 17, 16, 1, 0 }, \
+ { 17, 17, 17, 17, 17, 17, 17, 17, 17, 1, 0 }, \
+ { 16, 17, 17, 16, 16, 16, 16, 16, 16, 0, 0 }, \
+ { 17, 17, 17, 17, 17, 17, 17, 17, 17, 1, 0 }}
+#define SUN50I_A64_DX_WRITE_DELAYS \
+ {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 15 }, \
+ { 0, 0, 0, 0, 1, 1, 1, 1, 0, 10, 10 }, \
+ { 1, 0, 1, 1, 1, 1, 1, 1, 0, 11, 11 }, \
+ { 1, 0, 0, 1, 1, 1, 1, 1, 0, 12, 12 }}
+#define SUN50I_A64_AC_DELAYS \
+ { 5, 5, 13, 10, 2, 5, 3, 3, \
+ 0, 3, 3, 3, 1, 0, 0, 0, \
+ 3, 4, 0, 3, 4, 1, 4, 0, \
+ 1, 1, 0, 1, 13, 5, 4 }
+
+#define SUN8I_H5_DX_READ_DELAYS \
+ {{ 14, 15, 17, 17, 17, 17, 17, 18, 17, 3, 3 }, \
+ { 21, 21, 12, 22, 21, 21, 21, 21, 21, 3, 3 }, \
+ { 16, 19, 19, 17, 22, 22, 21, 22, 19, 3, 3 }, \
+ { 21, 21, 22, 22, 20, 21, 19, 19, 19, 3, 3 } }
+#define SUN8I_H5_DX_WRITE_DELAYS \
+ {{ 1, 2, 3, 4, 3, 4, 4, 4, 6, 6, 6 }, \
+ { 6, 6, 6, 5, 5, 5, 5, 5, 6, 6, 6 }, \
+ { 0, 2, 4, 2, 6, 5, 5, 5, 6, 6, 6 }, \
+ { 3, 3, 3, 2, 2, 1, 1, 1, 4, 4, 4 } }
+#define SUN8I_H5_AC_DELAYS \
+ { 0, 0, 5, 5, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 3, 3, 3, 3, \
+ 3, 3, 3, 3, 3, 3, 3, 3, \
+ 3, 3, 3, 3, 2, 0, 0 }
+
+unsigned long sunxi_dram_init(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ struct dram_para para = {
+ .dual_rank = 1,
+ .bus_full_width = 1,
+ .row_bits = 15,
+ .bank_bits = 3,
+ .page_size = 4096,
+
+#if defined(CONFIG_MACH_SUN8I_H3)
+ .dx_read_delays = SUN8I_H3_DX_READ_DELAYS,
+ .dx_write_delays = SUN8I_H3_DX_WRITE_DELAYS,
+ .ac_delays = SUN8I_H3_AC_DELAYS,
+#elif defined(CONFIG_MACH_SUN8I_R40)
+ .dx_read_delays = SUN8I_R40_DX_READ_DELAYS,
+ .dx_write_delays = SUN8I_R40_DX_WRITE_DELAYS,
+ .ac_delays = SUN8I_R40_AC_DELAYS,
+#elif defined(CONFIG_MACH_SUN50I)
+ .dx_read_delays = SUN50I_A64_DX_READ_DELAYS,
+ .dx_write_delays = SUN50I_A64_DX_WRITE_DELAYS,
+ .ac_delays = SUN50I_A64_AC_DELAYS,
+#elif defined(CONFIG_MACH_SUN50I_H5)
+ .dx_read_delays = SUN8I_H5_DX_READ_DELAYS,
+ .dx_write_delays = SUN8I_H5_DX_WRITE_DELAYS,
+ .ac_delays = SUN8I_H5_AC_DELAYS,
+#endif
+ };
+/*
+ * Let the compiler optimize alternatives away by passing this value into
+ * the static functions. This saves us #ifdefs, but still keeps the binary
+ * small.
+ */
+#if defined(CONFIG_MACH_SUN8I_H3)
+ uint16_t socid = SOCID_H3;
+#elif defined(CONFIG_MACH_SUN8I_R40)
+ uint16_t socid = SOCID_R40;
+ /* Currently we cannot support R40 with dual rank memory */
+ para.dual_rank = 0;
+#elif defined(CONFIG_MACH_SUN8I_V3S)
+ /* TODO: set delays and mbus priority for V3s */
+ uint16_t socid = SOCID_H3;
+#elif defined(CONFIG_MACH_SUN50I)
+ uint16_t socid = SOCID_A64;
+#elif defined(CONFIG_MACH_SUN50I_H5)
+ uint16_t socid = SOCID_H5;
+#endif
+
+ mctl_sys_init(socid, ¶);
+ if (mctl_channel_init(socid, ¶))
+ return 0;
+
+ if (para.dual_rank)
+ writel(0x00000303, &mctl_ctl->odtmap);
+ else
+ writel(0x00000201, &mctl_ctl->odtmap);
+ udelay(1);
+
+ /* odt delay */
+ if (socid == SOCID_H3)
+ writel(0x0c000400, &mctl_ctl->odtcfg);
+
+ if (socid == SOCID_A64 || socid == SOCID_H5 || socid == SOCID_R40) {
+ /* VTF enable (tpr13[8] == 1) */
+ setbits_le32(&mctl_ctl->vtfcr,
+ (socid != SOCID_A64 ? 3 : 2) << 8);
+ /* DQ hold disable (tpr13[26] == 1) */
+ clrbits_le32(&mctl_ctl->pgcr[2], (1 << 13));
+ }
+
+ /* clear credit value */
+ setbits_le32(&mctl_com->cccr, 1 << 31);
+ udelay(10);
+
+ mctl_auto_detect_dram_size(socid, ¶);
+ mctl_set_cr(socid, ¶);
+
+ return (1UL << (para.row_bits + para.bank_bits)) * para.page_size *
+ (para.dual_rank ? 2 : 1);
+}
--- /dev/null
+obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o
+obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK) += lpddr3_stock.o
+obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o
--- /dev/null
+#include <common.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/cpu.h>
+
+void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ u8 tccd = 1;
+ u8 tfaw = ns_to_t(50);
+ u8 trrd = max(ns_to_t(10), 2);
+ u8 trcd = ns_to_t(20);
+ u8 trc = ns_to_t(65);
+ u8 txp = 2;
+ u8 twtr = max(ns_to_t(8), 2);
+ u8 trtp = max(ns_to_t(8), 2);
+ u8 twr = max(ns_to_t(15), 3);
+ u8 trp = ns_to_t(15);
+ u8 tras = ns_to_t(45);
+ u16 trefi = ns_to_t(7800) / 32;
+ u16 trfc = ns_to_t(328);
+
+ u8 tmrw = 0;
+ u8 tmrd = 2;
+ u8 tmod = 12;
+ u8 tcke = 3;
+ u8 tcksrx = 5;
+ u8 tcksre = 5;
+ u8 tckesr = 4;
+ u8 trasmax = 27;
+
+ u8 tcl = 3; /* CL 6 */
+ u8 tcwl = 3; /* CWL 6 */
+ u8 t_rdata_en = 1;
+ u8 wr_latency = 1;
+
+ u32 tdinit0 = (400 * CONFIG_DRAM_CLK) + 1; /* 400us */
+ u32 tdinit1 = (500 * CONFIG_DRAM_CLK) / 1000 + 1; /* 500ns */
+ u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
+ u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
+
+ u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
+ u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
+ u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
+
+ /* set mode register */
+ writel(0x263, &mctl_ctl->mr[0]);
+ writel(0x4, &mctl_ctl->mr[1]);
+ writel(0x0, &mctl_ctl->mr[2]);
+ writel(0x0, &mctl_ctl->mr[3]);
+
+ /* set DRAM timing */
+ writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
+ DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
+ &mctl_ctl->dramtmg[0]);
+ writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
+ &mctl_ctl->dramtmg[1]);
+ writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
+ DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
+ &mctl_ctl->dramtmg[2]);
+ writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
+ &mctl_ctl->dramtmg[3]);
+ writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
+ DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
+ writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
+ DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
+ &mctl_ctl->dramtmg[5]);
+
+ /* set two rank timing */
+ clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
+ (0x66 << 8) | (0x10 << 0));
+
+ /* set PHY interface timing, write latency and read latency configure */
+ writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
+ (wr_latency << 0), &mctl_ctl->pitmg[0]);
+
+ /* set PHY timing, PTR0-2 use default */
+ writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
+ writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
+
+ /* set refresh timing */
+ writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
+}
--- /dev/null
+#include <common.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/cpu.h>
+
+void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ u8 tccd = 2;
+ u8 tfaw = ns_to_t(50);
+ u8 trrd = max(ns_to_t(10), 4);
+ u8 trcd = ns_to_t(15);
+ u8 trc = ns_to_t(53);
+ u8 txp = max(ns_to_t(8), 3);
+ u8 twtr = max(ns_to_t(8), 4);
+ u8 trtp = max(ns_to_t(8), 4);
+ u8 twr = max(ns_to_t(15), 3);
+ u8 trp = ns_to_t(15);
+ u8 tras = ns_to_t(38);
+ u16 trefi = ns_to_t(7800) / 32;
+ u16 trfc = ns_to_t(350);
+
+ u8 tmrw = 0;
+ u8 tmrd = 4;
+ u8 tmod = 12;
+ u8 tcke = 3;
+ u8 tcksrx = 5;
+ u8 tcksre = 5;
+ u8 tckesr = 4;
+ u8 trasmax = 24;
+
+ u8 tcl = 6; /* CL 12 */
+ u8 tcwl = 4; /* CWL 8 */
+ u8 t_rdata_en = 4;
+ u8 wr_latency = 2;
+
+ u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
+ u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
+ u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
+ u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
+
+ u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
+ u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
+ u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
+
+ /* set mode register */
+ writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */
+ writel(0x40, &mctl_ctl->mr[1]);
+ writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
+ writel(0x0, &mctl_ctl->mr[3]);
+
+ if (socid == SOCID_R40)
+ writel(0x3, &mctl_ctl->lp3mr11); /* odt_en[7:4] */
+
+ /* set DRAM timing */
+ writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
+ DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
+ &mctl_ctl->dramtmg[0]);
+ writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
+ &mctl_ctl->dramtmg[1]);
+ writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
+ DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
+ &mctl_ctl->dramtmg[2]);
+ writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
+ &mctl_ctl->dramtmg[3]);
+ writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
+ DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
+ writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
+ DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
+ &mctl_ctl->dramtmg[5]);
+
+ /* set two rank timing */
+ clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
+ ((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0));
+
+ /* set PHY interface timing, write latency and read latency configure */
+ writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
+ (wr_latency << 0), &mctl_ctl->pitmg[0]);
+
+ /* set PHY timing, PTR0-2 use default */
+ writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
+ writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
+
+ /* set refresh timing */
+ writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
+}
--- /dev/null
+#include <common.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/cpu.h>
+
+void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ u8 tccd = 2;
+ u8 tfaw = max(ns_to_t(50), 4);
+ u8 trrd = max(ns_to_t(10), 2);
+ u8 trcd = max(ns_to_t(24), 2);
+ u8 trc = ns_to_t(70);
+ u8 txp = max(ns_to_t(8), 2);
+ u8 twtr = max(ns_to_t(8), 2);
+ u8 trtp = max(ns_to_t(8), 2);
+ u8 twr = max(ns_to_t(15), 3);
+ u8 trp = max(ns_to_t(27), 2);
+ u8 tras = ns_to_t(42);
+ u16 trefi = ns_to_t(3900) / 32;
+ u16 trfc = ns_to_t(210);
+
+ u8 tmrw = 5;
+ u8 tmrd = 5;
+ u8 tmod = 12;
+ u8 tcke = 3;
+ u8 tcksrx = 5;
+ u8 tcksre = 5;
+ u8 tckesr = 5;
+ u8 trasmax = 24;
+
+ u8 tcl = 6; /* CL 12 */
+ u8 tcwl = 3; /* CWL 6 */
+ u8 t_rdata_en = 5;
+ u8 wr_latency = 2;
+
+ u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
+ u32 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */
+ u32 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 11us */
+ u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
+
+ u8 twtp = tcwl + 4 + twr + 1;
+ u8 twr2rd = tcwl + 4 + 1 + twtr;
+ u8 trd2wr = tcl + 4 + 5 - tcwl + 1;
+
+ /* set mode register */
+ writel(0xc3, &mctl_ctl->mr[1]); /* nWR=8, BL8 */
+ writel(0xa, &mctl_ctl->mr[2]); /* RL=12, WL=6 */
+ writel(0x2, &mctl_ctl->mr[3]); /* 40 0hms PD/PU */
+
+ /* set DRAM timing */
+ writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
+ DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
+ &mctl_ctl->dramtmg[0]);
+ writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
+ &mctl_ctl->dramtmg[1]);
+ writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
+ DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
+ &mctl_ctl->dramtmg[2]);
+ writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
+ &mctl_ctl->dramtmg[3]);
+ writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
+ DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
+ writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
+ DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
+ &mctl_ctl->dramtmg[5]);
+
+ /* set two rank timing */
+ clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
+ (0x66 << 8) | (0x10 << 0));
+
+ /* set PHY interface timing, write latency and read latency configure */
+ writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
+ (wr_latency << 0), &mctl_ctl->pitmg[0]);
+
+ /* set PHY timing, PTR0-2 use default */
+ writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
+ writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
+
+ /* set refresh timing */
+ writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
+}
S: Maintained
F: configs/nanopi_m1_defconfig
+NANOPI-M1 PLUS BOARD
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: configs/nanopi_m1_plus_defconfig
+
NANOPI-NEO BOARD
M: Jelle van der Waa <jelle@vdwaa.nl>
S: Maintained
F: configs/nanopi_neo_defconfig
+NANOPI-NEO2 BOARD
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: configs/nanopi_neo2_defconfig
+
NANOPI-NEO-AIR BOARD
M: Jelle van der Waa <jelle@vdwaa.nl>
S: Maintained
S: Maintained
F: configs/Nintendo_NES_Classic_Edition_defconfig
+ORANGEPI WIN/WIN PLUS BOARD
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: configs/orangepi_win_defconfig
+
ORANGEPI ZERO BOARD
M: Icenowy Zheng <icenowy@aosc.xyz>
S: Maintained
F: configs/orangepi_zero_defconfig
+ORANGEPI ZERO PLUS 2 BOARD
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: configs/orangepi_zero_plus2_defconfig
+
ORANGEPI PC 2 BOARD
M: Andre Przywara <andre.przywara@arm.com>
S: Maintained
S: Maintained
F: configs/Sinovoip_BPI_M3_defconfig
+SOPINE BOARD
+M: Icenowy Zheng <icenowy@aosc.io>
+S: Maintained
+F: configs/sopine_baseboard_defconfig
+
SUNCHIP CX-A99 BOARD
M: Rask Ingemann Lambertsen <rask@formelder.dk>
S: Maintained
for (i = 0; i < ums_count; i++)
free((void *)ums[i].name);
free(ums);
- ums = 0;
+ ums = NULL;
ums_count = 0;
}
return ret;
}
-int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
+static int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
const char *usb_controller;
# CONFIG_CONSOLE_MUX is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
-CONFIG_CMD_DHCP=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
# CONFIG_CONSOLE_MUX is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
-CONFIG_CMD_DHCP=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
-CONFIG_CMD_DHCP=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
-CONFIG_CMD_DHCP=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
-CONFIG_CMD_DHCP=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
-CONFIG_CMD_DHCP=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
-CONFIG_CMD_DHCP=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
-CONFIG_CMD_DHCP=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
-CONFIG_MMC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_BAUDRATE=38400
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_MMC=y
CONFIG_MTD=y
+CONFIG_MTD_NOR_FLASH=y
CONFIG_CFI_FLASH=y
CONFIG_DM_ETH=y
CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_TIMER=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
-CONFIG_MMC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_BAUDRATE=38400
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_MMC=y
+CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_ETH=y
CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_TIMER=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_AM33XX=y
-CONFIG_TARGET_AM335X_EVM=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_AM33XX=y
-CONFIG_TARGET_AM335X_EVM=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
CONFIG_DFU_RAM=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-# CONFIG_DM_MMC_OPS is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_AM33XX=y
-CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
-# CONFIG_DM_MMC_OPS is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_AM33XX=y
-CONFIG_TARGET_AM335X_EVM=y
CONFIG_NOR=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_AM33XX=y
-CONFIG_TARGET_AM335X_EVM=y
CONFIG_NOR=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NOR_BOOT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_AM33XX=y
-CONFIG_TARGET_AM335X_EVM=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_AM33XX=y
-CONFIG_TARGET_AM335X_EVM=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USBETH_SUPPORT=y
+# CONFIG_SPL_YMODEM_SUPPORT is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
-CONFIG_SPL_USB_GADGET_SUPPORT=y
-CONFIG_SPL_USBETH_SUPPORT=y
-# CONFIG_SPL_YMODEM_SUPPORT is not set
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_AM33XX=y
CONFIG_TI_SECURE_DEVICE=y
-CONFIG_TARGET_AM335X_EVM=y
CONFIG_ISW_ENTRY_ADDR=0x40300350
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
-# CONFIG_DM_MMC_OPS is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_USE_TINY_PRINTF=y
CONFIG_RSA=y
-CONFIG_SPL_OF_LIBFDT=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_IGEP003X=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0033"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SERIES=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SHC_ICT=y
CONFIG_SERIES=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SHC_NETBOOT=y
CONFIG_SERIES=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SERIES=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SHC_SDBOOT=y
CONFIG_SERIES=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SHC_SDBOOT=y
CONFIG_SERIES=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
# CONFIG_AUTOBOOT is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
# CONFIG_SPL_GPIO_SUPPORT is not set
-CONFIG_OMAP34XX=y
CONFIG_TARGET_AM3517_CRANE=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
# CONFIG_SPL_GPIO_SUPPORT is not set
-CONFIG_OMAP34XX=y
CONFIG_TARGET_AM3517_EVM=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_AM43XX=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_TARGET_AM43XX_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_SPL_LOAD_FIT=y
CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-# CONFIG_DM_MMC_OPS is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_AM43XX=y
-CONFIG_TARGET_AM43XX_EVM=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_AM43XX=y
-CONFIG_TARGET_AM43XX_EVM=y
CONFIG_ISW_ENTRY_ADDR=0x30000000
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_AM43XX=y
-CONFIG_TARGET_AM43XX_EVM=y
CONFIG_ISW_ENTRY_ADDR=0x40300350
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-# CONFIG_DM_MMC_OPS is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_AM43XX=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_TI_SECURE_DEVICE=y
-CONFIG_TARGET_AM43XX_EVM=y
CONFIG_ISW_ENTRY_ADDR=0x403018e0
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-# CONFIG_DM_MMC_OPS is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_OMAP54XX=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_TARGET_AM57XX_EVM=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ARMV7_LPAE=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_ARMV7_LPAE=y
CONFIG_DEFAULT_DEVICE_TREE="am572x-idk"
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-# CONFIG_DM_MMC_OPS is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_OMAP54XX=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_TARGET_AM57XX_EVM=y
CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ARMV7_LPAE=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_ARMV7_LPAE=y
CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-# CONFIG_DM_MMC_OPS is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ARCH_ATH79=y
CONFIG_DEFAULT_DEVICE_TREE="ap121"
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_AR933X=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_AR933X=y
CONFIG_DEBUG_UART_BASE=0xb8020000
CONFIG_DEBUG_UART_CLOCK=25000000
CONFIG_ARCH_ATH79=y
CONFIG_TARGET_AP143=y
CONFIG_DEFAULT_DEVICE_TREE="ap143"
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PINCTRL=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xb8020000
CONFIG_DEBUG_UART_CLOCK=25000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
-CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
-CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek_2mmc"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek_2mmc"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9M10G45EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9M10G45EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
+CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CRC32_VERIFY=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
-CONFIG_CRC32_VERIFY=y
CONFIG_CMD_HASH=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_BAV_VERSION=1
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_BAV_VERSION=2
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
-CONFIG_FAT_WRITE=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
-CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
CONFIG_BOOTDELAY=-2
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
-CONFIG_OMAP_WATCHDOG=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
CONFIG_BOOTDELAY=-2
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
-CONFIG_OMAP_WATCHDOG=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
CONFIG_SPI_BOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
-CONFIG_OMAP_WATCHDOG=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_TARGET_BRXRE1=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
CONFIG_BOOTDELAY=-2
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_CAIRO=y
CONFIG_BOOTDELAY=-2
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
+CONFIG_DEBUG_UART=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry"
+CONFIG_DEBUG_UART=y
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_VENDOR_GOOGLE=y
CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
CONFIG_TARGET_CHROMEBOOK_LINK64=y
+CONFIG_DEBUG_UART=y
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_HAVE_MRC=y
CONFIG_SMP=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_VENDOR_GOOGLE=y
CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
CONFIG_TARGET_CHROMEBOOK_LINK=y
+CONFIG_DEBUG_UART=y
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_HAVE_MRC=y
CONFIG_SMP=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
+CONFIG_DEBUG_UART=y
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
-CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_DISPLAY_ROCKCHIP_EDP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_VENDOR_GOOGLE=y
CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
CONFIG_TARGET_CHROMEBOOK_SAMUS=y
+CONFIG_DEBUG_UART=y
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_HAVE_MRC=y
CONFIG_HAVE_REFCODE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
+CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
-CONFIG_EFI_PARTITION=y
-# CONFIG_PARTITION_UUIDS is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH=y
CONFIG_PCI=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-# CONFIG_CMD_BMODE is not set
CONFIG_VIDEO=y
+# CONFIG_CMD_BMODE is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
CONFIG_BOOTDELAY=3
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CM-T335 # "
CONFIG_CMD_BOOTZ=y
CONFIG_ARM=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_CM_T3517=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_ARM=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_CM_T35=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_ARM=y
-CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CM-T43 # "
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MX7=y
CONFIG_TARGET_COLIBRI_IMX7=y
+CONFIG_VIDEO=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
-CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D"
CONFIG_BOOTDELAY=1
CONFIG_ARM=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_VF610=y
-CONFIG_TARGET_COLIBRI_VF=y
CONFIG_VIDEO=y
+CONFIG_TARGET_COLIBRI_VF=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND"
CONFIG_BOOTDELAY=1
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_ARCH_BMIPS=y
-CONFIG_BAUDRATE=115200
-CONFIG_BCM6328_POWER_DOMAIN=y
-CONFIG_BCM6345_CLK=y
-CONFIG_BCM6345_SERIAL=y
-CONFIG_BMIPS_BOOT_RAM=y
-CONFIG_BOARD_COMTREND_AR5387UN=y
-# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTM=y
+CONFIG_SOC_BMIPS_BCM6328=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="AR-5387un # "
CONFIG_CMD_CPU=y
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_EDITENV is not set
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
-CONFIG_CMD_LED=y
-CONFIG_CMD_LICENSE=y
-CONFIG_CMD_LOADB=y
-# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_MISC is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un"
-CONFIG_DISPLAY_CPUINFO=y
+# CONFIG_CMD_MISC is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_GPIO=y
-CONFIG_DM_RESET=y
-CONFIG_DM_SERIAL=y
-CONFIG_HUSH_PARSER=y
CONFIG_LED=y
CONFIG_LED_BCM6328=y
CONFIG_LED_BLINK=y
-CONFIG_MIPS=y
-# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
-# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
-CONFIG_MIPS_BOOT_FDT=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_POWER_DOMAIN=y
-CONFIG_RESET=y
+CONFIG_BCM6328_POWER_DOMAIN=y
+CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
-CONFIG_SOC_BMIPS_BCM6328=y
# CONFIG_SPL_SERIAL_PRESENT is not set
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_NO_FLASH=y
-CONFIG_SYS_PROMPT="AR-5387un # "
-CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_DM_SERIAL=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_ARCH_BMIPS=y
-CONFIG_BAUDRATE=115200
-CONFIG_BCM6345_CLK=y
-CONFIG_BCM6345_GPIO=y
-CONFIG_BCM6345_SERIAL=y
-CONFIG_BMIPS_BOOT_RAM=y
-CONFIG_BOARD_COMTREND_CT5361=y
-CONFIG_CFI_FLASH=y
-# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTM=y
+CONFIG_SOC_BMIPS_BCM6348=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="comtrend,ct-5361"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="CT-5361 # "
CONFIG_CMD_CPU=y
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_EDITENV is not set
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_EXPORTENV is not set
-CONFIG_CMD_FLASH=y
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
-CONFIG_CMD_LED=y
-CONFIG_CMD_LICENSE=y
-CONFIG_CMD_LOADB=y
-# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_MISC is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_DEFAULT_DEVICE_TREE="comtrend,ct-5361"
-CONFIG_DISPLAY_CPUINFO=y
+# CONFIG_CMD_MISC is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_GPIO=y
-CONFIG_DM_RESET=y
-CONFIG_DM_SERIAL=y
-CONFIG_HUSH_PARSER=y
+CONFIG_BCM6345_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_MIPS=y
-# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
-# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
-CONFIG_MIPS_BOOT_FDT=y
CONFIG_MTD=y
-CONFIG_MTD_DEVICE=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_RESET=y
+CONFIG_CFI_FLASH=y
+CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
-CONFIG_SOC_BMIPS_BCM6348=y
# CONFIG_SPL_SERIAL_PRESENT is not set
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_PROMPT="CT-5361 # "
-CONFIG_SYS_TEXT_BASE=0x80010000
-CONFIG_WDT=y
+CONFIG_DM_SERIAL=y
+CONFIG_BCM6345_SERIAL=y
CONFIG_WDT_BCM6345=y
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_ARCH_BMIPS=y
-CONFIG_BAUDRATE=115200
-CONFIG_BCM6328_POWER_DOMAIN=y
-CONFIG_BCM6345_CLK=y
-CONFIG_BCM6345_SERIAL=y
-CONFIG_BMIPS_BOOT_RAM=y
-CONFIG_BOARD_COMTREND_VR3032U=y
-# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTM=y
+CONFIG_SOC_BMIPS_BCM63268=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="VR-3032u # "
CONFIG_CMD_CPU=y
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_EDITENV is not set
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
-CONFIG_CMD_LED=y
-CONFIG_CMD_LICENSE=y
-CONFIG_CMD_LOADB=y
-# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_MISC is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u"
-CONFIG_DISPLAY_CPUINFO=y
+# CONFIG_CMD_MISC is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_GPIO=y
-CONFIG_DM_RESET=y
-CONFIG_DM_SERIAL=y
-CONFIG_HUSH_PARSER=y
CONFIG_LED=y
CONFIG_LED_BCM6328=y
CONFIG_LED_BLINK=y
-CONFIG_MIPS=y
-# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
-# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
-CONFIG_MIPS_BOOT_FDT=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_POWER_DOMAIN=y
-CONFIG_RESET=y
+CONFIG_BCM6328_POWER_DOMAIN=y
+CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
-CONFIG_SOC_BMIPS_BCM63268=y
# CONFIG_SPL_SERIAL_PRESENT is not set
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_NO_FLASH=y
-CONFIG_SYS_PROMPT="VR-3032u # "
-CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_DM_SERIAL=y
+CONFIG_BCM6345_SERIAL=y
CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y
CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
CONFIG_INTERNAL_UART=y
+CONFIG_DEBUG_UART=y
CONFIG_HAVE_INTEL_ME=y
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_SYS_NS16550=y
CONFIG_VENDOR_CONGATEC=y
CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y
CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
+CONFIG_DEBUG_UART=y
CONFIG_HAVE_INTEL_ME=y
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_SYS_NS16550=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-38x-controlcenterdc"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-375-db"
+CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MVPP2=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xf1012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-385-amc"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PCI=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp"
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PCI=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
+CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PCI=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_DEVKIT8000=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_VENDOR_DFI=y
CONFIG_DEFAULT_DEVICE_TREE="dfi-bt700-q7x-151"
CONFIG_TARGET_DFI_BT700=y
+CONFIG_DEBUG_UART=y
CONFIG_HAVE_INTEL_ME=y
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_OMAP54XX=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_TARGET_DRA7XX_EVM=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ARMV7_LPAE=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_ARMV7_LPAE=y
CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
-CONFIG_BLK=y
+CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DM_SCSI=y
CONFIG_DWC_AHCI=y
-CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_PCF8575_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-# CONFIG_DM_MMC_OPS is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_ETH=y
+CONFIG_SPL_PHY=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_PALMAS=y
CONFIG_PMIC_LP873X=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_SPL_PHY=y
-CONFIG_PIPE3_PHY=y
-CONFIG_SPL_PIPE3_PHY=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_OMAP54XX=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ARMV7_LPAE=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_ARMV7_LPAE=y
CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_PCF8575_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-# CONFIG_DM_MMC_OPS is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_ETH=y
+CONFIG_SPL_PHY=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_PALMAS=y
CONFIG_PMIC_LP873X=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_SPL_PHY=y
-CONFIG_PIPE3_PHY=y
-CONFIG_SPL_PIPE3_PHY=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_G_DNL_MANUFACTURER="Siemens AG"
CONFIG_G_DNL_VENDOR_NUM=0x0908
CONFIG_G_DNL_PRODUCT_NUM=0x02d2
-CONFIG_OMAP_WATCHDOG=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PCI=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ARM=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_ECO5PK=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_VENDOR_EFI=y
CONFIG_DEFAULT_DEVICE_TREE="efi"
CONFIG_TARGET_EFI=y
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DM_PCI=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_EFI_CONSOLE=y
CONFIG_DEBUG_UART_BASE=0
CONFIG_DEBUG_UART_CLOCK=0
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_G_DNL_MANUFACTURER="Siemens AG"
CONFIG_G_DNL_VENDOR_NUM=0x0908
CONFIG_G_DNL_PRODUCT_NUM=0x02d2
-CONFIG_OMAP_WATCHDOG=y
CONFIG_ASPEED_AST2500=y
CONFIG_TARGET_EVB_AST2500=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb"
+CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_PRE_CON_BUF_ADDR=0x1e720000
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_I2C=y
CONFIG_REGMAP=y
CONFIG_CLK=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_ASPEED=y
+CONFIG_PINCTRL=y
CONFIG_RAM=y
+CONFIG_DM_RESET=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_TIMER=y
CONFIG_WDT=y
-CONFIG_DM_RESET=y
-CONFIG_PINCTRL=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_ASPEED=y
-CONFIG_CMD_I2C=y
CONFIG_ROCKCHIP_RK3368=y
CONFIG_TARGET_EVB_PX5=y
CONFIG_DEFAULT_DEVICE_TREE="rk3368-px5-evb"
-CONFIG_HUSH_PARSER=y
+CONFIG_DEBUG_UART=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_FASTBOOT=y
CONFIG_ANDROID_BOOT_IMAGE=y
-CONFIG_CMD_BOOTRK=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ROCKCHIP_RK3368=y
CONFIG_RAM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xFF1c0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_TARGET_EVB_RK3036=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
+CONFIG_DEBUG_UART=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
CONFIG_PINCTRL_ROCKCHIP_RK3036=y
CONFIG_RAM=y
# CONFIG_SPL_SERIAL_PRESENT is not set
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_TARGET_EVB_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb"
+CONFIG_DEBUG_UART=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_REGMAP=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_RAM=y
CONFIG_BAUDRATE=1500000
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
-CONFIG_USE_TINY_PRINTF=y
-CONFIG_ERRNO_STR=y
CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_CMD_USB=y
-CONFIG_USB_STORAGE=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_RK=y
+CONFIG_USB_STORAGE=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_ERRNO_STR=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_OF_PLATDATA=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_RK808=y
-CONFIG_REGULATOR_RK808=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_RV1108=y
CONFIG_TARGET_EVB_RV1108=y
CONFIG_DEFAULT_DEVICE_TREE="rv1108-evb"
+CONFIG_DEBUG_UART=y
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_SF=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_RAM=y
CONFIG_BAUDRATE=1500000
# CONFIG_SPL_SERIAL_PRESENT is not set
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x10210000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_TARGET_FENNEC_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-fennec"
+CONFIG_DEBUG_UART=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_TARGET_FIREFLY_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
+CONFIG_DEBUG_UART=y
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_RK3399=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_RK3368=y
CONFIG_TARGET_GEEKBOX=y
CONFIG_DEFAULT_DEVICE_TREE="rk3368-geekbox"
-CONFIG_HUSH_PARSER=y
+CONFIG_DEBUG_UART=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_CMD_IMLS is not set
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
-CONFIG_SYSRESET=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ROCKCHIP_RK3368=y
CONFIG_RAM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xFF690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYSRESET=y
CONFIG_ERRNO_STR=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_CMD_HDMIDETECT=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_CMD_HDMIDETECT=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_CMD_HDMIDETECT=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_ARCH_BMIPS=y
-CONFIG_BAUDRATE=115200
-CONFIG_BCM6345_CLK=y
-CONFIG_BCM6345_GPIO=y
-CONFIG_BCM6345_SERIAL=y
-CONFIG_BMIPS_BOOT_RAM=y
-CONFIG_BOARD_HUAWEI_HG556A=y
-CONFIG_CFI_FLASH=y
-# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTM=y
+CONFIG_SOC_BMIPS_BCM6358=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="HG556a # "
CONFIG_CMD_CPU=y
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_EDITENV is not set
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_EXPORTENV is not set
-CONFIG_CMD_FLASH=y
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
-CONFIG_CMD_LED=y
-CONFIG_CMD_LICENSE=y
-CONFIG_CMD_LOADB=y
-# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_MISC is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a"
-CONFIG_DISPLAY_CPUINFO=y
+# CONFIG_CMD_MISC is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_GPIO=y
-CONFIG_DM_RESET=y
-CONFIG_DM_SERIAL=y
-CONFIG_HUSH_PARSER=y
+CONFIG_BCM6345_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_MIPS=y
-# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
-# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
-CONFIG_MIPS_BOOT_FDT=y
CONFIG_MTD=y
-CONFIG_MTD_DEVICE=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_RESET=y
+CONFIG_CFI_FLASH=y
+CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
-CONFIG_SOC_BMIPS_BCM6358=y
# CONFIG_SPL_SERIAL_PRESENT is not set
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_PROMPT="HG556a # "
-CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_DM_SERIAL=y
+CONFIG_BCM6345_SERIAL=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_UBI=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-# CONFIG_CMD_BMODE is not set
CONFIG_VIDEO=y
+# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
-CONFIG_OF_LIST="imx6q-icore imx6dl-icore"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_LIST="imx6q-icore imx6dl-icore"
# CONFIG_BLK is not set
CONFIG_SYS_I2C_MXC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs"
-CONFIG_OF_LIST="imx6q-icore-rqs imx6dl-icore-rqs"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_LIST="imx6q-icore-rqs imx6dl-icore-rqs"
# CONFIG_BLK is not set
CONFIG_SYS_I2C_MXC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_ARM=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_SYS_TEXT_BASE=0x0c000000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_K2E_EVM=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPT is not set
CONFIG_ARM=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_SYS_TEXT_BASE=0x0c000060
-CONFIG_TARGET_K2E_EVM=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_TI_SECURE_DEVICE=y
+CONFIG_TARGET_K2E_EVM=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARM=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_SYS_TEXT_BASE=0x0c000000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_K2G_EVM=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_MMC=y
-# CONFIG_DM_MMC_OPS is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_SYS_TEXT_BASE=0x0c000060
-CONFIG_TARGET_K2G_EVM=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_TI_SECURE_DEVICE=y
+CONFIG_TARGET_K2G_EVM=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
-CONFIG_FIT=y
-CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_MMC=y
-# CONFIG_DM_MMC_OPS is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_SYS_TEXT_BASE=0x0c000000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_K2HK_EVM=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_ARM=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_SYS_TEXT_BASE=0x0c000060
-CONFIG_TARGET_K2HK_EVM=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_TI_SECURE_DEVICE=y
+CONFIG_TARGET_K2HK_EVM=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARM=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_SYS_TEXT_BASE=0x0c000000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_K2L_EVM=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm"
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_CMD_IMMAP=y
CONFIG_TARGET_KMP204X=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PPC=y
CONFIG_MPC83xx=y
-CONFIG_CMD_IMMAP=y
CONFIG_TARGET_KM8360=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_PPC=y
CONFIG_MPC83xx=y
-CONFIG_CMD_IMMAP=y
CONFIG_TARGET_KM8360=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_CMD_IMMAP=y
CONFIG_TARGET_KMP204X=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PPC=y
CONFIG_MPC83xx=y
-CONFIG_CMD_IMMAP=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_PPC=y
CONFIG_MPC83xx=y
-CONFIG_CMD_IMMAP=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_PPC=y
CONFIG_MPC83xx=y
-CONFIG_CMD_IMMAP=y
CONFIG_TARGET_SUVD3=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_PPC=y
CONFIG_MPC83xx=y
-CONFIG_CMD_IMMAP=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_PPC=y
CONFIG_MPC83xx=y
-CONFIG_CMD_IMMAP=y
CONFIG_TARGET_SUVD3=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
-CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_CRYPTO_SUPPORT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_NAND_BOOT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_TARGET_LS2080AQDS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
-CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
-CONFIG_FSL_LS_PPA=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
-CONFIG_SPL_MMC_SUPPORT=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_NAND_BOOT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
-CONFIG_CMD_GREPENV=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
CONFIG_FSL_DSPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
+CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
-CONFIG_CMD_GREPENV=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
CONFIG_FSL_DSPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
+CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_TARGET_M53EVK=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
-# CONFIG_CMD_BMODE is not set
CONFIG_VIDEO=y
+# CONFIG_CMD_BMODE is not set
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aries/m53evk/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm"
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART_SHIFT=2
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
# CONFIG_SPL_GPIO_SUPPORT is not set
-CONFIG_OMAP34XX=y
CONFIG_TARGET_MCX=y
CONFIG_VIDEO=y
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
CONFIG_TARGET_MINNOWMAX=y
CONFIG_INTERNAL_UART=y
+CONFIG_DEBUG_UART=y
CONFIG_HAVE_INTEL_ME=y
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y
CONFIG_RTL8169=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_SYS_NS16550=y
CONFIG_TARGET_MIQI_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-miqi"
+CONFIG_DEBUG_UART=y
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ARM=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_MT_VENTOUX=y
CONFIG_VIDEO=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_MVEBU_ARMADA_37XX=y
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-db"
+CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_37XX=y
# CONFIG_SPL_SERIAL_PRESENT is not set
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_MVEBU_A3700_UART=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=25804800
CONFIG_TARGET_MVEBU_ARMADA_8K=y
CONFIG_DEFAULT_DEVICE_TREE="armada-7040-db-nand"
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_8K=y
# CONFIG_SPL_SERIAL_PRESENT is not set
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xf0512000
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_TARGET_MVEBU_ARMADA_8K=y
CONFIG_DEFAULT_DEVICE_TREE="armada-7040-db"
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_8K=y
# CONFIG_SPL_SERIAL_PRESENT is not set
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xf0512000
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_TARGET_MVEBU_ARMADA_8K=y
CONFIG_DEFAULT_DEVICE_TREE="armada-8040-db"
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_8K=y
# CONFIG_SPL_SERIAL_PRESENT is not set
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xf0512000
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_MVEBU_ARMADA_37XX=y
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-espressobin"
+CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_PHYLIB=y
CONFIG_MVEBU_COMPHY_SUPPORT=y
# CONFIG_SPL_SERIAL_PRESENT is not set
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_MVEBU_A3700_UART=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=25804800
CONFIG_TARGET_MVEBU_ARMADA_8K=y
CONFIG_DEFAULT_DEVICE_TREE="armada-8040-mcbin"
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_PINCTRL_ARMADA_8K=y
CONFIG_DM_REGULATOR_FIXED=y
# CONFIG_SPL_SERIAL_PRESENT is not set
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xf0512000
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_TARGET_MX51EVK=y
-# CONFIG_CMD_BMODE is not set
CONFIG_VIDEO=y
+# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_TARGET_MX53CX9020=y
-# CONFIG_CMD_BMODE is not set
CONFIG_VIDEO=y
+# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx53-cx9020"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/beckhoff/mx53cx9020/imximage.cfg"
CONFIG_BOOTDELAY=1
CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_TARGET_MX53LOCO=y
-# CONFIG_CMD_BMODE is not set
CONFIG_VIDEO=y
+# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
# CONFIG_CMD_BMODE is not set
CONFIG_CMD_HDMIDETECT=y
-CONFIG_VIDEO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SXSABRESD=y
-# CONFIG_CMD_BMODE is not set
CONFIG_VIDEO=y
+# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-# CONFIG_CMD_BMODE is not set
CONFIG_VIDEO=y
+# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
CONFIG_TARGET_MX7DSABRESD=y
+CONFIG_VIDEO=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
# CONFIG_CMD_BMODE is not set
-CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
CONFIG_BOOTDELAY=3
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PH13"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_USB_EHCI_HCD=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881977
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
+# CONFIG_VIDEO_DE2 is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo-air"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_EHCI_HCD=y
-# CONFIG_VIDEO_DE2 is not set
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
+# CONFIG_VIDEO_DE2 is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
-# CONFIG_VIDEO_DE2 is not set
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_ARCH_BMIPS=y
-CONFIG_BAUDRATE=115200
-CONFIG_BCM6345_CLK=y
-CONFIG_BCM6345_GPIO=y
-CONFIG_BCM6345_SERIAL=y
-CONFIG_BMIPS_BOOT_RAM=y
-CONFIG_BOARD_NETGEAR_CG3100D=y
-# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTM=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="netgear,cg3100d"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="CG3100D # "
CONFIG_CMD_CPU=y
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_EDITENV is not set
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
-CONFIG_CMD_LED=y
-CONFIG_CMD_LICENSE=y
-CONFIG_CMD_LOADB=y
-# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_MISC is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_DEFAULT_DEVICE_TREE="netgear,cg3100d"
-CONFIG_DISPLAY_CPUINFO=y
+# CONFIG_CMD_MISC is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_GPIO=y
-CONFIG_DM_RESET=y
-CONFIG_DM_SERIAL=y
-CONFIG_HUSH_PARSER=y
+CONFIG_BCM6345_GPIO=y
CONFIG_LED=y
CONFIG_LED_BCM6328=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
-CONFIG_MIPS=y
-# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
-# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
-CONFIG_MIPS_BOOT_FDT=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_RESET=y
+CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
-CONFIG_SOC_BMIPS_BCM3380=y
# CONFIG_SPL_SERIAL_PRESENT is not set
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_NO_FLASH=y
-CONFIG_SYS_PROMPT="CG3100D # "
-CONFIG_SYS_TEXT_BASE=0x80010000
-CONFIG_WDT=y
+CONFIG_DM_SERIAL=y
+CONFIG_BCM6345_SERIAL=y
CONFIG_WDT_BCM6345=y
CONFIG_ARM=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_NOKIA_RX51=y
CONFIG_VIDEO=y
CONFIG_BOOTDELAY=30
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_CMD_HDMIDETECT=y
-CONFIG_VIDEO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
CONFIG_TARGET_ODROID_C2=y
CONFIG_IDENT_STRING=" odroid-c2"
CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
+CONFIG_DEBUG_UART=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_BDI is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXBB=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_BEAGLE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_ARM=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_EVM=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_ARM=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_TAO3530=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA"
CONFIG_BOOTDELAY=3
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_LOGIC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit"
# CONFIG_BLK is not set
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-# CONFIG_DM_MMC_OPS is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MMC_OMAP36XX_PINS=y
CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_OVERO=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_PANDORA=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_ZOOM1=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-# CONFIG_CMD_BMODE is not set
CONFIG_VIDEO=y
+# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-opos6uldev"
CONFIG_BOOTDELAY=5
# CONFIG_CONSOLE_MUX is not set
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
CONFIG_DRAM_ODT_EN=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-lite"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_DRAM_ODT_EN=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_DRAM_ZQ=3881977
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_DRAM_ODT_EN=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus2e"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
CONFIG_SATAPWR="PG11"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I=y
+CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_SPI_SUNXI=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
+# CONFIG_VIDEO_DE2 is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SPL_SPI_SUNXI=y
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
-# CONFIG_VIDEO_DE2 is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881977
+CONFIG_MMC0_CD_PIN="PH13"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="REV1"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="REV3"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="pepper# "
CONFIG_CMD_BOOTZ=y
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
-CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus"
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_TARGET_POPMETAL_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-popmetal"
+CONFIG_DEBUG_UART=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
CONFIG_VIDEO=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-pxm50"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_SYS_CONSOLE_BG_COL=0xff
CONFIG_SYS_CONSOLE_FG_COL=0x00
-CONFIG_OMAP_WATCHDOG=y
CONFIG_X86_RUN_64BIT=y
CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
CONFIG_TARGET_QEMU_X86_64=y
+CONFIG_DEBUG_UART=y
CONFIG_SMP=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_SYS_NS16550=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SALVATOR_X=y
-CONFIG_DEFAULT_FDT_FILE=r8a7795-salvator-x.dtb
+CONFIG_DEFAULT_FDT_FILE="r8a7795-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_FDT=y
-CONFIG_R8A7795=y
-CONFIG_SH_SDHI=y
# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_EDITENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_NET=y
-CONFIG_CMD_NFS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_USB=y
+CONFIG_SH_SDHI=y
+CONFIG_DM_ETH=y
+CONFIG_RENESAS_RAVB=y
CONFIG_USB=y
-CONFIG_USB_HOST=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_USB_EHCI_RCAR_GEN3=y
-CONFIG_DOS_PARTITION=y
-CONFIG_MMC=y
-CONFIG_GENERIC_MMC=y
CONFIG_OF_LIBFDT=y
-CONFIG_DM_ETH=y
-CONFIG_RENESAS_RAVB=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
+CONFIG_R8A7796=y
CONFIG_TARGET_SALVATOR_X=y
-CONFIG_DEFAULT_FDT_FILE=r8a7796-salvator-x.dtb
+CONFIG_DEFAULT_FDT_FILE="r8a7796-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_FDT=y
-CONFIG_R8A7796=y
-CONFIG_SH_SDHI=y
# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_EDITENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_NET=y
-CONFIG_CMD_NFS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_USB=y
+CONFIG_SH_SDHI=y
+CONFIG_DM_ETH=y
+CONFIG_RENESAS_RAVB=y
CONFIG_USB=y
-CONFIG_USB_HOST=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_USB_EHCI_RCAR_GEN3=y
-CONFIG_DOS_PARTITION=y
-CONFIG_MMC=y
-CONFIG_GENERIC_MMC=y
CONFIG_OF_LIBFDT=y
-CONFIG_DM_ETH=y
-CONFIG_RENESAS_RAVB=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_G_DNL_MANUFACTURER="Siemens AG"
CONFIG_G_DNL_VENDOR_NUM=0x0908
CONFIG_G_DNL_PRODUCT_NUM=0x02d2
-CONFIG_OMAP_WATCHDOG=y
CONFIG_TARGET_ROCK2=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock2-square"
+CONFIG_DEBUG_UART=y
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_TARGET_ROCK=y
CONFIG_SPL_STACK_R_ADDR=0x60080000
CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
+CONFIG_DEBUG_UART=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_RAM=y
# CONFIG_TPL_DM_SERIAL is not set
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x20064000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
CONFIG_VIDEO=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-rut"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_ARCH_BMIPS=y
-CONFIG_BAUDRATE=115200
-CONFIG_BCM6345_CLK=y
-CONFIG_BCM6345_GPIO=y
-CONFIG_BCM6345_SERIAL=y
-CONFIG_BMIPS_BOOT_RAM=y
-CONFIG_BOARD_SAGEM_FAST1704=y
-# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTM=y
+CONFIG_SOC_BMIPS_BCM6338=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="sagem,f@st1704"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="F@ST1704 # "
CONFIG_CMD_CPU=y
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_EDITENV is not set
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
-CONFIG_CMD_LED=y
-CONFIG_CMD_LICENSE=y
-CONFIG_CMD_LOADB=y
-# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_MISC is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_DEFAULT_DEVICE_TREE="sagem,f@st1704"
-CONFIG_DISPLAY_CPUINFO=y
+# CONFIG_CMD_MISC is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_GPIO=y
-CONFIG_DM_RESET=y
-CONFIG_DM_SERIAL=y
-CONFIG_HUSH_PARSER=y
+CONFIG_BCM6345_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_MIPS=y
-# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
-# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
-CONFIG_MIPS_BOOT_FDT=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_RESET=y
+CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
-CONFIG_SOC_BMIPS_BCM6338=y
# CONFIG_SPL_SERIAL_PRESENT is not set
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_NO_FLASH=y
-CONFIG_SYS_PROMPT="F@ST1704 # "
-CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_DM_SERIAL=y
+CONFIG_BCM6345_SERIAL=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xf8020000
CONFIG_DEBUG_UART_CLOCK=83000000
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xf8020000
CONFIG_DEBUG_UART_CLOCK=83000000
CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=88000000
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=88000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=88000000
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=88000000
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=88000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=88000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_USER_COUNT=32
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_SANDBOX=y
+CONFIG_PHY=y
+CONFIG_PHY_SANDBOX=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_ROCKCHIP_RK3036=y
CONFIG_CONSOLE_TRUETYPE=y
CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
CONFIG_VIDEO_SANDBOX_SDL=y
+CONFIG_WDT=y
+CONFIG_WDT_SANDBOX=y
CONFIG_FS_CBFS=y
CONFIG_FS_CRAMFS=y
-CONFIG_PHY=y
-CONFIG_PHY_SANDBOX=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
CONFIG_LZ4=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
CONFIG_UT_ENV=y
-CONFIG_WDT=y
-CONFIG_WDT_SANDBOX=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_USER_COUNT=32
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_SANDBOX=y
+CONFIG_PHY=y
+CONFIG_PHY_SANDBOX=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_ROCKCHIP_RK3036=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_PMIC_MAX77686=y
CONFIG_PMIC_PM8916=y
-CONFIG_PMIC_RK808=y
CONFIG_PMIC_S2MPS11=y
CONFIG_DM_PMIC_SANDBOX=y
CONFIG_PMIC_S5M8767=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_MAX77686=y
CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_REGULATOR_RK808=y
CONFIG_REGULATOR_S5M8767=y
CONFIG_DM_REGULATOR_SANDBOX=y
CONFIG_REGULATOR_TPS65090=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_SANDBOX=y
CONFIG_RAM=y
CONFIG_REMOTEPROC_SANDBOX=y
CONFIG_DM_RESET=y
CONFIG_CONSOLE_TRUETYPE=y
CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
CONFIG_VIDEO_SANDBOX_SDL=y
-CONFIG_PHY=y
-CONFIG_PHY_SANDBOX=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
CONFIG_LZ4=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
CONFIG_UT_ENV=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_SANDBOX=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_USER_COUNT=32
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_SANDBOX=y
+CONFIG_PHY=y
+CONFIG_PHY_SANDBOX=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_ROCKCHIP_RK3036=y
CONFIG_VIDEO_SANDBOX_SDL=y
CONFIG_FS_CBFS=y
CONFIG_FS_CRAMFS=y
-CONFIG_PHY=y
-CONFIG_PHY_SANDBOX=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
CONFIG_LZ4=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_SANDBOX=y
+CONFIG_PHY=y
+CONFIG_PHY_SANDBOX=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_SANDBOX=y
CONFIG_VIDEO_SANDBOX_SDL=y
CONFIG_FS_CBFS=y
CONFIG_FS_CRAMFS=y
-CONFIG_PHY=y
-CONFIG_PHY_SANDBOX=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
CONFIG_LZ4=y
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_ARCH_BMIPS=y
-CONFIG_BAUDRATE=115200
-CONFIG_BCM6345_CLK=y
-CONFIG_BCM6345_GPIO=y
-CONFIG_BCM6345_SERIAL=y
-CONFIG_BMIPS_BOOT_RAM=y
+CONFIG_SOC_BMIPS_BCM6358=y
CONFIG_BOARD_SFR_NB4_SER=y
-CONFIG_CFI_FLASH=y
-# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTM=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="sfr,nb4-ser"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="NB4-SER # "
CONFIG_CMD_CPU=y
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_EDITENV is not set
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_EXPORTENV is not set
-CONFIG_CMD_FLASH=y
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
-CONFIG_CMD_LED=y
-CONFIG_CMD_LICENSE=y
-CONFIG_CMD_LOADB=y
-# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_MISC is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_DEFAULT_DEVICE_TREE="sfr,nb4-ser"
-CONFIG_DISPLAY_CPUINFO=y
+# CONFIG_CMD_MISC is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_GPIO=y
-CONFIG_DM_RESET=y
-CONFIG_DM_SERIAL=y
-CONFIG_HUSH_PARSER=y
+CONFIG_BCM6345_GPIO=y
CONFIG_LED=y
CONFIG_LED_BCM6358=y
CONFIG_LED_GPIO=y
-CONFIG_MIPS=y
-# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
-# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
-CONFIG_MIPS_BOOT_FDT=y
CONFIG_MTD=y
-CONFIG_MTD_DEVICE=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_RESET=y
+CONFIG_CFI_FLASH=y
+CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
-CONFIG_SOC_BMIPS_BCM6358=y
# CONFIG_SPL_SERIAL_PRESENT is not set
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_PROMPT="NB4-SER # "
-CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_DM_SERIAL=y
+CONFIG_BCM6345_SERIAL=y
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ROCKCHIP_RK3368=y
-CONFIG_TARGET_SHEEP=y
CONFIG_DEFAULT_DEVICE_TREE="rk3368-sheep"
-CONFIG_HUSH_PARSER=y
+CONFIG_DEBUG_UART=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_FASTBOOT=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_BOOTRK=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_SYSRESET=y
CONFIG_PINCTRL=y
-CONFIG_ROCKCHIP_RK3368_PINCTRL=y
CONFIG_RAM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xFF1b0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYSRESET=y
CONFIG_ERRNO_STR=y
CONFIG_ARM=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_SNIPER=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_TARGET_SNOW=y
CONFIG_IDENT_STRING=" for snow"
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow"
+CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_REGULATOR_TPS65090=y
CONFIG_DM_PWM=y
CONFIG_PWM_EXYNOS=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_S5P=y
CONFIG_DEBUG_UART_BASE=0x12c30000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_VENDOR_ADVANTECH=y
CONFIG_TARGET_SOM_DB5800_SOM_6867=y
CONFIG_DEFAULT_DEVICE_TREE="baytrail_som-db5800-som-6867"
+CONFIG_DEBUG_UART=y
CONFIG_HAVE_INTEL_ME=y
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I=y
+CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=3881949
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN=""
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_SPI_SUNXI=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_TARGET_SPRING=y
CONFIG_IDENT_STRING=" for spring"
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-spring"
+CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_REGULATOR_TPS65090=y
CONFIG_DM_PWM=y
CONFIG_PWM_EXYNOS=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_S5P=y
CONFIG_DEBUG_UART_BASE=0x12c30000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_ARM=y
CONFIG_STM32=y
+CONFIG_SYS_MALLOC_F_LEN=0xC00
CONFIG_STM32F7=y
CONFIG_TARGET_STM32F746_DISCO=y
CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco"
CONFIG_CMD_LINK_LOCAL=y
CONFIG_CMD_TIMER=y
CONFIG_OF_CONTROL=y
-CONFIG_DM_SEQ_ALIAS=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_CLK=y
+CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_FULL is not set
CONFIG_PINCTRL_STM32=y
+CONFIG_RAM=y
+CONFIG_STM32_SDRAM=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set
-CONFIG_RAM=y
-CONFIG_STM32_SDRAM=y
-CONFIG_DM_GPIO=y
-CONFIG_STM32F7_GPIO=y
-CONFIG_SYS_MALLOC_F_LEN=0xC00
CONFIG_PPC=y
CONFIG_MPC83xx=y
-CONFIG_CMD_IMMAP=y
CONFIG_TARGET_SUVD3=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_ARM=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_TAO3530=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_TBS2910=y
-CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_VIDEO=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_PRE_CON_BUF_ADDR=0x7c000000
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
+CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PCI=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
+CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART_SHIFT=2
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_G_DNL_MANUFACTURER="Siemens AG"
CONFIG_G_DNL_VENDOR_NUM=0x0908
CONFIG_G_DNL_PRODUCT_NUM=0x02d2
-CONFIG_OMAP_WATCHDOG=y
CONFIG_TARGET_THUNDERX_88XX=y
CONFIG_IDENT_STRING=" for Cavium Thunder CN88XX ARM v8 Multi-Core"
CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx"
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DM=y
# CONFIG_MMC is not set
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_PL011=y
CONFIG_DEBUG_UART_BASE=0x87e024000000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_TARGET_TINKER_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker"
+CONFIG_DEBUG_UART=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt"
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami"
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=0
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt"
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus"
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=0
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
# CONFIG_NETDEVICES is not set
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_TRICORDER=y
CONFIG_BOOTDELAY=0
CONFIG_SILENT_CONSOLE=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_TRICORDER=y
CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD"
CONFIG_BOOTDELAY=0
CONFIG_PPC=y
CONFIG_MPC83xx=y
-CONFIG_CMD_IMMAP=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_PPC=y
CONFIG_MPC83xx=y
-CONFIG_CMD_IMMAP=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_ARM=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP34XX=y
CONFIG_TARGET_TWISTER=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_ZYNQMP_USB=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
+CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=25000000
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_ZYNQMP_USB=y
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1"
+CONFIG_ZYNQMP_USB=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
+CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm016 dc2"
# CONFIG_SPL_FAT_SUPPORT is not set
CONFIG_ZYNQMP_USB=y
-CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm016 dc2"
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
+CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPI_FLASH_SST=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm018 dc4"
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
+CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_ZYNQMP_USB=y
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102"
+CONFIG_ZYNQMP_USB=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102"
+CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_ZYNQMP_USB=y
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102"
+CONFIG_ZYNQMP_USB=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
+CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ZYNQ_GEM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ZYNQ_GEM=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
gpio_set_value(udc->board.pullup_pin, !active);
}
-static const struct at91_udc_caps at91rm9200_udc_caps = {
- .init = at91rm9200_udc_init,
- .pullup = at91rm9200_udc_pullup,
-};
-
static int at91sam9260_udc_init(struct at91_udc *udc)
{
struct at91_ep *ep;
return 0;
}
-static const struct at91_udc_caps at91sam9263_udc_caps = {
- .init = at91sam9263_udc_init,
- .pullup = at91sam9260_udc_pullup,
-};
-
int usb_gadget_handle_interrupts(int index)
{
struct at91_udc *udc = controller;
struct dwc2_core_regs *regs;
int root_hub_devnum;
bool ext_vbus;
+ bool hnp_srp_disable;
bool oc_disable;
};
usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
}
#endif
+ if (priv->hnp_srp_disable)
+ usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
+
writel(usbcfg, ®s->gusbcfg);
/* Program the GAHBCFG Register. */
writel(ahbcfg, ®s->gahbcfg);
- /* Program the GUSBCFG register for HNP/SRP. */
- setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
+ /* Program the capabilities in GUSBCFG Register */
+ usbcfg = 0;
+ if (!priv->hnp_srp_disable)
+ usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
#ifdef CONFIG_DWC2_IC_USB_CAP
- setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
+ usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
#endif
+
+ setbits_le32(®s->gusbcfg, usbcfg);
}
/*
if (prop)
priv->oc_disable = true;
+ prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
+ "hnp-srp-disable", NULL);
+ if (prop)
+ priv->hnp_srp_disable = true;
+
return 0;
}
} __attribute__ ((packed));
#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
-#define ehci_readl(x) cpu_to_be32((*((volatile u32 *)(x))))
-#define ehci_writel(a, b) (*((volatile u32 *)(a)) = \
- cpu_to_be32(((volatile u32)b)))
+#define ehci_readl(x) cpu_to_be32(readl(x))
+#define ehci_writel(a, b) writel(cpu_to_be32(b), a)
#else
-#define ehci_readl(x) cpu_to_le32((*((volatile u32 *)(x))))
-#define ehci_writel(a, b) (*((volatile u32 *)(a)) = \
- cpu_to_le32(((volatile u32)b)))
+#define ehci_readl(x) cpu_to_le32(readl(x))
+#define ehci_writel(a, b) writel(cpu_to_le32(b), a)
#endif
#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
#include <linux/bitops.h>
#else
#include <errno.h>
+#if defined(__FreeBSD__)
+#include <sys/endian.h>
+#else
#include <endian.h>
+#endif
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
};
#ifdef USE_HOSTCC
+#ifndef __BSD_VISIBLE
static int fls(int x)
{
int r = 32;
return r;
}
#endif
+#endif
/*
* same as encode_bch(), but process input data one byte at a time