x86: ivybridge: Move lpc_early_init() to probe()

Move this code to the LPC's probe() method so that it will happen
automatically when the LPC is probed before relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 6ffc843a86b7420cd64526e0e6a1ba636b5a08cd..4c6ffb249d77f1c509f5dadfcc0933a03e710a04 100644 (file)
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -124,10 +124,8 @@ int arch_cpu_init(void)
 
 int arch_cpu_init_dm(void)
 {
-       const void *blob = gd->fdt_blob;
        struct pci_controller *hose;
        struct udevice *bus, *dev;
-       int node;
        int ret;
 
        post_code(0x70);
@@ -145,13 +143,6 @@ int arch_cpu_init_dm(void)
        if (!dev)
                return -ENODEV;
 
-       node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
-       if (node < 0)
-               return -ENOENT;
-       ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV);
-       if (ret)
-               return ret;
-
        enable_spi_prefetch(hose, PCH_LPC_DEV);
 
        /* This is already done in start.S, but let's do it in C */

diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 51a407379adb222741e1246b2f9498946771ad4a..9d089c75bf53ea072e596cc9d812f48f824db248 100644 (file)
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -454,7 +454,13 @@ static void pch_fixups(pci_dev_t dev)
        setbits_le32(RCB_REG(0x21a8), 0x3);
 }
 
-int lpc_early_init(const void *blob, int node, pci_dev_t dev)
+/**
+ * lpc_early_init() - set up LPC serial ports and other early things
+ *
+ * @dev:       LPC device
+ * @return 0 if OK, -ve on error
+ */
+static int lpc_early_init(struct udevice *dev)
 {
        struct reg_info {
                u32 base;
@@ -463,17 +469,18 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev)
        int count;
        int i;
 
-       count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec",
-                       (u32 *)values, sizeof(values) / sizeof(u32));
+       count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset,
+                       "intel,gen-dec", (u32 *)values,
+                       sizeof(values) / sizeof(u32));
        if (count < 0)
                return -EINVAL;
 
        /* Set COM1/COM2 decode range */
-       x86_pci_write_config16(dev, LPC_IO_DEC, 0x0010);
+       dm_pci_write_config16(dev->parent, LPC_IO_DEC, 0x0010);
 
        /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
-       x86_pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
-                          GAMEL_LPC_EN | COMA_LPC_EN);
+       dm_pci_write_config16(dev->parent, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
+                             GAMEL_LPC_EN | COMA_LPC_EN);
 
        /* Write all registers but use 0 if we run out of data */
        count = count * sizeof(u32) / sizeof(values[0]);
@@ -482,7 +489,7 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev)
 
                if (i < count)
                        reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
-               x86_pci_write_config32(dev, LPC_GENX_DEC(i), reg);
+               dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg);
        }
 
        return 0;
@@ -561,6 +568,17 @@ void lpc_enable(pci_dev_t dev)
 
 static int bd82x6x_lpc_probe(struct udevice *dev)
 {
+       int ret;
+
+       if (gd->flags & GD_FLG_RELOC)
+               return 0;
+
+       ret = lpc_early_init(dev);
+       if (ret) {
+               debug("%s: lpc_early_init() failed\n", __func__);
+               return ret;
+       }
+
        return 0;
 }
 

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index d5c5bfdd08299ccee1f4119572fe029b9a7e1ccb..f2db8443d2f9ea5b8a1131b85468a267956e9472 100644 (file)
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -192,8 +192,6 @@
                        u-boot,dm-pre-reloc;
                        #address-cells = <1>;
                        #size-cells = <1>;
-                       gen-dec = <0x800 0xfc 0x900 0xfc>;
-                       intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
                        intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
                                                0x80 0x80 0x80 0x80>;
                        intel,gpi-routing = <0 0 0 0 0 0 0 2
@@ -224,6 +222,7 @@
                                #address-cells = <1>;
                                #size-cells = <0>;
                                u-boot,dm-pre-reloc;
+                               intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
                                cros-ec@200 {
                                        compatible = "google,cros-ec";
                                        reg = <0x204 1 0x200 1 0x880 0x80>;

diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index 31437c8618d13f6c40a772a06447dfe436ce223e..19cd7e5bebc5fb51b7e7ae33fada7d0a74a00c73 100644 (file)
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -473,14 +473,4 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
 int lpc_init(struct pci_controller *hose, pci_dev_t dev);
 void lpc_enable(pci_dev_t dev);
 
-/**
- * lpc_early_init() - set up LPC serial ports and other early things
- *
- * @blob:      Device tree blob
- * @node:      Offset of LPC node
- * @dev:       PCH PCI device containing the LPC
- * @return 0 if OK, -ve on error
- */
-int lpc_early_init(const void *blob, int node, pci_dev_t dev);
-
 #endif