]> git.sur5r.net Git - u-boot/commitdiff
rockchip: Use pwrseq for MMC start-up on jerry
authorSimon Glass <sjg@chromium.org>
Fri, 22 Jan 2016 02:43:36 +0000 (19:43 -0700)
committerSimon Glass <sjg@chromium.org>
Fri, 22 Jan 2016 03:42:34 +0000 (20:42 -0700)
This is defined in the device tree in Linux. Copy over the settings so that
this can be used instead of hard-coding the reset line.

Signed-off-by: Simon Glass <sjg@chromium.org>
arch/arm/dts/rk3288-veyron.dtsi
configs/chromebook_jerry_defconfig
include/configs/rk3288_common.h

index 7e37158fc3512324ab49671f01b9f1bdcbabadf8..12404ff76b99687cfde3ccd6e7513e018a14d7ff 100644 (file)
                priority = /bits/ 8 <200>;
        };
 
+       emmc_pwrseq: emmc-pwrseq {
+               compatible = "mmc-pwrseq-emmc";
+               pinctrl-0 = <&emmc_reset>;
+               pinctrl-names = "default";
+               reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
+       };
+
        sound {
                compatible = "rockchip,rockchip-audio-max98090";
                rockchip,model = "ROCKCHIP-I2S";
        bus-width = <8>;
        cap-mmc-highspeed;
        mmc-hs200-1_8v;
+       mmc-pwrseq = <&emmc_pwrseq>;
        disable-wp;
        non-removable;
        num-slots = <1>;
        pinctrl-names = "default";
-       pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_deassert_reset>;
+       pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>;
        status = "okay";
 };
 
        };
 
        emmc {
-               /* Make sure eMMC is not in reset */
-               emmc_deassert_reset: emmc-deassert-reset {
-                       rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_up>;
+               emmc_reset: emmc-reset {
+                       rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
                /*
index 39cd9d696baa3001b783ea0fb549c723234008da..456b6ea2906dbea696233911ce62aae0afebf550 100644 (file)
@@ -23,6 +23,7 @@ CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_LED=y
 CONFIG_SPL_LED=y
 CONFIG_LED_GPIO=y
+CONFIG_PWRSEQ=y
 CONFIG_RESET=y
 CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
index 238711a699206008c940e02d84a7cb0e50ac7e00..f47573b25c49cf8095c2f12c8b315a8f8fde53ab 100644 (file)
@@ -26,6 +26,7 @@
 #define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMER_BASE + 8)
 
 #define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT