\r
/******************************************************************************\r
*\r
- * See the following URL for information on the commands defined in this file:\r
- * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Ethernet_Related_CLI_Commands.shtml\r
+ * http://www.FreeRTOS.org/cli\r
*\r
******************************************************************************/\r
\r
{\r
const char *pcParameter;\r
BaseType_t xParameterStringLength, xReturn;\r
-static BaseType_t lParameterNumber = 0;\r
+static UBaseType_t uxParameterNumber = 0;\r
\r
/* Remove compile time warnings about unused parameters, and check the\r
write buffer is not NULL. NOTE - for simplicity, this example assumes the\r
( void ) xWriteBufferLen;\r
configASSERT( pcWriteBuffer );\r
\r
- if( lParameterNumber == 0 )\r
+ if( uxParameterNumber == 0 )\r
{\r
/* The first time the function is called after the command has been\r
entered just a header string is returned. */\r
\r
/* Next time the function is called the first parameter will be echoed\r
back. */\r
- lParameterNumber = 1L;\r
+ uxParameterNumber = 1U;\r
\r
/* There is more data to be returned as no parameters have been echoed\r
back yet. */\r
pcParameter = FreeRTOS_CLIGetParameter\r
(\r
pcCommandString, /* The command string itself. */\r
- lParameterNumber, /* Return the next parameter. */\r
+ uxParameterNumber, /* Return the next parameter. */\r
&xParameterStringLength /* Store the parameter string length. */\r
);\r
\r
\r
/* Return the parameter string. */\r
memset( pcWriteBuffer, 0x00, xWriteBufferLen );\r
- sprintf( pcWriteBuffer, "%d: ", ( int ) lParameterNumber );\r
- strncat( pcWriteBuffer, pcParameter, xParameterStringLength );\r
+ sprintf( pcWriteBuffer, "%d: ", ( int ) uxParameterNumber );\r
+ strncat( pcWriteBuffer, pcParameter, ( size_t ) xParameterStringLength );\r
strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) );\r
\r
/* If this is the last of the three parameters then there are no more\r
strings to return after this one. */\r
- if( lParameterNumber == 3L )\r
+ if( uxParameterNumber == 3U )\r
{\r
/* If this is the last of the three parameters then there are no more\r
strings to return after this one. */\r
xReturn = pdFALSE;\r
- lParameterNumber = 0L;\r
+ uxParameterNumber = 0;\r
}\r
else\r
{\r
/* There are more parameters to return after this one. */\r
xReturn = pdTRUE;\r
- lParameterNumber++;\r
+ uxParameterNumber++;\r
}\r
}\r
\r
{\r
const char *pcParameter;\r
BaseType_t xParameterStringLength, xReturn;\r
-static BaseType_t lParameterNumber = 0;\r
+static UBaseType_t uxParameterNumber = 0;\r
\r
/* Remove compile time warnings about unused parameters, and check the\r
write buffer is not NULL. NOTE - for simplicity, this example assumes the\r
( void ) xWriteBufferLen;\r
configASSERT( pcWriteBuffer );\r
\r
- if( lParameterNumber == 0 )\r
+ if( uxParameterNumber == 0 )\r
{\r
/* The first time the function is called after the command has been\r
entered just a header string is returned. */\r
\r
/* Next time the function is called the first parameter will be echoed\r
back. */\r
- lParameterNumber = 1L;\r
+ uxParameterNumber = 1U;\r
\r
/* There is more data to be returned as no parameters have been echoed\r
back yet. */\r
pcParameter = FreeRTOS_CLIGetParameter\r
(\r
pcCommandString, /* The command string itself. */\r
- lParameterNumber, /* Return the next parameter. */\r
+ uxParameterNumber, /* Return the next parameter. */\r
&xParameterStringLength /* Store the parameter string length. */\r
);\r
\r
{\r
/* Return the parameter string. */\r
memset( pcWriteBuffer, 0x00, xWriteBufferLen );\r
- sprintf( pcWriteBuffer, "%d: ", ( int ) lParameterNumber );\r
- strncat( pcWriteBuffer, pcParameter, xParameterStringLength );\r
+ sprintf( pcWriteBuffer, "%d: ", ( int ) uxParameterNumber );\r
+ strncat( pcWriteBuffer, ( char * ) pcParameter, ( size_t ) xParameterStringLength );\r
strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) );\r
\r
/* There might be more parameters to return after this one. */\r
xReturn = pdTRUE;\r
- lParameterNumber++;\r
+ uxParameterNumber++;\r
}\r
else\r
{\r
xReturn = pdFALSE;\r
\r
/* Start over the next time this command is executed. */\r
- lParameterNumber = 0;\r
+ uxParameterNumber = 0;\r
}\r
}\r
\r
xPort = xSerialPortInitMinimal( configCLI_BAUD_RATE, cmdQUEUE_LENGTH );\r
\r
/* Send the welcome message. */\r
- vSerialPutString( xPort, ( signed char * ) pcWelcomeMessage, strlen( pcWelcomeMessage ) );\r
+ vSerialPutString( xPort, ( signed char * ) pcWelcomeMessage, ( unsigned short ) strlen( pcWelcomeMessage ) );\r
\r
for( ;; )\r
{\r
if( cRxedChar == '\n' || cRxedChar == '\r' )\r
{\r
/* Just to space the output from the input. */\r
- vSerialPutString( xPort, ( signed char * ) pcNewLine, strlen( pcNewLine ) );\r
+ vSerialPutString( xPort, ( signed char * ) pcNewLine, ( unsigned short ) strlen( pcNewLine ) );\r
\r
/* See if the command is empty, indicating that the last command\r
is to be executed again. */\r
xReturned = FreeRTOS_CLIProcessCommand( cInputString, pcOutputString, configCOMMAND_INT_MAX_OUTPUT_SIZE );\r
\r
/* Write the generated string to the UART. */\r
- vSerialPutString( xPort, ( signed char * ) pcOutputString, strlen( pcOutputString ) );\r
+ vSerialPutString( xPort, ( signed char * ) pcOutputString, ( unsigned short ) strlen( pcOutputString ) );\r
\r
} while( xReturned != pdFALSE );\r
\r
ucInputIndex = 0;\r
memset( cInputString, 0x00, cmdMAX_INPUT_SIZE );\r
\r
- vSerialPutString( xPort, ( signed char * ) pcEndOfOutputMessage, strlen( pcEndOfOutputMessage ) );\r
+ vSerialPutString( xPort, ( signed char * ) pcEndOfOutputMessage, ( unsigned short ) strlen( pcEndOfOutputMessage ) );\r
}\r
else\r
{\r
{\r
if( xSemaphoreTake( xTxMutex, cmdMAX_MUTEX_WAIT ) == pdPASS )\r
{\r
- vSerialPutString( xPort, ( signed char * ) pcMessage, strlen( pcMessage ) );\r
+ vSerialPutString( xPort, ( signed char * ) pcMessage, ( unsigned short ) strlen( pcMessage ) );\r
xSemaphoreGive( xTxMutex );\r
}\r
}\r
vmov d14, r4, r5\r
vmov d15, r6, r7\r
\r
- ; Loop, checking each itteration that each register still contains the\r
+ ; Loop, checking each iteration that each register still contains the\r
; expected value.\r
reg1_loop\r
; Yield to increase test coverage\r
vmov d14, r4, r5\r
vmov d15, r6, r7\r
\r
- ; Loop, checking each itteration that each register still contains the\r
+ ; Loop, checking each iteration that each register still contains the\r
; expected value.\r
reg2_loop\r
; Check all the VFP registers still contain the values set above.\r
vmov d30, r4, r5\r
vmov d31, r6, r7\r
\r
- ; Loop, checking each itteration that each register still contains the\r
+ ; Loop, checking each iteration that each register still contains the\r
; expected value.\r
reg1_loop\r
; Yield to increase test coverage\r
vmov d30, r4, r5\r
vmov d31, r6, r7\r
\r
- ; Loop, checking each itteration that each register still contains the\r
+ ; Loop, checking each iteration that each register still contains the\r
; expected value.\r
reg2_loop\r
; Check all the VFP registers still contain the values set above.\r
vmov d30, r4, r5\r
vmov d31, r6, r7\r
\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
reg1_loop:\r
/* Yield to increase test coverage */\r
vmov d30, r4, r5\r
vmov d31, r6, r7\r
\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
reg2_loop:\r
/* Check all the VFP registers still contain the values set above.\r
vmov d30, r4, r5\r
vmov d31, r6, r7\r
\r
- ; Loop, checking each itteration that each register still contains the\r
+ ; Loop, checking each iteration that each register still contains the\r
; expected value.\r
reg1_loop\r
; Yield to increase test coverage\r
vmov d30, r4, r5\r
vmov d31, r6, r7\r
\r
- ; Loop, checking each itteration that each register still contains the\r
+ ; Loop, checking each iteration that each register still contains the\r
; expected value.\r
reg2_loop\r
; Check all the VFP registers still contain the values set above.\r
vmov d30, r4, r5\r
vmov d31, r6, r7\r
\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
reg1_loop:\r
/* Yield to increase test coverage */\r
vmov d30, r4, r5\r
vmov d31, r6, r7\r
\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
reg2_loop:\r
/* Check all the VFP registers still contain the values set above.\r
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</configuration>\r
</storageModule>\r
<type>2</type>\r
<locationURI>FREERTOS_ROOT/FreeRTOS/Source</locationURI>\r
</link>\r
+ <link>\r
+ <name>src/Full_Demo/FreeRTOS-Plus-CLI</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>src/Full_Demo/Sample-CLI-commands.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/Sample-CLI-commands.c</locationURI>\r
+ </link>\r
<link>\r
<name>src/Full_Demo/Standard_Demo_Tasks</name>\r
<type>2</type>\r
<locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal</locationURI>\r
</link>\r
+ <link>\r
+ <name>src/Full_Demo/UARTCommandConsole.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UARTCommandConsole.c</locationURI>\r
+ </link>\r
<link>\r
<name>src/Full_Demo/Standard_Demo_Tasks/include</name>\r
<type>2</type>\r
</link>\r
</linkedResources>\r
<filteredResources>\r
+ <filter>\r
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<version>1</version>\r
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<option>\r
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<state>$PROJ_DIR$\src\cg_src</state>\r
<state>$PROJ_DIR$\..\Common\include</state>\r
<state>$PROJ_DIR$\src\Full_Demo</state>\r
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</option>\r
<option>\r
<name>CCStdIncCheck</name>\r
</option>\r
<option>\r
<name>CCOptLevel</name>\r
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</option>\r
<option>\r
<name>CCOptStrategy</name>\r
</option>\r
<option>\r
<name>CCOptLevelSlave</name>\r
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+ <state>0</state>\r
</option>\r
<option>\r
<name>CompilerMisraRules98</name>\r
<name>$PROJ_DIR$\..\Common\Minimal\TimerDemo.c</name>\r
</file>\r
</group>\r
+ <group>\r
+ <name>FreeRTOS+CLI</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.c</name>\r
+ </file>\r
+ </group>\r
<file>\r
<name>$PROJ_DIR$\src\Full_Demo\IntQueueTimer.c</name>\r
</file>\r
<file>\r
<name>$PROJ_DIR$\src\Full_Demo\reg_test_IAR.asm</name>\r
</file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\Sample-CLI-commands.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\UARTCommandConsole.c</name>\r
+ </file>\r
</group>\r
<group>\r
<name>Renesas_cg_src</name>\r
<file>\r
<name>$PROJ_DIR$\src\cg_src\r_cg_rspi_user.c</name>\r
</file>\r
+ <file>\r
+ <name>$PROJ_DIR$\src\cg_src\r_cg_scifa.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\src\cg_src\r_cg_scifa_user.c</name>\r
+ </file>\r
<file>\r
<name>$PROJ_DIR$\src\cg_src\r_cg_systeminit.c</name>\r
</file>\r
EXTERN FreeRTOS_IRQ_Handler\r
EXTERN vCMT_1_Channel_0_ISR\r
EXTERN vCMT_1_Channel_1_ISR\r
+ EXTERN r_scifa2_txif2_interrupt\r
+ EXTERN r_scifa2_rxif2_interrupt\r
+ EXTERN r_scifa2_drif2_interrupt\r
+ EXTERN r_scifa2_brif2_interrupt\r
\r
PUBLIC FreeRTOS_Tick_Handler_Entry\r
PUBLIC vCMT_1_Channel_0_ISR_Entry\r
PUBLIC vCMT_1_Channel_1_ISR_Entry\r
+ PUBLIC r_scifa2_txif2_interrupt_entry\r
+ PUBLIC r_scifa2_rxif2_interrupt_entry\r
+ PUBLIC r_scifa2_drif2_interrupt_entry\r
+ PUBLIC r_scifa2_brif2_interrupt_entry\r
\r
FreeRTOS_Tick_Handler_Entry:\r
/* Save used registers (probably not necessary). */\r
/* Restore used registers then branch to the FreeRTOS IRQ handler. */\r
POP {r0-r1}\r
B FreeRTOS_IRQ_Handler\r
+/*-----------------------------------------------------------*/\r
+\r
+r_scifa2_txif2_interrupt_entry:\r
+ /* Save used registers (probably not necessary). */\r
+ PUSH {r0-r1}\r
+ /* Save the address of the C portion of this handler in pxISRFunction. */\r
+ LDR r0, =pxISRFunction\r
+ LDR R1, =r_scifa2_txif2_interrupt\r
+ STR R1, [r0]\r
+ /* Restore used registers then branch to the FreeRTOS IRQ handler. */\r
+ POP {r0-r1}\r
+ B FreeRTOS_IRQ_Handler\r
+/*-----------------------------------------------------------*/\r
+\r
+r_scifa2_rxif2_interrupt_entry:\r
+ /* Save used registers (probably not necessary). */\r
+ PUSH {r0-r1}\r
+ /* Save the address of the C portion of this handler in pxISRFunction. */\r
+ LDR r0, =pxISRFunction\r
+ LDR R1, =r_scifa2_rxif2_interrupt\r
+ STR R1, [r0]\r
+ /* Restore used registers then branch to the FreeRTOS IRQ handler. */\r
+ POP {r0-r1}\r
+ B FreeRTOS_IRQ_Handler\r
+/*-----------------------------------------------------------*/\r
+\r
+r_scifa2_drif2_interrupt_entry:\r
+ /* Save used registers (probably not necessary). */\r
+ PUSH {r0-r1}\r
+ /* Save the address of the C portion of this handler in pxISRFunction. */\r
+ LDR r0, =pxISRFunction\r
+ LDR R1, =r_scifa2_drif2_interrupt\r
+ STR R1, [r0]\r
+ /* Restore used registers then branch to the FreeRTOS IRQ handler. */\r
+ POP {r0-r1}\r
+ B FreeRTOS_IRQ_Handler\r
+/*-----------------------------------------------------------*/\r
+\r
+r_scifa2_brif2_interrupt_entry:\r
+ /* Save used registers (probably not necessary). */\r
+ PUSH {r0-r1}\r
+ /* Save the address of the C portion of this handler in pxISRFunction. */\r
+ LDR r0, =pxISRFunction\r
+ LDR R1, =r_scifa2_brif2_interrupt\r
+ STR R1, [r0]\r
+ /* Restore used registers then branch to the FreeRTOS IRQ handler. */\r
+ POP {r0-r1}\r
+ B FreeRTOS_IRQ_Handler\r
\r
- END\r
+ END\r
<Desktop>\r
<Static>\r
<Debug-Log>\r
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- </Debug-Log>\r
+ \r
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</Workspace>\r
<Disassembly>\r
<col-names>\r
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+ \r
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<col-widths>\r
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+ \r
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+ \r
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<Breakpoints>\r
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</Register>\r
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<Windows>\r
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\r
[ArmDriver]\r
EnableCache=1\r
[DebugChecksum]\r
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[Disassemble mode]\r
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</Workspace>\r
\r
[MainWindow]\r
-WindowPlacement=_ 519 0 1619 872 3\r
+WindowPlacement=_ 367 9 1633 963 3\r
*\r
* The Queue Send Task:\r
* The queue send task is implemented by the prvQueueSendTask() function in\r
- * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
- * block for 200 milliseconds, before sending the value 100 to the queue that\r
- * was created within main_blinky(). Once the value is sent, the task loops\r
- * back around to block for another 200 milliseconds...and so on.\r
+ * this file. It sends the value 100 to the queue every 200 milliseconds.\r
*\r
* The Queue Receive Task:\r
* The queue receive task is implemented by the prvQueueReceiveTask() function\r
- * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
- * blocks on attempts to read data from the queue that was created within\r
- * main_blinky(). When data is received, the task checks the value of the\r
- * data, and if the value equals the expected 100, toggles an LED. The 'block\r
- * time' parameter passed to the queue receive function specifies that the\r
- * task should be held in the Blocked state indefinitely to wait for data to\r
- * be available on the queue. The queue receive task will only leave the\r
- * Blocked state when the queue send task writes to the queue. As the queue\r
- * send task writes to the queue every 200 milliseconds, the queue receive\r
- * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
- * the LED every 200 milliseconds.\r
+ * in this file. It blocks on the queue to wait for data to arrive from the\r
+ * queue send task - toggling the LED each time it receives the value 100. The\r
+ * queue send task writes to the queue every 200ms, so the LED should toggle\r
+ * every 200ms.\r
*/\r
\r
/* Kernel includes. */\r
\r
/* The rate at which data is sent to the queue. The 200ms value is converted\r
to ticks using the portTICK_PERIOD_MS constant. */\r
-#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS )\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( pdMS_TO_TICKS( 200UL ) )\r
\r
/* The number of items the queue can hold. This is 1 as the receive task\r
will remove items as they are added, meaning the send task should always find\r
is it the expected value? If it is, toggle the LED. */\r
if( ulReceivedValue == ulExpectedValue )\r
{\r
- LED2 = !LED2;\r
+ LED0 = !LED0;\r
ulReceivedValue = 0U;\r
}\r
}\r
#define configUSE_IDLE_HOOK 1\r
#define configUSE_TICK_HOOK 1\r
#define configMAX_PRIORITIES ( 5 )\r
-#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 100 )\r
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 38 * 1024 ) )\r
#define configMAX_TASK_NAME_LEN ( 10 )\r
#define configUSE_TRACE_FACILITY 1\r
FreeRTOS/Source/tasks.c for limitations. */\r
#define configUSE_STATS_FORMATTING_FUNCTIONS 1\r
\r
+/* The buffer into which output generated by FreeRTOS+CLI is placed. This must\r
+be at least big enough to contain the output of the task-stats command, as the\r
+example implementation does not include buffer overlow checking. */\r
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE 3500\r
+#define configINCLUDE_QUERY_HEAP_COMMAND 1\r
+\r
/* Cortex-R specific setting: FPU has 16 (rather than 32) d registers. */\r
#define configFPU_D32 0\r
\r
*\r
******************************************************************************\r
*\r
- * main_full() creates all the demo application tasks and software timers, then\r
+ * main_full() creates a set of demo application tasks and software timers, then\r
* starts the scheduler. The web documentation provides more details of the\r
* standard demo application tasks, which provide no particular functionality,\r
* but do provide a good example of how to use the FreeRTOS API.\r
* In addition to the standard demo tasks, the following tasks and tests are\r
* defined and/or created within this file:\r
*\r
+ * "FreeRTOS+CLI command console" - The command console uses SCI1 for its\r
+ * input and output. The baud rate is set to 19200. Type "help" to see a list\r
+ * of registered commands. The FreeRTOS+CLI license is different to the\r
+ * FreeRTOS license, see http://www.FreeRTOS.org/cli for license and usage\r
+ * details.\r
+ *\r
* "Reg test" tasks - These fill both the core and floating point registers with\r
* known values, then check that each register maintains its expected value for\r
* the lifetime of the task. Each task uses a different set of values. The reg\r
* error in the context switching mechanism.\r
*\r
* "Check" task - The check task period is initially set to three seconds. The\r
- * task checks that all the standard demo tasks, and the register check tasks,\r
- * are not only still executing, but are executing without reporting any errors.\r
- * If the check task discovers that a task has either stalled, or reported an\r
- * error, then it changes its own execution period from the initial three\r
- * seconds, to just 200ms. The check task also toggles an LED each time it is\r
- * called. This provides a visual indication of the system status: If the LED\r
- * toggles every three seconds, then no issues have been discovered. If the LED\r
- * toggles every 200ms, then an issue has been discovered with at least one\r
- * task.\r
+ * task checks that all the standard demo tasks are not only still executing,\r
+ * but are executing without reporting any errors. If the check task discovers\r
+ * that a task has either stalled, or reported an error, then it changes its own\r
+ * execution period from the initial three seconds, to just 200ms. The check\r
+ * task also toggles an LED on each iteration of its loop. This provides a\r
+ * visual indication of the system status: If the LED toggles every three\r
+ * seconds, then no issues have been discovered. If the LED toggles every\r
+ * 200ms, then an issue has been discovered with at least one task.\r
*/\r
\r
/* Standard includes. */\r
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL )\r
-#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )\r
\r
/* The priority used by the UART command console task. */\r
#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )\r
\r
-/* A block time of zero simply means "don't block". */\r
-#define mainDONT_BLOCK ( 0UL )\r
-\r
/* The period after which the check timer will expire, in ms, provided no errors\r
have been reported by any of the standard demo tasks. ms are converted to the\r
equivalent in ticks using the portTICK_PERIOD_MS constant. */\r
-#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS )\r
+#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 3000UL )\r
\r
/* The period at which the check timer will expire, in ms, if an error has been\r
reported in one of the standard demo tasks. ms are converted to the equivalent\r
in ticks using the portTICK_PERIOD_MS constant. */\r
-#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS )\r
+#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 200UL )\r
\r
/* Parameters that are passed into the register check tasks solely for the\r
purpose of ensuring parameters are passed into tasks correctly. */\r
*/\r
static void prvPseudoRandomiser( void *pvParameters );\r
\r
+/*\r
+ * Register commands that can be used with FreeRTOS+CLI. The commands are\r
+ * defined in CLI-Commands.c and File-Related-CLI-Command.c respectively.\r
+ */\r
+extern void vRegisterSampleCLICommands( void );\r
+\r
+/*\r
+ * The task that manages the FreeRTOS+CLI input and output.\r
+ */\r
+extern void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority );\r
+\r
/*-----------------------------------------------------------*/\r
\r
/* The following two variables are used to communicate the status of the\r
stops incrementing, then an error has been found. */\r
volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
\r
-/* String for display in the web server. It is set to an error message if the\r
-check task detects an error. */\r
-const char *pcStatusMessage = "All tasks running without error";\r
/*-----------------------------------------------------------*/\r
\r
void main_full( void )\r
/* Create the task that just adds a little random behaviour. */\r
xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );\r
\r
+ /* Start the tasks that implements the command console on the UART, as\r
+ described above. */\r
+ vUARTCommandConsoleStart( mainUART_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY );\r
+\r
+ /* Register the standard CLI commands. */\r
+ vRegisterSampleCLICommands();\r
+\r
/* Create the task that performs the 'check' functionality, as described at\r
the top of this file. */\r
xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
/* Toggle the check LED to give an indication of the system status. If\r
the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then\r
everything is ok. A faster toggle indicates an error. */\r
- LED2 = !LED2;\r
+ LED0 = !LED0;\r
\r
if( ulErrorFound != pdFALSE )\r
{\r
gone wrong (it might just be that the loop back connector required\r
by the comtest tasks has not been fitted). */\r
xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;\r
- pcStatusMessage = "Error found in at least one task.";\r
}\r
}\r
}\r
\r
static void prvPseudoRandomiser( void *pvParameters )\r
{\r
-const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS );\r
+const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = pdMS_TO_TICKS( 35 );\r
volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue;\r
\r
/* This task does nothing other than ensure there is a little bit of\r
vmov d14, r4, r5\r
vmov d15, r6, r7\r
\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
reg1_loop:\r
/* Yield to increase test coverage */\r
vmov d14, r4, r5\r
vmov d15, r6, r7\r
\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
reg2_loop:\r
/* Check all the VFP registers still contain the values set above.\r
vmov d14, r4, r5\r
vmov d15, r6, r7\r
\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
reg1_loop:\r
/* Yield to increase test coverage */\r
vmov d14, r4, r5\r
vmov d15, r6, r7\r
\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
reg2_loop:\r
/* Check all the VFP registers still contain the values set above.\r
* Arguments : None\r
* Return Value : None\r
***********************************************************************************************************************/\r
+#ifdef __ICCARM__\r
+ __arm __irq\r
+#endif\r
void r_cmt_cmi4_interrupt(void)\r
{\r
/* Clear the interrupt source CMI4 */\r
* Arguments : None\r
* Return Value : None\r
***********************************************************************************************************************/\r
+#ifdef __ICCARM__\r
+ __arm __irq\r
+#endif\r
void r_cmt_cmi5_interrupt(void)\r
{\r
/* Clear the interrupt source CMI5 */\r
\r
/* RSPI1 SPII1 */\r
__irq __arm void r_rspi1_idle_interrupt(void);\r
+\r
+ /* SCIFA TXIF2 */\r
+ __irq __arm void r_scifa2_txif2_interrupt_entry(void);\r
+\r
+ /* SCIFA DRIF2 */\r
+ __irq __arm void r_scifa2_drif2_interrupt_entry(void);\r
+\r
+ /* SCIFA RXIF2 */\r
+ __irq __arm void r_scifa2_rxif2_interrupt_entry(void);\r
+\r
+ /* SCIFA BRIF2 */\r
+ __irq __arm void r_scifa2_brif2_interrupt_entry(void);\r
+\r
+ /* CMT CMI4 */\r
+ __irq __arm void r_cmt_cmi4_interrupt(void);\r
+\r
+ /* CMT CMI5 */\r
+ __irq __arm void r_cmt_cmi5_interrupt(void);\r
#endif /* __ICCARM__ */\r
\r
#ifdef __GNUC__\r
\r
/* RSPI1 SPII1 */\r
void r_rspi1_idle_interrupt(void) __attribute__((interrupt ("IRQ")));\r
+\r
+ /* SCIFA TXIF2 */\r
+ void r_scifa2_txif2_interrupt_entry(void) __attribute__((interrupt ("IRQ")));\r
+\r
+ /* SCIFA DRIF2 */\r
+ void r_scifa2_drif2_interrupt_entry(void) __attribute__((interrupt ("IRQ")));\r
+\r
+ /* SCIFA RXIF2 */\r
+ void r_scifa2_rxif2_interrupt_entry(void) __attribute__((interrupt ("IRQ")));\r
+\r
+ /* SCIFA BRIF2 */\r
+ void r_scifa2_brif2_interrupt_entry(void) __attribute__((interrupt ("IRQ")));\r
+\r
+ /* CMT CMI4 */\r
+ void r_cmt_cmi4_interrupt(void) __attribute__((interrupt ("IRQ")));\r
+\r
+ /* CMT CMI5 */\r
+ void r_cmt_cmi5_interrupt(void) __attribute__((interrupt ("IRQ")));\r
#endif /* __GNUC__ */\r
\r
#endif\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability\r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_scifa.c\r
+* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]\r
+* Device(s) : R7S910018CBG\r
+* Tool-Chain : GCCARM\r
+* Description : This file implements device driver for SCIF module.\r
+* Creation Date: 19/04/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_scifa.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+const uint8_t * gp_scifa2_tx_address; /* SCIFA2 transmit buffer address */\r
+uint16_t g_scifa2_tx_count; /* SCIFA2 transmit data number */\r
+uint8_t * gp_scifa2_rx_address; /* SCIFA2 receive buffer address */\r
+uint16_t g_scifa2_rx_count; /* SCIFA2 receive data number */\r
+uint16_t g_scifa2_rx_length; /* SCIFA2 receive data length */\r
+/* Start user code for global. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: R_SCIFA2_Create\r
+* Description : This function initializes SCIFA2.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_SCIFA2_Create(void)\r
+{\r
+ volatile uint16_t dummy;\r
+ uint16_t w_count;\r
+\r
+ /* Cancel SCIFA2 module stop state */\r
+ MSTP(SCIFA2) = 0U;\r
+\r
+ /* Disable TXIF2 interrupt */\r
+ VIC.IEC3.LONG = 0x00008000UL;\r
+\r
+ /* Disable RXIF2 interrupt */\r
+ VIC.IEC3.LONG = 0x00004000UL;\r
+\r
+ /* Disable BRIF2 interrupt */\r
+ VIC.IEC3.LONG = 0x00002000UL;\r
+\r
+ /* Disable DRIF2 interrupt */\r
+ VIC.IEC3.LONG = 0x00010000UL;\r
+\r
+ /* Clear transmit/receive enable bits */\r
+ SCIFA2.SCR.BIT.TE = 0U;\r
+ SCIFA2.SCR.BIT.RE = 0U;\r
+\r
+ /* Reset transmit/receive FIFO data register operation */\r
+ SCIFA2.FCR.BIT.TFRST = 1U;\r
+ SCIFA2.FCR.BIT.RFRST = 1U;\r
+\r
+ /* Read and clear status flags */\r
+ dummy = SCIFA2.FSR.WORD;\r
+\r
+ /* Remove compiler warnings. */\r
+ ( void ) dummy;\r
+\r
+ SCIFA2.FSR.WORD = 0x00U;\r
+ dummy = (uint16_t) SCIFA2.LSR.BIT.ORER;\r
+\r
+ /* Remove compiler warnings. */\r
+ ( void ) dummy;\r
+\r
+ SCIFA2.LSR.BIT.ORER = 0U;\r
+\r
+ /* Set clock enable bits */\r
+ SCIFA2.SCR.WORD = _SCIF_INTERNAL_SCK_UNUSED;\r
+\r
+ /* Set transmission/reception format */\r
+ SCIFA2.SMR.WORD = _SCIF_CLOCK_SERICLK_4 | _SCIF_STOP_1 | _SCIF_PARITY_DISABLE | _SCIF_DATA_LENGTH_8 |\r
+ _SCIF_ASYNCHRONOUS_MODE;\r
+ SCIFA2.SEMR.BYTE = _SCIF_16_BASE_CLOCK | _SCIF_NOISE_FILTER_ENABLE | _SCIF_DATA_TRANSFER_LSB_FIRST |\r
+ _SCIF_BAUDRATE_SINGLE;\r
+\r
+ /* Clear modulation duty register select */\r
+ SCIFA2.SEMR.BIT.MDDRS = 0U;\r
+\r
+ /* Set bit rate */\r
+ SCIFA2.BRR_MDDR.BRR = 0x3CU;\r
+\r
+ /* Wait for at least 1-bit interval */\r
+ for (w_count = 0U; w_count < _SCIF_1BIT_INTERVAL_2; w_count++)\r
+ {\r
+ nop();\r
+ }\r
+\r
+ /* Set FIFO trigger conditions */\r
+ SCIFA2.FTCR.WORD = _SCIF_TX_FIFO_TRIGGER_NUM_0 | _SCIF_TX_TRIGGER_TFTC_VALID | _SCIF_RX_FIFO_TRIGGER_NUM_1 |\r
+ _SCIF_RX_TRIGGER_RFTC_VALID;\r
+ SCIFA2.FCR.WORD = _SCIF_LOOPBACK_DISABLE | _SCIF_MODEM_CONTROL_DISABLE;\r
+\r
+ /* Disable transmit/receive FIFO data register reset operation */\r
+ SCIFA2.FCR.BIT.TFRST = 0U;\r
+ SCIFA2.FCR.BIT.RFRST = 0U;\r
+\r
+ /* Set TXIF2 interrupt priority */\r
+ VIC.PRL111.LONG = _SCIF_PRIORITY_LEVEL2;\r
+\r
+ /* Set TXIF2 interrupt address */\r
+ VIC.VAD111.LONG = (uint32_t)r_scifa2_txif2_interrupt_entry;\r
+\r
+ /* Set RXIF2 interrupt priority */\r
+ VIC.PRL110.LONG = _SCIF_PRIORITY_LEVEL3;\r
+\r
+ /* Set RXIF2 interrupt address */\r
+ VIC.VAD110.LONG = (uint32_t)r_scifa2_rxif2_interrupt_entry;\r
+\r
+ /* Set BRIF2 interrupt priority */\r
+ VIC.PRL109.LONG = _SCIF_PRIORITY_LEVEL5;\r
+\r
+ /* Set BRIF2 interrupt address */\r
+ VIC.VAD109.LONG = (uint32_t)r_scifa2_brif2_interrupt_entry;\r
+\r
+ /* Set DRIF2 interrupt priority */\r
+ VIC.PRL112.LONG = _SCIF_PRIORITY_LEVEL4;\r
+\r
+ /* Set DRIF2 interrupt address */\r
+ VIC.VAD112.LONG = (uint32_t)r_scifa2_drif2_interrupt_entry;\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_SCIFA2_Start\r
+* Description : This function starts SCIFA2.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_SCIFA2_Start(void)\r
+{\r
+ /* Enable TXIF2 interrupt */\r
+ VIC.IEN3.LONG |= 0x00008000UL;\r
+\r
+ /* Enable RXIF2 interrupt */\r
+ VIC.IEN3.LONG |= 0x00004000UL;\r
+\r
+ /* Enable BRIF2 interrupt */\r
+ VIC.IEN3.LONG |= 0x00002000UL;\r
+\r
+ /* Enable DRIF2 interrupt */\r
+ VIC.IEN3.LONG |= 0x00010000UL;\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_SCIFA2_Stop\r
+* Description : This function stops SCIFA2.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_SCIFA2_Stop(void)\r
+{\r
+ /* Disable serial transmit */\r
+ SCIFA2.SCR.BIT.TE = 0U;\r
+\r
+ /* Disable serial receive */\r
+ SCIFA2.SCR.BIT.RE = 0U;\r
+\r
+ /* Disable TXI interrupt */\r
+ SCIFA2.SCR.BIT.TIE = 0U;\r
+\r
+ /* Disable RXI and ERI interrupt */\r
+ SCIFA2.SCR.BIT.RIE = 0U;\r
+\r
+ /* Disable TXIF2 interrupt */\r
+ VIC.IEC3.LONG = 0x00008000UL;\r
+\r
+ /* Disable RXIF2 interrupt */\r
+ VIC.IEC3.LONG = 0x00004000UL;\r
+\r
+ /* Disable BRIF2 interrupt */\r
+ VIC.IEC3.LONG = 0x00002000UL;\r
+\r
+ /* Disable DRIF2 interrupt */\r
+ VIC.IEC3.LONG = 0x00010000UL;\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_SCIFA2_Serial_Receive\r
+* Description : This function receives SCIFA2 data.\r
+* Arguments : rx_buf -\r
+* receive buffer pointer (Not used when receive data handled by DMAC)\r
+* rx_num -\r
+* buffer size (Not used when receive data handled by DMAC)\r
+* Return Value : status -\r
+* MD_OK or MD_ARGERROR\r
+***********************************************************************************************************************/\r
+MD_STATUS R_SCIFA2_Serial_Receive(uint8_t * rx_buf, uint16_t rx_num)\r
+{\r
+ MD_STATUS status = MD_OK;\r
+\r
+ if (rx_num < 1U)\r
+ {\r
+ status = MD_ARGERROR;\r
+ }\r
+ else\r
+ {\r
+ g_scifa2_rx_count = 0U;\r
+ g_scifa2_rx_length = rx_num;\r
+ gp_scifa2_rx_address = rx_buf;\r
+\r
+ SCIFA2.FTCR.BIT.RFTC = _SCIF_RX_TRIG_NUM_2;\r
+\r
+ SCIFA2.SCR.BIT.RE = 1U;\r
+ SCIFA2.SCR.BIT.RIE = 1U;\r
+ SCIFA2.SCR.BIT.REIE = 1U;\r
+ }\r
+\r
+ return (status);\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_SCIFA2_Serial_Send\r
+* Description : This function transmits SCIFA2 data.\r
+* Arguments : tx_buf -\r
+* transfer buffer pointer (Not used when transmit data handled by DMAC)\r
+* tx_num -\r
+* buffer size (Not used when transmit data handled by DMAC)\r
+* Return Value : status -\r
+* MD_OK or MD_ARGERROR\r
+***********************************************************************************************************************/\r
+MD_STATUS R_SCIFA2_Serial_Send(const uint8_t * tx_buf, uint16_t tx_num)\r
+{\r
+ MD_STATUS status = MD_OK;\r
+\r
+ if (tx_num < 1U)\r
+ {\r
+ status = MD_ARGERROR;\r
+ }\r
+ else\r
+ {\r
+ gp_scifa2_tx_address = tx_buf;\r
+ g_scifa2_tx_count = tx_num;\r
+ SCIFA2.SCR.BIT.TE = 1U;\r
+ SCIFA2.SCR.BIT.TIE = 1U;\r
+ }\r
+\r
+ return (status);\r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_scifa.h\r
+* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]\r
+* Device(s) : R7S910018CBG\r
+* Tool-Chain : GCCARM\r
+* Description : This file implements device driver for SCIF module.\r
+* Creation Date: 19/04/2015\r
+***********************************************************************************************************************/\r
+#ifndef SCIF_H\r
+#define SCIF_H\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+\r
+/*\r
+ Serial mode register (SMR)\r
+*/\r
+/* Clock select (CKS[1:0]) */\r
+#define _SCIF_CLOCK_SERICLK (0x0000U) /* SERICLK */\r
+#define _SCIF_CLOCK_SERICLK_4 (0x0001U) /* SERICLK/4 */\r
+#define _SCIF_CLOCK_SERICLK_16 (0x0002U) /* SERICLK/16 */\r
+#define _SCIF_CLOCK_SERICLK_64 (0x0003U) /* SERICLK/64 */\r
+/* Stop bit length (STOP) */\r
+#define _SCIF_STOP_1 (0x0000U) /* 1 stop bit */\r
+#define _SCIF_STOP_2 (0x0008U) /* 2 stop bits */\r
+/* Parity mode (PM) */\r
+#define _SCIF_PARITY_EVEN (0x0000U) /* Parity even */\r
+#define _SCIF_PARITY_ODD (0x0010U) /* Parity odd */\r
+/* Parity enable (PE) */\r
+#define _SCIF_PARITY_DISABLE (0x0000U) /* Parity disable */\r
+#define _SCIF_PARITY_ENABLE (0x0020U) /* Parity enable */\r
+/* Character length (CHR) */\r
+#define _SCIF_DATA_LENGTH_8 (0x0000U) /* Data length 8 bits */\r
+#define _SCIF_DATA_LENGTH_7 (0x0040U) /* Data length 7 bits */\r
+/* Communications mode (CM) */\r
+#define _SCIF_ASYNCHRONOUS_MODE (0x0000U) /* Asynchronous mode */\r
+#define _SCIF_CLOCK_SYNCHRONOUS_MODE (0x0080U) /* Clock synchronous mode */\r
+\r
+/*\r
+ Serial control register (SCR)\r
+*/\r
+/* Clock enable (CKE) */\r
+#define _SCIF_INTERNAL_SCK_UNUSED (0x0000U) /* Internal clock selected, SCK pin unused */\r
+#define _SCIF_INTERNAL_SCK_OUTPUT (0x0001U) /* Internal clock selected, SCK pin as clock output */\r
+/* Clock enable (CKE) for clock synchronous mode */\r
+#define _SCIF_INTERNAL_SCK_OUTPUT_SYNC (0x0000U) /* Internal clock, SCK pin is used for clock output */\r
+#define _SCIF_EXTERNAL_SCK_INPUT_SYNC (0x0002U) /* External clock, SCK pin is used for clock input */\r
+/* Transmit end interrupt enable (TEIE) */\r
+#define _SCIF_TEI_INTERRUPT_DISABLE (0x0000U) /* TEI interrupt request disable */\r
+#define _SCIF_TEI_INTERRUPT_ENABLE (0x0004U) /* TEI interrupt request enable */\r
+/* Receive error interrupt enable (REIE) */\r
+#define _SCIF_ERI_BRI_INTERRUPT_DISABLE (0x0000U) /* Disable receive-error interrupt and break interrupt */\r
+#define _SCIF_ERI_BRI_INTERRUPT_ENABLE (0x0008U) /* Enable receive-error interrupt and break interrupt */\r
+/* Receive enable (RE) */\r
+#define _SCIF_RECEIVE_DISABLE (0x0000U) /* Disable receive mode */\r
+#define _SCIF_RECEIVE_ENABLE (0x0010U) /* Enable receive mode */\r
+/* Transmit enable (TE) */\r
+#define _SCIF_TRANSMIT_DISABLE (0x0000U) /* Disable transmit mode */\r
+#define _SCIF_TRANSMIT_ENABLE (0x0020U) /* Enable transmit mode */\r
+/* Receive interrupt enable (RIE) */\r
+#define _SCIF_RXI_ERI_DISABLE (0x0000U) /* Disable RXI and ERI interrupt requests */\r
+#define _SCIF_RXI_ERI_ENABLE (0x0040U) /* Enable RXI and ERI interrupt requests */\r
+/* Transmit interrupt enable (TIE) */\r
+#define _SCIF_TXI_DISABLE (0x0000U) /* Disable TXI interrupt requests */\r
+#define _SCIF_TXI_ENABLE (0x0080U) /* Enable TXI interrupt requests */\r
+\r
+/*\r
+ FIFO control register (FCR)\r
+*/\r
+/* Loop-Back test (LOOP) */\r
+#define _SCIF_LOOPBACK_DISABLE (0x0000U) /* Loop back test is disabled */\r
+#define _SCIF_LOOPBACK_ENABLE (0x0001U) /* Loop back test is enabled */\r
+/* Receive FIFO Data Register Reset (RFRST) */\r
+#define _SCIF_RX_FIFO_RESET_DISABLE (0x0000U) /* FRDR reset operation is disabled */\r
+#define _SCIF_RX_FIFO_RESET_ENABLE (0x0002U) /* FRDR reset operation is enabled */\r
+/* Transmit FIFO Data Register Reset (TFRST) */\r
+#define _SCIF_TX_FIFO_RESET_DISABLE (0x0000U) /* FTDR reset operation is disabled */\r
+#define _SCIF_TX_FIFO_RESET_ENABLE (0x0004U) /* FTDR reset operation is enabled */\r
+/* Modem control enable (MCE) */\r
+#define _SCIF_MODEM_CONTROL_DISABLE (0x0000U) /* Model signal is disabled */\r
+#define _SCIF_MODEM_CONTROL_ENABLE (0x0008U) /* Model signal is enabled */\r
+/* Transmit FIFO Data Trigger Number (TTRG[1:0]) */\r
+#define _SCIF_TX_TRIGGER_NUMBER_8 (0x0000U) /* 8 (or 8 when TDFE flag is 1) */\r
+#define _SCIF_TX_TRIGGER_NUMBER_4 (0x0010U) /* 4 (or 12 when TDFE flag is 1) */\r
+#define _SCIF_TX_TRIGGER_NUMBER_2 (0x0020U) /* 2 (or 14 when TDFE flag is 1) */\r
+#define _SCIF_TX_TRIGGER_NUMBER_0 (0x0030U) /* 0 (or 16 when TDFE flag is 1) */\r
+/* Receive FIFO Data Trigger Number (RTRG[1:0]) */\r
+#define _SCIF_RX_TRIGGER_NUMBER_1 (0x0000U) /* 1 */\r
+#define _SCIF_RX_TRIGGER_NUMBER_4 (0x0040U) /* 4 (for asynchronous mode) */\r
+#define _SCIF_RX_TRIGGER_NUMBER_2 (0x0040U) /* 2 (for clock synchronous mode */\r
+#define _SCIF_RX_TRIGGER_NUMBER_8 (0x0080U) /* 8 */\r
+#define _SCIF_RX_TRIGGER_NUMBER_14 (0x00C0U) /* 14 */\r
+/* RTS# Output Active Trigger Number Select (RSTRG[2:0]) */\r
+#define _SCIF_RTS_TRIGGER_NUMBER_15 (0x0000U) /* 15 */\r
+#define _SCIF_RTS_TRIGGER_NUMBER_1 (0x0100U) /* 1 */\r
+#define _SCIF_RTS_TRIGGER_NUMBER_4 (0x0200U) /* 4 */\r
+#define _SCIF_RTS_TRIGGER_NUMBER_6 (0x0300U) /* 6 */\r
+#define _SCIF_RTS_TRIGGER_NUMBER_8 (0x0400U) /* 8 */\r
+#define _SCIF_RTS_TRIGGER_NUMBER_10 (0x0500U) /* 10 */\r
+#define _SCIF_RTS_TRIGGER_NUMBER_12 (0x0600U) /* 12 */\r
+#define _SCIF_RTS_TRIGGER_NUMBER_14 (0x0700U) /* 14 */\r
+\r
+/*\r
+ Serial port register (SPTR)\r
+*/\r
+/* Serial Port Break Data (SPB2DT) */\r
+#define _SCIF_SERIAL_BREAK_DATA_LOW (0x0000U) /* Input/output data is at low */\r
+#define _SCIF_SERIAL_BREAK_DATA_HIGH (0x0001U) /* Input/output data is at high */\r
+/* Serial Port Break input/output (SPB2IO) */\r
+#define _SCIF_SERIAL_BREAK_TXD_NO_OUTPUT (0x0000U) /* SPB2DT bit value is not output to TXD pin */\r
+#define _SCIF_SERIAL_BREAK_TXD_OUTPUT (0x0002U) /* SPB2DT bit value is output to TXD pin */\r
+/* SCK Port Data (SCKDT) */\r
+#define _SCIF_SCK_DATA_LOW (0x0000U) /* Input/output data is at low */\r
+#define _SCIF_SCK_DATA_HIGH (0x0004U) /* Input/output data is at high */\r
+/* SCK Port input/output (SCKIO) */\r
+#define _SCIF_SCK_PORT_NO_OUTPUT (0x0000U) /* SCKDT bit value is not output to SCK pin */\r
+#define _SCIF_SCK_PORT_OUTPUT (0x0008U) /* SCKDT bit value is output to SCK pin */\r
+/* CTS# Port Data Select (CTS2DT) */\r
+#define _SCIF_CTS_DATA_0 (0x0000U) /* Set b4 to 0. Controls CTS# pin with MCE, CTS2IO bit */\r
+#define _SCIF_CTS_DATA_1 (0x0010U) /* Set b4 to 1. Controls CTS# pin with MCE, CTS2IO bit */\r
+/* CTS# Port Output Specify (CTS2IO) */\r
+#define _SCIF_CTS_OUTPUT_0 (0x0000U) /* Set b5 to 0. Controls CTS# pin with MCE, CTS2IO bit */\r
+#define _SCIF_CTS_OUTPUT_1 (0x0020U) /* Set b5 to 1. Controls CTS# pin with MCE, CTS2IO bit */\r
+/* RTS# Port Data Select (RTS2DT) */\r
+#define _SCIF_RTS_DATA_0 (0x0000U) /* Set b6 to 0. Controls RTS# pin with MCE, RTS2IO bit */\r
+#define _SCIF_RTS_DATA_1 (0x0040U) /* Set b6 to 1. Controls RTS# pin with MCE, RTS2IO bit */\r
+/* RTS# Port Output Specify (RTS2IO) */\r
+#define _SCIF_RTS_OUTPUT_0 (0x0000U) /* Set b7 to 0. Controls RTS# pin with MCE, RTS2IO bit */\r
+#define _SCIF_RTS_OUTPUT_1 (0x0080U) /* Set b7 to 1. Controls RTS# pin with MCE, RTS2IO bit */\r
+\r
+/*\r
+ FIFO Trigger Control Register (FTCR)\r
+*/\r
+/* Transmit FIFO Data Trigger Number (TFTC[4:0]) */\r
+#define _SCIF_TX_FIFO_TRIGGER_NUM_0 (0x0000U) /* 0 (no transmit data trigger) */\r
+#define _SCIF_TX_FIFO_TRIGGER_NUM_1 (0x0001U) /* 1 (transmit data triggers) */\r
+#define _SCIF_TX_FIFO_TRIGGER_NUM_2 (0x0002U) /* 2 (transmit data triggers) */\r
+#define _SCIF_TX_FIFO_TRIGGER_NUM_3 (0x0003U) /* 3 (transmit data triggers) */\r
+#define _SCIF_TX_FIFO_TRIGGER_NUM_4 (0x0004U) /* 4 (transmit data triggers) */\r
+#define _SCIF_TX_FIFO_TRIGGER_NUM_5 (0x0005U) /* 5 (transmit data triggers) */\r
+#define _SCIF_TX_FIFO_TRIGGER_NUM_6 (0x0006U) /* 6 (transmit data triggers) */\r
+#define _SCIF_TX_FIFO_TRIGGER_NUM_7 (0x0007U) /* 7 (transmit data triggers) */\r
+#define _SCIF_TX_FIFO_TRIGGER_NUM_8 (0x0008U) /* 8 (transmit data triggers) */\r
+#define _SCIF_TX_FIFO_TRIGGER_NUM_9 (0x0009U) /* 9 (transmit data triggers) */\r
+#define _SCIF_TX_FIFO_TRIGGER_NUM_10 (0x000AU) /* 10 (transmit data triggers) */\r
+#define _SCIF_TX_FIFO_TRIGGER_NUM_11 (0x000BU) /* 11 (transmit data triggers) */\r
+#define _SCIF_TX_FIFO_TRIGGER_NUM_12 (0x000CU) /* 12 (transmit data triggers) */\r
+#define _SCIF_TX_FIFO_TRIGGER_NUM_13 (0x000DU) /* 13 (transmit data triggers) */\r
+#define _SCIF_TX_FIFO_TRIGGER_NUM_14 (0x000EU) /* 14 (transmit data triggers) */\r
+#define _SCIF_TX_FIFO_TRIGGER_NUM_15 (0x000FU) /* 15 (transmit data triggers) */\r
+/* Transmit Trigger Select (TTRGS) */\r
+#define _SCIF_TX_TRIGGER_TTRG_VALID (0x0000U) /* TTRG[1:0] bits in FCR are valid */\r
+#define _SCIF_TX_TRIGGER_TFTC_VALID (0x0080U) /* TFTC[4:0] bits in FTCR are valid */\r
+/* Receive FIFO Data Trigger Number (RFTC[4:0]) */\r
+#define _SCIF_RX_FIFO_TRIGGER_NUM_1 (0x0100U) /* 1 (no receive data trigger) */\r
+#define _SCIF_RX_FIFO_TRIGGER_NUM_2 (0x0200U) /* 2 (receive data triggers) */\r
+#define _SCIF_RX_FIFO_TRIGGER_NUM_3 (0x0300U) /* 3 (receive data triggers) */\r
+#define _SCIF_RX_FIFO_TRIGGER_NUM_4 (0x0400U) /* 4 (receive data triggers) */\r
+#define _SCIF_RX_FIFO_TRIGGER_NUM_5 (0x0500U) /* 5 (receive data triggers) */\r
+#define _SCIF_RX_FIFO_TRIGGER_NUM_6 (0x0600U) /* 6 (receive data triggers) */\r
+#define _SCIF_RX_FIFO_TRIGGER_NUM_7 (0x0700U) /* 7 (receive data triggers) */\r
+#define _SCIF_RX_FIFO_TRIGGER_NUM_8 (0x0800U) /* 8 (receive data triggers) */\r
+#define _SCIF_RX_FIFO_TRIGGER_NUM_9 (0x0900U) /* 9 (receive data triggers) */\r
+#define _SCIF_RX_FIFO_TRIGGER_NUM_10 (0x0A00U) /* 10 (receive data triggers) */\r
+#define _SCIF_RX_FIFO_TRIGGER_NUM_11 (0x0B00U) /* 11 (receive data triggers) */\r
+#define _SCIF_RX_FIFO_TRIGGER_NUM_12 (0x0C00U) /* 12 (receive data triggers) */\r
+#define _SCIF_RX_FIFO_TRIGGER_NUM_13 (0x0D00U) /* 13 (receive data triggers) */\r
+#define _SCIF_RX_FIFO_TRIGGER_NUM_14 (0x0E00U) /* 14 (receive data triggers) */\r
+#define _SCIF_RX_FIFO_TRIGGER_NUM_15 (0x0F00U) /* 15 (receive data triggers) */\r
+#define _SCIF_RX_FIFO_TRIGGER_NUM_16 (0x1000U) /* 16 (receive data triggers) */\r
+/* Transmit Trigger Select (RTRGS) */\r
+#define _SCIF_RX_TRIGGER_RTRG_VALID (0x0000U) /* RTRG[1:0] bits in FCR are valid */\r
+#define _SCIF_RX_TRIGGER_RFTC_VALID (0x8000U) /* RFTC[4:0] bits in FTCR are valid */\r
+\r
+/*\r
+ Serial extended mode register (SEMR)\r
+*/\r
+/* Asynchronous base clock select (ABCS0) */\r
+#define _SCIF_16_BASE_CLOCK (0x00U) /* Selects 16 base clock cycles for 1 bit period */\r
+#define _SCIF_8_BASE_CLOCK (0x01U) /* Selects 8 base clock cycles for 1 bit period */\r
+/* Noise Cancellation Enable (NFEN) */\r
+#define _SCIF_NOISE_FILTER_DISABLE (0x00U) /* Noise cancellation for the RxD pin input is disabled */\r
+#define _SCIF_NOISE_FILTER_ENABLE (0x04U) /* Noise cancellation for the RxD pin input is enabled */\r
+/* Data Transfer Direction Select (DIR) */\r
+#define _SCIF_DATA_TRANSFER_LSB_FIRST (0x00U) /* Transmits the data in FTDR by the LSB-first method */\r
+#define _SCIF_DATA_TRANSFER_MSB_FIRST (0x08U) /* Transmits the data in FTDR by the MSB-first method */\r
+/* Modulation Duty Register Select (MDDRS) */\r
+#define _SCIF_BRR_USED (0x00U) /* BRR register can be accessed */\r
+#define _SCIF_MDDR_USED (0x10U) /* MDDR register can be accessed. */\r
+/* Bit Rate Modulation Enable (BRME) */\r
+#define _SCIF_BIT_RATE_MODULATION_DISABLE (0x00U) /* Bit rate modulation function is disabled */\r
+#define _SCIF_BIT_RATE_MODULATION_ENABLE (0x20U) /* Bit rate modulation function is enabled */\r
+/* Baud Rate Generator Double-Speed Mode Select (BGDM) */\r
+#define _SCIF_BAUDRATE_SINGLE (0x00U) /* Baud rate generator outputs normal frequency */\r
+#define _SCIF_BAUDRATE_DOUBLE (0x80U) /* Baud rate generator doubles output frequency */\r
+\r
+/*\r
+ Interrupt Source Priority Register n (PRLn)\r
+*/\r
+/* Interrupt Priority Level Select (PRL[3:0]) */\r
+#define _SCIF_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (highest) */\r
+#define _SCIF_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */\r
+#define _SCIF_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */\r
+#define _SCIF_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */\r
+#define _SCIF_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */\r
+#define _SCIF_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */\r
+#define _SCIF_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */\r
+#define _SCIF_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */\r
+#define _SCIF_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */\r
+#define _SCIF_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */\r
+#define _SCIF_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */\r
+#define _SCIF_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */\r
+#define _SCIF_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */\r
+#define _SCIF_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */\r
+#define _SCIF_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */\r
+#define _SCIF_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 */\r
+\r
+/* FIFO buffer maximum size */\r
+#define _SCIF_FIFO_MAX_SIZE (0x10U) /* Size of 16-stage FIFO buffer */\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+#define _SCIF_1BIT_INTERVAL_2 (0x0619U) /* Wait time for 1-bit interval */\r
+#define _SCIF_RX_TRIG_NUM_2 (0x01U) /* Receive FIFO data trigger number */\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+typedef enum\r
+{\r
+ OVERRUN_ERROR,\r
+ BREAK_DETECT,\r
+ RECEIVE_ERROR\r
+} scif_error_type_t;\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+void R_SCIFA2_Create(void);\r
+void R_SCIFA2_Start(void);\r
+void R_SCIFA2_Stop(void);\r
+MD_STATUS R_SCIFA2_Serial_Send(const uint8_t * tx_buf, uint16_t tx_num);\r
+MD_STATUS R_SCIFA2_Serial_Receive(uint8_t * rx_buf, uint16_t rx_num);\r
+void r_scifa2_callback_transmitend(void);\r
+void r_scifa2_callback_receiveend(void);\r
+void r_scifa2_callback_error(scif_error_type_t error_type);\r
+\r
+/* Start user code for function. Do not edit comment generated here */\r
+\r
+/* Declared volatile to prevent it being optimised out in Release build mode */\r
+extern volatile uint8_t g_uart_in;\r
+\r
+/* End user code. Do not edit comment generated here */\r
+#endif\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability\r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_scifa_user.c\r
+* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]\r
+* Device(s) : R7S910018CBG\r
+* Tool-Chain : GCCARM\r
+* Description : This file implements device driver for SCIF module.\r
+* Creation Date: 19/04/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_scifa.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+#include "r_typedefs.h"\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "serial.h"\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+extern const uint8_t * gp_scifa2_tx_address; /* SCIFA2 send buffer address */\r
+extern uint16_t g_scifa2_tx_count; /* SCIFA2 send data number */\r
+extern uint8_t * gp_scifa2_rx_address; /* SCIFA2 receive buffer address */\r
+extern uint16_t g_scifa2_rx_count; /* SCIFA2 receive data number */\r
+extern uint16_t g_scifa2_rx_length; /* SCIFA2 receive data length */\r
+\r
+/* Start user code for global. Do not edit comment generated here */\r
+\r
+/* Characters received from the UART are stored in this queue, ready to be\r
+received by the application. ***NOTE*** Using a queue in this way is very\r
+convenient, but also very inefficient. It can be used here because characters\r
+will only arrive slowly. In a higher bandwidth system a circular RAM buffer or\r
+DMA should be used in place of this queue. */\r
+static QueueHandle_t xRxQueue = NULL;\r
+\r
+/* When a task calls vSerialPutString() its handle is stored in xSendingTask,\r
+before being placed into the Blocked state (so does not use any CPU time) to\r
+wait for the transmission to end. The task handle is then used from the UART\r
+transmit end interrupt to remove the task from the Blocked state. */\r
+static TaskHandle_t xSendingTask = NULL;\r
+\r
+/*\r
+ * Entry point for the handlers. These set the pxISRFunction variable to point\r
+ * to the C handler for each timer, then branch to the FreeRTOS IRQ handler.\r
+ */\r
+#ifdef __GNUC__\r
+ void r_scifa2_txif2_interrupt_entry( void ) __attribute__((naked));\r
+ void r_scifa2_rxif2_interrupt_entry( void ) __attribute__((naked));\r
+ void r_scifa2_drif2_interrupt_entry( void ) __attribute__((naked));\r
+ void r_scifa2_brif2_interrupt_entry( void ) __attribute__((naked));\r
+#endif /* __GNUC__ */\r
+\r
+#ifdef __ICCARM__\r
+ /* IAR requires the entry point to be in an assembly file. The functions\r
+ are implemented in $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm. */\r
+ extern void r_scifa2_txif2_interrupt_entry( void );\r
+ extern void r_scifa2_rxif2_interrupt_entry( void );\r
+ extern void r_scifa2_drif2_interrupt_entry( void );\r
+ extern void r_scifa2_brif2_interrupt_entry( void );\r
+#endif /* __ICCARM__ */\r
+\r
+\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: r_scifa2_txif2_interrupt\r
+* Description : This function is TXIF2 interrupt service routine.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void r_scifa2_txif2_interrupt(void)\r
+{\r
+ uint16_t count = 0;\r
+\r
+ /* Get the amount of untransmitted data stored in the FRDR register */\r
+ uint16_t dummy_fdr = SCIFA2.FDR.BIT.T;\r
+\r
+ /* Write data to the transmit FIFO data register */\r
+ while ((g_scifa2_tx_count > 0U) && (count < _SCIF_FIFO_MAX_SIZE - dummy_fdr))\r
+ {\r
+ SCIFA2.FTDR = *gp_scifa2_tx_address;\r
+ gp_scifa2_tx_address++;\r
+ g_scifa2_tx_count--;\r
+ count++;\r
+ }\r
+\r
+ if (SCIFA2.FSR.BIT.TDFE == 1U)\r
+ {\r
+ SCIFA2.FSR.BIT.TDFE = 0U;\r
+ }\r
+\r
+ if (g_scifa2_tx_count <= 0U)\r
+ {\r
+ SCIFA2.SCR.BIT.TIE = 0U;\r
+ SCIFA2.SCR.BIT.TEIE = 1U;\r
+ }\r
+\r
+ /* Wait the interrupt signal is disabled */\r
+ while (0U != (VIC.IRQS3.LONG & 0x00008000UL))\r
+ {\r
+ VIC.IEC3.LONG = 0x00008000UL;\r
+ }\r
+\r
+ VIC.IEN3.LONG |= 0x00008000UL;\r
+\r
+ /* Dummy write */\r
+ VIC.HVA0.LONG = 0x00000000UL;\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: r_scifa2_rxif2_interrupt\r
+* Description : This function is RXIF2 interrupt service routine.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void r_scifa2_rxif2_interrupt(void)\r
+{\r
+ uint16_t count = 0;\r
+\r
+ /* Get the amount of receive data stored in FRDR register */\r
+ uint16_t dummy_fdr = SCIFA2.FDR.BIT.R;\r
+\r
+ /* Read data from the receive FIFO data register */\r
+ while ((g_scifa2_rx_length > g_scifa2_rx_count) && (count < dummy_fdr))\r
+ {\r
+ *gp_scifa2_rx_address = SCIFA2.FRDR;\r
+ gp_scifa2_rx_address++;\r
+ g_scifa2_rx_count++;\r
+ count++;\r
+ }\r
+\r
+ /* If remaining data is less than the receive trigger number, receive interrupt will not occur.\r
+ In this case, set trigger number to 1 to force receive interrupt for each one byte of data in FRDR */\r
+ if ((g_scifa2_rx_length - g_scifa2_rx_count < _SCIF_RX_TRIG_NUM_2) && (SCIFA2.FTCR.BIT.RFTC != 1U))\r
+ {\r
+ SCIFA2.FTCR.BIT.RFTC = 1U;\r
+ }\r
+\r
+ /* Clear receive FIFO data full flag */\r
+ if (SCIFA2.FSR.BIT.RDF == 1U)\r
+ {\r
+ SCIFA2.FSR.BIT.RDF = 0U;\r
+ }\r
+\r
+ if (g_scifa2_rx_length <= g_scifa2_rx_count)\r
+ {\r
+ /* All data received */\r
+ SCIFA2.SCR.BIT.RE = 0U;\r
+ r_scifa2_callback_receiveend();\r
+ }\r
+\r
+ /* Wait the interrupt signal is disabled */\r
+ while (0U != (VIC.IRQS3.LONG & 0x00004000UL))\r
+ {\r
+ VIC.IEC3.LONG = 0x00004000UL;\r
+ }\r
+\r
+ VIC.IEN3.LONG |= 0x00004000UL;\r
+\r
+ /* Dummy write */\r
+ VIC.HVA0.LONG = 0x00000000UL;\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: r_scifa2_drif2_interrupt\r
+* Description : This function is TEIF 2 or DRIF2 interrupt service routine.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void r_scifa2_drif2_interrupt(void)\r
+{\r
+ if (1U == SCIFA2.FSR.BIT.TEND)\r
+ {\r
+ SCIFA2.SPTR.BIT.SPB2DT = 0U;\r
+ SCIFA2.SPTR.BIT.SPB2IO = 1U;\r
+ SCIFA2.SCR.BIT.TE = 0U;\r
+ SCIFA2.SCR.BIT.TEIE = 0U;\r
+ }\r
+ r_scifa2_callback_transmitend();\r
+\r
+ /* Clear data ready detect flag */\r
+ if (1U == SCIFA2.FSR.BIT.DR)\r
+ {\r
+ /* Start user code. Do not edit comment generated here */\r
+ /* End user code. Do not edit comment generated here */\r
+ SCIFA2.FSR.BIT.DR = 0U;\r
+ }\r
+\r
+ /* Wait the interrupt signal is disabled */\r
+ while (0U != (VIC.IRQS3.LONG & 0x00010000UL))\r
+ {\r
+ VIC.IEC3.LONG = 0x00010000UL;\r
+ }\r
+\r
+ VIC.IEN3.LONG |= 0x00010000UL;\r
+\r
+ /* Dummy write */\r
+ VIC.HVA0.LONG = 0x00000000UL;\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: r_scifa2_brif2_interrupt\r
+* Description : This function is BRIF2 or ERIF2 interrupt service routine.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void r_scifa2_brif2_interrupt(void)\r
+{\r
+ if (1U == SCIFA2.FSR.BIT.BRK)\r
+ {\r
+ r_scifa2_callback_error(BREAK_DETECT);\r
+ /* Clear break detect flag */\r
+ SCIFA2.FSR.BIT.BRK = 0U;\r
+ }\r
+\r
+ if (1U == SCIFA2.FSR.BIT.ER)\r
+ {\r
+ r_scifa2_callback_error(RECEIVE_ERROR);\r
+ /* Clear receive error flag */\r
+ SCIFA2.FSR.BIT.ER = 0U;\r
+ }\r
+\r
+ if (1U == SCIFA2.LSR.BIT.ORER)\r
+ {\r
+ r_scifa2_callback_error(OVERRUN_ERROR);\r
+ /* Clear overrun error flag */\r
+ SCIFA2.LSR.BIT.ORER = 0U;\r
+ }\r
+\r
+ /* Wait the interrupt signal is disabled */\r
+ while (0U != (VIC.IRQS3.LONG & 0x00002000UL))\r
+ {\r
+ VIC.IEC3.LONG = 0x00002000UL;\r
+ }\r
+\r
+ VIC.IEN3.LONG |= 0x00002000UL;\r
+\r
+ /* Dummy write */\r
+ VIC.HVA0.LONG = 0x00000000UL;\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: r_scifa2_callback_transmitend\r
+* Description : This function is a callback function when SCIFA2 finishes transmission.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void r_scifa2_callback_transmitend(void)\r
+{\r
+ /* Start user code. Do not edit comment generated here */\r
+ BaseType_t xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ if( xSendingTask != NULL )\r
+ {\r
+ /* A task is waiting for the end of the Tx, unblock it now.\r
+ http://www.freertos.org/vTaskNotifyGiveFromISR.html */\r
+ vTaskNotifyGiveFromISR( xSendingTask, &xHigherPriorityTaskWoken );\r
+ xSendingTask = NULL;\r
+\r
+ portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\r
+ }\r
+\r
+ /* End user code. Do not edit comment generated here */\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: r_scifa2_callback_receiveend\r
+* Description : This function is a callback function when SCIFA2 finishes reception.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void r_scifa2_callback_receiveend(void)\r
+{\r
+ /* Start user code. Do not edit comment generated here */\r
+ uint8_t ucRxedChar = 0;\r
+ BaseType_t xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ /* Read the received data */\r
+ ucRxedChar = SCIFA2.FRDR;\r
+\r
+ /* Characters received from the UART are stored in this queue, ready to be\r
+ received by the application. ***NOTE*** Using a queue in this way is very\r
+ convenient, but also very inefficient. It can be used here because\r
+ characters will only arrive slowly. In a higher bandwidth system a circular\r
+ RAM buffer or DMA should be used in place of this queue. */\r
+ xQueueSendFromISR( xRxQueue, ( void * ) &ucRxedChar, &xHigherPriorityTaskWoken );\r
+\r
+ /* Re-enable receptions */\r
+ SCIFA2.SCR.BIT.RE = 1U;\r
+\r
+ /* End user code. Do not edit comment generated here */\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: r_scifa2_callback_error\r
+* Description : This function is a callback function when SCIFA2 reception encounters error.\r
+* Arguments : error_type -\r
+* reception error type\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void r_scifa2_callback_error(scif_error_type_t error_type)\r
+{\r
+ /* Start user code. Do not edit comment generated here */\r
+\r
+ /* Used to suppress the warning message generated for unused variables */\r
+ UNUSED_PARAM(error_type);\r
+\r
+ /* End user code. Do not edit comment generated here */\r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+\r
+/* Function required in order to link UARTCommandConsole.c - which is used by\r
+multiple different demo application. */\r
+xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+ ( void ) ulWantedBaud;\r
+ ( void ) uxQueueLength;\r
+\r
+ /* Characters received from the UART are stored in this queue, ready to be\r
+ received by the application. ***NOTE*** Using a queue in this way is very\r
+ convenient, but also very inefficient. It can be used here because\r
+ characters will only arrive slowly. In a higher bandwidth system a circular\r
+ RAM buffer or DMA should be used in place of this queue. */\r
+ xRxQueue = xQueueCreate( uxQueueLength, sizeof( char ) );\r
+ configASSERT( xRxQueue );\r
+\r
+ /* Enable the receive. */\r
+ SCIFA2.FTCR.BIT.RFTC = _SCIF_RX_TRIG_NUM_2;\r
+\r
+ SCIFA2.SCR.BIT.RE = 1U;\r
+ SCIFA2.SCR.BIT.RIE = 1U;\r
+ SCIFA2.SCR.BIT.REIE = 1U;\r
+\r
+ /* Enable SCI1 operations */\r
+ R_SCIFA2_Start();\r
+\r
+ /* Only one UART is supported, so it doesn't matter what is returned\r
+ here. */\r
+ return 0;\r
+}\r
+\r
+/* Function required in order to link UARTCommandConsole.c - which is used by\r
+multiple different demo application. */\r
+void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )\r
+{\r
+const TickType_t xMaxBlockTime = pdMS_TO_TICKS( 5000 );\r
+\r
+ /* Only one port is supported. */\r
+ ( void ) pxPort;\r
+\r
+ /* Don't send the string unless the previous string has been sent. */\r
+ if( xSendingTask == NULL )\r
+ {\r
+ /* Ensure the calling task's notification state is not already\r
+ pending. */\r
+ vTaskNotifyStateClear( NULL );\r
+\r
+ /* Store the handle of the transmitting task. This is used to unblock\r
+ the task when the transmission has completed. */\r
+ xSendingTask = xTaskGetCurrentTaskHandle();\r
+\r
+ /* Send the string using the auto-generated API. */\r
+ R_SCIFA2_Serial_Send( ( uint8_t * ) pcString, usStringLength );\r
+\r
+ /* Wait in the Blocked state (so not using any CPU time) until the\r
+ transmission has completed. */\r
+ ulTaskNotifyTake( pdTRUE, xMaxBlockTime );\r
+ }\r
+}\r
+\r
+/* Function required in order to link UARTCommandConsole.c - which is used by\r
+multiple different demo application. */\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )\r
+{\r
+ /* Only one UART is supported. */\r
+ ( void ) pxPort;\r
+\r
+ /* Return a received character, if any are available. Otherwise block to\r
+ wait for a character. */\r
+ return xQueueReceive( xRxQueue, pcRxedChar, xBlockTime );\r
+}\r
+\r
+/* Function required in order to link UARTCommandConsole.c - which is used by\r
+multiple different demo application. */\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime )\r
+{\r
+ /* Just mapped to vSerialPutString() so the block time is not used. */\r
+ ( void ) xBlockTime;\r
+\r
+ vSerialPutString( pxPort, &cOutChar, sizeof( cOutChar ) );\r
+ return pdPASS;\r
+}\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/*\r
+ * The RZ/T vectors directly to a peripheral specific interrupt handler, rather\r
+ * than using the Cortex-R IRQ vector. Therefore each interrupt handler\r
+ * installed by the application must follow the examples below, which save a\r
+ * pointer to a standard C function in the pxISRFunction variable, before\r
+ * branching to the FreeRTOS IRQ handler. The FreeRTOS IRQ handler then manages\r
+ * interrupt entry (including interrupt nesting), before calling the C function\r
+ * saved in the pxISRFunction variable. NOTE: The entry points are naked\r
+ * functions - do not add C code to these functions.\r
+ */\r
+#ifdef __GNUC__\r
+ /* The IAR equivalent is implemented in\r
+ $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */\r
+ void r_scifa2_txif2_interrupt_entry( void )\r
+ {\r
+ __asm volatile ( \\r
+ "PUSH {r0-r1} \t\n" \\r
+ "LDR r0, =pxISRFunction \t\n" \\r
+ "LDR r1, =r_scifa2_txif2_interrupt \t\n" \\r
+ "STR r1, [r0] \t\n" \\r
+ "POP {r0-r1} \t\n" \\r
+ "B FreeRTOS_IRQ_Handler "\r
+ );\r
+ }\r
+#endif /* __GNUC__ */\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __GNUC__\r
+ /* The IAR equivalent is implemented in\r
+ $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */\r
+ void r_scifa2_rxif2_interrupt_entry( void )\r
+ {\r
+ __asm volatile ( \\r
+ "PUSH {r0-r1} \t\n" \\r
+ "LDR r0, =pxISRFunction \t\n" \\r
+ "LDR r1, =r_scifa2_rxif2_interrupt \t\n" \\r
+ "STR r1, [r0] \t\n" \\r
+ "POP {r0-r1} \t\n" \\r
+ "B FreeRTOS_IRQ_Handler "\r
+ );\r
+ }\r
+#endif /* __GNUC__ */\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __GNUC__\r
+ /* The IAR equivalent is implemented in\r
+ $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */\r
+ void r_scifa2_drif2_interrupt_entry( void )\r
+ {\r
+ __asm volatile ( \\r
+ "PUSH {r0-r1} \t\n" \\r
+ "LDR r0, =pxISRFunction \t\n" \\r
+ "LDR r1, =r_scifa2_drif2_interrupt \t\n" \\r
+ "STR r1, [r0] \t\n" \\r
+ "POP {r0-r1} \t\n" \\r
+ "B FreeRTOS_IRQ_Handler "\r
+ );\r
+ }\r
+#endif /* __GNUC__ */\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __GNUC__\r
+ /* The IAR equivalent is implemented in\r
+ $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */\r
+ void r_scifa2_brif2_interrupt_entry( void )\r
+ {\r
+ __asm volatile ( \\r
+ "PUSH {r0-r1} \t\n" \\r
+ "LDR r0, =pxISRFunction \t\n" \\r
+ "LDR r1, =r_scifa2_brif2_interrupt \t\n" \\r
+ "STR r1, [r0] \t\n" \\r
+ "POP {r0-r1} \t\n" \\r
+ "B FreeRTOS_IRQ_Handler "\r
+ );\r
+ }\r
+#endif /* __GNUC__ */\r
+/*-----------------------------------------------------------*/\r
* DISCLAIMER\r
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
+* applicable laws, including copyright laws.\r
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability\r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
* following link:\r
* http://www.renesas.com/disclaimer\r
*\r
#include "r_cg_tpu.h"\r
#include "r_cg_rspi.h"\r
#include "r_cg_mpc.h"\r
+#include "r_cg_scifa.h"\r
/* Start user code for include. Do not edit comment generated here */\r
/* End user code. Do not edit comment generated here */\r
#include "r_cg_userdefine.h"\r
DI();\r
\r
/* Enable writing to registers related to operating modes, LPC, CGC and ATCM */\r
- SYSTEM.PRCR.LONG = 0x0000A50BU; \r
+ SYSTEM.PRCR.LONG = 0x0000A50BU;\r
\r
/* Enable writing to MPC pin function control registers */\r
MPC.PWPR.BIT.B0WI = 0U;\r
R_TPU_Create();\r
R_RSPI1_Create();\r
R_MPC_Create();\r
+ R_SCIFA2_Create();\r
\r
/* Disable writing to MPC pin function control registers */\r
- MPC.PWPR.BIT.PFSWE = 0U; \r
- MPC.PWPR.BIT.B0WI = 1U; \r
+ MPC.PWPR.BIT.PFSWE = 0U;\r
+ MPC.PWPR.BIT.B0WI = 1U;\r
\r
/* Enable protection */\r
SYSTEM.PRCR.LONG = 0x0000A500U;\r
*/\r
static void prvClearBSS( void );\r
\r
-/*\r
- * Configure the hardware as necessary to run this demo.\r
- */\r
-static void prvSetupHardware( void );\r
-\r
/*\r
* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
* main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );\r
void vApplicationTickHook( void );\r
\r
-/* Prototype for the IRQ handler called by the generic Cortex-A5 RTOS port\r
-layer. */\r
-void vApplicationIRQHandler( void );\r
-\r
/* Library initialisation. */\r
extern void R_Systeminit( void );\r
\r
prvClearBSS();\r
\r
/* Configure the hardware ready to run the demo. */\r
- prvSetupHardware();\r
+ R_Systeminit();\r
\r
/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
of this file. */\r
}\r
/*-----------------------------------------------------------*/\r
\r
-static void prvSetupHardware( void )\r
-{\r
- R_Systeminit();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
void vApplicationMallocFailedHook( void )\r
{\r
/* Called if a call to pvPortMalloc() fails because there is insufficient\r
ulTicksToWait = mainERROR_PERIOD;\r
}\r
\r
- /* Toggle the LED each itteration. */\r
+ /* Toggle the LED each iteration. */\r
vParTestToggleLED( mainCHECK_LED );\r
\r
/* For demo only - how much unused stack does this task have? */\r
ulTicksToWait = mainERROR_PERIOD;\r
}\r
\r
- /* Toggle the LED each itteration. */\r
+ /* Toggle the LED each iteration. */\r
vParTestToggleLED( mainCHECK_LED );\r
}\r
}\r
ulTicksToWait = mainERROR_PERIOD;\r
}\r
\r
- /* Toggle the LED each itteration. */\r
+ /* Toggle the LED each iteration. */\r
vParTestToggleLED( mainCHECK_LED );\r
}\r
}\r
<configuration id="%com.renesas.cdt.rx.hardwaredebug.win32.configuration.Id.485661513" name="HardwareDebug">\r
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">\r
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>\r
- <provider class="com.renesas.cdt.common.build.spec.RXGCCBuiltinSpecsDetector" console="false" env-hash="-83633861543855079" id="RXGCCBuiltinSpecsDetector" keep-relative-paths="false" name="Renesas GCCBuildinCompilerSettings" options-hash="-645709713" parameter="rx-elf-gcc -E -P -v -dD ${INPUTS}" prefer-non-shared="true">\r
+ <provider class="com.renesas.cdt.common.build.spec.RXGCCBuiltinSpecsDetector" console="false" env-hash="738196985922260309" id="RXGCCBuiltinSpecsDetector" keep-relative-paths="false" name="Renesas GCCBuildinCompilerSettings" options-hash="-645709713" parameter="rx-elf-gcc -E -P -v -dD ${INPUTS}" prefer-non-shared="true">\r
<language-scope id="org.eclipse.cdt.core.gcc"/>\r
<language-scope id="org.eclipse.cdt.core.g++"/>\r
</provider>\r
MOV.L #14, R14\r
MOV.L #15, R15\r
\r
- ; Loop, checking each itteration that each register still contains the\r
+ ; Loop, checking each iteration that each register still contains the\r
; expected value.\r
TestLoop1:\r
\r
MOV.L #140, R14\r
MOV.L #150, R15\r
\r
- ; Loop, checking on each itteration that each register still contains the\r
+ ; Loop, checking on each iteration that each register still contains the\r
; expected value.\r
TestLoop2:\r
\r
</option>\r
<option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.isa.891020448" name="Instruction set architecture" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.isa" value="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.isa.rxv1" valueType="enumerated"/>\r
<option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.floatIns.887015730" name="Use floating point arithmetic instructions" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.floatIns" value="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.floatIns.enable" valueType="enumerated"/>\r
- <option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.optimizeLevel.964108751" name="Optimize level" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.optimizeLevel" value="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.optimizeLevel.0" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.optimizeLevel.964108751" name="Optimize level" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.optimizeLevel" value="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.optimizeLevel.max" valueType="enumerated"/>\r
<option defaultValue="true" id="com.renesas.cdt.renesas.Compiler.option.GenDebugInfo.159226508" name="Generate debug information" superClass="com.renesas.cdt.renesas.Compiler.option.GenDebugInfo" value="true" valueType="boolean"/>\r
<option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.stuffD.189152785" name="Allocates initialized variables to 4-byte boundary alignment sections" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.stuffD" value="false" valueType="boolean"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.optimizationType.2131923502" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.optimizationType" value="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.optimizationType.speed" valueType="enumerated"/>\r
<inputType id="%Base.Compiler.Shc.C.Input.Id.1411777144" name="C Input" superClass="%Base.Compiler.Shc.C.Input.Id"/>\r
<inputType id="%Base.Compiler.Shc.C.Input1.Id.1988726590" name="C++ Input" superClass="%Base.Compiler.Shc.C.Input1.Id"/>\r
</tool>\r
MOV.L #14, R14\r
MOV.L #15, R15\r
\r
- ; Loop, checking each itteration that each register still contains the\r
+ ; Loop, checking each iteration that each register still contains the\r
; expected value.\r
TestLoop1:\r
\r
MOV.L #140, R14\r
MOV.L #150, R15\r
\r
- ; Loop, checking on each itteration that each register still contains the\r
+ ; Loop, checking on each iteration that each register still contains the\r
; expected value.\r
TestLoop2:\r
\r
MOV.L #14, R14\r
MOV.L #15, R15\r
\r
- ; Loop, checking each itteration that each register still contains the\r
+ ; Loop, checking each iteration that each register still contains the\r
; expected value.\r
TestLoop1:\r
\r
MOV.L #140, R14\r
MOV.L #150, R15\r
\r
- ; Loop, checking on each itteration that each register still contains the\r
+ ; Loop, checking on each iteration that each register still contains the\r
; expected value.\r
TestLoop2:\r
\r
MOV.L #14, R14\r
MOV.L #15, R15\r
\r
- ; Loop, checking each itteration that each register still contains the\r
+ ; Loop, checking each iteration that each register still contains the\r
; expected value.\r
TestLoop1:\r
\r
MOV.L #140, R14\r
MOV.L #150, R15\r
\r
- ; Loop, checking on each itteration that each register still contains the\r
+ ; Loop, checking on each iteration that each register still contains the\r
; expected value.\r
TestLoop2:\r
\r
MVTACLO R2, A0\r
MVTACHI R3, A1\r
MVTACLO R4, A1\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
TestLoop1: \r
\r
MVTACHI R3, A1\r
MVTACLO R4, A1\r
\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
TestLoop2: \r
\r
MOV.L #14, R14\r
MOV.L #15, R15\r
\r
- ; Loop, checking each itteration that each register still contains the\r
+ ; Loop, checking each iteration that each register still contains the\r
; expected value.\r
TestLoop1:\r
\r
MOV.L #140, R14\r
MOV.L #150, R15\r
\r
- ; Loop, checking on each itteration that each register still contains the\r
+ ; Loop, checking on each iteration that each register still contains the\r
; expected value.\r
TestLoop2:\r
\r
"MOV #14, R14 \n" \\r
"MOV #15, R15 \n" \\r
\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
"TestLoop1: \n" \\r
\r
"MOV #140H, R14 \n" \\r
"MOV #150H, R15 \n" \\r
\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
"TestLoop2: \n" \\r
\r
MOV #14, R14 \r
MOV #15, R15 \r
\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
TestLoop1: \r
\r
MOV #140H, R14 \r
MOV #150H, R15 \r
\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
TestLoop2: \r
\r
MOV.L #14, R14\r
MOV.L #15, R15\r
\r
- ; Loop, checking each itteration that each register still contains the\r
+ ; Loop, checking each iteration that each register still contains the\r
; expected value.\r
TestLoop1:\r
\r
MOV.L #140, R14\r
MOV.L #150, R15\r
\r
- ; Loop, checking on each itteration that each register still contains the\r
+ ; Loop, checking on each iteration that each register still contains the\r
; expected value.\r
TestLoop2:\r
\r
"MOV #14, R14 \n" \\r
"MOV #15, R15 \n" \\r
\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
"TestLoop1: \n" \\r
\r
"MOV #140H, R14 \n" \\r
"MOV #150H, R15 \n" \\r
\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
"TestLoop2: \n" \\r
\r
MOV #14, R14 \r
MOV #15, R15 \r
\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
TestLoop1: \r
\r
MOV #140H, R14 \r
MOV #150H, R15 \r
\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
TestLoop2: \r
\r
MOV.L #14, R14\r
MOV.L #15, R15\r
\r
- ; Loop, checking each itteration that each register still contains the\r
+ ; Loop, checking each iteration that each register still contains the\r
; expected value.\r
TestLoop1:\r
\r
MOV.L #140, R14\r
MOV.L #150, R15\r
\r
- ; Loop, checking on each itteration that each register still contains the\r
+ ; Loop, checking on each iteration that each register still contains the\r
; expected value.\r
TestLoop2:\r
\r
MOV.L #14, R14\r
MOV.L #15, R15\r
\r
- ; Loop, checking each itteration that each register still contains the\r
+ ; Loop, checking each iteration that each register still contains the\r
; expected value.\r
TestLoop1:\r
\r
MOV.L #140, R14\r
MOV.L #150, R15\r
\r
- ; Loop, checking on each itteration that each register still contains the\r
+ ; Loop, checking on each iteration that each register still contains the\r
; expected value.\r
TestLoop2:\r
\r
MOV.L #14, R14\r
MOV.L #15, R15\r
\r
- ; Loop, checking each itteration that each register still contains the\r
+ ; Loop, checking each iteration that each register still contains the\r
; expected value.\r
TestLoop1:\r
\r
MOV.L #140, R14\r
MOV.L #150, R15\r
\r
- ; Loop, checking on each itteration that each register still contains the\r
+ ; Loop, checking on each iteration that each register still contains the\r
; expected value.\r
TestLoop2:\r
\r
MOV.L #14, R14\r
MOV.L #15, R15\r
\r
- ; Loop, checking each itteration that each register still contains the\r
+ ; Loop, checking each iteration that each register still contains the\r
; expected value.\r
TestLoop1:\r
\r
MOV.L #140, R14\r
MOV.L #150, R15\r
\r
- ; Loop, checking on each itteration that each register still contains the\r
+ ; Loop, checking on each iteration that each register still contains the\r
; expected value.\r
TestLoop2:\r
\r
MVTACHI R3, A1\r
MVTACLO R4, A1\r
\r
- ;/* Loop, checking each itteration that each register still contains the\r
+ ;/* Loop, checking each iteration that each register still contains the\r
;expected value. */\r
TestLoop1: \r
\r
MVTACHI R3, A1\r
MVTACLO R4, A1\r
\r
- ;/* Loop, checking each itteration that each register still contains the\r
+ ;/* Loop, checking each iteration that each register still contains the\r
;expected value. */\r
TestLoop2: \r
\r
MVTACHI R3, A1\r
MVTACLO R4, A1\r
\r
- ;/* Loop, checking each itteration that each register still contains the\r
+ ;/* Loop, checking each iteration that each register still contains the\r
;expected value. */\r
TestLoop1: \r
\r
MVTACHI R3, A1\r
MVTACLO R4, A1\r
\r
- ;/* Loop, checking each itteration that each register still contains the\r
+ ;/* Loop, checking each iteration that each register still contains the\r
;expected value. */\r
TestLoop2: \r
\r
MVTACHI R3, A1\r
MVTACLO R4, A1\r
\r
- ;/* Loop, checking each itteration that each register still contains the\r
+ ;/* Loop, checking each iteration that each register still contains the\r
;expected value. */\r
TestLoop1: \r
\r
MVTACHI R3, A1\r
MVTACLO R4, A1\r
\r
- ;/* Loop, checking each itteration that each register still contains the\r
+ ;/* Loop, checking each iteration that each register still contains the\r
;expected value. */\r
TestLoop2: \r
\r
MVTACLO R2, A0\r
MVTACHI R3, A1\r
MVTACLO R4, A1\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
TestLoop1: \r
\r
MVTACHI R3, A1\r
MVTACLO R4, A1\r
\r
- /* Loop, checking each itteration that each register still contains the\r
+ /* Loop, checking each iteration that each register still contains the\r
expected value. */\r
TestLoop2: \r
\r
MOV.L #14, R14\r
MOV.L #15, R15\r
\r
- ; Loop, checking each itteration that each register still contains the\r
+ ; Loop, checking each iteration that each register still contains the\r
; expected value.\r
TestLoop1:\r
\r
MOV.L #140, R14\r
MOV.L #150, R15\r
\r
- ; Loop, checking on each itteration that each register still contains the\r
+ ; Loop, checking on each iteration that each register still contains the\r
; expected value.\r
TestLoop2:\r
\r
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