Enable L2 cache for MPC8568MDS board

The L2 cache size is 512KB for 8568, print out the correct informaiton.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 7b9961013c054a74881f43a51e79f25efd0d9697..79ad20c91aa2a2d63d3ad1e8a6b67bc49ae97363 100644 (file)
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -247,7 +247,7 @@ int cpu_init_r(void)
        switch (cache_ctl & 0x30000000) {
        case 0x20000000:
                if (ver == SVR_8548 || ver == SVR_8548_E ||
-                   ver == SVR_8544) {
+                   ver == SVR_8544 || ver == SVR_8568_E) {
                        printf ("L2 cache 512KB:");
                        /* set L2E=1, L2I=1, & L2SRAM=0 */
                        cache_ctl = 0xc0000000;

diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index d5a14fc3922be47bf011e7a13f0c88db922dc208..ba744e99f8d3d0e6437a100570bef7d763c87df9 100644 (file)
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -63,9 +63,9 @@ extern unsigned long get_clock_freq(void);
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
-/*#define CONFIG_L2_CACHE*/                        /* toggle L2 cache  */
-#define CONFIG_BTB                                             /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING              /* toggle addr streaming   */
+#define CONFIG_L2_CACHE                                /* toggle L2 cache      */
+#define CONFIG_BTB                             /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING                  /* toggle addr streaming   */
 
 /*
  * Only possible on E500 Version 2 or newer cores.