ARM: tegra: pinmux: simplify some defines

Future SoCs have a slightly different combination of pinmux options per
pin. This will be simpler to handle if we simply have one define per
option, rather than grouping various options together, in combinations
that don't align with future chips.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h
index ab764960fa7faf82ace592a55734fadcdd77d66a..c95c9738f3106dbc1903f6882b36d6df9c021aee 100644 (file)
--- a/arch/arm/include/asm/arch-tegra/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -23,39 +23,45 @@ enum pmux_tristate {
        PMUX_TRI_TRISTATE = 1,
 };
 
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
 enum pmux_pin_io {
        PMUX_PIN_OUTPUT = 0,
        PMUX_PIN_INPUT = 1,
        PMUX_PIN_NONE,
 };
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
 enum pmux_pin_lock {
        PMUX_PIN_LOCK_DEFAULT = 0,
        PMUX_PIN_LOCK_DISABLE,
        PMUX_PIN_LOCK_ENABLE,
 };
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_OD
 enum pmux_pin_od {
        PMUX_PIN_OD_DEFAULT = 0,
        PMUX_PIN_OD_DISABLE,
        PMUX_PIN_OD_ENABLE,
 };
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
 enum pmux_pin_ioreset {
        PMUX_PIN_IO_RESET_DEFAULT = 0,
        PMUX_PIN_IO_RESET_DISABLE,
        PMUX_PIN_IO_RESET_ENABLE,
 };
+#endif
 
-#ifdef TEGRA_PMX_HAS_RCV_SEL
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
 enum pmux_pin_rcv_sel {
        PMUX_PIN_RCV_SEL_DEFAULT = 0,
        PMUX_PIN_RCV_SEL_NORMAL,
        PMUX_PIN_RCV_SEL_HIGH,
 };
-#endif /* TEGRA_PMX_HAS_RCV_SEL */
-#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+#endif
 
 /*
  * This defines the configuration for a pin, including the function assigned,
@@ -68,19 +74,25 @@ struct pmux_pingrp_config {
        u32 func:8;             /* function to assign PMUX_FUNC_... */
        u32 pull:2;             /* pull up/down/normal PMUX_PULL_...*/
        u32 tristate:2;         /* tristate or normal PMUX_TRI_...  */
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
        u32 io:2;               /* input or output PMUX_PIN_...     */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
        u32 lock:2;             /* lock enable/disable PMUX_PIN...  */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_OD
        u32 od:2;               /* open-drain or push-pull driver   */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
        u32 ioreset:2;          /* input/output reset PMUX_PIN...   */
-#ifdef TEGRA_PMX_HAS_RCV_SEL
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
        u32 rcv_sel:2;          /* select between High and Normal  */
                                /* VIL/VIH receivers */
 #endif
-#endif
 };
 
-#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
+#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
 /* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
 void pinmux_set_tristate_input_clamping(void);
 void pinmux_clear_tristate_input_clamping(void);
@@ -98,7 +110,7 @@ void pinmux_tristate_enable(enum pmux_pingrp pin);
 /* Set a pin group to normal (non tristate) */
 void pinmux_tristate_disable(enum pmux_pingrp pin);
 
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
 /* Set a pin group as input or output */
 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
 #endif
@@ -112,7 +124,7 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
                                int len);
 
-#ifdef TEGRA_PMX_HAS_DRVGRPS
+#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
 
 #define PMUX_SLWF_MIN  0
 #define PMUX_SLWF_MAX  3
@@ -176,7 +188,7 @@ struct pmux_drvgrp_config {
 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
                                int len);
 
-#endif /* TEGRA_PMX_HAS_DRVGRPS */
+#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
 
 struct pmux_pingrp_desc {
        u8 funcs[4];

diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h
index b86562ac6dee99fe4f8f22b49a2f6165145a9d17..06a7572f0db6d7719d8ebfc70e3aa193089f383f 100644 (file)
--- a/arch/arm/include/asm/arch-tegra114/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra114/pinmux.h
@@ -313,9 +313,13 @@ enum pmux_func {
        PMUX_FUNC_COUNT,
 };
 
-#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
-#define TEGRA_PMX_HAS_RCV_SEL
-#define TEGRA_PMX_HAS_DRVGRPS
+#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
+#define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_PINS_HAVE_E_INPUT
+#define TEGRA_PMX_PINS_HAVE_LOCK
+#define TEGRA_PMX_PINS_HAVE_OD
+#define TEGRA_PMX_PINS_HAVE_IO_RESET
+#define TEGRA_PMX_PINS_HAVE_RCV_SEL
 #include <asm/arch-tegra/pinmux.h>
 
 #endif /* _TEGRA114_PINMUX_H_ */

diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
index 1884935a579edb8c794b080625b55d630afe2eca..c440f9fe5afff6ab29bb7d19f2567004d17f4db2 100644 (file)
--- a/arch/arm/include/asm/arch-tegra124/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -335,9 +335,13 @@ enum pmux_func {
        PMUX_FUNC_COUNT,
 };
 
-#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
-#define TEGRA_PMX_HAS_RCV_SEL
-#define TEGRA_PMX_HAS_DRVGRPS
+#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
+#define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_PINS_HAVE_E_INPUT
+#define TEGRA_PMX_PINS_HAVE_LOCK
+#define TEGRA_PMX_PINS_HAVE_OD
+#define TEGRA_PMX_PINS_HAVE_IO_RESET
+#define TEGRA_PMX_PINS_HAVE_RCV_SEL
 #include <asm/arch-tegra/pinmux.h>
 
 #endif /* _TEGRA124_PINMUX_H_ */

diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h
index a42e00990f0c1b4537a61448c9c077a36d9e1aa7..e9046ff36fdde20314010bb685d47384f1dd2dff 100644 (file)
--- a/arch/arm/include/asm/arch-tegra30/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra30/pinmux.h
@@ -391,8 +391,11 @@ enum pmux_func {
        PMUX_FUNC_COUNT,
 };
 
-#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
-#define TEGRA_PMX_HAS_DRVGRPS
+#define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_PINS_HAVE_E_INPUT
+#define TEGRA_PMX_PINS_HAVE_LOCK
+#define TEGRA_PMX_PINS_HAVE_OD
+#define TEGRA_PMX_PINS_HAVE_IO_RESET
 #include <asm/arch-tegra/pinmux.h>
 
 #endif /* _TEGRA30_PINMUX_H_ */

diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c
index 0bef6e246357c0d929f4297e2d914f5557d822c1..5d4d2e9c30021b8f6ae501a2b4c95125ef37f566 100644 (file)
--- a/arch/arm/mach-tegra/pinmux-common.c
+++ b/arch/arm/mach-tegra/pinmux-common.c
@@ -24,31 +24,37 @@
 #define pmux_pin_tristate_isvalid(tristate) \
        (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
 
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
 /* return 1 if a pin_io_is in range */
 #define pmux_pin_io_isvalid(io) \
        (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
 /* return 1 if a pin_lock is in range */
 #define pmux_pin_lock_isvalid(lock) \
        (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_OD
 /* return 1 if a pin_od is in range */
 #define pmux_pin_od_isvalid(od) \
        (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
 /* return 1 if a pin_ioreset_is in range */
 #define pmux_pin_ioreset_isvalid(ioreset) \
        (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
         ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+#endif
 
-#ifdef TEGRA_PMX_HAS_RCV_SEL
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
 /* return 1 if a pin_rcv_sel_is in range */
 #define pmux_pin_rcv_sel_isvalid(rcv_sel) \
        (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
         ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
-#endif /* TEGRA_PMX_HAS_RCV_SEL */
-#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+#endif
 
 #define _R(offset)     (u32 *)(NV_PA_APB_MISC_BASE + (offset))
 
@@ -86,7 +92,7 @@
 #define IO_RESET_SHIFT 8
 #define RCV_SEL_SHIFT  9
 
-#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
+#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
 /* This register/field only exists on Tegra114 and later */
 #define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
 #define CLAMP_INPUTS_WHEN_TRISTATED 1
@@ -180,7 +186,7 @@ void pinmux_tristate_disable(enum pmux_pingrp pin)
        pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
 }
 
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
 {
        u32 *reg = REG(pin);
@@ -200,7 +206,9 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
                val &= ~(1 << IO_SHIFT);
        writel(val, reg);
 }
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
 static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
 {
        u32 *reg = REG(pin);
@@ -225,7 +233,9 @@ static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
 
        return;
 }
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_OD
 static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
 {
        u32 *reg = REG(pin);
@@ -247,7 +257,9 @@ static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
 
        return;
 }
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
 static void pinmux_set_ioreset(enum pmux_pingrp pin,
                                enum pmux_pin_ioreset ioreset)
 {
@@ -270,8 +282,9 @@ static void pinmux_set_ioreset(enum pmux_pingrp pin,
 
        return;
 }
+#endif
 
-#ifdef TEGRA_PMX_HAS_RCV_SEL
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
 static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
                                enum pmux_pin_rcv_sel rcv_sel)
 {
@@ -294,8 +307,7 @@ static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
 
        return;
 }
-#endif /* TEGRA_PMX_HAS_RCV_SEL */
-#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+#endif
 
 static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
 {
@@ -304,14 +316,20 @@ static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
        pinmux_set_func(pin, config->func);
        pinmux_set_pullupdown(pin, config->pull);
        pinmux_set_tristate(pin, config->tristate);
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
        pinmux_set_io(pin, config->io);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
        pinmux_set_lock(pin, config->lock);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_OD
        pinmux_set_od(pin, config->od);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
        pinmux_set_ioreset(pin, config->ioreset);
-#ifdef TEGRA_PMX_HAS_RCV_SEL
-       pinmux_set_rcv_sel(pin, config->rcv_sel);
 #endif
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
+       pinmux_set_rcv_sel(pin, config->rcv_sel);
 #endif
 }
 
@@ -324,7 +342,7 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
                pinmux_config_pingrp(&config[i]);
 }
 
-#ifdef TEGRA_PMX_HAS_DRVGRPS
+#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
 
 #define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))