arm: auto gen asm-offsets.h for mb86r0x

auto gen asm-offsets.h for mb86r0x

Signed-off-by: Matthias Weisser <weisserm@arcor.de>

diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
index bab048bfd5f0b6cc66d94bf9b3001c15fc9158d8..974d0be0bc2b97b4d3f83b15303bebe87fa8e5d4 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
+++ b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
@@ -37,6 +37,8 @@ all:  $(obj).depend $(LIB)
 $(LIB):        $(OBJS)
        $(call cmd_link_o_target, $(OBJS))
 
+$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h
+
 #########################################################################
 
 # defines $(obj).depend target

diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c b/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c
new file mode 100644 (file)
index 0000000..6f9c722
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c
@@ -0,0 +1,65 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/mb86r0x.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+       /* ddr2 controller */
+       DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
+       DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
+       DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
+       DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
+       DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
+       DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
+       DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
+       DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
+       DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
+       DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
+       DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
+       DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
+       DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
+       DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
+       DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
+
+       /* clock reset generator */
+       DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
+       DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
+       DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
+       DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
+       DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
+       DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
+
+       /* chip control module */
+       DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
+
+       /* external bus interface */
+       DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
+       DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
+       DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
+       DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
+       DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
+       DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
+       DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
+       DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
+       DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
+
+       return 0;
+}

diff --git a/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h b/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h
deleted file mode 100644 (file)
index 0bc5279..0000000
--- a/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef ASM_OFFSETS_H
-#define ASM_OFFSETS_H
-
-/*
- * Offset definitions for DDR controller
- */
-#define DDR2_DRIC              0x00
-#define DDR2_DRIC1             0x02
-#define DDR2_DRIC2             0x04
-#define DDR2_DRCA              0x06
-#define DDR2_DRCM              0x08
-#define DDR2_DRCST1            0x0a
-#define DDR2_DRCST2            0x0c
-#define DDR2_DRCR              0x0e
-#define DDR2_DRCF              0x20
-#define DDR2_DRASR             0x30
-#define DDR2_DRIMS             0x50
-#define DDR2_DROS              0x60
-#define DDR2_DRIBSODT1         0x64
-#define DDR2_DROABA            0x70
-#define DDR2_DROBS             0x84
-
-/*
- * Offset definitions Chip Control Module
- */
-#define CCNT_CDCRC             0xec
-
-/*
- * Offset definitions clock reset generator
- */
-#define CRG_CRPR               0x00
-#define CRG_CRHA               0x18
-#define CRG_CRPA               0x1c
-#define CRG_CRPB               0x20
-#define CRG_CRHB               0x24
-#define CRG_CRAM               0x28
-
-/*
- * Offset definitions External bus interface
- */
-#define MEMC_MCFMODE0          0x00
-#define MEMC_MCFMODE2          0x08
-#define MEMC_MCFMODE4          0x10
-#define MEMC_MCFTIM0           0x20
-#define MEMC_MCFTIM2           0x28
-#define MEMC_MCFTIM4           0x30
-#define MEMC_MCFAREA0          0x40
-#define MEMC_MCFAREA2          0x48
-#define MEMC_MCFAREA4          0x50
-
-#endif /* ASM_OFFSETS_H */

diff --git a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
index 36a28b7af331008083821e40ea1875b42ccf6a4d..cb9eee546206be612fc3881bc315361d4f4ae96c 100644 (file)
--- a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
+++ b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
@@ -498,6 +498,48 @@ struct mb86r0x_gdc {
        uint32_t pad08[7*1024];
 };
 
+/* mb86r0x ddr2c */
+struct mb86r0x_ddr2c {
+       uint16_t dric;
+       uint16_t dric1;
+       uint16_t dric2;
+       uint16_t drca;
+       uint16_t drcm;
+       uint16_t drcst1;
+       uint16_t drcst2;
+       uint16_t drcr;
+       uint16_t pad00[8];
+       uint16_t drcf;
+       uint16_t pad01[7];
+       uint16_t drasr;
+       uint16_t pad02[15];
+       uint16_t drims;
+       uint16_t pad03[7];
+       uint16_t dros;
+       uint16_t pad04;
+       uint16_t dribsodt1;
+       uint16_t dribsocd;
+       uint16_t dribsocd2;
+       uint16_t pad05[3];
+       uint16_t droaba;
+       uint16_t pad06[9];
+       uint16_t drobs;
+       uint16_t pad07[5];
+       uint16_t drimr1;
+       uint16_t drimr2;
+       uint16_t drimr3;
+       uint16_t drimr4;
+       uint16_t droisr1;
+       uint16_t droisr2;
+};
+
+/* mb86r0x memc */
+struct mb86r0x_memc {
+       uint32_t mcfmode[8];
+       uint32_t mcftim[8];
+       uint32_t mcfarea[8];
+};
+
 #endif /* __ASSEMBLY__ */
 
 /*