x86: turn off cache: set control register properly

Bits should be ORed when they are supposed to be added together

Signed-off-by: Ondrej Kupka <ondra.cap@gmail.com>

diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S
index 3d3017a0eb963c32ba29d164fcd1188cb247b994..9dabff2b9f3309f2253ead84d28130f7a28066f0 100644 (file)
--- a/arch/x86/cpu/start16.S
+++ b/arch/x86/cpu/start16.S
@@ -50,7 +50,7 @@ board_init16_ret:
 
        /* Turn of cache (this might require a 486-class CPU) */
        movl    %cr0, %eax
-       orl     $(X86_CR0_NW & X86_CR0_CD), %eax
+       orl     $(X86_CR0_NW | X86_CR0_CD), %eax
        movl    %eax, %cr0
        wbinvd