ARM: dts: uniphier: add PH1-LD20 SoC/board device tree sources

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 578038be21f99a8bc67923b8c01902be2922f317..f2ea60f941224a52a92de5612e3c779c06a8b5ca 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -57,6 +57,7 @@ dtb-$(CONFIG_ARCH_MVEBU) +=                   \
        armada-xp-theadorable.dtb
 
 dtb-$(CONFIG_ARCH_UNIPHIER) += \
+       uniphier-ph1-ld20-ref.dtb \
        uniphier-ph1-ld4-ref.dtb \
        uniphier-ph1-ld6b-ref.dtb \
        uniphier-ph1-pro4-ace.dtb \

diff --git a/arch/arm/dts/uniphier-ph1-ld20-ref.dts b/arch/arm/dts/uniphier-ph1-ld20-ref.dts
new file mode 100644 (file)
index 0000000..108adeb
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-ld20-ref.dts
@@ -0,0 +1,69 @@
+/*
+ * Device Tree Source for UniPhier PH1-LD20 Reference Board
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-ld20.dtsi"
+/include/ "uniphier-support-card.dtsi"
+
+/ {
+       model = "UniPhier PH1-LD20 Reference Board";
+       compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20";
+
+       memory {
+               device_type = "memory";
+               reg = <0 0x80000000 0 0xc0000000>;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       aliases {
+               serial0 = &serial0;
+               serial1 = &serial1;
+               serial2 = &serial2;
+               serial3 = &serial3;
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               i2c2 = &i2c2;
+               i2c3 = &i2c3;
+               i2c4 = &i2c4;
+               i2c5 = &i2c5;
+       };
+};
+
+&ethsc {
+       interrupts = <0 48 4>;
+};
+
+&serial0 {
+       status = "okay";
+};
+
+&i2c0 {
+       status = "okay";
+};
+
+/* for U-Boot only */
+/ {
+       soc {
+               u-boot,dm-pre-reloc;
+       };
+};
+
+&serial0 {
+       u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+       u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+       u-boot,dm-pre-reloc;
+};

diff --git a/arch/arm/dts/uniphier-ph1-ld20.dtsi b/arch/arm/dts/uniphier-ph1-ld20.dtsi
new file mode 100644 (file)
index 0000000..1bb45be
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-ld20.dtsi
@@ -0,0 +1,241 @@
+/*
+ * Device Tree Source for UniPhier PH1-LD20 SoC
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        X11
+ */
+
+/ {
+       compatible = "socionext,ph1-ld20";
+       #address-cells = <2>;
+       #size-cells = <2>;
+       interrupt-parent = <&gic>;
+
+       cpus {
+               #address-cells = <2>;
+               #size-cells = <0>;
+
+               cpu-map {
+                       cluster0 {
+                               core0 {
+                                       cpu = <&cpu0>;
+                               };
+                               core1 {
+                                       cpu = <&cpu1>;
+                               };
+                       };
+
+                       cluster1 {
+                               core0 {
+                                       cpu = <&cpu2>;
+                               };
+                               core1 {
+                                       cpu = <&cpu3>;
+                               };
+                       };
+               };
+
+               cpu0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a72", "arm,armv8";
+                       reg = <0 0x000>;
+                       enable-method = "spin-table";
+                       cpu-release-addr = <0 0x80000100>;
+               };
+
+               cpu1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a72", "arm,armv8";
+                       reg = <0 0x001>;
+                       enable-method = "spin-table";
+                       cpu-release-addr = <0 0x80000100>;
+               };
+
+               cpu2: cpu@100 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0 0x100>;
+                       enable-method = "spin-table";
+                       cpu-release-addr = <0 0x80000100>;
+               };
+
+               cpu3: cpu@101 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0 0x101>;
+                       enable-method = "spin-table";
+                       cpu-release-addr = <0 0x80000100>;
+               };
+       };
+
+       clocks {
+               uart_clk: uart_clk {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <58820000>;
+               };
+
+               i2c_clk: i2c_clk {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <50000000>;
+               };
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts = <1 13 0xf01>,
+                            <1 14 0xf01>,
+                            <1 11 0xf01>,
+                            <1 10 0xf01>;
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0 0 0xffffffff>;
+
+               serial0: serial@54006800 {
+                       compatible = "socionext,uniphier-uart";
+                       status = "disabled";
+                       reg = <0x54006800 0x40>;
+                       interrupts = <0 33 4>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_uart0>;
+                       clocks = <&uart_clk>;
+               };
+
+               serial1: serial@54006900 {
+                       compatible = "socionext,uniphier-uart";
+                       status = "disabled";
+                       reg = <0x54006900 0x40>;
+                       interrupts = <0 35 4>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_uart1>;
+                       clocks = <&uart_clk>;
+               };
+
+               serial2: serial@54006a00 {
+                       compatible = "socionext,uniphier-uart";
+                       status = "disabled";
+                       reg = <0x54006a00 0x40>;
+                       interrupts = <0 37 4>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_uart2>;
+                       clocks = <&uart_clk>;
+               };
+
+               serial3: serial@54006b00 {
+                       compatible = "socionext,uniphier-uart";
+                       status = "disabled";
+                       reg = <0x54006b00 0x40>;
+                       interrupts = <0 177 4>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_uart3>;
+                       clocks = <&uart_clk>;
+               };
+
+               i2c0: i2c@58780000 {
+                       compatible = "socionext,uniphier-fi2c";
+                       status = "disabled";
+                       reg = <0x58780000 0x80>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <0 41 4>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_i2c0>;
+                       clocks = <&i2c_clk>;
+                       clock-frequency = <100000>;
+               };
+
+               i2c1: i2c@58781000 {
+                       compatible = "socionext,uniphier-fi2c";
+                       status = "disabled";
+                       reg = <0x58781000 0x80>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <0 42 4>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_i2c1>;
+                       clocks = <&i2c_clk>;
+                       clock-frequency = <100000>;
+               };
+
+               i2c2: i2c@58782000 {
+                       compatible = "socionext,uniphier-fi2c";
+                       reg = <0x58782000 0x80>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <0 43 4>;
+                       clocks = <&i2c_clk>;
+                       clock-frequency = <400000>;
+               };
+
+               i2c3: i2c@58783000 {
+                       compatible = "socionext,uniphier-fi2c";
+                       status = "disabled";
+                       reg = <0x58783000 0x80>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <0 44 4>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_i2c3>;
+                       clocks = <&i2c_clk>;
+                       clock-frequency = <100000>;
+               };
+
+               i2c4: i2c@58784000 {
+                       compatible = "socionext,uniphier-fi2c";
+                       status = "disabled";
+                       reg = <0x58784000 0x80>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <0 45 4>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_i2c4>;
+                       clocks = <&i2c_clk>;
+                       clock-frequency = <100000>;
+               };
+
+               i2c5: i2c@58785000 {
+                       compatible = "socionext,uniphier-fi2c";
+                       reg = <0x58785000 0x80>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <0 25 4>;
+                       clocks = <&i2c_clk>;
+                       clock-frequency = <400000>;
+               };
+
+               system_bus: system-bus@58c00000 {
+                       compatible = "socionext,uniphier-system-bus";
+                       status = "disabled";
+                       reg = <0x58c00000 0x400>;
+                       #address-cells = <2>;
+                       #size-cells = <1>;
+               };
+
+               smpctrl@59800000 {
+                       compatible = "socionext,uniphier-smpctrl";
+                       reg = <0x59801000 0x400>;
+               };
+
+               pinctrl: pinctrl@5f801000 {
+                       compatible = "socionext,ph1-ld20-pinctrl", "syscon";
+                       reg = <0x5f801000 0xe00>;
+               };
+
+               gic: interrupt-controller@5fe00000 {
+                       compatible = "arm,gic-v3";
+                       reg = <0x5fe00000 0x10000>,     /* GICD */
+                             <0x5fe80000 0x80000>;     /* GICR */
+                       interrupt-controller;
+                       #interrupt-cells = <3>;
+                       interrupts = <1 9 4>;
+               };
+       };
+};
+
+/include/ "uniphier-pinctrl.dtsi"

diff --git a/arch/arm/dts/uniphier-pinctrl.dtsi b/arch/arm/dts/uniphier-pinctrl.dtsi
index 494139a05d7718a9d6078d45a5c3f2711cfc389e..988e60a98cf71a525ba37dcf91cc10006bd4cd93 100644 (file)
--- a/arch/arm/dts/uniphier-pinctrl.dtsi
+++ b/arch/arm/dts/uniphier-pinctrl.dtsi
@@ -37,6 +37,11 @@
                function = "i2c3";
        };
 
+       pinctrl_i2c4: i2c4_grp {
+               groups = "i2c4";
+               function = "i2c4";
+       };
+
        pinctrl_sd: sd_grp {
                groups = "sd";
                function = "sd";