x86: baytrail: Add GPIO ASL description

Since BayTrail, Intel starts to use new GPIO IPs in their chipset.
This adds the GPIO ASL, so that OS can load corresponding drivers
for it. On Linux, this is BayTrail pinctrl driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl
new file mode 100644 (file)
index 0000000..ef340f3
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/gpio.asl
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/* SouthCluster GPIO */
+Device (GPSC)
+{
+       Name(_HID, "INT33FC")
+       Name(_CID, "INT33FC")
+       Name(_UID, 1)
+
+       Name(RBUF, ResourceTemplate()
+       {
+               Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+               Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+               {
+                       GPIO_SC_IRQ
+               }
+       })
+
+       Method(_CRS)
+       {
+               CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+               Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
+               Return (^RBUF)
+       }
+
+       Method(_STA)
+       {
+               Return (STA_VISIBLE)
+       }
+}
+
+/* NorthCluster GPIO */
+Device (GPNC)
+{
+       Name(_HID, "INT33FC")
+       Name(_CID, "INT33FC")
+       Name(_UID, 2)
+
+       Name(RBUF, ResourceTemplate()
+       {
+               Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+               Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+               {
+                       GPIO_NC_IRQ
+               }
+       })
+
+       Method(_CRS)
+       {
+               CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+               Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
+               Return (^RBUF)
+       }
+
+       Method(_STA)
+       {
+               Return (STA_VISIBLE)
+       }
+}
+
+/* SUS GPIO */
+Device (GPSS)
+{
+       Name(_HID, "INT33FC")
+       Name(_CID, "INT33FC")
+       Name(_UID, 3)
+
+       Name(RBUF, ResourceTemplate()
+       {
+               Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+               Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+               {
+                       GPIO_SUS_IRQ
+               }
+       })
+
+       Method(_CRS)
+       {
+               CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+               Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)
+               Return (^RBUF)
+       }
+
+       Method(_STA)
+       {
+               Return (STA_VISIBLE)
+       }
+}

diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
index bd72842dd6b3eb7d10809f67bca6e6aaee21d7c5..6bc82ecfe1932c78ca42bfa4b0dc623c3b8fb86e 100644 (file)
--- a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
@@ -27,6 +27,9 @@ Method(_WAK, 1)
 Scope (\_SB)
 {
        #include "southcluster.asl"
+
+       /* ACPI devices */
+       #include "gpio.asl"
 }
 
 /* Chipset specific sleep states */