]> git.sur5r.net Git - u-boot/commitdiff
SPEAr: explicitly select clk src for UART
authorShiraz Hashim <shiraz.hashim@st.com>
Mon, 7 May 2012 07:36:59 +0000 (13:06 +0530)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sat, 7 Jul 2012 12:07:42 +0000 (14:07 +0200)
UART in u-boot intends to run on 48MHz clock supplied by USB PLL.
Explicitly select the intended clock source.

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
arch/arm/cpu/arm926ejs/spear/cpu.c
arch/arm/include/asm/arch-spear/spr_misc.h

index 9e074bc9eb558630f2e2c02363da0974268345db..e299de3137af4ac5b0a4e452f5c75630e28f6319 100644 (file)
@@ -30,7 +30,7 @@ int arch_cpu_init(void)
 {
        struct misc_regs *const misc_p =
            (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-       u32 periph1_clken;
+       u32 periph1_clken, periph_clk_cfg;
 
        periph1_clken = readl(&misc_p->periph1_clken);
 
@@ -42,6 +42,11 @@ int arch_cpu_init(void)
 
 #if defined(CONFIG_PL011_SERIAL)
        periph1_clken |= MISC_UART0ENB;
+
+       periph_clk_cfg = readl(&misc_p->periph_clk_cfg);
+       periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK;
+       periph_clk_cfg |= CONFIG_SPEAR_UART48M;
+       writel(periph_clk_cfg, &misc_p->periph_clk_cfg);
 #endif
 #if defined(CONFIG_DESIGNWARE_ETH)
        periph1_clken |= MISC_ETHENB;
index b10c72607a5b8aac410acdadac5b003c16454e90..384944d33e3c3ae1390550a4b2c3d7cfcae3f7bb 100644 (file)
@@ -110,6 +110,8 @@ struct misc_regs {
 /* PERIPH_CLK_CFG value */
 #define MISC_GPT3SYNTH                 0x00000400
 #define MISC_GPT4SYNTH                 0x00000800
+#define CONFIG_SPEAR_UART48M           0
+#define CONFIG_SPEAR_UARTCLKMSK                (0x1 << 4)
 
 /* PRSC_CLK_CFG value */
 /*