]> git.sur5r.net Git - u-boot/commitdiff
imx: iomux-v3: Include PKE and PUE to pad control pull definitions
authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Fri, 26 Apr 2013 01:34:47 +0000 (01:34 +0000)
committerStefano Babic <sbabic@denx.de>
Sun, 28 Apr 2013 09:15:07 +0000 (11:15 +0200)
PUE requires PKE to mean something, as do pull values with PUE, so do not
compell users to explicitly use PKE and PUE everywhere. This is also what is
done on Linux and what has already been done for i.MX51.

By the way, remove some unused pad control definitions.

There is no change of behavior.

Note that SPI_PAD_CTRL was defined by several boards with a pull value, but
without PKE or PUE, which means that no pull was actually enabled in the pad.
This might be a bug in those boards, but this patch does not change the
behavior, so it just removes the meaningless pull value from those definitions.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
arch/arm/include/asm/arch-mx5/iomux-mx51.h
arch/arm/include/asm/imx-common/iomux-v3.h
board/boundary/nitrogen6x/nitrogen6x.c
board/freescale/mx6qarm2/mx6qarm2.c
board/freescale/mx6qsabreauto/mx6qsabreauto.c
board/freescale/mx6qsabrelite/mx6qsabrelite.c
board/freescale/mx6qsabresd/mx6qsabresd.c
board/freescale/mx6slevk/mx6slevk.c
board/freescale/titanium/titanium.c
board/wandboard/wandboard.c

index 5f96dc499e4bf27e1e8f3817983c0957f8a41c29..328c1880ed9451a6363f6e663758788d278819eb 100644 (file)
@@ -22,7 +22,7 @@
 #include <asm/imx-common/iomux-v3.h>
 
 /* Pad control groupings */
-#define MX51_UART_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
+#define MX51_UART_PAD_CTRL     (PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
                                PAD_CTL_HYS | PAD_CTL_SRE_FAST)
 #define MX51_I2C_PAD_CTRL      (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
                                PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
 #define MX51_ESDHC_PAD_CTRL    (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
                                PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
                                PAD_CTL_HYS)
-#define MX51_USBH1_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
-                               PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
-                               PAD_CTL_HYS | PAD_CTL_PUE)
+#define MX51_USBH1_PAD_CTRL    (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+                               PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
 #define MX51_ECSPI_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_HYS | \
                                PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
-#define MX51_SDHCI_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
-                               PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
+#define MX51_SDHCI_PAD_CTRL    (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
                                PAD_CTL_SRE_FAST | PAD_CTL_DVS)
 #define MX51_GPIO_PAD_CTRL     (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
 
index 2ba0a053de4a4627be2b98646372eef1ddcee12b..0b4e76333e456159599f656afed7c1c91c36b2d3 100644 (file)
@@ -99,11 +99,11 @@ typedef u64 iomux_v3_cfg_t;
 
 #define PAD_CTL_HYS            (1 << 16)
 
-#define PAD_CTL_PUS_100K_DOWN  (0 << 14)
-#define PAD_CTL_PUS_47K_UP     (1 << 14)
-#define PAD_CTL_PUS_100K_UP    (2 << 14)
-#define PAD_CTL_PUS_22K_UP     (3 << 14)
-#define PAD_CTL_PUE            (1 << 13)
+#define PAD_CTL_PUS_100K_DOWN  (0 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP     (1 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP    (2 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP     (3 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUE            (1 << 13 | PAD_CTL_PKE)
 #define PAD_CTL_PKE            (1 << 12)
 
 #define PAD_CTL_ODE            (1 << 11)
index cc071d6d38c3ea9b9656fd800307b886f8404b6c..e155556ce2d38d35f32e7bc4fd96a71e6341c0ab 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |           \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |              \
-       PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |           \
-       PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |              \
-       PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                   \
+       PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
-       PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
-#define SPI_PAD_CTRL (PAD_CTL_HYS |                            \
-       PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |                \
        PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
 
-#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |           \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
-       PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                 \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
-#define I2C_PAD_CTRL   (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
-       PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
+#define I2C_PAD_CTRL   (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
        PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 
-#define WEAK_PULLUP    (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
-       PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
+#define WEAK_PULLUP    (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
        PAD_CTL_SRE_SLOW)
 
-#define WEAK_PULLDOWN  (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
-       PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
-       PAD_CTL_SRE_SLOW)
+#define WEAK_PULLDOWN  (PAD_CTL_PUS_100K_DOWN |                \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
+       PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 
 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
 
index ff7f5e83a0fde9a8339f267741f1b08f2282cae2..e33674665f865b0ea380a6c9b04c58b2fe96bff4 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
-       PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
-       PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                   \
+       PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
-       PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
 int dram_init(void)
 {
index a3afa58ae2a0f568046cdb155a2ed7ba599584fc..bfe4868e8a856da8144d808683dc23437ec84ebf 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
-       PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
-       PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                   \
+       PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
-       PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
 int dram_init(void)
 {
index 9f9cac82c423295c6c1baf3610106fb3f7e52b77..8ce054e42840a4a10a71a14c1df14387f1d3f771 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |           \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |              \
-       PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |           \
-       PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |              \
-       PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                   \
+       PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
-       PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
-#define SPI_PAD_CTRL (PAD_CTL_HYS |                            \
-       PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |                \
        PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
 
-#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |           \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
-       PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                 \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
-#define I2C_PAD_CTRL   (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
-       PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
+#define I2C_PAD_CTRL   (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
        PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 
 int dram_init(void)
index bf9beef014720614c041508231f0906210bee96f..25298261455ed69f4a7a79f02d005b0e1c723077 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
-       PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
-       PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                   \
+       PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
-       PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
 int dram_init(void)
 {
index fc6353e0fc49b4d1a68e071d963e56730160923a..69fe8fc0e42777bd4227753997913b3f5850c98e 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
-       PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
-       PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP |                   \
+       PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
 int dram_init(void)
 {
index 894ebae9d8a78797c48e92bc67a1ac63ff1c5493..5250522d9168478fbee7273d1e7a9f051f714506 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |                    \
-                       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |       \
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |      \
                        PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |                    \
-                       PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |       \
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |      \
                        PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |                    \
-                       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |     \
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED          |     \
                        PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
 
-#define SPI_PAD_CTRL (PAD_CTL_HYS |                                    \
-                     PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |       \
-                     PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
-
-#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |                   \
-                        PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |    \
-                        PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL   (PAD_CTL_PKE | PAD_CTL_PUE |                    \
-                        PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |      \
+#define I2C_PAD_CTRL   (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |      \
                         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |              \
                         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 
index c71c90d6564dc3335d36cd9ecaa231682d679e07..bb983528b9a5905addc2a4947c683548ec2b272b 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
-       PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
-       PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                   \
+       PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
-       PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
 #define USDHC1_CD_GPIO         IMX_GPIO_NR(1, 2)
 #define USDHC3_CD_GPIO         IMX_GPIO_NR(3, 9)