/mips Files generic to MIPS architecture
/cpu CPU specific files
/mips32 Files specific to MIPS32 CPUs
- /xburst Files specific to Ingenic XBurst CPUs
/lib Architecture specific library files
/nds32 Files generic to NDS32 architecture
/cpu CPU specific files
+++ /dev/null
-#
-# Copyright (C) 2011 Xiangfu Liu <xiangfu@openmobilefree.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-extra-y = start.o
-obj-y = cpu.o timer.o jz_serial.o
-obj-$(CONFIG_JZ4740) += jz4740.o
+++ /dev/null
-#
-# Copyright (C) 2011 Xiangfu Liu <xiangfu@openmobilefree.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=mips32
-PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
-ifdef CONFIG_SYS_BIG_ENDIAN
-PLATFORM_LDFLAGS += -m elf32btsmip
-else
-PLATFORM_LDFLAGS += -m elf32ltsmip
-endif
-
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \
- -T $(srctree)/examples/standalone/mips.lds
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- * (C) Copyright 2011
- * Xiangfu Liu <xiangfu@openmobilefree.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/mipsregs.h>
-#include <asm/cacheops.h>
-#include <asm/reboot.h>
-#include <asm/io.h>
-#include <asm/jz4740.h>
-
-#define cache_op(op, addr) \
- __asm__ __volatile__( \
- ".set push\n" \
- ".set noreorder\n" \
- ".set mips3\n" \
- "cache %0, %1\n" \
- ".set pop\n" \
- : \
- : "i" (op), "R" (*(unsigned char *)(addr)))
-
-void __attribute__((weak)) _machine_restart(void)
-{
- struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
- struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
- u16 tmp;
-
- /* wdt_select_extalclk() */
- tmp = readw(&wdt->tcsr);
- tmp &= ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN);
- tmp |= WDT_TCSR_EXT_EN;
- writew(tmp, &wdt->tcsr);
-
- /* wdt_select_clk_div64() */
- tmp = readw(&wdt->tcsr);
- tmp &= ~WDT_TCSR_PRESCALE_MASK;
- tmp |= WDT_TCSR_PRESCALE64,
- writew(tmp, &wdt->tcsr);
-
- writew(100, &wdt->tdr); /* wdt_set_data(100) */
- writew(0, &wdt->tcnt); /* wdt_set_count(0); */
- writel(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */
- writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */
-
- while (1)
- ;
-}
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- _machine_restart();
-
- fprintf(stderr, "*** reset failed ***\n");
- return 0;
-}
-
-void flush_cache(ulong start_addr, ulong size)
-{
- unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
- unsigned long addr = start_addr & ~(lsize - 1);
- unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
-
- for (; addr <= aend; addr += lsize) {
- cache_op(HIT_WRITEBACK_INV_D, addr);
- cache_op(HIT_INVALIDATE_I, addr);
- }
-}
-
-void flush_dcache_range(ulong start_addr, ulong stop)
-{
- unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
- unsigned long addr = start_addr & ~(lsize - 1);
- unsigned long aend = (stop - 1) & ~(lsize - 1);
-
- for (; addr <= aend; addr += lsize)
- cache_op(HIT_WRITEBACK_INV_D, addr);
-}
-
-void invalidate_dcache_range(ulong start_addr, ulong stop)
-{
- unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
- unsigned long addr = start_addr & ~(lsize - 1);
- unsigned long aend = (stop - 1) & ~(lsize - 1);
-
- for (; addr <= aend; addr += lsize)
- cache_op(HIT_INVALIDATE_D, addr);
-}
-
-void flush_icache_all(void)
-{
- u32 addr, t = 0;
-
- __asm__ __volatile__("mtc0 $0, $28"); /* Clear Taglo */
- __asm__ __volatile__("mtc0 $0, $29"); /* Clear TagHi */
-
- for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
- addr += CONFIG_SYS_CACHELINE_SIZE) {
- cache_op(INDEX_STORE_TAG_I, addr);
- }
-
- /* invalidate btb */
- __asm__ __volatile__(
- ".set mips32\n\t"
- "mfc0 %0, $16, 7\n\t"
- "nop\n\t"
- "ori %0,2\n\t"
- "mtc0 %0, $16, 7\n\t"
- ".set mips2\n\t"
- :
- : "r" (t));
-}
-
-void flush_dcache_all(void)
-{
- u32 addr;
-
- for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
- addr += CONFIG_SYS_CACHELINE_SIZE) {
- cache_op(INDEX_WRITEBACK_INV_D, addr);
- }
-
- __asm__ __volatile__("sync");
-}
-
-void flush_cache_all(void)
-{
- flush_dcache_all();
- flush_icache_all();
-}
+++ /dev/null
-/*
- * Jz4740 common routines
- * Copyright (c) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/jz4740.h>
-
-void enable_interrupts(void)
-{
-}
-
-int disable_interrupts(void)
-{
- return 0;
-}
-
-/*
- * PLL output clock = EXTAL * NF / (NR * NO)
- * NF = FD + 2, NR = RD + 2
- * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
- */
-void pll_init(void)
-{
- struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
-
- register unsigned int cfcr, plcr1;
- int n2FR[33] = {
- 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
- 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
- 9
- };
- int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
- int nf, pllout2;
-
- cfcr = CPM_CPCCR_CLKOEN |
- CPM_CPCCR_PCS |
- (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
- (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
- (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
- (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
- (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
-
- pllout2 = (cfcr & CPM_CPCCR_PCS) ?
- CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
-
- /* Init USB Host clock, pllout2 must be n*48MHz */
- writel(pllout2 / 48000000 - 1, &cpm->uhccdr);
-
- nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
- plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
- (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
- (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
- (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
- CPM_CPPCR_PLLEN; /* enable PLL */
-
- /* init PLL */
- writel(cfcr, &cpm->cpccr);
- writel(plcr1, &cpm->cppcr);
-}
-
-void sdram_init(void)
-{
- struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
-
- register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
-
- unsigned int cas_latency_sdmr[2] = {
- EMC_SDMR_CAS_2,
- EMC_SDMR_CAS_3,
- };
-
- unsigned int cas_latency_dmcr[2] = {
- 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
- 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
- };
-
- int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
-
- cpu_clk = CONFIG_SYS_CPU_SPEED;
- mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
-
- writel(0, &emc->bcr); /* Disable bus release */
- writew(0, &emc->rtcsr); /* Disable clock for counting */
-
- /* Fault DMCR value for mode register setting*/
-#define SDRAM_ROW0 11
-#define SDRAM_COL0 8
-#define SDRAM_BANK40 0
-
- dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) |
- ((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) |
- (SDRAM_BANK40 << EMC_DMCR_BA_BIT) |
- (SDRAM_BW16 << EMC_DMCR_BW_BIT) |
- EMC_DMCR_EPIN |
- cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
-
- /* Basic DMCR value */
- dmcr = ((SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) |
- ((SDRAM_COL - 8) << EMC_DMCR_CA_BIT) |
- (SDRAM_BANK4 << EMC_DMCR_BA_BIT) |
- (SDRAM_BW16 << EMC_DMCR_BW_BIT) |
- EMC_DMCR_EPIN |
- cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
-
- /* SDRAM timimg */
- ns = 1000000000 / mem_clk;
- tmp = SDRAM_TRAS / ns;
- if (tmp < 4)
- tmp = 4;
- if (tmp > 11)
- tmp = 11;
- dmcr |= (tmp - 4) << EMC_DMCR_TRAS_BIT;
- tmp = SDRAM_RCD / ns;
-
- if (tmp > 3)
- tmp = 3;
- dmcr |= tmp << EMC_DMCR_RCD_BIT;
- tmp = SDRAM_TPC / ns;
-
- if (tmp > 7)
- tmp = 7;
- dmcr |= tmp << EMC_DMCR_TPC_BIT;
- tmp = SDRAM_TRWL / ns;
-
- if (tmp > 3)
- tmp = 3;
- dmcr |= tmp << EMC_DMCR_TRWL_BIT;
- tmp = (SDRAM_TRAS + SDRAM_TPC) / ns;
-
- if (tmp > 14)
- tmp = 14;
- dmcr |= ((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT;
-
- /* SDRAM mode value */
- sdmode = EMC_SDMR_BT_SEQ |
- EMC_SDMR_OM_NORMAL |
- EMC_SDMR_BL_4 |
- cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
-
- /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
- writel(dmcr, &emc->dmcr);
- writeb(0, JZ4740_EMC_SDMR0 | sdmode);
-
- /* Wait for precharge, > 200us */
- tmp = (cpu_clk / 1000000) * 1000;
- while (tmp--)
- ;
-
- /* Stage 2. Enable auto-refresh */
- writel(dmcr | EMC_DMCR_RFSH, &emc->dmcr);
-
- tmp = SDRAM_TREF / ns;
- tmp = tmp / 64 + 1;
- if (tmp > 0xff)
- tmp = 0xff;
- writew(tmp, &emc->rtcor);
- writew(0, &emc->rtcnt);
- /* Divisor is 64, CKO/64 */
- writew(EMC_RTCSR_CKS_64, &emc->rtcsr);
-
- /* Wait for number of auto-refresh cycles */
- tmp = (cpu_clk / 1000000) * 1000;
- while (tmp--)
- ;
-
- /* Stage 3. Mode Register Set */
- writel(dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
- writeb(0, JZ4740_EMC_SDMR0 | sdmode);
-
- /* Set back to basic DMCR value */
- writel(dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
-
- /* everything is ok now */
-}
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void calc_clocks(void)
-{
- unsigned int pllout;
- unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
-
- pllout = __cpm_get_pllout();
-
- gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
- gd->arch.sys_clk = pllout / div[__cpm_get_hdiv()];
- gd->arch.per_clk = pllout / div[__cpm_get_pdiv()];
- gd->mem_clk = pllout / div[__cpm_get_mdiv()];
- gd->arch.dev_clk = CONFIG_SYS_EXTAL;
-}
-
-void rtc_init(void)
-{
- struct jz4740_rtc *rtc = (struct jz4740_rtc *)JZ4740_RTC_BASE;
-
- while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
- ;
- writel(readl(&rtc->rcr) | RTC_RCR_AE, &rtc->rcr); /* enable alarm */
-
- while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
- ;
- writel(0x00007fff, &rtc->rgr); /* type value */
-
- while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
- ;
- writel(0x0000ffe0, &rtc->hwfcr); /* Power on delay 2s */
-
- while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
- ;
- writel(0x00000fe0, &rtc->hrcr); /* reset delay 125ms */
-}
-
-/* U-Boot common routines */
-phys_size_t initdram(int board_type)
-{
- struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
- u32 dmcr;
- u32 rows, cols, dw, banks;
- ulong size;
-
- dmcr = readl(&emc->dmcr);
- rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
- cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
- dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
- banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
-
- size = (1 << (rows + cols)) * dw * banks;
-
- return size;
-}
+++ /dev/null
-/*
- * Jz4740 UART support
- * Copyright (c) 2011
- * Qi Hardware, Xiangfu Liu <xiangfu@sharism.cc>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/jz4740.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-/*
- * serial_init - initialize a channel
- *
- * This routine initializes the number of data bits, parity
- * and set the selected baud rate. Interrupts are disabled.
- * Set the modem control signals if the option is selected.
- *
- * RETURNS: N/A
- */
-struct jz4740_uart *uart = (struct jz4740_uart *)CONFIG_SYS_UART_BASE;
-
-static int jz_serial_init(void)
-{
- /* Disable port interrupts while changing hardware */
- writeb(0, &uart->dlhr_ier);
-
- /* Disable UART unit function */
- writeb(~UART_FCR_UUE, &uart->iir_fcr);
-
- /* Set both receiver and transmitter in UART mode (not SIR) */
- writeb(~(SIRCR_RSIRE | SIRCR_TSIRE), &uart->isr);
-
- /*
- * Set databits, stopbits and parity.
- * (8-bit data, 1 stopbit, no parity)
- */
- writeb(UART_LCR_WLEN_8 | UART_LCR_STOP_1, &uart->lcr);
-
- /* Set baud rate */
- serial_setbrg();
-
- /* Enable UART unit, enable and clear FIFO */
- writeb(UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS,
- &uart->iir_fcr);
-
- return 0;
-}
-
-static void jz_serial_setbrg(void)
-{
- u32 baud_div, tmp;
-
- baud_div = CONFIG_SYS_EXTAL / 16 / CONFIG_BAUDRATE;
-
- tmp = readb(&uart->lcr);
- tmp |= UART_LCR_DLAB;
- writeb(tmp, &uart->lcr);
-
- writeb((baud_div >> 8) & 0xff, &uart->dlhr_ier);
- writeb(baud_div & 0xff, &uart->rbr_thr_dllr);
-
- tmp &= ~UART_LCR_DLAB;
- writeb(tmp, &uart->lcr);
-}
-
-static int jz_serial_tstc(void)
-{
- if (readb(&uart->lsr) & UART_LSR_DR)
- return 1;
-
- return 0;
-}
-
-static void jz_serial_putc(const char c)
-{
- if (c == '\n')
- serial_putc('\r');
-
- /* Wait for fifo to shift out some bytes */
- while (!((readb(&uart->lsr) & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60))
- ;
-
- writeb((u8)c, &uart->rbr_thr_dllr);
-}
-
-static int jz_serial_getc(void)
-{
- while (!serial_tstc())
- ;
-
- return readb(&uart->rbr_thr_dllr);
-}
-
-static struct serial_device jz_serial_drv = {
- .name = "jz_serial",
- .start = jz_serial_init,
- .stop = NULL,
- .setbrg = jz_serial_setbrg,
- .putc = jz_serial_putc,
- .puts = default_serial_puts,
- .getc = jz_serial_getc,
- .tstc = jz_serial_tstc,
-};
-
-void jz_serial_initialize(void)
-{
- serial_register(&jz_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &jz_serial_drv;
-}
+++ /dev/null
-/*
- * Startup Code for MIPS32 XBURST CPU-core
- *
- * Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <asm/cacheops.h>
-
- .set noreorder
-
- .globl _start
- .text
-_start:
- /* Initialize $gp */
- bal 1f
- nop
- .word _gp
-1:
- lw gp, 0(ra)
-
- /* Set up temporary stack */
- li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
-
- la t9, board_init_f
- jr t9
- nop
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * a0 = addr_sp
- * a1 = gd
- * a2 = destination address
- */
- .globl relocate_code
- .ent relocate_code
-relocate_code:
- move sp, a0 # set new stack pointer
-
- move s0, a1 # save gd in s0
- move s2, a2 # save destination address in s2
-
- li t0, CONFIG_SYS_MONITOR_BASE
- sub s1, s2, t0 # s1 <-- relocation offset
-
- la t3, in_ram
- lw t2, -12(t3) # t2 <-- __image_copy_end
- move t1, a2
-
- add gp, s1 # adjust gp
-
- /*
- * t0 = source address
- * t1 = target address
- * t2 = source end address
- */
-1:
- lw t3, 0(t0)
- sw t3, 0(t1)
- addu t0, 4
- blt t0, t2, 1b
- addu t1, 4
-
- /* If caches were enabled, we would have to flush them here. */
-
- /* flush d-cache */
- li t0, KSEG0
- addi t1, t0, CONFIG_SYS_DCACHE_SIZE
-2:
- cache INDEX_WRITEBACK_INV_D, 0(t0)
- bne t0, t1, 2b
- addi t0, CONFIG_SYS_CACHELINE_SIZE
-
- sync
-
- /* flush i-cache */
- li t0, KSEG0
- addi t1, t0, CONFIG_SYS_ICACHE_SIZE
-3:
- cache INDEX_INVALIDATE_I, 0(t0)
- bne t0, t1, 3b
- addi t0, CONFIG_SYS_CACHELINE_SIZE
-
- /* Invalidate BTB */
- mfc0 t0, CP0_CONFIG, 7
- nop
- ori t0, 2
- mtc0 t0, CP0_CONFIG, 7
- nop
-
- /* Jump to where we've relocated ourselves */
- addi t0, s2, in_ram - _start
- jr t0
- nop
-
- .word __rel_dyn_end
- .word __rel_dyn_start
- .word __image_copy_end
- .word _GLOBAL_OFFSET_TABLE_
- .word num_got_entries
-
-in_ram:
- /*
- * Now we want to update GOT.
- *
- * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
- * generated by GNU ld. Skip these reserved entries from relocation.
- */
- lw t3, -4(t0) # t3 <-- num_got_entries
- lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
- add t8, s1 # t8 now holds relocated _G_O_T_
- addi t8, t8, 8 # skipping first two entries
- li t2, 2
-1:
- lw t1, 0(t8)
- beqz t1, 2f
- add t1, s1
- sw t1, 0(t8)
-2:
- addi t2, 1
- blt t2, t3, 1b
- addi t8, 4
-
- /* Update dynamic relocations */
- lw t1, -16(t0) # t1 <-- __rel_dyn_start
- lw t2, -20(t0) # t2 <-- __rel_dyn_end
-
- b 2f # skip first reserved entry
- addi t1, 8
-
-1:
- lw t8, -4(t1) # t8 <-- relocation info
-
- li t3, 3
- bne t8, t3, 2f # skip non R_MIPS_REL32 entries
- nop
-
- lw t3, -8(t1) # t3 <-- location to fix up in FLASH
-
- lw t8, 0(t3) # t8 <-- original pointer
- add t8, s1 # t8 <-- adjusted pointer
-
- add t3, s1 # t3 <-- location to fix up in RAM
- sw t8, 0(t3)
-
-2:
- blt t1, t2, 1b
- addi t1, 8 # each rel.dyn entry is 8 bytes
-
- /*
- * Clear BSS
- *
- * GOT is now relocated. Thus __bss_start and __bss_end can be
- * accessed directly via $gp.
- */
- la t1, __bss_start # t1 <-- __bss_start
- la t2, __bss_end # t2 <-- __bss_end
-
-1:
- sw zero, 0(t1)
- blt t1, t2, 1b
- addi t1, 4
-
- move a0, s0 # a0 <-- gd
- la t9, board_init_r
- jr t9
- move a1, s2
-
- .end relocate_code
+++ /dev/null
-/*
- * Copyright (c) 2006
- * Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-
-#include <asm/jz4740.h>
-
-#define TIMER_CHAN 0
-#define TIMER_FDATA 0xffff /* Timer full data value */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
-
-void reset_timer_masked(void)
-{
- /* reset time */
- gd->arch.lastinc = readl(&tcu->tcnt0);
- gd->arch.tbl = 0;
-}
-
-ulong get_timer_masked(void)
-{
- ulong now = readl(&tcu->tcnt0);
-
- if (gd->arch.lastinc <= now)
- gd->arch.tbl += now - gd->arch.lastinc; /* normal mode */
- else {
- /* we have an overflow ... */
- gd->arch.tbl += TIMER_FDATA + now - gd->arch.lastinc;
- }
-
- gd->arch.lastinc = now;
-
- return gd->arch.tbl;
-}
-
-void udelay_masked(unsigned long usec)
-{
- ulong tmo;
- ulong endtime;
- signed long diff;
-
- /* normalize */
- if (usec >= 1000) {
- tmo = usec / 1000;
- tmo *= CONFIG_SYS_HZ;
- tmo /= 1000;
- } else {
- if (usec > 1) {
- tmo = usec * CONFIG_SYS_HZ;
- tmo /= 1000*1000;
- } else
- tmo = 1;
- }
-
- endtime = get_timer_masked() + tmo;
-
- do {
- ulong now = get_timer_masked();
- diff = endtime - now;
- } while (diff >= 0);
-}
-
-int timer_init(void)
-{
- writel(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0);
-
- writel(0, &tcu->tcnt0);
- writel(0, &tcu->tdhr0);
- writel(TIMER_FDATA, &tcu->tdfr0);
-
- /* mask irqs */
- writel((1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)), &tcu->tmsr);
- writel(1 << TIMER_CHAN, &tcu->tscr); /* enable timer clock */
- writeb(1 << TIMER_CHAN, &tcu->tesr); /* start counting up */
-
- gd->arch.lastinc = 0;
- gd->arch.tbl = 0;
-
- return 0;
-}
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
- gd->arch.tbl = t;
-}
-
-void __udelay(unsigned long usec)
-{
- ulong tmo, tmp;
-
- /* normalize */
- if (usec >= 1000) {
- tmo = usec / 1000;
- tmo *= CONFIG_SYS_HZ;
- tmo /= 1000;
- } else {
- if (usec >= 1) {
- tmo = usec * CONFIG_SYS_HZ;
- tmo /= 1000 * 1000;
- } else
- tmo = 1;
- }
-
- /* check for rollover during this delay */
- tmp = get_timer(0);
- if ((tmp + tmo) < tmp)
- reset_timer_masked(); /* timer would roll over */
- else
- tmo += tmp;
-
- while (get_timer_masked() < tmo)
- ;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On MIPS it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On MIPS it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
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