]> git.sur5r.net Git - u-boot/commitdiff
ARM: hisilicon: hikey: dts: Add pl011 additional clock binding.
authorPeter Griffin <peter.griffin@linaro.org>
Wed, 20 Apr 2016 16:14:01 +0000 (17:14 +0100)
committerTom Rini <trini@konsulko.com>
Mon, 25 Apr 2016 19:10:34 +0000 (15:10 -0400)
This is a binding which only exists in U-Boot, but is
required to get working serial in U-Boot.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
arch/arm/dts/hi6220.dtsi

index ad1f1ebcb05c9c5e5fa207774a998105628222e8..a610ccb63463ccbbb2bf58ada4edf8f1796c71c2 100644 (file)
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x0 0xf8015000 0x0 0x1000>;
                        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                       clock = <19200000>;
                        clocks = <&ao_ctrl HI6220_UART0_PCLK>,
                                 <&ao_ctrl HI6220_UART0_PCLK>;
                        clock-names = "uartclk", "apb_pclk";
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x0 0xf7111000 0x0 0x1000>;
                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                       clock = <19200000>;
                        clocks = <&sys_ctrl HI6220_UART1_PCLK>,
                                 <&sys_ctrl HI6220_UART1_PCLK>;
                        clock-names = "uartclk", "apb_pclk";
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x0 0xf7112000 0x0 0x1000>;
                        interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+                       clock = <19200000>;
                        clocks = <&sys_ctrl HI6220_UART2_PCLK>,
                                 <&sys_ctrl HI6220_UART2_PCLK>;
                        clock-names = "uartclk", "apb_pclk";
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x0 0xf7113000 0x0 0x1000>;
                        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+                       clock = <19200000>;
                        clocks = <&sys_ctrl HI6220_UART3_PCLK>,
                                 <&sys_ctrl HI6220_UART3_PCLK>;
                        clock-names = "uartclk", "apb_pclk";
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x0 0xf7114000 0x0 0x1000>;
                        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+                       clock = <19200000>;
                        clocks = <&sys_ctrl HI6220_UART4_PCLK>,
                                 <&sys_ctrl HI6220_UART4_PCLK>;
                        clock-names = "uartclk", "apb_pclk";