Changes since U-Boot 1.1.1:
======================================================================
+* Patch by Martin Krause, 27 Oct 2004:
+ - add support for "STK52xx" board (including PS/2 multiplexer)
+ - add hardware detection for TQM5200
+
* Clean up CMC PU2 flash driver
* Update MAINTAINERS file
}
@./mkconfig -a Total5200 ppc mpc5xxx total5200
+TQM5200_auto_config \
TQM5200_AA_config \
TQM5200_AB_config \
TQM5200_AC_config \
echo "... with 4 MB Flash, 128 MB SDRAM" ; \
echo "... with Graphics Controller"; \
}
+ @[ -z "$(findstring auto,$@)" ] || \
+ { echo "#define CONFIG_CS_AUTOCONF" >>include/config.h ; \
+ echo "... with automatic CS configuration" ; \
+ }
@./mkconfig -a TQM5200 ppc mpc5xxx tqm5200
#########################################################################
LIB = lib$(BOARD).a
-OBJS := $(BOARD).o flash.o
+#OBJS := $(BOARD).o flash.o
+OBJS := $(BOARD).o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
#else
#include "mt48lc16m16a2-75.h"
#endif
+#ifdef CONFIG_PS2MULT
+void ps2mult_early_init(void);
+#endif
#ifndef CFG_RAMBOOT
static void sdram_start (int hi_addr)
{
#if defined (CONFIG_TQM5200_AA)
puts ("Board: TQM5200-AA (TQ-Systems GmbH)\n");
-#endif
-#if defined (CONFIG_TQM5200_AB)
+#elif defined (CONFIG_TQM5200_AB)
puts ("Board: TQM5200-AB (TQ-Systems GmbH)\n");
-#endif
-#if defined (CONFIG_TQM5200_AC)
+#elif defined (CONFIG_TQM5200_AC)
puts ("Board: TQM5200-AC (TQ-Systems GmbH)\n");
+#elif defined (CONFIG_TQM5200)
+ puts ("Board: TQM5200 (TQ-Systems GmbH)\n");
#endif
+#if defined (CONFIG_STK52XX)
+ puts (" on a STK52XX baseboard\n");
+#endif
+
return 0;
}
return *save_addr;
}
-
#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
+
+#ifdef CONFIG_PS2MULT
+#ifdef CONFIG_BOARD_EARLY_INIT_R
+int board_early_init_r (void)
+{
+ ps2mult_early_init();
+ return (0);
+}
+#endif
+#endif /* CONFIG_PS2MULT */
+
+#if defined(CONFIG_CS_AUTOCONF)
+int last_stage_init (void)
+{
+ /*
+ * auto scan for really existing devices and re-set chip select
+ * configuration.
+ */
+ u16 save, tmp;
+ int restore;
+
+ /*
+ * Check for SRAM and SRAM size
+ */
+
+ /* save origianl SRAM content */
+ save = *(volatile u16 *)CFG_CS2_START;
+ restore = 1;
+
+ /* write test pattern to SRAM */
+ *(volatile u16 *)CFG_CS2_START = 0xA5A5;
+ __asm__ volatile ("sync");
+ /*
+ * Put a different pattern on the data lines: otherwise they may float
+ * long enough to read back what we wrote.
+ */
+ tmp = *(volatile u16 *)CFG_FLASH_BASE;
+ if (tmp == 0xA5A5)
+ puts ("!! possible error in SRAM detection\n");
+
+ if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
+ /* no SRAM at all, disable cs */
+ *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
+ *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
+ *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
+ restore = 0;
+ __asm__ volatile ("sync");
+ }
+ else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
+ /* make sure that we access a mirrored address */
+ *(volatile u16 *)CFG_CS2_START = 0x1111;
+ __asm__ volatile ("sync");
+ if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
+ /* SRAM size = 512 kByte */
+ *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
+ 0x80000);
+ __asm__ volatile ("sync");
+ puts ("SRAM: 512 kB\n");
+ }
+ else
+ puts ("!! possible error in SRAM detection\n");
+ }
+ else {
+ puts ("SRAM: 1 MB\n");
+ }
+ /* restore origianl SRAM content */
+ if (restore) {
+ *(volatile u16 *)CFG_CS2_START = save;
+ __asm__ volatile ("sync");
+ }
+
+ /*
+ * Check for Grafic Controller
+ */
+
+ /* save origianl FB content */
+ save = *(volatile u16 *)CFG_CS1_START;
+ restore = 1;
+
+ /* write test pattern to FB memory */
+ *(volatile u16 *)CFG_CS1_START = 0xA5A5;
+ __asm__ volatile ("sync");
+ /*
+ * Put a different pattern on the data lines: otherwise they may float
+ * long enough to read back what we wrote.
+ */
+ tmp = *(volatile u16 *)CFG_FLASH_BASE;
+ if (tmp == 0xA5A5)
+ puts ("!! possible error in grafic controller detection\n");
+
+ if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
+ /* no grafic controller at all, disable cs */
+ *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
+ *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
+ *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
+ restore = 0;
+ __asm__ volatile ("sync");
+ }
+ else {
+ puts ("VGA: SMI501 (Voyager) with 8 MB\n");
+ }
+ /* restore origianl FB content */
+ if (restore) {
+ *(volatile u16 *)CFG_CS1_START = save;
+ __asm__ volatile ("sync");
+ }
+
+ return 0;
+}
+#endif /* CONFIG_CS_AUTOCONF */
#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */
+#ifdef CONFIG_MPC5xxx
+int ps2ser_check(void);
+#endif
+
static volatile char kbd_buffer[KBD_BUFFER_LEN];
static volatile int in_pointer = 0;
static volatile int out_pointer = 0;
/* test if a character is in the queue */
static int kbd_testc(void)
{
+#ifdef CONFIG_MPC5xxx
+ /* no ISR is used, so received chars must be polled */
+ ps2ser_check();
+#endif
if(in_pointer==out_pointer)
return(0); /* no data */
else
static int kbd_getc(void)
{
char c;
- while(in_pointer==out_pointer);
+ while(in_pointer==out_pointer) {
+#ifdef CONFIG_MPC5xxx
+ /* no ISR is used, so received chars must be polled */
+ ps2ser_check();
+#endif
+ ;}
if((out_pointer+1)==KBD_BUFFER_LEN)
out_pointer=0;
else
#define PS2SER_BAUD 57600
+#ifdef CONFIG_MPC5xxx
+#if CONFIG_PS2SERIAL == 1
+#define PSC_BASE MPC5XXX_PSC1
+#elif CONFIG_PS2SERIAL == 2
+#define PSC_BASE MPC5XXX_PSC2
+#elif CONFIG_PS2SERIAL == 3
+#define PSC_BASE MPC5XXX_PSC3
+#elif defined(CONFIG_MGT5100)
+#error CONFIG_PS2SERIAL must be in 1, 2 or 3
+#elif CONFIG_PS2SERIAL == 4
+#define PSC_BASE MPC5XXX_PSC4
+#elif CONFIG_PS2SERIAL == 5
+#define PSC_BASE MPC5XXX_PSC5
+#elif CONFIG_PS2SERIAL == 6
+#define PSC_BASE MPC5XXX_PSC6
+#else
+#error CONFIG_PS2SERIAL must be in 1 ... 6
+#endif
+#endif /* CONFIG_MPC5xxx */
+
static int ps2ser_getc_hw(void);
static void ps2ser_interrupt(void *dev_id);
extern struct serial_state rs_table[]; /* in serial.c */
+#ifndef CONFIG_MPC5xxx
static struct serial_state *state;
+#endif
static u_char ps2buf[PS2BUF_SIZE];
static atomic_t ps2buf_cnt;
static int ps2buf_in_idx;
static int ps2buf_out_idx;
+#ifdef CONFIG_MPC5xxx
+int ps2ser_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
+ unsigned long baseclk;
+ int div;
+
+ /* reset PSC */
+ psc->command = PSC_SEL_MODE_REG_1;
+
+ /* select clock sources */
+#if defined(CONFIG_MGT5100)
+ psc->psc_clock_select = 0xdd00;
+ baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32;
+#elif defined(CONFIG_MPC5200)
+ psc->psc_clock_select = 0;
+ baseclk = (gd->ipb_clk + 16) / 32;
+#endif
+
+ /* switch to UART mode */
+ psc->sicr = 0;
+
+ /* configure parity, bit length and so on */
+#if defined(CONFIG_MGT5100)
+ psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE;
+#elif defined(CONFIG_MPC5200)
+ psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
+#endif
+ psc->mode = PSC_MODE_ONE_STOP;
+
+ /* set up UART divisor */
+ div = (baseclk + (PS2SER_BAUD/2)) / PS2SER_BAUD;
+ psc->ctur = (div >> 8) & 0xff;
+ psc->ctlr = div & 0xff;
+
+ /* disable all interrupts */
+ psc->psc_imr = 0;
+
+ /* reset and enable Rx/Tx */
+ psc->command = PSC_RST_RX;
+ psc->command = PSC_RST_TX;
+ psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;
+
+ return (0);
+}
+
+#else /* !CONFIG_MPC5xxx */
static inline unsigned int ps2ser_in(int offset)
{
return 0;
}
+#endif /* CONFIG_MPC5xxx */
void ps2ser_putc(int chr)
{
+#ifdef CONFIG_MPC5xxx
+ volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
+#endif
#ifdef DEBUG
printf(">>>> 0x%02x\n", chr);
#endif
+#ifdef CONFIG_MPC5xxx
+ while (!(psc->psc_status & PSC_SR_TXRDY));
+
+ psc->psc_buffer_8 = chr;
+#else
while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE));
ps2ser_out(UART_TX, chr);
+#endif
}
static int ps2ser_getc_hw(void)
{
+#ifdef CONFIG_MPC5xxx
+ volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
+#endif
int res = -1;
+#ifdef CONFIG_MPC5xxx
+ if (psc->psc_status & PSC_SR_RXRDY) {
+ res = (psc->psc_buffer_8);
+ }
+#else
if (ps2ser_in(UART_LSR) & UART_LSR_DR) {
res = (ps2ser_in(UART_RX));
}
+#endif
return res;
}
static void ps2ser_interrupt(void *dev_id)
{
+#ifdef CONFIG_MPC5xxx
+ volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
+#endif
int chr;
- int iir;
+ int status;
do {
chr = ps2ser_getc_hw();
- iir = ps2ser_in(UART_IIR);
+#ifdef CONFIG_MPC5xxx
+ status = psc->psc_status;
+#else
+ status = ps2ser_in(UART_IIR);
+#endif
if (chr < 0) continue;
if (atomic_read(&ps2buf_cnt) < PS2BUF_SIZE) {
} else {
printf ("ps2ser.c: buffer overflow\n");
}
- } while (iir & UART_IIR_RDI);
+#ifdef CONFIG_MPC5xxx
+ } while (status & PSC_SR_RXRDY);
+#else
+ } while (status & UART_IIR_RDI);
+#endif
if (atomic_read(&ps2buf_cnt)) {
ps2mult_callback(atomic_read(&ps2buf_cnt));
#endif
#elif defined(CONFIG_5xx)
#include <asm/5xx_immap.h>
+#elif defined(CONFIG_MPC5xxx)
+#include <mpc5xxx.h>
#elif defined(CONFIG_MPC8220)
#include <asm/immap_8220.h>
#elif defined(CONFIG_8260)
void setenv (char *, char *);
#endif /* CONFIG_PPC */
#ifdef CONFIG_ARM
-# include <asm/mach-types.h>
# include <asm/setup.h>
# include <asm/u-boot-arm.h> /* ARM version to be fixed! */
#endif /* CONFIG_ARM */
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
+#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+#ifdef CONFIG_STK52XX
+#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
+#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
+#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
+#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
+#define CONFIG_BOARD_EARLY_INIT_R
+#endif /* CONFIG_STK52XX */
#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
/*
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
+#ifdef CONFIG_STK52XX
+#define CONFIG_PCI 1
+#elif
#define CONFIG_PCI 0
+#endif
#define CONFIG_PCI_PNP 1
/* #define CONFIG_PCI_SCAN_SHOW 1 */
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
-#define ADD_PCI_CMD 0 /* CFG_CMD_PCI */
+#ifdef CONFIG_STK52XX
+#define ADD_PCI_CMD CFG_CMD_PCI
+#elif
+#define ADD_PCI_CMD 0
+#endif
#else /* MPC5100 */
#endif
/* USB */
-#if 0
+#ifdef CONFIG_STK52XX
#define CONFIG_USB_OHCI
#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_DOS_PARTITION
#define CONFIG_USB_STORAGE
#else
#define ADD_USB_CMD 0
#endif
/* IDE */
-#if defined (CONFIG_MINIFAP)
+#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX)
#define ADD_IDE_CMD CFG_CMD_IDE | CFG_CMD_FAT
#else
#define ADD_IDE_CMD 0
"update=protect off 1:0-4; erase 1:0-4; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-4\0" \
"serverip=172.20.5.13\0" \
""
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
+ "bootfile=uImage_tqm5200_mkr\0" \
+ "load=tftp 200000 $(loadfile)\0" \
+ "load133=tftp 200000 $(loadfile133)\0" \
+ "loadfile=u-boot_tqm5200_mkr.bin\0" \
+ "loadfile133=u-boot_tqm5200_133_mkr.bin\0" \
+ "update=protect off fc000000 fc03ffff; erase fc000000 fc03ffff; cp.b 200000 0xfc000000 $(filesize); protect on fc000000 fc03ffff\0" \
+ "serverip=172.20.5.13\0" \
+ ""
#endif
#endif
#endif
*/
#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
-#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AC)
-#define CFG_FLASH_SIZE 0x00400000 /* 4 MByte */
-#define CFG_MAX_FLASH_SECT 35 /* max num of sects on one chip */
-#else
-#ifdef CONFIG_TQM5200_AB
+/* use CFI flash driver if no module variant is spezified */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
+#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE 0x02000000 /* 32 MByte */
#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
-#endif
-#endif
#if !defined(CFG_LOWBOOT)
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00740000 + 0x00800000)
#else /* CFG_LOWBOOT */
-#if defined(CONFIG_TQM5200_AA) || defined(CONFIG_TQM5200_AB) || \
- defined (CONFIG_TQM5200_AC)
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
-#endif
#endif /* CFG_LOWBOOT */
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
(= chip selects) */
* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
* EEPROM
* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
- * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
- * 011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
+ * use PSC6:
+ * on STK52xx:
+ * use as UART. Pins PSC6_0 to PSC6_3 are used.
+ Bits 9:11 (mask: 0x00700000):
+ * 101 -> PSC6 : Extended POST test is not available
+ * on MINI-FAP and TQM5200_IB:
+ * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
+ * 011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
* GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
* tests.
*/
#if defined (CONFIG_MINIFAP)
-#define CFG_GPS_PORT_CONFIG 0x93000004
+#define CFG_GPS_PORT_CONFIG 0x91300004
+#elif defined (CONFIG_STK52XX)
+#define CFG_GPS_PORT_CONFIG 0x81500004
#else
-#define CFG_GPS_PORT_CONFIG 0x83000004
+#define CFG_GPS_PORT_CONFIG 0x81300004
#endif
/*
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
+/* automatic configuration of chip selects */
+#ifdef CONFIG_CS_AUTOCONF
+#define CONFIG_LAST_STAGE_INIT
+#endif
+
/*
* SRAM - Do not map below 2 GB in address space, because this area is used
* for SDRAM autosizing.
*/
-#ifdef CONFIG_TQM5200_AB
+#if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF)
#define CFG_CS2_START 0xE5000000
+#ifdef CONFIG_TQM5200_AB
#define CFG_CS2_SIZE 0x80000 /* 512 kByte */
+#else /* CONFIG_CS_AUTOCONF */
+#define CFG_CS2_SIZE 0x100000 /* 1 MByte */
+#endif
#define CFG_CS2_CFG 0x0004D930
#endif
* Grafic controller - Do not map below 2 GB in address space, because this
* area is used for SDRAM autosizing.
*/
-#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC)
+#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \
+ defined (CONFIG_CS_AUTOCONF)
#define CFG_CS1_START 0xE0000000
#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
#define CFG_CS1_CFG 0x8F48FF70
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