dbau1x00 MIPS32 Au1000
gth2 MIPS32 Au1000
-Vlad Lungu <vlad@comsys.ro>
+Vlad Lungu <vlad.lungu@windriver.com>
qemu_mips MIPS32
#########################################################################
# This target actually generates 2 files; autoconf.mk and autoconf.mk.dep.
# the dep file is only include in this top level makefile to determine when
# to regenerate the autoconf.mk file.
-$(obj)include/autoconf.mk: $(obj)include/config.h $(VERSION_FILE)
+$(obj)include/autoconf.mk: $(obj)include/config.h
@$(XECHO) Generating include/autoconf.mk ; \
set -e ; \
: Generate the dependancies ; \
CONFIG_CMD_SPI * SPI serial bus support
CONFIG_CMD_USB * USB support
CONFIG_CMD_VFD * VFD support (TRAB)
- CONFIG_CMD_BSP * Board SPecific functions
CONFIG_CMD_CDP * Cisco Discover Protocol support
CONFIG_CMD_FSL * Microblaze FSL support
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
-TEXT_BASE = 0xFFFC0000
+TEXT_BASE = 0xFFF80000
endif
ifeq ($(debug),1)
#include <asm/processor.h>
#include <asm/io.h>
#include <spd_sdram.h>
+#include <libfdt.h>
+#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
/* give reset to BCSR */
*(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09;
}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 val[4];
+ int rc;
+
+ ft_cpu_setup(blob, bd);
+
+ /* Fixup NOR mapping */
+ val[0] = 0; /* chip select number */
+ val[1] = 0; /* always 0 */
+ val[2] = gd->bd->bi_flashstart;
+ val[3] = gd->bd->bi_flashsize;
+ rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
+ val, sizeof(val), 1);
+ if (rc)
+ printf("Unable to update property NOR mapping, err=%s\n",
+ fdt_strerror(rc));
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-By Vlad Lungu vlad@comsys.ro 2007-Oct-01
+By Vlad Lungu vlad.lungu@windriver.com 2007-Oct-01
----------------------------------------
Qemu is a full system emulator. See
Supports the "-m mips" configuration of qemu: serial,NE2000,IDE.
Support is big endian only for now (or at least this is what I tested).
Derived from au1x00 with a lot of things cut out.
+
+Supports emulated flash (patch Jean-Christophe PLAGNIOL-VILLARD) with
+recent qemu versions. When using emulated flash, launch with
+-pflash <filename> and erase mips_bios.bin.
/*
* (C) Copyright 2007
- * Vlad Lungu vlad@comsys.ro
+ * Vlad Lungu vlad.lungu@windriver.com
*
* See file CREDITS for list of people who contributed to this
* project.
# include <status_led.h>
#endif
-#ifndef __PPC__
-#include <asm/io.h>
-#endif
-
#ifdef CONFIG_IDE_8xx_DIRECT
DECLARE_GLOBAL_DATA_PTR;
#endif
{ IH_ARCH_MIPS64, "mips64", "MIPS 64 Bit", },
{ IH_ARCH_NIOS, "nios", "NIOS", },
{ IH_ARCH_NIOS2, "nios2", "NIOS II", },
+ { IH_ARCH_PPC, "powerpc", "PowerPC", },
{ IH_ARCH_PPC, "ppc", "PowerPC", },
{ IH_ARCH_S390, "s390", "IBM S390", },
{ IH_ARCH_SH, "sh", "SuperH", },
#include <post.h>
-#if defined(CONFIG_SILENT_CONSOLE) || defined(CONFIG_POST)
+#if defined(CONFIG_SILENT_CONSOLE) || defined(CONFIG_POST) || defined(CONFIG_CMDLINE_EDITING)
DECLARE_GLOBAL_DATA_PTR;
#endif
char console_buffer[CFG_CBSIZE]; /* console I/O buffer */
-#ifndef CONFIG_CMDLINE_EDITING
static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen);
static char erase_seq[] = "\b \b"; /* erase sequence */
static char tab_seq[] = " "; /* used to expand TABs */
-#endif /* CONFIG_CMDLINE_EDITING */
#ifdef CONFIG_BOOT_RETRY_TIME
static uint64_t endtime = 0; /* must be set, default is instant timeout */
initted = 1;
}
- puts (prompt);
- rc = cread_line(prompt, p, &len);
- return rc < 0 ? rc : len;
-#else
+ /*
+ * History uses a global array which is not
+ * writable until after relocation to RAM.
+ * Revert to non-history version if still
+ * running from flash.
+ */
+ if (gd->flags & GD_FLG_RELOC) {
+ if (!initted) {
+ hist_init();
+ initted = 1;
+ }
+
+ puts (prompt);
+
+ rc = cread_line(prompt, p, &len);
+ return rc < 0 ? rc : len;
+
+ } else {
+#endif /* CONFIG_CMDLINE_EDITING */
char * p_buf = p;
int n = 0; /* buffer index */
int plen = 0; /* prompt length */
}
}
}
-#endif /* CONFIG_CMDLINE_EDITING */
+#ifdef CONFIG_CMDLINE_EDITING
+ }
+#endif
}
/****************************************************************************/
-#ifndef CONFIG_CMDLINE_EDITING
static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen)
{
char *s;
(*np)--;
return (p);
}
-#endif /* CONFIG_CMDLINE_EDITING */
/****************************************************************************/
blr
/*
- * Invalidate L2 cache using L2I and polling L2IP
+ * Invalidate L2 cache using L2I and polling L2IP or L2I
*/
_GLOBAL(l2cache_invalidate)
sync
+ mfspr r3, l2cr
oris r3, r3, L2CR_L2I@h
sync
mtspr l2cr, r3
sync
+ mfspr r3, PVR
+ sync
+ rlwinm r3, r3, 16,16,31
+ cmpli 0,r3,0x8000 /* 7451, 7441 */
+ beq 0,inv_7450
+ cmpli 0,r3,0x8001 /* 7455, 7445 */
+ beq 0,inv_7450
+ cmpli 0,r3,0x8002 /* 7457, 7447 */
+ beq 0,inv_7450
+ cmpli 0,r3,0x8003 /* 7447A */
+ beq 0,inv_7450
+ cmpli 0,r3,0x8004 /* 7448 */
+ beq 0,inv_7450
invl2:
mfspr r3, l2cr
andi. r3, r3, L2CR_L2IP
mtspr l2cr, r3
sync
blr
+inv_7450:
+ mfspr r3, l2cr
+ andis. r3, r3, L2CR_L2I@h
+ bne inv_7450
+ blr
/*
* Enable L2 cache
}
# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
-#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
+#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) */
invl2:
mfspr r3, l2cr
- andi. r3, r3, L2CR_L2I@h
+ andis. r3, r3, L2CR_L2I@h
bne invl2
blr
/*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
#include <asm/cache.h>
#include <ppc4xx.h>
-#if defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
#include <libfdt.h>
#include <libfdt_env.h>
#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
+void __ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 val[4];
+ int rc;
+
+ ft_cpu_setup(blob, bd);
+
+ /* Fixup NOR mapping */
+ val[0] = 0; /* chip select number */
+ val[1] = 0; /* always 0 */
+ val[2] = gd->bd->bi_flashstart;
+ val[3] = gd->bd->bi_flashsize;
+ rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
+ val, sizeof(val), 1);
+ if (rc)
+ printf("Unable to update property NOR mapping, err=%s\n",
+ fdt_strerror(rc));
+}
+void ft_board_setup(void *blob, bd_t *bd) __attribute__((weak, alias("__ft_board_setup")));
+
/*
* Fixup all PCIe nodes by setting the device_type property
* to "pci-endpoint" instead is "pci" for endpoint ports.
*/
fdt_pcie_setup(blob);
}
-#endif /* CONFIG_OF_LIBFDT */
+#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */
/* values for: 101 - 200 */
0x78, 0xf1, 0x62, 0xc5, 0x0a, 0x94, 0x28, 0xd0, 0x21, 0xc3,
0x06, 0x8c, 0x18, 0xb0, 0x60, 0xc1, 0x02, 0x84, 0x08, 0x90,
- 0x20, 0xc0, 0x01, 0x83, 0x77, 0xff, 0x1f, 0xbf, 0x7f, 0xfe,
+ 0x20, 0xc0, 0x01, 0x83, 0x07, 0x8f, 0x1f, 0xbf, 0x7f, 0xfe,
0x7d, 0xfa, 0x75, 0xea, 0x55, 0xaa, 0x54, 0xa9, 0x53, 0xa6,
0x4c, 0x99, 0x33, 0xe7, 0x4e, 0x9d, 0x3b, 0xf7, 0x6e, 0xdd,
0x3a, 0xf4, 0x69, 0xd2, 0x25, 0xcb, 0x16, 0xac, 0x58, 0xb1,
lbaint_t lba512;
#endif
- if (dev_desc->type==DEV_TYPE_UNKNOWN) {
- puts ("not available\n");
- return;
- }
- if (dev_desc->if_type==IF_TYPE_SCSI) {
- printf ("(%d:%d) ", dev_desc->target,dev_desc->lun);
- }
- if (dev_desc->if_type==IF_TYPE_IDE) {
- printf ("Model: %s Firm: %s Ser#: %s\n",
+ switch (dev_desc->type) {
+ case IF_TYPE_SCSI:
+ printf ("(%d:%d) Vendor: %s Prod.: %s Rev: %s\n",
+ dev_desc->target,dev_desc->lun,
dev_desc->vendor,
- dev_desc->revision,
- dev_desc->product);
- }
- if (dev_desc->if_type==IF_TYPE_SATA) {
+ dev_desc->product,
+ dev_desc->revision);
+ break;
+ case IF_TYPE_IDE:
+ case IF_TYPE_SATA:
printf ("Model: %s Firm: %s Ser#: %s\n",
dev_desc->vendor,
dev_desc->revision,
dev_desc->product);
- } else {
- printf ("Vendor: %s Prod.: %s Rev: %s\n",
- dev_desc->vendor,
- dev_desc->product,
- dev_desc->revision);
+ break;
+ case DEV_TYPE_UNKNOWN:
+ default:
+ puts ("not available\n");
+ return;
}
puts (" Type: ");
if (dev_desc->removable)
puts ("Removable ");
switch (dev_desc->type & 0x1F) {
- case DEV_TYPE_HARDDISK: puts ("Hard Disk");
- break;
- case DEV_TYPE_CDROM: puts ("CD ROM");
- break;
- case DEV_TYPE_OPDISK: puts ("Optical Device");
- break;
- case DEV_TYPE_TAPE: puts ("Tape");
- break;
- default: printf ("# %02X #", dev_desc->type & 0x1F);
- break;
+ case DEV_TYPE_HARDDISK:
+ puts ("Hard Disk");
+ break;
+ case DEV_TYPE_CDROM:
+ puts ("CD ROM");
+ break;
+ case DEV_TYPE_OPDISK:
+ puts ("Optical Device");
+ break;
+ case DEV_TYPE_TAPE:
+ puts ("Tape");
+ break;
+ default:
+ printf ("# %02X #", dev_desc->type & 0x1F);
+ break;
}
puts ("\n");
if ((dev_desc->lba * dev_desc->blksz)>0L) {
{
puts ("\nPartition Map for ");
switch (dev_desc->if_type) {
- case IF_TYPE_IDE: puts ("IDE");
- break;
- case IF_TYPE_SATA: puts ("SATA");
- break;
- case IF_TYPE_SCSI: puts ("SCSI");
- break;
- case IF_TYPE_ATAPI: puts ("ATAPI");
- break;
- case IF_TYPE_USB: puts ("USB");
- break;
- case IF_TYPE_DOC: puts ("DOC");
- break;
- default: puts ("UNKNOWN");
- break;
+ case IF_TYPE_IDE:
+ puts ("IDE");
+ break;
+ case IF_TYPE_SATA:
+ puts ("SATA");
+ break;
+ case IF_TYPE_SCSI:
+ puts ("SCSI");
+ break;
+ case IF_TYPE_ATAPI:
+ puts ("ATAPI");
+ break;
+ case IF_TYPE_USB:
+ puts ("USB");
+ break;
+ case IF_TYPE_DOC:
+ puts ("DOC");
+ break;
+ default:
+ puts ("UNKNOWN");
+ break;
}
printf (" device %d -- Partition Type: %s\n\n",
dev_desc->dev, type);
completely without NOR FLASH. This can be done by using the NAND
boot feature of the 440 NAND flash controller (NDFC).
-Here a short desciption of the different boot stages:
+Here a short description of the different boot stages:
a) IPL (Initial Program Loader, integrated inside CPU)
------------------------------------------------------
/autoconf.mk*
/asm
-/asm-blackfin/arch
-/asm-ppc/arch
+/asm-*/arch
+/asm-*/proc
/bmp_logo.h
/config.h
/config.mk
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */
-
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xfe000000
-#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_CPLD_BASE 0x80000000
#define CFG_NAND_ADDR 0xd0000000
#define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_BASE + 1)
+#define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */
+
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer
*----------------------------------------------------------------------*/
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_NET_MULTI 1
#define CFG_RX_ETH_BUFFER 16 /* # of rx buffers & descriptors*/
+#define CONFIG_HAS_ETH0 1
#define CONFIG_NETCONSOLE /* include NetConsole support */
#undef CONFIG_BOOTARGS
+#define xstr(s) str(s)
+#define str(s) #s
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=acadia\0" \
"ramdisk_addr=fff20000\0" \
"initrd_high=30000000\0" \
"load=tftp 200000 acadia/u-boot.bin\0" \
- "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
- "cp.b ${fileaddr} fffc0000 ${filesize};" \
+ "update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \
+ "era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \
+ "cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \
"setenv filesize;saveenv\0" \
"upd=run load update\0" \
"nload=tftp 200000 acadia/u-boot-nand.bin\0" \
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_HAS_ETH0
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
#define CONFIG_PHY1_ADDR 1
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
+#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
#define CONFIG_NET_MULTI 1
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 8 /* PHY address */
+#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR 9 /* EMAC1 PHY address */
#define CONFIG_NET_MULTI 1
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
#define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */
#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_LEN + 1)
+#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_BASE + 1)
#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
/*-----------------------------------------------------------------------
* Some Kilauea stuff..., mainly fpga registers
*/
#define CFG_FPGA_REG_BASE CFG_FPGA_BASE
-#define CFG_FPGA_FIFO_BASE (in32(CFG_FPGA_BASE) | (1 << 11))
+#define CFG_FPGA_FIFO_BASE (in32(CFG_FPGA_BASE) | (1 << 10))
/* interrupt */
#define CFG_FPGA_SLIC0_R_DPRAM_INT 0x80000000
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_HAS_ETH0
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1
#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
/* ethernet */
#ifdef XILINX_EMAC_BASEADDR
#define CONFIG_XILINX_EMAC 1
+#define CFG_ENET
#else
#ifdef XILINX_EMACLITE_BASEADDR
#define CONFIG_XILINX_EMACLITE 1
+#define CFG_ENET
#endif
#endif
#undef ET_DEBUG
#endif
/* interrupt controller */
+#ifdef XILINX_INTC_BASEADDR
#define CFG_INTC_0 1
#define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR
#define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
+#endif
/* timer */
+#ifdef XILINX_TIMER_BASEADDR
+#if (XILINX_TIMER_IRQ != -1)
#define CFG_TIMER_0 1
#define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR
#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
#define FREQUENCE XILINX_CLOCK_FREQ
#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
+#endif
+#else
+#ifdef XILINX_CLOCK_FREQ
#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
-
+#else
+#error BAD CLOCK FREQ
+#endif
+#endif
/* FSL */
/* #define CFG_FSL_2 */
/* #define FSL_INTR_2 1 */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MFSL
-#define CONFIG_CMD_PING
+
+#ifndef CFG_ENET
+ #undef CONFIG_CMD_NET
+#else
+ #define CONFIG_CMD_PING
+#endif
#if defined(CONFIG_SYSTEMACE)
#define CONFIG_CMD_EXT2
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0x14 /* PHY address */
+#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */
#define CONFIG_NET_MULTI 1
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
+#define CONFIG_HAS_ETH0 1
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* needed for NetConsole */
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
/* ethernet */
#ifdef XILINX_EMAC_BASEADDR
#define CONFIG_XILINX_EMAC 1
+#define CFG_ENET
#else
#ifdef XILINX_EMACLITE_BASEADDR
#define CONFIG_XILINX_EMACLITE 1
+#define CFG_ENET
#endif
#endif
#undef ET_DEBUG
#endif
/* interrupt controller */
+#ifdef XILINX_INTC_BASEADDR
#define CFG_INTC_0 1
#define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR
#define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
+#endif
/* timer */
+#ifdef XILINX_TIMER_BASEADDR
+#if (XILINX_TIMER_IRQ != -1)
#define CFG_TIMER_0 1
#define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR
#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
#define FREQUENCE XILINX_CLOCK_FREQ
#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
+#endif
+#else
+#ifdef XILINX_CLOCK_FREQ
#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
-
+#else
+#error BAD CLOCK FREQ
+#endif
+#endif
/*
* memory layout - Example
* TEXT_BASE = 0x3600_0000;
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_PING
+
+#ifndef CFG_ENET
+ #undef CONFIG_CMD_NET
+#else
+ #define CONFIG_CMD_PING
+#endif
#ifdef XILINX_SYSACE_BASEADDR
#define CONFIG_CMD_EXT2
#define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */
#define CFG_SDRAM_BANKS (2)
-
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1 /* required for netconsole */
#define CONFIG_PHY1_ADDR 3
+#define CONFIG_HAS_ETH0 1 /* add support for "ethaddr" */
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
/*---------------------------------------------------------------------------*/
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
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