Changes for U-Boot 1.1.3:
======================================================================
+* Patch by Stefan Roese, 06 Apr 2005:
+ Updates for OCOTEA board:
+ - Changed U-Boot size from 512kByte to 256kByte
+ - Fixed flash driver to support boot from soldered user flash
+ - Added README for switch from PIBS firmware to U-Boot
+
+* Patch by Travis Sawyer, 05 Apr 2005:
+ - Change timer frequency for ppc 440 from 10 ms to 1 ms.
+ Problem found by Andrew Wozniak.
+
* Patch by Steven Scholz, 06 Apr 2005:
- creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200
- moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200
ifeq ($(ramsym),1)
TEXT_BASE = 0x07FD0000
else
-TEXT_BASE = 0xFFF80000
+TEXT_BASE = 0xFFFC0000
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
/*
- * (C) Copyright 2004
+ * (C) Copyright 2004-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
#define DEBUGF(x...)
#endif /* DEBUG */
-#define BOOT_SMALL_FLASH 32 /* 00100000 */
+#define BOOT_SMALL_FLASH 0x40 /* 01000000 */
+#define FLASH_ONBD_N 2 /* 00000010 */
+#define FLASH_SRAM_SEL 1 /* 00000001 */
#define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
- {0xFF800000, 0xFF900000, 0xFFC00000}, /* 0:000: configuraton 4 */
- {0xFF900000, 0xFF800000, 0xFFC00000}, /* 1:001: configuraton 3 */
+ {0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */
+ {0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */
{0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */
{0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */
{0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */
total_b += flash_info[i].size;
}
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CFG_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[2]);
+
return total_b;
}
case FLASH_MAN_AMD:
printf("AMD ");
break;
+ case FLASH_MAN_STM:
+ printf("STM ");
+ break;
case FLASH_MAN_FUJ:
printf("FUJITSU ");
break;
info->sector_count = 8;
info->size = 0x0080000; /* => 512 ko */
break;
+ case (FLASH_WORD_SIZE) STM_ID_M29W040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
case (FLASH_WORD_SIZE) AMD_ID_LV033C:
info->flash_id += FLASH_AMDLV033C;
info->sector_count = 64;
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- (info->flash_id == FLASH_AM040) ||
- (info->flash_id == FLASH_AMD016)) {
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
} else {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if ( i == 32 ) {
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55555555;
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90909090;
+ }
+
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
info->protect[i] = 0;
else
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
- printf("Erasing sector %p\n", addr2);
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
int board_early_init_f (void)
{
unsigned long mfr;
+ unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
+ unsigned char switch_status;
+ unsigned long cs0_base;
+ unsigned long cs0_size;
+ unsigned long cs0_twt;
+ unsigned long cs2_base;
+ unsigned long cs2_size;
+ unsigned long cs2_twt;
+
/*-------------------------------------------------------------------------+
| Initialize EBC CONFIG
+-------------------------------------------------------------------------*/
EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
+ /*-------------------------------------------------------------------------+
+ | FPGA. Initialize bank 7 with default values.
+ +-------------------------------------------------------------------------*/
+ mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
+ EBC_BXAP_BCE_DISABLE|
+ EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+ EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+ EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+ EBC_BXAP_BEM_WRITEONLY|
+ EBC_BXAP_PEN_DISABLED);
+ mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
+ EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+ /* read FPGA base register FPGA_REG0 */
+ switch_status = *fpga_base;
+
+ if (switch_status & 0x40) {
+ cs0_base = 0xFFE00000;
+ cs0_size = EBC_BXCR_BS_2MB;
+ cs0_twt = 8;
+ cs2_base = 0xFF800000;
+ cs2_size = EBC_BXCR_BS_4MB;
+ cs2_twt = 10;
+ } else {
+ cs0_base = 0xFFC00000;
+ cs0_size = EBC_BXCR_BS_4MB;
+ cs0_twt = 10;
+ cs2_base = 0xFF800000;
+ cs2_size = EBC_BXCR_BS_2MB;
+ cs2_twt = 8;
+ }
+
/*-------------------------------------------------------------------------+
| 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
+-------------------------------------------------------------------------*/
- mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(8)|
+ mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
EBC_BXAP_BCE_DISABLE|
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
EBC_BXAP_BEM_WRITEONLY|
EBC_BXAP_PEN_DISABLED);
- mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(0xFFE00000)|
- EBC_BXCR_BS_2MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+ mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|
+ cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
/*-------------------------------------------------------------------------+
| 8KB NVRAM/RTC. Initialize bank 1 with default values.
/*-------------------------------------------------------------------------+
| 4 MB FLASH. Initialize bank 2 with default values.
+-------------------------------------------------------------------------*/
- mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
+ mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
EBC_BXAP_BCE_DISABLE|
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
EBC_BXAP_BEM_WRITEONLY|
EBC_BXAP_PEN_DISABLED);
- mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xFF800000)|
- EBC_BXCR_BS_4MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+ mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|
+ cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
/*-------------------------------------------------------------------------+
| FPGA. Initialize bank 7 with default values.
--- /dev/null
+------------------------------------------
+Installation of U-Boot using PIBS firmware
+------------------------------------------
+
+This document describes how to install U-Boot on the Ocotea PPC440GX
+Evaluation Board. We do not erase the PIBS firmware but install U-Boot in the
+soldered FLASH. After this you should be able to switch between PIBS and
+U-Boot via the switch U46 SW1. Please check that SW1 is off (= open) before
+continuing.
+
+Connect to the serial port 0 (J11 lower) of the Ocotea board using the cu
+program. See the hints for configuring cu above. Make sure you can
+communicate with the PIBS firmware: reset the board and hit ENTER a couple of
+times until you see the PIBS prompt (PIBS $). Then proceed as follows:
+
+
+Read MAC Addresses from PIBS
+----------------------------
+
+To read the configured MAC addresses available on your Ocotea board please use
+the following commands:
+
+PIBS $ echo $hwdaddr0
+000173017FE3
+PIBS $ echo $hwdaddr1
+000173017FE4
+PIBS $ echo $hwdaddr2
+000173017FE1
+PIBS $ echo $hwdaddr3
+000173017FE2
+
+In U-Boot this is stored in the following environment variables:
+
+* Ethernet Address 0: ethaddr = 000173017FE3 (==> 00:01:73:01:7F:E3)
+* Ethernet Address 1: eth1addr = 000173017FE4 (==> 00:01:73:01:7F:E4)
+* Ethernet Address 2: eth2addr = 000173017FE1 (==> 00:01:73:01:7F:E1)
+* Ethernet Address 3: eth3addr = 000173017FE2 (==> 00:01:73:01:7F:E2)
+
+
+Configure the network interface (ent0 == emac0)
+-----------------------------------------------
+
+To download the U-Boot image we need to configure the ethernet interface with
+the following commands:
+
+PIBS $ ifconfig ent0 192.168.160.142 netmask 255.255.0.0 up
+PIBS $ set ipdstaddr0=192.168.1.1
+status: writing PIBS variable value to FLASH
+PIBS $ set bootfilename=/tftpboot/ocotea/u-boot.bin
+status: writing PIBS variable value to FLASH
+
+Please insert correct parameters for your configuration (ip-addresses and
+file-location).
+
+
+Program U-Boot into soldered User-FLASH
+---------------------------------------
+
+Please make sure to use a newer version of U-Boot (at least 1.1.3), since
+older versions don't support running from user-FLASH.
+
+To program U-Boot into the soldered user-FLASH use the following command:
+
+PIBS $ storefile bin eth 0xffbc0000
+
+This commands loads the file vis ethernet into ram and copies it into the
+user-FLASH.
+
+
+Switch to U-Boot
+----------------
+
+Now you can turn your board off and switch SW1 (U46) to on (= closed). After
+powering the board you should see the following message:
+
+U-Boot 1.1.3 (Apr 5 2005 - 22:59:57)
+
+IBM PowerPC 440 GX Rev. C
+Board: IBM 440GX Evaluation Board
+ VCO: 1066 MHz
+ CPU: 533 MHz
+ PLB: 152 MHz
+ OPB: 76 MHz
+ EPB: 76 MHz
+I2C: ready
+DRAM: 256 MB
+FLASH: 5 MB
+PCI: Bus Dev VenId DevId Class Int
+In: serial
+Out: serial
+Err: serial
+KGDB: kgdb ready
+ready
+Net: ppc_440x_eth0, ppc_440x_eth1, ppc_440x_eth2, ppc_440x_eth3
+BEDBUG:ready
+=>
+
+
+April 06 2005, Stefan Roese <sr@denx.de>
*----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
-#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */
+#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
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