[PPC440SPe] Improve PCIe configuration space access

- correct configuration space mapping
- correct bus numbering
- better access to config space

Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the
first device on the first bus. We now allow to configure up to 16 buses;
also, scanning for devices behind the PCIe-PCIe bridge is supported, so
peripheral devices farther in hierarchy can be identified.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>

diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S
index 5202ae694ce935eb9729d01f2cd3e5008eb2d8ad..e3f3da6bd84f75bdd3176444453afc209f7814a4 100644 (file)
--- a/board/amcc/katmai/init.S
+++ b/board/amcc/katmai/init.S
@@ -67,9 +67,9 @@ tlbtabA:
        tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
        tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 
-       tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
        tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
        tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
        tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
@@ -109,9 +109,9 @@ tlbtabB:
        tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
        tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 
-       tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
        tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
        tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
        tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)

diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index b804d55f2e7d33e11f2888de85bf642bb93e308b..a9ae4a373923b41caf4eaf83916f94004679f6b4 100644 (file)
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -392,7 +392,7 @@ int katmai_pcie_card_present(int port)
 
 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
 
-void pcie_setup_hoses(void)
+void pcie_setup_hoses(int busno)
 {
        struct pci_controller *hose;
        int i, bus;
@@ -401,7 +401,7 @@ void pcie_setup_hoses(void)
         * assume we're called after the PCIX hose is initialized, which takes
         * bus ID 0 and therefore start numbering PCIe's from 1.
         */
-       bus = 1;
+       bus = busno;
        for (i = 0; i <= 2; i++) {
                /* Check for katmai card presence */
                if (!katmai_pcie_card_present(i))
@@ -418,8 +418,8 @@ void pcie_setup_hoses(void)
 
                hose = &pcie_hose[i];
                hose->first_busno = bus;
-               hose->last_busno  = bus;
-               bus++;
+               hose->last_busno = bus;
+               hose->current_busno = bus;
 
                /* setup mem resource */
                pci_set_region(hose->regions + 0,
@@ -443,6 +443,7 @@ void pcie_setup_hoses(void)
                 * Config access can only go down stream
                 */
                hose->last_busno = pci_hose_scan(hose);
+               bus = hose->last_busno + 1;
 #endif
        }
 }

diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S
index c92dcf7a514a9a54a46537812390569a4393dfcf..67e8f8f3a2c53bc1c5432555b479c3fcb16f6c44 100644 (file)
--- a/board/amcc/yucca/init.S
+++ b/board/amcc/yucca/init.S
@@ -70,9 +70,9 @@ tlbtabA:
        tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
        tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 
-       tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
        tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
        tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
        tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
@@ -112,9 +112,9 @@ tlbtabB:
        tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
        tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 
-       tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
        tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
        tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
        tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)

diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index d08fcf3565ffc618eb0e3b2ce0fdc1e70b75d62d..252e4fe07a61e49525180f45b40ff313473942c0 100644 (file)
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -846,7 +846,7 @@ void yucca_setup_pcie_fpga_endpoint(int port)
 
 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
 
-void pcie_setup_hoses(void)
+void pcie_setup_hoses(int busno)
 {
        struct pci_controller *hose;
        int i, bus;
@@ -855,7 +855,7 @@ void pcie_setup_hoses(void)
         * assume we're called after the PCIX hose is initialized, which takes
         * bus ID 0 and therefore start numbering PCIe's from 1.
         */
-       bus = 1;
+       bus = busno;
        for (i = 0; i <= 2; i++) {
                /* Check for yucca card presence */
                if (!yucca_pcie_card_present(i))
@@ -874,8 +874,8 @@ void pcie_setup_hoses(void)
 
                hose = &pcie_hose[i];
                hose->first_busno = bus;
-               hose->last_busno  = bus;
-               bus++;
+               hose->last_busno = bus;
+               hose->current_busno = bus;
 
                /* setup mem resource */
                pci_set_region(hose->regions + 0,
@@ -899,6 +899,7 @@ void pcie_setup_hoses(void)
                 * Config access can only go down stream
                 */
                hose->last_busno = pci_hose_scan(hose);
+               bus = hose->last_busno + 1;
 #endif
        }
 }

diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 28379298b72a9f7a19be590b8c26fe9ae08ba0c4..282e7a1ba4737d87a0f6641bb84638ea78a01cf1 100644 (file)
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -443,7 +443,7 @@ void pci_init_board(void)
 static struct pci_controller ppc440_hose = {0};
 
 
-void pci_440_init (struct pci_controller *hose)
+int pci_440_init (struct pci_controller *hose)
 {
        int reg_num = 0;
 
@@ -459,7 +459,7 @@ void pci_440_init (struct pci_controller *hose)
        if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
                printf("PCI: SDR0_STRP1[PISE] not set.\n");
                printf("PCI: Configuration aborted.\n");
-               return;
+               return -1;
        }
 #elif defined(CONFIG_440GP)
        unsigned long strap;
@@ -468,7 +468,7 @@ void pci_440_init (struct pci_controller *hose)
        if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
                printf("PCI: CPC0_STRP1[PISE] not set.\n");
                printf("PCI: Configuration aborted.\n");
-               return;
+               return -1;
        }
 #endif
 #endif /* CONFIG_DISABLE_PISE_TEST */
@@ -477,7 +477,7 @@ void pci_440_init (struct pci_controller *hose)
         * PCI controller init
         *--------------------------------------------------------------------------*/
        hose->first_busno = 0;
-       hose->last_busno = 0xff;
+       hose->last_busno = 0;
 
        /* PCI I/O space */
        pci_set_region(hose->regions + reg_num++,
@@ -515,7 +515,7 @@ void pci_440_init (struct pci_controller *hose)
        if (pci_pre_init (hose) == 0) {
                printf("PCI: Board-specific initialization failed.\n");
                printf("PCI: Configuration aborted.\n");
-               return;
+               return -1;
        }
 
        pci_register_hose( hose );
@@ -578,13 +578,16 @@ void pci_440_init (struct pci_controller *hose)
 #endif
                hose->last_busno = pci_hose_scan(hose);
        }
+       return hose->last_busno;
 }
 
 void pci_init_board(void)
 {
-       pci_440_init (&ppc440_hose);
+       int busno;
+
+       busno = pci_440_init (&ppc440_hose);
 #if defined(CONFIG_440SPE)
-       pcie_setup_hoses();
+       pcie_setup_hoses(busno + 1);
 #endif
 }
 

diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c
index 2d0b4067af71ae27c92675c5c2d2337af2c1c8f6..158f1c559576a0f4dd552372a5a7bc694f5e82c3 100644 (file)
--- a/cpu/ppc4xx/440spe_pcie.c
+++ b/cpu/ppc4xx/440spe_pcie.c
@@ -40,6 +40,23 @@ enum {
        LNKW_X8                 = 0x8
 };
 
+static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
+{
+       u8 *base = (u8*)hose->cfg_data;
+
+       /* use local configuration space for the first bus */
+       if (PCI_BUS(devfn) == 0) {
+               if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE)
+                       base = (u8*)CFG_PCIE0_XCFGBASE;
+               if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
+                       base = (u8*)CFG_PCIE1_XCFGBASE;
+               if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
+                       base = (u8*)CFG_PCIE2_XCFGBASE;
+       }
+
+       return base;
+}
+
 static void pcie_dmer_disable(void)
 {
        mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
@@ -60,18 +77,35 @@ static void pcie_dmer_enable(void)
                mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
 }
 
-
 static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
        int offset, int len, u32 *val) {
 
+       u8 *address;
        *val = 0;
+
+       /*
+        * Bus numbers are relative to hose->first_busno
+        */
+       devfn -= PCI_BDF(hose->first_busno, 0, 0);
+
        /*
-        * 440SPE implements only one function per port
+        * NOTICE: configuration space ranges are currenlty mapped only for
+        * the first 16 buses, so such limit must be imposed. In case more
+        * buses are required the TLB settings in board/amcc/<board>/init.S
+        * need to be altered accordingly (one bus takes 1 MB of memory space).
         */
-       if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
+       if (PCI_BUS(devfn) >= 16)
                return 0;
 
-       devfn = PCI_BDF(0,0,0);
+       /*
+        * Only single device/single function is supported for the primary and
+        * secondary buses of the 440SPe host bridge.
+        */
+       if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
+               ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
+               return 0;
+               
+       address = pcie_get_base(hose, devfn);
        offset += devfn << 4;
 
        /*
@@ -101,13 +135,24 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
 static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
        int offset, int len, u32 val) {
 
+       u8 *address;
+       
        /*
-        * 440SPE implements only one function per port
+        * Bus numbers are relative to hose->first_busno
         */
-       if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
+       devfn -= PCI_BDF(hose->first_busno, 0, 0);
+       
+       /*
+        * Same constraints as in pcie_read_config().
+        */
+       if (PCI_BUS(devfn) >= 16)
                return 0;
 
-       devfn = PCI_BDF(0,0,0);
+       if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
+               ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
+               return 0;
+       
+       address = pcie_get_base(hose, devfn);
        offset += devfn << 4;
 
        /*
@@ -137,7 +182,7 @@ int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u
        u32 v;
        int rv;
 
-       rv =  pcie_read_config(hose, dev, offset, 1, &v);
+       rv = pcie_read_config(hose, dev, offset, 1, &v);
        *val = (u8)v;
        return rv;
 }
@@ -794,12 +839,12 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
        volatile void *rmbase = NULL;
 
        pci_set_ops(hose,
-                   pcie_read_config_byte,
-                   pcie_read_config_word,
-                   pcie_read_config_dword,
-                   pcie_write_config_byte,
-                   pcie_write_config_word,
-                   pcie_write_config_dword);
+               pcie_read_config_byte,
+               pcie_read_config_word,
+               pcie_read_config_dword,
+               pcie_write_config_byte,
+               pcie_write_config_word,
+               pcie_write_config_dword);
 
        switch (port) {
        case 0:
@@ -822,14 +867,9 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
        /*
         * Set bus numbers on our root port
         */
-       if (ppc440spe_revB()) {
-               out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
-               out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
-               out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
-       } else {
-               out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
-               out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0);
-       }
+       out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
+       out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
+       out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
 
        /*
         * Set up outbound translation to hose->mem_space from PLB
@@ -886,6 +926,29 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
                 in_le16((u16 *)(mbase + PCI_COMMAND)) |
                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
        printf("PCIE:%d successfully set as rootpoint\n",port);
+       
+       /* Set Device and Vendor Id */
+       switch (port) {
+       case 0:
+               out_le16(mbase + 0x200, 0xaaa0);
+               out_le16(mbase + 0x202, 0xbed0);
+               break;
+       case 1:
+               out_le16(mbase + 0x200, 0xaaa1);
+               out_le16(mbase + 0x202, 0xbed1);
+               break;
+       case 2:
+               out_le16(mbase + 0x200, 0xaaa2);
+               out_le16(mbase + 0x202, 0xbed2);
+               break;
+       default:
+               out_le16(mbase + 0x200, 0xaaa3);
+               out_le16(mbase + 0x202, 0xbed3);
+       }
+
+       /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
+       out_le32(mbase + 0x208, 0x06040001);
+
 }
 
 int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
@@ -963,8 +1026,8 @@ int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
 
        /* Enable I/O, Mem, and Busmaster cycles */
        out_le16((u16 *)(mbase + PCI_COMMAND),
-                in_le16((u16 *)(mbase + PCI_COMMAND)) |
-                PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+               in_le16((u16 *)(mbase + PCI_COMMAND)) |
+               PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
        out_le16(mbase + 0x200,0xcaad);                 /* Setting vendor ID */
        out_le16(mbase + 0x202,0xfeed);                 /* Setting device ID */
        attempts = 10;

diff --git a/include/common.h b/include/common.h
index 9a5a0ab7988ce58a24a21192793167cf10c11f0a..aca281bdad6ad2064011a797cd6d88118d0c9ad8 100644 (file)
--- a/include/common.h
+++ b/include/common.h
@@ -275,7 +275,7 @@ void        pciinfo       (int, int);
 #   endif
     int            is_pci_host         (struct pci_controller *);
 #if defined(CONFIG_440SPE)
-   void pcie_setup_hoses(void);
+   void pcie_setup_hoses(int busno);
 #endif
 #endif
 

diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index b6d0f519a829acf1f6b9071cbf27a2a22a978db6..7834e39084698c74d69e73db464db6fe90dc921a 100644 (file)
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -66,11 +66,11 @@
 #define CFG_PCIE_BASE          0xe0000000      /* PCIe UTL regs */
 
 #define CFG_PCIE0_CFGBASE      0xc0000000
-#define CFG_PCIE0_XCFGBASE     0xc0000400
-#define CFG_PCIE1_CFGBASE      0xc0001000
-#define CFG_PCIE1_XCFGBASE     0xc0001400
-#define CFG_PCIE2_CFGBASE      0xc0002000
-#define CFG_PCIE2_XCFGBASE     0xc0002400
+#define CFG_PCIE1_CFGBASE      0xc1000000
+#define CFG_PCIE2_CFGBASE      0xc2000000
+#define CFG_PCIE0_XCFGBASE     0xc3000000
+#define CFG_PCIE1_XCFGBASE     0xc3001000
+#define CFG_PCIE2_XCFGBASE     0xc3002000
 
 /* System RAM mapped to PCI space */
 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE

diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 906f046fa7aa66da11a4199e696e5d62dcc20194..323535aa9fc1815d88cbac0412fed07f5962fc8d 100644 (file)
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -68,11 +68,11 @@
 #define CFG_PCIE_BASE          0xe0000000      /* PCIe UTL regs */
 
 #define CFG_PCIE0_CFGBASE      0xc0000000
-#define CFG_PCIE0_XCFGBASE     0xc0000400
-#define CFG_PCIE1_CFGBASE      0xc0001000
-#define CFG_PCIE1_XCFGBASE     0xc0001400
-#define CFG_PCIE2_CFGBASE      0xc0002000
-#define CFG_PCIE2_XCFGBASE     0xc0002400
+#define CFG_PCIE1_CFGBASE      0xc1000000
+#define CFG_PCIE2_CFGBASE      0xc2000000
+#define CFG_PCIE0_XCFGBASE     0xc3000000
+#define CFG_PCIE1_XCFGBASE     0xc3001000
+#define CFG_PCIE2_XCFGBASE     0xc3002000
 
 /* System RAM mapped to PCI space */
 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE