omap5/dra7: i2c: correct register offset for sync register

The register offset of i2c_sysc offset is not correct as per
omap5[1]/dra7[2] TRM, correct the offsets as per the
documentation.

[1] - http://www.ti.com/lit/pdf/swpu249
[2] - http://www.ti.com/lit/pdf/spruhz6

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/include/asm/arch-omap5/i2c.h b/arch/arm/include/asm/arch-omap5/i2c.h
index d875cfe0b4fdd5418bcd81ee6c28e54619bbed09..2b55edf7f0c89628048aa9e56c84057603f94e8c 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/i2c.h
+++ b/arch/arm/include/asm/arch-omap5/i2c.h
@@ -14,9 +14,9 @@ struct i2c {
        unsigned short revnb_lo;        /* 0x00 */
        unsigned short res1;
        unsigned short revnb_hi;        /* 0x04 */
-       unsigned short res2[13];
-       unsigned short sysc;            /* 0x20 */
-       unsigned short res3;
+       unsigned short res2[5];
+       unsigned short sysc;            /* 0x10 */
+       unsigned short res3[9];
        unsigned short irqstatus_raw;   /* 0x24 */
        unsigned short res4;
        unsigned short stat;            /* 0x28 */