These pin mux settings are cared by the pinctrl drivers.
Remove the ad-hoc code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */
#endif
-#ifdef CONFIG_USB_EHCI
- sg_set_pinsel(53, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(54, 0, 8, 4); /* USB0OD -> USB0OD */
- sg_set_pinsel(55, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(56, 0, 8, 4); /* USB1OD -> USB1OD */
- /* sg_set_pinsel(67, 23, 8, 4); */ /* PCOE -> USB2VBUS */
- /* sg_set_pinsel(68, 23, 8, 4); */ /* PCWAIT -> USB2OD */
-#endif
-
tmp = readl(SG_IECTRL);
tmp |= 0x41;
writel(tmp, SG_IECTRL);
sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */
#endif
-#ifdef CONFIG_USB_EHCI
- sg_set_pinsel(184, 0, 4, 8); /* USB2VBUS -> USB2VBUS */
- sg_set_pinsel(185, 0, 4, 8); /* USB2OD -> USB2OD */
- sg_set_pinsel(187, 0, 4, 8); /* USB3VBUS -> USB3VBUS */
- sg_set_pinsel(188, 0, 4, 8); /* USB3OD -> USB3OD */
-#endif
-
writel(1, SG_LOADPINCTRL);
}
sg_set_pinsel(30, 0, 8, 4); /* NFD6_GB -> NFD6_GB */
sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */
#endif
-
-#ifdef CONFIG_USB_EHCI
- sg_set_pinsel(41, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(42, 0, 8, 4); /* USB0OD -> USB0OD */
- sg_set_pinsel(43, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(44, 0, 8, 4); /* USB1OD -> USB1OD */
- /* sg_set_pinsel(114, 1, 8, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */
- /* sg_set_pinsel(115, 1, 8, 4); */ /* RXD1 -> USB2OD */
-#endif
}