]> git.sur5r.net Git - u-boot/commitdiff
Merge branch 'master' of git://git.denx.de/u-boot-rockchip
authorTom Rini <trini@konsulko.com>
Fri, 18 Aug 2017 22:23:58 +0000 (18:23 -0400)
committerTom Rini <trini@konsulko.com>
Fri, 18 Aug 2017 22:23:58 +0000 (18:23 -0400)
arch/arm/dts/rk3399-evb.dts
arch/arm/dts/rk3399-firefly.dts
arch/arm/include/asm/arch-rockchip/cru_rk322x.h
arch/arm/mach-rockchip/rk322x-board.c
arch/arm/mach-rockchip/rk3399-board-spl.c
common/spl/Makefile
drivers/pinctrl/rockchip/pinctrl_rk322x.c

index bff00c328386fe43793a9524e36c176ae9e4a6cb..be0c6d98bd39945245552873c8cb8030c12771c0 100644 (file)
        rx_delay = <0x10>;
        status = "okay";
 };
-
-&gmac {
-        phy-supply = <&vcc_phy>;
-       phy-mode = "rgmii";
-       clock_in_out = "input";
-       snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
-       snps,reset-active-low;
-       snps,reset-delays-us = <0 10000 50000>;
-       assigned-clocks = <&cru SCLK_RMII_SRC>;
-       assigned-clock-parents = <&clkin_gmac>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&rgmii_pins>;
-       tx_delay = <0x10>;
-       rx_delay = <0x10>;
-       status = "okay";
-};
index 3d3f5079345a13f17441aff28d1ca67aad873c9f..31e3ba8a4742bb4fb862859e3808288016f42aa4 100644 (file)
        snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
        snps,reset-active-low;
        snps,reset-delays-us = <0 10000 50000>;
-       tx_delay = <0x28>;
-       rx_delay = <0x11>;
+       tx_delay = <0x33>;
+       rx_delay = <0x45>;
        status = "okay";
 };
 
index 2a2f804f675ea1d2c6bebb8dd6f256c989c2cbba..a7999ca5af4dc8d50aa6b44ee0b86f599d34da2d 100644 (file)
@@ -162,20 +162,17 @@ enum {
        /* CRU_CLKSEL11_CON */
        EMMC_PLL_SHIFT          = 12,
        EMMC_PLL_MASK           = 3 << EMMC_PLL_SHIFT,
-       EMMC_SEL_APLL           = 0,
-       EMMC_SEL_DPLL,
+       EMMC_SEL_CPLL           = 0,
        EMMC_SEL_GPLL,
        EMMC_SEL_24M,
        SDIO_PLL_SHIFT          = 10,
        SDIO_PLL_MASK           = 3 << SDIO_PLL_SHIFT,
-       SDIO_SEL_APLL           = 0,
-       SDIO_SEL_DPLL,
+       SDIO_SEL_CPLL           = 0,
        SDIO_SEL_GPLL,
        SDIO_SEL_24M,
        MMC0_PLL_SHIFT          = 8,
        MMC0_PLL_MASK           = 3 << MMC0_PLL_SHIFT,
-       MMC0_SEL_APLL           = 0,
-       MMC0_SEL_DPLL,
+       MMC0_SEL_CPLL           = 0,
        MMC0_SEL_GPLL,
        MMC0_SEL_24M,
        MMC0_DIV_SHIFT          = 0,
index 1e79c19309656cc76ba7b708975f4887cb117b19..c0ac2e9b56fc499245899fbc99c2f2e920881caa 100644 (file)
@@ -72,11 +72,13 @@ int board_init(void)
 
 int dram_init_banksize(void)
 {
-       /* Reserve 0x200000 for OPTEE */
-       gd->bd->bi_dram[0].start = 0x60000000;
+       gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
        gd->bd->bi_dram[0].size = 0x8400000;
-       gd->bd->bi_dram[1].start = 0x6a400000;
-       gd->bd->bi_dram[1].size = gd->ram_size - gd->bd->bi_dram[1].start;
+       /* Reserve 0x200000 for OPTEE */
+       gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+                               + gd->bd->bi_dram[0].size + 0x200000;
+       gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+                               + gd->ram_size - gd->bd->bi_dram[1].start;
 
        return 0;
 }
index a13b717bbd003f5913af3082664297a2bdbf3145..d6bf74f7ad7a35095231cf3c99d85c8efdef359a 100644 (file)
@@ -7,7 +7,6 @@
 #include <common.h>
 #include <debug_uart.h>
 #include <dm.h>
-#include <fdtdec.h>
 #include <ram.h>
 #include <spl.h>
 #include <asm/gpio.h>
index 112b3e6022f12590e48be0e97d89278a727a5133..fde0d09a5a9b151090464294ec04534b32e058f5 100644 (file)
@@ -12,9 +12,9 @@ ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
 obj-$(CONFIG_$(SPL_TPL_)BOOTROM_SUPPORT) += spl_bootrom.o
 obj-$(CONFIG_$(SPL_TPL_)LOAD_FIT) += spl_fit.o
-obj-$(CONFIG_$(SPL_TPL_)SPL_NOR_SUPPORT) += spl_nor.o
-obj-$(CONFIG_$(SPL_TPL_)SPL_XIP_SUPPORT) += spl_xip.o
-obj-$(CONFIG_$(SPL_TPL_)SPL_YMODEM_SUPPORT) += spl_ymodem.o
+obj-$(CONFIG_$(SPL_TPL_)NOR_SUPPORT) += spl_nor.o
+obj-$(CONFIG_$(SPL_TPL_)XIP_SUPPORT) += spl_xip.o
+obj-$(CONFIG_$(SPL_TPL_)YMODEM_SUPPORT) += spl_ymodem.o
 ifndef CONFIG_SPL_UBI
 obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += spl_nand.o
 obj-$(CONFIG_$(SPL_TPL_)ONENAND_SUPPORT) += spl_onenand.o
index 7aaf4b5801ad7a21bca90dd15c59a7b4009d4465..576b03739fa845b93eecae1ba56bd1b30fbe7836 100644 (file)
@@ -168,7 +168,7 @@ static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id)
                rk_clrsetreg(&grf->gpio1b_iomux,
                             GPIO1B6_MASK | GPIO1B7_MASK,
                             GPIO1B6_SDMMC_PWREN << GPIO1B6_SHIFT |
-                            GPIO1B7_SDMMC_CMD << GPIO1B6_SHIFT);
+                            GPIO1B7_SDMMC_CMD << GPIO1B7_SHIFT);
                rk_clrsetreg(&grf->gpio1c_iomux, 0xfff,
                             GPIO1C5_SDMMC_D3 << GPIO1C5_SHIFT |
                             GPIO1C4_SDMMC_D2 << GPIO1C4_SHIFT |
@@ -279,12 +279,12 @@ static int rk322x_pinctrl_probe(struct udevice *dev)
 }
 
 static const struct udevice_id rk322x_pinctrl_ids[] = {
-       { .compatible = "rockchip,rk322x-pinctrl" },
+       { .compatible = "rockchip,rk3228-pinctrl" },
        { }
 };
 
-U_BOOT_DRIVER(pinctrl_rk322x) = {
-       .name           = "pinctrl_rk322x",
+U_BOOT_DRIVER(pinctrl_rk3228) = {
+       .name           = "pinctrl_rk3228",
        .id             = UCLASS_PINCTRL,
        .of_match       = rk322x_pinctrl_ids,
        .priv_auto_alloc_size = sizeof(struct rk322x_pinctrl_priv),