phys_size_t fixed_sdram(void);
+int board_early_init_f (void)
+{
+#ifdef CONFIG_MMC
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->pmuxcr,
+ (MPC85xx_PMUXCR_SD_DATA |
+ MPC85xx_PMUXCR_SDHC_CD |
+ MPC85xx_PMUXCR_SDHC_WP));
+
+#endif
+ return 0;
+}
+
int checkboard (void)
{
printf ("Board: MPC8536DS, System ID: 0x%02x, "
#include <command.h>
#include <tsec.h>
#include <netdev.h>
+#include <fsl_esdhc.h>
#include <asm/cache.h>
#include <asm/io.h>
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
tsec_standard_init(bis);
#endif
+
return 0;
}
+
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_FSL_ESDHC
+ return fsl_esdhc_mmc_init(bis);
+#else
+ return 0;
+#endif
+}
uint gpindr; /* 0xe0050 - General-purpose input data register */
char res5[12];
uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
+#define MPC85xx_PMUXCR_SD_DATA 0x80000000
+#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
+#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
char res6[12];
uint devdisr; /* 0xe0070 - Device disable control */
#define MPC85xx_DEVDISR_PCI1 0x80000000
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_MMC 1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
/*
* Miscellaneous configurable options
*/