VERSION = 2015
PATCHLEVEL = 07
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*
Monitor commands can be included or excluded
from the build by using the #include files
<config_cmd_all.h> and #undef'ing unwanted
- commands, or using <config_cmd_default.h>
- and augmenting with additional #define's
- for wanted commands.
+ commands, or adding #define's for wanted commands.
The default command configuration includes all commands
except those marked below with a "*".
this is instead controlled by the value of
/config/load-environment.
+- Parallel Flash support:
+ CONFIG_SYS_NO_FLASH
+
+ Traditionally U-boot was run on systems with parallel NOR
+ flash. This option is used to disable support for parallel NOR
+ flash. This option should be defined if the board does not have
+ parallel flash.
+
+ If this option is not defined one of the generic flash drivers
+ (e.g. CONFIG_FLASH_CFI_DRIVER or CONFIG_ST_SMI) must be
+ selected or the board must provide an implementation of the
+ flash API (see include/flash.h).
+
- DataFlash Support:
CONFIG_HAS_DATAFLASH
Define this option to include a destructive SPI flash
test ('sf test').
- CONFIG_SPI_FLASH_BAR Ban/Extended Addr Reg
-
- Define this option to use the Bank addr/Extended addr
- support on SPI flashes which has size > 16Mbytes.
-
CONFIG_SF_DUAL_FLASH Dual flash memories
Define this option to use dual flash support where two flash
config AVR32
bool "AVR32 architecture"
select HAVE_GENERIC_BOARD
+ select SYS_GENERIC_BOARD
config BLACKFIN
bool "Blackfin architecture"
config SYS_ARCH
default "arc"
-config USE_PRIVATE_LIBGCC
- default y
-
config SYS_CPU
default "arcv1" if ISA_ARCOMPACT
default "arcv2" if ISA_ARCV2
#endif
#define ARC_BCR_DC_BUILD 0x72
#define ARC_BCR_SLC 0xce
-#define ARC_AUX_SLC_CONTROL 0x903
+#define ARC_AUX_SLC_CONFIG 0x901
+#define ARC_AUX_SLC_CTRL 0x903
#define ARC_AUX_SLC_FLUSH 0x904
#define ARC_AUX_SLC_INVALIDATE 0x905
+#define ARC_AUX_SLC_IVDL 0x910
+#define ARC_AUX_SLC_FLDL 0x912
#ifndef __ASSEMBLY__
/* Accessors for auxiliary registers */
#ifndef __ASSEMBLY__
-#ifdef CONFIG_ISA_ARCV2
-void slc_enable(void);
-void slc_disable(void);
-void slc_flush(void);
-void slc_invalidate(void);
-#endif
+void cache_init(void);
#endif /* __ASSEMBLY__ */
hang();
}
+__weak void smp_set_core_boot_addr(unsigned long addr, int corenr) {}
+__weak void smp_kick_all_cpus(void) {}
+
/* Subcommand: GO */
static void boot_jump_linux(bootm_headers_t *images, int flag)
{
r2 = (unsigned int)getenv("bootargs");
}
+ smp_set_core_boot_addr((unsigned long)kernel_entry, -1);
+ smp_kick_all_cpus();
+
if (!fake)
kernel_entry(r0, 0, r2);
}
*/
#include <config.h>
+#include <linux/compiler.h>
+#include <linux/kernel.h>
#include <asm/arcregs.h>
#include <asm/cache.h>
+#define CACHE_LINE_MASK (~(CONFIG_SYS_CACHELINE_SIZE - 1))
+
/* Bit values in IC_CTRL */
#define IC_CTRL_CACHE_DISABLE (1 << 0)
#define CACHE_VER_NUM_MASK 0xF
#define SLC_CTRL_SB (1 << 2)
+#define OP_INV 0x1
+#define OP_FLUSH 0x2
+#define OP_INV_IC 0x3
+
+#ifdef CONFIG_ISA_ARCV2
+/*
+ * By default that variable will fall into .bss section.
+ * But .bss section is not relocated and so it will be initilized before
+ * relocation but will be used after being zeroed.
+ */
+int slc_line_sz __section(".data");
+int slc_exists __section(".data");
+
+static unsigned int __before_slc_op(const int op)
+{
+ unsigned int reg = reg;
+
+ if (op == OP_INV) {
+ /*
+ * IM is set by default and implies Flush-n-inv
+ * Clear it here for vanilla inv
+ */
+ reg = read_aux_reg(ARC_AUX_SLC_CTRL);
+ write_aux_reg(ARC_AUX_SLC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
+ }
+
+ return reg;
+}
+
+static void __after_slc_op(const int op, unsigned int reg)
+{
+ if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
+ while (read_aux_reg(ARC_AUX_SLC_CTRL) &
+ DC_CTRL_FLUSH_STATUS)
+ ;
+
+ /* Switch back to default Invalidate mode */
+ if (op == OP_INV)
+ write_aux_reg(ARC_AUX_SLC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
+}
+
+static inline void __slc_line_loop(unsigned long paddr, unsigned long sz,
+ const int op)
+{
+ unsigned int aux_cmd;
+ int num_lines;
+
+#define SLC_LINE_MASK (~(slc_line_sz - 1))
+
+ aux_cmd = op & OP_INV ? ARC_AUX_SLC_IVDL : ARC_AUX_SLC_FLDL;
+
+ sz += paddr & ~SLC_LINE_MASK;
+ paddr &= SLC_LINE_MASK;
+
+ num_lines = DIV_ROUND_UP(sz, slc_line_sz);
+
+ while (num_lines-- > 0) {
+ write_aux_reg(aux_cmd, paddr);
+ paddr += slc_line_sz;
+ }
+}
+
+static inline void __slc_entire_op(const int cacheop)
+{
+ int aux;
+ unsigned int ctrl_reg = __before_slc_op(cacheop);
+
+ if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
+ aux = ARC_AUX_SLC_INVALIDATE;
+ else
+ aux = ARC_AUX_SLC_FLUSH;
+
+ write_aux_reg(aux, 0x1);
+
+ __after_slc_op(cacheop, ctrl_reg);
+}
+
+static inline void __slc_line_op(unsigned long paddr, unsigned long sz,
+ const int cacheop)
+{
+ unsigned int ctrl_reg = __before_slc_op(cacheop);
+ __slc_line_loop(paddr, sz, cacheop);
+ __after_slc_op(cacheop, ctrl_reg);
+}
+#else
+#define __slc_entire_op(cacheop)
+#define __slc_line_op(paddr, sz, cacheop)
+#endif
+
+static inline int icache_exists(void)
+{
+ /* Check if Instruction Cache is available */
+ if (read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK)
+ return 1;
+ else
+ return 0;
+}
+
+static inline int dcache_exists(void)
+{
+ /* Check if Data Cache is available */
+ if (read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK)
+ return 1;
+ else
+ return 0;
+}
+
+void cache_init(void)
+{
+#ifdef CONFIG_ISA_ARCV2
+ /* Check if System-Level Cache (SLC) is available */
+ if (read_aux_reg(ARC_BCR_SLC) & CACHE_VER_NUM_MASK) {
+#define LSIZE_OFFSET 4
+#define LSIZE_MASK 3
+ if (read_aux_reg(ARC_AUX_SLC_CONFIG) &
+ (LSIZE_MASK << LSIZE_OFFSET))
+ slc_line_sz = 64;
+ else
+ slc_line_sz = 128;
+ slc_exists = 1;
+ } else {
+ slc_exists = 0;
+ }
+#endif
+}
+
int icache_status(void)
{
- /* If no cache in CPU exit immediately */
- if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
+ if (!icache_exists())
return 0;
- return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
- IC_CTRL_CACHE_DISABLE;
+ if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE)
+ return 0;
+ else
+ return 1;
}
void icache_enable(void)
{
- /* If no cache in CPU exit immediately */
- if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
- return;
-
- write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
- ~IC_CTRL_CACHE_DISABLE);
+ if (icache_exists())
+ write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
+ ~IC_CTRL_CACHE_DISABLE);
}
void icache_disable(void)
{
- /* If no cache in CPU exit immediately */
- if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
- return;
-
- write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
- IC_CTRL_CACHE_DISABLE);
+ if (icache_exists())
+ write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
+ IC_CTRL_CACHE_DISABLE);
}
+#ifndef CONFIG_SYS_DCACHE_OFF
void invalidate_icache_all(void)
{
- /* If no cache in CPU exit immediately */
- if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
- return;
-
/* Any write to IC_IVIC register triggers invalidation of entire I$ */
- write_aux_reg(ARC_AUX_IC_IVIC, 1);
+ if (icache_status()) {
+ write_aux_reg(ARC_AUX_IC_IVIC, 1);
+ read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
+ }
}
+#else
+void invalidate_icache_all(void)
+{
+}
+#endif
int dcache_status(void)
{
- /* If no cache in CPU exit immediately */
- if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+ if (!dcache_exists())
return 0;
- return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
- DC_CTRL_CACHE_DISABLE;
+ if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE)
+ return 0;
+ else
+ return 1;
}
void dcache_enable(void)
{
- /* If no cache in CPU exit immediately */
- if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+ if (!dcache_exists())
return;
write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
void dcache_disable(void)
{
- /* If no cache in CPU exit immediately */
- if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+ if (!dcache_exists())
return;
write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
DC_CTRL_CACHE_DISABLE);
}
-void flush_dcache_all(void)
-{
- /* If no cache in CPU exit immediately */
- if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
- return;
-
- /* Do flush of entire cache */
- write_aux_reg(ARC_AUX_DC_FLSH, 1);
-
- /* Wait flush end */
- while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
- ;
-}
-
#ifndef CONFIG_SYS_DCACHE_OFF
-static void dcache_flush_line(unsigned addr)
+/*
+ * Common Helper for Line Operations on {I,D}-Cache
+ */
+static inline void __cache_line_loop(unsigned long paddr, unsigned long sz,
+ const int cacheop)
{
+ unsigned int aux_cmd;
#if (CONFIG_ARC_MMU_VER == 3)
- write_aux_reg(ARC_AUX_DC_PTAG, addr);
+ unsigned int aux_tag;
#endif
- write_aux_reg(ARC_AUX_DC_FLDL, addr);
+ int num_lines;
- /* Wait flush end */
- while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
- ;
-
-#ifndef CONFIG_SYS_ICACHE_OFF
- /*
- * Invalidate I$ for addresses range just flushed from D$.
- * If we try to execute data flushed above it will be valid/correct
- */
+ if (cacheop == OP_INV_IC) {
+ aux_cmd = ARC_AUX_IC_IVIL;
#if (CONFIG_ARC_MMU_VER == 3)
- write_aux_reg(ARC_AUX_IC_PTAG, addr);
+ aux_tag = ARC_AUX_IC_PTAG;
#endif
- write_aux_reg(ARC_AUX_IC_IVIL, addr);
-#endif /* CONFIG_SYS_ICACHE_OFF */
-}
-#endif /* CONFIG_SYS_DCACHE_OFF */
-
-void flush_dcache_range(unsigned long start, unsigned long end)
-{
-#ifndef CONFIG_SYS_DCACHE_OFF
- unsigned int addr;
+ } else {
+ /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
+ aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
+#if (CONFIG_ARC_MMU_VER == 3)
+ aux_tag = ARC_AUX_DC_PTAG;
+#endif
+ }
- start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
- end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+ sz += paddr & ~CACHE_LINE_MASK;
+ paddr &= CACHE_LINE_MASK;
- for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE)
- dcache_flush_line(addr);
-#endif /* CONFIG_SYS_DCACHE_OFF */
-}
+ num_lines = DIV_ROUND_UP(sz, CONFIG_SYS_CACHELINE_SIZE);
-void invalidate_dcache_range(unsigned long start, unsigned long end)
-{
-#ifndef CONFIG_SYS_DCACHE_OFF
- unsigned int addr;
-
- start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
- end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
-
- for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
+ while (num_lines-- > 0) {
#if (CONFIG_ARC_MMU_VER == 3)
- write_aux_reg(ARC_AUX_DC_PTAG, addr);
+ write_aux_reg(aux_tag, paddr);
#endif
- write_aux_reg(ARC_AUX_DC_IVDL, addr);
+ write_aux_reg(aux_cmd, paddr);
+ paddr += CONFIG_SYS_CACHELINE_SIZE;
}
-#endif /* CONFIG_SYS_DCACHE_OFF */
}
-void invalidate_dcache_all(void)
+static unsigned int __before_dc_op(const int op)
{
- /* If no cache in CPU exit immediately */
- if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
- return;
+ unsigned int reg;
+
+ if (op == OP_INV) {
+ /*
+ * IM is set by default and implies Flush-n-inv
+ * Clear it here for vanilla inv
+ */
+ reg = read_aux_reg(ARC_AUX_DC_CTRL);
+ write_aux_reg(ARC_AUX_DC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
+ }
- /* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
- write_aux_reg(ARC_AUX_DC_IVDC, 1);
+ return reg;
}
-void flush_cache(unsigned long start, unsigned long size)
+static void __after_dc_op(const int op, unsigned int reg)
{
- flush_dcache_range(start, start + size);
+ if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
+ while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
+ ;
+
+ /* Switch back to default Invalidate mode */
+ if (op == OP_INV)
+ write_aux_reg(ARC_AUX_DC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
}
-#ifdef CONFIG_ISA_ARCV2
-void slc_enable(void)
+static inline void __dc_entire_op(const int cacheop)
{
- /* If SLC ver = 0, no SLC present in CPU */
- if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
- return;
+ int aux;
+ unsigned int ctrl_reg = __before_dc_op(cacheop);
- write_aux_reg(ARC_AUX_SLC_CONTROL,
- read_aux_reg(ARC_AUX_SLC_CONTROL) & ~1);
-}
+ if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
+ aux = ARC_AUX_DC_IVDC;
+ else
+ aux = ARC_AUX_DC_FLSH;
-void slc_disable(void)
-{
- /* If SLC ver = 0, no SLC present in CPU */
- if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
- return;
+ write_aux_reg(aux, 0x1);
- write_aux_reg(ARC_AUX_SLC_CONTROL,
- read_aux_reg(ARC_AUX_SLC_CONTROL) | 1);
+ __after_dc_op(cacheop, ctrl_reg);
}
-void slc_flush(void)
+static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
+ const int cacheop)
{
- /* If SLC ver = 0, no SLC present in CPU */
- if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
- return;
+ unsigned int ctrl_reg = __before_dc_op(cacheop);
+ __cache_line_loop(paddr, sz, cacheop);
+ __after_dc_op(cacheop, ctrl_reg);
+}
+#else
+#define __dc_entire_op(cacheop)
+#define __dc_line_op(paddr, sz, cacheop)
+#endif /* !CONFIG_SYS_DCACHE_OFF */
- write_aux_reg(ARC_AUX_SLC_FLUSH, 1);
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+ __dc_line_op(start, end - start, OP_INV);
+#ifdef CONFIG_ISA_ARCV2
+ if (slc_exists)
+ __slc_line_op(start, end - start, OP_INV);
+#endif
+}
- /* Wait flush end */
- while (read_aux_reg(ARC_AUX_SLC_CONTROL) & SLC_CTRL_SB)
- ;
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+ __dc_line_op(start, end - start, OP_FLUSH);
+#ifdef CONFIG_ISA_ARCV2
+ if (slc_exists)
+ __slc_line_op(start, end - start, OP_FLUSH);
+#endif
}
-void slc_invalidate(void)
+void flush_cache(unsigned long start, unsigned long size)
{
- /* If SLC ver = 0, no SLC present in CPU */
- if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
- return;
+ flush_dcache_range(start, start + size);
+}
- write_aux_reg(ARC_AUX_SLC_INVALIDATE, 1);
+void invalidate_dcache_all(void)
+{
+ __dc_entire_op(OP_INV);
+#ifdef CONFIG_ISA_ARCV2
+ if (slc_exists)
+ __slc_entire_op(OP_INV);
+#endif
}
-#endif /* CONFIG_ISA_ARCV2 */
+void flush_dcache_all(void)
+{
+ __dc_entire_op(OP_FLUSH);
+#ifdef CONFIG_ISA_ARCV2
+ if (slc_exists)
+ __slc_entire_op(OP_FLUSH);
+#endif
+}
gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ cache_init();
+
return 0;
}
int init_cache_f_r(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
- icache_enable();
- /* Make sure no stale entries persist from before we disabled cache */
- invalidate_icache_all();
-#endif
-
#ifndef CONFIG_SYS_DCACHE_OFF
- dcache_enable();
- /* Make sure no stale entries persist from before we disabled cache */
- invalidate_dcache_all();
+ flush_dcache_all();
#endif
return 0;
}
/* Setup interrupt vector base that matches "__text_start" */
sr __ivt_start, [ARC_AUX_INTR_VEC_BASE]
- /* Setup stack- and frame-pointers */
- mov %sp, CONFIG_SYS_INIT_SP_ADDR
- mov %fp, %sp
+ ; Disable/enable I-cache according to configuration
+ lr r5, [ARC_BCR_IC_BUILD]
+ breq r5, 0, 1f ; I$ doesn't exist
+ lr r5, [ARC_AUX_IC_CTRL]
+#ifndef CONFIG_SYS_ICACHE_OFF
+ bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
+#else
+ bset r5, r5, 0 ; I$ exists, but is not used
+#endif
+ sr r5, [ARC_AUX_IC_CTRL]
+
+1:
+ ; Disable/enable D-cache according to configuration
+ lr r5, [ARC_BCR_DC_BUILD]
+ breq r5, 0, 1f ; D$ doesn't exist
+ lr r5, [ARC_AUX_DC_CTRL]
+ bclr r5, r5, 6 ; Invalidate (discard w/o wback)
+#ifndef CONFIG_SYS_DCACHE_OFF
+ bclr r5, r5, 0 ; Enable (+Inv)
+#else
+ bset r5, r5, 0 ; Disable (+Inv)
+#endif
+ sr r5, [ARC_AUX_DC_CTRL]
- /* Unconditionally disable caches */
+1:
#ifdef CONFIG_ISA_ARCV2
- bl slc_flush
- bl slc_disable
+ ; Disable System-Level Cache (SLC)
+ lr r5, [ARC_BCR_SLC]
+ breq r5, 0, 1f ; SLC doesn't exist
+ lr r5, [ARC_AUX_SLC_CTRL]
+ bclr r5, r5, 6 ; Invalidate (discard w/o wback)
+ bclr r5, r5, 0 ; Enable (+Inv)
+ sr r5, [ARC_AUX_SLC_CTRL]
+
+1:
#endif
- bl flush_dcache_all
- bl dcache_disable
- bl icache_disable
+
+ /* Setup stack- and frame-pointers */
+ mov %sp, CONFIG_SYS_INIT_SP_ADDR
+ mov %fp, %sp
/* Allocate and zero GD, update SP */
mov %r0, %sp
select CPU_V7
select SUPPORT_SPL
-config TARGET_DXR2
- bool "Support dxr2"
+config TARGET_THUBAN
+ bool "Support thuban"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_RASTABAN
+ bool "Support rastaban"
select CPU_V7
select SUPPORT_SPL
select DM_SERIAL
select DM_GPIO
+config TARGET_AM335X_BALTOS
+ bool "Support am335x_baltos"
+ select CPU_V7
+ select SUPPORT_SPL
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
config TARGET_AM335X_EVM
bool "Support am335x_evm"
select CPU_V7
bool "Xilinx Zynq Platform"
select CPU_V7
select SUPPORT_SPL
+ select OF_CONTROL
+ select SPL_DISABLE_OF_CONTROL
select DM
+ select DM_SPI
+ select DM_SPI_FLASH
config TARGET_XILINX_ZYNQMP
bool "Support Xilinx ZynqMP Platform"
source "board/ttcontrol/vision2/Kconfig"
source "board/udoo/Kconfig"
source "board/vpac270/Kconfig"
+source "board/vscom/baltos/Kconfig"
source "board/wandboard/Kconfig"
source "board/warp/Kconfig"
source "board/woodburn/Kconfig"
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
- /* Perform hardware leveling. */
- udelay(1000);
- writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
- 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
- writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
- 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
-
- writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
-
- /* Enable read leveling */
- writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
-
- /*
- * Enable full read and write leveling. Wait for read and write
- * leveling bit to clear RDWRLVLFULL_START bit 31
- */
- while((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) != 0)
- ;
-
- /* Check the timeout register to see if leveling is complete */
- if((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
- puts("DDR3 H/W leveling incomplete with errors\n");
-
- if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
+ /* Perform hardware leveling for DDR3 */
+ if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
+ udelay(1000);
+ writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
+ 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
+ writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
+ 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
+
+ writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
+
+ /* Enable read leveling */
+ writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+
+ /*
+ * Enable full read and write leveling. Wait for read and write
+ * leveling bit to clear RDWRLVLFULL_START bit 31
+ */
+ while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000)
+ != 0)
+ ;
+
+ /* Check the timeout register to see if leveling is complete */
+ if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
+ puts("DDR3 H/W leveling incomplete with errors\n");
+
+ } else {
+ /* DDR2 */
configure_mr(nr, 0);
configure_mr(nr, 1);
}
writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
}
+/*
+ * Configure EXT PHY registers for software leveling
+ */
+static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
+{
+ u32 *ext_phy_ctrl_base = 0;
+ u32 *emif_ext_phy_ctrl_base = 0;
+ __maybe_unused const u32 *ext_phy_ctrl_const_regs;
+ u32 i = 0;
+ __maybe_unused u32 size;
+
+ ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
+ emif_ext_phy_ctrl_base =
+ (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+
+ /* Configure external phy control timing registers */
+ for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+ writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+ /* Update shadow registers */
+ writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+ }
+
+#ifdef CONFIG_AM43XX
+ /*
+ * External phy 6-24 registers do not change with ddr frequency.
+ * These only need to be set on DDR2 on AM43xx.
+ */
+ emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
+
+ if (!size)
+ return;
+
+ for (i = 0; i < size; i++) {
+ writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+ /* Update shadow registers */
+ writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+ }
+#endif
+}
+
/*
* Configure EXT PHY registers for hardware leveling
*/
-static void ext_phy_settings(const struct emif_regs *regs, int nr)
+static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
{
/*
* Enable hardware leveling on the EMIF. For details about these
writel(regs->emif_ddr_phy_ctlr_1,
&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
- if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5)
- ext_phy_settings(regs, nr);
+ if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) {
+ if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
+ ext_phy_settings_hwlvl(regs, nr);
+ else
+ ext_phy_settings_swlvl(regs, nr);
+ }
}
/**
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
- /* Allow EMIF to control DDR_RESET */
- writel(0x00000000, &ddrctrl->ddrioctrl);
+ if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
+ /* Allow EMIF to control DDR_RESET */
+ writel(0x00000000, &ddrctrl->ddrioctrl);
#endif
/* Program EMIF instance */
config SYS_SOC
default "exynos"
-config DM_USB
- default y
-
source "board/samsung/smdkv310/Kconfig"
source "board/samsung/trats/Kconfig"
source "board/samsung/universal_c210/Kconfig"
{
u32 temp;
const struct dpll_params *params;
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
debug("setup_dplls\n");
* Core DPLL will be locked after setting up EMIF
* using the FREQ_UPDATE method(freq_update_core())
*/
- if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
+ if (emif_sdram_type(readl(&emif->emif_sdram_config)) ==
+ EMIF_SDRAM_TYPE_LPDDR2)
do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
DPLL_NO_LOCK, "core");
else
return val;
}
+#ifdef CONFIG_IODELAY_RECALIBRATION
+void __weak recalibrate_iodelay(void)
+{
+}
+#endif
+
/*
* Setup the voltages for the main SoC core power domains.
* We start with the maximum voltages allowed here, as set in the corresponding
debug("cor: %d\n", vcores->core.value);
do_scale_vcore(vcores->core.addr, vcores->core.value, vcores->core.pmic);
+ /*
+ * IO delay recalibration should be done immediately after
+ * adjusting AVS voltages for VDD_CORE_L.
+ * Respective boards should call __recalibrate_iodelay()
+ * with proper mux, virtual and manual mode configurations.
+ */
+#ifdef CONFIG_IODELAY_RECALIBRATION
+ recalibrate_iodelay();
+#endif
+
debug("mpu: %d\n", vcores->mpu.value);
do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic);
/* Configure MPU ABB LDO after scale */
val = optimize_vcore_voltage(&vcores->core);
do_scale_vcore(vcores->core.addr, val, vcores->core.pmic);
+ /*
+ * IO delay recalibration should be done immediately after
+ * adjusting AVS voltages for VDD_CORE_L.
+ * Respective boards should call __recalibrate_iodelay()
+ * with proper mux, virtual and manual mode configurations.
+ */
+#ifdef CONFIG_IODELAY_RECALIBRATION
+ recalibrate_iodelay();
+#endif
+
val = optimize_vcore_voltage(&vcores->mpu);
do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
__udelay(130);
}
-static void ddr3_leveling(u32 base, const struct emif_regs *regs)
+static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
{
- if (is_omap54xx())
- omap5_ddr3_leveling(base, regs);
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+ u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
+ u32 reg, i;
+
+ emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];
+
+ /* Update PHY_REG_RDDQS_RATIO */
+ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
+ for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
+ reg = readl(emif_phy_status++);
+ writel(reg, emif_ext_phy_ctrl_reg++);
+ writel(reg, emif_ext_phy_ctrl_reg++);
+ }
+
+ /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
+ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
+ for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
+ reg = readl(emif_phy_status++);
+ writel(reg, emif_ext_phy_ctrl_reg++);
+ writel(reg, emif_ext_phy_ctrl_reg++);
+ }
+
+ /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
+ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
+ for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
+ reg = readl(emif_phy_status++);
+ writel(reg, emif_ext_phy_ctrl_reg++);
+ writel(reg, emif_ext_phy_ctrl_reg++);
+ }
+
+ /* Disable Leveling */
+ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+ writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
}
-static void ddr3_init(u32 base, const struct emif_regs *regs)
+static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ /* Clear Error Status */
+ clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36,
+ EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
+ EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
+
+ clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw,
+ EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
+ EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
+
+ /* Disable refreshed before leveling */
+ clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT,
+ EMIF_REG_INITREF_DIS_SHIFT);
+
+ /* Start Full leveling */
+ writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
+
+ __udelay(300);
+
+ /* Check for leveling timeout */
+ if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) {
+ printf("Leveling timeout on EMIF%d\n", emif_num(base));
+ return;
+ }
+
+ /* Enable refreshes after leveling */
+ clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT);
+
+ debug("HW leveling success\n");
+ /*
+ * Update slave ratios in EXT_PHY_CTRLx registers
+ * as per HW leveling output
+ */
+ update_hwleveling_output(base, regs);
+}
+
+static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ if (warm_reset())
+ emif_reset_phy(base);
+ do_ext_phy_settings(base, regs);
+
+ writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
+ &emif->emif_sdram_ref_ctrl);
+ /* Update timing registers */
+ writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
+ writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
+ writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
+
+ writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config);
+ writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
+ writel(regs->zq_config, &emif->emif_zq_config);
+ writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
+ writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
+ writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
+
+ writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+ writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh);
+
+ writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
+
+ writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
+ writel(regs->sdram_config_init, &emif->emif_sdram_config);
+
+ __udelay(1000);
+
+ writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
+
+ if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK)
+ dra7_ddr3_leveling(base, regs);
+}
+
+static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
- /*
- * The same sequence should work on OMAP5432 as well. But strange that
- * it is not working
- */
- if (is_dra7xx()) {
- do_ext_phy_settings(base, regs);
- writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
- writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
- writel(regs->sdram_config_init, &emif->emif_sdram_config);
- } else {
- writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
- writel(regs->sdram_config_init, &emif->emif_sdram_config);
- do_ext_phy_settings(base, regs);
- }
+ writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
+ writel(regs->sdram_config_init, &emif->emif_sdram_config);
+ do_ext_phy_settings(base, regs);
- /* enable leveling */
writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
+ omap5_ddr3_leveling(base, regs);
+}
- ddr3_leveling(base, regs);
+static void ddr3_init(u32 base, const struct emif_regs *regs)
+{
+ if (is_omap54xx())
+ omap5_ddr3_init(base, regs);
+ else
+ dra7_ddr3_init(base, regs);
}
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
* Changing the timing registers in EMIF can happen(going from one
* OPP to another)
*/
- if (!(in_sdram || warm_reset())) {
- if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
+ if (!in_sdram && (!warm_reset() || is_dra7xx())) {
+ if (emif_sdram_type(regs->sdram_config) ==
+ EMIF_SDRAM_TYPE_LPDDR2)
lpddr2_init(base, regs);
else
ddr3_init(base, regs);
}
- if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
+ if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
+ EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
set_lpmode_selfrefresh(base);
emif_reset_phy(base);
- ddr3_leveling(base, regs);
+ omap5_ddr3_leveling(base, regs);
}
/* Write to the shadow registers */
void sdram_init(void)
{
u32 in_sdram, size_prog, size_detect;
- u32 sdram_type = emif_sdram_type();
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+ u32 sdram_type = emif_sdram_type(emif->emif_sdram_config);
debug(">>sdram_init()\n");
obj-y += prcm-regs.o
obj-y += hw_data.o
obj-y += abb.o
+obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o
--- /dev/null
+/*
+ * (C) Copyright 2015
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/utils.h>
+#include <asm/arch/dra7xx_iodelay.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mux_dra7xx.h>
+#include <asm/omap_common.h>
+
+static int isolate_io(u32 isolate)
+{
+ if (isolate) {
+ clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ,
+ SDCARD_PWRDNZ);
+ clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ,
+ SDCARD_BIAS_PWRDNZ);
+ }
+
+ /* Override control on ISOCLKIN signal to IO pad ring. */
+ clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK,
+ PMCTRL_ISOCLK_OVERRIDE_CTRL);
+ if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK, PMCTRL_ISOCLK_STATUS_MASK,
+ (u32 *)(*prcm)->prm_io_pmctrl, LDELAY))
+ return ERR_DEISOLATE_IO << isolate;
+
+ /* Isolate/Deisolate IO */
+ clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK,
+ isolate << CTRL_ISOLATE_SHIFT);
+ /* Dummy read to add delay t > 10ns */
+ readl((*ctrl)->ctrl_core_sma_sw_0);
+
+ /* Return control on ISOCLKIN to hardware */
+ clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK,
+ PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL);
+ if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK,
+ 0 << PMCTRL_ISOCLK_STATUS_SHIFT,
+ (u32 *)(*prcm)->prm_io_pmctrl, LDELAY))
+ return ERR_DEISOLATE_IO << isolate;
+
+ return 0;
+}
+
+static int calibrate_iodelay(u32 base)
+{
+ u32 reg;
+
+ /* Configure REFCLK period */
+ reg = readl(base + CFG_REG_2_OFFSET);
+ reg &= ~CFG_REG_REFCLK_PERIOD_MASK;
+ reg |= CFG_REG_REFCLK_PERIOD;
+ writel(reg, base + CFG_REG_2_OFFSET);
+
+ /* Initiate Calibration */
+ clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_CALIB_STRT_MASK,
+ CFG_REG_CALIB_STRT << CFG_REG_CALIB_STRT_SHIFT);
+ if (!wait_on_value(CFG_REG_CALIB_STRT_MASK, CFG_REG_CALIB_END,
+ (u32 *)(base + CFG_REG_0_OFFSET), LDELAY))
+ return ERR_CALIBRATE_IODELAY;
+
+ return 0;
+}
+
+static int update_delay_mechanism(u32 base)
+{
+ /* Initiate the reload of calibrated values. */
+ clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_ROM_READ_MASK,
+ CFG_REG_ROM_READ_START);
+ if (!wait_on_value(CFG_REG_ROM_READ_MASK, CFG_REG_ROM_READ_END,
+ (u32 *)(base + CFG_REG_0_OFFSET), LDELAY))
+ return ERR_UPDATE_DELAY;
+
+ return 0;
+}
+
+static u32 calculate_delay(u32 base, u16 offset, u16 den)
+{
+ u16 refclk_period, dly_cnt, ref_cnt;
+ u32 reg, q, r;
+
+ refclk_period = readl(base + CFG_REG_2_OFFSET) &
+ CFG_REG_REFCLK_PERIOD_MASK;
+
+ reg = readl(base + offset);
+ dly_cnt = (reg & CFG_REG_DLY_CNT_MASK) >> CFG_REG_DLY_CNT_SHIFT;
+ ref_cnt = (reg & CFG_REG_REF_CNT_MASK) >> CFG_REG_REF_CNT_SHIFT;
+
+ if (!dly_cnt || !den)
+ return 0;
+
+ /*
+ * To avoid overflow and integer truncation, delay value
+ * is calculated as quotient + remainder.
+ */
+ q = 5 * ((ref_cnt * refclk_period) / (dly_cnt * den));
+ r = (10 * ((ref_cnt * refclk_period) % (dly_cnt * den))) /
+ (2 * dly_cnt * den);
+
+ return q + r;
+}
+
+static u32 get_cfg_reg(u16 a_delay, u16 g_delay, u32 cpde, u32 fpde)
+{
+ u32 g_delay_coarse, g_delay_fine;
+ u32 a_delay_coarse, a_delay_fine;
+ u32 c_elements, f_elements;
+ u32 total_delay, reg = 0;
+
+ g_delay_coarse = g_delay / 920;
+ g_delay_fine = ((g_delay % 920) * 10) / 60;
+
+ a_delay_coarse = a_delay / cpde;
+ a_delay_fine = ((a_delay % cpde) * 10) / fpde;
+
+ c_elements = g_delay_coarse + a_delay_coarse;
+ f_elements = (g_delay_fine + a_delay_fine) / 10;
+
+ if (f_elements > 22) {
+ total_delay = c_elements * cpde + f_elements * fpde;
+
+ c_elements = total_delay / cpde;
+ f_elements = (total_delay % cpde) / fpde;
+ }
+
+ reg = (c_elements << CFG_X_COARSE_DLY_SHIFT) & CFG_X_COARSE_DLY_MASK;
+ reg |= (f_elements << CFG_X_FINE_DLY_SHIFT) & CFG_X_FINE_DLY_MASK;
+ reg |= CFG_X_SIGNATURE << CFG_X_SIGNATURE_SHIFT;
+ reg |= CFG_X_LOCK << CFG_X_LOCK_SHIFT;
+
+ return reg;
+}
+
+static int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
+ int niodelays)
+{
+ struct iodelay_cfg_entry *iodelay = (struct iodelay_cfg_entry *)array;
+ u32 reg, cpde, fpde, i;
+
+ if (!niodelays)
+ return 0;
+
+ cpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_3_OFFSET,
+ 88);
+ if (!cpde)
+ return ERR_CPDE;
+
+ fpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_4_OFFSET,
+ 264);
+ if (!fpde)
+ return ERR_FPDE;
+
+ for (i = 0; i < niodelays; i++, iodelay++) {
+ reg = get_cfg_reg(iodelay->a_delay, iodelay->g_delay, cpde,
+ fpde);
+ writel(reg, base + iodelay->offset);
+ }
+
+ return 0;
+}
+
+void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
+ struct iodelay_cfg_entry const *iodelay,
+ int niodelays)
+{
+ int ret = 0;
+
+ /* IO recalibration should be done only from SRAM */
+ if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
+ puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
+ return;
+ }
+
+ /* unlock IODELAY CONFIG registers */
+ writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base +
+ CFG_REG_8_OFFSET);
+
+ ret = calibrate_iodelay((*ctrl)->iodelay_config_base);
+ if (ret)
+ goto err;
+
+ ret = isolate_io(ISOLATE_IO);
+ if (ret)
+ goto err;
+
+ ret = update_delay_mechanism((*ctrl)->iodelay_config_base);
+ if (ret)
+ goto err;
+
+ /* Configure Mux settings */
+ do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);
+
+ /* Configure Manual IO timing modes */
+ ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
+ if (ret)
+ goto err;
+
+ ret = isolate_io(DEISOLATE_IO);
+
+err:
+ /* lock IODELAY CONFIG registers */
+ writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base +
+ CFG_REG_8_OFFSET);
+ /*
+ * UART cannot be used during IO recalibration sequence as IOs are in
+ * isolation. So error handling and debug prints are done after
+ * complete IO delay recalibration sequence
+ */
+ switch (ret) {
+ case ERR_CALIBRATE_IODELAY:
+ puts("IODELAY: IO delay calibration sequence failed\n");
+ break;
+ case ERR_ISOLATE_IO:
+ puts("IODELAY: Isolation of Device IOs failed\n");
+ break;
+ case ERR_UPDATE_DELAY:
+ puts("IODELAY: Delay mechanism update with new calibrated values failed\n");
+ break;
+ case ERR_DEISOLATE_IO:
+ puts("IODELAY: De-isolation of Device IOs failed\n");
+ break;
+ case ERR_CPDE:
+ puts("IODELAY: CPDE calculation failed\n");
+ break;
+ case ERR_FPDE:
+ puts("IODELAY: FPDE calculation failed\n");
+ break;
+ default:
+ debug("IODELAY: IO delay recalibration successfully completed\n");
+ }
+}
void enable_basic_uboot_clocks(void)
{
u32 const clk_domains_essential[] = {
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+ (*prcm)->cm_ipu_clkstctrl,
+#endif
0
};
(*prcm)->cm_l4per_i2c2_clkctrl,
(*prcm)->cm_l4per_i2c3_clkctrl,
(*prcm)->cm_l4per_i2c4_clkctrl,
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+ (*prcm)->cm_ipu_i2c5_clkctrl,
+#else
(*prcm)->cm_l4per_i2c5_clkctrl,
+#endif
(*prcm)->cm_l3init_hsusbhost_clkctrl,
(*prcm)->cm_l3init_fsusb_clkctrl,
0
.ctrl_ddrch = 0x40404040,
.ctrl_lpddr2ch = 0x40404040,
.ctrl_ddr3ch = 0x80808080,
- .ctrl_ddrio_0 = 0xA2084210,
- .ctrl_ddrio_1 = 0x84210840,
+ .ctrl_ddrio_0 = 0x00094A40,
+ .ctrl_ddrio_1 = 0x04A52000,
.ctrl_ddrio_2 = 0x84210000,
.ctrl_emif_sdram_config_ext = 0x0001C1A7,
.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
.ctrl_ddrch = 0x40404040,
.ctrl_lpddr2ch = 0x40404040,
.ctrl_ddr3ch = 0x60606080,
- .ctrl_ddrio_0 = 0xA2084210,
- .ctrl_ddrio_1 = 0x84210840,
+ .ctrl_ddrio_0 = 0x00094A40,
+ .ctrl_ddrio_1 = 0x04A52000,
.ctrl_ddrio_2 = 0x84210000,
.ctrl_emif_sdram_config_ext = 0x0001C1A7,
.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
+void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
+{
+ int i;
+ struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
+
+ for (i = 0; i < size; i++, pad++)
+ writel(pad->val, base + pad->offset);
+}
+
#ifdef CONFIG_SPL_BUILD
/* LPDDR2 specific IO settings */
static void io_settings_lpddr2(void)
writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
- writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
+
+ if (!is_dra7xx()) {
+ writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
+ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
+ }
/* omap5432 does not use lpddr2 */
writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
- writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
writel(ioregs->ctrl_emif_sdram_config_ext,
(*ctrl)->control_emif1_sdram_config_ext);
- writel(ioregs->ctrl_emif_sdram_config_ext,
- (*ctrl)->control_emif2_sdram_config_ext);
+ if (!is_dra72x())
+ writel(ioregs->ctrl_emif_sdram_config_ext,
+ (*ctrl)->control_emif2_sdram_config_ext);
if (is_omap54xx()) {
/* Disable DLL select */
void do_io_settings(void)
{
u32 io_settings = 0, mask = 0;
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
/* Impedance settings EMMC, C2C 1,2, hsi2 */
mask = (ds_mask << 2) | (ds_mask << 8) |
(sc_fast << 17) | (sc_fast << 14);
writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
- if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
+ if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
io_settings_lpddr2();
else
io_settings_ddr3();
.control_status = 0x4A002134,
.control_phy_power_usb = 0x4A002370,
.control_phy_power_sata = 0x4A002374,
+ .ctrl_core_sma_sw_0 = 0x4A0023FC,
.control_core_mac_id_0_lo = 0x4A002514,
.control_core_mac_id_0_hi = 0x4A002518,
.control_core_mac_id_1_lo = 0x4A00251C,
.control_efuse_3 = 0x4AE0C5D0,
.control_efuse_4 = 0x4AE0C5D4,
.control_efuse_13 = 0x4AE0C5F0,
+ .iodelay_config_base = 0x4844A000,
};
struct prcm_regs const omap5_es2_prcm = {
.cm_dsp_clkstctrl = 0x4a005400,
.cm_dsp_dsp_clkctrl = 0x4a005420,
+ /* cm IPU */
+ .cm_ipu_clkstctrl = 0x4a005540,
+ .cm_ipu_i2c5_clkctrl = 0x4a005578,
+
/* prm irqstatus regs */
.prm_irqstatus_mpu_2 = 0x4ae06014,
.prm_rstctrl = 0x4ae07d00,
.prm_rstst = 0x4ae07d04,
.prm_rsttime = 0x4ae07d08,
+ .prm_io_pmctrl = 0x4ae07d20,
.prm_vc_val_bypass = 0x4ae07da0,
.prm_vc_cfg_i2c_mode = 0x4ae07db4,
.prm_vc_cfg_i2c_clk = 0x4ae07db8,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
- .read_idle_ctrl = 0x00050001,
+ .read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0E24400A,
- .emif_ddr_phy_ctlr_1 = 0x0E24400A,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400B,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
- .read_idle_ctrl = 0x00050001,
+ .read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0E24400A,
- .emif_ddr_phy_ctlr_1 = 0x0E24400A,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400B,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
.sdram_config_init = 0x61862B32,
.sdram_config = 0x61862B32,
.sdram_config2 = 0x08000000,
- .ref_ctrl = 0x0000493E,
+ .ref_ctrl = 0x0000514C,
.ref_ctrl_final = 0x0000144A,
.sdram_tim1 = 0xD113781C,
- .sdram_tim2 = 0x308F7FE3,
- .sdram_tim3 = 0x009F86A8,
+ .sdram_tim2 = 0x305A7FDA,
+ .sdram_tim3 = 0x409F86A8,
.read_idle_ctrl = 0x00050000,
- .zq_config = 0x0007190B,
+ .zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0E24400D,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400D,
.emif_ddr_phy_ctlr_1 = 0x0E24400D,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
.emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
0x0
};
+/* Ext phy ctrl 1-35 regs */
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
+ 0x10040100,
+ 0x00910091,
+ 0x00950095,
+ 0x009B009B,
+ 0x009E009E,
0x00980098,
0x00340034,
0x00350035,
0x00500050,
0x00000000,
0x00600020,
- 0x40010080,
+ 0x40011080,
0x08102040,
0x0,
0x0,
0x0,
0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
0x0
};
+/* Ext phy ctrl 1-35 regs */
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
+ 0x10040100,
+ 0x00910091,
+ 0x00950095,
+ 0x009B009B,
+ 0x009E009E,
0x00980098,
0x00330033,
0x00330033,
0x00500050,
0x00000000,
0x00600020,
- 0x40010080,
+ 0x40011080,
0x08102040,
0x0,
0x0,
0x0,
0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
0x0
};
+/* Ext phy ctrl 1-35 regs */
const u32
dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
+ 0x10040100,
+ 0x00A400A4,
+ 0x00A900A9,
+ 0x00B000B0,
+ 0x00B000B0,
0x00A400A4,
0x00390039,
0x00320032,
0x0,
0x0,
0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
0x0
};
*regs = &mr_regs;
}
-void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs)
{
u32 *ext_phy_ctrl_base = 0;
u32 *emif_ext_phy_ctrl_base = 0;
}
}
+static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+ u32 *emif_ext_phy_ctrl_base = 0;
+ u32 emif_nr;
+ const u32 *ext_phy_ctrl_const_regs;
+ u32 i, hw_leveling, size;
+
+ emif_nr = (base == EMIF1_BASE) ? 1 : 2;
+
+ hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
+
+ emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);
+
+ emif_get_ext_phy_ctrl_const_regs(emif_nr,
+ &ext_phy_ctrl_const_regs, &size);
+
+ writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]);
+ writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]);
+
+ if (!hw_leveling) {
+ /*
+ * Copy the predefined PHY register values
+ * in case of sw leveling
+ */
+ for (i = 1; i < 25; i++) {
+ writel(ext_phy_ctrl_const_regs[i],
+ &emif_ext_phy_ctrl_base[i * 2]);
+ writel(ext_phy_ctrl_const_regs[i],
+ &emif_ext_phy_ctrl_base[i * 2 + 1]);
+ }
+ } else {
+ /*
+ * Write the init value for HW levling to occur
+ */
+ for (i = 21; i < 35; i++) {
+ writel(ext_phy_ctrl_const_regs[i],
+ &emif_ext_phy_ctrl_base[i * 2]);
+ writel(ext_phy_ctrl_const_regs[i],
+ &emif_ext_phy_ctrl_base[i * 2 + 1]);
+ }
+ }
+}
+
+void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+{
+ if (is_omap54xx())
+ do_ext_phy_settings_omap5(base, regs);
+ else
+ do_ext_phy_settings_dra7(base, regs);
+}
+
#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
.max_freq = 532000000,
#ifdef CONFIG_SPL_BUILD
/* The sunxi internal brom will try to loader external bootloader
* from mmc0, nand flash, mmc2.
- *
- * Unfortunately we can't check how SPL was loaded so assume it's
- * always the first SD/MMC controller, unless it was explicitly
- * stated that SPL is on nand flash.
+ * Unfortunately we can't check how SPL was loaded so assume
+ * it's always the first SD/MMC controller
*/
u32 spl_boot_device(void)
{
-#if defined(CONFIG_SPL_NAND_SUPPORT)
- /*
- * This is compile time configuration informing SPL, that it
- * was loaded from nand flash.
- */
- return BOOT_DEVICE_NAND;
-#else
/*
* When booting from the SD card, the "eGON.BT0" signature is expected
* to be found in memory at the address 0x0004 (see the "mksunxiboot"
return BOOT_DEVICE_MMC1;
else
return BOOT_DEVICE_BOARD;
-#endif
}
/* No confirmation data available in SPL yet. Hardcode bootmode */
writel(WDT_CFG_RESET, &wdog->cfg);
writel(WDT_MODE_EN, &wdog->mode);
writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
+ while (1) { }
#endif
}
dspiflash: at45db021d@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "spi-flash";
+ compatible = "atmel,dataflash";
spi-max-frequency = <16000000>;
spi-cpol;
spi-cpha;
* Copyright (C) 2015 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
/*
* Device Tree Source for UniPhier PH1-LD4 SoC
*
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "skeleton.dtsi"
};
};
+ clocks {
+ arm_timer_clk: arm_timer_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ interrupt-parent = <&intc>;
+
+ extbus: extbus {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ };
uart0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
};
+ system-bus-controller-misc@59800000 {
+ compatible = "socionext,uniphier-system-bus-controller-misc",
+ "syscon";
+ reg = <0x59800000 0x2000>;
+ };
+
usb0: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
};
+ timer@60000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x60000200 0x20>;
+ interrupts = <1 11 0x104>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ timer@60000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x60000600 0x20>;
+ interrupts = <1 13 0x104>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ intc: interrupt-controller@60001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x60001000 0x1000>,
+ <0x60000100 0x100>;
+ };
+
nand: nand@68000000 {
compatible = "denali,denali-nand-dt";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
* Copyright (C) 2015 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
/*
* Device Tree Source for UniPhier PH1-Pro4 SoC
*
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "skeleton.dtsi"
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "socionext,uniphier-smp";
cpu@0 {
device_type = "cpu";
};
};
+ clocks {
+ arm_timer_clk: arm_timer_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ interrupt-parent = <&intc>;
+
+ extbus: extbus {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ };
uart0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "ok";
};
+ system-bus-controller-misc@59800000 {
+ compatible = "socionext,uniphier-system-bus-controller-misc",
+ "syscon";
+ reg = <0x59800000 0x2000>;
+ };
+
usb2: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x65c00000 0x100>;
};
+ timer@60000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x60000200 0x20>;
+ interrupts = <1 11 0x304>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ timer@60000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x60000600 0x20>;
+ interrupts = <1 13 0x304>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ intc: interrupt-controller@60001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x60001000 0x1000>,
+ <0x60000100 0x100>;
+ };
+
nand: nand@68000000 {
compatible = "denali,denali-nand-dt";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
* Copyright (C) 2015 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
/*
* Device Tree Source for UniPhier PH1-sLD3 SoC
*
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "skeleton.dtsi"
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "socionext,uniphier-smp";
cpu@0 {
device_type = "cpu";
};
};
+ clocks {
+ arm_timer_clk: arm_timer_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ interrupt-parent = <&intc>;
+
+ extbus: extbus {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ };
+
+ timer@20000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x20000200 0x20>;
+ interrupts = <1 11 0x304>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ timer@20000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x20000600 0x20>;
+ interrupts = <1 13 0x304>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ intc: interrupt-controller@20001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x20001000 0x1000>,
+ <0x20000100 0x100>;
+ };
uart0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
};
+ system-bus-controller-misc@59800000 {
+ compatible = "socionext,uniphier-system-bus-controller-misc",
+ "syscon";
+ reg = <0x59800000 0x2000>;
+ };
+
usb0: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
* Copyright (C) 2015 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
/*
* Device Tree Source for UniPhier PH1-sLD8 SoC
*
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "skeleton.dtsi"
};
};
+ clocks {
+ arm_timer_clk: arm_timer_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ interrupt-parent = <&intc>;
+
+ extbus: extbus {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ };
uart0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
};
+ system-bus-controller-misc@59800000 {
+ compatible = "socionext,uniphier-system-bus-controller-misc",
+ "syscon";
+ reg = <0x59800000 0x2000>;
+ };
+
usb0: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
};
+ timer@60000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x60000200 0x20>;
+ interrupts = <1 11 0x104>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ timer@60000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x60000600 0x20>;
+ interrupts = <1 13 0x104>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ intc: interrupt-controller@60001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x60001000 0x1000>,
+ <0x60000100 0x100>;
+ };
+
nand: nand@68000000 {
compatible = "denali,denali-nand-dt";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
/*
* Device Tree Source for UniPhier Reference Daughter Board
*
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
&i2c0 {
interrupts = <0 50 4>;
};
+ spi0: spi@e0006000 {
+ compatible = "xlnx,zynq-spi";
+ reg = <0xe0006000 0x1000>;
+ status = "disabled";
+ interrupt-parent = <&intc>;
+ interrupts = <0 26 4>;
+ clocks = <&clkc 25>, <&clkc 34>;
+ clock-names = "ref_clk", "pclk";
+ spi-max-frequency = <166666700>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@e0007000 {
+ compatible = "xlnx,zynq-spi";
+ reg = <0xe0007000 0x1000>;
+ status = "disabled";
+ interrupt-parent = <&intc>;
+ interrupts = <0 49 4>;
+ clocks = <&clkc 26>, <&clkc 35>;
+ clock-names = "ref_clk", "pclk";
+ spi-max-frequency = <166666700>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
gem0: ethernet@e000b000 {
compatible = "cdns,gem";
reg = <0xe000b000 0x4000>;
aliases {
serial0 = &uart1;
+ spi1 = &spi1;
};
memory {
reg = <0 0x40000000>;
};
};
+
+&spi1 {
+ status = "okay";
+};
#define EXYNOS5420_USB_HOST_EHCI_BASE 0x12110000
#define EXYNOS5420_MMC_BASE 0x12200000
#define EXYNOS5420_SROMC_BASE 0x12250000
+#define EXYNOS5420_USB3PHY_BASE 0x12500000
#define EXYNOS5420_UART_BASE 0x12C00000
#define EXYNOS5420_I2C_BASE 0x12C60000
#define EXYNOS5420_I2C_8910_BASE 0x12E00000
#define EXYNOS5420_FIMD_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_ADC_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS5420_USB3PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
--- /dev/null
+/*
+ * (C) Copyright 2015
+ * Texas Instruments Incorporated
+ *
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DRA7_IODELAY_H_
+#define _DRA7_IODELAY_H_
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+/* CONFIG_REG_0 */
+#define CFG_REG_0_OFFSET 0xC
+#define CFG_REG_ROM_READ_SHIFT 1
+#define CFG_REG_ROM_READ_MASK (1 << 1)
+#define CFG_REG_CALIB_STRT_SHIFT 0
+#define CFG_REG_CALIB_STRT_MASK (1 << 0)
+#define CFG_REG_CALIB_STRT 1
+#define CFG_REG_CALIB_END 0
+#define CFG_REG_ROM_READ_START (1 << 1)
+#define CFG_REG_ROM_READ_END (0 << 1)
+
+/* CONFIG_REG_2 */
+#define CFG_REG_2_OFFSET 0x14
+#define CFG_REG_REFCLK_PERIOD_SHIFT 0
+#define CFG_REG_REFCLK_PERIOD_MASK (0xFFFF << 0)
+#define CFG_REG_REFCLK_PERIOD 0x2EF
+
+/* CONFIG_REG_8 */
+#define CFG_REG_8_OFFSET 0x2C
+#define CFG_IODELAY_UNLOCK_KEY 0x0000AAAA
+#define CFG_IODELAY_LOCK_KEY 0x0000AAAB
+
+/* CONFIG_REG_3/4 */
+#define CFG_REG_3_OFFSET 0x18
+#define CFG_REG_4_OFFSET 0x1C
+#define CFG_REG_DLY_CNT_SHIFT 16
+#define CFG_REG_DLY_CNT_MASK (0xFFFF << 16)
+#define CFG_REG_REF_CNT_SHIFT 0
+#define CFG_REG_REF_CNT_MASK (0xFFFF << 0)
+
+/* CTRL_CORE_SMA_SW_0 */
+#define CTRL_ISOLATE_SHIFT 2
+#define CTRL_ISOLATE_MASK (1 << 2)
+#define ISOLATE_IO 1
+#define DEISOLATE_IO 0
+
+/* PRM_IO_PMCTRL */
+#define PMCTRL_ISOCLK_OVERRIDE_SHIFT 0
+#define PMCTRL_ISOCLK_OVERRIDE_MASK (1 << 0)
+#define PMCTRL_ISOCLK_STATUS_SHIFT 1
+#define PMCTRL_ISOCLK_STATUS_MASK (1 << 1)
+#define PMCTRL_ISOCLK_OVERRIDE_CTRL 1
+#define PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL 0
+
+#define ERR_CALIBRATE_IODELAY 0x1
+#define ERR_DEISOLATE_IO 0x2
+#define ERR_ISOLATE_IO 0x4
+#define ERR_UPDATE_DELAY 0x8
+#define ERR_CPDE 0x3
+#define ERR_FPDE 0x5
+
+/* CFG_XXX */
+#define CFG_X_SIGNATURE_SHIFT 12
+#define CFG_X_SIGNATURE_MASK (0x3F << 12)
+#define CFG_X_LOCK_SHIFT 10
+#define CFG_X_LOCK_MASK (0x1 << 10)
+#define CFG_X_COARSE_DLY_SHIFT 5
+#define CFG_X_COARSE_DLY_MASK (0x1F << 5)
+#define CFG_X_FINE_DLY_SHIFT 0
+#define CFG_X_FINE_DLY_MASK (0x1F << 0)
+#define CFG_X_SIGNATURE 0x29
+#define CFG_X_LOCK 1
+
+void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
+ struct iodelay_cfg_entry const *iodelay,
+ int niodelays);
+
+#endif
#define WKEN (1 << 24)
#define WKDIS (0 << 24)
+#define PULL_ENA (0 << 16)
+#define PULL_DIS (1 << 16)
+#define PULL_UP (1 << 17)
+#define INPUT_EN (1 << 18)
+#define SLEWCONTROL (1 << 19)
+
+/* Active pin states */
+#define PIN_OUTPUT (0 | PULL_DIS)
+#define PIN_OUTPUT_PULLUP (PULL_UP)
+#define PIN_OUTPUT_PULLDOWN (0)
+#define PIN_INPUT (INPUT_EN | PULL_DIS)
+#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL)
+#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
+
#define M0 0
#define M1 1
#define M2 2
#define M14 14
#define M15 15
+#define MODE_SELECT (1 << 8)
+#define DELAYMODE_SHIFT 4
+
+#define MANUAL_MODE MODE_SELECT
+
+#define VIRTUAL_MODE0 (MODE_SELECT | (0x0 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE1 (MODE_SELECT | (0x1 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE2 (MODE_SELECT | (0x2 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE3 (MODE_SELECT | (0x3 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE4 (MODE_SELECT | (0x4 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE5 (MODE_SELECT | (0x5 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE6 (MODE_SELECT | (0x6 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE7 (MODE_SELECT | (0x7 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE8 (MODE_SELECT | (0x8 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE9 (MODE_SELECT | (0x9 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE10 (MODE_SELECT | (0xa << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE11 (MODE_SELECT | (0xb << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE12 (MODE_SELECT | (0xc << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE13 (MODE_SELECT | (0xd << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE14 (MODE_SELECT | (0xe << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE15 (MODE_SELECT | (0xf << DELAYMODE_SHIFT))
+
#define SAFE_MODE M15
#define GPMC_AD0 0x000
#define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10)
#define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0)
-/* IO Delay module defines */
-#define CFG_IO_DELAY_BASE 0x4844A000
-#define CFG_IO_DELAY_LOCK (CFG_IO_DELAY_BASE + 0x02C)
-
-/* CPSW IO Delay registers*/
-#define CFG_RGMII0_TXCTL (CFG_IO_DELAY_BASE + 0x74C)
-#define CFG_RGMII0_TXD0 (CFG_IO_DELAY_BASE + 0x758)
-#define CFG_RGMII0_TXD1 (CFG_IO_DELAY_BASE + 0x764)
-#define CFG_RGMII0_TXD2 (CFG_IO_DELAY_BASE + 0x770)
-#define CFG_RGMII0_TXD3 (CFG_IO_DELAY_BASE + 0x77C)
-#define CFG_VIN2A_D13 (CFG_IO_DELAY_BASE + 0xA7C)
-#define CFG_VIN2A_D17 (CFG_IO_DELAY_BASE + 0xAAC)
-#define CFG_VIN2A_D16 (CFG_IO_DELAY_BASE + 0xAA0)
-#define CFG_VIN2A_D15 (CFG_IO_DELAY_BASE + 0xA94)
-#define CFG_VIN2A_D14 (CFG_IO_DELAY_BASE + 0xA88)
-
-#define CFG_IO_DELAY_UNLOCK_KEY 0x0000AAAA
-#define CFG_IO_DELAY_LOCK_KEY 0x0000AAAB
-#define CFG_IO_DELAY_ACCESS_PATTERN 0x00029000
-#define CFG_IO_DELAY_LOCK_MASK 0x400
-
#ifndef __ASSEMBLY__
struct srcomp_params {
s8 divide_factor;
u32 ctrl_ddr_ctrl_ext_0;
};
-struct io_delay {
- u32 addr;
- u32 dly;
-};
#endif /* __ASSEMBLY__ */
#endif
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Structure for Iodelay configuration registers.
+ * Theoretical max for g_delay is 21560 ps.
+ * Theoretical max for a_delay is 1/3rd of g_delay max.
+ * So using u16 for both a/g_delay.
+ */
+struct iodelay_cfg_entry {
+ u16 offset;
+ u16 a_delay;
+ u16 g_delay;
+};
+
struct pad_conf_entry {
u32 offset;
u32 val;
void watchdog_init(void);
u32 get_device_type(void);
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size);
void set_muxconf_regs_essential(void);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
#define SUN5I_GPB_UART0 2
#define SUN8I_GPB_UART2 2
-#define SUNXI_GPC_NAND 2
-
#define SUNXI_GPC_SDC2 3
#define SUN6I_GPC_SDC3 4
+++ /dev/null
-/*
- * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SUNXI_NAND_H
-#define _SUNXI_NAND_H
-
-#include <linux/types.h>
-
-struct sunxi_nand
-{
- u32 ctl; /* 0x000 Configure and control */
- u32 st; /* 0x004 Status information */
- u32 intr; /* 0x008 Interrupt control */
- u32 timing_ctl; /* 0x00C Timing control */
- u32 timing_cfg; /* 0x010 Timing configure */
- u32 addr_low; /* 0x014 Low word address */
- u32 addr_high; /* 0x018 High word address */
- u32 block_num; /* 0x01C Data block number */
- u32 data_cnt; /* 0x020 Data counter for transfer */
- u32 cmd; /* 0x024 NDFC commands */
- u32 rcmd_set; /* 0x028 Read command set for vendor NAND mem */
- u32 wcmd_set; /* 0x02C Write command set */
- u32 io_data; /* 0x030 IO data */
- u32 ecc_ctl; /* 0x034 ECC configure and control */
- u32 ecc_st; /* 0x038 ECC status and operation info */
- u32 efr; /* 0x03C Enhanced feature */
- u32 err_cnt0; /* 0x040 Corrected error bit counter 0 */
- u32 err_cnt1; /* 0x044 Corrected error bit counter 1 */
- u32 user_data[16]; /* 0x050[16] User data field */
- u32 efnand_st; /* 0x090 EFNAND status */
- u32 res0[3];
- u32 spare_area; /* 0x0A0 Spare area configure */
- u32 pat_id; /* 0x0A4 Pattern ID register */
- u32 rdata_sta_ctl; /* 0x0A8 Read data status control */
- u32 rdata_sta_0; /* 0x0AC Read data status 0 */
- u32 rdata_sta_1; /* 0x0B0 Read data status 1 */
- u32 res1[3];
- u32 mdma_addr; /* 0x0C0 MBUS DMA Address */
- u32 mdma_cnt; /* 0x0C4 MBUS DMA data counter */
-};
-
-#define SUNXI_NAND_CTL_EN (1 << 0)
-#define SUNXI_NAND_CTL_RST (1 << 1)
-#define SUNXI_NAND_CTL_PAGE_SIZE(a) ((fls(a) - 11) << 8)
-#define SUNXI_NAND_CTL_RAM_METHOD_DMA (1 << 14)
-
-#define SUNXI_NAND_ST_CMD_INT (1 << 1)
-#define SUNXI_NAND_ST_DMA_INT (1 << 2)
-#define SUNXI_NAND_ST_FIFO_FULL (1 << 3)
-
-#define SUNXI_NAND_CMD_ADDR_CYCLES(a) ((a - 1) << 16);
-#define SUNXI_NAND_CMD_SEND_CMD1 (1 << 22)
-#define SUNXI_NAND_CMD_WAIT_FLAG (1 << 23)
-#define SUNXI_NAND_CMD_ORDER_INTERLEAVE 0
-#define SUNXI_NAND_CMD_ORDER_SEQ (1 << 25)
-
-#define SUNXI_NAND_ECC_CTL_ECC_EN (1 << 0)
-#define SUNXI_NAND_ECC_CTL_PIPELINE (1 << 3)
-#define SUNXI_NAND_ECC_CTL_BS_512B (1 << 5)
-#define SUNXI_NAND_ECC_CTL_RND_EN (1 << 9)
-#define SUNXI_NAND_ECC_CTL_MODE(a) ((a) << 12)
-#define SUNXI_NAND_ECC_CTL_RND_SEED(a) ((a) << 16)
-
-#endif /* _SUNXI_NAND_H */
#define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30)
#define EMIF_REG_FAST_INIT_SHIFT 29
#define EMIF_REG_FAST_INIT_MASK (1 << 29)
+#define EMIF_REG_LEVLING_TO_SHIFT 4
+#define EMIF_REG_LEVELING_TO_MASK (7 << 4)
#define EMIF_REG_PHY_DLL_READY_SHIFT 2
#define EMIF_REG_PHY_DLL_READY_MASK (1 << 2)
#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0
#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0)
+/* EMIF_PHY_CTRL_36 */
+#define EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR (1 << 8)
+
+#define PHY_RDDQS_RATIO_REGS 5
+#define PHY_FIFO_WE_SLAVE_RATIO_REGS 5
+#define PHY_REG_WR_DQ_SLAVE_RATIO_REGS 10
+
/*Leveling Fields */
#define DDR3_WR_LVL_INT 0x73
#define DDR3_RD_LVL_INT 0x33
* which is typically the case. So it is sufficient to get
* SDRAM type from EMIF1.
*/
-static inline u32 emif_sdram_type(void)
+static inline u32 emif_sdram_type(u32 sdram_config)
{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
-
- return (readl(&emif->emif_sdram_config) &
- EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
+ return (sdram_config & EMIF_REG_SDRAM_TYPE_MASK)
+ >> EMIF_REG_SDRAM_TYPE_SHIFT;
}
/* assert macros */
#endif
void config_data_eye_leveling_samples(u32 emif_base);
-u32 emif_sdram_type(void);
const struct read_write_regs *get_bug_regs(u32 *iterations);
#endif
u32 prm_rstctrl;
u32 prm_rstst;
u32 prm_rsttime;
+ u32 prm_io_pmctrl;
u32 prm_vc_val_bypass;
u32 prm_vc_cfg_i2c_mode;
u32 prm_vc_cfg_i2c_clk;
/* GMAC Clk Ctrl */
u32 cm_gmac_gmac_clkctrl;
u32 cm_gmac_clkstctrl;
+
+ /* IPU */
+ u32 cm_ipu_clkstctrl;
+ u32 cm_ipu_i2c5_clkctrl;
};
struct omap_sys_ctrl_regs {
u32 control_efuse_12;
u32 control_efuse_13;
u32 control_padconf_wkup_base;
+ u32 iodelay_config_base;
+ u32 ctrl_core_sma_sw_0;
};
struct dpll_params {
void usb_fake_mac_from_die_id(u32 *id);
void usb_set_serial_num_from_die_id(u32 *id);
+void recalibrate_iodelay(void);
void omap_smc1(u32 service, u32 val);
}
#define DRA7XX 0x07000000
+#define DRA72X 0x07200000
static inline u8 is_dra7xx(void)
{
extern u32 *const omap_si_rev;
return ((*omap_si_rev & 0xFF000000) == DRA7XX);
}
+
+static inline u8 is_dra72x(void)
+{
+ extern u32 *const omap_si_rev;
+ return (*omap_si_rev & 0xFFF00000) == DRA72X;
+}
#endif
/*
endchoice
-config PHYS_TO_BUS
- default y
-
config SYS_BOARD
default "rpi" if TARGET_RPI
default "rpi_2" if TARGET_RPI_2
}
#endif
-inline int get_max_dev_speed(void)
-{
- return get_max_speed(read_efuse_bootrom() & 0xffff, dev_speeds);
-}
-
#ifndef CONFIG_SOC_K2E
inline int get_max_arm_speed(void)
{
- return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
+ return get_max_speed(read_efuse_bootrom() & 0xffff, arm_speeds);
}
#endif
+inline int get_max_dev_speed(void)
+{
+ return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, dev_speeds);
+}
+
void pass_pll_pa_clk_enable(void)
{
u32 reg;
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
+#include <asm/pl310.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
}
#ifdef CONFIG_ARCH_CPU_INIT
+static void set_cbar(u32 addr)
+{
+ asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
+}
+
+
int arch_cpu_init(void)
{
/* Linux expects the internal registers to be at 0xf1000000 */
writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
+ set_cbar(SOC_REGS_PHY_BASE + 0xC000);
/*
* We need to call mvebu_mbus_probe() before calling
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
+ struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+ /* First disable L2 cache - may still be enable from BootROM */
+ if (mvebu_soc_family() == MVEBU_SOC_A38X)
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
/* Avoid problem with e.g. neta ethernet driver */
invalidate_dcache_all();
config SYS_MALLOC_F_LEN
default 0x1800
-config USE_PRIVATE_LIBGCC
- default y
-
-config DM_USB
- default y
-
-config SPL_DM
- default y
-
-config SPL_DISABLE_OF_CONTROL
- default y
-
source "arch/arm/mach-tegra/tegra20/Kconfig"
source "arch/arm/mach-tegra/tegra30/Kconfig"
source "arch/arm/mach-tegra/tegra114/Kconfig"
case 0x29:
puts("PH1-sLD8 (MN2WS0270)");
break;
+ case 0x2A:
+ puts("PH1-Pro5 (MN2WS0300)");
+ break;
+ case 0x2E:
+ puts("ProXstream2 (MN2WS0310)");
+ break;
+ case 0x2F:
+ puts("PH1-LD6b (MN2WS0320)");
+ break;
default:
printf("Unknown Processor ID (0x%x)\n", revision);
return -1;
default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2
default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2
-config USE_PRIVATE_LIBGCC
- default y
-
choice
prompt "Target select"
optional
default "sh3" if CPU_SH3
default "sh4" if CPU_SH4
-config USE_PRIVATE_LIBGCC
- default y
-
source "board/alphaproject/ap_sh4a_4a/Kconfig"
source "board/espt/Kconfig"
source "board/mpr2/Kconfig"
config SYS_ARCH
default "x86"
-config USE_PRIVATE_LIBGCC
- default y
-
-config SYS_VSNPRINTF
- default y
-
choice
prompt "Mainboard vendor"
default VENDOR_EMULATION
assigned to PCI devices - i.e. the memory and prefetch regions, as
passed to pci_set_region().
-config BOOTSTAGE
- default y
-
-config BOOTSTAGE_REPORT
- default y
-
-config CMD_BOOTSTAGE
- default y
-
endmenu
string
default "UCP1020"
-config SPI_FLASH
- bool
- default y
-
-config SPI_PCI
- bool
- default y
-
choice
prompt "Target image select"
unsigned int pwmfrq = getenv_ulong("ds1_pwmfreq", 10, ~0UL);
#endif
unsigned int tmp;
-
- struct gptimer *const timerhw = (struct gptimer *)DM_TIMER6_BASE;
+ struct gptimer *timerhw;
if (on)
bright = bright != ~0UL ? bright : 50;
else
bright = 0;
+ switch (driver) {
+ case 2:
+ timerhw = (struct gptimer *)DM_TIMER5_BASE;
+ break;
+ default:
+ timerhw = (struct gptimer *)DM_TIMER6_BASE;
+ }
+
switch (driver) {
case 0: /* PMIC LED-Driver */
/* brightness level */
bright != 0 ? 0x0A : 0x02,
0xFF);
break;
- case 1: /* PWM using timer6 */
+ case 1:
+ case 2: /* PWM using timer */
if (pwmfrq != ~0UL) {
timerhw->tiocp_cfg = TCFG_RESET;
udelay(10);
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := highbank.o
+obj-y := highbank.o ahci.o
--- /dev/null
+/*
+ * Copyright 2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <asm/io.h>
+
+#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
+#define CPHY_ADDR(base, dev, addr) ((base) | (((addr) & 0x1ff) << 2))
+#define CPHY_BASE 0xfff58000
+#define CPHY_WIDTH 0x1000
+#define CPHY_DTE_XS 5
+#define CPHY_MII 31
+#define SERDES_CR_CTL 0x80a0
+#define SERDES_CR_ADDR 0x80a1
+#define SERDES_CR_DATA 0x80a2
+#define CR_BUSY 0x0001
+#define CR_START 0x0001
+#define CR_WR_RDN 0x0002
+#define CPHY_TX_INPUT_STS 0x2001
+#define CPHY_RX_INPUT_STS 0x2002
+#define CPHY_SATA_TX_OVERRIDE_BIT 0x8000
+#define CPHY_SATA_RX_OVERRIDE_BIT 0x4000
+#define CPHY_TX_INPUT_OVERRIDE 0x2004
+#define CPHY_RX_INPUT_OVERRIDE 0x2005
+#define SPHY_LANE 0x100
+#define SPHY_HALF_RATE 0x0001
+#define CPHY_SATA_DPLL_MODE 0x0700
+#define CPHY_SATA_DPLL_SHIFT 8
+#define CPHY_SATA_TX_ATTEN 0x1c00
+#define CPHY_SATA_TX_ATTEN_SHIFT 10
+
+#define HB_SREG_SATA_ATTEN 0xfff3cf24
+
+#define SATA_PORT_BASE 0xffe08000
+#define SATA_VERSIONR 0xf8
+#define SATA_HB_VERSION 0x3332302a
+
+static u32 __combo_phy_reg_read(u8 phy, u8 dev, u32 addr)
+{
+ u32 data;
+ writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
+ data = readl(CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
+ return data;
+}
+
+static void __combo_phy_reg_write(u8 phy, u8 dev, u32 addr, u32 data)
+{
+ writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
+ writel(data, CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
+}
+
+static u32 combo_phy_read(u8 phy, u32 addr)
+{
+ u8 dev = CPHY_DTE_XS;
+ if (phy == 5)
+ dev = CPHY_MII;
+ while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
+ udelay(5);
+ __combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
+ __combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_START);
+ while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
+ udelay(5);
+ return __combo_phy_reg_read(phy, dev, SERDES_CR_DATA);
+}
+
+static void combo_phy_write(u8 phy, u32 addr, u32 data)
+{
+ u8 dev = CPHY_DTE_XS;
+ if (phy == 5)
+ dev = CPHY_MII;
+ while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
+ udelay(5);
+ __combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
+ __combo_phy_reg_write(phy, dev, SERDES_CR_DATA, data);
+ __combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_WR_RDN | CR_START);
+}
+
+static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val)
+{
+ u32 tmp;
+ tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
+ tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
+ combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+ tmp |= CPHY_SATA_RX_OVERRIDE_BIT;
+ combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+ tmp &= ~CPHY_SATA_DPLL_MODE;
+ tmp |= (val << CPHY_SATA_DPLL_SHIFT) & CPHY_SATA_DPLL_MODE;
+ combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+}
+
+static void cphy_tx_attenuation_override(u8 phy, u8 lane)
+{
+ u32 val;
+ u32 tmp;
+ u8 shift;
+
+ shift = ((phy == 5) ? 4 : lane) * 4;
+
+ val = (readl(HB_SREG_SATA_ATTEN) >> shift) & 0xf;
+
+ if (val & 0x8)
+ return;
+
+ tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE);
+ tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
+ combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+ tmp |= CPHY_SATA_TX_OVERRIDE_BIT;
+ combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+ tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN;
+ combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+}
+
+static void cphy_disable_port_overrides(u8 port)
+{
+ u32 tmp;
+ u8 lane = 0, phy = 0;
+
+ if (port == 0)
+ phy = 5;
+ else if (port < 5)
+ lane = port - 1;
+ else
+ return;
+ tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
+ tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
+ combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+ tmp = combo_phy_read(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE);
+ tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
+ combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+}
+
+void cphy_disable_overrides(void)
+{
+ int i;
+ u32 port_map;
+
+ port_map = readl(0xffe08000 + HOST_PORTS_IMPL);
+ for (i = 0; i < 5; i++) {
+ if (port_map & (1 << i))
+ cphy_disable_port_overrides(i);
+ }
+}
+
+static void cphy_override_lane(u8 port)
+{
+ u32 tmp, k = 0;
+ u8 lane = 0, phy = 0;
+
+ if (port == 0)
+ phy = 5;
+ else if (port < 5)
+ lane = port - 1;
+ else
+ return;
+
+ do {
+ tmp = combo_phy_read(0, CPHY_RX_INPUT_STS +
+ lane * SPHY_LANE);
+ } while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
+ cphy_spread_spectrum_override(phy, lane, 3);
+ cphy_tx_attenuation_override(phy, lane);
+}
+
+#define WAIT_MS_LINKUP 4
+
+int ahci_link_up(struct ahci_probe_ent *probe_ent, int port)
+{
+ u32 tmp;
+ int j = 0;
+ u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
+ u32 is_highbank = readl(SATA_PORT_BASE + SATA_VERSIONR) ==
+ SATA_HB_VERSION ? 1 : 0;
+
+ /* Bring up SATA link.
+ * SATA link bringup time is usually less than 1 ms; only very
+ * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
+ */
+ while (j < WAIT_MS_LINKUP) {
+ if (is_highbank && (j == 0)) {
+ cphy_disable_port_overrides(port);
+ writel(0x301, port_mmio + PORT_SCR_CTL);
+ udelay(1000);
+ writel(0x300, port_mmio + PORT_SCR_CTL);
+ udelay(1000);
+ cphy_override_lane(port);
+ }
+
+ tmp = readl(port_mmio + PORT_SCR_STAT);
+ if ((tmp & 0xf) == 0x3)
+ return 0;
+ udelay(1000);
+ j++;
+
+ if ((j == WAIT_MS_LINKUP) && (tmp & 0xf))
+ j = 0; /* retry phy reset */
+ }
+ return 1;
+}
#define HB_AHCI_BASE 0xffe08000
+#define HB_SCU_A9_PWR_STATUS 0xfff10008
#define HB_SREG_A9_PWR_REQ 0xfff3cf00
#define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04
#define HB_SREG_A9_PWRDOM_STAT 0xfff3cf20
+#define HB_SREG_A15_PWR_CTRL 0xfff3c200
#define HB_PWR_SUSPEND 0
#define HB_PWR_SOFT_RESET 1
#define PWRDOM_STAT_PCI 0x40000000
#define PWRDOM_STAT_EMMC 0x20000000
+#define HB_SCU_A9_PWR_NORMAL 0
+#define HB_SCU_A9_PWR_DORMANT 2
+#define HB_SCU_A9_PWR_OFF 3
+
DECLARE_GLOBAL_DATA_PTR;
+void cphy_disable_overrides(void);
+
/*
* Miscellaneous platform dependent initialisations
*/
{
u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
+ cphy_disable_overrides();
if (reg & PWRDOM_STAT_SATA) {
ahci_init((void __iomem *)HB_AHCI_BASE);
scsi_scan(1);
}
#endif
+static int is_highbank(void)
+{
+ uint32_t midr;
+
+ asm volatile ("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
+
+ return (midr & 0xfff0) == 0xc090;
+}
+
void reset_cpu(ulong addr)
{
writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
+ if (is_highbank())
+ writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS);
+ else
+ writel(0x1, HB_SREG_A15_PWR_CTRL);
wfi();
}
+
+/*
+ * turn off the override before transferring control to Linux, since Linux
+ * may not support spread spectrum.
+ */
+void arch_preboot_os(void)
+{
+ cphy_disable_overrides();
+}
#include <asm/arch/sromc.h>
#include <lcd.h>
#include <i2c.h>
-#include <samsung/misc.h>
#include <usb.h>
+#include <dwc3-uboot.h>
+#include <samsung/misc.h>
DECLARE_GLOBAL_DATA_PTR;
int board_usb_cleanup(int index, enum usb_init_type init)
{
+#ifdef CONFIG_USB_DWC3
+ dwc3_uboot_exit(index);
+#endif
return 0;
}
--- /dev/null
+# This is an example file to generate boot.scr - a boot script for U-Boot
+# Generate boot.scr:
+# ./tools/mkimage -c none -A arm -T script -d autoboot.cmd boot.scr
+#
+# It requires a list of environment variables to be defined before load:
+# platform dependent: boardname, fdtfile, console
+# system dependent: mmcbootdev, mmcbootpart, mmcrootdev, mmcrootpart, rootfstype
+#
+setenv fdtaddr "40800000"
+setenv initrdname "uInitrd"
+setenv initrdaddr "42000000"
+setenv loaddtb "load mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} ${fdtfile}"
+setenv loadinitrd "load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} ${initrdname}"
+setenv loadkernel "load mmc ${mmcbootdev}:${mmcbootpart} '${kerneladdr}' '${kernelname}'"
+setenv kernel_args "setenv bootargs ${console} root=/dev/mmcblk${mmcrootdev}p${mmcrootpart} rootfstype=${rootfstype} rootwait ${opts}"
+
+#### Routine: check_dtb - check that target.dtb exists on boot partition
+setenv check_dtb "
+if test -e mmc '${mmcbootdev}':'${mmcbootpart}' '${fdtfile}'; then
+ run loaddtb;
+ setenv fdt_addr ${fdtaddr};
+else
+ echo Warning! Booting without DTB: '${fdtfile}'!;
+ setenv fdt_addr;
+fi;"
+
+#### Routine: check_ramdisk - check that uInitrd exists on boot partition
+setenv check_ramdisk "
+if test -e mmc '${mmcbootdev}':'${mmcbootpart}' '${initrdname}'; then
+ echo "Found ramdisk image.";
+ run loadinitrd;
+ setenv initrd_addr ${initrdaddr};
+else
+ echo Warning! Booting without RAMDISK: '${initrdname}'!;
+ setenv initrd_addr -;
+fi;"
+
+#### Routine: boot_fit - check that env $boardname is set and boot proper config of ITB image
+setenv setboot_fit "
+if test -e '${boardname}'; then
+ setenv fdt_addr ;
+ setenv initrd_addr ;
+ setenv kerneladdr 0x42000000;
+ setenv kernelname Image.itb;
+ setenv itbcfg "\"#${boardname}\"";
+ setenv imgbootcmd bootm;
+else
+ echo Warning! Variable: \$boardname is undefined!;
+fi"
+
+#### Routine: setboot_uimg - prepare env to boot uImage
+setenv setboot_uimg "
+ setenv kerneladdr 0x40007FC0;
+ setenv kernelname uImage;
+ setenv itbcfg ;
+ setenv imgbootcmd bootm;
+ run check_dtb;
+ run check_ramdisk;"
+
+#### Routine: setboot_zimg - prepare env to boot zImage
+setenv setboot_zimg "
+ setenv kerneladdr 0x40007FC0;
+ setenv kernelname zImage;
+ setenv itbcfg ;
+ setenv imgbootcmd bootz;
+ run check_dtb;
+ run check_ramdisk;"
+
+#### Routine: boot_img - boot the kernel after env setup
+setenv boot_img "
+ run loadkernel;
+ run kernel_args;
+ '${imgbootcmd}' '${kerneladdr}${itbcfg}' '${initrd_addr}' '${fdt_addr}';"
+
+#### Routine: autoboot - choose proper boot path
+setenv autoboot "
+if test -e mmc 0:${mmcbootpart} Image.itb; then
+ echo Found kernel image: Image.itb;
+ run setboot_fit;
+ run boot_img;
+elif test -e mmc 0:${mmcbootpart} zImage; then
+ echo Found kernel image: zImage;
+ run setboot_zimg;
+ run boot_img;
+elif test -e mmc 0:${mmcbootpart} uImage; then
+ echo Found kernel image: uImage;
+ run setboot_uimg;
+ run boot_img;
+fi;"
+
+#### Execute the defined autoboot macro
+run autoboot
--- /dev/null
+setenv kernelname zImage;
+setenv boot_kernel "setenv bootargs \"${console} root=/dev/mmcblk${mmcrootdev}p${mmcrootpart} rootfstype=${rootfstype} rootwait ${opts}\";
+load mmc ${mmcbootdev}:${mmcbootpart} 0x40007FC0 '${kernelname}';
+if load mmc ${mmcbootdev}:${mmcbootpart} 40800000 ${fdtfile}; then
+ bootz 0x40007FC0 - 40800000;
+else
+ echo Warning! Booting without DTB: '${fdtfile}'!;
+ bootz 0x40007FC0 -;
+fi;"
+run boot_kernel;
\ No newline at end of file
#include <common.h>
#include <fdtdec.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include <lcd.h>
-#include <parade.h>
-#include <spi.h>
#include <errno.h>
+#include <asm/io.h>
#include <asm/gpio.h>
-#include <asm/arch/board.h>
#include <asm/arch/cpu.h>
-#include <asm/arch/pinmux.h>
+#include <asm/arch/board.h>
+#include <asm/arch/power.h>
#include <asm/arch/system.h>
+#include <asm/arch/pinmux.h>
#include <asm/arch/dp_info.h>
+#include <asm/arch/xhci-exynos.h>
#include <power/tps65090_pmic.h>
+#include <i2c.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <parade.h>
+#include <spi.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
+#include <samsung-usb-phy-uboot.h>
DECLARE_GLOBAL_DATA_PTR;
{
return 0;
}
+
+#ifdef CONFIG_USB_DWC3
+static struct dwc3_device dwc3_device_data = {
+ .maximum_speed = USB_SPEED_SUPER,
+ .base = 0x12400000,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 0,
+};
+
+int usb_gadget_handle_interrupts(void)
+{
+ dwc3_uboot_handle_interrupt(0);
+ return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ struct exynos_usb3_phy *phy = (struct exynos_usb3_phy *)
+ samsung_get_base_usb3_phy();
+
+ if (!phy) {
+ error("usb3 phy not supported");
+ return -ENODEV;
+ }
+
+ set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN);
+ exynos5_usb3_phy_init(phy);
+
+ return dwc3_uboot_init(&dwc3_device_data);
+}
+#endif
+#ifdef CONFIG_SET_DFU_ALT_INFO
+char *get_dfu_alt_system(char *interface, char *devstr)
+{
+ return getenv("dfu_alt_system");
+}
+
+char *get_dfu_alt_boot(char *interface, char *devstr)
+{
+ struct mmc *mmc;
+ char *alt_boot;
+ int dev_num;
+
+ dev_num = simple_strtoul(devstr, NULL, 10);
+
+ mmc = find_mmc_device(dev_num);
+ if (!mmc)
+ return NULL;
+
+ if (mmc_init(mmc))
+ return NULL;
+
+ if (IS_SD(mmc))
+ alt_boot = CONFIG_DFU_ALT_BOOT_SD;
+ else
+ alt_boot = CONFIG_DFU_ALT_BOOT_EMMC;
+
+ return alt_boot;
+}
+#endif
i2c_set_bus_num(0);
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
-
+#ifdef CONFIG_MACH_TYPE
gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_FACTORYSET
}
#ifndef CONFIG_SPL_BUILD
+
+#define MAX_NR_LEDS 10
+#define MAX_PIN_NUMBER 128
+#define STARTUP 0
+
#if defined(BOARD_DFU_BUTTON_GPIO)
-/*
- * This command returns the status of the user button on
- * Input - none
- * Returns - 1 if button is held down
- * 0 if button is not held down
- */
-static int
-do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+unsigned char get_button_state(char * const envname, unsigned char def)
{
int button = 0;
int gpio;
+ char *ptr_env;
- gpio = BOARD_DFU_BUTTON_GPIO;
- gpio_request(gpio, "DFU");
+ /* If button is not found we take default */
+ ptr_env = getenv(envname);
+ if (NULL == ptr_env) {
+ gpio = def;
+ } else {
+ gpio = (unsigned char)simple_strtoul(ptr_env, NULL, 0);
+ if (gpio > MAX_PIN_NUMBER)
+ gpio = def;
+ }
+
+ gpio_request(gpio, "");
gpio_direction_input(gpio);
if (gpio_get_value(gpio))
button = 1;
return button;
}
-
-U_BOOT_CMD(
- dfubutton, CONFIG_SYS_MAXARGS, 1, do_userbutton,
- "Return the status of the DFU button",
- ""
-);
-#endif
-/*
- * This command sets led
- * Input - name of led
- * value of led
- * Returns - 1 if input does not match
- * 0 if led was set
+/**
+ * This command returns the status of the user button on
+ * Input - none
+ * Returns - 1 if button is held down
+ * 0 if button is not held down
*/
static int
-do_setled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- int gpio = 0;
- if (argc != 3)
- goto exit;
-#if defined(BOARD_STATUS_LED)
- if (!strcmp(argv[1], "stat"))
- gpio = BOARD_STATUS_LED;
-#endif
-#if defined(BOARD_DFU_BUTTON_LED)
- if (!strcmp(argv[1], "dfu"))
- gpio = BOARD_DFU_BUTTON_LED;
-#endif
- /* If argument does not mach exit */
- if (gpio == 0)
- goto exit;
- gpio_request(gpio, "");
- gpio_direction_output(gpio, 1);
- if (!strcmp(argv[2], "1"))
- gpio_set_value(gpio, 1);
- else
- gpio_set_value(gpio, 0);
- return 0;
-exit:
- return 1;
+ int button = 0;
+ button = get_button_state("button_dfu0", BOARD_DFU_BUTTON_GPIO);
+ button |= get_button_state("button_dfu1", BOARD_DFU_BUTTON_GPIO);
+ return button;
}
U_BOOT_CMD(
- led, CONFIG_SYS_MAXARGS, 2, do_setled,
- "Set led on or off",
- "dfu val - set dfu led\nled stat val - set status led"
+ dfubutton, CONFIG_SYS_MAXARGS, 1, do_userbutton,
+ "Return the status of the DFU button",
+ ""
);
+#endif
static int
do_usertestwdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
"Sends U-Boot into infinite loop",
""
);
+
+/**
+ * Get led gpios from env and set them.
+ * The led define in environment need to need to be of the form ledN=NN,S0,S1
+ * where N is an unsigned integer from 0 to 9 and S0 and S1 is 0 or 1. S0
+ * defines the startup state of the led, S1 the special state of the led when
+ * it enters e.g. dfu mode.
+ */
+void set_env_gpios(unsigned char state)
+{
+ char *ptr_env;
+ char str_tmp[5]; /* must contain "ledX"*/
+ char num[1];
+ unsigned char i, idx, pos1, pos2, ccount;
+ unsigned char gpio_n, gpio_s0, gpio_s1;
+
+ for (i = 0; i < MAX_NR_LEDS; i++) {
+ strcpy(str_tmp, "led");
+ sprintf(num, "%d", i);
+ strcat(str_tmp, num);
+
+ /* If env var is not found we stop */
+ ptr_env = getenv(str_tmp);
+ if (NULL == ptr_env)
+ break;
+
+ /* Find sperators position */
+ pos1 = 0;
+ pos2 = 0;
+ ccount = 0;
+ for (idx = 0; ptr_env[idx] != '\0'; idx++) {
+ if (ptr_env[idx] == ',') {
+ if (ccount++ < 1)
+ pos1 = idx;
+ else
+ pos2 = idx;
+ }
+ }
+ /* Bad led description skip this definition */
+ if (pos2 <= pos1 || ccount > 2)
+ continue;
+
+ /* Get pin number and request gpio */
+ memset(str_tmp, 0, sizeof(str_tmp));
+ strncpy(str_tmp, ptr_env, pos1*sizeof(char));
+ gpio_n = (unsigned char)simple_strtoul(str_tmp, NULL, 0);
+
+ /* Invalid gpio number skip definition */
+ if (gpio_n > MAX_PIN_NUMBER)
+ continue;
+
+ gpio_request(gpio_n, "");
+
+ if (state == STARTUP) {
+ /* get pin state 0 and set */
+ memset(str_tmp, 0, sizeof(str_tmp));
+ strncpy(str_tmp, ptr_env+pos1+1,
+ (pos2-pos1-1)*sizeof(char));
+ gpio_s0 = (unsigned char)simple_strtoul(str_tmp, NULL,
+ 0);
+
+ gpio_direction_output(gpio_n, gpio_s0);
+
+ } else {
+ /* get pin state 1 and set */
+ memset(str_tmp, 0, sizeof(str_tmp));
+ strcpy(str_tmp, ptr_env+pos2+1);
+ gpio_s1 = (unsigned char)simple_strtoul(str_tmp, NULL,
+ 0);
+ gpio_direction_output(gpio_n, gpio_s1);
+ }
+ } /* loop through defined led in environment */
+}
+
+static int do_board_led(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ if (argc != 2)
+ return CMD_RET_USAGE;
+ if ((unsigned char)simple_strtoul(argv[1], NULL, 0) == STARTUP)
+ set_env_gpios(0);
+ else
+ set_env_gpios(1);
+ return 0;
+};
+
+U_BOOT_CMD(
+ draco_led, CONFIG_SYS_MAXARGS, 2, do_board_led,
+ "Set LEDs defined in environment",
+ "<0|1>"
+);
#endif /* !CONFIG_SPL_BUILD */
endif
-if TARGET_DXR2
+if TARGET_THUBAN
config SYS_BOARD
default "draco"
default "am33xx"
config SYS_CONFIG_NAME
- default "dxr2"
+ default "thuban"
+
+endif
+
+if TARGET_RASTABAN
+
+config SYS_BOARD
+ default "draco"
+
+config SYS_VENDOR
+ default "siemens"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "rastaban"
endif
F: board/siemens/draco/
F: include/configs/draco.h
F: configs/draco_defconfig
-F: include/configs/dxr2.h
-F: configs/dxr2_defconfig
+F: include/configs/thuban.h
+F: configs/thuban_defconfig
+F: include/configs/rastaban.h
+F: configs/rastaban_defconfig
/* Default@303MHz-i0 */
const struct ddr3_data ddr3_default = {
0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
- 0x0079, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
+ 0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32,
0x0000093B, 0x0000014A,
"default name @303MHz \0",
"default marking \0",
printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
printf("device:\t\t%s\n", settings.ddr3.manu_name);
printf("marking:\t%s\n", settings.ddr3.manu_marking);
- printf("timing parameters\n");
- printf("diff\teeprom\tdefault\n");
+ printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom",
+ "default", "diff");
PRINTARGS(magic);
PRINTARGS(version);
PRINTARGS(ddr3_sratio);
static void print_chip_data(void)
{
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
printf("\nCPU BOARD\n");
printf("device: \t'%s'\n", settings.chip.sdevname);
printf("hw version: \t'%s'\n", settings.chip.shwver);
+ printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m);
}
#endif /* CONFIG_SPL_BUILD */
config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
&draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
+
+ /* For Samsung 2Gbit RAM we need this delay otherwise config fails after
+ * soft reset.
+ */
+ udelay(2000);
}
static void spl_siemens_board_init(void)
}
#endif /* if def CONFIG_SPL_BUILD */
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ omap_nand_switch_ecc(1, 8);
+#ifdef CONFIG_FACTORYSET
+ /* Set ASN in environment*/
+ if (factory_dat.asn[0] != 0) {
+ setenv("dtb_name", (char *)factory_dat.asn);
+ } else {
+ /* dtb suffix gets added in load script */
+ setenv("dtb_name", "am335x-draco");
+ }
+#else
+ setenv("dtb_name", "am335x-draco");
+#endif
+
+ return 0;
+}
+#endif
+
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- omap_nand_switch_ecc(1, 8);
-
- return 0;
-}
-#endif
-
#include "../common/board.c"
#ifndef _BOARD_H_
#define _BOARD_H_
-#define PARGS3(x) settings.ddr3.x-ddr3_default.x, \
- settings.ddr3.x, ddr3_default.x
-#define PRINTARGS(y) printf("%x, %8x, %8x : "#y"\n", PARGS3(y))
+#define PARGS(x) #x , /* Parameter Name */ \
+ settings.ddr3.x, /* EEPROM Value */ \
+ ddr3_default.x, /* Default Value */ \
+ settings.ddr3.x-ddr3_default.x /* Difference */
+
+#define PRINTARGS(y) printf("%-20s, %8x, %8x, %4d\n", PARGS(y))
+
#define MAGIC_CHIP 0x50494843
/* Automatic generated definition */
void enable_uart5_pin_mux(void);
void enable_i2c0_pin_mux(void);
void enable_board_pin_mux(void);
+
+/* Forwared declaration, defined in common board.c */
+void set_env_gpios(unsigned char state);
#endif
static struct module_pin_mux gpios_pin_mux[] = {
/* DFU button GPIO0_27*/
- {OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)},
+ {OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
{OFFSET(gpmc_csn3), MODE(7) }, /* LED0 GPIO2_0 */
{OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */
/* Triacs in HW Rev 2 */
{OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS},
{OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS},
/* nRST for SMSC LAN9303 switch - GPIO2_24 */
- {OFFSET(lcd_pclk), MODE(7) }, /* LAN9303 nRST */
+ {OFFSET(lcd_pclk), MODE(7) | PULLUDEN | PULLUP_EN }, /* LAN9303 nRST */
{-1},
};
slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
support for this.
-config SPL_NAND_SUPPORT
- bool "SPL/NAND mode support"
- depends on SPL
- default n
- ---help---
- This enables support for booting from NAND internal
- memory. U-Boot SPL doesn't detect where is it load from,
- therefore this option is needed to properly load image from
- flash. Option also disables MMC functionality on U-Boot due to
- initialization errors encountered, when both controllers are
- enabled.
-
config USB0_VBUS_PIN
string "Vbus enable pin for usb0 (otg)"
default ""
---help---
Set the GMAC Transmit Clock Delay Chain value.
-config SYS_MALLOC_CLEAR_ON_INIT
- default n
-
-config NETDEVICES
- default y
-
-config DM_ETH
- default y
-
-config DM_SERIAL
- default y
-
-config DM_USB
- default y if !USB_MUSB_SUNXI
-
-config CMD_SETEXPR
- default y
-
-config CMD_NET
- default y
-
endif
#ifdef CONFIG_AXP221_POWER
#include <axp221.h>
#endif
-#ifdef CONFIG_NAND_SUNXI
-#include <nand.h>
-#endif
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include <asm/arch/display.h>
}
#endif
-#ifdef CONFIG_NAND
-void board_nand_init(void)
-{
- unsigned int pin;
- static u8 ports[] = CONFIG_NAND_SUNXI_GPC_PORTS;
-
- /* Configure AHB muxes to connect output pins with NAND controller */
- for (pin = 0; pin < 16; pin++)
- sunxi_gpio_set_cfgpin(SUNXI_GPC(pin), SUNXI_GPC_NAND);
-
- for (pin = 0; pin < ARRAY_SIZE(ports); pin++)
- sunxi_gpio_set_cfgpin(SUNXI_GPC(ports[pin]), SUNXI_GPC_NAND);
-}
-#endif
-
void i2c_init_board(void)
{
#ifdef CONFIG_I2C0_ENABLE
F: board/synopsys/axs101/
F: include/configs/axs101.h
F: configs/axs101_defconfig
+F: configs/axs103_defconfig
return 0;
}
+
+#ifdef CONFIG_ISA_ARCV2
+#define RESET_VECTOR_ADDR 0x0
+
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+ /* All cores have reset vector pointing to 0 */
+ writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
+
+ /* Make sure other cores see written value in memory */
+ flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int));
+}
+
+void smp_kick_all_cpus(void)
+{
+/* CPU start CREG */
+#define AXC003_CREG_CPU_START 0xF0001400
+
+/* Bits positions in CPU start CREG */
+#define BITS_START 0
+#define BITS_POLARITY 8
+#define BITS_CORE_SEL 9
+#define BITS_MULTICORE 12
+
+#define CMD (1 << BITS_MULTICORE) | (1 << BITS_CORE_SEL) | \
+ (1 << BITS_POLARITY) | (1 << BITS_START)
+
+ writel(CMD, (void __iomem *)AXC003_CREG_CPU_START);
+}
+#endif
400, 23, 1, -1, 2, -1, -1
};
+static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
+ 0x00500050,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x40001000,
+ 0x08102040
+};
+
const struct ctrl_ioregs ioregs_lpddr2 = {
.cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
.cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
.emif_cos_config = 0x00ffffff
};
+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
+{
+ if (board_is_eposevm()) {
+ *regs = ext_phy_ctrl_const_base_lpddr2;
+ *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
+ }
+
+ return;
+}
+
/*
* get_sys_clk_index : returns the index of the sys_clk read from
* ctrl status register. This value is either
#include <usb.h>
#include <asm/omap_common.h>
#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
#include <asm/arch/clock.h>
+#include <asm/arch/dra7xx_iodelay.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
DECLARE_GLOBAL_DATA_PTR;
+/* GPIO 7_11 */
+#define GPIO_DDR_VTT_EN 203
+
const struct omap_sysinfo sysinfo = {
"Board: BeagleBoard x15\n"
};
.sdram_tim1 = 0xceef266b,
.sdram_tim2 = 0x328f7fda,
.sdram_tim3 = 0x027f88a8,
- .read_idle_ctrl = 0x00050001,
+ .read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190b,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
- .emif_ddr_phy_ctlr_1 = 0x0e24400a,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400b,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
+/* Ext phy ctrl regs 1-35 */
static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
+ 0x10040100,
+ 0x00740074,
+ 0x00780078,
+ 0x007c007c,
+ 0x007b007b,
0x00800080,
0x00360036,
0x00340034,
0x00000000,
0x00600020,
- 0x40010080,
+ 0x40011080,
0x08102040,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
- 0x00400040
+ 0x00400040,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0
};
static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
.sdram_tim1 = 0xceef266b,
.sdram_tim2 = 0x328f7fda,
.sdram_tim3 = 0x027f88a8,
- .read_idle_ctrl = 0x00050001,
+ .read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190b,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
- .emif_ddr_phy_ctlr_1 = 0x0e24400a,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400b,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00820082,
.emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
.emif_ddr_ext_phy_ctrl_4 = 0x00800080,
.emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
+ 0x10040100,
+ 0x00820082,
+ 0x008b008b,
+ 0x00800080,
+ 0x007e007e,
0x00800080,
0x00370037,
0x00390039,
0x00000000,
0x00600020,
- 0x40010080,
+ 0x40011080,
0x08102040,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
- 0x00400040
+ 0x00400040,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0
};
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
return 0;
}
-static void do_set_mux32(u32 base,
- struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_essential(void)
{
- int i;
- struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
-
- for (i = 0; i < size; i++, pad++)
- writel(pad->val, base + pad->offset);
+ do_set_mux32((*ctrl)->control_padconf_core_base,
+ early_padconf, ARRAY_SIZE(early_padconf));
}
-void set_muxconf_regs_essential(void)
+#ifdef CONFIG_IODELAY_RECALIBRATION
+void recalibrate_iodelay(void)
{
- do_set_mux32((*ctrl)->control_padconf_core_base,
- core_padconf_array_essential,
- sizeof(core_padconf_array_essential) /
- sizeof(struct pad_conf_entry));
+ __recalibrate_iodelay(core_padconf_array_essential,
+ ARRAY_SIZE(core_padconf_array_essential),
+ iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array));
}
+#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
return ret;
}
#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+/* VTT regulator enable */
+static inline void vtt_regulator_enable(void)
+{
+ if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
+ return;
+
+ gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
+ gpio_direction_output(GPIO_DDR_VTT_EN, 1);
+}
+
+int board_early_init_f(void)
+{
+ vtt_regulator_enable();
+ return 0;
+}
+#endif
#include <asm/arch/mux_dra7xx.h>
const struct pad_conf_entry core_padconf_array_essential[] = {
- {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
- {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
- {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
- {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
- {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
- {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
- {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
- {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
- {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
- {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
- {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
- {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
- {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
- {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
- {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
- {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
- {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
- {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
- {UART2_CTSN, (FSC | IEN | PTU | PDIS | M2)}, /* uart2_ctsn.uart3_rxd */
- {UART2_RTSN, (FSC | IEN | PTU | PDIS | M1)}, /* uart2_rtsn.uart3_txd */
- {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
- {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
- {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
- {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
- {RGMII0_TXC, (M0) },
- {RGMII0_TXCTL, (M0) },
- {RGMII0_TXD3, (M0) },
- {RGMII0_TXD2, (M0) },
- {RGMII0_TXD1, (M0) },
- {RGMII0_TXD0, (M0) },
- {RGMII0_RXC, (IEN | M0) },
- {RGMII0_RXCTL, (IEN | M0) },
- {RGMII0_RXD3, (IEN | M0) },
- {RGMII0_RXD2, (IEN | M0) },
- {RGMII0_RXD1, (IEN | M0) },
- {RGMII0_RXD0, (IEN | M0) },
- {USB1_DRVVBUS, (M0 | FSC) },
- {SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */
+ {GPMC_AD0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad0.vin3a_d0 */
+ {GPMC_AD1, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad1.vin3a_d1 */
+ {GPMC_AD2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad2.vin3a_d2 */
+ {GPMC_AD3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad3.vin3a_d3 */
+ {GPMC_AD4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad4.vin3a_d4 */
+ {GPMC_AD5, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad5.vin3a_d5 */
+ {GPMC_AD6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad6.vin3a_d6 */
+ {GPMC_AD7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad7.vin3a_d7 */
+ {GPMC_AD8, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad8.vin3a_d8 */
+ {GPMC_AD9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad9.vin3a_d9 */
+ {GPMC_AD10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad10.vin3a_d10 */
+ {GPMC_AD11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad11.vin3a_d11 */
+ {GPMC_AD12, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad12.vin3a_d12 */
+ {GPMC_AD13, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad13.vin3a_d13 */
+ {GPMC_AD14, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad14.vin3a_d14 */
+ {GPMC_AD15, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad15.vin3a_d15 */
+ {GPMC_A0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vin3a_d16 */
+ {GPMC_A1, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a1.vin3a_d17 */
+ {GPMC_A2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vin3a_d18 */
+ {GPMC_A3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vin3a_d19 */
+ {GPMC_A4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vin3a_d20 */
+ {GPMC_A5, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a5.vin3a_d21 */
+ {GPMC_A6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vin3a_d22 */
+ {GPMC_A7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vin3a_d23 */
+ {GPMC_A8, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a8.vin3a_hsync0 */
+ {GPMC_A9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vin3a_vsync0 */
+ {GPMC_A10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vin3a_de0 */
+ {GPMC_A11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a11.vin3a_fld0 */
+ {GPMC_A12, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a12.gpio2_2 */
+ {GPMC_A13, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.gpio2_3 */
+ {GPMC_A14, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a14.gpio2_4 */
+ {GPMC_A15, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.gpio2_5 */
+ {GPMC_A16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.gpio2_6 */
+ {GPMC_A17, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.gpio2_7 */
+ {GPMC_A18, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a18.gpio2_8 */
+ {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
+ {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
+ {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
+ {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
+ {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
+ {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
+ {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
+ {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
+ {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
+ {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
+ {GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs0.gpio2_19 */
+ {GPMC_CS2, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.gpio2_20 */
+ {GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs3.vin3a_clk0 */
+ {GPMC_CLK, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_clk.dma_evt1 */
+ {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */
+ {GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */
+ {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */
+ {GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.dma_evt3 */
+ {GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben1.dma_evt4 */
+ {GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wait0.gpio2_28 */
+ {VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)}, /* vin1b_clk1.gpio2_31 */
+ {VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d2.gpio3_6 */
+ {VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d3.gpio3_7 */
+ {VIN1A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d4.gpio3_8 */
+ {VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d5.gpio3_9 */
+ {VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d6.gpio3_10 */
+ {VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d7.gpio3_11 */
+ {VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d8.gpio3_12 */
+ {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */
+ {VIN1A_D11, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d11.gpio3_15 */
+ {VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d12.gpio3_16 */
+ {VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d14.gpio3_18 */
+ {VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d16.gpio3_20 */
+ {VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d19.gpio3_23 */
+ {VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d20.gpio3_24 */
+ {VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_d21.vin1a_d21 */
+ {VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d22.gpio3_26 */
+ {VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_clk0.gpio3_28 */
+ {VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_de0.gpio3_29 */
+ {VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */
+ {VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_hsync0.pr1_uart0_cts_n */
+ {VIN2A_VSYNC0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_vsync0.pr1_uart0_rts_n */
+ {VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */
+ {VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */
+ {VIN2A_D2, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.uart10_rxd */
+ {VIN2A_D3, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.uart10_txd */
+ {VIN2A_D4, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.uart10_ctsn */
+ {VIN2A_D5, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.uart10_rtsn */
+ {VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.gpio4_7 */
+ {VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.gpio4_8 */
+ {VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.gpio4_9 */
+ {VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.gpio4_10 */
+ {VIN2A_D10, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.ehrpwm2B */
+ {VIN2A_D11, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d11.ehrpwm2_tripzone_input */
+ {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
+ {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */
+ {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */
+ {VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */
+ {VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */
+ {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */
+ {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT_PULLUP)}, /* mdio_d.mdio_d */
+ {RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)}, /* RMII_MHZ_50_CLK.gpio5_17 */
+ {UART3_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_rxd.gpio5_18 */
+ {UART3_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.gpio5_19 */
+ {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
+ {GPIO6_14, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_14.timer1 */
+ {GPIO6_15, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_15.timer2 */
+ {GPIO6_16, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_16.timer3 */
+ {XREF_CLK0, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.clkout2 */
+ {XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.gpio6_18 */
+ {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */
+ {XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
+ {MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkx.i2c3_sda */
+ {MCASP1_FSX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsx.i2c3_scl */
+ {MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.i2c4_sda */
+ {MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.i2c4_scl */
+ {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */
+ {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */
+ {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
+ {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
+ {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
+ {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
+ {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
+ {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
+ {MCASP1_AXR8, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr8.gpio5_10 */
+ {MCASP1_AXR9, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.gpio5_11 */
+ {MCASP1_AXR10, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.gpio5_12 */
+ {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.gpio4_17 */
+ {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr12.mcasp7_axr0 */
+ {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
+ {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.mcasp7_aclkx */
+ {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.mcasp7_fsx */
+ {MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.mcasp2_aclkx */
+ {MCASP2_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.mcasp2_fsx */
+ {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */
+ {MCASP2_FSR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.mcasp2_fsr */
+ {MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.mcasp2_axr0 */
+ {MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.mcasp2_axr1 */
+ {MCASP2_AXR2, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.mcasp2_axr2 */
+ {MCASP2_AXR3, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.mcasp2_axr3 */
+ {MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.mcasp2_axr4 */
+ {MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.mcasp2_axr5 */
+ {MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.mcasp2_axr6 */
+ {MCASP2_AXR7, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.mcasp2_axr7 */
+ {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
+ {MCASP3_FSX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_fsx.mcasp3_fsx */
+ {MCASP3_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr0.mcasp3_axr0 */
+ {MCASP3_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr1.mcasp3_axr1 */
+ {MCASP4_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.uart8_rxd */
+ {MCASP4_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.uart8_txd */
+ {MCASP4_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.uart8_ctsn */
+ {MCASP4_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.uart8_rtsn */
+ {MCASP5_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_aclkx.uart9_rxd */
+ {MCASP5_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_fsx.uart9_txd */
+ {MCASP5_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.uart9_ctsn */
+ {MCASP5_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_axr1.uart9_rtsn */
+ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
+ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
+ {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
+ {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
+ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
+ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
+ {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.mmc1_sdcd */
+ {MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */
+ {GPIO6_10, (M10 | PIN_INPUT_PULLDOWN)}, /* gpio6_10.ehrpwm2A */
+ {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
+ {MMC3_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_clk.mmc3_clk */
+ {MMC3_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.mmc3_cmd */
+ {MMC3_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.mmc3_dat0 */
+ {MMC3_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.mmc3_dat1 */
+ {MMC3_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.mmc3_dat2 */
+ {MMC3_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat3.mmc3_dat3 */
+ {MMC3_DAT4, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.spi4_sclk */
+ {MMC3_DAT5, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.spi4_d1 */
+ {MMC3_DAT6, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.spi4_d0 */
+ {MMC3_DAT7, (M1 | PIN_INPUT_PULLUP)}, /* mmc3_dat7.spi4_cs0 */
+ {SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */
+ {SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */
+ {SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */
+ {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
+ {SPI1_CS1, (M14 | PIN_OUTPUT_PULLUP)}, /* spi1_cs1.gpio7_11 */
+ {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
+ {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
+ {SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.gpio7_14 */
+ {SPI2_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_d1.gpio7_15 */
+ {SPI2_D0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_d0.gpio7_16 */
+ {SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.gpio7_17 */
+ {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */
+ {DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */
+ {UART1_RXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_rxd.uart1_rxd */
+ {UART1_TXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_txd.uart1_txd */
+ {UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.Driveroff */
+ {UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)}, /* N/A.Driveroff */
+ {UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)}, /* uart2_txd.Driveroff */
+ {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */
+ {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
+ {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
+ {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
+ {WAKEUP0, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup0.Wakeup0 */
+ {WAKEUP1, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup1.Wakeup1 */
+ {WAKEUP2, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup2.Wakeup2 */
+ {WAKEUP3, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup3.Wakeup3 */
+ {ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */
+ {RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */
+ {RTCK, (M0 | PIN_INPUT_PULLDOWN)}, /* rtck.rtck */
};
+
+const struct pad_conf_entry early_padconf[] = {
+ {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */
+ {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
+ {I2C1_SDA, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SDA */
+ {I2C1_SCL, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SCL */
+};
+
+#ifdef CONFIG_IODELAY_RECALIBRATION
+const struct iodelay_cfg_entry iodelay_cfg_array[] = {
+ {0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */
+ {0x0120, 2648, 0}, /* CFG_GPMC_A10_IN */
+ {0x012C, 2918, 0}, /* CFG_GPMC_A11_IN */
+ {0x0198, 2917, 0}, /* CFG_GPMC_A1_IN */
+ {0x0204, 3156, 178}, /* CFG_GPMC_A2_IN */
+ {0x0210, 3109, 246}, /* CFG_GPMC_A3_IN */
+ {0x021C, 3142, 100}, /* CFG_GPMC_A4_IN */
+ {0x0228, 3084, 33}, /* CFG_GPMC_A5_IN */
+ {0x0234, 2778, 0}, /* CFG_GPMC_A6_IN */
+ {0x0240, 3110, 0}, /* CFG_GPMC_A7_IN */
+ {0x024C, 2874, 0}, /* CFG_GPMC_A8_IN */
+ {0x0258, 3072, 0}, /* CFG_GPMC_A9_IN */
+ {0x0264, 2466, 0}, /* CFG_GPMC_AD0_IN */
+ {0x0270, 2523, 0}, /* CFG_GPMC_AD10_IN */
+ {0x027C, 2453, 0}, /* CFG_GPMC_AD11_IN */
+ {0x0288, 2285, 0}, /* CFG_GPMC_AD12_IN */
+ {0x0294, 2206, 0}, /* CFG_GPMC_AD13_IN */
+ {0x02A0, 1898, 0}, /* CFG_GPMC_AD14_IN */
+ {0x02AC, 2473, 0}, /* CFG_GPMC_AD15_IN */
+ {0x02B8, 2307, 0}, /* CFG_GPMC_AD1_IN */
+ {0x02C4, 2691, 0}, /* CFG_GPMC_AD2_IN */
+ {0x02D0, 2384, 0}, /* CFG_GPMC_AD3_IN */
+ {0x02DC, 2462, 0}, /* CFG_GPMC_AD4_IN */
+ {0x02E8, 2335, 0}, /* CFG_GPMC_AD5_IN */
+ {0x02F4, 2370, 0}, /* CFG_GPMC_AD6_IN */
+ {0x0300, 2389, 0}, /* CFG_GPMC_AD7_IN */
+ {0x030C, 2672, 0}, /* CFG_GPMC_AD8_IN */
+ {0x0318, 2334, 0}, /* CFG_GPMC_AD9_IN */
+ {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 531, 120}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 11, 60}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 7, 120}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 276, 120}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 440, 120}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0A70, 1551, 115}, /* CFG_VIN2A_D12_OUT */
+ {0x0A7C, 816, 0}, /* CFG_VIN2A_D13_OUT */
+ {0x0A88, 876, 0}, /* CFG_VIN2A_D14_OUT */
+ {0x0A94, 312, 0}, /* CFG_VIN2A_D15_OUT */
+ {0x0AA0, 58, 0}, /* CFG_VIN2A_D16_OUT */
+ {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */
+ {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */
+ {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
+ {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
+ {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
+ {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
+};
+#endif
#endif /* _MUX_DATA_BEAGLE_X15_H_ */
#include <usb.h>
#include <linux/usb/gadget.h>
#include <asm/arch/gpio.h>
+#include <asm/arch/dra7xx_iodelay.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
"Board: DRA7xx\n"
};
-/*
- * Adjust I/O delays on the Tx control and data lines of each MAC port. This
- * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
- * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
- * essentially need to counteract the DRA7xx internal delay, and we do this
- * by delaying the control and data lines. If not using this PHY, you probably
- * don't need to do this stuff!
- */
-static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
-{
- int i = 0;
- u32 reg_val;
- u32 delta;
- u32 coarse;
- u32 fine;
-
- writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
-
- while(io_dly[i].addr) {
- writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
- io_dly[i].addr);
- delta = io_dly[i].dly;
- reg_val = readl(io_dly[i].addr) & 0x3ff;
- coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
- coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
- fine = (reg_val & 0x1F) + (delta & 0x1F);
- fine = (fine > 0x1F) ? (0x1F) : (fine);
- reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
- CFG_IO_DELAY_LOCK_MASK |
- ((coarse << 5) | (fine));
- writel(reg_val, io_dly[i].addr);
- i++;
- }
-
- writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
-}
-
/**
* @brief board_init
*
return 0;
}
-static void do_set_mux32(u32 base,
- struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_essential(void)
{
- int i;
- struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
-
- for (i = 0; i < size; i++, pad++)
- writel(pad->val, base + pad->offset);
+ do_set_mux32((*ctrl)->control_padconf_core_base,
+ early_padconf, ARRAY_SIZE(early_padconf));
}
-void set_muxconf_regs_essential(void)
+#ifdef CONFIG_IODELAY_RECALIBRATION
+void recalibrate_iodelay(void)
{
- do_set_mux32((*ctrl)->control_padconf_core_base,
- core_padconf_array_essential,
- sizeof(core_padconf_array_essential) /
- sizeof(struct pad_conf_entry));
+ if (is_dra72x()) {
+ __recalibrate_iodelay(core_padconf_array_essential,
+ ARRAY_SIZE(core_padconf_array_essential),
+ iodelay_cfg_array,
+ ARRAY_SIZE(iodelay_cfg_array));
+ } else {
+ __recalibrate_iodelay(dra74x_core_padconf_array,
+ ARRAY_SIZE(dra74x_core_padconf_array),
+ dra742_iodelay_cfg_array,
+ ARRAY_SIZE(dra742_iodelay_cfg_array));
+ }
}
+#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
#endif
#ifdef CONFIG_DRIVER_TI_CPSW
-
-/* Delay value to add to calibrated value */
-#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
-#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
-#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
-#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
-#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
-#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
-#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
-#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
-#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
-#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
-
extern u32 *const omap_si_rev;
static void cpsw_control(int enabled)
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
uint32_t ctrl_val;
- const struct io_delay io_dly[] = {
- {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
- {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
- {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
- {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
- {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
- {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
- {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
- {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
- {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
- {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
- {0}
- };
-
- /* Adjust IO delay for RGMII tx path */
- dra7xx_adj_io_delay(io_dly);
/* try reading mac address from efuse */
mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
{I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
{MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
{MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
- {RGMII0_TXC, (M0) },
- {RGMII0_TXCTL, (M0) },
- {RGMII0_TXD3, (M0) },
- {RGMII0_TXD2, (M0) },
- {RGMII0_TXD1, (M0) },
- {RGMII0_TXD0, (M0) },
- {RGMII0_RXC, (IEN | M0) },
- {RGMII0_RXCTL, (IEN | M0) },
- {RGMII0_RXD3, (IEN | M0) },
- {RGMII0_RXD2, (IEN | M0) },
- {RGMII0_RXD1, (IEN | M0) },
- {RGMII0_RXD0, (IEN | M0) },
- {VIN2A_D12, (M3) },
- {VIN2A_D13, (M3) },
- {VIN2A_D14, (M3) },
- {VIN2A_D15, (M3) },
- {VIN2A_D16, (M3) },
- {VIN2A_D17, (M3) },
- {VIN2A_D18, (IEN | M3)},
- {VIN2A_D19, (IEN | M3)},
- {VIN2A_D20, (IEN | M3)},
- {VIN2A_D21, (IEN | M3)},
- {VIN2A_D22, (IEN | M3)},
- {VIN2A_D23, (IEN | M3)},
+ {RGMII0_TXC, (PIN_OUTPUT | MANUAL_MODE | M0) },
+ {RGMII0_TXCTL, (PIN_OUTPUT | MANUAL_MODE | M0) },
+ {RGMII0_TXD3, (PIN_OUTPUT | MANUAL_MODE | M0) },
+ {RGMII0_TXD2, (PIN_OUTPUT | MANUAL_MODE | M0) },
+ {RGMII0_TXD1, (PIN_OUTPUT | MANUAL_MODE | M0) },
+ {RGMII0_TXD0, (PIN_OUTPUT | MANUAL_MODE | M0) },
+ {RGMII0_RXC, (PIN_INPUT | MANUAL_MODE | M0) },
+ {RGMII0_RXCTL, (PIN_INPUT | MANUAL_MODE | M0) },
+ {RGMII0_RXD3, (PIN_INPUT | MANUAL_MODE | M0) },
+ {RGMII0_RXD2, (PIN_INPUT | MANUAL_MODE | M0) },
+ {RGMII0_RXD1, (PIN_INPUT | MANUAL_MODE | M0) },
+ {RGMII0_RXD0, (PIN_INPUT | MANUAL_MODE | M0) },
+ {VIN2A_D12, (PIN_OUTPUT | MANUAL_MODE | M3) },
+ {VIN2A_D13, (PIN_OUTPUT | MANUAL_MODE | M3) },
+ {VIN2A_D14, (PIN_OUTPUT | MANUAL_MODE | M3) },
+ {VIN2A_D15, (PIN_OUTPUT | MANUAL_MODE | M3) },
+ {VIN2A_D16, (PIN_OUTPUT | MANUAL_MODE | M3) },
+ {VIN2A_D17, (PIN_OUTPUT | MANUAL_MODE | M3) },
+ {VIN2A_D18, (PIN_INPUT | MANUAL_MODE | M3)},
+ {VIN2A_D19, (PIN_INPUT | MANUAL_MODE | M3)},
+ {VIN2A_D20, (PIN_INPUT | MANUAL_MODE | M3)},
+ {VIN2A_D21, (PIN_INPUT | MANUAL_MODE | M3)},
+ {VIN2A_D22, (PIN_INPUT | MANUAL_MODE | M3)},
+ {VIN2A_D23, (PIN_INPUT | MANUAL_MODE | M3)},
#if defined(CONFIG_NAND) || defined(CONFIG_NOR)
/* NAND / NOR pin-mux */
{GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */
{USB2_DRVVBUS, (M0 | IEN | FSC) },
{SPI1_CS1, (PEN | IDIS | M14) },
};
+
+const struct pad_conf_entry early_padconf[] = {
+#if (CONFIG_CONS_INDEX == 1)
+ {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */
+ {UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */
+#elif (CONFIG_CONS_INDEX == 3)
+ {UART3_RXD, (PIN_INPUT_SLEW | M0)}, /* UART3_RXD */
+ {UART3_TXD, (PIN_INPUT_SLEW | M0)}, /* UART3_TXD */
+#endif
+ {I2C1_SDA, (PIN_INPUT | M0)}, /* I2C1_SDA */
+ {I2C1_SCL, (PIN_INPUT | M0)}, /* I2C1_SCL */
+};
+
+#ifdef CONFIG_IODELAY_RECALIBRATION
+const struct iodelay_cfg_entry iodelay_cfg_array[] = {
+ {0x6F0, 480, 0}, /* RGMMI0_RXC_IN */
+ {0x6FC, 111, 1641}, /* RGMMI0_RXCTL_IN */
+ {0x708, 272, 1116}, /* RGMMI0_RXD0_IN */
+ {0x714, 243, 1260}, /* RGMMI0_RXD1_IN */
+ {0x720, 0, 1614}, /* RGMMI0_RXD2_IN */
+ {0x72C, 105, 1673}, /* RGMMI0_RXD3_IN */
+ {0x740, 531, 120}, /* RGMMI0_TXC_OUT */
+ {0x74C, 11, 60}, /* RGMMI0_TXCTL_OUT */
+ {0x758, 7, 120}, /* RGMMI0_TXD0_OUT */
+ {0x764, 0, 0}, /* RGMMI0_TXD1_OUT */
+ {0x770, 276, 120}, /* RGMMI0_TXD2_OUT */
+ {0x77C, 440, 120}, /* RGMMI0_TXD3_OUT */
+ {0xAB0, 702, 0}, /* CFG_VIN2A_D18_IN */
+ {0xABC, 136, 976}, /* CFG_VIN2A_D19_IN */
+ {0xAD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
+ {0xAE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
+ {0xAEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
+ {0xAF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
+ {0xA70, 1551, 115}, /* CFG_VIN2A_D12_OUT */
+ {0xA7C, 816, 0}, /* CFG_VIN2A_D13_OUT */
+ {0xA88, 876, 0}, /* CFG_VIN2A_D14_OUT */
+ {0xA94, 312, 0}, /* CFG_VIN2A_D15_OUT */
+ {0xAA0, 58, 0}, /* CFG_VIN2A_D16_OUT */
+ {0xAAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
+};
+#endif
+
+const struct pad_conf_entry dra74x_core_padconf_array[] = {
+ {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
+ {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
+ {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
+ {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
+ {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
+ {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
+ {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
+ {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
+ {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
+ {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
+ {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
+ {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
+ {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
+ {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
+ {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
+ {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
+ {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
+ {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
+ {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
+ {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
+ {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
+ {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
+ {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
+ {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
+ {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
+ {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
+ {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
+ {GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */
+ {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.qspi1_rtclk */
+ {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a14.qspi1_d3 */
+ {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.qspi1_d2 */
+ {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.qspi1_d0 */
+ {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.qspi1_d1 */
+ {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a18.qspi1_sclk */
+ {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
+ {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
+ {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
+ {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
+ {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
+ {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
+ {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
+ {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
+ {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
+ {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
+ {GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.qspi1_cs0 */
+ {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
+ {VIN1A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_clk0.vin1a_clk0 */
+ {VIN1A_DE0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_de0.vin1a_de0 */
+ {VIN1A_FLD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_fld0.vin1a_fld0 */
+ {VIN1A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_hsync0.vin1a_hsync0 */
+ {VIN1A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_vsync0.vin1a_vsync0 */
+ {VIN1A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d0.vin1a_d0 */
+ {VIN1A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d1.vin1a_d1 */
+ {VIN1A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d2.vin1a_d2 */
+ {VIN1A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d3.vin1a_d3 */
+ {VIN1A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d4.vin1a_d4 */
+ {VIN1A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d5.vin1a_d5 */
+ {VIN1A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d6.vin1a_d6 */
+ {VIN1A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d7.vin1a_d7 */
+ {VIN1A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d8.vin1a_d8 */
+ {VIN1A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d9.vin1a_d9 */
+ {VIN1A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d10.vin1a_d10 */
+ {VIN1A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d11.vin1a_d11 */
+ {VIN1A_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d12.vin1a_d12 */
+ {VIN1A_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d13.vin1a_d13 */
+ {VIN1A_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d14.vin1a_d14 */
+ {VIN1A_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d15.vin1a_d15 */
+ {VIN1A_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d16.vin1a_d16 */
+ {VIN1A_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d17.vin1a_d17 */
+ {VIN1A_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d18.vin1a_d18 */
+ {VIN1A_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d19.vin1a_d19 */
+ {VIN1A_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d20.vin1a_d20 */
+ {VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d21.vin1a_d21 */
+ {VIN1A_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d22.vin1a_d22 */
+ {VIN1A_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d23.vin1a_d23 */
+ {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
+ {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */
+ {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */
+ {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */
+ {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
+ {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
+ {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
+ {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
+ {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
+ {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
+ {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
+ {MCASP1_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.mcasp1_aclkx */
+ {MCASP1_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.mcasp1_fsx */
+ {MCASP1_AXR0, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE15)}, /* mcasp1_axr0.mcasp1_axr0 */
+ {MCASP1_AXR1, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.mcasp1_axr1 */
+ {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
+ {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
+ {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
+ {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
+ {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
+ {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
+ {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
+ {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
+ {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
+ {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
+ {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */
+ {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
+ {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
+ {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
+ {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
+ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
+ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
+ {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
+ {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
+ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
+ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
+ {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.mmc1_sdcd */
+ {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
+ {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
+ {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
+ {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
+ {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
+ {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
+ {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
+ {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
+ {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
+ {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
+ {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
+ {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
+ {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
+ {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */
+ {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */
+ {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
+ {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
+ {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
+ {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
+ {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* N/A.mmc4_dat0 */
+ {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
+ {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
+ {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
+ {I2C2_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_sda.i2c2_sda */
+ {I2C2_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_scl.i2c2_scl */
+ {WAKEUP0, (M1 | PIN_OUTPUT)}, /* Wakeup0.dcan1_rx */
+ {WAKEUP2, (M14 | PIN_OUTPUT)}, /* Wakeup2.gpio1_2 */
+};
+
+#ifdef CONFIG_IODELAY_RECALIBRATION
+const struct iodelay_cfg_entry dra742_iodelay_cfg_array[] = {
+ {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 0, 0}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 1560, 120}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 1570, 120}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 1500, 120}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 1775, 120}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 1875, 120}, /* CFG_RGMII0_TXD3_OUT */
+ {0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */
+ {0x08DC, 2600, 0}, /* CFG_VIN1A_D0_IN */
+ {0x08E8, 2652, 46}, /* CFG_VIN1A_D10_IN */
+ {0x08F4, 2541, 0}, /* CFG_VIN1A_D11_IN */
+ {0x0900, 2603, 574}, /* CFG_VIN1A_D12_IN */
+ {0x090C, 2548, 443}, /* CFG_VIN1A_D13_IN */
+ {0x0918, 2624, 598}, /* CFG_VIN1A_D14_IN */
+ {0x0924, 2535, 1027}, /* CFG_VIN1A_D15_IN */
+ {0x0930, 2526, 818}, /* CFG_VIN1A_D16_IN */
+ {0x093C, 2623, 797}, /* CFG_VIN1A_D17_IN */
+ {0x0948, 2578, 888}, /* CFG_VIN1A_D18_IN */
+ {0x0954, 2574, 1008}, /* CFG_VIN1A_D19_IN */
+ {0x0960, 2527, 123}, /* CFG_VIN1A_D1_IN */
+ {0x096C, 2577, 737}, /* CFG_VIN1A_D20_IN */
+ {0x0978, 2627, 616}, /* CFG_VIN1A_D21_IN */
+ {0x0984, 2573, 777}, /* CFG_VIN1A_D22_IN */
+ {0x0990, 2730, 67}, /* CFG_VIN1A_D23_IN */
+ {0x099C, 2509, 303}, /* CFG_VIN1A_D2_IN */
+ {0x09A8, 2494, 267}, /* CFG_VIN1A_D3_IN */
+ {0x09B4, 2474, 0}, /* CFG_VIN1A_D4_IN */
+ {0x09C0, 2556, 181}, /* CFG_VIN1A_D5_IN */
+ {0x09CC, 2516, 195}, /* CFG_VIN1A_D6_IN */
+ {0x09D8, 2589, 210}, /* CFG_VIN1A_D7_IN */
+ {0x09E4, 2624, 75}, /* CFG_VIN1A_D8_IN */
+ {0x09F0, 2704, 14}, /* CFG_VIN1A_D9_IN */
+ {0x09FC, 2469, 55}, /* CFG_VIN1A_DE0_IN */
+ {0x0A08, 2557, 264}, /* CFG_VIN1A_FLD0_IN */
+ {0x0A14, 2465, 269}, /* CFG_VIN1A_HSYNC0_IN */
+ {0x0A20, 2411, 348}, /* CFG_VIN1A_VSYNC0_IN */
+ {0x0A70, 150, 0}, /* CFG_VIN2A_D12_OUT */
+ {0x0A7C, 1500, 0}, /* CFG_VIN2A_D13_OUT */
+ {0x0A88, 1600, 0}, /* CFG_VIN2A_D14_OUT */
+ {0x0A94, 900, 0}, /* CFG_VIN2A_D15_OUT */
+ {0x0AA0, 680, 0}, /* CFG_VIN2A_D16_OUT */
+ {0x0AAC, 500, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */
+ {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */
+ {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
+ {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
+ {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
+ {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
+};
+#endif
+
#endif /* _MUX_DATA_DRA7XX_H_ */
--- /dev/null
+if TARGET_AM335X_BALTOS
+
+config SYS_BOARD
+ default "baltos"
+
+config SYS_VENDOR
+ default "vscom"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "baltos"
+
+config CONS_INDEX
+ int "UART used for console"
+ range 1 6
+ default 1
+ help
+ The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+ in documentation, etc) available to it. Depending on your specific
+ board you may want something other than UART0.
+
+endif
--- /dev/null
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y := mux.o
+endif
+
+obj-y += board.o
--- /dev/null
+BSP for VScom OnRISC Balios family devices, like Balios iR 5221.
--- /dev/null
+/*
+ * board.c
+ *
+ * Board functions for TI AM335X based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include <power/tps65910.h>
+#include <environment.h>
+#include <watchdog.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO that controls power to DDR on EVM-SK */
+#define GPIO_DDR_VTT_EN 7
+#define DIP_S1 44
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+static int baltos_set_console(void)
+{
+ int val, i, dips = 0;
+ char buf[7];
+
+ for (i = 0; i < 4; i++) {
+ sprintf(buf, "dip_s%d", i + 1);
+
+ if (gpio_request(DIP_S1 + i, buf)) {
+ printf("failed to export GPIO %d\n", DIP_S1 + i);
+ return 0;
+ }
+
+ if (gpio_direction_input(DIP_S1 + i)) {
+ printf("failed to set GPIO %d direction\n", DIP_S1 + i);
+ return 0;
+ }
+
+ val = gpio_get_value(DIP_S1 + i);
+ dips |= val << i;
+ }
+
+ printf("DIPs: 0x%1x\n", (~dips) & 0xf);
+
+ if ((dips & 0xf) == 0xe)
+ setenv("console", "ttyUSB0,115200n8");
+
+ return 0;
+}
+
+static int read_eeprom(BSP_VS_HWPARAM *header)
+{
+ i2c_set_bus_num(1);
+
+ /* Check if baseboard eeprom is available */
+ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+ puts("Could not probe the EEPROM; something fundamentally "
+ "wrong on the I2C bus.\n");
+ return -ENODEV;
+ }
+
+ /* read the eeprom using i2c */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
+ sizeof(BSP_VS_HWPARAM))) {
+ puts("Could not read the EEPROM; something fundamentally"
+ " wrong on the I2C bus.\n");
+ return -EIO;
+ }
+
+ if (header->Magic != 0xDEADBEEF) {
+
+ printf("Incorrect magic number (0x%x) in EEPROM\n",
+ header->Magic);
+
+ /* fill default values */
+ header->SystemId = 211;
+ header->MAC1[0] = 0x00;
+ header->MAC1[1] = 0x00;
+ header->MAC1[2] = 0x00;
+ header->MAC1[3] = 0x00;
+ header->MAC1[4] = 0x00;
+ header->MAC1[5] = 0x01;
+
+ header->MAC2[0] = 0x00;
+ header->MAC2[1] = 0x00;
+ header->MAC2[2] = 0x00;
+ header->MAC2[3] = 0x00;
+ header->MAC2[4] = 0x00;
+ header->MAC2[5] = 0x02;
+
+ header->MAC3[0] = 0x00;
+ header->MAC3[1] = 0x00;
+ header->MAC3[2] = 0x00;
+ header->MAC3[3] = 0x00;
+ header->MAC3[4] = 0x00;
+ header->MAC3[5] = 0x03;
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+
+static const struct ddr_data ddr3_baltos_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_baltos_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ return (serial_tstc() && serial_getc() == 'c');
+}
+#endif
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+ 266, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_evm_sk = {
+ 303, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_baltos = {
+ 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ int mpu_vdd;
+ int sil_rev;
+
+ /* Get the frequency */
+ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+ /*
+ * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
+ * MPU frequencies we support we use a CORE voltage of
+ * 1.1375V. For MPU voltage we need to switch based on
+ * the frequency we are running at.
+ */
+ i2c_set_bus_num(1);
+
+ if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
+ puts("i2c: cannot access TPS65910\n");
+ return;
+ }
+
+ /*
+ * Depending on MPU clock and PG we will need a different
+ * VDD to drive at that speed.
+ */
+ sil_rev = readl(&cdev->deviceid) >> 28;
+ mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
+ dpll_mpu_opp100.m);
+
+ /* Tell the TPS65910 to use i2c */
+ tps65910_set_i2c_control();
+
+ /* First update MPU voltage. */
+ if (tps65910_voltage_update(MPU, mpu_vdd))
+ return;
+
+ /* Second, update the CORE voltage. */
+ if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
+ return;
+
+ /* Set CORE Frequencies to OPP100 */
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+ /* Set MPU Frequency to what we detected now that voltages are set */
+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+
+ writel(0x000010ff, PRM_DEVICE_INST + 4);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ enable_i2c1_pin_mux();
+ i2c_set_bus_num(1);
+
+ return &dpll_ddr_baltos;
+}
+
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ enable_board_pin_mux();
+}
+
+const struct ctrl_ioregs ioregs_baltos = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+ gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
+ gpio_direction_output(GPIO_DDR_VTT_EN, 1);
+
+ config_ddr(400, &ioregs_baltos,
+ &ddr3_baltos_data,
+ &ddr3_baltos_cmd_ctrl_data,
+ &ddr3_baltos_emif_reg_data, 0);
+}
+#endif
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+ hw_watchdog_init();
+#endif
+
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
+ gpmc_init();
+#endif
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int node, ret;
+ unsigned char mac_addr[6];
+ BSP_VS_HWPARAM header;
+
+ /* get production data */
+ if (read_eeprom(&header))
+ return 0;
+
+ /* setup MAC1 */
+ mac_addr[0] = header.MAC1[0];
+ mac_addr[1] = header.MAC1[1];
+ mac_addr[2] = header.MAC1[2];
+ mac_addr[3] = header.MAC1[3];
+ mac_addr[4] = header.MAC1[4];
+ mac_addr[5] = header.MAC1[5];
+
+
+ node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200");
+ if (node < 0) {
+ printf("no /soc/fman/ethernet path offset\n");
+ return -ENODEV;
+ }
+
+ ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
+ if (ret) {
+ printf("error setting local-mac-address property\n");
+ return -ENODEV;
+ }
+
+ /* setup MAC2 */
+ mac_addr[0] = header.MAC2[0];
+ mac_addr[1] = header.MAC2[1];
+ mac_addr[2] = header.MAC2[2];
+ mac_addr[3] = header.MAC2[3];
+ mac_addr[4] = header.MAC2[4];
+ mac_addr[5] = header.MAC2[5];
+
+ node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300");
+ if (node < 0) {
+ printf("no /soc/fman/ethernet path offset\n");
+ return -ENODEV;
+ }
+
+ ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
+ if (ret) {
+ printf("error setting local-mac-address property\n");
+ return -ENODEV;
+ }
+
+ printf("\nFDT was successfully setup\n");
+
+ return 0;
+}
+
+static struct module_pin_mux dip_pin_mux[] = {
+ {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */
+ {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */
+ {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */
+ {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */
+ {-1},
+};
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ BSP_VS_HWPARAM header;
+ char model[4];
+
+ /* get production data */
+ if (read_eeprom(&header)) {
+ sprintf(model, "211");
+ } else {
+ sprintf(model, "%d", header.SystemId);
+ if (header.SystemId == 215) {
+ configure_module_pin_mux(dip_pin_mux);
+ baltos_set_console();
+ }
+ }
+ setenv("board_name", model);
+#endif
+
+ return 0;
+}
+#endif
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 7,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 2,
+ .slave_data = cpsw_slaves,
+ .active_slave = 1,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+#endif
+
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
+ && defined(CONFIG_SPL_BUILD)) || \
+ ((defined(CONFIG_DRIVER_TI_CPSW) || \
+ defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
+ !defined(CONFIG_SPL_BUILD))
+int board_eth_init(bd_t *bis)
+{
+ int rv, n = 0;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+ __maybe_unused struct am335x_baseboard_id header;
+
+ /*
+ * Note here that we're using CPSW1 since that has a 1Gbit PHY while
+ * CSPW0 has a 100Mbit PHY.
+ *
+ * On product, CPSW1 maps to port labeled WAN.
+ */
+
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid1l);
+ mac_hi = readl(&cdev->macid1h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+ if (is_valid_ethaddr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+ writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
+ cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+#endif
+
+ /*
+ *
+ * CPSW RGMII Internal Delay Mode is not supported in all PVT
+ * operating points. So we must set the TX clock delay feature
+ * in the AR8051 PHY. Since we only support a single ethernet
+ * device in U-Boot, we only do this for the first instance.
+ */
+#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
+#define AR8051_PHY_DEBUG_DATA_REG 0x1e
+#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
+#define AR8051_RGMII_TX_CLK_DLY 0x100
+ const char *devname;
+ devname = miiphy_get_current_dev();
+
+ miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
+ AR8051_DEBUG_RGMII_CLK_DLY_REG);
+ miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
+ AR8051_RGMII_TX_CLK_DLY);
+#endif
+ return n;
+}
+#endif
--- /dev/null
+/*
+ * board.h
+ *
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * TI AM335x parts define a system EEPROM that defines certain sub-fields.
+ * We use these fields to in turn see what board we are on, and what
+ * that might require us to set or not set.
+ */
+#define HDR_NO_OF_MAC_ADDR 3
+#define HDR_ETH_ALEN 6
+#define HDR_NAME_LEN 8
+
+struct am335x_baseboard_id {
+ unsigned int magic;
+ char name[HDR_NAME_LEN];
+ char version[4];
+ char serial[12];
+ char config[32];
+ char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
+};
+
+typedef struct _BSP_VS_HWPARAM // v1.0
+{
+ uint32_t Magic;
+ uint32_t HwRev;
+ uint32_t SerialNumber;
+ char PrdDate[11]; // as a string ie. "01.01.2006"
+ uint16_t SystemId;
+ uint8_t MAC1[6]; // internal EMAC
+ uint8_t MAC2[6]; // SMSC9514
+ uint8_t MAC3[6]; // WL1271 WLAN
+} __attribute__ ((packed)) BSP_VS_HWPARAM;
+
+static inline int board_is_bone(struct am335x_baseboard_id *header)
+{
+ return !strncmp(header->name, "A335BONE", HDR_NAME_LEN);
+}
+
+static inline int board_is_bone_lt(struct am335x_baseboard_id *header)
+{
+ return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN);
+}
+
+static inline int board_is_evm_sk(struct am335x_baseboard_id *header)
+{
+ return !strncmp("A335X_SK", header->name, HDR_NAME_LEN);
+}
+
+static inline int board_is_idk(struct am335x_baseboard_id *header)
+{
+ return !strncmp(header->config, "SKU#02", 6);
+}
+
+static inline int board_is_gp_evm(struct am335x_baseboard_id *header)
+{
+ return !strncmp("A33515BB", header->name, HDR_NAME_LEN);
+}
+
+static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header)
+{
+ return (board_is_gp_evm(header) &&
+ strncmp("1.5", header->version, 3) <= 0);
+}
+
+/*
+ * We have three pin mux functions that must exist. We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_i2c1_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
--- /dev/null
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+ {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
+ {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart2_pin_mux[] = {
+ {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
+ {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+ {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+ {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
+ {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart5_pin_mux[] = {
+ {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
+ {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ //{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+ {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static struct module_pin_mux gpio0_7_pin_mux[] = {
+ {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
+ {-1},
+};
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+ {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
+ {OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */
+ {OFFSET(mii1_txd1), MODE(1)}, /* RGMII1_TCTL */
+ {OFFSET(mii1_txd0), MODE(1)}, /* RGMII1_TCTL */
+ {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
+ {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
+ {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RGMII1_TCTL */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux rgmii2_pin_mux[] = {
+ {OFFSET(gpmc_a0), MODE(2)}, /* RGMII1_TCTL */
+ {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
+ {OFFSET(gpmc_a2), MODE(2)}, /* RGMII1_TD3 */
+ {OFFSET(gpmc_a3), MODE(2)}, /* RGMII1_TD2 */
+ {OFFSET(gpmc_a4), MODE(2)}, /* RGMII1_TD1 */
+ {OFFSET(gpmc_a5), MODE(2)}, /* RGMII1_TD0 */
+ {OFFSET(gpmc_a6), MODE(2)}, /* RGMII1_TCLK */
+ {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
+ {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
+ {OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
+ {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
+ {OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+ configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+ configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+ configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+ configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+ configure_module_pin_mux(uart5_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_i2c1_pin_mux(void)
+{
+ configure_module_pin_mux(i2c1_pin_mux);
+}
+
+void enable_board_pin_mux()
+{
+ /* Baltos */
+ configure_module_pin_mux(i2c1_pin_mux);
+ configure_module_pin_mux(gpio0_7_pin_mux);
+ configure_module_pin_mux(rgmii2_pin_mux);
+ configure_module_pin_mux(rmii1_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+
+#if defined(CONFIG_NAND)
+ configure_module_pin_mux(nand_pin_mux);
+#endif
+}
--- /dev/null
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.__image_copy_start)
+ *(.vectors)
+ CPUDIR/start.o (.text*)
+ board/vscom/baltos/built-in.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ }
+
+ .hash : { *(.hash*) }
+
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
+
+ /*
+ * Deprecated: this MMU section is used by pxa at present but
+ * should not be used by new boards/CPUs.
+ */
+ . = ALIGN(4096);
+ .mmutable : {
+ *(.mmutable)
+ }
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ __bss_base = .;
+ }
+
+ .bss __bss_base (OVERLAY) : {
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_limit = .;
+ }
+
+ .bss_end __bss_limit (OVERLAY) : {
+ KEEP(*(.__bss_end));
+ }
+
+ .dynsym _image_binary_end : { *(.dynsym) }
+ .dynbss : { *(.dynbss) }
+ .dynstr : { *(.dynstr*) }
+ .dynamic : { *(.dynamic*) }
+ .gnu.hash : { *(.gnu.hash) }
+ .plt : { *(.plt*) }
+ .interp : { *(.interp*) }
+ .gnu : { *(.gnu*) }
+ .ARM.exidx : { *(.ARM.exidx*) }
+}
config CMD_BDI
bool "bdinfo"
+ default y
help
Print board info
config CMD_CONSOLE
bool "coninfo"
+ default y
help
Print console devices and information.
config CMD_BOOTD
bool "bootd"
+ default y
help
Run the command stored in the environment "bootcmd", i.e.
"bootd" does the same thing as "run bootcmd".
config CMD_RUN
bool "run"
+ default y
help
Run the command in the given environment variable.
config CMD_IMI
bool "iminfo"
+ default y
help
Print header information for application image.
config CMD_IMLS
bool "imls"
+ default y
help
List all images found in flash
config CMD_XIMG
bool "imxtract"
+ default y
help
Extract a part of a multi-image.
config CMD_EDITENV
bool "editenv"
+ default y
help
Edit environment variable.
config CMD_SAVEENV
bool "saveenv"
+ default y
help
- Run the command in the given environment variable.
+ Save all environment variables into the compiled-in persistent
+ storage.
+
+config CMD_ENV_EXISTS
+ bool "env exists"
+ default y
+ help
+ Check if a variable is defined in the environment for use in
+ shell scripting.
endmenu
config CMD_MEMORY
bool "md, mm, nm, mw, cp, cmp, base, loop"
+ default y
help
Memeory commands.
md - memory display
config CMD_LOADB
bool "loadb"
+ default y
help
Load a binary file over serial line.
config CMD_LOADS
bool "loads"
+ default y
help
Load an S-Record file over serial line
config CMD_FLASH
bool "flinfo, erase, protect"
+ default y
help
NOR flash support.
flinfo - print FLASH memory information
help
NAND support.
+config CMD_SF
+ bool "sf"
+ help
+ SPI Flash support
+
config CMD_SPI
bool "sspi"
help
config CMD_FPGA
bool "fpga"
+ default y
help
FPGA support.
config CMD_ECHO
bool "echo"
+ default y
help
Echo args to console
config CMD_ITEST
bool "itest"
+ default y
help
Return true/false on integer compare.
config CMD_SOURCE
bool "source"
+ default y
help
Run script from memory
config CMD_SETEXPR
bool "setexpr"
+ default y
help
Evaluate boolean and math expressions and store the result in an env
variable.
config CMD_NET
bool "bootp, tftpboot"
select NET
+ default y
help
Network commands.
bootp - boot image via network using BOOTP/TFTP protocol
config CMD_NFS
bool "nfs"
+ default y
help
Boot image via network using NFS protocol.
# TODO: rename to CMD_SLEEP
config CMD_MISC
bool "sleep"
+ default y
help
Delay execution for some time
config CMD_SETGETDCR
bool "getdcr, setdcr, getidcr, setidcr"
depends on 4xx
+ default y
help
getdcr - Get an AMCC PPC 4xx DCR's value
setdcr - Set an AMCC PPC 4xx DCR's value
return 0;
}
-static inline int str2off(const char *p, loff_t *num)
-{
- char *endptr;
-
- *num = simple_strtoull(p, &endptr, 16);
- return *p != '\0' && *endptr == '\0';
-}
-
-static inline int str2long(const char *p, ulong *num)
-{
- char *endptr;
-
- *num = simple_strtoul(p, &endptr, 16);
- return *p != '\0' && *endptr == '\0';
-}
-
-static int get_part(const char *partname, int *idx, loff_t *off, loff_t *size,
- loff_t *maxsize)
-{
-#ifdef CONFIG_CMD_MTDPARTS
- struct mtd_device *dev;
- struct part_info *part;
- u8 pnum;
- int ret;
-
- ret = mtdparts_init();
- if (ret)
- return ret;
-
- ret = find_dev_and_part(partname, &dev, &pnum, &part);
- if (ret)
- return ret;
-
- if (dev->id->type != MTD_DEV_TYPE_NAND) {
- puts("not a NAND device\n");
- return -1;
- }
-
- *off = part->offset;
- *size = part->size;
- *maxsize = part->size;
- *idx = dev->id->num;
-
- ret = set_dev(*idx);
- if (ret)
- return ret;
-
- return 0;
-#else
- puts("offset is not a number\n");
- return -1;
-#endif
-}
-
-static int arg_off(const char *arg, int *idx, loff_t *off, loff_t *size,
- loff_t *maxsize)
-{
- if (!str2off(arg, off))
- return get_part(arg, idx, off, size, maxsize);
-
- if (*off >= nand_info[*idx].size) {
- puts("Offset exceeds device limit\n");
- return -1;
- }
-
- *maxsize = nand_info[*idx].size - *off;
- *size = *maxsize;
- return 0;
-}
-
-static int arg_off_size(int argc, char *const argv[], int *idx,
- loff_t *off, loff_t *size, loff_t *maxsize)
-{
- int ret;
-
- if (argc == 0) {
- *off = 0;
- *size = nand_info[*idx].size;
- *maxsize = *size;
- goto print;
- }
-
- ret = arg_off(argv[0], idx, off, size, maxsize);
- if (ret)
- return ret;
-
- if (argc == 1)
- goto print;
-
- if (!str2off(argv[1], size)) {
- printf("'%s' is not a number\n", argv[1]);
- return -1;
- }
-
- if (*size > *maxsize) {
- puts("Size exceeds partition or device limit\n");
- return -1;
- }
-
-print:
- printf("device %d ", *idx);
- if (*size == nand_info[*idx].size)
- puts("whole chip\n");
- else
- printf("offset 0x%llx, size 0x%llx\n",
- (unsigned long long)*off, (unsigned long long)*size);
- return 0;
-}
-
#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
static void print_status(ulong start, ulong end, ulong erasesize, int status)
{
goto usage;
/* We don't care about size, or maxsize. */
- if (arg_off(argv[2], &idx, &addr, &maxsize, &maxsize)) {
+ if (mtd_arg_off(argv[2], &idx, &addr, &maxsize, &maxsize,
+ MTD_DEV_TYPE_NAND, nand_info[idx].size)) {
+ puts("Offset or partition name expected\n");
+ return 1;
+ }
+ if (set_dev(idx)) {
puts("Offset or partition name expected\n");
return 1;
}
printf("\nNAND %s: ", cmd);
/* skip first two or three arguments, look for offset and size */
- if (arg_off_size(argc - o, argv + o, &dev, &off, &size,
- &maxsize) != 0)
+ if (mtd_arg_off_size(argc - o, argv + o, &dev, &off, &size,
+ &maxsize, MTD_DEV_TYPE_NAND,
+ nand_info[dev].size) != 0)
+ return 1;
+
+ if (set_dev(dev))
return 1;
nand = &nand_info[dev];
if (s && !strcmp(s, ".raw")) {
raw = 1;
- if (arg_off(argv[3], &dev, &off, &size, &maxsize))
+ if (mtd_arg_off(argv[3], &dev, &off, &size, &maxsize,
+ MTD_DEV_TYPE_NAND,
+ nand_info[dev].size))
+ return 1;
+
+ if (set_dev(dev))
return 1;
nand = &nand_info[dev];
rwsize = pagecount * (nand->writesize + nand->oobsize);
} else {
- if (arg_off_size(argc - 3, argv + 3, &dev,
- &off, &size, &maxsize) != 0)
+ if (mtd_arg_off_size(argc - 3, argv + 3, &dev, &off,
+ &size, &maxsize,
+ MTD_DEV_TYPE_NAND,
+ nand_info[dev].size) != 0)
+ return 1;
+
+ if (set_dev(dev))
return 1;
/* size is unspecified */
if (s && !strcmp(s, ".allexcept"))
allexcept = 1;
- if (arg_off_size(argc - 2, argv + 2, &dev, &off, &size,
- &maxsize) < 0)
+ if (mtd_arg_off_size(argc - 2, argv + 2, &dev, &off, &size,
+ &maxsize, MTD_DEV_TYPE_NAND,
+ nand_info[dev].size) < 0)
+ return 1;
+
+ if (set_dev(dev))
return 1;
if (!nand_unlock(&nand_info[dev], off, size, allexcept)) {
static loff_t next_ofs;
static loff_t skip_ofs;
-static inline int str2long(char *p, ulong *num)
-{
- char *endptr;
-
- *num = simple_strtoul(p, &endptr, 16);
- return (*p != '\0' && *endptr == '\0') ? 1 : 0;
-}
-
-static int arg_off_size(int argc, char * const argv[], ulong *off, size_t *size)
+static int arg_off_size_onenand(int argc, char * const argv[], ulong *off,
+ size_t *size)
{
if (argc >= 1) {
if (!(str2long(argv[0], off))) {
addr = (ulong)simple_strtoul(argv[1], NULL, 16);
printf("\nOneNAND read: ");
- if (arg_off_size(argc - 2, argv + 2, &ofs, &len) != 0)
+ if (arg_off_size_onenand(argc - 2, argv + 2, &ofs, &len) != 0)
return 1;
ret = onenand_block_read(ofs, len, &retlen, (u8 *)addr, oob);
addr = (ulong)simple_strtoul(argv[1], NULL, 16);
printf("\nOneNAND write: ");
- if (arg_off_size(argc - 2, argv + 2, &ofs, &len) != 0)
+ if (arg_off_size_onenand(argc - 2, argv + 2, &ofs, &len) != 0)
return 1;
ret = onenand_block_write(ofs, len, &retlen, (u8 *)addr, withoob);
printf("\nOneNAND erase: ");
/* skip first two or three arguments, look for offset and size */
- if (arg_off_size(argc, argv, &ofs, &len) != 0)
+ if (arg_off_size_onenand(argc, argv, &ofs, &len) != 0)
return 1;
ret = onenand_block_erase(ofs, len, force);
printf("\nOneNAND test: ");
/* skip first two or three arguments, look for offset and size */
- if (arg_off_size(argc - 1, argv + 1, &ofs, &len) != 0)
+ if (arg_off_size_onenand(argc - 1, argv + 1, &ofs, &len) != 0)
return 1;
ret = onenand_block_test(ofs, len);
if (var != NULL) {
int p;
char str[512] = { '\0', };
- disk_partition_t info;
+ disk_partition_t info;
for (p = 1; p < 128; p++) {
char t[5];
return 0;
}
+static int do_part_start(int argc, char * const argv[])
+{
+ block_dev_desc_t *desc;
+ disk_partition_t info;
+ char buf[512] = { 0 };
+ int part;
+ int err;
+ int ret;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+ if (argc > 4)
+ return CMD_RET_USAGE;
+
+ part = simple_strtoul(argv[2], NULL, 0);
+
+ ret = get_device(argv[0], argv[1], &desc);
+ if (ret < 0)
+ return 1;
+
+ err = get_partition_info(desc, part, &info);
+ if (err)
+ return 1;
+
+ snprintf(buf, sizeof(buf), LBAF, info.start);
+
+ if (argc > 3)
+ setenv(argv[3], buf);
+ else
+ printf("%s\n", buf);
+
+ return 0;
+}
+
+static int do_part_size(int argc, char * const argv[])
+{
+ block_dev_desc_t *desc;
+ disk_partition_t info;
+ char buf[512] = { 0 };
+ int part;
+ int err;
+ int ret;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+ if (argc > 4)
+ return CMD_RET_USAGE;
+
+ part = simple_strtoul(argv[2], NULL, 0);
+
+ ret = get_device(argv[0], argv[1], &desc);
+ if (ret < 0)
+ return 1;
+
+ err = get_partition_info(desc, part, &info);
+ if (err)
+ return 1;
+
+ snprintf(buf, sizeof(buf), LBAF, info.size);
+
+ if (argc > 3)
+ setenv(argv[3], buf);
+ else
+ printf("%s\n", buf);
+
+ return 0;
+}
+
static int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc < 2)
return do_part_uuid(argc - 2, argv + 2);
else if (!strcmp(argv[1], "list"))
return do_part_list(argc - 2, argv + 2);
+ else if (!strcmp(argv[1], "start"))
+ return do_part_start(argc - 2, argv + 2);
+ else if (!strcmp(argv[1], "size"))
+ return do_part_size(argc - 2, argv + 2);
return CMD_RET_USAGE;
}
" - print a device's partition table\n"
"part list <interface> <dev> [flags] <varname>\n"
" - set environment variable to the list of partitions\n"
- " flags can be -bootable (list only bootable partitions)"
+ " flags can be -bootable (list only bootable partitions)\n"
+ "part start <interface> <dev> <part> <varname>\n"
+ " - set environment variable to the start of the partition (in blocks)\n"
+ "part size <interface> <dev> <part> <varname>\n"
+ " - set environment variable to the size of the partition (in blocks)"
);
* forward declerations of some Setup Routines
*/
void scsi_setup_test_unit_ready(ccb * pccb);
-void scsi_setup_read6(ccb * pccb, unsigned long start, unsigned short blocks);
-void scsi_setup_read_ext(ccb * pccb, unsigned long start, unsigned short blocks);
-static void scsi_setup_write_ext(ccb *pccb, unsigned long start,
- unsigned short blocks);
+void scsi_setup_read6(ccb * pccb, lbaint_t start, unsigned short blocks);
+void scsi_setup_read_ext(ccb * pccb, lbaint_t start, unsigned short blocks);
+void scsi_setup_read16(ccb * pccb, lbaint_t start, unsigned long blocks);
+
+static void scsi_setup_write_ext(ccb *pccb, lbaint_t start,
+ unsigned short blocks);
void scsi_setup_inquiry(ccb * pccb);
void scsi_ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
* scsi_read
*/
-#define SCSI_MAX_READ_BLK 0xFFFF /* almost the maximum amount of the scsi_ext command.. */
+/* almost the maximum amount of the scsi_ext command.. */
+#define SCSI_MAX_READ_BLK 0xFFFF
+#define SCSI_LBA48_READ 0xFFFFFFF
static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt,
void *buffer)
device, start, blks, (unsigned long)buffer);
do {
pccb->pdata=(unsigned char *)buf_addr;
- if(blks>SCSI_MAX_READ_BLK) {
+#ifdef CONFIG_SYS_64BIT_LBA
+ if (start > SCSI_LBA48_READ) {
+ unsigned long blocks;
+ blocks = min_t(lbaint_t, blks, SCSI_MAX_READ_BLK);
+ pccb->datalen = scsi_dev_desc[device].blksz * blocks;
+ scsi_setup_read16(pccb, start, blocks);
+ start += blocks;
+ blks -= blocks;
+ } else
+#endif
+ if (blks > SCSI_MAX_READ_BLK) {
pccb->datalen=scsi_dev_desc[device].blksz * SCSI_MAX_READ_BLK;
smallblks=SCSI_MAX_READ_BLK;
scsi_setup_read_ext(pccb,start,smallblks);
pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
}
-void scsi_setup_read_ext(ccb * pccb, unsigned long start, unsigned short blocks)
+#ifdef CONFIG_SYS_64BIT_LBA
+void scsi_setup_read16(ccb * pccb, lbaint_t start, unsigned long blocks)
+{
+ pccb->cmd[0] = SCSI_READ16;
+ pccb->cmd[1] = pccb->lun<<5;
+ pccb->cmd[2] = ((unsigned char) (start >> 56)) & 0xff;
+ pccb->cmd[3] = ((unsigned char) (start >> 48)) & 0xff;
+ pccb->cmd[4] = ((unsigned char) (start >> 40)) & 0xff;
+ pccb->cmd[5] = ((unsigned char) (start >> 32)) & 0xff;
+ pccb->cmd[6] = ((unsigned char) (start >> 24)) & 0xff;
+ pccb->cmd[7] = ((unsigned char) (start >> 16)) & 0xff;
+ pccb->cmd[8] = ((unsigned char) (start >> 8)) & 0xff;
+ pccb->cmd[9] = ((unsigned char) (start)) & 0xff;
+ pccb->cmd[10] = 0;
+ pccb->cmd[11] = ((unsigned char) (blocks >> 24)) & 0xff;
+ pccb->cmd[12] = ((unsigned char) (blocks >> 16)) & 0xff;
+ pccb->cmd[13] = ((unsigned char) (blocks >> 8)) & 0xff;
+ pccb->cmd[14] = (unsigned char) blocks & 0xff;
+ pccb->cmd[15] = 0;
+ pccb->cmdlen = 16;
+ pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+ debug ("scsi_setup_read16: cmd: %02X %02X "
+ "startblk %02X%02X%02X%02X%02X%02X%02X%02X "
+ "blccnt %02X%02X%02X%02X\n",
+ pccb->cmd[0], pccb->cmd[1],
+ pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
+ pccb->cmd[6], pccb->cmd[7], pccb->cmd[8], pccb->cmd[9],
+ pccb->cmd[11], pccb->cmd[12], pccb->cmd[13], pccb->cmd[14]);
+}
+#endif
+
+void scsi_setup_read_ext(ccb * pccb, lbaint_t start, unsigned short blocks)
{
pccb->cmd[0]=SCSI_READ10;
pccb->cmd[1]=pccb->lun<<5;
pccb->cmd[7],pccb->cmd[8]);
}
-void scsi_setup_write_ext(ccb *pccb, unsigned long start, unsigned short blocks)
+void scsi_setup_write_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
{
pccb->cmd[0] = SCSI_WRITE10;
pccb->cmd[1] = pccb->lun << 5;
pccb->cmd[7], pccb->cmd[8]);
}
-void scsi_setup_read6(ccb * pccb, unsigned long start, unsigned short blocks)
+void scsi_setup_read6(ccb * pccb, lbaint_t start, unsigned short blocks)
{
pccb->cmd[0]=SCSI_READ6;
pccb->cmd[1]=pccb->lun<<5 | (((unsigned char)(start>>16))&0x1f);
#include <mapmem.h>
#include <spi.h>
#include <spi_flash.h>
+#include <jffs2/jffs2.h>
+#include <linux/mtd/mtd.h>
#include <asm/io.h>
#include <dm/device-internal.h>
flash = dev_get_uclass_priv(new);
#else
+ if (flash)
+ spi_flash_free(flash);
+
new = spi_flash_probe(bus, cs, speed, mode);
+ flash = new;
+
if (!new) {
printf("Failed to initialize SPI flash at %u:%u\n", bus, cs);
return 1;
}
- if (flash)
- spi_flash_free(flash);
flash = new;
#endif
static int do_spi_flash_read_write(int argc, char * const argv[])
{
unsigned long addr;
- unsigned long offset;
- unsigned long len;
void *buf;
char *endp;
int ret = 1;
+ int dev = 0;
+ loff_t offset, len, maxsize;
- if (argc < 4)
+ if (argc < 3)
return -1;
addr = simple_strtoul(argv[1], &endp, 16);
if (*argv[1] == 0 || *endp != 0)
return -1;
- offset = simple_strtoul(argv[2], &endp, 16);
- if (*argv[2] == 0 || *endp != 0)
- return -1;
- len = simple_strtoul(argv[3], &endp, 16);
- if (*argv[3] == 0 || *endp != 0)
+
+ if (mtd_arg_off_size(argc - 2, &argv[2], &dev, &offset, &len,
+ &maxsize, MTD_DEV_TYPE_NOR, flash->size))
return -1;
/* Consistency checking */
static int do_spi_flash_erase(int argc, char * const argv[])
{
- unsigned long offset;
- unsigned long len;
- char *endp;
int ret;
+ int dev = 0;
+ loff_t offset, len, maxsize;
+ ulong size;
if (argc < 3)
return -1;
- offset = simple_strtoul(argv[1], &endp, 16);
- if (*argv[1] == 0 || *endp != 0)
+ if (mtd_arg_off(argv[1], &dev, &offset, &len, &maxsize,
+ MTD_DEV_TYPE_NOR, flash->size))
return -1;
- ret = sf_parse_len_arg(argv[2], &len);
+ ret = sf_parse_len_arg(argv[2], &size);
if (ret != 1)
return -1;
/* Consistency checking */
- if (offset + len > flash->size) {
+ if (offset + size > flash->size) {
printf("ERROR: attempting %s past flash size (%#x)\n",
argv[0], flash->size);
return 1;
}
- ret = spi_flash_erase(flash, offset, len);
- printf("SF: %zu bytes @ %#x Erased: %s\n", (size_t)len, (u32)offset,
+ ret = spi_flash_erase(flash, offset, size);
+ printf("SF: %zu bytes @ %#x Erased: %s\n", (size_t)size, (u32)offset,
ret ? "ERROR" : "OK");
return ret == 0 ? 0 : 1;
"SPI flash sub-system",
"probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus\n"
" and chip select\n"
- "sf read addr offset len - read `len' bytes starting at\n"
- " `offset' to memory at `addr'\n"
- "sf write addr offset len - write `len' bytes from memory\n"
- " at `addr' to flash at `offset'\n"
- "sf erase offset [+]len - erase `len' bytes from `offset'\n"
- " `+len' round up `len' to block size\n"
- "sf update addr offset len - erase and write `len' bytes from memory\n"
- " at `addr' to flash at `offset'"
+ "sf read addr offset|partition len - read `len' bytes starting at\n"
+ " `offset' or from start of mtd\n"
+ " `partition'to memory at `addr'\n"
+ "sf write addr offset|partition len - write `len' bytes from memory\n"
+ " at `addr' to flash at `offset'\n"
+ " or to start of mtd `partition'\n"
+ "sf erase offset|partition [+]len - erase `len' bytes from `offset'\n"
+ " or from start of mtd `partition'\n"
+ " `+len' round up `len' to block size\n"
+ "sf update addr offset|partition len - erase and write `len' bytes from memory\n"
+ " at `addr' to flash at `offset'\n"
+ " or to start of mtd `partition'\n"
SF_TEST_HELP
);
* SPDX-License-Identifier: GPL-2.0+
*/
-/*
- * Define _STDBOOL_H here to avoid macro expansion of true and false.
- * If the future code requires macro true or false, remove this define
- * and undef true and false before U_BOOT_CMD. This define and comment
- * shall be removed if change to U_BOOT_CMD is made to take string
- * instead of stringifying it.
- */
-#define _STDBOOL_H
-
#include <common.h>
#include <command.h>
#include <fs.h>
return expr;
}
+#undef true
+#undef false
+
U_BOOT_CMD(
test, CONFIG_SYS_MAXARGS, 1, do_test,
"minimal test like /bin/sh",
(void *) spl_image.load_addr);
end:
+ if (count == 0) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- if (count == 0)
- printf("spl: mmc block read error\n");
+ puts("spl: mmc block read error\n");
#endif
-
- if (count == 0)
return -1;
+ }
return 0;
}
err = get_partition_info(&mmc->block_dev, partition, &info);
if (err) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- printf("spl: partition error\n");
+ puts("spl: partition error\n");
#endif
return -1;
}
(void *) CONFIG_SYS_SPL_ARGS_ADDR);
if (count == 0) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- printf("spl: mmc block read error\n");
+ puts("spl: mmc block read error\n");
#endif
return -1;
}
return;
}
#endif
-#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+#if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION)
err = mmc_load_image_raw_partition(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION);
-#else
+ if (!err)
+ return;
+#elif defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR)
err = mmc_load_image_raw_sector(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
-#endif
if (!err)
return;
-#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#endif
case MMCSD_MODE_FS:
debug("spl: mmc boot mode: fs\n");
+#ifdef CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
#ifdef CONFIG_SPL_FAT_SUPPORT
#ifdef CONFIG_SPL_OS_BOOT
if (!spl_start_uboot()) {
return;
}
#endif
+#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
err = spl_load_image_fat(&mmc->block_dev,
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
if (!err)
return;
#endif
+#endif
#ifdef CONFIG_SPL_EXT_SUPPORT
#ifdef CONFIG_SPL_OS_BOOT
if (!spl_start_uboot()) {
return;
}
#endif
+#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
err = spl_load_image_ext(&mmc->block_dev,
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
return;
#endif
#endif
+#endif
#ifdef CONFIG_SUPPORT_EMMC_BOOT
case MMCSD_MODE_EMMCBOOT:
/*
return;
}
#endif
-#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+#if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION)
err = mmc_load_image_raw_partition(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION);
-#else
+ if (!err)
+ return;
+#elif defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR)
err = mmc_load_image_raw_sector(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
-#endif
if (!err)
return;
+#endif
#endif
case MMCSD_MODE_UNDEFINED:
default:
/* We found a USB Keyboard, install it. */
usb_set_protocol(dev, iface->desc.bInterfaceNumber, 0);
+ debug("USB KBD: found set idle...\n");
#if !defined(CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP) && \
!defined(CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE)
- debug("USB KBD: found set idle...\n");
usb_set_idle(dev, iface->desc.bInterfaceNumber, REPEAT_RATE / 4, 0);
+#else
+ usb_set_idle(dev, iface->desc.bInterfaceNumber, 0, 0);
#endif
debug("USB KBD: enable interrupt pipe...\n");
CONFIG_DRAM_EMR1=4
CONFIG_SYS_CLK_FREQ=912000000
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB1_VBUS_PIN="PB10"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,SUNXI_EMAC,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_VIDEO_LCD_POWER="PB10"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_VIDEO_VGA=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_TARGET_B4860QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_B4860QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_B4860QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_B4860QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_B4860QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_B4860QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_B4860QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_B4860QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_BSC9131RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND,SYS_CLK_100"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_BSC9131RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9131RDB=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH,SYS_CLK_100"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9131RDB=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_DRAM_CLK=432
CONFIG_GMAC_TX_DELAY=3
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB2_VBUS_PIN="PH1"
CONFIG_GMAC_TX_DELAY=3
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_C29XPCIE=y
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_C29XPCIE=y
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_C29XPCIE=y
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_C29XPCIE=y
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_CPCI2DP=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_PPC=y
-CONFIG_CMD_NET=y
CONFIG_4xx=y
CONFIG_TARGET_CPCI4052=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
CONFIG_AXP221_DLDO1_VOLT=3300
CONFIG_AXP221_ALDO1_VOLT=3300
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y
CONFIG_USB_MUSB_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
CONFIG_VIDEO_LCD_SPI_CS="PA0"
CONFIG_VIDEO_LCD_SPI_SCLK="PA1"
CONFIG_VIDEO_LCD_SPI_MOSI="PA2"
CONFIG_DRAM_ZQ=251
CONFIG_USB1_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
CONFIG_AXP221_ALDO1_VOLT=3300
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_DRAM_CLK=480
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=480
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_VIDEO_VGA=y
CONFIG_GMAC_TX_DELAY=1
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-et-q8-v1.6"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
CONFIG_AXP221_DLDO1_VOLT=3300
CONFIG_AXP221_ALDO1_VOLT=3000
CONFIG_VIDEO_VGA_VIA_LCD=y
CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
CONFIG_AXP221_ALDO1_VOLT=3300
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_USB_MUSB_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ippo-q8h-v1.2-lcd1024x600"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
CONFIG_AXP221_DLDO1_VOLT=3300
CONFIG_AXP221_ALDO1_VOLT=3000
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v1.2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
CONFIG_AXP221_DLDO1_VOLT=3300
CONFIG_AXP221_ALDO1_VOLT=3000
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
CONFIG_AXP221_DLDO1_VOLT=3300
CONFIG_AXP221_ALDO1_VOLT=3000
CONFIG_USB1_VBUS_PIN="PH11"
CONFIG_GMAC_TX_DELAY=3
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3-nano"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=122
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_M68K=y
CONFIG_TARGET_M5208EVBE=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M52277EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000"
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
CONFIG_M68K=y
CONFIG_TARGET_M52277EVB=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000"
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
CONFIG_M68K=y
CONFIG_TARGET_M5235EVB=y
CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5235EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFE00000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5249EVB=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
CONFIG_M68K=y
CONFIG_TARGET_M5253DEMO=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5253EVBE=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
CONFIG_M68K=y
CONFIG_TARGET_M5272C3=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5275EVB=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5282EVB=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M53017EVB=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5329EVB=y
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5329EVB=y
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5373EVB=y
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_M68K=y
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_M68K=y
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_M68K=y
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_M68K=y
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_M68K=y
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_M68K=y
CONFIG_TARGET_M54451EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_M68K=y
CONFIG_TARGET_M54451EVB=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_M68K=y
CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_M68K=y
CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_M68K=y
CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_M68K=y
CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_M68K=y
CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_4xx=y
CONFIG_TARGET_MIP405=y
CONFIG_SYS_EXTRA_OPTIONS="MIP405T"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_MIP405=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8308RDB=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8313ERDB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8313ERDB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_MPC8313ERDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_MPC8313ERDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8315ERDB=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8323ERDB=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M,PQ_MDS_PIB=1"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M,PQ_MDS_PIB=1"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,PCISLAVE"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349EMDS=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC837XEMDS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC837XEMDS=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC837XERDB=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8536DS=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8536DS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8536DS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8536DS=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8540ADS=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8541CDS=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8541CDS=y
CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8544DS=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8548CDS=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8548CDS=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8548CDS=y
CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8555CDS=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8555CDS=y
CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8560ADS=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8568MDS=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8569MDS=y
CONFIG_SYS_EXTRA_OPTIONS="ATM"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8569MDS=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8572DS=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8572DS=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_PPC=y
CONFIG_MPC86xx=y
CONFIG_TARGET_MPC8610HPCD=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC86xx=y
CONFIG_TARGET_MPC8641HPCN=y
CONFIG_SYS_EXTRA_OPTIONS="PHYS_64BIT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC86xx=y
CONFIG_TARGET_MPC8641HPCN=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_USB_KEYBOARD is not set
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=360
CONFIG_DRAM_ZQ=122
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:768,y:1024,depth:18,pclk_khz:66000,le:56,ri:60,up:30,lo:36,hs:64,vs:50,sync:3,vmode:0"
CONFIG_VIDEO_LCD_BL_EN="PA25"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y
+CONFIG_USB_MUSB_SUNXI=y
# CONFIG_USB_KEYBOARD is not set
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-primo81"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
CONFIG_AXP221_DLDO1_VOLT=3300
CONFIG_VIDEO_LCD_SSD2828_TX_CLK=27
CONFIG_VIDEO_LCD_SSD2828_RESET="PA26"
CONFIG_VIDEO_LCD_SPI_SCLK="PH10"
CONFIG_VIDEO_LCD_SPI_MOSI="PH11"
CONFIG_VIDEO_LCD_SPI_MISO="PH12"
+CONFIG_USB=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN4I=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
-# The Mele A1000G quad is yet another Allwinnner based Android top set box
-# from Mele.
-#
-# It uses the same case as the original Mele A1000 and the same PCB as the M9,
-# the USM sata storage slot is connected via anusb to sata bridge connected to
-# the otg controller, this renders the micro USB B receptacle non functional.
-#
-# It features an A31 SoC, 2G RAM, 16G Nand, 100Mbit ethernet, HDMI out,
-# 3 USB A receptacles, 3.5 mm jack for analog audio out, optical spdif,
-# RTL R8188EU (USB) wifi and a full size sdcard slot
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN6I=y
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
CONFIG_AXP221_DCDC1_VOLT=3300
CONFIG_AXP221_DLDO1_VOLT=3300
CONFIG_AXP221_DLDO4_VOLT=3300
CONFIG_AXP221_ALDO1_VOLT=3300
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_MACH_SUN4I=y
CONFIG_VIDEO_VGA=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
CONFIG_AXP221_DCDC1_VOLT=3300
CONFIG_AXP221_DLDO1_VOLT=3300
CONFIG_AXP221_DLDO4_VOLT=3300
CONFIG_AXP221_ALDO1_VOLT=3300
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_VIDEO_VGA=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_DRAM_ZQ=122
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,USB_EHCI,STATUSLED=234"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
-# The Mele M9 is yet another Allwinnner based Android top set box from Mele.
-#
-# It uses the same PCB as the A1000G quad, but in a new case without a
-# USM sata storage slot, and the space on the PCB for the usb to sata
-# bridge connected to the otg controller is not populated, possible
-# making the micro usb otg connector functional (untested)
-#
-# It features an A31 SoC, 2G RAM, 16G Nand, 100Mbit ethernet, HDMI out,
-# 3 USB A receptacles, 3.5 mm jack for analog audio out, optical spdif,
-# micro USB B receptacle, RTL R8188EU (USB) and a full size sdcard slot
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN6I=y
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
CONFIG_AXP221_DCDC1_VOLT=3300
CONFIG_AXP221_DLDO1_VOLT=3300
CONFIG_AXP221_DLDO4_VOLT=3300
CONFIG_AXP221_ALDO1_VOLT=3300
+CONFIG_USB=y
+CONFIG_DM_USB=y
-CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus"
-CONFIG_VIDEO=n
-CONFIG_USB_KEYBOARD=n
-CONFIG_MMC0_CD_PIN="PH18"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN9I=y
-# these are unused atm but we must set them to something
CONFIG_DRAM_CLK=360
CONFIG_DRAM_ZQ=123
CONFIG_SYS_CLK_FREQ=1008000000
+CONFIG_MMC0_CD_PIN="PH18"
+# CONFIG_VIDEO is not set
+# CONFIG_USB_KEYBOARD is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_SH=y
CONFIG_TARGET_MIGOR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN4I=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_SYS_EXTRA_OPTIONS="MINIFAP"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2D300=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
-CONFIG_CMD_NET=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2DNT2=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000"
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n"
CONFIG_AUTOBOOT_STOP_STR="++++++++++"
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
-CONFIG_CMD_NET=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2DNT2=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n"
CONFIG_AUTOBOOT_STOP_STR="++++++++++"
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2D=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2I=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2MNT=y
CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M110\""
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2MNT=y
CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M112\""
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2MNT=y
CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M113\""
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2MNT=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_O3DNT=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_VIDEO_VGA=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB2_VBUS_PIN="PH22"
CONFIG_GMAC_TX_DELAY=3
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD,36BIT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,36BIT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1020MBG"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1020UTM"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1022DS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1022DS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1022DS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1022DS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1023RDB=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,36BIT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,36BIT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5020DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5020DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5020DS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5020DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5020DS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5020DS=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_5xx=y
CONFIG_TARGET_PATI=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_PIP405=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
-CONFIG_CMD_NET=y
CONFIG_4xx=y
CONFIG_TARGET_PLU405=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
-CONFIG_CMD_NET=y
CONFIG_4xx=y
CONFIG_TARGET_PMC405DE=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
-CONFIG_CMD_NET=y
CONFIG_4xx=y
CONFIG_TARGET_PMC440=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_T102XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T102XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T102XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T102XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SYS_FSL_DDR4"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT,T1040RDB"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T208XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T208XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T208XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T208XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T208XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T208XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T208XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T208XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T208XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T208XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T208XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T208XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T208XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T208XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T208XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T208XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T208XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T4240QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T4240QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240RDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T4240QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T4240QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_T4240RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240RDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+CONFIG_SPI_FLASH=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,SYS_TEXT_BASE=0xFFF00000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_SYS_EXTRA_OPTIONS="STK52XX_REV100"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM823L=y
CONFIG_SYS_EXTRA_OPTIONS="LCD,NEC_NL6448BC20"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_TQM823L=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_TQM823M=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_TQM834X=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_TQM850L=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_TQM850M=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_TQM855L=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_TQM855M=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_TQM860L=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_TQM860M=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_TQM862L=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_TQM862M=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_TQM866M=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_TQM885D=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM823L=y
CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ104V7DS01"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_TWR=y
CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-tzx-q8-713b7"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
CONFIG_PPC=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_UCP1020=y
CONFIG_TARGET_UCP1020_SPIFLASH=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b"
+CONFIG_SPI_FLASH=y
CONFIG_PPC=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_UCP1020=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b"
+CONFIG_SPI_FLASH=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_TL059WV5C0=y
CONFIG_USB_MUSB_SUNXI=y
-# CONFIG_DM_SERIAL is not set
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ARM=y
CONFIG_TARGET_VCMA9=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_VOM405=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wits-pro-a20-dkt"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_USB_MUSB_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_A3M071=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_LIB_RAND=y
CONFIG_PPC=y
-CONFIG_CMD_NET=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_A4M072=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="asdfg"
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_A3M071=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="A4M2K"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_LIB_RAND=y
CONFIG_PPC=y
CONFIG_MPC512X=y
CONFIG_TARGET_AC14XX=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_ACADIA=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_NDS32=y
CONFIG_TARGET_ADP_AG101=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NDS32=y
CONFIG_TARGET_ADP_AG101P=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NDS32=y
CONFIG_TARGET_ADP_AG102=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_ALPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_RMOBILE=y
CONFIG_TARGET_ALT=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_SH_SDHI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_BALTOS=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_CONS_INDEX=1
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_AM335X_EVM=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_SPI_FLASH=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="NAND"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="NAND"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_AM335X_EVM=y
CONFIG_NOR=y
CONFIG_NOR_BOOT=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="NAND,SPL_USBETH_SUPPORT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_OMAP34XX=y
CONFIG_TARGET_AM3517_CRANE=y
CONFIG_SPL=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_OMAP34XX=y
CONFIG_TARGET_AM3517_EVM=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_AM43XX_EVM=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
-CONFIG_CMD_NET=y
+CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_ETH_SUPPORT"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_AM43XX_EVM=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_USB_HOST_SUPPORT"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_M68K=y
CONFIG_TARGET_AMCORE=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_SH=y
CONFIG_TARGET_AP325RXA=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SH=y
CONFIG_TARGET_AP_SH4A_4A=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TEGRA30=y
CONFIG_TARGET_APALIS_T30=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_TARGET_APF27=y
CONFIG_SPL=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
CONFIG_ARM=y
CONFIG_TARGET_APX4DEVKIT=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_TARGET_ARCANGEL4=y
CONFIG_SYS_CLK_FREQ=70000000
-CONFIG_DM_SERIAL=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_DEFAULT_DEVICE_TREE="arcangel4"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARC=y
CONFIG_TARGET_ARCANGEL4=y
CONFIG_SYS_CLK_FREQ=70000000
-CONFIG_DM_SERIAL=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_DEFAULT_DEVICE_TREE="arcangel4"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TARGET_CANYONLANDS=y
CONFIG_ARCHES=y
CONFIG_DEFAULT_DEVICE_TREE="arches"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_PPC=y
CONFIG_MPC512X=y
CONFIG_TARGET_ARIA=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_ARISTAINETOS2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_ARISTAINETOS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_RMOBILE=y
CONFIG_TARGET_ARMADILLO_800EVA=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
CONFIG_TARGET_ARNDALE=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale"
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SOUND=y
CONFIG_SOUND=y
CONFIG_I2S=y
CONFIG_I2S_SAMSUNG=y
CONFIG_SOUND_MAX98095=y
CONFIG_SOUND_WM8994=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_ARM=y
CONFIG_TARGET_ASPENITE=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_M68K=y
CONFIG_TARGET_ASTRO_MCF5373L=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91RM9200EK=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91RM9200EK=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_NANDFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_NANDFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_MMC"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_AT91SAM9M10G45EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_AT91SAM9M10G45EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_MMC"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH"
CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC"
CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH"
CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_AVR32=y
-CONFIG_CMD_NET=y
CONFIG_TARGET_ATNGW100=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_AVR32=y
-CONFIG_CMD_NET=y
CONFIG_TARGET_ATNGW100MKII=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_AVR32=y
-CONFIG_CMD_NET=y
CONFIG_TARGET_ATSTK1002=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_TAURUS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARC_CACHE_LINE_SHIFT=5
CONFIG_TARGET_AXS101=y
CONFIG_SYS_CLK_FREQ=750000000
-CONFIG_NETDEVICES=y
CONFIG_SYS_TEXT_BASE=0x81000000
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ISA_ARCV2=y
CONFIG_TARGET_AXS101=y
CONFIG_SYS_CLK_FREQ=50000000
-CONFIG_NETDEVICES=y
CONFIG_SYS_TEXT_BASE=0x81000000
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_DRAM_EMR1=4
CONFIG_USB2_VBUS_PIN="PH12"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_ARM=y
CONFIG_TARGET_BALLOON3=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_BAMBOO=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_ARM=y
CONFIG_TARGET_BCM28155_AP=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_MMC_ENV_DEV=0"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_TARGET_BCM28155_AP=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_TARGET_BCM28155_AP=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_TARGET_BCM28155_AP=y
CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000,ARMV7_NONSEC"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000,ARMV7_NONSEC"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_BCMNSP=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x01000000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_BLACKFIN=y
CONFIG_TARGET_BCT_BRETTL2=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_TARGET_BEAGLE_X15=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TEGRA30=y
CONFIG_TARGET_BEAVER=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-beaver"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF506F_EZKIT=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF518F_EZBRD=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF525_UCR2=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF526_EZBRD=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF527_AD7160_EVAL=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF527_EZKIT=y
CONFIG_SYS_EXTRA_OPTIONS="BF527_EZKIT_REV_2_1"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF527_EZKIT=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF527_SDP=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF533_EZKIT=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF533_STAMP=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF537_MINOTAUR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPI_FLASH=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF537_PNAV=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPI_FLASH=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF537_SRV1=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPI_FLASH=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF537_STAMP=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF538F_EZKIT=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF548_EZKIT=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF561_ACVILON=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF561_EZKIT=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_BLACKFIN=y
-CONFIG_NETDEVICES=y
CONFIG_TARGET_BF609_EZKIT=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_LIB_RAND=y
CONFIG_ARM=y
CONFIG_TARGET_BG0900=y
CONFIG_SPL=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_BAV_VERSION=1
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_BAV_VERSION=2
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BLACKSTAMP=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BLACKVME=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BR4=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_BUBINGA=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_MPC83xx=y
CONFIG_TARGET_VME8349=y
CONFIG_SYS_EXTRA_OPTIONS="CADDY2"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_CAIRO=y
CONFIG_SPL=y
-CONFIG_CMD_SETEXPR=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NET is not set
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_CALIMAIN=y
-CONFIG_CMD_NET=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR="\x0b"
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_CAM_ENC_4XX=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_CANMB=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_CANYONLANDS=y
CONFIG_CANYONLANDS=y
CONFIG_DEFAULT_DEVICE_TREE="canyonlands"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_TEGRA30=y
CONFIG_TARGET_CARDHU=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-cardhu"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_TARGET_CGTQMX6EVAL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx6eval/imximage.cfg,MX6Q"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_CHARON=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
CONFIG_TARGET_CHROMEBOOK_LINK=y
CONFIG_HAVE_MRC=y
-CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
-CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_CONTROL=y
CONFIG_DM_PCI=y
+CONFIG_SPI_FLASH=y
CONFIG_VIDEO_VESA=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_VSNPRINTF=y
CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther"
CONFIG_TARGET_CHROMEBOX_PANTHER=y
CONFIG_HAVE_MRC=y
-CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
-CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_CONTROL=y
CONFIG_DM_PCI=y
+CONFIG_SPI_FLASH=y
CONFIG_VIDEO_VESA=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_VSNPRINTF=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF527=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF533=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF537E=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF537U=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF548=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF561=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_CM5200=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_CM_FX6=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_CM_T335=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_CM_T3517=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_OMAP34XX=y
CONFIG_TARGET_CM_T35=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_OMAP54XX=y
CONFIG_TARGET_CM_T54=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
CONFIG_PPC=y
CONFIG_5xx=y
CONFIG_TARGET_CMI_MPC5XX=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_M68K=y
CONFIG_TARGET_COBRA5272=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_COLIBRI_PXA270=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TEGRA20=y
CONFIG_TARGET_COLIBRI_T20=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TEGRA30=y
CONFIG_TARGET_COLIBRI_T30=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_TARGET_COLIBRI_VF=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_DM=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
-CONFIG_DM=y
CONFIG_ARM=y
CONFIG_TARGET_COLIBRI_VF=y
+CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
-CONFIG_DM=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
CONFIG_MPC85xx=y
CONFIG_TARGET_CONTROLCENTERD=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD,DEVELOP"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_CONTROLCENTERD=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_CONTROLCENTERD=y
CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH,DEVELOP"
# CONFIG_CMD_BOOTM is not set
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_CONTROLCENTERD=y
CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH"
# CONFIG_CMD_BOOTM is not set
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_X86=y
CONFIG_VENDOR_COREBOOT=y
CONFIG_TARGET_COREBOOT=y
-CONFIG_CMD_NET=y
+CONFIG_TSC_CALIBRATION_BYPASS=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_CONTROL=y
CONFIG_DM_PCI=y
-CONFIG_TSC_CALIBRATION_BYPASS=y
+CONFIG_SPI_FLASH=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_VSNPRINTF=y
CONFIG_TARGET_CORVUS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_CPU9260=y
CONFIG_SYS_EXTRA_OPTIONS="CPU9260,CPU9260_128M"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_CPU9260=y
CONFIG_SYS_EXTRA_OPTIONS="CPU9260"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_CPU9260=y
CONFIG_SYS_EXTRA_OPTIONS="CPU9260,CPU9260_128M,NANDBOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_CPU9260=y
CONFIG_SYS_EXTRA_OPTIONS="CPU9260,NANDBOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_CPU9260=y
CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,CPU9G20_128M"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_CPU9260=y
CONFIG_SYS_EXTRA_OPTIONS="CPU9G20"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_CPU9260=y
CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,CPU9G20_128M,NANDBOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_CPU9260=y
CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,NANDBOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_CPUAT91=y
-CONFIG_CMD_NET=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_CPUAT91=y
-CONFIG_CMD_NET=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
CONFIG_DEFAULT_DEVICE_TREE="crownbay"
CONFIG_TARGET_CROWNBAY=y
CONFIG_GENERATE_PIRQ_TABLE=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_CONTROL=y
+CONFIG_SPI_FLASH=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_VSNPRINTF=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_CSB272=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_CSB472=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NET2BIG_V2=y
CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DA830EVM=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_DA850EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_DA850EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DA850EVM=y
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_TEGRA114=y
CONFIG_TARGET_DALMORE=y
CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_DM355EVM=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_DM355LEOPARD=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_DM365EVM=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_DM6467EVM=y
CONFIG_SYS_EXTRA_OPTIONS="DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_DM6467EVM=y
CONFIG_SYS_EXTRA_OPTIONS="REFCLK_FREQ=27000000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_DVEVM=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_SCHMOOGIE=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_SFFSDR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_SONATA=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_DB_88F6820_GP=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_DB_MV784MP_GP=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
CONFIG_SYS_EXTRA_OPTIONS="DBAU1000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
CONFIG_DBAU1100=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
CONFIG_DBAU1500=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
CONFIG_DBAU1550=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TARGET_DBAU1X00=y
CONFIG_DBAU1550=y
CONFIG_SYS_LITTLE_ENDIAN=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_4xx=y
CONFIG_TARGET_INTIP=y
CONFIG_SYS_EXTRA_OPTIONS="DEVCONCENTER"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_ARM=y
CONFIG_TARGET_DEVKIT3250=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_OMAP34XX=y
CONFIG_TARGET_DEVKIT8000=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_DIG297=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
CONFIG_PPC=y
-CONFIG_CMD_NET=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_DIGSY_MTC=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000"
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
-CONFIG_CMD_NET=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_DIGSY_MTC=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR=" "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
-CONFIG_CMD_NET=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_DIGSY_MTC=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000,DIGSY_REV5"
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
-CONFIG_CMD_NET=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_DIGSY_MTC=y
CONFIG_SYS_EXTRA_OPTIONS="DIGSY_REV5"
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_4xx=y
CONFIG_TARGET_DLVISION_10G=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_NFS is not set
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_DLVISION=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_NFS is not set
CONFIG_BLACKFIN=y
CONFIG_TARGET_DNP5370=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_DNS325=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_DOCKSTAR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,QSPI_BOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3,SPL_YMODEM_SUPPORT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_DRACO=y
-CONFIG_CMD_NET=y
CONFIG_SPL=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_DREAMPLUG=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_OMAP44XX=y
CONFIG_TARGET_DUOVERO=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_DXR2=y
-CONFIG_CMD_NET=y
-CONFIG_SPL=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
-CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_EA20=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_M68K=y
CONFIG_TARGET_EB_CPU5282=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_EB_CPU5282=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_EB_CPUX9K2=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_EB_CPUX9K2=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_EBONY=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_ECO5PK=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_SH=y
CONFIG_TARGET_ECOVEC=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_TARGET_EDB93XX=y
CONFIG_SYS_EXTRA_OPTIONS="MK_edb9315a"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ORION5X=y
CONFIG_TARGET_EDMINIV2=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_ENBW_CMC=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_SH=y
CONFIG_TARGET_ESPT=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_ETHERNUT5=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_FLEA3=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_SYS_EXTRA_OPTIONS="FO300"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-forfun-q88db"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
CONFIG_4xx=y
CONFIG_TARGET_FX12MM=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_4xx=y
CONFIG_TARGET_FX12MM=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_USB_MUSB_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ga10h-v1.1"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
CONFIG_AXP221_DLDO1_VOLT=3300
CONFIG_AXP221_ALDO1_VOLT=3000
CONFIG_X86=y
-CONFIG_NETDEVICES=y
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="galileo"
CONFIG_TARGET_GALILEO=y
-CONFIG_CMD_NET=y
+CONFIG_GENERATE_PIRQ_TABLE=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_VSNPRINTF=y
CONFIG_PPC=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_4xx=y
CONFIG_TARGET_GDPPC440ETX=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_TARGET_CANYONLANDS=y
CONFIG_GLACIER=y
CONFIG_DEFAULT_DEVICE_TREE="glacier"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_GLACIER=y
CONFIG_DEFAULT_DEVICE_TREE="glacier"
CONFIG_SYS_EXTRA_OPTIONS="SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_GOFLEXHOME=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_RMOBILE=y
CONFIG_TARGET_GOSE=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_SH_SDHI=y
CONFIG_ARM=y
CONFIG_TARGET_GPLUGD=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_SPARC=y
CONFIG_TARGET_GR_CPCI_AX2000=y
CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_SPARC=y
CONFIG_TARGET_GR_EP2S60=y
CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_SPARC=y
CONFIG_TARGET_GR_XC3S_1500=y
CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_AVR32=y
-CONFIG_CMD_NET=y
CONFIG_TARGET_GRASSHOPPER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_SPARC=y
CONFIG_TARGET_GRSIM=y
CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_MEMORY is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
CONFIG_SPARC=y
CONFIG_TARGET_GRSIM_LEON2=y
CONFIG_SYS_TEXT_BASE=0x00000000
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_MEMORY is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_GURUPLUG=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_GW_VENTANA=y
-CONFIG_SYS_MALLOC_F=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
CONFIG_ARM=y
CONFIG_TARGET_H2200=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_MEMORY is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_4xx=y
CONFIG_TARGET_KILAUEA=y
CONFIG_SYS_EXTRA_OPTIONS="HALEAKALA"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_TEGRA20=y
CONFIG_TARGET_HARMONY=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-harmony"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_ARCH_HIGHBANK=y
-CONFIG_CMD_NET=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds...\nPress <s> to stop or <d> to delay\n"
CONFIG_AUTOBOOT_KEYED_CTRLC=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
-CONFIG_CMD_NET=y
CONFIG_MPC83xx=y
CONFIG_TARGET_HRCON=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_USB_MUSB_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_IB62X0=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_BLACKFIN=y
CONFIG_TARGET_IBF_DSP561=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_LIB_RAND=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_ICON=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_ICONNECT=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
-CONFIG_CMD_NET=y
CONFIG_MPC83xx=y
CONFIG_TARGET_IDS8313=y
CONFIG_FIT=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n"
CONFIG_AUTOBOOT_DELAY_STR="ids"
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_IMA3_MX53=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_IMX27LITE=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_IMX31_LITEKIT=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_IMX31_PHYCORE=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_IMX31_PHYCORE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX31_PHYCORE_EET"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_INKA4X0=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM720T=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM920T=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM926EJ_S=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM946ES=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM1136=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM920T=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM926EJ_S=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM946ES=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_4xx=y
CONFIG_TARGET_INTIP=y
CONFIG_SYS_EXTRA_OPTIONS="INTIB"
CONFIG_PPC=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_4xx=y
CONFIG_TARGET_IO64=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_PPC=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_4xx=y
CONFIG_TARGET_IO=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_NFS is not set
CONFIG_PPC=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_4xx=y
CONFIG_TARGET_IOCON=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_NFS is not set
CONFIG_BLACKFIN=y
CONFIG_TARGET_IP04=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_IPAM390=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_IPEK01=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=312
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI,MACPWR=SUNXI_GPH(19)"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_TEGRA124=y
CONFIG_TARGET_JETSON_TK1=y
CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_TARGET_JORNADA=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_JUPITER=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_KEYSTONE=y
CONFIG_TARGET_K2E_EVM=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TARGET_K2HK_EVM=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TARGET_K2L_EVM=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_KATMAI=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_4xx=y
CONFIG_TARGET_KILAUEA=y
CONFIG_SYS_EXTRA_OPTIONS="KILAUEA"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_MPC85xx=y
CONFIG_TARGET_KMP204X=y
CONFIG_SYS_EXTRA_OPTIONS="KMCOGE4"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_MPC83xx=y
CONFIG_TARGET_KM8360=y
CONFIG_SYS_EXTRA_OPTIONS="KMCOGE5NE"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_MPC83xx=y
CONFIG_TARGET_KM8360=y
CONFIG_SYS_EXTRA_OPTIONS="KMETER1"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_KMP204X=y
CONFIG_SYS_EXTRA_OPTIONS="KMLION1"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_SYS_EXTRA_OPTIONS="KMOPTI2"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_SYS_EXTRA_OPTIONS="KM_SUGP1"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_SYS_EXTRA_OPTIONS="KMSUPX5"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_SYS_EXTRA_OPTIONS="KM_SUV31"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_MPC83xx=y
CONFIG_TARGET_SUVD3=y
CONFIG_SYS_EXTRA_OPTIONS="KMVECT1"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_ARM=y
CONFIG_RMOBILE=y
CONFIG_TARGET_KOELSCH=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_SH_SDHI=y
CONFIG_TARGET_KWB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_RMOBILE=y
CONFIG_TARGET_KZM9G=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_RMOBILE=y
CONFIG_TARGET_LAGER=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_SH_SDHI=y
CONFIG_TARGET_LWMON5=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="LCD4_LWMON5"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_LP8X4X=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_LS2085A_EMU=y
CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_ARM=y
CONFIG_TARGET_LS2085A_EMU=y
CONFIG_SYS_EXTRA_OPTIONS="EMU"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_ARM=y
CONFIG_TARGET_LS2085A_SIMU=y
CONFIG_SYS_EXTRA_OPTIONS="SIMU"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_ARM=y
CONFIG_TARGET_LS2085AQDS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_LS2085AQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_LS2085ARDB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_LS2085ARDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_KIRKWOOD=y
CONFIG_TARGET_LSXL=y
CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPI_FLASH=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_LSXL=y
CONFIG_SYS_EXTRA_OPTIONS="LSXHL"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_LUAN=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_LWMON5=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_M28EVK=y
CONFIG_SPL=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_M53EVK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/denx/m53evk/imximage.cfg"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
CONFIG_ARM=y
CONFIG_TARGET_MAGNESIUM=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_MAKALU=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_MIPS=y
CONFIG_TARGET_MALTA=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_MIPS=y
CONFIG_TARGET_MALTA=y
CONFIG_SYS_LITTLE_ENDIAN=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
CONFIG_DM=y
+CONFIG_SPI_FLASH=y
CONFIG_DM_THERMAL=y
CONFIG_ARM=y
CONFIG_TARGET_MAXBCM=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_MCX=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC512X=y
CONFIG_TARGET_MECP5123=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TEGRA20=y
CONFIG_TARGET_MEDCOM_WIDE=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-medcom-wide"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_MEESC=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_MEESC=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC8260=y
CONFIG_TARGET_KM82XX=y
CONFIG_SYS_EXTRA_OPTIONS="MGCOGE3NE"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_SYS_EXTRA_OPTIONS="KM_MGCOGE3UN"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_MPC8260=y
CONFIG_TARGET_KM82XX=y
CONFIG_SYS_EXTRA_OPTIONS="MGCOGE"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_TARGET_MICROBLAZE_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
CONFIG_TARGET_MINNOWMAX=y
CONFIG_HAVE_INTEL_ME=y
-CONFIG_VIDEO_VESA=y
-CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
-CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_SMP=y
CONFIG_GENERATE_SFI_TABLE=y
CONFIG_CMD_CPU=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_CONTROL=y
CONFIG_CPU=y
+CONFIG_SPI_FLASH=y
+CONFIG_VIDEO_VESA=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_VSNPRINTF=y
CONFIG_USB1_VBUS_PIN="PH24"
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
CONFIG_AXP221_ALDO1_VOLT=3300
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_DRAM_EMR1=0
CONFIG_USB1_VBUS_PIN="PB10"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_MACH_SUN4I=y
CONFIG_USB2_VBUS_PIN="PH12"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN4I=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_4xx=y
CONFIG_TARGET_ML507=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_4xx=y
CONFIG_TARGET_ML507=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_PPC=y
-CONFIG_CMD_NET=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_MOTIONPRO=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC512X=y
CONFIG_TARGET_MPC5121ADS=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC512X=y
CONFIG_TARGET_MPC5121ADS=y
CONFIG_SYS_EXTRA_OPTIONS="MPC5121ADS_REV2"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8308_P1M=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_SH=y
CONFIG_TARGET_MPR2=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SH=y
CONFIG_TARGET_MS7720SE=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SH=y
CONFIG_TARGET_MS7722SE=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SH=y
CONFIG_TARGET_MS7750SE=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_MEMORY is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_MT_VENTOUX=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_MUNICES=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_MV88F6281GTW_GE=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_MX23_OLINUXINO=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_MX23EVK=y
CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_TARGET_MX25PDK=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_MX28EVK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_MX28EVK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_MX28EVK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_MX28EVK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_SPI_FLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_MX31ADS=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_MX31PDK=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_MX35PDK=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_MX51_EFIKAMX=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_MX51_EFIKAMX=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_MX51EVK=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_MX53ARD=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
CONFIG_TARGET_MX53EVK=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53evk/imximage.cfg"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_MX53LOCO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_MX53SMD=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53smd/imximage.cfg"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_MX6CUBOXI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
CONFIG_DM=y
CONFIG_DM_THERMAL=y
CONFIG_ARM=y
CONFIG_TARGET_MX6QARM2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_MX6QARM2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_MX6QSABREAUTO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_MX6SABRESD=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_MX6QARM2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_MX6QARM2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_MX6QSABREAUTO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
CONFIG_DM=y
+CONFIG_SPI_FLASH=y
CONFIG_DM_THERMAL=y
CONFIG_ARM=y
CONFIG_TARGET_MX6SABRESD=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_MX6SABRESD=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_MX6SLEVK=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_DM=y
+CONFIG_SPI_FLASH=y
CONFIG_DM_THERMAL=y
CONFIG_ARM=y
CONFIG_TARGET_MX6SLEVK=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_DM=y
+CONFIG_SPI_FLASH=y
CONFIG_DM_THERMAL=y
CONFIG_ARM=y
CONFIG_TARGET_MX6SXSABRESD=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,MX6SX"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_TARGET_MX6SXSABRESD=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NAS220=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_NEO=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_NFS is not set
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NET2BIG_V2=y
CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_ARCH_NOMADIK=y
CONFIG_NOMADIK_NHK8815=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_NOMADIK=y
CONFIG_NOMADIK_NHK8815=y
CONFIG_SYS_EXTRA_OPTIONS="BOOT_ONENAND"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NIOS2=y
CONFIG_TARGET_NIOS2_GENERIC=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_NOKIA_RX51=y
CONFIG_AUTOBOOT_KEYED=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_TARGET_KOSAGI_NOVENA=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
CONFIG_TEGRA124=y
CONFIG_TARGET_NYAN_BIG=y
CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big"
-CONFIG_CMD_NET=y
-CONFIG_DISPLAY_PORT=y
-CONFIG_VIDEO_TEGRA124=y
-CONFIG_DM_CROS_EC=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_CROS_EC_KEYB=y
-CONFIG_CMD_CROS_EC=y
+CONFIG_DISPLAY_PORT=y
+CONFIG_VIDEO_TEGRA124=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_OCOTEA=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_ODROID_XU3=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
-CONFIG_CMD_NET=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_ODROID=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_MAX77686=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_MAX77686=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_ERRNO_STR=y
CONFIG_TARGET_OMAP3_BEAGLE=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_EVM=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_EVM_QUICK_MMC=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_MEMORY is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_EVM_QUICK_NAND=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_MEMORY is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_TARGET_TAO3530=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_LOGIC=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_MVBLX=y
-CONFIG_CMD_NET=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR="S"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_OVERO=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_PANDORA=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_SDP3430=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_ZOOM1=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_OMAP44XX=y
CONFIG_TARGET_OMAP4_PANDA=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
CONFIG_OMAP44XX=y
CONFIG_TARGET_OMAP4_SDP4430=y
CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_OMAP54XX=y
CONFIG_TARGET_OMAP5_UEVM=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_OMAPL138_LCDK=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_OPENRD=y
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_KIRKWOOD=y
CONFIG_TARGET_OPENRD=y
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_KIRKWOOD=y
CONFIG_TARGET_OPENRD=y
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_OPENRISC=y
CONFIG_TARGET_OPENRISC_GENERIC=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_ORIGEN=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
CONFIG_SPL=y
-CONFIG_CMD_SETEXPR=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_ARM=y
CONFIG_TARGET_OT1200=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_OT1200=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_OTC570=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_OTC570=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_P3P440=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_PALMLD=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_TARGET_PALMTC=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_TARGET_PALMTREO680=y
CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_TEGRA20=y
CONFIG_TARGET_PAZ00=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-paz00"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_MIPS=y
CONFIG_TARGET_PB1X00=y
CONFIG_SYS_EXTRA_OPTIONS="PB1000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_PCM030=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_PCM030=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_PCM051=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="REV1"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_PCM051=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="REV3"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_PCS440EP=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC512X=y
CONFIG_TARGET_PDM360NG=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_PEACH_PI=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi"
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_CROS_EC_KEYB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_TARGET_PEACH_PIT=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit"
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_CROS_EC_KEYB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_ARM=y
CONFIG_TARGET_PENGWYN=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_PEPPER=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
-CONFIG_SPL_DM=y
CONFIG_MACH_PH1_LD4=y
CONFIG_PFC_MICRO_SUPPORT_CARD=y
-CONFIG_NET=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_BDI=y
-CONFIG_CMD_CONSOLE=y
-CONFIG_CMD_BOOTD=y
-CONFIG_CMD_RUN=y
-CONFIG_CMD_IMI=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_EDITENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_MEMORY=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_LOADS=y
-CONFIG_CMD_FLASH=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
-CONFIG_CMD_ECHO=y
-CONFIG_CMD_ITEST=y
-CONFIG_CMD_SOURCE=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_NFS=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
-CONFIG_SPL_DM=y
CONFIG_PFC_MICRO_SUPPORT_CARD=y
-CONFIG_NET=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_BDI=y
-CONFIG_CMD_CONSOLE=y
-CONFIG_CMD_BOOTD=y
-CONFIG_CMD_RUN=y
-CONFIG_CMD_IMI=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_EDITENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_MEMORY=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_LOADS=y
-CONFIG_CMD_FLASH=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
-CONFIG_CMD_ECHO=y
-CONFIG_CMD_ITEST=y
-CONFIG_CMD_SOURCE=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_NFS=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
-CONFIG_SPL_DM=y
CONFIG_MACH_PH1_SLD8=y
CONFIG_PFC_MICRO_SUPPORT_CARD=y
-CONFIG_NET=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_BDI=y
-CONFIG_CMD_CONSOLE=y
-CONFIG_CMD_BOOTD=y
-CONFIG_CMD_RUN=y
-CONFIG_CMD_IMI=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_EDITENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_MEMORY=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_LOADS=y
-CONFIG_CMD_FLASH=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
-CONFIG_CMD_ECHO=y
-CONFIG_CMD_ITEST=y
-CONFIG_CMD_SOURCE=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_NFS=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_TARGET_PLATINUM_PICON=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_PLATINUM_TITANIUM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TEGRA20=y
CONFIG_TARGET_PLUTUX=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-plutux"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_PM9261=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_PM9263=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_PM9G45=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_POGO_E02=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_TRIZEPSIV=y
CONFIG_SYS_EXTRA_OPTIONS="POLARIS"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_RMOBILE=y
CONFIG_TARGET_PORTER=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_SH_SDHI=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_SYS_EXTRA_OPTIONS="KM_PORTL2"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_STAMP9G20=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,PORTUXG20"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_BLACKFIN=y
CONFIG_TARGET_PR1=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_ARM=y
CONFIG_TARGET_PXA255_IDP=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_PXM2=y
-CONFIG_CMD_NET=y
CONFIG_SPL=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_QEMU_PPCE500=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
CONFIG_X86=y
-CONFIG_VENDOR_EMULATION=y
CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
-CONFIG_TARGET_QEMU_X86=y
CONFIG_GENERATE_PIRQ_TABLE=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_CONTROL=y
+CONFIG_SPI_FLASH=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_111=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_VSNPRINTF=y
CONFIG_MIPS=y
CONFIG_TARGET_QEMU_MIPS=y
CONFIG_CPU_MIPS64_R1=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TARGET_QEMU_MIPS=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_CPU_MIPS64_R1=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_MIPS=y
CONFIG_TARGET_QEMU_MIPS=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_MIPS=y
CONFIG_TARGET_QEMU_MIPS=y
CONFIG_SYS_LITTLE_ENDIAN=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_TARGET_QONG=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_SH=y
CONFIG_TARGET_R0P7734=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SH=y
CONFIG_TARGET_R2DPLUS=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_DRAM_CLK=384
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_SH=y
CONFIG_TARGET_R7780MP=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_SYS_EXTRA_OPTIONS="RAINIER"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_SYS_EXTRA_OPTIONS="RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_RASTABAN=y
+CONFIG_SPL=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
+CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_RD6281A=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_REDWOOD=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_ARM=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
CONFIG_DM=y
+CONFIG_SPI_FLASH=y
CONFIG_DM_THERMAL=y
CONFIG_ARM=y
CONFIG_ARCH_BCM283X=y
CONFIG_TARGET_RPI_2=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_PHYS_TO_BUS=y
CONFIG_ARM=y
CONFIG_ARCH_BCM283X=y
CONFIG_TARGET_RPI=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_PHYS_TO_BUS=y
CONFIG_SH=y
CONFIG_TARGET_RSK7203=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SH=y
CONFIG_TARGET_RSK7264=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SH=y
CONFIG_TARGET_RSK7269=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_TARGET_RUT=y
-CONFIG_CMD_NET=y
CONFIG_SPL=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARCH_S5PC1XX=y
CONFIG_TARGET_S5P_GONI=y
CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_S5PC210_UNIVERSAL=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210"
-CONFIG_CMD_SETEXPR=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_TARGET_SAMA5D3_XPLAINED=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
CONFIG_TARGET_SAMA5D3_XPLAINED=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_SAMA5D4_XPLAINED=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_SAMA5D4_XPLAINED=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_SAMA5D4_XPLAINED=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_SAMA5D4EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_SAMA5D4EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_SAMA5D4EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
-CONFIG_DM_USB=y
-CONFIG_NETDEVICES=y
-CONFIG_DM_ETH=y
CONFIG_PCI=y
-CONFIG_SYS_VSNPRINTF=y
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SOUND=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_OF_HOSTFILE=y
CONFIG_DM_PCI=y
CONFIG_PCI_SANDBOX=y
+CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SANDBOX=y
+CONFIG_DM_ETH=y
CONFIG_CROS_EC_KEYB=y
+CONFIG_SANDBOX_SERIAL=y
CONFIG_TPM_TIS_SANDBOX=y
CONFIG_SYS_I2C_SANDBOX=y
CONFIG_SANDBOX_SPI=y
CONFIG_SOUND=y
CONFIG_SOUND_SANDBOX=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EMUL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_RTC=y
+CONFIG_SYS_VSNPRINTF=y
CONFIG_ERRNO_STR=y
CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
CONFIG_UT_ENV=y
-CONFIG_SANDBOX_SERIAL=y
CONFIG_ARM=y
CONFIG_TARGET_SANSA_FUZE_PLUS=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_SBC405=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_SBC8349=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_SBC8349=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_SBC8349=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_SBC8548=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,33,PCIE"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_SBC8548=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,33"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_SBC8548=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,66,PCIE"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_SBC8548=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,66"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_SBC8548=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC86xx=y
CONFIG_TARGET_SBC8641D=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_SC_SPS_1=y
CONFIG_SPL=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
CONFIG_ARM=y
CONFIG_TARGET_SCB9328=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TEGRA20=y
CONFIG_TARGET_SEABOARD=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-seaboard"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SECOMX6Q=y
CONFIG_SECOMX6_2GB=y
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_SH=y
CONFIG_SH_32BIT=y
CONFIG_TARGET_SH7752EVB=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_SPI_FLASH=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SH=y
CONFIG_TARGET_SH7753EVB=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_SPI_FLASH=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SH=y
CONFIG_SH_32BIT=y
CONFIG_TARGET_SH7757LCR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_SPI_FLASH=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SH=y
CONFIG_TARGET_SH7763RDP=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SH=y
CONFIG_SH_32BIT=y
CONFIG_TARGET_SH7785LCR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SH=y
CONFIG_TARGET_SH7785LCR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_SHEEVAPLUG=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_SH=y
CONFIG_TARGET_SHMIN=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_RMOBILE=y
CONFIG_TARGET_SILK=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_SH_SDHI=y
CONFIG_ARM=y
CONFIG_TARGET_SMDK2410=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_SMDK5250=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250"
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SOUND=y
+CONFIG_SPI_FLASH=y
CONFIG_SOUND=y
CONFIG_I2S=y
CONFIG_I2S_SAMSUNG=y
CONFIG_SOUND_MAX98095=y
CONFIG_SOUND_WM8994=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_TARGET_SMDK5420=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420"
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_ARCH_S5PC1XX=y
CONFIG_TARGET_SMDKC100=y
CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_SMDKV310=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310"
CONFIG_SPL=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SNAPPER9260=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SNAPPER9260=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_SNOW=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow"
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SOUND=y
+CONFIG_SPI_FLASH=y
CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_I2S_SAMSUNG=y
CONFIG_SOUND_MAX98095=y
CONFIG_SOUND_WM8994=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_ARM=y
CONFIG_TARGET_SNOWBALL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_TARGET_SOCFPGA_ARRIA5=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
CONFIG_SPL=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
CONFIG_OF_CONTROL=y
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_TARGET_SOCFPGA_CYCLONE5=y
-CONFIG_NETDEVICES=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
CONFIG_SPL=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
CONFIG_OF_CONTROL=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_TARGET_SOCFPGA_CYCLONE5=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
-CONFIG_NETDEVICES=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_SPL=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_SOCRATES=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_TARGET_SPEAR300=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear300"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR300=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear300,nand"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR300=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear300,usbtty"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR300=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear300,usbtty,nand"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR310=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear310"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR310=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear310,nand"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR310=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear310,FLASH_PNOR"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR310=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR310=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty,nand"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR310=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty,FLASH_PNOR"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR320=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear320"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR320=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear320,nand"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR320=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear320,FLASH_PNOR"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR320=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR320=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty,nand"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR320=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty,FLASH_PNOR"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR600=y
-CONFIG_NETDEVICES=y
-CONFIG_CMD_NET=y
CONFIG_SYS_EXTRA_OPTIONS="spear600"
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR600=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear600,nand"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR600=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear600,usbtty"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR600=y
-CONFIG_NETDEVICES=y
CONFIG_SYS_EXTRA_OPTIONS="spear600,usbtty,nand"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_STAMP9G20=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_STM32F429_DISCOVERY=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_STV0991=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NETDEVICES=y
-CONFIG_CMD_NET=y
CONFIG_DEFAULT_DEVICE_TREE="stv0991"
CONFIG_SYS_EXTRA_OPTIONS="stv0991"
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_STXGP3=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_STXSSA=y
CONFIG_SYS_EXTRA_OPTIONS="STXSSA_4M"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_STXSSA=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_MPC83xx=y
CONFIG_TARGET_SUVD3=y
CONFIG_SYS_EXTRA_OPTIONS="SUVD3"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_WALNUT=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_T3CORP=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_TAIHU=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_TAISHAN=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_TAO3530=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_TAURUS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARC_CACHE_LINE_SHIFT=5
CONFIG_TARGET_TB100=y
CONFIG_SYS_CLK_FREQ=500000000
-CONFIG_NETDEVICES=y
-CONFIG_DM_SERIAL=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="abilis_tb100"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DM=y
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SERIAL=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_TARGET_TBS2910=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
CONFIG_DM=y
CONFIG_DM_THERMAL=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_TCM_BF518=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_TCM_BF537=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_TEGRA30=y
CONFIG_TARGET_TEC_NG=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-tec-ng"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TEGRA20=y
CONFIG_TARGET_TEC=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-tec"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_THUBAN=y
+CONFIG_SPL=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
+CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_TI814X_EVM=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_TI816X_EVM=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_TITANIUM=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/barco/titanium/imximage.cfg"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_TK71=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_TQMA6=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_TQMA6=y
CONFIG_TQMA6X_SPI_BOOT=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_TQMA6=y
CONFIG_TQMA6S=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_TARGET_TQMA6=y
CONFIG_TQMA6S=y
CONFIG_TQMA6X_SPI_BOOT=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_TRATS2=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2"
-CONFIG_CMD_SETEXPR=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_TRATS=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats"
-CONFIG_CMD_SETEXPR=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_TRICORDER=y
CONFIG_SPL=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_TARGET_TRICORDER=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_TEGRA20=y
CONFIG_TARGET_TRIMSLICE=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-trimslice"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_TARGET_TRIZEPSIV=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_TSERIES=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
CONFIG_TARGET_TSERIES=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
CONFIG_TARGET_TSERIES=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
-CONFIG_CMD_NET=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_TT01=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_SYS_EXTRA_OPTIONS="TUGE1"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_SYS_EXTRA_OPTIONS="TUXX1"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_TWISTER=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_TX25=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_U8500_HREF=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_TARGET_UDOO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_USB_A9263=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_TARGET_USBARMORY=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_V38B=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_4xx=y
CONFIG_TARGET_V5FX30TEVAL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_4xx=y
CONFIG_TARGET_V5FX30TEVAL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUM=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUM=y
CONFIG_VCT_ONENAND=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_VCT_PLATINUM=y
CONFIG_VCT_ONENAND=y
CONFIG_VCT_SMALL_IMAGE=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUM=y
CONFIG_VCT_SMALL_IMAGE=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUMAVC=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUMAVC=y
CONFIG_VCT_ONENAND=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_VCT_PLATINUMAVC=y
CONFIG_VCT_ONENAND=y
CONFIG_VCT_SMALL_IMAGE=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUMAVC=y
CONFIG_VCT_SMALL_IMAGE=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
CONFIG_VCT_PREMIUM=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TARGET_VCT=y
CONFIG_VCT_PREMIUM=y
CONFIG_VCT_ONENAND=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_VCT_PREMIUM=y
CONFIG_VCT_ONENAND=y
CONFIG_VCT_SMALL_IMAGE=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TARGET_VCT=y
CONFIG_VCT_PREMIUM=y
CONFIG_VCT_SMALL_IMAGE=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_VE8313=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TEGRA124=y
CONFIG_TARGET_VENICE2=y
CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TEGRA20=y
CONFIG_TARGET_VENTANA=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-ventana"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_ARCH_VERSATILE=y
CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_AB"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_ARM=y
CONFIG_ARCH_VERSATILE=y
CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_PB"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_ARM=y
CONFIG_ARCH_VERSATILE=y
CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS64_JUNO=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="vexpress64"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS64_BASE_FVP=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="vexpress64"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS_CA15_TC2=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS_CA5X2=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS_CA9X4=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
CONFIG_ARM=y
CONFIG_TARGET_VF610TWR=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_MMC"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_VF610TWR=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_NAND"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_VISION2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_VL_MA2SC=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_VL_MA2SC=y
CONFIG_SYS_EXTRA_OPTIONS="RAMLOAD"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_VME8349=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_VPAC270=y
CONFIG_SYS_EXTRA_OPTIONS="NOR,RAM_128M"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_VPAC270=y
CONFIG_SYS_EXTRA_OPTIONS="NOR,RAM_256M"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_VPAC270=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ONENAND,RAM_256M"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_WALNUT=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_TARGET_WANDBOARD=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
CONFIG_DM=y
CONFIG_DM_THERMAL=y
CONFIG_ARM=y
CONFIG_TARGET_WARP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_TEGRA20=y
CONFIG_TARGET_WHISTLER=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-whistler"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_WIRELESS_SPACE=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_WOODBURN=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_WOODBURN_SD=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_WORK_92105=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_8xx=y
CONFIG_TARGET_TQM823L=y
CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ065T9DR51U"
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_X600=y
-CONFIG_NETDEVICES=y
-CONFIG_CMD_NET=y
CONFIG_SPL=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_XAENIAX=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_XFI3=y
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_4xx=y
CONFIG_TARGET_XILINX_PPC405_GENERIC=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_4xx=y
CONFIG_TARGET_XILINX_PPC405_GENERIC=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_4xx=y
CONFIG_TARGET_XILINX_PPC440_GENERIC=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_4xx=y
CONFIG_TARGET_XILINX_PPC440_GENERIC=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_TARGET_XILINX_ZYNQMP=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp"
-CONFIG_CMD_BDI=y
-CONFIG_CMD_BOOTD=y
-CONFIG_CMD_RUN=y
-CONFIG_CMD_IMI=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_ECHO=y
-CONFIG_CMD_SOURCE=y
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_CMD_TIME=y
-CONFIG_CMD_MISC=y
CONFIG_CMD_TIMER=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_XPEDITE1000=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC86xx=y
CONFIG_TARGET_XPEDITE517X=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_XPEDITE520X=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_XPEDITE537X=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_XPEDITE550X=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_4xx=y
CONFIG_TARGET_YOSEMITE=y
CONFIG_SYS_EXTRA_OPTIONS="YELLOWSTONE"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_4xx=y
CONFIG_TARGET_YOSEMITE=y
CONFIG_SYS_EXTRA_OPTIONS="YOSEMITE"
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_YUCCA=y
-CONFIG_CMD_SETEXPR=y
-CONFIG_CMD_NET=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_ZEUS=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_ZIPITZ2=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_TARGET_ZMX25=y
-CONFIG_CMD_NET=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="boot in %d s\n"
CONFIG_AUTOBOOT_DELAY_STR="delaygs"
CONFIG_AUTOBOOT_STOP_STR="stopgs"
+# CONFIG_CMD_SETEXPR is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
-CONFIG_CMD_NET=y
-CONFIG_OF_CONTROL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_ZYNQ_PICOZED=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
CONFIG_SPL=y
-CONFIG_CMD_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
-CONFIG_CMD_NET=y
-CONFIG_OF_CONTROL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
-CONFIG_CMD_NET=y
-CONFIG_OF_CONTROL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_TARGET_ZYNQ_ZC70X=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
-CONFIG_CMD_NET=y
-CONFIG_OF_CONTROL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_TARGET_ZYNQ_ZC770=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
-CONFIG_CMD_NET=y
-CONFIG_OF_CONTROL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_TARGET_ZYNQ_ZC770=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
-CONFIG_CMD_NET=y
-CONFIG_OF_CONTROL=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_TARGET_ZYNQ_ZC770=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
-CONFIG_CMD_NET=y
-CONFIG_OF_CONTROL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_TARGET_ZYNQ_ZED=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
-CONFIG_CMD_NET=y
-CONFIG_OF_CONTROL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_TARGET_ZYNQ_ZYBO=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
-CONFIG_CMD_NET=y
-CONFIG_OF_CONTROL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
--- /dev/null
+Zynq SPI controller Device Tree Bindings
+----------------------------------------
+
+Required properties:
+- compatible : Should be "xlnx,spi-zynq".
+- reg : Physical base address and size of SPI registers map.
+- status : Status will be disabled in dtsi and enabled in required dts.
+- interrupt-parent : Must be core interrupt controller.
+- interrupts : Property with a value describing the interrupt
+ number.
+- clocks : Clock phandles (see clock bindings for details).
+- clock-names : List of input clock names - "ref_clk", "pclk"
+ (See clock bindings for details).
+- spi-max-frequency : Maximum SPI clocking speed of device in Hz
+
+Example:
+
+ spi@e0006000 {
+ compatible = "xlnx,zynq-spi";
+ reg = <0xe0006000 0x1000>;
+ status = "disabled";
+ interrupt-parent = <&intc>;
+ interrupts = <0 26 4>;
+ clocks = <&clkc 25>, <&clkc 34>;
+ clock-names = "ref_clk", "pclk";
+ spi-max-frequency = <166666700>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ } ;
endmenu
config PHYS_TO_BUS
- bool
+ bool "Custom physical to bus address mapping"
help
Some SoCs use a different address map for CPU physical addresses and
peripheral DMA master accesses. If yours does, select this option in
/* Maximum timeouts for each event */
#define WAIT_MS_SPINUP 20000
-#define WAIT_MS_DATAIO 5000
+#define WAIT_MS_DATAIO 10000
#define WAIT_MS_FLUSH 5000
#define WAIT_MS_LINKUP 200
*/
static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
{
- u32 lba = 0;
+ lbaint_t lba = 0;
u16 blocks = 0;
u8 fis[20];
u8 *user_buffer = pccb->pdata;
u32 user_buffer_size = pccb->datalen;
/* Retrieve the base LBA number from the ccb structure. */
- memcpy(&lba, pccb->cmd + 2, sizeof(lba));
- lba = be32_to_cpu(lba);
+ if (pccb->cmd[0] == SCSI_READ16) {
+ memcpy(&lba, pccb->cmd + 2, 8);
+ lba = be64_to_cpu(lba);
+ } else {
+ u32 temp;
+ memcpy(&temp, pccb->cmd + 2, 4);
+ lba = be32_to_cpu(temp);
+ }
/*
- * And the number of blocks.
+ * Retrieve the base LBA number and the block count from
+ * the ccb structure.
*
* For 10-byte and 16-byte SCSI R/W commands, transfer
* length 0 means transfer 0 block of data.
*
* WARNING: one or two older ATA drives treat 0 as 0...
*/
- blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
+ if (pccb->cmd[0] == SCSI_READ16)
+ blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
+ else
+ blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
- debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
- is_write ? "write" : "read", (unsigned)lba, blocks);
+ debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
+ is_write ? "write" : "read", blocks, lba);
/* Preset the FIS */
memset(fis, 0, sizeof(fis));
return -EIO;
}
- /* LBA48 SATA command but only use 32bit address range within
- * that. The next smaller command range (28bit) is too small.
+ /*
+ * LBA48 SATA command but only use 32bit address range within
+ * that (unless we've enabled 64bit LBA support). The next
+ * smaller command range (28bit) is too small.
*/
fis[4] = (lba >> 0) & 0xff;
fis[5] = (lba >> 8) & 0xff;
fis[6] = (lba >> 16) & 0xff;
fis[7] = 1 << 6; /* device reg: set LBA mode */
fis[8] = ((lba >> 24) & 0xff);
+#ifdef CONFIG_SYS_64BIT_LBA
+ if (pccb->cmd[0] == SCSI_READ16) {
+ fis[9] = ((lba >> 32) & 0xff);
+ fis[10] = ((lba >> 40) & 0xff);
+ }
+#endif
+
fis[3] = 0xe0; /* features */
/* Block (sector) count */
int ret;
switch (pccb->cmd[0]) {
+ case SCSI_READ16:
case SCSI_READ10:
ret = ata_scsiop_read_write(pccb, 0);
break;
* (Which is just as well - otherwise we'd have to nobble the DMA engine
* too)
*/
- while (get_timer(bcm_host->last_write) < bcm_host->twoticks_delay)
+ while (timer_get_us() - bcm_host->last_write < bcm_host->twoticks_delay)
;
writel(val, host->ioaddr + reg);
- bcm_host->last_write = get_timer(0);
+ bcm_host->last_write = timer_get_us();
}
static inline u32 bcm2835_sdhci_raw_readl(struct sdhci_host *host, int reg)
#include <config.h>
#include <common.h>
#include <part.h>
+#include <div64.h>
+#include <linux/math64.h>
#include "mmc_private.h"
static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt)
unsigned long mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt)
{
int err = 0;
+ u32 start_rem, blkcnt_rem;
struct mmc *mmc = find_mmc_device(dev_num);
lbaint_t blk = 0, blk_r = 0;
int timeout = 1000;
if (!mmc)
return -1;
- if ((start % mmc->erase_grp_size) || (blkcnt % mmc->erase_grp_size))
+ /*
+ * We want to see if the requested start or total block count are
+ * unaligned. We discard the whole numbers and only care about the
+ * remainder.
+ */
+ err = div_u64_rem(start, mmc->erase_grp_size, &start_rem);
+ err = div_u64_rem(blkcnt, mmc->erase_grp_size, &blkcnt_rem);
+ if (start_rem || blkcnt_rem)
printf("\n\nCaution! Your devices Erase group is 0x%x\n"
"The erase range would be change to "
"0x" LBAF "~0x" LBAF "\n\n",
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq (,$(findstring y,$(CONFIG_MTD_DEVICE)$(CONFIG_CMD_NAND)$(CONFIG_CMD_ONENAND)))
-obj-y += mtdcore.o
+ifneq (,$(findstring y,$(CONFIG_MTD_DEVICE)$(CONFIG_CMD_NAND)$(CONFIG_CMD_ONENAND)$(CONFIG_CMD_SF)))
+obj-y += mtdcore.o mtd_uboot.o
endif
obj-$(CONFIG_MTD_PARTITIONS) += mtdpart.o
obj-$(CONFIG_MTD_CONCAT) += mtdconcat.o
--- /dev/null
+/*
+ * (C) Copyright 2014
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <linux/mtd/mtd.h>
+#include <jffs2/jffs2.h>
+
+static int get_part(const char *partname, int *idx, loff_t *off, loff_t *size,
+ loff_t *maxsize, int devtype)
+{
+#ifdef CONFIG_CMD_MTDPARTS
+ struct mtd_device *dev;
+ struct part_info *part;
+ u8 pnum;
+ int ret;
+
+ ret = mtdparts_init();
+ if (ret)
+ return ret;
+
+ ret = find_dev_and_part(partname, &dev, &pnum, &part);
+ if (ret)
+ return ret;
+
+ if (dev->id->type != devtype) {
+ printf("not same typ %d != %d\n", dev->id->type, devtype);
+ return -1;
+ }
+
+ *off = part->offset;
+ *size = part->size;
+ *maxsize = part->size;
+ *idx = dev->id->num;
+
+ return 0;
+#else
+ puts("offset is not a number\n");
+ return -1;
+#endif
+}
+
+int mtd_arg_off(const char *arg, int *idx, loff_t *off, loff_t *size,
+ loff_t *maxsize, int devtype, int chipsize)
+{
+ if (!str2off(arg, off))
+ return get_part(arg, idx, off, size, maxsize, devtype);
+
+ if (*off >= chipsize) {
+ puts("Offset exceeds device limit\n");
+ return -1;
+ }
+
+ *maxsize = chipsize - *off;
+ *size = *maxsize;
+ return 0;
+}
+
+int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off,
+ loff_t *size, loff_t *maxsize, int devtype, int chipsize)
+{
+ int ret;
+
+ if (argc == 0) {
+ *off = 0;
+ *size = chipsize;
+ *maxsize = *size;
+ goto print;
+ }
+
+ ret = mtd_arg_off(argv[0], idx, off, size, maxsize, devtype,
+ chipsize);
+ if (ret)
+ return ret;
+
+ if (argc == 1)
+ goto print;
+
+ if (!str2off(argv[1], size)) {
+ printf("'%s' is not a number\n", argv[1]);
+ return -1;
+ }
+
+ if (*size > *maxsize) {
+ puts("Size exceeds partition or device limit\n");
+ return -1;
+ }
+
+print:
+ printf("device %d ", *idx);
+ if (*size == chipsize)
+ puts("whole chip\n");
+ else
+ printf("offset 0x%llx, size 0x%llx\n",
+ (unsigned long long)*off, (unsigned long long)*size);
+ return 0;
+}
obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o
-obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o
endif # drivers
return 0;
}
+#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
+
+#define PREFETCH_CONFIG1_CS_SHIFT 24
+#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
+#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
+#define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
+#define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
+#define ENABLE_PREFETCH (1 << 7)
+
+/**
+ * omap_prefetch_enable - configures and starts prefetch transfer
+ * @fifo_th: fifo threshold to be used for read/ write
+ * @count: number of bytes to be transferred
+ * @is_write: prefetch read(0) or write post(1) mode
+ * @cs: chip select to use
+ */
+static int omap_prefetch_enable(int fifo_th, unsigned int count, int is_write, int cs)
+{
+ uint32_t val;
+
+ if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
+ return -EINVAL;
+
+ if (readl(&gpmc_cfg->prefetch_control))
+ return -EBUSY;
+
+ /* Set the amount of bytes to be prefetched */
+ writel(count, &gpmc_cfg->prefetch_config2);
+
+ val = (cs << PREFETCH_CONFIG1_CS_SHIFT) | (is_write & 1) |
+ PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH;
+ writel(val, &gpmc_cfg->prefetch_config1);
+
+ /* Start the prefetch engine */
+ writel(1, &gpmc_cfg->prefetch_control);
+
+ return 0;
+}
+
+/**
+ * omap_prefetch_reset - disables and stops the prefetch engine
+ */
+static void omap_prefetch_reset(void)
+{
+ writel(0, &gpmc_cfg->prefetch_control);
+ writel(0, &gpmc_cfg->prefetch_config1);
+}
+
+static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int len)
+{
+ int ret;
+ uint32_t cnt;
+ struct omap_nand_info *info = chip->priv;
+
+ ret = omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX, len, 0, info->cs);
+ if (ret < 0)
+ return ret;
+
+ do {
+ int i;
+
+ cnt = readl(&gpmc_cfg->prefetch_status);
+ cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
+
+ for (i = 0; i < cnt / 4; i++) {
+ *buf++ = readl(CONFIG_SYS_NAND_BASE);
+ len -= 4;
+ }
+ } while (len);
+
+ omap_prefetch_reset();
+
+ return 0;
+}
+
+static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ if (chip->options & NAND_BUSWIDTH_16)
+ nand_read_buf16(mtd, buf, len);
+ else
+ nand_read_buf(mtd, buf, len);
+}
+
+static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ int ret;
+ uint32_t head, tail;
+ struct nand_chip *chip = mtd->priv;
+
+ /*
+ * If the destination buffer is unaligned, start with reading
+ * the overlap byte-wise.
+ */
+ head = ((uint32_t) buf) % 4;
+ if (head) {
+ omap_nand_read(mtd, buf, head);
+ buf += head;
+ len -= head;
+ }
+
+ /*
+ * Only transfer multiples of 4 bytes in a pre-fetched fashion.
+ * If there's a residue, care for it byte-wise afterwards.
+ */
+ tail = len % 4;
+
+ ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail);
+ if (ret < 0) {
+ /* fallback in case the prefetch engine is busy */
+ omap_nand_read(mtd, buf, len);
+ } else if (tail) {
+ buf += len - tail;
+ omap_nand_read(mtd, buf, tail);
+ }
+}
+#endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
+
#ifdef CONFIG_NAND_OMAP_ELM
/*
* omap_reverse_list - re-orders list elements in reverse order [internal]
return (err) ? err : error_count;
}
-#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
-
-#define PREFETCH_CONFIG1_CS_SHIFT 24
-#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
-#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
-#define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
-#define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
-#define ENABLE_PREFETCH (1 << 7)
-
-/**
- * omap_prefetch_enable - configures and starts prefetch transfer
- * @fifo_th: fifo threshold to be used for read/ write
- * @count: number of bytes to be transferred
- * @is_write: prefetch read(0) or write post(1) mode
- * @cs: chip select to use
- */
-static int omap_prefetch_enable(int fifo_th, unsigned int count, int is_write, int cs)
-{
- uint32_t val;
-
- if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
- return -EINVAL;
-
- if (readl(&gpmc_cfg->prefetch_control))
- return -EBUSY;
-
- /* Set the amount of bytes to be prefetched */
- writel(count, &gpmc_cfg->prefetch_config2);
-
- val = (cs << PREFETCH_CONFIG1_CS_SHIFT) | (is_write & 1) |
- PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH;
- writel(val, &gpmc_cfg->prefetch_config1);
-
- /* Start the prefetch engine */
- writel(1, &gpmc_cfg->prefetch_control);
-
- return 0;
-}
-
-/**
- * omap_prefetch_reset - disables and stops the prefetch engine
- */
-static void omap_prefetch_reset(void)
-{
- writel(0, &gpmc_cfg->prefetch_control);
- writel(0, &gpmc_cfg->prefetch_config1);
-}
-
-static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int len)
-{
- int ret;
- uint32_t cnt;
- struct omap_nand_info *info = chip->priv;
-
- ret = omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX, len, 0, info->cs);
- if (ret < 0)
- return ret;
-
- do {
- int i;
-
- cnt = readl(&gpmc_cfg->prefetch_status);
- cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
-
- for (i = 0; i < cnt / 4; i++) {
- *buf++ = readl(CONFIG_SYS_NAND_BASE);
- len -= 4;
- }
- } while (len);
-
- omap_prefetch_reset();
-
- return 0;
-}
-
-static void omap_nand_read_prefetch8(struct mtd_info *mtd, uint8_t *buf, int len)
-{
- int ret;
- uint32_t head, tail;
- struct nand_chip *chip = mtd->priv;
-
- /*
- * If the destination buffer is unaligned, start with reading
- * the overlap byte-wise.
- */
- head = ((uint32_t) buf) % 4;
- if (head) {
- nand_read_buf(mtd, buf, head);
- buf += head;
- len -= head;
- }
-
- /*
- * Only transfer multiples of 4 bytes in a pre-fetched fashion.
- * If there's a residue, care for it byte-wise afterwards.
- */
- tail = len % 4;
-
- ret = __read_prefetch_aligned(chip, (uint32_t *) buf, len - tail);
- if (ret < 0) {
- /* fallback in case the prefetch engine is busy */
- nand_read_buf(mtd, buf, len);
- } else if (tail) {
- buf += len - tail;
- nand_read_buf(mtd, buf, tail);
- }
-}
-#endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
-
/**
* omap_read_page_bch - hardware ecc based page read function
* @mtd: mtd info structure
if (err)
return err;
- /* TODO: Implement for 16-bit bus width */
- if (nand->options & NAND_BUSWIDTH_16)
- nand->read_buf = nand_read_buf16;
#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
- else
- nand->read_buf = omap_nand_read_prefetch8;
+ nand->read_buf = omap_nand_read_prefetch;
#else
+ if (nand->options & NAND_BUSWIDTH_16)
+ nand->read_buf = nand_read_buf16;
else
nand->read_buf = nand_read_buf;
#endif
+++ /dev/null
-/*
- * Copyright (c) 2014, Antmicro Ltd <www.antmicro.com>
- * Copyright (c) 2015, Turtle Solutions <www.turtle-solutions.eu>
- * Copyright (c) 2015, Roy Spliet <rspliet@ultimaker.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * \todo Detect chip parameters (page size, ECC mode, randomisation...)
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/dma.h>
-#include <asm/arch/nand.h>
-
-void
-nand_init(void)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- struct sunxi_nand * const nand = (struct sunxi_nand *)SUNXI_NFC_BASE;
- u32 val;
-
- board_nand_init();
-
- /* "un-gate" NAND clock and clock source
- * This assumes that the clock was already correctly configured by
- * BootROM */
- setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0));
-#ifdef CONFIG_MACH_SUN9I
- setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
-#else
- setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
-#endif
- setbits_le32(&ccm->nand0_clk_cfg, 0x80000000);
-
- val = readl(&nand->ctl);
- val |= SUNXI_NAND_CTL_RST;
- writel(val, &nand->ctl);
-
- /* Wait until reset pin is deasserted */
- do {
- val = readl(&nand->ctl);
- if (!(val & SUNXI_NAND_CTL_RST))
- break;
- } while (1);
-
- /** \todo Chip select, currently kind of static */
- val = readl(&nand->ctl);
- val &= 0xf0fff0f2;
- val |= SUNXI_NAND_CTL_EN;
- val |= SUNXI_NAND_CTL_PAGE_SIZE(CONFIG_NAND_SUNXI_PAGE_SIZE);
- writel(val, &nand->ctl);
-
- writel(0x100, &nand->timing_ctl);
- writel(0x7ff, &nand->timing_cfg);
-
- /* reset CMD */
- val = SUNXI_NAND_CMD_SEND_CMD1 | SUNXI_NAND_CMD_WAIT_FLAG |
- NAND_CMD_RESET;
- writel(val, &nand->cmd);
- do {
- val = readl(&nand->st);
- if (val & (1<<1))
- break;
- udelay(1000);
- } while (1);
-
- printf("Nand initialised\n");
-}
-
-int
-nand_wait_timeout(u32 *reg, u32 mask, u32 val)
-{
- unsigned long tmo = timer_get_us() + 1000000; /* 1s */
-
- while ((readl(reg) & mask) != val) {
- if (timer_get_us() > tmo)
- return -ETIMEDOUT;
- }
-
- return 0;
-}
-
-/* random seed */
-static const uint16_t random_seed[128] = {
- 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
- 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
- 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
- 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
- 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
- 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
- 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
- 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
- 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
- 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
- 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
- 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
- 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
- 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
- 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
- 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
-};
-
-uint32_t ecc_errors = 0;
-
-static void
-nand_config_ecc(struct sunxi_nand *nand, uint32_t page, int syndrome)
-{
- static u8 strength[] = {16, 24, 28, 32, 40, 48, 56, 60, 64};
- int i;
- uint32_t ecc_mode;
- u32 ecc;
- u16 seed = 0;
-
- for (i = 0; i < ARRAY_SIZE(strength); i++) {
- if (CONFIG_NAND_SUNXI_ECC_STRENGTH == strength[i]) {
- ecc_mode = i;
- break;
- }
- }
-
- if (i == ARRAY_SIZE(strength)) {
- printf("ECC strength unsupported\n");
- return;
- }
-
- ecc = SUNXI_NAND_ECC_CTL_ECC_EN |
- SUNXI_NAND_ECC_CTL_PIPELINE |
- SUNXI_NAND_ECC_CTL_RND_EN |
- SUNXI_NAND_ECC_CTL_MODE(ecc_mode);
-
- if (CONFIG_NAND_SUNXI_ECC_STEP == 512)
- ecc |= SUNXI_NAND_ECC_CTL_BS_512B;
-
- if (syndrome)
- seed = 0x4A80;
- else
- seed = random_seed[page % ARRAY_SIZE(random_seed)];
-
- ecc |= SUNXI_NAND_ECC_CTL_RND_SEED(seed);
-
- writel(ecc, &nand->ecc_ctl);
-}
-
-/* read CONFIG_NAND_SUNXI_ECC_STEP bytes from real_addr to temp_buf */
-void
-nand_read_block(struct sunxi_nand *nand, phys_addr_t src, dma_addr_t dst,
- int syndrome)
-{
- struct sunxi_dma * const dma = (struct sunxi_dma *)SUNXI_DMA_BASE;
- struct sunxi_dma_cfg * const dma_cfg = &dma->ddma[0];
-
- uint32_t shift;
- uint32_t page;
- uint32_t addr;
- uint32_t oob_offset;
- uint32_t ecc_bytes;
- u32 val;
- u32 cmd;
-
- page = src / CONFIG_NAND_SUNXI_PAGE_SIZE;
- if (page > 0xFFFF) {
- /* TODO: currently this is not supported */
- printf("Reading from address >= %08X is not allowed.\n",
- 0xFFFF * CONFIG_NAND_SUNXI_PAGE_SIZE);
- return;
- }
-
- shift = src % CONFIG_NAND_SUNXI_PAGE_SIZE;
- writel(0, &nand->ecc_st);
-
- /* ECC_CTL, randomization */
- ecc_bytes = CONFIG_NAND_SUNXI_ECC_STRENGTH *
- fls(CONFIG_NAND_SUNXI_ECC_STEP * 8);
- ecc_bytes = DIV_ROUND_UP(ecc_bytes, 8);
- ecc_bytes += (ecc_bytes & 1); /* Align to 2-bytes */
- ecc_bytes += 4;
-
- nand_config_ecc(nand, page, syndrome);
- if (syndrome) {
- /* shift every 1kB in syndrome */
- shift += (shift / CONFIG_NAND_SUNXI_ECC_STEP) * ecc_bytes;
- oob_offset = CONFIG_NAND_SUNXI_ECC_STEP + shift;
- } else {
- oob_offset = CONFIG_NAND_SUNXI_PAGE_SIZE +
- (shift / CONFIG_NAND_SUNXI_ECC_STEP) * ecc_bytes;
- }
-
- addr = (page << 16) | shift;
-
- /* DMA */
- val = readl(&nand->ctl);
- writel(val | SUNXI_NAND_CTL_RAM_METHOD_DMA, &nand->ctl);
-
- writel(oob_offset, &nand->spare_area);
-
- /* DMAC
- * \todo Separate this into a tidy driver */
- writel(0x0, &dma->irq_en); /* clear dma interrupts */
- writel((uint32_t) &nand->io_data , &dma_cfg->src_addr);
- writel(dst , &dma_cfg->dst_addr);
- writel(0x00007F0F , &dma_cfg->ddma_para);
- writel(CONFIG_NAND_SUNXI_ECC_STEP, &dma_cfg->bc);
-
- val = SUNXI_DMA_CTL_SRC_DRQ(DDMA_SRC_DRQ_NAND) |
- SUNXI_DMA_CTL_MODE_IO |
- SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 |
- SUNXI_DMA_CTL_DST_DRQ(DDMA_DST_DRQ_SDRAM) |
- SUNXI_DMA_CTL_DST_DATA_WIDTH_32 |
- SUNXI_DMA_CTL_TRIGGER;
- writel(val, &dma_cfg->ctl);
-
- writel(0x00E00530, &nand->rcmd_set);
- nand_wait_timeout(&nand->st, SUNXI_NAND_ST_FIFO_FULL, 0);
-
- writel(1 , &nand->block_num);
- writel(addr, &nand->addr_low);
- writel(0 , &nand->addr_high);
-
- /* CMD (PAGE READ) */
- cmd = 0x85E80000;
- cmd |= SUNXI_NAND_CMD_ADDR_CYCLES(CONFIG_NAND_SUNXI_ADDR_CYCLES);
- cmd |= (syndrome ? SUNXI_NAND_CMD_ORDER_SEQ :
- SUNXI_NAND_CMD_ORDER_INTERLEAVE);
- writel(cmd, &nand->cmd);
-
- if(nand_wait_timeout(&nand->st, SUNXI_NAND_ST_DMA_INT,
- SUNXI_NAND_ST_DMA_INT)) {
- printf("NAND timeout reading data\n");
- return;
- }
-
- if(nand_wait_timeout(&dma_cfg->ctl, SUNXI_DMA_CTL_TRIGGER, 0)) {
- printf("NAND timeout reading data\n");
- return;
- }
-
- if (readl(&nand->ecc_st))
- ecc_errors++;
-}
-
-int
-nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
-{
- struct sunxi_nand * const nand = (struct sunxi_nand *)SUNXI_NFC_BASE;
- dma_addr_t dst_block;
- dma_addr_t dst_end;
- phys_addr_t addr = offs;
-
- dst_end = ((dma_addr_t) dest) + size;
-
- memset((void *)dest, 0x0, size);
- ecc_errors = 0;
- for (dst_block = (dma_addr_t) dest; dst_block < dst_end;
- dst_block += CONFIG_NAND_SUNXI_ECC_STEP,
- addr += CONFIG_NAND_SUNXI_ECC_STEP) {
- /* syndrome read first 4MiB to match Allwinner BootROM */
- nand_read_block(nand, addr, dst_block, addr < 0x400000);
- }
-
- if (ecc_errors)
- printf("Error: %d ECC failures detected\n", ecc_errors);
- return ecc_errors == 0;
-}
-
-void
-nand_deselect(void)
-{}
+menu "SPI Flash Support"
+
config DM_SPI_FLASH
bool "Enable Driver Model for SPI flash"
depends on DM && DM_SPI
bus (see CONFIG_SANDBOX_SPI) and SPI traffic will be routed to this
device. Typically the contents of the emulated SPI flash device is
stored in a file on the host filesystem.
+
+config SPI_FLASH
+ bool "Legacy SPI Flash Interface support"
+ help
+ Enable the legacy SPI flash support. This will include basic
+ standard support for things like probing, read / write, and
+ erasing through cmd_sf interface.
+
+ If unsure, say N
+
+config SPI_FLASH_BAR
+ bool "SPI flash Bank/Extended address register support"
+ depends on SPI_FLASH
+ help
+ Enable the SPI flash Bank/Extended address register support.
+ Bank/Extended address registers are used to access the flash
+ which has size > 16MiB in 3-byte addressing.
+
+config SPI_FLASH_DATAFLASH
+ bool "AT45xxx DataFlash support"
+ depends on SPI_FLASH && DM_SPI_FLASH
+ help
+ Enable the access for SPI-flash-based AT45xxx DataFlash chips.
+ DataFlash is a kind of SPI flash. Most AT45 chips have two buffers
+ in each chip, which may be used for double buffered I/O; but this
+ driver doesn't (yet) use these for any kind of i/o overlap or prefetching.
+
+ Sometimes DataFlash is packaged in MMC-format cards, although the
+ MMC stack can't (yet?) distinguish between MMC and DataFlash
+ protocols during enumeration.
+
+ If unsure, say N
+
+config SPI_FLASH_MTD
+ bool "SPI Flash MTD support"
+ depends on SPI_FLASH
+ help
+ Enable the MTD support for spi flash layer, this adapter is for
+ translating mtd_read/mtd_write commands into spi_flash_read/write
+ commands. It is not intended to use it within sf_cmd or the SPI
+ flash subsystem. Such an adapter is needed for subsystems like
+ UBI which can only operate on top of the MTD layer.
+
+ If unsure, say N
+
+endmenu # menu "SPI Flash Support"
#endif
obj-$(CONFIG_CMD_SF) += sf.o
obj-$(CONFIG_SPI_FLASH) += sf_ops.o sf_params.o
+obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o
+obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
obj-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
--- /dev/null
+/*
+ *
+ * Atmel DataFlash probing
+ *
+ * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
+ * Haikun Wang (haikun.wang@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <div64.h>
+#include <linux/err.h>
+#include <linux/math64.h>
+
+#include "sf_internal.h"
+
+/* reads can bypass the buffers */
+#define OP_READ_CONTINUOUS 0xE8
+#define OP_READ_PAGE 0xD2
+
+/* group B requests can run even while status reports "busy" */
+#define OP_READ_STATUS 0xD7 /* group B */
+
+/* move data between host and buffer */
+#define OP_READ_BUFFER1 0xD4 /* group B */
+#define OP_READ_BUFFER2 0xD6 /* group B */
+#define OP_WRITE_BUFFER1 0x84 /* group B */
+#define OP_WRITE_BUFFER2 0x87 /* group B */
+
+/* erasing flash */
+#define OP_ERASE_PAGE 0x81
+#define OP_ERASE_BLOCK 0x50
+
+/* move data between buffer and flash */
+#define OP_TRANSFER_BUF1 0x53
+#define OP_TRANSFER_BUF2 0x55
+#define OP_MREAD_BUFFER1 0xD4
+#define OP_MREAD_BUFFER2 0xD6
+#define OP_MWERASE_BUFFER1 0x83
+#define OP_MWERASE_BUFFER2 0x86
+#define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */
+#define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */
+
+/* write to buffer, then write-erase to flash */
+#define OP_PROGRAM_VIA_BUF1 0x82
+#define OP_PROGRAM_VIA_BUF2 0x85
+
+/* compare buffer to flash */
+#define OP_COMPARE_BUF1 0x60
+#define OP_COMPARE_BUF2 0x61
+
+/* read flash to buffer, then write-erase to flash */
+#define OP_REWRITE_VIA_BUF1 0x58
+#define OP_REWRITE_VIA_BUF2 0x59
+
+/*
+ * newer chips report JEDEC manufacturer and device IDs; chip
+ * serial number and OTP bits; and per-sector writeprotect.
+ */
+#define OP_READ_ID 0x9F
+#define OP_READ_SECURITY 0x77
+#define OP_WRITE_SECURITY_REVC 0x9A
+#define OP_WRITE_SECURITY 0x9B /* revision D */
+
+
+struct dataflash {
+ uint8_t command[16];
+ unsigned short page_offset; /* offset in flash address */
+};
+
+/*
+ * Return the status of the DataFlash device.
+ */
+static inline int dataflash_status(struct spi_slave *spi)
+{
+ int ret;
+ u8 status;
+ /*
+ * NOTE: at45db321c over 25 MHz wants to write
+ * a dummy byte after the opcode...
+ */
+ ret = spi_flash_cmd(spi, OP_READ_STATUS, &status, 1);
+ return ret ? -EIO : status;
+}
+
+/*
+ * Poll the DataFlash device until it is READY.
+ * This usually takes 5-20 msec or so; more for sector erase.
+ * ready: return > 0
+ */
+static int dataflash_waitready(struct spi_slave *spi)
+{
+ int status;
+ int timeout = 2 * CONFIG_SYS_HZ;
+ int timebase;
+
+ timebase = get_timer(0);
+ do {
+ status = dataflash_status(spi);
+ if (status < 0)
+ status = 0;
+
+ if (status & (1 << 7)) /* RDY/nBSY */
+ return status;
+
+ mdelay(3);
+ } while (get_timer(timebase) < timeout);
+
+ return -ETIME;
+}
+
+/*
+ * Erase pages of flash.
+ */
+static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len)
+{
+ struct dataflash *dataflash;
+ struct spi_flash *spi_flash;
+ struct spi_slave *spi;
+ unsigned blocksize;
+ uint8_t *command;
+ uint32_t rem;
+ int status;
+
+ dataflash = dev_get_priv(dev);
+ spi_flash = dev_get_uclass_priv(dev);
+ spi = spi_flash->spi;
+
+ blocksize = spi_flash->page_size << 3;
+
+ memset(dataflash->command, 0 , sizeof(dataflash->command));
+ command = dataflash->command;
+
+ debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
+
+ div_u64_rem(len, spi_flash->page_size, &rem);
+ if (rem)
+ return -EINVAL;
+ div_u64_rem(offset, spi_flash->page_size, &rem);
+ if (rem)
+ return -EINVAL;
+
+ status = spi_claim_bus(spi);
+ if (status) {
+ debug("SPI DATAFLASH: unable to claim SPI bus\n");
+ return status;
+ }
+
+ while (len > 0) {
+ unsigned int pageaddr;
+ int do_block;
+ /*
+ * Calculate flash page address; use block erase (for speed) if
+ * we're at a block boundary and need to erase the whole block.
+ */
+ pageaddr = div_u64(offset, spi_flash->page_size);
+ do_block = (pageaddr & 0x7) == 0 && len >= blocksize;
+ pageaddr = pageaddr << dataflash->page_offset;
+
+ command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE;
+ command[1] = (uint8_t)(pageaddr >> 16);
+ command[2] = (uint8_t)(pageaddr >> 8);
+ command[3] = 0;
+
+ debug("%s ERASE %s: (%x) %x %x %x [%d]\n",
+ dev->name, do_block ? "block" : "page",
+ command[0], command[1], command[2], command[3],
+ pageaddr);
+
+ status = spi_flash_cmd_write(spi, command, 4, NULL, 0);
+ if (status < 0) {
+ debug("%s: erase send command error!\n", dev->name);
+ return -EIO;
+ }
+
+ status = dataflash_waitready(spi);
+ if (status < 0) {
+ debug("%s: erase waitready error!\n", dev->name);
+ return status;
+ }
+
+ if (do_block) {
+ offset += blocksize;
+ len -= blocksize;
+ } else {
+ offset += spi_flash->page_size;
+ len -= spi_flash->page_size;
+ }
+ }
+
+ spi_release_bus(spi);
+
+ return 0;
+}
+
+/*
+ * Read from the DataFlash device.
+ * offset : Start offset in flash device
+ * len : Amount to read
+ * buf : Buffer containing the data
+ */
+static int spi_dataflash_read(struct udevice *dev, u32 offset, size_t len,
+ void *buf)
+{
+ struct dataflash *dataflash;
+ struct spi_flash *spi_flash;
+ struct spi_slave *spi;
+ unsigned int addr;
+ uint8_t *command;
+ int status;
+
+ dataflash = dev_get_priv(dev);
+ spi_flash = dev_get_uclass_priv(dev);
+ spi = spi_flash->spi;
+
+ memset(dataflash->command, 0 , sizeof(dataflash->command));
+ command = dataflash->command;
+
+ debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
+ debug("READ: (%x) %x %x %x\n",
+ command[0], command[1], command[2], command[3]);
+
+ /* Calculate flash page/byte address */
+ addr = (((unsigned)offset / spi_flash->page_size)
+ << dataflash->page_offset)
+ + ((unsigned)offset % spi_flash->page_size);
+
+ status = spi_claim_bus(spi);
+ if (status) {
+ debug("SPI DATAFLASH: unable to claim SPI bus\n");
+ return status;
+ }
+
+ /*
+ * Continuous read, max clock = f(car) which may be less than
+ * the peak rate available. Some chips support commands with
+ * fewer "don't care" bytes. Both buffers stay unchanged.
+ */
+ command[0] = OP_READ_CONTINUOUS;
+ command[1] = (uint8_t)(addr >> 16);
+ command[2] = (uint8_t)(addr >> 8);
+ command[3] = (uint8_t)(addr >> 0);
+
+ /* plus 4 "don't care" bytes, command len: 4 + 4 "don't care" bytes */
+ status = spi_flash_cmd_read(spi, command, 8, buf, len);
+
+ spi_release_bus(spi);
+
+ return status;
+}
+
+/*
+ * Write to the DataFlash device.
+ * offset : Start offset in flash device
+ * len : Amount to write
+ * buf : Buffer containing the data
+ */
+int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len,
+ const void *buf)
+{
+ struct dataflash *dataflash;
+ struct spi_flash *spi_flash;
+ struct spi_slave *spi;
+ uint8_t *command;
+ unsigned int pageaddr, addr, to, writelen;
+ size_t remaining = len;
+ u_char *writebuf = (u_char *)buf;
+ int status = -EINVAL;
+
+ dataflash = dev_get_priv(dev);
+ spi_flash = dev_get_uclass_priv(dev);
+ spi = spi_flash->spi;
+
+ memset(dataflash->command, 0 , sizeof(dataflash->command));
+ command = dataflash->command;
+
+ debug("%s: write 0x%x..0x%x\n", dev->name, offset, (offset + len));
+
+ pageaddr = ((unsigned)offset / spi_flash->page_size);
+ to = ((unsigned)offset % spi_flash->page_size);
+ if (to + len > spi_flash->page_size)
+ writelen = spi_flash->page_size - to;
+ else
+ writelen = len;
+
+ status = spi_claim_bus(spi);
+ if (status) {
+ debug("SPI DATAFLASH: unable to claim SPI bus\n");
+ return status;
+ }
+
+ while (remaining > 0) {
+ debug("write @ %d:%d len=%d\n", pageaddr, to, writelen);
+
+ /*
+ * REVISIT:
+ * (a) each page in a sector must be rewritten at least
+ * once every 10K sibling erase/program operations.
+ * (b) for pages that are already erased, we could
+ * use WRITE+MWRITE not PROGRAM for ~30% speedup.
+ * (c) WRITE to buffer could be done while waiting for
+ * a previous MWRITE/MWERASE to complete ...
+ * (d) error handling here seems to be mostly missing.
+ *
+ * Two persistent bits per page, plus a per-sector counter,
+ * could support (a) and (b) ... we might consider using
+ * the second half of sector zero, which is just one block,
+ * to track that state. (On AT91, that sector should also
+ * support boot-from-DataFlash.)
+ */
+
+ addr = pageaddr << dataflash->page_offset;
+
+ /* (1) Maybe transfer partial page to Buffer1 */
+ if (writelen != spi_flash->page_size) {
+ command[0] = OP_TRANSFER_BUF1;
+ command[1] = (addr & 0x00FF0000) >> 16;
+ command[2] = (addr & 0x0000FF00) >> 8;
+ command[3] = 0;
+
+ debug("TRANSFER: (%x) %x %x %x\n",
+ command[0], command[1], command[2], command[3]);
+
+ status = spi_flash_cmd_write(spi, command, 4, NULL, 0);
+ if (status < 0) {
+ debug("%s: write(<pagesize) command error!\n",
+ dev->name);
+ return -EIO;
+ }
+
+ status = dataflash_waitready(spi);
+ if (status < 0) {
+ debug("%s: write(<pagesize) waitready error!\n",
+ dev->name);
+ return status;
+ }
+ }
+
+ /* (2) Program full page via Buffer1 */
+ addr += to;
+ command[0] = OP_PROGRAM_VIA_BUF1;
+ command[1] = (addr & 0x00FF0000) >> 16;
+ command[2] = (addr & 0x0000FF00) >> 8;
+ command[3] = (addr & 0x000000FF);
+
+ debug("PROGRAM: (%x) %x %x %x\n",
+ command[0], command[1], command[2], command[3]);
+
+ status = spi_flash_cmd_write(spi, command,
+ 4, writebuf, writelen);
+ if (status < 0) {
+ debug("%s: write send command error!\n", dev->name);
+ return -EIO;
+ }
+
+ status = dataflash_waitready(spi);
+ if (status < 0) {
+ debug("%s: write waitready error!\n", dev->name);
+ return status;
+ }
+
+#ifdef CONFIG_SPI_DATAFLASH_WRITE_VERIFY
+ /* (3) Compare to Buffer1 */
+ addr = pageaddr << dataflash->page_offset;
+ command[0] = OP_COMPARE_BUF1;
+ command[1] = (addr & 0x00FF0000) >> 16;
+ command[2] = (addr & 0x0000FF00) >> 8;
+ command[3] = 0;
+
+ debug("COMPARE: (%x) %x %x %x\n",
+ command[0], command[1], command[2], command[3]);
+
+ status = spi_flash_cmd_write(spi, command,
+ 4, writebuf, writelen);
+ if (status < 0) {
+ debug("%s: write(compare) send command error!\n",
+ dev->name);
+ return -EIO;
+ }
+
+ status = dataflash_waitready(spi);
+
+ /* Check result of the compare operation */
+ if (status & (1 << 6)) {
+ printf("SPI DataFlash: write compare page %u, err %d\n",
+ pageaddr, status);
+ remaining = 0;
+ status = -EIO;
+ break;
+ } else {
+ status = 0;
+ }
+
+#endif /* CONFIG_SPI_DATAFLASH_WRITE_VERIFY */
+ remaining = remaining - writelen;
+ pageaddr++;
+ to = 0;
+ writebuf += writelen;
+
+ if (remaining > spi_flash->page_size)
+ writelen = spi_flash->page_size;
+ else
+ writelen = remaining;
+ }
+
+ spi_release_bus(spi);
+
+ return 0;
+}
+
+static int add_dataflash(struct udevice *dev, char *name, int nr_pages,
+ int pagesize, int pageoffset, char revision)
+{
+ struct spi_flash *spi_flash;
+ struct dataflash *dataflash;
+
+ dataflash = dev_get_priv(dev);
+ spi_flash = dev_get_uclass_priv(dev);
+
+ dataflash->page_offset = pageoffset;
+
+ spi_flash->name = name;
+ spi_flash->page_size = pagesize;
+ spi_flash->size = nr_pages * pagesize;
+ spi_flash->erase_size = pagesize;
+
+#ifndef CONFIG_SPL_BUILD
+ printf("SPI DataFlash: Detected %s with page size ", spi_flash->name);
+ print_size(spi_flash->page_size, ", erase size ");
+ print_size(spi_flash->erase_size, ", total ");
+ print_size(spi_flash->size, "");
+ printf(", revision %c", revision);
+ puts("\n");
+#endif
+
+ return 0;
+}
+
+struct flash_info {
+ char *name;
+
+ /*
+ * JEDEC id has a high byte of zero plus three data bytes:
+ * the manufacturer id, then a two byte device id.
+ */
+ uint32_t jedec_id;
+
+ /* The size listed here is what works with OP_ERASE_PAGE. */
+ unsigned nr_pages;
+ uint16_t pagesize;
+ uint16_t pageoffset;
+
+ uint16_t flags;
+#define SUP_POW2PS 0x0002 /* supports 2^N byte pages */
+#define IS_POW2PS 0x0001 /* uses 2^N byte pages */
+};
+
+static struct flash_info dataflash_data[] = {
+ /*
+ * NOTE: chips with SUP_POW2PS (rev D and up) need two entries,
+ * one with IS_POW2PS and the other without. The entry with the
+ * non-2^N byte page size can't name exact chip revisions without
+ * losing backwards compatibility for cmdlinepart.
+ *
+ * Those two entries have different name spelling format in order to
+ * show their difference obviously.
+ * The upper case refer to the chip isn't in normal 2^N bytes page-size
+ * mode.
+ * The lower case refer to the chip is in normal 2^N bytes page-size
+ * mode.
+ *
+ * These newer chips also support 128-byte security registers (with
+ * 64 bytes one-time-programmable) and software write-protection.
+ */
+ { "AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS},
+ { "at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS},
+
+ { "AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS},
+ { "at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS},
+
+ { "AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS},
+ { "at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS},
+
+ { "AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS},
+ { "at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS},
+
+ { "AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS},
+ { "at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS},
+
+ { "AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */
+
+ { "AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS},
+ { "at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS},
+
+ { "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS},
+ { "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
+};
+
+static struct flash_info *jedec_probe(struct spi_slave *spi, u8 *id)
+{
+ int tmp;
+ uint32_t jedec;
+ struct flash_info *info;
+ int status;
+
+ /*
+ * JEDEC also defines an optional "extended device information"
+ * string for after vendor-specific data, after the three bytes
+ * we use here. Supporting some chips might require using it.
+ *
+ * If the vendor ID isn't Atmel's (0x1f), assume this call failed.
+ * That's not an error; only rev C and newer chips handle it, and
+ * only Atmel sells these chips.
+ */
+ if (id[0] != 0x1f)
+ return NULL;
+
+ jedec = id[0];
+ jedec = jedec << 8;
+ jedec |= id[1];
+ jedec = jedec << 8;
+ jedec |= id[2];
+
+ for (tmp = 0, info = dataflash_data;
+ tmp < ARRAY_SIZE(dataflash_data);
+ tmp++, info++) {
+ if (info->jedec_id == jedec) {
+ if (info->flags & SUP_POW2PS) {
+ status = dataflash_status(spi);
+ if (status < 0) {
+ debug("SPI DataFlash: status error %d\n",
+ status);
+ return NULL;
+ }
+ if (status & 0x1) {
+ if (info->flags & IS_POW2PS)
+ return info;
+ } else {
+ if (!(info->flags & IS_POW2PS))
+ return info;
+ }
+ } else {
+ return info;
+ }
+ }
+ }
+
+ /*
+ * Treat other chips as errors ... we won't know the right page
+ * size (it might be binary) even when we can tell which density
+ * class is involved (legacy chip id scheme).
+ */
+ printf("SPI DataFlash: Unsupported flash IDs: ");
+ printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
+ id[0], jedec, id[3] << 8 | id[4]);
+ return NULL;
+}
+
+/*
+ * Detect and initialize DataFlash device, using JEDEC IDs on newer chips
+ * or else the ID code embedded in the status bits:
+ *
+ * Device Density ID code #Pages PageSize Offset
+ * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9
+ * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9
+ * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9
+ * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9
+ * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10
+ * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10
+ * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11
+ * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11
+ */
+static int spi_dataflash_probe(struct udevice *dev)
+{
+ struct spi_slave *spi = dev_get_parentdata(dev);
+ struct spi_flash *spi_flash;
+ struct flash_info *info;
+ u8 idcode[5];
+ int ret, status = 0;
+
+ spi_flash = dev_get_uclass_priv(dev);
+ spi_flash->dev = dev;
+
+ ret = spi_claim_bus(spi);
+ if (ret)
+ return ret;
+
+ ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
+ if (ret) {
+ printf("SPI DataFlash: Failed to get idcodes\n");
+ goto err_read_cmd;
+ }
+
+ /*
+ * Try to detect dataflash by JEDEC ID.
+ * If it succeeds we know we have either a C or D part.
+ * D will support power of 2 pagesize option.
+ * Both support the security register, though with different
+ * write procedures.
+ */
+ info = jedec_probe(spi, idcode);
+ if (info != NULL)
+ add_dataflash(dev, info->name, info->nr_pages,
+ info->pagesize, info->pageoffset,
+ (info->flags & SUP_POW2PS) ? 'd' : 'c');
+ else {
+ /*
+ * Older chips support only legacy commands, identifing
+ * capacity using bits in the status byte.
+ */
+ status = dataflash_status(spi);
+ if (status <= 0 || status == 0xff) {
+ printf("SPI DataFlash: read status error %d\n", status);
+ if (status == 0 || status == 0xff)
+ status = -ENODEV;
+ goto err_read_cmd;
+ }
+ /*
+ * if there's a device there, assume it's dataflash.
+ * board setup should have set spi->max_speed_max to
+ * match f(car) for continuous reads, mode 0 or 3.
+ */
+ switch (status & 0x3c) {
+ case 0x0c: /* 0 0 1 1 x x */
+ status = add_dataflash(dev, "AT45DB011B",
+ 512, 264, 9, 0);
+ break;
+ case 0x14: /* 0 1 0 1 x x */
+ status = add_dataflash(dev, "AT45DB021B",
+ 1024, 264, 9, 0);
+ break;
+ case 0x1c: /* 0 1 1 1 x x */
+ status = add_dataflash(dev, "AT45DB041x",
+ 2048, 264, 9, 0);
+ break;
+ case 0x24: /* 1 0 0 1 x x */
+ status = add_dataflash(dev, "AT45DB081B",
+ 4096, 264, 9, 0);
+ break;
+ case 0x2c: /* 1 0 1 1 x x */
+ status = add_dataflash(dev, "AT45DB161x",
+ 4096, 528, 10, 0);
+ break;
+ case 0x34: /* 1 1 0 1 x x */
+ status = add_dataflash(dev, "AT45DB321x",
+ 8192, 528, 10, 0);
+ break;
+ case 0x38: /* 1 1 1 x x x */
+ case 0x3c:
+ status = add_dataflash(dev, "AT45DB642x",
+ 8192, 1056, 11, 0);
+ break;
+ /* obsolete AT45DB1282 not (yet?) supported */
+ default:
+ dev_info(&spi->dev, "unsupported device (%x)\n",
+ status & 0x3c);
+ status = -ENODEV;
+ goto err_read_cmd;
+ }
+ }
+
+ /* Assign spi data */
+ spi_flash->spi = spi;
+ spi_flash->memory_map = spi->memory_map;
+ spi_flash->dual_flash = spi->option;
+
+ spi_release_bus(spi);
+
+ return 0;
+
+err_read_cmd:
+ spi_release_bus(spi);
+
+ return status;
+}
+
+static const struct dm_spi_flash_ops spi_dataflash_ops = {
+ .read = spi_dataflash_read,
+ .write = spi_dataflash_write,
+ .erase = spi_dataflash_erase,
+};
+
+static const struct udevice_id spi_dataflash_ids[] = {
+ { .compatible = "atmel,at45", },
+ { .compatible = "atmel,dataflash", },
+ { }
+};
+
+U_BOOT_DRIVER(spi_dataflash) = {
+ .name = "spi_dataflash",
+ .id = UCLASS_SPI_FLASH,
+ .of_match = spi_dataflash_ids,
+ .probe = spi_dataflash_probe,
+ .priv_auto_alloc_size = sizeof(struct dataflash),
+ .ops = &spi_dataflash_ops,
+};
};
/* Normal - Extended - Full command set */
-#define RD_NORM (ARRAY_SLOW | ARRAY_FAST)
-#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
-#define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
+#define RD_NORM (ARRAY_SLOW | ARRAY_FAST)
+#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
+#define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
/* sf param flags */
enum {
#define CMD_WRITE_STATUS 0x01
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
-#define CMD_READ_STATUS 0x05
+#define CMD_READ_STATUS 0x05
#define CMD_QUAD_PAGE_PROGRAM 0x32
#define CMD_READ_STATUS1 0x35
#define CMD_WRITE_ENABLE 0x06
-#define CMD_READ_CONFIG 0x35
-#define CMD_FLAG_STATUS 0x70
+#define CMD_READ_CONFIG 0x35
+#define CMD_FLAG_STATUS 0x70
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
-#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
+#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
/* SST specific */
#ifdef CONFIG_SPI_FLASH_SST
# define CMD_SST_BP 0x02 /* Byte Program */
-# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
+# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf);
* @ext_jedec: Device ext_jedec ID
* @sector_size: Isn't necessarily a sector size from vendor,
* the size listed here is what works with CMD_ERASE_64K
- * @nr_sectors: No.of sectors on this device
+ * @nr_sectors: No.of sectors on this device
* @e_rd_cmd: Enum list for read commands
* @flags: Important param, for flash specific behaviour
*/
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data);
+#ifdef CONFIG_SPI_FLASH_MTD
+int spi_flash_mtd_register(struct spi_flash *flash);
+void spi_flash_mtd_unregister(void);
+#endif
+
#endif /* _SF_INTERNAL_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2012-2014 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/errno.h>
+#include <linux/mtd/mtd.h>
+#include <spi_flash.h>
+
+static struct mtd_info sf_mtd_info;
+static char sf_mtd_name[8];
+
+static int spi_flash_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+ struct spi_flash *flash = mtd->priv;
+ int err;
+
+ instr->state = MTD_ERASING;
+
+ err = spi_flash_erase(flash, instr->addr, instr->len);
+ if (err) {
+ instr->state = MTD_ERASE_FAILED;
+ instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+ return -EIO;
+ }
+
+ instr->state = MTD_ERASE_DONE;
+ mtd_erase_callback(instr);
+
+ return 0;
+}
+
+static int spi_flash_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct spi_flash *flash = mtd->priv;
+ int err;
+
+ err = spi_flash_read(flash, from, len, buf);
+ if (!err)
+ *retlen = len;
+
+ return err;
+}
+
+static int spi_flash_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf)
+{
+ struct spi_flash *flash = mtd->priv;
+ int err;
+
+ err = spi_flash_write(flash, to, len, buf);
+ if (!err)
+ *retlen = len;
+
+ return err;
+}
+
+static void spi_flash_mtd_sync(struct mtd_info *mtd)
+{
+}
+
+static int spi_flash_mtd_number(void)
+{
+#ifdef CONFIG_SYS_MAX_FLASH_BANKS
+ return CONFIG_SYS_MAX_FLASH_BANKS;
+#else
+ return 0;
+#endif
+}
+
+int spi_flash_mtd_register(struct spi_flash *flash)
+{
+ memset(&sf_mtd_info, 0, sizeof(sf_mtd_info));
+ sprintf(sf_mtd_name, "nor%d", spi_flash_mtd_number());
+
+ sf_mtd_info.name = sf_mtd_name;
+ sf_mtd_info.type = MTD_NORFLASH;
+ sf_mtd_info.flags = MTD_CAP_NORFLASH;
+ sf_mtd_info.writesize = 1;
+ sf_mtd_info.writebufsize = flash->page_size;
+
+ sf_mtd_info._erase = spi_flash_mtd_erase;
+ sf_mtd_info._read = spi_flash_mtd_read;
+ sf_mtd_info._write = spi_flash_mtd_write;
+ sf_mtd_info._sync = spi_flash_mtd_sync;
+
+ sf_mtd_info.size = flash->size;
+ sf_mtd_info.priv = flash;
+
+ /* Only uniform flash devices for now */
+ sf_mtd_info.numeraseregions = 0;
+ sf_mtd_info.erasesize = flash->sector_size;
+
+ return add_mtd_device(&sf_mtd_info);
+}
+
+void spi_flash_mtd_unregister(void)
+{
+ del_mtd_device(&sf_mtd_info);
+}
{"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM, SECT_4K | SST_WR},
{"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K | SST_WR},
{"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR},
- {"SST25WF040B", 0x621613, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR},
+ {"SST25WF040B", 0x621613, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
{"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR},
#endif
#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
}
#endif
-
- /* Release spi bus */
- spi_release_bus(spi);
-
- return 0;
+#ifdef CONFIG_SPI_FLASH_MTD
+ ret = spi_flash_mtd_register(flash);
+#endif
err_read_id:
spi_release_bus(spi);
void spi_flash_free(struct spi_flash *flash)
{
+#ifdef CONFIG_SPI_FLASH_MTD
+ spi_flash_mtd_unregister();
+#endif
spi_free_slave(flash->spi);
free(flash);
}
menuconfig NETDEVICES
bool "Network device support"
depends on NET
+ default y if DM_ETH
help
You must select Y to enable any network device support
Generally if you have any networking support this is a given
+menu "SPI Support"
+
config DM_SPI
bool "Enable Driver Model for SPI drivers"
depends on DM
typically use driver-private data instead of extending the
spi_slave structure.
+if DM_SPI
+
+config CADENCE_QSPI
+ bool "Cadence QSPI driver"
+ help
+ Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
+ used to access the SPI NOR flash on platforms embedding this
+ Cadence IP core.
+
+config DESIGNWARE_SPI
+ bool "Designware SPI driver"
+ help
+ Enable the Designware SPI driver. This driver can be used to
+ access the SPI NOR flash on platforms embedding this Designware
+ IP core.
+
+config EXYNOS_SPI
+ bool "Samsung Exynos SPI driver"
+ help
+ Enable the Samsung Exynos SPI driver. This driver can be used to
+ access the SPI NOR flash on platforms embedding this Samsung
+ Exynos IP core.
+
+config FSL_DSPI
+ bool "Freescale DSPI driver"
+ help
+ Enable the Freescale DSPI driver. This driver can be used to
+ access the SPI NOR flash and SPI Data flash on platforms embedding
+ this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
+ use this driver.
+
+config FSL_QSPI
+ bool "Freescale QSPI driver"
+ help
+ Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
+ used to access the SPI NOR flash on platforms embedding this
+ Freescale IP core.
+
+config ICH_SPI
+ bool "Intel ICH SPI driver"
+ help
+ Enable the Intel ICH SPI driver. This driver can be used to
+ access the SPI NOR flash on platforms embedding this Intel
+ ICH IP core.
+
config SANDBOX_SPI
bool "Sandbox SPI driver"
depends on SANDBOX && DM
spi-max-frequency = <40000000>;
sandbox,filename = "spi.bin";
};
- };
+ };
-config DESIGNWARE_SPI
- bool "Designware SPI driver"
- depends on DM_SPI
+config TEGRA114_SPI
+ bool "nVidia Tegra114 SPI driver"
help
- Enable the Designware SPI driver. This driver can be used to
- access the SPI NOR flash on platforms embedding this Designware
+ Enable the nVidia Tegra114 SPI driver. This driver can be used to
+ access the SPI NOR flash on platforms embedding this nVidia Tegra114
IP core.
-config CADENCE_QSPI
- bool "Cadence QSPI driver"
- depends on DM_SPI
+ This controller is different than the older SoCs SPI controller and
+ also register interface get changed with this controller.
+
+config TEGRA20_SFLASH
+ bool "nVidia Tegra20 Serial Flash controller driver"
help
- Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
- used to access the SPI NOR flash on platforms embedding this
- Cadence IP core.
+ Enable the nVidia Tegra20 Serial Flash controller driver. This driver
+ can be used to access the SPI NOR flash on platforms embedding this
+ nVidia Tegra20 IP core.
+
+config TEGRA20_SLINK
+ bool "nVidia Tegra20/Tegra30 SLINK driver"
+ help
+ Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can
+ be used to access the SPI NOR flash on platforms embedding this
+ nVidia Tegra20/Tegra30 IP cores.
+
+config XILINX_SPI
+ bool "Xilinx SPI driver"
+ help
+ Enable the Xilinx SPI driver from the Xilinx EDK. This SPI
+ controller support 8 bit SPI transfers only, with or w/o FIFO.
+ For more info on Xilinx SPI Register Definitions and Overview
+ see driver file - drivers/spi/xilinx_spi.c
+
+config ZYNQ_SPI
+ bool "Zynq SPI driver"
+ depends on ARCH_ZYNQ || TARGET_XILINX_ZYNQMP
+ help
+ Enable the Zynq SPI driver. This driver can be used to
+ access the SPI NOR flash on platforms embedding this Zynq
+ SPI IP core.
+
+endif # if DM_SPI
+
+config FSL_ESPI
+ bool "Freescale eSPI driver"
+ help
+ Enable the Freescale eSPI driver. This driver can be used to
+ access the SPI interface and SPI NOR flash on platforms embedding
+ this Freescale eSPI IP core.
+
+config TI_QSPI
+ bool "TI QSPI driver"
+ help
+ Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
+ This driver support spi flash single, quad and memory reads.
+
+endmenu # menu "SPI Support"
obj-$(CONFIG_SOFT_SPI) += soft_spi_legacy.o
endif
-obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
-obj-$(CONFIG_ANDES_SPI) += andes_spi.o
obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
obj-$(CONFIG_CF_QSPI) += cf_qspi.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
+obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o
obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
-obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
+obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
+obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
+obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
obj-$(CONFIG_MXS_SPI) += mxs_spi.o
-obj-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
obj-$(CONFIG_SH_SPI) += sh_spi.o
obj-$(CONFIG_SH_QSPI) += sh_qspi.o
-obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
+obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
-obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
obj-$(CONFIG_TI_QSPI) += ti_qspi.o
obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
-obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
-obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
+++ /dev/null
-/*
- * Driver of Andes SPI Controller
- *
- * (C) Copyright 2011 Andes Technology
- * Macpaul Lin <macpaul@andestech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <spi.h>
-
-#include <asm/io.h>
-#include "andes_spi.h"
-
-void spi_init(void)
-{
- /* do nothing */
-}
-
-static void andes_spi_spit_en(struct andes_spi_slave *ds)
-{
- unsigned int dcr = readl(&ds->regs->dcr);
-
- debug("%s: dcr: %x, write value: %x\n",
- __func__, dcr, (dcr | ANDES_SPI_DCR_SPIT));
-
- writel((dcr | ANDES_SPI_DCR_SPIT), &ds->regs->dcr);
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct andes_spi_slave *ds;
-
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
-
- ds = spi_alloc_slave(struct andes_spi_slave, bus, cs);
- if (!ds)
- return NULL;
-
- ds->regs = (struct andes_spi_regs *)CONFIG_SYS_SPI_BASE;
-
- /*
- * The hardware of andes_spi will set its frequency according
- * to APB/AHB bus clock. Hence the hardware doesn't allow changing of
- * requency and so the user requested speed is always ignored.
- */
- ds->freq = max_hz;
-
- return &ds->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct andes_spi_slave *ds = to_andes_spi(slave);
-
- free(ds);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct andes_spi_slave *ds = to_andes_spi(slave);
- unsigned int apb;
- unsigned int baud;
-
- /* Enable the SPI hardware */
- writel(ANDES_SPI_CR_SPIRST, &ds->regs->cr);
- udelay(1000);
-
- /* setup format */
- baud = ((CONFIG_SYS_CLK_FREQ / CONFIG_SYS_SPI_CLK / 2) - 1) & 0xFF;
-
- /*
- * SPI_CLK = AHB bus clock / ((BAUD + 1)*2)
- * BAUD = AHB bus clock / SPI_CLK / 2) - 1
- */
- apb = (readl(&ds->regs->apb) & 0xffffff00) | baud;
- writel(apb, &ds->regs->apb);
-
- /* no interrupts */
- writel(0, &ds->regs->ie);
-
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- struct andes_spi_slave *ds = to_andes_spi(slave);
-
- /* Disable the SPI hardware */
- writel(ANDES_SPI_CR_SPIRST, &ds->regs->cr);
-}
-
-static int andes_spi_read(struct spi_slave *slave, unsigned int len,
- u8 *rxp, unsigned long flags)
-{
- struct andes_spi_slave *ds = to_andes_spi(slave);
- unsigned int i, left;
- unsigned int data;
-
- debug("%s: slave: %x, len: %d, rxp: %x, flags: %d\n",
- __func__, slave, len, rxp, flags);
-
- debug("%s: data: ", __func__);
- while (len > 0) {
- left = min(len, 4);
- data = readl(&ds->regs->data);
-
- debug(" ");
- for (i = 0; i < left; i++) {
- debug("%02x ", data & 0xff);
- *rxp++ = data;
- data >>= 8;
- len--;
- }
- }
- debug("\n");
-
- return 0;
-}
-
-static int andes_spi_write(struct spi_slave *slave, unsigned int wlen,
- unsigned int rlen, const u8 *txp, unsigned long flags)
-{
- struct andes_spi_slave *ds = to_andes_spi(slave);
- unsigned int data;
- unsigned int i, left;
- unsigned int spit_enabled = 0;
-
- debug("%s: slave: %x, wlen: %d, rlen: %d, txp: %x, flags: %x\n",
- __func__, slave, wlen, rlen, txp, flags);
-
- /* The value of wlen and rlen wrote to register must minus 1 */
- if (rlen == 0) /* write only */
- writel(ANDES_SPI_DCR_MODE_WO | ANDES_SPI_DCR_WCNT(wlen-1) |
- ANDES_SPI_DCR_RCNT(0), &ds->regs->dcr);
- else /* write then read */
- writel(ANDES_SPI_DCR_MODE_WR | ANDES_SPI_DCR_WCNT(wlen-1) |
- ANDES_SPI_DCR_RCNT(rlen-1), &ds->regs->dcr);
-
- /* wait till SPIBSY is cleared */
- while (readl(&ds->regs->st) & ANDES_SPI_ST_SPIBSY)
- ;
-
- /* data write process */
- debug("%s: txp: ", __func__);
- while (wlen > 0) {
- /* clear the data */
- data = 0;
-
- /* data are usually be read 32bits once a time */
- left = min(wlen, 4);
-
- for (i = 0; i < left; i++) {
- debug("%x ", *txp);
- data |= *txp++ << (i * 8);
- wlen--;
- }
- debug("\n");
-
- debug("data: %08x\n", data);
- debug("streg before write: %08x\n", readl(&ds->regs->st));
- /* wait till TXFULL is deasserted */
- while (readl(&ds->regs->st) & ANDES_SPI_ST_TXFEL)
- ;
- writel(data, &ds->regs->data);
- debug("streg after write: %08x\n", readl(&ds->regs->st));
-
-
- if (spit_enabled == 0) {
- /* enable SPIT bit - trigger the tx and rx progress */
- andes_spi_spit_en(ds);
- spit_enabled = 1;
- }
-
- }
- debug("\n");
-
- return 0;
-}
-
-/*
- * spi_xfer:
- * Since andes_spi doesn't support independent command transaction,
- * that is, write and than read must be operated in continuous
- * execution, there is no need to set dcr and trigger spit again in
- * RX process.
- */
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
-{
- unsigned int len;
- static int op_nextime;
- static u8 tmp_cmd[5];
- static int tmp_wlen;
- unsigned int i;
-
- if (bitlen == 0)
- /* Finish any previously submitted transfers */
- goto out;
-
- if (bitlen % 8) {
- /* Errors always terminate an ongoing transfer */
- flags |= SPI_XFER_END;
- goto out;
- }
-
- len = bitlen / 8;
-
- debug("%s: slave: %08x, bitlen: %d, dout: "
- "%08x, din: %08x, flags: %d, len: %d\n",
- __func__, slave, bitlen, dout, din, flags, len);
-
- /*
- * Important:
- * andes_spi's hardware doesn't support 2 data channel. The read
- * and write cmd/data share the same register (data register).
- *
- * If a command has write and read transaction, you cannot do write
- * this time and then do read on next time.
- *
- * A command writes first with a read response must indicating
- * the read length in write operation. Hence the write action must
- * be stored temporary and wait until the next read action has been
- * arrived. Then we flush the write and read action out together.
- */
- if (!dout) {
- if (op_nextime == 1) {
- /* flags should be SPI_XFER_END, value is 2 */
- op_nextime = 0;
- andes_spi_write(slave, tmp_wlen, len, tmp_cmd, flags);
- }
- return andes_spi_read(slave, len, din, flags);
- } else if (!din) {
- if (flags == SPI_XFER_BEGIN) {
- /* store the write command and do operation next time */
- op_nextime = 1;
- memset(tmp_cmd, 0, sizeof(tmp_cmd));
- memcpy(tmp_cmd, dout, len);
-
- debug("%s: tmp_cmd: ", __func__);
- for (i = 0; i < len; i++)
- debug("%x ", *(tmp_cmd + i));
- debug("\n");
-
- tmp_wlen = len;
- } else {
- /*
- * flags should be (SPI_XFER_BEGIN | SPI_XFER_END),
- * the value is 3.
- */
- if (op_nextime == 1) {
- /* flags should be SPI_XFER_END, value is 2 */
- op_nextime = 0;
- /* flags 3 implies write only */
- andes_spi_write(slave, tmp_wlen, 0, tmp_cmd, 3);
- }
-
- debug("flags: %x\n", flags);
- return andes_spi_write(slave, len, 0, dout, flags);
- }
- }
-
-out:
- return 0;
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- /* do nothing */
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- /* do nothing */
-}
+++ /dev/null
-/*
- * Register definitions for the Andes SPI Controller
- *
- * (C) Copyright 2011 Andes Technology
- * Macpaul Lin <macpaul@andestech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ANDES_SPI_H
-#define __ANDES_SPI_H
-
-struct andes_spi_regs {
- unsigned int apb; /* 0x00 - APB SPI interface setting */
- unsigned int pio; /* 0x04 - PIO reg */
- unsigned int cr; /* 0x08 - SPI Control reg */
- unsigned int st; /* 0x0c - SPI Status reg */
- unsigned int ie; /* 0x10 - Interrupt Enable reg */
- unsigned int ist; /* 0x14 - Interrupt Status reg */
- unsigned int dcr; /* 0x18 - data control reg */
- unsigned int data; /* 0x1c - data register */
- unsigned int ahb; /* 0x20 - AHB SPI interface setting */
- unsigned int ver; /* 0x3c - SPI version reg */
-};
-
-#define BIT(x) (1 << (x))
-
-/* 0x00 - APB SPI interface setting register */
-#define ANDES_SPI_APB_BAUD(x) (((x) & 0xff) < 0)
-#define ANDES_SPI_APB_CSHT(x) (((x) & 0xf) < 16)
-#define ANDES_SPI_APB_SPNTS BIT(20) /* 0: normal, 1: delay */
-#define ANDES_SPI_APB_CPHA BIT(24) /* 0: Sampling at odd edges */
-#define ANDES_SPI_APB_CPOL BIT(25) /* 0: SCK low, 1: SCK high */
-#define ANDES_SPI_APB_MSSL BIT(26) /* 0: SPI Master, 1: slave */
-
-/* 0x04 - PIO register */
-#define ANDES_SPI_PIO_MISO BIT(0) /* input value of pin MISO */
-#define ANDES_SPI_PIO_MOSI BIT(1) /* I/O value of pin MOSI */
-#define ANDES_SPI_PIO_SCK BIT(2) /* I/O value of pin SCK */
-#define ANDES_SPI_PIO_CS BIT(3) /* I/O value of pin CS */
-#define ANDES_SPI_PIO_PIOE BIT(4) /* Programming IO Enable */
-
-/* 0x08 - SPI Control register */
-#define ANDES_SPI_CR_SPIRST BIT(0) /* SPI mode reset */
-#define ANDES_SPI_CR_RXFRST BIT(1) /* RxFIFO reset */
-#define ANDES_SPI_CR_TXFRST BIT(2) /* TxFIFO reset */
-#define ANDES_SPI_CR_RXFTH(x) (((x) & 0x1f) << 10) /* RxFIFO Threshold */
-#define ANDES_SPI_CR_TXFTH(x) (((x) & 0x1f) << 18) /* TxFIFO Threshold */
-
-/* 0x0c - SPI Status register */
-#define ANDES_SPI_ST_SPIBSY BIT(0) /* SPI Transfer is active */
-#define ANDES_SPI_ST_RXFEM BIT(8) /* RxFIFO Empty Flag */
-#define ANDES_SPI_ST_RXFEL BIT(9) /* RxFIFO Full Flag */
-#define ANDES_SPI_ST_RXFVE(x) (((x) >> 10) & 0x1f)
-#define ANDES_SPI_ST_TXFEM BIT(16) /* TxFIFO Empty Flag */
-#define ANDES_SPI_ST_TXFEL BIT(7) /* TxFIFO Full Flag */
-#define ANDES_SPI_ST_TXFVE(x) (((x) >> 18) & 0x1f)
-
-/* 0x10 - Interrupt Enable register */
-#define ANDES_SPI_IE_RXFORIE BIT(0) /* RxFIFO overrun intr */
-#define ANDES_SPI_IE_TXFURIE BIT(1) /* TxFOFO underrun intr */
-#define ANDES_SPI_IE_RXFTHIE BIT(2) /* RxFIFO threshold intr */
-#define ANDES_SPI_IE_TXFTHIE BIT(3) /* TxFIFO threshold intr */
-#define ANDES_SPI_IE_SPIEIE BIT(4) /* SPI transmit END intr */
-#define ANDES_SPI_IE_SPCFIE BIT(5) /* AHB/APB TxReq conflict */
-
-/* 0x14 - Interrupt Status Register */
-#define ANDES_SPI_IST_RXFORI BIT(0) /* has RxFIFO overrun */
-#define ANDES_SPI_IST_TXFURI BIT(1) /* has TxFOFO underrun */
-#define ANDES_SPI_IST_RXFTHI BIT(2) /* has RxFIFO threshold */
-#define ANDES_SPI_IST_TXFTHI BIT(3) /* has TxFIFO threshold */
-#define ANDES_SPI_IST_SPIEI BIT(4) /* has SPI transmit END */
-#define ANDES_SPI_IST_SPCFI BIT(5) /* has AHB/APB TxReq conflict */
-
-/* 0x18 - Data Control Register */
-#define ANDES_SPI_DCR_RCNT(x) (((x) & 0x3ff) << 0)
-#define ANDES_SPI_DCR_DYCNT(x) (((x) & 0x7) << 12)
-#define ANDES_SPI_DCR_WCNT(x) (((x) & 0x3ff) << 16)
-#define ANDES_SPI_DCR_TRAMODE(x) (((x) & 0x7) << 28)
-#define ANDES_SPI_DCR_SPIT BIT(31) /* SPI bus trigger */
-
-#define ANDES_SPI_DCR_MODE_WRCON ANDES_SPI_DCR_TRAMODE(0) /* w/r at the same time */
-#define ANDES_SPI_DCR_MODE_WO ANDES_SPI_DCR_TRAMODE(1) /* write only */
-#define ANDES_SPI_DCR_MODE_RO ANDES_SPI_DCR_TRAMODE(2) /* read only */
-#define ANDES_SPI_DCR_MODE_WR ANDES_SPI_DCR_TRAMODE(3) /* write, read */
-#define ANDES_SPI_DCR_MODE_RW ANDES_SPI_DCR_TRAMODE(4) /* read, write */
-#define ANDES_SPI_DCR_MODE_WDR ANDES_SPI_DCR_TRAMODE(5) /* write, dummy, read */
-#define ANDES_SPI_DCR_MODE_RDW ANDES_SPI_DCR_TRAMODE(6) /* read, dummy, write */
-#define ANDES_SPI_DCR_MODE_RECEIVE ANDES_SPI_DCR_TRAMODE(7) /* receive */
-
-/* 0x20 - AHB SPI interface setting register */
-#define ANDES_SPI_AHB_BAUD(x) (((x) & 0xff) < 0)
-#define ANDES_SPI_AHB_CSHT(x) (((x) & 0xf) < 16)
-#define ANDES_SPI_AHB_SPNTS BIT(20) /* 0: normal, 1: delay */
-#define ANDES_SPI_AHB_CPHA BIT(24) /* 0: Sampling at odd edges */
-#define ANDES_SPI_AHB_CPOL BIT(25) /* 0: SCK low, 1: SCK high */
-#define ANDES_SPI_AHB_MSSL BIT(26) /* only Master mode */
-
-/* 0x3c - Version Register - (Year V.MAJOR.MINOR) */
-#define ANDES_SPI_VER_MINOR(x) (((x) >> 0) & 0xf)
-#define ANDES_SPI_VER_MAJOR(x) (((x) >> 8) & 0xf)
-#define ANDES_SPI_VER_YEAR(x) (((x) >> 16) & 0xf)
-
-struct andes_spi_slave {
- struct spi_slave slave;
- struct andes_spi_regs *regs;
- unsigned int freq;
-};
-
-static inline struct andes_spi_slave *to_andes_spi(struct spi_slave *slave)
-{
- return container_of(slave, struct andes_spi_slave, slave);
-}
-
-#endif /* __ANDES_SPI_H */
DECLARE_GLOBAL_DATA_PTR;
-#define clamp(x, low, high) (min(max(low, x), high))
#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, slave)
struct cf_qspi_slave {
dev->qmr = 2u;
else /* Get the closest baud rate */
dev->qmr = clamp(((gd->bus_clk >> 2) + max_hz - 1)/max_hz,
- 2u, 255u);
+ 2lu, 255lu);
/* Map mode to QMR[CPOL] and QMR[CPHA] */
if (mode & SPI_CPOL)
*
* SPDX-License-Identifier: GPL-2.0+
*/
+
#include <common.h>
#include <spi.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
-#include "davinci_spi.h"
-void spi_init()
-{
- /* do nothing */
-}
+#define BIT(x) (1 << (x))
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct davinci_spi_slave *ds;
+/* SPIGCR0 */
+#define SPIGCR0_SPIENA_MASK 0x1
+#define SPIGCR0_SPIRST_MASK 0x0
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
+/* SPIGCR0 */
+#define SPIGCR1_CLKMOD_MASK BIT(1)
+#define SPIGCR1_MASTER_MASK BIT(0)
+#define SPIGCR1_SPIENA_MASK BIT(24)
- ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs);
- if (!ds)
- return NULL;
+/* SPIPC0 */
+#define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */
+#define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */
+#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
+#define SPIPC0_EN0FUN_MASK BIT(0)
- switch (bus) {
- case SPI0_BUS:
- ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
- break;
-#ifdef CONFIG_SYS_SPI1
- case SPI1_BUS:
- ds->regs = (struct davinci_spi_regs *)SPI1_BASE;
- break;
-#endif
-#ifdef CONFIG_SYS_SPI2
- case SPI2_BUS:
- ds->regs = (struct davinci_spi_regs *)SPI2_BASE;
- break;
-#endif
- default: /* Invalid bus number */
- return NULL;
- }
+/* SPIFMT0 */
+#define SPIFMT_SHIFTDIR_SHIFT 20
+#define SPIFMT_POLARITY_SHIFT 17
+#define SPIFMT_PHASE_SHIFT 16
+#define SPIFMT_PRESCALE_SHIFT 8
- ds->freq = max_hz;
+/* SPIDAT1 */
+#define SPIDAT1_CSHOLD_SHIFT 28
+#define SPIDAT1_CSNR_SHIFT 16
- return &ds->slave;
-}
+/* SPIDELAY */
+#define SPI_C2TDELAY_SHIFT 24
+#define SPI_T2CDELAY_SHIFT 16
-void spi_free_slave(struct spi_slave *slave)
-{
- struct davinci_spi_slave *ds = to_davinci_spi(slave);
+/* SPIBUF */
+#define SPIBUF_RXEMPTY_MASK BIT(31)
+#define SPIBUF_TXFULL_MASK BIT(29)
- free(ds);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct davinci_spi_slave *ds = to_davinci_spi(slave);
- unsigned int scalar;
-
- /* Enable the SPI hardware */
- writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
- udelay(1000);
- writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
+/* SPIDEF */
+#define SPIDEF_CSDEF0_MASK BIT(0)
- /* Set master mode, powered up and not activated */
- writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
-
- /* CS, CLK, SIMO and SOMI are functional pins */
- writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK |
- SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
-
- /* setup format */
- scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
-
- /*
- * Use following format:
- * character length = 8,
- * clock signal delayed by half clk cycle,
- * clock low in idle state - Mode 0,
- * MSB shifted out first
- */
- writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
- (1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
-
- /*
- * Including a minor delay. No science here. Should be good even with
- * no delay
- */
- writel((50 << SPI_C2TDELAY_SHIFT) |
- (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
-
- /* default chip select register */
- writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
-
- /* no interrupts */
- writel(0, &ds->regs->int0);
- writel(0, &ds->regs->lvl);
+#define SPI0_BUS 0
+#define SPI0_BASE CONFIG_SYS_SPI_BASE
+/*
+ * Define default SPI0_NUM_CS as 1 for existing platforms that uses this
+ * driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS
+ * if more than one CS is supported and by defining CONFIG_SYS_SPI0.
+ */
+#ifndef CONFIG_SYS_SPI0
+#define SPI0_NUM_CS 1
+#else
+#define SPI0_NUM_CS CONFIG_SYS_SPI0_NUM_CS
+#endif
- /* enable SPI */
- writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
+/*
+ * define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and
+ * CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus
+ */
+#ifdef CONFIG_SYS_SPI1
+#define SPI1_BUS 1
+#define SPI1_NUM_CS CONFIG_SYS_SPI1_NUM_CS
+#define SPI1_BASE CONFIG_SYS_SPI1_BASE
+#endif
- return 0;
-}
+/*
+ * define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and
+ * CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus
+ */
+#ifdef CONFIG_SYS_SPI2
+#define SPI2_BUS 2
+#define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS
+#define SPI2_BASE CONFIG_SYS_SPI2_BASE
+#endif
-void spi_release_bus(struct spi_slave *slave)
+/* davinci spi register set */
+struct davinci_spi_regs {
+ dv_reg gcr0; /* 0x00 */
+ dv_reg gcr1; /* 0x04 */
+ dv_reg int0; /* 0x08 */
+ dv_reg lvl; /* 0x0c */
+ dv_reg flg; /* 0x10 */
+ dv_reg pc0; /* 0x14 */
+ dv_reg pc1; /* 0x18 */
+ dv_reg pc2; /* 0x1c */
+ dv_reg pc3; /* 0x20 */
+ dv_reg pc4; /* 0x24 */
+ dv_reg pc5; /* 0x28 */
+ dv_reg rsvd[3];
+ dv_reg dat0; /* 0x38 */
+ dv_reg dat1; /* 0x3c */
+ dv_reg buf; /* 0x40 */
+ dv_reg emu; /* 0x44 */
+ dv_reg delay; /* 0x48 */
+ dv_reg def; /* 0x4c */
+ dv_reg fmt0; /* 0x50 */
+ dv_reg fmt1; /* 0x54 */
+ dv_reg fmt2; /* 0x58 */
+ dv_reg fmt3; /* 0x5c */
+ dv_reg intvec0; /* 0x60 */
+ dv_reg intvec1; /* 0x64 */
+};
+
+/* davinci spi slave */
+struct davinci_spi_slave {
+ struct spi_slave slave;
+ struct davinci_spi_regs *regs;
+ unsigned int freq;
+};
+
+static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
{
- struct davinci_spi_slave *ds = to_davinci_spi(slave);
-
- /* Disable the SPI hardware */
- writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
+ return container_of(slave, struct davinci_spi_slave, slave);
}
/*
}
#endif
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ int ret = 0;
+
+ switch (bus) {
+ case SPI0_BUS:
+ if (cs < SPI0_NUM_CS)
+ ret = 1;
+ break;
+#ifdef CONFIG_SYS_SPI1
+ case SPI1_BUS:
+ if (cs < SPI1_NUM_CS)
+ ret = 1;
+ break;
+#endif
+#ifdef CONFIG_SYS_SPI2
+ case SPI2_BUS:
+ if (cs < SPI2_NUM_CS)
+ ret = 1;
+ break;
+#endif
+ default:
+ /* Invalid bus number. Do nothing */
+ break;
+ }
+ return ret;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void spi_init(void)
+{
+ /* do nothing */
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct davinci_spi_slave *ds;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs);
+ if (!ds)
+ return NULL;
+
+ switch (bus) {
+ case SPI0_BUS:
+ ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
+ break;
+#ifdef CONFIG_SYS_SPI1
+ case SPI1_BUS:
+ ds->regs = (struct davinci_spi_regs *)SPI1_BASE;
+ break;
+#endif
+#ifdef CONFIG_SYS_SPI2
+ case SPI2_BUS:
+ ds->regs = (struct davinci_spi_regs *)SPI2_BASE;
+ break;
+#endif
+ default: /* Invalid bus number */
+ return NULL;
+ }
+
+ ds->freq = max_hz;
+
+ return &ds->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct davinci_spi_slave *ds = to_davinci_spi(slave);
+
+ free(ds);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct davinci_spi_slave *ds = to_davinci_spi(slave);
+ unsigned int scalar;
+
+ /* Enable the SPI hardware */
+ writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
+ udelay(1000);
+ writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
+
+ /* Set master mode, powered up and not activated */
+ writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
+
+ /* CS, CLK, SIMO and SOMI are functional pins */
+ writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK |
+ SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
+
+ /* setup format */
+ scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
+
+ /*
+ * Use following format:
+ * character length = 8,
+ * clock signal delayed by half clk cycle,
+ * clock low in idle state - Mode 0,
+ * MSB shifted out first
+ */
+ writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
+ (1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
+
+ /*
+ * Including a minor delay. No science here. Should be good even with
+ * no delay
+ */
+ writel((50 << SPI_C2TDELAY_SHIFT) |
+ (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
+
+ /* default chip select register */
+ writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
+
+ /* no interrupts */
+ writel(0, &ds->regs->int0);
+ writel(0, &ds->regs->lvl);
+
+ /* enable SPI */
+ writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
+
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct davinci_spi_slave *ds = to_davinci_spi(slave);
+
+ /* Disable the SPI hardware */
+ writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
+}
+
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
}
return 0;
}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- int ret = 0;
-
- switch (bus) {
- case SPI0_BUS:
- if (cs < SPI0_NUM_CS)
- ret = 1;
- break;
-#ifdef CONFIG_SYS_SPI1
- case SPI1_BUS:
- if (cs < SPI1_NUM_CS)
- ret = 1;
- break;
-#endif
-#ifdef CONFIG_SYS_SPI2
- case SPI2_BUS:
- if (cs < SPI2_NUM_CS)
- ret = 1;
- break;
-#endif
- default:
- /* Invalid bus number. Do nothing */
- break;
- }
- return ret;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- /* do nothing */
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- /* do nothing */
-}
+++ /dev/null
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Register definitions for the DaVinci SPI Controller
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _DAVINCI_SPI_H_
-#define _DAVINCI_SPI_H_
-
-struct davinci_spi_regs {
- dv_reg gcr0; /* 0x00 */
- dv_reg gcr1; /* 0x04 */
- dv_reg int0; /* 0x08 */
- dv_reg lvl; /* 0x0c */
- dv_reg flg; /* 0x10 */
- dv_reg pc0; /* 0x14 */
- dv_reg pc1; /* 0x18 */
- dv_reg pc2; /* 0x1c */
- dv_reg pc3; /* 0x20 */
- dv_reg pc4; /* 0x24 */
- dv_reg pc5; /* 0x28 */
- dv_reg rsvd[3];
- dv_reg dat0; /* 0x38 */
- dv_reg dat1; /* 0x3c */
- dv_reg buf; /* 0x40 */
- dv_reg emu; /* 0x44 */
- dv_reg delay; /* 0x48 */
- dv_reg def; /* 0x4c */
- dv_reg fmt0; /* 0x50 */
- dv_reg fmt1; /* 0x54 */
- dv_reg fmt2; /* 0x58 */
- dv_reg fmt3; /* 0x5c */
- dv_reg intvec0; /* 0x60 */
- dv_reg intvec1; /* 0x64 */
-};
-
-#define BIT(x) (1 << (x))
-
-/* SPIGCR0 */
-#define SPIGCR0_SPIENA_MASK 0x1
-#define SPIGCR0_SPIRST_MASK 0x0
-
-/* SPIGCR0 */
-#define SPIGCR1_CLKMOD_MASK BIT(1)
-#define SPIGCR1_MASTER_MASK BIT(0)
-#define SPIGCR1_SPIENA_MASK BIT(24)
-
-/* SPIPC0 */
-#define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */
-#define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */
-#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
-#define SPIPC0_EN0FUN_MASK BIT(0)
-
-/* SPIFMT0 */
-#define SPIFMT_SHIFTDIR_SHIFT 20
-#define SPIFMT_POLARITY_SHIFT 17
-#define SPIFMT_PHASE_SHIFT 16
-#define SPIFMT_PRESCALE_SHIFT 8
-
-/* SPIDAT1 */
-#define SPIDAT1_CSHOLD_SHIFT 28
-#define SPIDAT1_CSNR_SHIFT 16
-
-/* SPIDELAY */
-#define SPI_C2TDELAY_SHIFT 24
-#define SPI_T2CDELAY_SHIFT 16
-
-/* SPIBUF */
-#define SPIBUF_RXEMPTY_MASK BIT(31)
-#define SPIBUF_TXFULL_MASK BIT(29)
-
-/* SPIDEF */
-#define SPIDEF_CSDEF0_MASK BIT(0)
-
-#define SPI0_BUS 0
-#define SPI0_BASE CONFIG_SYS_SPI_BASE
-/*
- * Define default SPI0_NUM_CS as 1 for existing platforms that uses this
- * driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS
- * if more than one CS is supported and by defining CONFIG_SYS_SPI0.
- */
-#ifndef CONFIG_SYS_SPI0
-#define SPI0_NUM_CS 1
-#else
-#define SPI0_NUM_CS CONFIG_SYS_SPI0_NUM_CS
-#endif
-
-/*
- * define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and
- * CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus
- */
-#ifdef CONFIG_SYS_SPI1
-#define SPI1_BUS 1
-#define SPI1_NUM_CS CONFIG_SYS_SPI1_NUM_CS
-#define SPI1_BASE CONFIG_SYS_SPI1_BASE
-#endif
-
-/*
- * define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and
- * CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus
- */
-#ifdef CONFIG_SYS_SPI2
-#define SPI2_BUS 2
-#define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS
-#define SPI2_BASE CONFIG_SYS_SPI2_BASE
-#endif
-
-struct davinci_spi_slave {
- struct spi_slave slave;
- struct davinci_spi_regs *regs;
- unsigned int freq;
-};
-
-static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
-{
- return container_of(slave, struct davinci_spi_slave, slave);
-}
-
-#endif /* _DAVINCI_SPI_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2013
- * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
- * Kuo-Jung Su <dantesu@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/compat.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <spi.h>
-
-#ifndef CONFIG_FTSSP010_BASE_LIST
-#define CONFIG_FTSSP010_BASE_LIST { CONFIG_FTSSP010_BASE }
-#endif
-
-#ifndef CONFIG_FTSSP010_GPIO_BASE
-#define CONFIG_FTSSP010_GPIO_BASE 0
-#endif
-
-#ifndef CONFIG_FTSSP010_GPIO_LIST
-#define CONFIG_FTSSP010_GPIO_LIST { CONFIG_FTSSP010_GPIO_BASE }
-#endif
-
-#ifndef CONFIG_FTSSP010_CLOCK
-#define CONFIG_FTSSP010_CLOCK clk_get_rate("SSP");
-#endif
-
-#ifndef CONFIG_FTSSP010_TIMEOUT
-#define CONFIG_FTSSP010_TIMEOUT 100
-#endif
-
-/* FTSSP010 chip registers */
-struct ftssp010_regs {
- uint32_t cr[3];/* control register */
- uint32_t sr; /* status register */
- uint32_t icr; /* interrupt control register */
- uint32_t isr; /* interrupt status register */
- uint32_t dr; /* data register */
- uint32_t rsvd[17];
- uint32_t revr; /* revision register */
- uint32_t fear; /* feature register */
-};
-
-/* Control Register 0 */
-#define CR0_FFMT_MASK (7 << 12)
-#define CR0_FFMT_SSP (0 << 12)
-#define CR0_FFMT_SPI (1 << 12)
-#define CR0_FFMT_MICROWIRE (2 << 12)
-#define CR0_FFMT_I2S (3 << 12)
-#define CR0_FFMT_AC97 (4 << 12)
-#define CR0_FLASH (1 << 11)
-#define CR0_FSDIST(x) (((x) & 0x03) << 8)
-#define CR0_LOOP (1 << 7) /* loopback mode */
-#define CR0_LSB (1 << 6) /* LSB */
-#define CR0_FSPO (1 << 5) /* fs atcive low (I2S only) */
-#define CR0_FSJUSTIFY (1 << 4)
-#define CR0_OPM_SLAVE (0 << 2)
-#define CR0_OPM_MASTER (3 << 2)
-#define CR0_OPM_I2S_MSST (3 << 2) /* master stereo mode */
-#define CR0_OPM_I2S_MSMO (2 << 2) /* master mono mode */
-#define CR0_OPM_I2S_SLST (1 << 2) /* slave stereo mode */
-#define CR0_OPM_I2S_SLMO (0 << 2) /* slave mono mode */
-#define CR0_SCLKPO (1 << 1) /* clock polarity */
-#define CR0_SCLKPH (1 << 0) /* clock phase */
-
-/* Control Register 1 */
-#define CR1_PDL(x) (((x) & 0xff) << 24) /* padding length */
-#define CR1_SDL(x) ((((x) - 1) & 0x1f) << 16) /* data length */
-#define CR1_DIV(x) (((x) - 1) & 0xffff) /* clock divider */
-
-/* Control Register 2 */
-#define CR2_CS(x) (((x) & 3) << 10) /* CS/FS select */
-#define CR2_FS (1 << 9) /* CS/FS signal level */
-#define CR2_TXEN (1 << 8) /* tx enable */
-#define CR2_RXEN (1 << 7) /* rx enable */
-#define CR2_RESET (1 << 6) /* chip reset */
-#define CR2_TXFC (1 << 3) /* tx fifo Clear */
-#define CR2_RXFC (1 << 2) /* rx fifo Clear */
-#define CR2_TXDOE (1 << 1) /* tx data output enable */
-#define CR2_EN (1 << 0) /* chip enable */
-
-/* Status Register */
-#define SR_RFF (1 << 0) /* rx fifo full */
-#define SR_TFNF (1 << 1) /* tx fifo not full */
-#define SR_BUSY (1 << 2) /* chip busy */
-#define SR_RFVE(reg) (((reg) >> 4) & 0x1f) /* rx fifo valid entries */
-#define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* tx fifo valid entries */
-
-/* Feature Register */
-#define FEAR_BITS(reg) ((((reg) >> 0) & 0xff) + 1) /* data width */
-#define FEAR_RFSZ(reg) ((((reg) >> 8) & 0xff) + 1) /* rx fifo size */
-#define FEAR_TFSZ(reg) ((((reg) >> 16) & 0xff) + 1) /* tx fifo size */
-#define FEAR_AC97 (1 << 24)
-#define FEAR_I2S (1 << 25)
-#define FEAR_SPI_MWR (1 << 26)
-#define FEAR_SSP (1 << 27)
-#define FEAR_SPDIF (1 << 28)
-
-/* FTGPIO010 chip registers */
-struct ftgpio010_regs {
- uint32_t out; /* 0x00: Data Output */
- uint32_t in; /* 0x04: Data Input */
- uint32_t dir; /* 0x08: Direction */
- uint32_t bypass; /* 0x0c: Bypass */
- uint32_t set; /* 0x10: Data Set */
- uint32_t clr; /* 0x14: Data Clear */
- uint32_t pull_up; /* 0x18: Pull-Up Enabled */
- uint32_t pull_st; /* 0x1c: Pull State (0=pull-down, 1=pull-up) */
-};
-
-struct ftssp010_gpio {
- struct ftgpio010_regs *regs;
- uint32_t pin;
-};
-
-struct ftssp010_spi {
- struct spi_slave slave;
- struct ftssp010_gpio gpio;
- struct ftssp010_regs *regs;
- uint32_t fifo;
- uint32_t mode;
- uint32_t div;
- uint32_t clk;
- uint32_t speed;
- uint32_t revision;
-};
-
-static inline struct ftssp010_spi *to_ftssp010_spi(struct spi_slave *slave)
-{
- return container_of(slave, struct ftssp010_spi, slave);
-}
-
-static int get_spi_chip(int bus, struct ftssp010_spi *chip)
-{
- uint32_t fear, base[] = CONFIG_FTSSP010_BASE_LIST;
-
- if (bus >= ARRAY_SIZE(base) || !base[bus])
- return -1;
-
- chip->regs = (struct ftssp010_regs *)base[bus];
-
- chip->revision = readl(&chip->regs->revr);
-
- fear = readl(&chip->regs->fear);
- chip->fifo = min_t(uint32_t, FEAR_TFSZ(fear), FEAR_RFSZ(fear));
-
- return 0;
-}
-
-static int get_spi_gpio(int bus, struct ftssp010_gpio *chip)
-{
- uint32_t base[] = CONFIG_FTSSP010_GPIO_LIST;
-
- if (bus >= ARRAY_SIZE(base) || !base[bus])
- return -1;
-
- chip->regs = (struct ftgpio010_regs *)(base[bus] & 0xfff00000);
- chip->pin = base[bus] & 0x1f;
-
- /* make it an output pin */
- setbits_le32(&chip->regs->dir, 1 << chip->pin);
-
- return 0;
-}
-
-static int ftssp010_wait(struct ftssp010_spi *chip)
-{
- struct ftssp010_regs *regs = chip->regs;
- ulong t;
-
- /* wait until device idle */
- for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
- if (!(readl(®s->sr) & SR_BUSY))
- return 0;
- }
-
- puts("ftspi010: busy timeout\n");
-
- return -1;
-}
-
-static int ftssp010_wait_tx(struct ftssp010_spi *chip)
-{
- struct ftssp010_regs *regs = chip->regs;
- ulong t;
-
- /* wait until tx fifo not full */
- for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
- if (readl(®s->sr) & SR_TFNF)
- return 0;
- }
-
- puts("ftssp010: tx timeout\n");
-
- return -1;
-}
-
-static int ftssp010_wait_rx(struct ftssp010_spi *chip)
-{
- struct ftssp010_regs *regs = chip->regs;
- ulong t;
-
- /* wait until rx fifo not empty */
- for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
- if (SR_RFVE(readl(®s->sr)))
- return 0;
- }
-
- puts("ftssp010: rx timeout\n");
-
- return -1;
-}
-
-static int ftssp010_spi_work_transfer_v2(struct ftssp010_spi *chip,
- const void *tx_buf, void *rx_buf, int len, uint flags)
-{
- struct ftssp010_regs *regs = chip->regs;
- const uint8_t *txb = tx_buf;
- uint8_t *rxb = rx_buf;
-
- while (len > 0) {
- int i, depth = min(chip->fifo >> 2, len);
- uint32_t xmsk = 0;
-
- if (tx_buf) {
- for (i = 0; i < depth; ++i) {
- ftssp010_wait_tx(chip);
- writel(*txb++, ®s->dr);
- }
- xmsk |= CR2_TXEN | CR2_TXDOE;
- if ((readl(®s->cr[2]) & xmsk) != xmsk)
- setbits_le32(®s->cr[2], xmsk);
- }
- if (rx_buf) {
- xmsk |= CR2_RXEN;
- if ((readl(®s->cr[2]) & xmsk) != xmsk)
- setbits_le32(®s->cr[2], xmsk);
- for (i = 0; i < depth; ++i) {
- ftssp010_wait_rx(chip);
- *rxb++ = (uint8_t)readl(®s->dr);
- }
- }
-
- len -= depth;
- }
-
- return 0;
-}
-
-static int ftssp010_spi_work_transfer_v1(struct ftssp010_spi *chip,
- const void *tx_buf, void *rx_buf, int len, uint flags)
-{
- struct ftssp010_regs *regs = chip->regs;
- const uint8_t *txb = tx_buf;
- uint8_t *rxb = rx_buf;
-
- while (len > 0) {
- int i, depth = min(chip->fifo >> 2, len);
- uint32_t tmp;
-
- for (i = 0; i < depth; ++i) {
- ftssp010_wait_tx(chip);
- writel(txb ? (*txb++) : 0, ®s->dr);
- }
- for (i = 0; i < depth; ++i) {
- ftssp010_wait_rx(chip);
- tmp = readl(®s->dr);
- if (rxb)
- *rxb++ = (uint8_t)tmp;
- }
-
- len -= depth;
- }
-
- return 0;
-}
-
-static void ftssp010_cs_set(struct ftssp010_spi *chip, int high)
-{
- struct ftssp010_regs *regs = chip->regs;
- struct ftssp010_gpio *gpio = &chip->gpio;
- uint32_t mask;
-
- /* cs pull high/low */
- if (chip->revision >= 0x11900) {
- mask = CR2_CS(chip->slave.cs) | (high ? CR2_FS : 0);
- writel(mask, ®s->cr[2]);
- } else if (gpio->regs) {
- mask = 1 << gpio->pin;
- if (high)
- writel(mask, &gpio->regs->set);
- else
- writel(mask, &gpio->regs->clr);
- }
-
- /* extra delay for signal propagation */
- udelay_masked(1);
-}
-
-/*
- * Determine if a SPI chipselect is valid.
- * This function is provided by the board if the low-level SPI driver
- * needs it to determine if a given chipselect is actually valid.
- *
- * Returns: 1 if bus:cs identifies a valid chip on this board, 0
- * otherwise.
- */
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- struct ftssp010_spi chip;
-
- if (get_spi_chip(bus, &chip))
- return 0;
-
- if (!cs)
- return 1;
- else if ((cs < 4) && (chip.revision >= 0x11900))
- return 1;
-
- return 0;
-}
-
-/*
- * Activate a SPI chipselect.
- * This function is provided by the board code when using a driver
- * that can't control its chipselects automatically (e.g.
- * common/soft_spi.c). When called, it should activate the chip select
- * to the device identified by "slave".
- */
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct ftssp010_spi *chip = to_ftssp010_spi(slave);
- struct ftssp010_regs *regs = chip->regs;
-
- /* cs pull */
- if (chip->mode & SPI_CS_HIGH)
- ftssp010_cs_set(chip, 1);
- else
- ftssp010_cs_set(chip, 0);
-
- /* chip enable + fifo clear */
- setbits_le32(®s->cr[2], CR2_EN | CR2_TXFC | CR2_RXFC);
-}
-
-/*
- * Deactivate a SPI chipselect.
- * This function is provided by the board code when using a driver
- * that can't control its chipselects automatically (e.g.
- * common/soft_spi.c). When called, it should deactivate the chip
- * select to the device identified by "slave".
- */
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct ftssp010_spi *chip = to_ftssp010_spi(slave);
-
- /* wait until chip idle */
- ftssp010_wait(chip);
-
- /* cs pull */
- if (chip->mode & SPI_CS_HIGH)
- ftssp010_cs_set(chip, 0);
- else
- ftssp010_cs_set(chip, 1);
-}
-
-void spi_init(void)
-{
- /* nothing to do */
-}
-
-struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
-{
- struct ftssp010_spi *chip;
-
- if (mode & SPI_3WIRE) {
- puts("ftssp010: can't do 3-wire\n");
- return NULL;
- }
-
- if (mode & SPI_SLAVE) {
- puts("ftssp010: can't do slave mode\n");
- return NULL;
- }
-
- if (mode & SPI_PREAMBLE) {
- puts("ftssp010: can't skip preamble bytes\n");
- return NULL;
- }
-
- if (!spi_cs_is_valid(bus, cs)) {
- puts("ftssp010: invalid (bus, cs)\n");
- return NULL;
- }
-
- chip = spi_alloc_slave(struct ftssp010_spi, bus, cs);
- if (!chip)
- return NULL;
-
- if (get_spi_chip(bus, chip))
- goto free_out;
-
- if (chip->revision < 0x11900 && get_spi_gpio(bus, &chip->gpio)) {
- puts("ftssp010: Before revision 1.19.0, its clock & cs are\n"
- "controlled by tx engine which is not synced with rx engine,\n"
- "so the clock & cs might be shutdown before rx engine\n"
- "finishs its jobs.\n"
- "If possible, please add a dedicated gpio for it.\n");
- }
-
- chip->mode = mode;
- chip->clk = CONFIG_FTSSP010_CLOCK;
- chip->div = 2;
- if (max_hz) {
- while (chip->div < 0xffff) {
- if ((chip->clk / (2 * chip->div)) <= max_hz)
- break;
- chip->div += 1;
- }
- }
- chip->speed = chip->clk / (2 * chip->div);
-
- return &chip->slave;
-
-free_out:
- free(chip);
- return NULL;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct ftssp010_spi *chip = to_ftssp010_spi(slave);
-
- free(chip);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct ftssp010_spi *chip = to_ftssp010_spi(slave);
- struct ftssp010_regs *regs = chip->regs;
-
- writel(CR1_SDL(8) | CR1_DIV(chip->div), ®s->cr[1]);
-
- if (chip->revision >= 0x11900) {
- writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO | CR0_FLASH,
- ®s->cr[0]);
- writel(CR2_TXFC | CR2_RXFC,
- ®s->cr[2]);
- } else {
- writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO,
- ®s->cr[0]);
- writel(CR2_TXFC | CR2_RXFC | CR2_EN | CR2_TXDOE,
- ®s->cr[2]);
- }
-
- if (chip->mode & SPI_LOOP)
- setbits_le32(®s->cr[0], CR0_LOOP);
-
- if (chip->mode & SPI_CPOL)
- setbits_le32(®s->cr[0], CR0_SCLKPO);
-
- if (chip->mode & SPI_CPHA)
- setbits_le32(®s->cr[0], CR0_SCLKPH);
-
- spi_cs_deactivate(slave);
-
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- struct ftssp010_spi *chip = to_ftssp010_spi(slave);
- struct ftssp010_regs *regs = chip->regs;
-
- writel(0, ®s->cr[2]);
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
-{
- struct ftssp010_spi *chip = to_ftssp010_spi(slave);
- uint32_t len = bitlen >> 3;
-
- if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
-
- if (chip->revision >= 0x11900)
- ftssp010_spi_work_transfer_v2(chip, dout, din, len, flags);
- else
- ftssp010_spi_work_transfer_v1(chip, dout, din, len, flags);
-
- if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
-
- return 0;
-}
+++ /dev/null
-/*
- * Opencore tiny_spi driver
- *
- * http://opencores.org/project,tiny_spi
- *
- * based on bfin_spi.c
- * Copyright (c) 2005-2008 Analog Devices Inc.
- * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <spi.h>
-#include <asm/gpio.h>
-
-#define TINY_SPI_STATUS_TXE 0x1
-#define TINY_SPI_STATUS_TXR 0x2
-
-struct tiny_spi_regs {
- unsigned rxdata; /* Rx data reg */
- unsigned txdata; /* Tx data reg */
- unsigned status; /* Status reg */
- unsigned control; /* Control reg */
- unsigned baud; /* Baud reg */
-};
-
-struct tiny_spi_host {
- uint base;
- uint freq;
- uint baudwidth;
-};
-static const struct tiny_spi_host tiny_spi_host_list[] =
- CONFIG_SYS_TINY_SPI_LIST;
-
-struct tiny_spi_slave {
- struct spi_slave slave;
- const struct tiny_spi_host *host;
- uint mode;
- uint baud;
- uint flg;
-};
-#define to_tiny_spi_slave(s) container_of(s, struct tiny_spi_slave, slave)
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus < ARRAY_SIZE(tiny_spi_host_list) && gpio_is_valid(cs);
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave);
- unsigned int cs = slave->cs;
-
- gpio_set_value(cs, tiny_spi->flg);
- debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave);
- unsigned int cs = slave->cs;
-
- gpio_set_value(cs, !tiny_spi->flg);
- debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
-}
-
-void spi_set_speed(struct spi_slave *slave, uint hz)
-{
- struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave);
- const struct tiny_spi_host *host = tiny_spi->host;
-
- tiny_spi->baud = min(DIV_ROUND_UP(host->freq, hz * 2),
- (1 << host->baudwidth)) - 1;
- debug("%s: speed %u actual %u\n", __func__, hz,
- host->freq / ((tiny_spi->baud + 1) * 2));
-}
-
-void spi_init(void)
-{
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int hz, unsigned int mode)
-{
- struct tiny_spi_slave *tiny_spi;
-
- if (!spi_cs_is_valid(bus, cs) || gpio_request(cs, "tiny_spi"))
- return NULL;
-
- tiny_spi = spi_alloc_slave(struct tiny_spi_slave, bus, cs);
- if (!tiny_spi)
- return NULL;
-
- tiny_spi->host = &tiny_spi_host_list[bus];
- tiny_spi->mode = mode & (SPI_CPOL | SPI_CPHA);
- tiny_spi->flg = mode & SPI_CS_HIGH ? 1 : 0;
- spi_set_speed(&tiny_spi->slave, hz);
-
- debug("%s: bus:%i cs:%i base:%lx\n", __func__,
- bus, cs, tiny_spi->host->base);
- return &tiny_spi->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave);
-
- gpio_free(slave->cs);
- free(tiny_spi);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave);
- struct tiny_spi_regs *regs = (void *)tiny_spi->host->base;
-
- debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
- gpio_direction_output(slave->cs, !tiny_spi->flg);
- writel(tiny_spi->mode, ®s->control);
- writel(tiny_spi->baud, ®s->baud);
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
-}
-
-#ifndef CONFIG_TINY_SPI_IDLE_VAL
-# define CONFIG_TINY_SPI_IDLE_VAL 0xff
-#endif
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
-{
- struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave);
- struct tiny_spi_regs *regs = (void *)tiny_spi->host->base;
- const u8 *txp = dout;
- u8 *rxp = din;
- uint bytes = bitlen / 8;
- uint i;
-
- debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
- slave->bus, slave->cs, bitlen, bytes, flags);
- if (bitlen == 0)
- goto done;
-
- /* assume to do 8 bits transfers */
- if (bitlen % 8) {
- flags |= SPI_XFER_END;
- goto done;
- }
-
- if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
-
- /* we need to tighten the transfer loop */
- if (txp && rxp) {
- writeb(*txp++, ®s->txdata);
- if (bytes > 1) {
- writeb(*txp++, ®s->txdata);
- for (i = 2; i < bytes; i++) {
- u8 rx, tx = *txp++;
- while (!(readb(®s->status) &
- TINY_SPI_STATUS_TXR))
- ;
- rx = readb(®s->txdata);
- writeb(tx, ®s->txdata);
- *rxp++ = rx;
- }
- while (!(readb(®s->status) &
- TINY_SPI_STATUS_TXR))
- ;
- *rxp++ = readb(®s->txdata);
- }
- while (!(readb(®s->status) &
- TINY_SPI_STATUS_TXE))
- ;
- *rxp++ = readb(®s->rxdata);
- } else if (rxp) {
- writeb(CONFIG_TINY_SPI_IDLE_VAL, ®s->txdata);
- if (bytes > 1) {
- writeb(CONFIG_TINY_SPI_IDLE_VAL,
- ®s->txdata);
- for (i = 2; i < bytes; i++) {
- u8 rx;
- while (!(readb(®s->status) &
- TINY_SPI_STATUS_TXR))
- ;
- rx = readb(®s->txdata);
- writeb(CONFIG_TINY_SPI_IDLE_VAL,
- ®s->txdata);
- *rxp++ = rx;
- }
- while (!(readb(®s->status) &
- TINY_SPI_STATUS_TXR))
- ;
- *rxp++ = readb(®s->txdata);
- }
- while (!(readb(®s->status) &
- TINY_SPI_STATUS_TXE))
- ;
- *rxp++ = readb(®s->rxdata);
- } else if (txp) {
- writeb(*txp++, ®s->txdata);
- if (bytes > 1) {
- writeb(*txp++, ®s->txdata);
- for (i = 2; i < bytes; i++) {
- u8 tx = *txp++;
- while (!(readb(®s->status) &
- TINY_SPI_STATUS_TXR))
- ;
- writeb(tx, ®s->txdata);
- }
- }
- while (!(readb(®s->status) &
- TINY_SPI_STATUS_TXE))
- ;
- } else {
- writeb(CONFIG_TINY_SPI_IDLE_VAL, ®s->txdata);
- if (bytes > 1) {
- writeb(CONFIG_TINY_SPI_IDLE_VAL,
- ®s->txdata);
- for (i = 2; i < bytes; i++) {
- while (!(readb(®s->status) &
- TINY_SPI_STATUS_TXR))
- ;
- writeb(CONFIG_TINY_SPI_IDLE_VAL,
- ®s->txdata);
- }
- }
- while (!(readb(®s->status) &
- TINY_SPI_STATUS_TXE))
- ;
- }
-
- done:
- if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
-
- return 0;
-}
/*
* Xilinx SPI driver
*
- * supports 8 bit SPI transfers only, with or w/o FIFO
+ * Supports 8 bit SPI transfers only, with or w/o FIFO
*
- * based on bfin_spi.c, by way of altera_spi.c
- * Copyright (c) 2005-2008 Analog Devices Inc.
- * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
- * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
+ * Based on bfin_spi.c, by way of altera_spi.c
+ * Copyright (c) 2015 Jagan Teki <jteki@openedev.com>
* Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
+ * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
+ * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
+ * Copyright (c) 2005-2008 Analog Devices Inc.
*
* SPDX-License-Identifier: GPL-2.0+
- *
- * [0]: http://www.xilinx.com/support/documentation
- *
- * [S]: [0]/ip_documentation/xps_spi.pdf
- * [0]/ip_documentation/axi_spi_ds742.pdf
*/
+
#include <config.h>
#include <common.h>
+#include <dm.h>
+#include <errno.h>
#include <malloc.h>
#include <spi.h>
+#include <asm/io.h>
-#include "xilinx_spi.h"
+/*
+ * [0]: http://www.xilinx.com/support/documentation
+ *
+ * Xilinx SPI Register Definitions
+ * [1]: [0]/ip_documentation/xps_spi.pdf
+ * page 8, Register Descriptions
+ * [2]: [0]/ip_documentation/axi_spi_ds742.pdf
+ * page 7, Register Overview Table
+ */
-#ifndef CONFIG_SYS_XILINX_SPI_LIST
-#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
-#endif
+/* SPI Control Register (spicr), [1] p9, [2] p8 */
+#define SPICR_LSB_FIRST (1 << 9)
+#define SPICR_MASTER_INHIBIT (1 << 8)
+#define SPICR_MANUAL_SS (1 << 7)
+#define SPICR_RXFIFO_RESEST (1 << 6)
+#define SPICR_TXFIFO_RESEST (1 << 5)
+#define SPICR_CPHA (1 << 4)
+#define SPICR_CPOL (1 << 3)
+#define SPICR_MASTER_MODE (1 << 2)
+#define SPICR_SPE (1 << 1)
+#define SPICR_LOOP (1 << 0)
+
+/* SPI Status Register (spisr), [1] p11, [2] p10 */
+#define SPISR_SLAVE_MODE_SELECT (1 << 5)
+#define SPISR_MODF (1 << 4)
+#define SPISR_TX_FULL (1 << 3)
+#define SPISR_TX_EMPTY (1 << 2)
+#define SPISR_RX_FULL (1 << 1)
+#define SPISR_RX_EMPTY (1 << 0)
+
+/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
+#define SPIDTR_8BIT_MASK (0xff << 0)
+#define SPIDTR_16BIT_MASK (0xffff << 0)
+#define SPIDTR_32BIT_MASK (0xffffffff << 0)
+
+/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
+#define SPIDRR_8BIT_MASK (0xff << 0)
+#define SPIDRR_16BIT_MASK (0xffff << 0)
+#define SPIDRR_32BIT_MASK (0xffffffff << 0)
+
+/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
+#define SPISSR_MASK(cs) (1 << (cs))
+#define SPISSR_ACT(cs) ~SPISSR_MASK(cs)
+#define SPISSR_OFF ~0UL
+
+/* SPI Software Reset Register (ssr) */
+#define SPISSR_RESET_VALUE 0x0a
+
+#define XILSPI_MAX_XFER_BITS 8
+#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | SPICR_MASTER_MODE | \
+ SPICR_SPE)
+#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
#ifndef CONFIG_XILINX_SPI_IDLE_VAL
#define CONFIG_XILINX_SPI_IDLE_VAL 0xff
#endif
-#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | \
- SPICR_MASTER_MODE | \
- SPICR_SPE)
-
-#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | \
- SPICR_MANUAL_SS)
+#ifndef CONFIG_SYS_XILINX_SPI_LIST
+#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
+#endif
-#define XILSPI_MAX_XFER_BITS 8
+/* xilinx spi register set */
+struct xilinx_spi_regs {
+ u32 __space0__[7];
+ u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
+ u32 ipisr; /* IP Interrupt Status Register (IPISR) */
+ u32 __space1__;
+ u32 ipier; /* IP Interrupt Enable Register (IPIER) */
+ u32 __space2__[5];
+ u32 srr; /* Softare Reset Register (SRR) */
+ u32 __space3__[7];
+ u32 spicr; /* SPI Control Register (SPICR) */
+ u32 spisr; /* SPI Status Register (SPISR) */
+ u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */
+ u32 spidrr; /* SPI Data Receive Register (SPIDRR) */
+ u32 spissr; /* SPI Slave Select Register (SPISSR) */
+ u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */
+ u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */
+};
+
+/* xilinx spi priv */
+struct xilinx_spi_priv {
+ struct xilinx_spi_regs *regs;
+ unsigned int freq;
+ unsigned int mode;
+};
static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
-
-__attribute__((weak))
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+static int xilinx_spi_probe(struct udevice *bus)
{
- return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32;
-}
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+ struct xilinx_spi_regs *regs = priv->regs;
-__attribute__((weak))
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+ priv->regs = (struct xilinx_spi_regs *)xilinx_spi_base_list[bus->seq];
- writel(SPISSR_ACT(slave->cs), &xilspi->regs->spissr);
-}
+ writel(SPISSR_RESET_VALUE, ®s->srr);
-__attribute__((weak))
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
-
- writel(SPISSR_OFF, &xilspi->regs->spissr);
+ return 0;
}
-void spi_init(void)
+static void spi_cs_activate(struct udevice *dev, uint cs)
{
- /* do nothing */
-}
+ struct udevice *bus = dev_get_parent(dev);
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+ struct xilinx_spi_regs *regs = priv->regs;
-void spi_set_speed(struct spi_slave *slave, uint hz)
-{
- /* xilinx spi core does not support programmable speed */
+ writel(SPISSR_ACT(cs), ®s->spissr);
}
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static void spi_cs_deactivate(struct udevice *dev)
{
- struct xilinx_spi_slave *xilspi;
-
- if (!spi_cs_is_valid(bus, cs)) {
- printf("XILSPI error: %s: unsupported bus %d / cs %d\n",
- __func__, bus, cs);
- return NULL;
- }
-
- xilspi = spi_alloc_slave(struct xilinx_spi_slave, bus, cs);
- if (!xilspi) {
- printf("XILSPI error: %s: malloc of SPI structure failed\n",
- __func__);
- return NULL;
- }
- xilspi->regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus];
- xilspi->freq = max_hz;
- xilspi->mode = mode;
- debug("%s: bus:%i cs:%i base:%p mode:%x max_hz:%d\n", __func__,
- bus, cs, xilspi->regs, xilspi->mode, xilspi->freq);
+ struct udevice *bus = dev_get_parent(dev);
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+ struct xilinx_spi_regs *regs = priv->regs;
- writel(SPISSR_RESET_VALUE, &xilspi->regs->srr);
-
- return &xilspi->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
-
- free(xilspi);
+ writel(SPISSR_OFF, ®s->spissr);
}
-int spi_claim_bus(struct spi_slave *slave)
+static int xilinx_spi_claim_bus(struct udevice *dev)
{
- struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
- u32 spicr;
+ struct udevice *bus = dev_get_parent(dev);
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+ struct xilinx_spi_regs *regs = priv->regs;
- debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
- writel(SPISSR_OFF, &xilspi->regs->spissr);
+ writel(SPISSR_OFF, ®s->spissr);
+ writel(XILSPI_SPICR_DFLT_ON, ®s->spicr);
- spicr = XILSPI_SPICR_DFLT_ON;
- if (xilspi->mode & SPI_LSB_FIRST)
- spicr |= SPICR_LSB_FIRST;
- if (xilspi->mode & SPI_CPHA)
- spicr |= SPICR_CPHA;
- if (xilspi->mode & SPI_CPOL)
- spicr |= SPICR_CPOL;
- if (xilspi->mode & SPI_LOOP)
- spicr |= SPICR_LOOP;
-
- writel(spicr, &xilspi->regs->spicr);
return 0;
}
-void spi_release_bus(struct spi_slave *slave)
+static int xilinx_spi_release_bus(struct udevice *dev)
{
- struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+ struct udevice *bus = dev_get_parent(dev);
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+ struct xilinx_spi_regs *regs = priv->regs;
+
+ writel(SPISSR_OFF, ®s->spissr);
+ writel(XILSPI_SPICR_DFLT_OFF, ®s->spicr);
- debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
- writel(SPISSR_OFF, &xilspi->regs->spissr);
- writel(XILSPI_SPICR_DFLT_OFF, &xilspi->regs->spicr);
+ return 0;
}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
+static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
{
- struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+ struct udevice *bus = dev_get_parent(dev);
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+ struct xilinx_spi_regs *regs = priv->regs;
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
/* assume spi core configured to do 8 bit transfers */
unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
const unsigned char *txp = dout;
unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */
unsigned global_timeout;
- debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
- slave->bus, slave->cs, bitlen, bytes, flags);
+ debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
+ bus->seq, slave_plat->cs, bitlen, bytes, flags);
+
if (bitlen == 0)
goto done;
if (bitlen % XILSPI_MAX_XFER_BITS) {
- printf("XILSPI warning: %s: Not a multiple of %d bits\n",
- __func__, XILSPI_MAX_XFER_BITS);
+ printf("XILSPI warning: Not a multiple of %d bits\n",
+ XILSPI_MAX_XFER_BITS);
flags |= SPI_XFER_END;
goto done;
}
/* empty read buffer */
- while (rxecount && !(readl(&xilspi->regs->spisr) & SPISR_RX_EMPTY)) {
- readl(&xilspi->regs->spidrr);
+ while (rxecount && !(readl(®s->spisr) & SPISR_RX_EMPTY)) {
+ readl(®s->spidrr);
rxecount--;
}
if (!rxecount) {
- printf("XILSPI error: %s: Rx buffer not empty\n", __func__);
+ printf("XILSPI error: Rx buffer not empty\n");
return -1;
}
if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
+ spi_cs_activate(dev, slave_plat->cs);
/* at least 1usec or greater, leftover 1 */
- global_timeout = xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 :
- (XILSPI_MAX_XFER_BITS * 1000000 / xilspi->freq) + 1;
+ global_timeout = priv->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 :
+ (XILSPI_MAX_XFER_BITS * 1000000 / priv->freq) + 1;
while (bytes--) {
unsigned timeout = global_timeout;
/* get Tx element from data out buffer and count up */
unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
- debug("%s: tx:%x ", __func__, d);
+ debug("spi_xfer: tx:%x ", d);
/* write out and wait for processing (receive data) */
- writel(d & SPIDTR_8BIT_MASK, &xilspi->regs->spidtr);
- while (timeout && readl(&xilspi->regs->spisr)
+ writel(d & SPIDTR_8BIT_MASK, ®s->spidtr);
+ while (timeout && readl(®s->spisr)
& SPISR_RX_EMPTY) {
timeout--;
udelay(1);
}
if (!timeout) {
- printf("XILSPI error: %s: Xfer timeout\n", __func__);
+ printf("XILSPI error: Xfer timeout\n");
return -1;
}
/* read Rx element and push into data in buffer */
- d = readl(&xilspi->regs->spidrr) & SPIDRR_8BIT_MASK;
+ d = readl(®s->spidrr) & SPIDRR_8BIT_MASK;
if (rxp)
*rxp++ = d;
- debug("rx:%x\n", d);
+ debug("spi_xfer: rx:%x\n", d);
}
done:
if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+ spi_cs_deactivate(dev);
return 0;
}
+
+static int xilinx_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+
+ priv->freq = speed;
+
+ debug("xilinx_spi_set_speed: regs=%p, mode=%d\n", priv->regs,
+ priv->freq);
+
+ return 0;
+}
+
+static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+ struct xilinx_spi_regs *regs = priv->regs;
+ uint32_t spicr;
+
+ spicr = readl(®s->spicr);
+ if (priv->mode & SPI_LSB_FIRST)
+ spicr |= SPICR_LSB_FIRST;
+ if (priv->mode & SPI_CPHA)
+ spicr |= SPICR_CPHA;
+ if (priv->mode & SPI_CPOL)
+ spicr |= SPICR_CPOL;
+ if (priv->mode & SPI_LOOP)
+ spicr |= SPICR_LOOP;
+
+ writel(spicr, ®s->spicr);
+ priv->mode = mode;
+
+ debug("xilinx_spi_set_mode: regs=%p, mode=%d\n", priv->regs,
+ priv->mode);
+
+ return 0;
+}
+
+static const struct dm_spi_ops xilinx_spi_ops = {
+ .claim_bus = xilinx_spi_claim_bus,
+ .release_bus = xilinx_spi_release_bus,
+ .xfer = xilinx_spi_xfer,
+ .set_speed = xilinx_spi_set_speed,
+ .set_mode = xilinx_spi_set_mode,
+};
+
+static const struct udevice_id xilinx_spi_ids[] = {
+ { .compatible = "xlnx,xilinx-spi" },
+ { }
+};
+
+U_BOOT_DRIVER(xilinx_spi) = {
+ .name = "xilinx_spi",
+ .id = UCLASS_SPI,
+ .of_match = xilinx_spi_ids,
+ .ops = &xilinx_spi_ops,
+ .priv_auto_alloc_size = sizeof(struct xilinx_spi_priv),
+ .probe = xilinx_spi_probe,
+};
+++ /dev/null
-/*
- * Xilinx SPI driver
- *
- * XPS/AXI bus interface
- *
- * based on bfin_spi.c, by way of altera_spi.c
- * Copyright (c) 2005-2008 Analog Devices Inc.
- * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
- * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
- * Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * [0]: http://www.xilinx.com/support/documentation
- *
- * [S]: [0]/ip_documentation/xps_spi.pdf
- * [0]/ip_documentation/axi_spi_ds742.pdf
- */
-#ifndef _XILINX_SPI_
-#define _XILINX_SPI_
-
-#include <asm/types.h>
-#include <asm/io.h>
-
-/*
- * Xilinx SPI Register Definition
- *
- * [1]: [0]/ip_documentation/xps_spi.pdf
- * page 8, Register Descriptions
- * [2]: [0]/ip_documentation/axi_spi_ds742.pdf
- * page 7, Register Overview Table
- */
-struct xilinx_spi_reg {
- u32 __space0__[7];
- u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
- u32 ipisr; /* IP Interrupt Status Register (IPISR) */
- u32 __space1__;
- u32 ipier; /* IP Interrupt Enable Register (IPIER) */
- u32 __space2__[5];
- u32 srr; /* Softare Reset Register (SRR) */
- u32 __space3__[7];
- u32 spicr; /* SPI Control Register (SPICR) */
- u32 spisr; /* SPI Status Register (SPISR) */
- u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */
- u32 spidrr; /* SPI Data Receive Register (SPIDRR) */
- u32 spissr; /* SPI Slave Select Register (SPISSR) */
- u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */
- u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */
-};
-
-/* Device Global Interrupt Enable Register (dgier), [1] p15, [2] p15 */
-#define DGIER_GIE (1 << 31)
-
-/* IP Interrupt Status Register (ipisr), [1] p15, [2] p15 */
-#define IPISR_DRR_NOT_EMPTY (1 << 8)
-#define IPISR_SLAVE_SELECT (1 << 7)
-#define IPISR_TXF_HALF_EMPTY (1 << 6)
-#define IPISR_DRR_OVERRUN (1 << 5)
-#define IPISR_DRR_FULL (1 << 4)
-#define IPISR_DTR_UNDERRUN (1 << 3)
-#define IPISR_DTR_EMPTY (1 << 2)
-#define IPISR_SLAVE_MODF (1 << 1)
-#define IPISR_MODF (1 << 0)
-
-/* IP Interrupt Enable Register (ipier), [1] p17, [2] p18 */
-#define IPIER_DRR_NOT_EMPTY (1 << 8)
-#define IPIER_SLAVE_SELECT (1 << 7)
-#define IPIER_TXF_HALF_EMPTY (1 << 6)
-#define IPIER_DRR_OVERRUN (1 << 5)
-#define IPIER_DRR_FULL (1 << 4)
-#define IPIER_DTR_UNDERRUN (1 << 3)
-#define IPIER_DTR_EMPTY (1 << 2)
-#define IPIER_SLAVE_MODF (1 << 1)
-#define IPIER_MODF (1 << 0)
-
-/* Softare Reset Register (srr), [1] p9, [2] p8 */
-#define SRR_RESET_CODE 0x0000000A
-
-/* SPI Control Register (spicr), [1] p9, [2] p8 */
-#define SPICR_LSB_FIRST (1 << 9)
-#define SPICR_MASTER_INHIBIT (1 << 8)
-#define SPICR_MANUAL_SS (1 << 7)
-#define SPICR_RXFIFO_RESEST (1 << 6)
-#define SPICR_TXFIFO_RESEST (1 << 5)
-#define SPICR_CPHA (1 << 4)
-#define SPICR_CPOL (1 << 3)
-#define SPICR_MASTER_MODE (1 << 2)
-#define SPICR_SPE (1 << 1)
-#define SPICR_LOOP (1 << 0)
-
-/* SPI Status Register (spisr), [1] p11, [2] p10 */
-#define SPISR_SLAVE_MODE_SELECT (1 << 5)
-#define SPISR_MODF (1 << 4)
-#define SPISR_TX_FULL (1 << 3)
-#define SPISR_TX_EMPTY (1 << 2)
-#define SPISR_RX_FULL (1 << 1)
-#define SPISR_RX_EMPTY (1 << 0)
-
-/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
-#define SPIDTR_8BIT_MASK (0xff << 0)
-#define SPIDTR_16BIT_MASK (0xffff << 0)
-#define SPIDTR_32BIT_MASK (0xffffffff << 0)
-
-/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
-#define SPIDRR_8BIT_MASK (0xff << 0)
-#define SPIDRR_16BIT_MASK (0xffff << 0)
-#define SPIDRR_32BIT_MASK (0xffffffff << 0)
-
-/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
-#define SPISSR_MASK(cs) (1 << (cs))
-#define SPISSR_ACT(cs) ~SPISSR_MASK(cs)
-#define SPISSR_OFF ~0UL
-
-/* SPI Transmit FIFO Occupancy Register (spitfor), [1] p13, [2] p14 */
-#define SPITFOR_OCYVAL_POS 0
-#define SPITFOR_OCYVAL_MASK (0xf << SPITFOR_OCYVAL_POS)
-
-/* SPI Receive FIFO Occupancy Register (spirfor), [1] p14, [2] p14 */
-#define SPIRFOR_OCYVAL_POS 0
-#define SPIRFOR_OCYVAL_MASK (0xf << SPIRFOR_OCYVAL_POS)
-
-/* SPI Software Reset Register (ssr) */
-#define SPISSR_RESET_VALUE 0x0a
-
-struct xilinx_spi_slave {
- struct spi_slave slave;
- struct xilinx_spi_reg *regs;
- unsigned int freq;
- unsigned int mode;
-};
-
-static inline struct xilinx_spi_slave *to_xilinx_spi_slave(
- struct spi_slave *slave)
-{
- return container_of(slave, struct xilinx_spi_slave, slave);
-}
-
-#endif /* _XILINX_SPI_ */
/*
* (C) Copyright 2013 Inc.
+ * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
*
* Xilinx Zynq PS SPI controller driver (master mode only)
*
#include <config.h>
#include <common.h>
+#include <dm.h>
+#include <errno.h>
#include <malloc.h>
#include <spi.h>
+#include <fdtdec.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
#define ZYNQ_SPI_CR_MSA_MASK (1 << 15) /* Manual start enb */
#define ZYNQ_SPI_CR_MCS_MASK (1 << 14) /* Manual chip select */
u32 rxdr; /* 0x20 */
};
-/* zynq spi slave */
-struct zynq_spi_slave {
- struct spi_slave slave;
- struct zynq_spi_regs *base;
+
+/* zynq spi platform data */
+struct zynq_spi_platdata {
+ struct zynq_spi_regs *regs;
+ u32 frequency; /* input frequency */
+ u32 speed_hz;
+};
+
+/* zynq spi priv */
+struct zynq_spi_priv {
+ struct zynq_spi_regs *regs;
u8 mode;
u8 fifo_depth;
- u32 speed_hz;
- u32 input_hz;
- u32 req_hz;
+ u32 freq; /* required frequency */
};
-static inline struct zynq_spi_slave *to_zynq_spi_slave(struct spi_slave *slave)
+static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
{
- return container_of(slave, struct zynq_spi_slave, slave);
-}
+ struct zynq_spi_platdata *plat = bus->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = bus->of_offset;
-static inline struct zynq_spi_regs *get_zynq_spi_base(int dev)
-{
- if (dev)
- return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR1;
- else
- return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR0;
+ plat->regs = (struct zynq_spi_regs *)fdtdec_get_addr(blob, node, "reg");
+
+ /* FIXME: Use 250MHz as a suitable default */
+ plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+ 250000000);
+ plat->speed_hz = plat->frequency / 2;
+
+ debug("zynq_spi_ofdata_to_platdata: regs=%p max-frequency=%d\n",
+ plat->regs, plat->frequency);
+
+ return 0;
}
-static void zynq_spi_init_hw(struct zynq_spi_slave *zslave)
+static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
{
+ struct zynq_spi_regs *regs = priv->regs;
u32 confr;
/* Disable SPI */
- writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
+ writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
/* Disable Interrupts */
- writel(ZYNQ_SPI_IXR_ALL_MASK, &zslave->base->idr);
+ writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->idr);
/* Clear RX FIFO */
- while (readl(&zslave->base->isr) &
+ while (readl(®s->isr) &
ZYNQ_SPI_IXR_RXNEMPTY_MASK)
- readl(&zslave->base->rxdr);
+ readl(®s->rxdr);
/* Clear Interrupts */
- writel(ZYNQ_SPI_IXR_ALL_MASK, &zslave->base->isr);
+ writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->isr);
/* Manual slave select and Auto start */
confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
ZYNQ_SPI_CR_MSTREN_MASK;
confr &= ~ZYNQ_SPI_CR_MSA_MASK;
- writel(confr, &zslave->base->cr);
+ writel(confr, ®s->cr);
/* Enable SPI */
- writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
+ writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
}
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+static int zynq_spi_probe(struct udevice *bus)
{
- /* 2 bus with 3 chipselect */
- return bus < 2 && cs < 3;
+ struct zynq_spi_platdata *plat = dev_get_platdata(bus);
+ struct zynq_spi_priv *priv = dev_get_priv(bus);
+
+ priv->regs = plat->regs;
+ priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
+
+ /* init the zynq spi hw */
+ zynq_spi_init_hw(priv);
+
+ return 0;
}
-void spi_cs_activate(struct spi_slave *slave)
+static void spi_cs_activate(struct udevice *dev, uint cs)
{
- struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
+ struct udevice *bus = dev->parent;
+ struct zynq_spi_priv *priv = dev_get_priv(bus);
+ struct zynq_spi_regs *regs = priv->regs;
u32 cr;
- debug("spi_cs_activate: 0x%08x\n", (u32)slave);
-
- clrbits_le32(&zslave->base->cr, ZYNQ_SPI_CR_CS_MASK);
- cr = readl(&zslave->base->cr);
+ clrbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK);
+ cr = readl(®s->cr);
/*
* CS cal logic: CS[13:10]
* xxx0 - cs0
* xx01 - cs1
* x011 - cs2
*/
- cr |= (~(0x1 << slave->cs) << 10) & ZYNQ_SPI_CR_CS_MASK;
- writel(cr, &zslave->base->cr);
+ cr |= (~(0x1 << cs) << 10) & ZYNQ_SPI_CR_CS_MASK;
+ writel(cr, ®s->cr);
}
-void spi_cs_deactivate(struct spi_slave *slave)
+static void spi_cs_deactivate(struct udevice *dev)
{
- struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
-
- debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
+ struct udevice *bus = dev->parent;
+ struct zynq_spi_priv *priv = dev_get_priv(bus);
+ struct zynq_spi_regs *regs = priv->regs;
- setbits_le32(&zslave->base->cr, ZYNQ_SPI_CR_CS_MASK);
-}
-
-void spi_init()
-{
- /* nothing to do */
+ setbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK);
}
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static int zynq_spi_claim_bus(struct udevice *dev)
{
- struct zynq_spi_slave *zslave;
+ struct udevice *bus = dev->parent;
+ struct zynq_spi_priv *priv = dev_get_priv(bus);
+ struct zynq_spi_regs *regs = priv->regs;
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
+ writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
- zslave = spi_alloc_slave(struct zynq_spi_slave, bus, cs);
- if (!zslave) {
- printf("SPI_error: Fail to allocate zynq_spi_slave\n");
- return NULL;
- }
-
- zslave->base = get_zynq_spi_base(bus);
- zslave->mode = mode;
- zslave->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
- zslave->input_hz = 166666700;
- zslave->speed_hz = zslave->input_hz / 2;
- zslave->req_hz = max_hz;
-
- /* init the zynq spi hw */
- zynq_spi_init_hw(zslave);
-
- return &zslave->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
-
- debug("spi_free_slave: 0x%08x\n", (u32)slave);
- free(zslave);
+ return 0;
}
-int spi_claim_bus(struct spi_slave *slave)
+static int zynq_spi_release_bus(struct udevice *dev)
{
- struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
- u32 confr = 0;
- u8 baud_rate_val = 0;
+ struct udevice *bus = dev->parent;
+ struct zynq_spi_priv *priv = dev_get_priv(bus);
+ struct zynq_spi_regs *regs = priv->regs;
- writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
-
- /* Set the SPI Clock phase and polarities */
- confr = readl(&zslave->base->cr);
- confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
- if (zslave->mode & SPI_CPHA)
- confr |= ZYNQ_SPI_CR_CPHA_MASK;
- if (zslave->mode & SPI_CPOL)
- confr |= ZYNQ_SPI_CR_CPOL_MASK;
-
- /* Set the clock frequency */
- if (zslave->req_hz == 0) {
- /* Set baudrate x8, if the req_hz is 0 */
- baud_rate_val = 0x2;
- } else if (zslave->speed_hz != zslave->req_hz) {
- while ((baud_rate_val < 8) &&
- ((zslave->input_hz /
- (2 << baud_rate_val)) > zslave->req_hz))
- baud_rate_val++;
- zslave->speed_hz = zslave->req_hz / (2 << baud_rate_val);
- }
- confr &= ~ZYNQ_SPI_CR_BRD_MASK;
- confr |= (baud_rate_val << 3);
- writel(confr, &zslave->base->cr);
-
- writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
+ writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
return 0;
}
-void spi_release_bus(struct spi_slave *slave)
+static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
{
- struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
-
- debug("spi_release_bus: 0x%08x\n", (u32)slave);
- writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
-{
- struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
+ struct udevice *bus = dev->parent;
+ struct zynq_spi_priv *priv = dev_get_priv(bus);
+ struct zynq_spi_regs *regs = priv->regs;
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
u32 len = bitlen / 8;
u32 tx_len = len, rx_len = len, tx_tvl;
const u8 *tx_buf = dout;
u32 ts, status;
debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
- slave->bus, slave->cs, bitlen, len, flags);
+ bus->seq, slave_plat->cs, bitlen, len, flags);
if (bitlen % 8) {
debug("spi_xfer: Non byte aligned SPI transfer\n");
}
if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
+ spi_cs_activate(dev, slave_plat->cs);
while (rx_len > 0) {
/* Write the data into TX FIFO - tx threshold is fifo_depth */
tx_tvl = 0;
- while ((tx_tvl < zslave->fifo_depth) && tx_len) {
+ while ((tx_tvl < priv->fifo_depth) && tx_len) {
if (tx_buf)
buf = *tx_buf++;
else
buf = 0;
- writel(buf, &zslave->base->txdr);
+ writel(buf, ®s->txdr);
tx_len--;
tx_tvl++;
}
/* Check TX FIFO completion */
ts = get_timer(0);
- status = readl(&zslave->base->isr);
+ status = readl(®s->isr);
while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
printf("spi_xfer: Timeout! TX FIFO not full\n");
return -1;
}
- status = readl(&zslave->base->isr);
+ status = readl(®s->isr);
}
/* Read the data from RX FIFO */
- status = readl(&zslave->base->isr);
+ status = readl(®s->isr);
while (status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) {
- buf = readl(&zslave->base->rxdr);
+ buf = readl(®s->rxdr);
if (rx_buf)
*rx_buf++ = buf;
- status = readl(&zslave->base->isr);
+ status = readl(®s->isr);
rx_len--;
}
}
if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+ spi_cs_deactivate(dev);
return 0;
}
+
+static int zynq_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct zynq_spi_platdata *plat = bus->platdata;
+ struct zynq_spi_priv *priv = dev_get_priv(bus);
+ struct zynq_spi_regs *regs = priv->regs;
+ uint32_t confr;
+ u8 baud_rate_val = 0;
+
+ if (speed > plat->frequency)
+ speed = plat->frequency;
+
+ /* Set the clock frequency */
+ confr = readl(®s->cr);
+ if (speed == 0) {
+ /* Set baudrate x8, if the freq is 0 */
+ baud_rate_val = 0x2;
+ } else if (plat->speed_hz != speed) {
+ while ((baud_rate_val < 8) &&
+ ((plat->frequency /
+ (2 << baud_rate_val)) > speed))
+ baud_rate_val++;
+ plat->speed_hz = speed / (2 << baud_rate_val);
+ }
+ confr &= ~ZYNQ_SPI_CR_BRD_MASK;
+ confr |= (baud_rate_val << 3);
+
+ writel(confr, ®s->cr);
+ priv->freq = speed;
+
+ debug("zynq_spi_set_speed: regs=%p, mode=%d\n", priv->regs, priv->freq);
+
+ return 0;
+}
+
+static int zynq_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct zynq_spi_priv *priv = dev_get_priv(bus);
+ struct zynq_spi_regs *regs = priv->regs;
+ uint32_t confr;
+
+ /* Set the SPI Clock phase and polarities */
+ confr = readl(®s->cr);
+ confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
+
+ if (priv->mode & SPI_CPHA)
+ confr |= ZYNQ_SPI_CR_CPHA_MASK;
+ if (priv->mode & SPI_CPOL)
+ confr |= ZYNQ_SPI_CR_CPOL_MASK;
+
+ writel(confr, ®s->cr);
+ priv->mode = mode;
+
+ debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
+
+ return 0;
+}
+
+static const struct dm_spi_ops zynq_spi_ops = {
+ .claim_bus = zynq_spi_claim_bus,
+ .release_bus = zynq_spi_release_bus,
+ .xfer = zynq_spi_xfer,
+ .set_speed = zynq_spi_set_speed,
+ .set_mode = zynq_spi_set_mode,
+};
+
+static const struct udevice_id zynq_spi_ids[] = {
+ { .compatible = "xlnx,zynq-spi" },
+ { }
+};
+
+U_BOOT_DRIVER(zynq_spi) = {
+ .name = "zynq_spi",
+ .id = UCLASS_SPI,
+ .of_match = zynq_spi_ids,
+ .ops = &zynq_spi_ops,
+ .ofdata_to_platdata = zynq_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct zynq_spi_priv),
+ .probe = zynq_spi_probe,
+};
obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
obj-$(CONFIG_USB_DWC3_PHY_OMAP) += ti_usb_phy.o
+obj-$(CONFIG_USB_DWC3_PHY_SAMSUNG) += samsung_usb_phy.o
--- /dev/null
+/**
+ * samsung_usb_phy.c - DesignWare USB3 (DWC3) PHY handling file
+ *
+ * Copyright (C) 2015 Samsung Electronics
+ *
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/arch/power.h>
+#include <asm/arch/xhci-exynos.h>
+
+void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy)
+{
+ u32 reg;
+
+ /* Reset USB 3.0 PHY */
+ writel(0x0, &phy->phy_reg0);
+
+ clrbits_le32(&phy->phy_param0,
+ /* Select PHY CLK source */
+ PHYPARAM0_REF_USE_PAD |
+ /* Set Loss-of-Signal Detector sensitivity */
+ PHYPARAM0_REF_LOSLEVEL_MASK);
+ setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL);
+
+
+ writel(0x0, &phy->phy_resume);
+
+ /*
+ * Setting the Frame length Adj value[6:1] to default 0x20
+ * See xHCI 1.0 spec, 5.2.4
+ */
+ setbits_le32(&phy->link_system,
+ LINKSYSTEM_XHCI_VERSION_CONTROL |
+ LINKSYSTEM_FLADJ(0x20));
+
+ /* Set Tx De-Emphasis level */
+ clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK);
+ setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH);
+
+ setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL);
+
+ /* PHYTEST POWERDOWN Control */
+ clrbits_le32(&phy->phy_test,
+ PHYTEST_POWERDOWN_SSP |
+ PHYTEST_POWERDOWN_HSP);
+
+ /* UTMI Power Control */
+ writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi);
+
+ /* Use core clock from main PLL */
+ reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
+ /* Default 24Mhz crystal clock */
+ PHYCLKRST_FSEL(FSEL_CLKSEL_24M) |
+ PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0) |
+ /* Force PortReset of PHY */
+ PHYCLKRST_PORTRESET |
+ /* Digital power supply in normal operating mode */
+ PHYCLKRST_RETENABLEN |
+ /* Enable ref clock for SS function */
+ PHYCLKRST_REF_SSP_EN |
+ /* Enable spread spectrum */
+ PHYCLKRST_SSC_EN |
+ /* Power down HS Bias and PLL blocks in suspend mode */
+ PHYCLKRST_COMMONONN;
+
+ writel(reg, &phy->phy_clk_rst);
+
+ /* giving time to Phy clock to settle before resetting */
+ udelay(10);
+
+ reg &= ~PHYCLKRST_PORTRESET;
+ writel(reg, &phy->phy_clk_rst);
+}
if (common->thread_wakeup_needed)
break;
- if (++i == 50000) {
+ if (++i == 20000) {
busy_indicator();
i = 0;
k++;
break;
default:
printf("ERROR: wrong controller index!!\n");
- break;
+ return -EINVAL;
};
*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
struct int_queue {
int elementsize;
+ unsigned long pipe;
struct QH *first;
struct QH *current;
struct QH *last;
{
struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
struct int_queue *result = NULL;
- int i;
+ uint32_t i, toggle;
/*
* Interrupt transfers requiring several transactions are not supported
goto fail1;
}
result->elementsize = elementsize;
+ result->pipe = pipe;
result->first = memalign(USB_DMA_MINALIGN,
sizeof(struct QH) * queuesize);
if (!result->first) {
memset(result->first, 0, sizeof(struct QH) * queuesize);
memset(result->tds, 0, sizeof(struct qTD) * queuesize);
+ toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
+
for (i = 0; i < queuesize; i++) {
struct QH *qh = result->first + i;
struct qTD *td = result->tds + i;
td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
debug("communication direction is '%s'\n",
usb_pipein(pipe) ? "in" : "out");
- td->qt_token = cpu_to_hc32((elementsize << 16) |
+ td->qt_token = cpu_to_hc32(
+ QT_TOKEN_DT(toggle) |
+ (elementsize << 16) |
((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
0x80); /* active */
td->qt_buffer[0] =
cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
*buf = buffer + i * elementsize;
+ toggle ^= 1;
}
flush_dcache_range((unsigned long)buffer,
{
struct QH *cur = queue->current;
struct qTD *cur_td;
+ uint32_t token, toggle;
+ unsigned long pipe = queue->pipe;
/* depleted queue */
if (cur == NULL) {
cur_td = &queue->tds[queue->current - queue->first];
invalidate_dcache_range((unsigned long)cur_td,
ALIGN_END_ADDR(struct qTD, cur_td, 1));
- if (QT_TOKEN_GET_STATUS(hc32_to_cpu(cur_td->qt_token)) &
- QT_TOKEN_STATUS_ACTIVE) {
- debug("Exit poll_int_queue with no completed intr transfer. token is %x\n",
- hc32_to_cpu(cur_td->qt_token));
+ token = hc32_to_cpu(cur_td->qt_token);
+ if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) {
+ debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", token);
return NULL;
}
+
+ toggle = QT_TOKEN_GET_DT(token);
+ usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle);
+
if (!(cur->qh_link & QH_LINK_TERMINATE))
queue->current++;
else
queue->elementsize));
debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
- hc32_to_cpu(cur_td->qt_token), cur, queue->first);
+ token, cur, queue->first);
return cur->buffer;
}
musb_writel(base, USBC_REG_o_ISCR, reg_val);
}
-static void USBC_DisableIdPullUp(__iomem void *base)
-{
- u32 reg_val;
-
- reg_val = musb_readl(base, USBC_REG_o_ISCR);
- reg_val &= ~(1 << USBC_BP_ISCR_ID_PULLUP_EN);
- reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
- musb_writel(base, USBC_REG_o_ISCR, reg_val);
-}
-
static void USBC_EnableDpDmPullUp(__iomem void *base)
{
u32 reg_val;
musb_writel(base, USBC_REG_o_ISCR, reg_val);
}
-static void USBC_DisableDpDmPullUp(__iomem void *base)
+static void USBC_ForceIdToLow(__iomem void *base)
{
u32 reg_val;
reg_val = musb_readl(base, USBC_REG_o_ISCR);
- reg_val &= ~(1 << USBC_BP_ISCR_DPDM_PULLUP_EN);
+ reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
+ reg_val |= (0x02 << USBC_BP_ISCR_FORCE_ID);
reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
musb_writel(base, USBC_REG_o_ISCR, reg_val);
}
-static void USBC_ForceIdToLow(__iomem void *base)
+static void USBC_ForceIdToHigh(__iomem void *base)
{
u32 reg_val;
reg_val = musb_readl(base, USBC_REG_o_ISCR);
reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
- reg_val |= (0x02 << USBC_BP_ISCR_FORCE_ID);
+ reg_val |= (0x03 << USBC_BP_ISCR_FORCE_ID);
reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
musb_writel(base, USBC_REG_o_ISCR, reg_val);
}
-static void USBC_ForceIdToHigh(__iomem void *base)
+static void USBC_ForceVbusValidToLow(__iomem void *base)
{
u32 reg_val;
reg_val = musb_readl(base, USBC_REG_o_ISCR);
- reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
- reg_val |= (0x03 << USBC_BP_ISCR_FORCE_ID);
+ reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
+ reg_val |= (0x02 << USBC_BP_ISCR_FORCE_VBUS_VALID);
reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
musb_writel(base, USBC_REG_o_ISCR, reg_val);
}
return retval;
}
+/* musb_core does not call enable / disable in a balanced manner <sigh> */
+static bool enabled = false;
+
static void sunxi_musb_enable(struct musb *musb)
{
pr_debug("%s():\n", __func__);
+ if (enabled)
+ return;
+
/* select PIO mode */
musb_writeb(musb->mregs, USBC_REG_o_VEND0, 0);
- if (is_host_enabled(musb)) {
- /* port power on */
- sunxi_usb_phy_power_on(0);
- }
+ if (is_host_enabled(musb))
+ sunxi_usb_phy_power_on(0); /* port power on */
+
+ USBC_ForceVbusValidToHigh(musb->mregs);
+
+ enabled = true;
}
static void sunxi_musb_disable(struct musb *musb)
{
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
pr_debug("%s():\n", __func__);
- /* Put the controller back in a pristane state for "usb reset" */
- if (musb->is_active) {
- sunxi_usb_phy_exit(0);
-#ifdef CONFIG_SUNXI_GEN_SUN6I
- clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
-#endif
- clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+ if (!enabled)
+ return;
- mdelay(10);
+ if (is_host_enabled(musb))
+ sunxi_usb_phy_power_off(0); /* port power off */
- setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
-#ifdef CONFIG_SUNXI_GEN_SUN6I
- setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
-#endif
- sunxi_usb_phy_init(0);
- musb->is_active = 0;
- }
+ USBC_ForceVbusValidToLow(musb->mregs);
+ mdelay(200); /* Wait for the current session to timeout */
+
+ enabled = false;
}
static int sunxi_musb_init(struct musb *musb)
return 0;
}
-static int sunxi_musb_exit(struct musb *musb)
-{
- pr_debug("%s():\n", __func__);
-
- USBC_DisableDpDmPullUp(musb->mregs);
- USBC_DisableIdPullUp(musb->mregs);
- sunxi_usb_phy_power_off(0);
- sunxi_usb_phy_exit(0);
-
- return 0;
-}
-
const struct musb_platform_ops sunxi_musb_ops = {
.init = sunxi_musb_init,
- .exit = sunxi_musb_exit,
-
.enable = sunxi_musb_enable,
.disable = sunxi_musb_disable,
};
#define CONFIG_CMD_AMBAPP /* AMBA Plug & Play Bus print utility */
#define CONFIG_CMD_ASKENV /* ask for env variable */
-#define CONFIG_CMD_BDI /* bdinfo */
#define CONFIG_CMD_BEDBUG /* Include BedBug Debugger */
#define CONFIG_CMD_BMP /* BMP support */
-#define CONFIG_CMD_BOOTD /* bootd */
#define CONFIG_CMD_BOOTZ /* boot zImage */
#define CONFIG_CMD_BSP /* Board Specific functions */
#define CONFIG_CMD_CACHE /* icache, dcache */
#define CONFIG_CMD_CDP /* Cisco Discovery Protocol */
#define CONFIG_CMD_CLK /* Clock support */
-#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_DATE /* support for RTC, date/time...*/
#define CONFIG_CMD_DHCP /* DHCP Support */
#define CONFIG_CMD_DIAG /* Diagnostics */
#define CONFIG_CMD_DISPLAY /* Display support */
#define CONFIG_CMD_DOC /* Disk-On-Chip Support */
#define CONFIG_CMD_DTT /* Digital Therm and Thermostat */
-#define CONFIG_CMD_ECHO /* echo arguments */
-#define CONFIG_CMD_EDITENV /* editenv */
#define CONFIG_CMD_EEPROM /* EEPROM read/write support */
#define CONFIG_CMD_ELF /* ELF (VxWorks) load/boot cmd */
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_FDC /* Floppy Disk Support */
-#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_FUSE /* Device fuse support */
#define CONFIG_CMD_GETTIME /* Get time since boot */
#define CONFIG_CMD_HASH /* calculate hash / digest */
#define CONFIG_CMD_HWFLOW /* RTS/CTS hw flow control */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_IDE /* IDE harddisk support */
-#define CONFIG_CMD_IMI /* iminfo */
-#define CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_CMD_IMMAP /* IMMR dump support */
#define CONFIG_CMD_IO /* Access to X86 IO space */
#define CONFIG_CMD_IRQ /* irqinfo */
-#define CONFIG_CMD_ITEST /* Integer (and string) test */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_KGDB /* kgdb */
#define CONFIG_CMD_LICENSE /* console license display */
-#define CONFIG_CMD_LOADB /* loadb */
-#define CONFIG_CMD_LOADS /* loads */
#define CONFIG_CMD_MEMINFO /* meminfo */
-#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop */
#define CONFIG_CMD_MEMTEST /* mtest */
#define CONFIG_CMD_MFSL /* FSL support for Microblaze */
#define CONFIG_CMD_MII /* MII support */
-#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_MTDPARTS /* mtd parts support */
#define CONFIG_CMD_NAND /* NAND support */
-#define CONFIG_CMD_NFS /* NFS support */
#define CONFIG_CMD_ONENAND /* OneNAND support */
#define CONFIG_CMD_PCI /* pciinfo */
#define CONFIG_CMD_PCMCIA /* PCMCIA support */
#define CONFIG_CMD_REISER /* Reiserfs support */
#define CONFIG_CMD_RARP /* rarpboot support */
#define CONFIG_CMD_READ /* Read data from partition */
-#define CONFIG_CMD_RUN /* run command in env variable */
#define CONFIG_CMD_SANDBOX /* sb command to access sandbox features */
-#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_SAVES /* save S record dump */
#define CONFIG_CMD_SCSI /* SCSI Support */
#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
-#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
#define CONFIG_CMD_SNTP /* SNTP support */
-#define CONFIG_CMD_SOURCE /* "source" command support */
#define CONFIG_CMD_SPI /* SPI utility */
#define CONFIG_CMD_TERMINAL /* built-in Serial Terminal */
#define CONFIG_CMD_UBI /* UBI Support */
#define CONFIG_CMD_UNIVERSE /* Tundra Universe Support */
#define CONFIG_CMD_UNZIP /* unzip from memory to memory */
#define CONFIG_CMD_USB /* USB Support */
-#define CONFIG_CMD_XIMG /* Load part of Multi Image */
#define CONFIG_CMD_ZFS /* ZFS Support */
#endif /* _CONFIG_CMD_ALL_H */
+++ /dev/null
-/*
- * Copyright 2007 Freescale Semiconductor, Inc.
- *
- * This file is licensed under the terms of the GNU General Public
- * License Version 2. This file is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef _CONFIG_CMD_DEFAULT_H
-#define _CONFIG_CMD_DEFAULT_H
-
-/*
- * Alphabetical list of all commands that are configured by default.
- * This is essentially all commands minus those that are considered
- * "non-standard" for some reason (memory hogs, requires special
- * hardware, not fully tested, etc.).
- */
-
-#define CONFIG_CMD_BDI /* bdinfo */
-#define CONFIG_CMD_BOOTD /* bootd */
-#define CONFIG_CMD_CONSOLE /* coninfo */
-#define CONFIG_CMD_ECHO /* echo arguments */
-#define CONFIG_CMD_EDITENV /* editenv */
-#define CONFIG_CMD_ENV_EXISTS /* query whether env variables exists */
-#define CONFIG_CMD_FPGA /* FPGA configuration Support */
-#define CONFIG_CMD_IMI /* iminfo */
-#define CONFIG_CMD_ITEST /* Integer (and string) test */
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#define CONFIG_CMD_IMLS /* List all found images */
-#endif
-#define CONFIG_CMD_LOADB /* loadb */
-#define CONFIG_CMD_LOADS /* loads */
-#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop */
-#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
-#define CONFIG_CMD_NFS /* NFS support */
-#define CONFIG_CMD_RUN /* run command in env variable */
-#define CONFIG_CMD_SAVEENV /* saveenv */
-#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
-#define CONFIG_CMD_SOURCE /* "source" command support */
-#define CONFIG_CMD_XIMG /* Load part of Multi Image */
-
-#endif /* _CONFIG_CMD_DEFAULT_H */
* eSPI - Enhanced SPI
*/
#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SST
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_FSL_ESPI
/* eSPI - Enhanced SPI */
#ifdef CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_ELF
/* eSPI - Enhanced SPI */
#define CONFIG_FSL_ESPI /* SPI */
#ifdef CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
/* eSPI - Enhanced SPI */
#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SPI_FLASH_EON
#define CONFIG_CMD_SF
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ELF
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_NFS
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#undef CONFIG_SYS_LONGHELP /* undef to save memory */
#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_WATCHDOG_TIMEOUT 5000
/* Command line configuration */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
#undef CONFIG_CMD_I2C
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_BOOTP_HOSTNAME
/* Command line configuration */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-#undef CONFIG_CMD_NFS
#define CONFIG_CMD_REGINFO
#undef CONFIG_CMD_USB
#undef CONFIG_CMD_BMP
#define CONFIG_SYS_SBFHDR_SIZE 0x7
#ifdef CONFIG_CMD_SPI
# define CONFIG_SYS_DSPI_CS2
-# define CONFIG_SPI_FLASH
# define CONFIG_SPI_FLASH_STMICRO
# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
#define CONFIG_BOOTP_HOSTNAME
/* Command line configuration */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_SYS_LONGHELP /* undef to save memory */
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
#define CONFIG_CMD_PING
#ifdef CONFIG_CMD_IDE
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
/* ATA */
#define CONFIG_DOS_PARTITION
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
-#define CONFIG_CMD_MISC
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_MEMORY
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_LOADB
#define CONFIG_BOOTDELAY 5
#define CONFIG_MCFFEC
#define CONFIG_BOOTP_HOSTNAME
/* Available command configuration */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_DHCP
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_LOADB
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_LOADB
-
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII 1
#define CONFIG_WATCHDOG_TIMEOUT 5000
/* Command line configuration */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
#undef CONFIG_CMD_I2C
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* Command line configuration */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
/* Command line configuration */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_BOOTP_HOSTNAME
/* Command line configuration */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
-#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_I2C
#undef CONFIG_CMD_JFFS2
#undef CONFIG_CMD_UBI
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#undef CONFIG_CMD_NAND
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
/*
* NAND FLASH
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE 0x7
#ifdef CONFIG_CMD_SPI
-# define CONFIG_SPI_FLASH
# define CONFIG_SPI_FLASH_ATMEL
# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
#define CONFIG_BOOTP_HOSTNAME
/* Command line configuration */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#undef CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
/* Network configuration */
#define CONFIG_MCFFEC
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE 0x7
#ifdef CONFIG_CMD_SPI
-# define CONFIG_SPI_FLASH
# define CONFIG_SPI_FLASH_STMICRO
# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
#define CONFIG_BOOTP_HOSTNAME
/* Command line configuration */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#undef CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
/* Network configuration */
#define CONFIG_MCFFEC
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE 0x13
#ifdef CONFIG_CMD_SPI
-# define CONFIG_SPI_FLASH
# define CONFIG_SPI_FLASH_STMICRO
# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* Command line configuration */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* Command line configuration */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#ifdef CONFIG_MPC8XXX_SPI
#define CONFIG_CMD_SPI
#define CONFIG_USE_SPIFLASH
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#endif
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PCI
-#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PCI
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_EEPROM
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_PCI
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PCI
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_IRQ
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PCI
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PCI
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
-#undef CONFIG_CMD_SAVEENV
-#undef CONFIG_CMD_LOADS
-#endif
-
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_MPC8536DS 1
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
-#define CONFIG_SPI_FLASH 1 /* Has SPI Flash */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI1 1 /* Enable PCI controller 1 */
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_ELF
#define CONFIG_CMD_PCI
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_ELF
#define CONFIG_CMD_MII
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PING
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
-#if defined(CONFIG_SYS_RAMBOOT)
-#undef CONFIG_CMD_SAVEENV
-#endif
-
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SCSI
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_REGINFO
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
-#endif
-
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SCSI
#define CONFIG_CPU_SH7722 1
#define CONFIG_MIGO_R 1
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_PING
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SAVEENV
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
/* eSPI - Enhanced SPI */
#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_ELF
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_HARD_SPI
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ELF
#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_IRQ
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
* eSPI - Enhanced SPI
*/
#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_ERRATA
/*
* Command line configuration.
*/
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_LOADB
#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_RUN
#define CONFIG_CMD_BSP
-#define CONFIG_CMD_IMI
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MISC
#if 0
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_IDE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_BSP
#define CONFIG_CMD_CHIP_CONFIG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
* eSPI - Enhanced SPI
*/
#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SPI_FLASH_SST
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
* eSPI - Enhanced SPI
*/
#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
#if defined(CONFIG_T1024RDB)
#define CONFIG_SPI_FLASH_STMICRO
#elif defined(CONFIG_T1023RDB)
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
-#define CONFIG_CMD_ECHO
#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_BDI
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
* eSPI - Enhanced SPI
*/
#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_SST
#define CONFIG_SPI_FLASH_EON
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
* eSPI - Enhanced SPI
*/
#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_BAR
#define CONFIG_CMD_SF
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#ifdef CONFIG_T1042RDB_PI
#define CONFIG_CMD_DATE
#endif
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#define CONFIG_MMC
-#define CONFIG_SPI_FLASH
#define CONFIG_USB_EHCI
#if defined(CONFIG_PPC_T2080)
#define CONFIG_T2080QDS
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_BDI
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#define CONFIG_T2080RDB
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#define CONFIG_MMC
-#define CONFIG_SPI_FLASH
#define CONFIG_USB_EHCI
#define CONFIG_FSL_SATA_V2
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_MII
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING
-#define CONFIG_CMD_ECHO
#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_BDI
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
* eSPI - Enhanced SPI
*/
#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SST
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_ERRATA
* eSPI - Enhanced SPI
*/
#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SST
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#ifdef CONFIG_SPLASH_SCREEN
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_PCI
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
/*
* Miscellaneous configurable options
*/
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_ETHPRIME "eTSEC3"
#ifndef CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH y
#endif
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ETHPRIME "eTSEC1"
#ifndef CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH y
#endif
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_BSP
#define CONFIG_CMD_IRQ
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_BSP
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_MII
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
#define CONFIG_CMD_MII
#define CONFIG_LOADS_ECHO 1
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#undef CONFIG_CMD_EXT2
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PING
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PING
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PING
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
/*
* PCI
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_I2C
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
-#undef CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#undef CONFIG_WATCHDOG /* watchdog disabled */
/* FLASH */
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SPI_FLASH_QUAD
#define CONFIG_SYS_NO_FLASH
"${optargs} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
- "nandroot=ubi0:rootfs rw ubi.mtd=9,2048\0" \
+ "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \
"nandrootfstype=ubifs rootwait=1\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
- "nand read ${fdtaddr} u-boot-spl-os; " \
- "nand read ${loadaddr} kernel; " \
+ "nand read ${fdtaddr} NAND.u-boot-spl-os; " \
+ "nand read ${loadaddr} NAND.kernel; " \
"bootz ${loadaddr} - ${fdtaddr}\0"
#else
#define NANDARGS ""
"128k(NAND.u-boot-env)," \
"128k(NAND.u-boot-env.backup1)," \
"8m(NAND.kernel)," \
- "-(NAND.rootfs)"
+ "-(NAND.file-system)"
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
#undef CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_IN_NAND
/* SPI flash. */
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_SPEED 24000000
*/
#if defined(CONFIG_NOR)
#undef CONFIG_SYS_NO_FLASH
-#define CONFIG_CMD_FLASH
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_CFI
#endif /* CONFIG_USB_AM35X */
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_DHCP
#undef CONFIG_CMD_PING
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
-#undef CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_SYS_I2C_OMAP34XX
-#undef CONFIG_CMD_NFS
/*
* Board NAND Info.
*/
#endif /* CONFIG_USB_MUSB_AM35X */
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_DHCP
#undef CONFIG_CMD_PING
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
-#undef CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_AM43XX
#define CONFIG_CMD_FAT
-#define CONFIG_CMD_SAVEENV
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_CACHELINE_SIZE 32
-#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
+#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
#define CONFIG_POWER_TPS62362
/* SPL defines. */
+#ifdef CONFIG_SPL_USB_HOST_SUPPORT
+/*
+ * For USB host boot, ROM uses DMA for copying MLO from USB storage
+ * and ARM internal ram is not accessible for DMA, so SPL text base
+ * should be in OCMC ram
+ */
#define CONFIG_SPL_TEXT_BASE 0x40300350
+#else
+#define CONFIG_SPL_TEXT_BASE 0x402F4000
+#endif
#define CONFIG_SPL_MAX_SIZE (220 << 10) /* 220KB */
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 << 20))
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
/* SPL USB Support */
+#ifdef CONFIG_SPL_USB_HOST_SUPPORT
#define CONFIG_SPL_USB_SUPPORT
-#define CONFIG_SPL_USB_HOST_SUPPORT
#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
#define CONFIG_CMD_USB
#define CONFIG_OMAP_USB_PHY
#define CONFIG_AM437X_USB2PHY2_HOST
+#endif
/* USB GADGET */
#if !defined(CONFIG_SPL_BUILD) || \
/* SPI */
#undef CONFIG_OMAP3_SPI
#define CONFIG_TI_QSPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_MACRONIX
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_TI_SPI_MMAP
-#define CONFIG_SPI_FLASH_BAR
#define CONFIG_QSPI_SEL_GPIO 48
#define CONFIG_SF_DEFAULT_SPEED 48000000
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
"setenv fdtfile am437x-idk-evm.dtb; fi; " \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree; fi; \0" \
+ NANDARGS \
NETARGS \
DFUARGS \
#define CONFIG_BOOTCOMMAND \
"run findfdt; " \
"run mmcboot;" \
- "run usbboot;"
+ "run usbboot;" \
+ NANDBOOT \
#endif
+#ifndef CONFIG_SPL_BUILD
/* CPSW Ethernet */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
-#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_PHY_GIGE
+#endif
+
+#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_PHYLIB
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NET_VCI_STRING "AM43xx U-Boot SPL"
-#define CONFIG_SPL_ETH_SUPPORT
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ETH_SUPPORT)
+#undef CONFIG_ENV_IS_IN_FAT
+#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SPL_NET_SUPPORT
+#endif
+
#define CONFIG_SYS_RX_ETH_BUFFER 64
/* NAND support */
"256k(NAND.u-boot-env)," \
"256k(NAND.u-boot-env.backup1)," \
"7m(NAND.kernel)," \
- "-(NAND.rootfs)"
+ "-(NAND.file-system)"
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00180000
/* NAND: SPL related configs */
#ifdef CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00300000 /* kernel offset */
#define CONFIG_CMD_SPL_WRITE_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#endif
-#endif /* !CONFIG_NAND */
+#define NANDARGS \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,4096\0" \
+ "nandrootfstype=ubifs rootwait=1\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${fdtaddr} NAND.u-boot-spl-os; " \
+ "nand read ${loadaddr} NAND.kernel; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0"
+#define NANDBOOT "run nandboot; "
+#else /* !CONFIG_NAND */
+#define NANDARGS
+#define NANDBOOT
+#endif /* CONFIG_NAND */
#endif /* __CONFIG_AM43XX_EVM_H */
/*
* Commands
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#if defined(CONFIG_440)
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_BOOTDELAY 1
#define CONFIG_BOOTCOMMAND "bootm ffc20000"
-#include <config_cmd_default.h>
#undef CONFIG_CMD_AES
-#undef CONFIG_CMD_BOOTD
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_XIMG
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_TIMER
#define CONFIG_CMD_DIAG
#define CONFIG_CPU_SH7723 1
#define CONFIG_AP325RXA 1
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_PING
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_IDE
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_TEXT_BASE 0x8BFC0000
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_SAVEENV
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
/*
* Enable the call to miscellaneous platform dependent initialization.
*/
-#define CONFIG_SYS_NO_FLASH /* to be define before <config_cmd_default.h> */
+#define CONFIG_SYS_NO_FLASH
/*
* Board display option
/*
* U-Boot Commands
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV /* ask for env variable */
#define CONFIG_CMD_BSP /* Board Specific functions */
#define CONFIG_CMD_CACHE /* icache, dcache */
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK
#define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_NFS /* NFS support */
#define CONFIG_CMD_PING /* ping support */
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_USB
/* Memory configuration */
/*
* Command line configuration
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ELF
#define CONFIG_OF_LIBFDT
#define CONFIG_LOADS_ECHO 1
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#undef CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_PHY_MICREL
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_MTD
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MXC_SPI
#include <asm/arch/rmobile.h>
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_LOADS
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_BOOTZ
#define CONFIG_OF_LIBFDT
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
#define CONFIG_CMD_I2C
-#undef CONFIG_CMD_NFS
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
#define CONFIG_ASTRO5373L /* define board type */
/* Command line configuration */
-#include <config_cmd_default.h>
-
/*
* CONFIG_RAM defines if u-boot is loaded via BDM (or started from
* a different bootloader that has already performed RAM setup) or
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_XIMG
-#undef CONFIG_CMD_NFS
#if ENABLE_JFFS
#define CONFIG_CMD_JFFS2
#endif
#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMDLINE_EDITING
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_FAT
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
-#undef CONFIG_CMD_FPGA
/*
* Network Driver Setting
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_SOURCE
-
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
#define CONFIG_CMD_NAND 1
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_SOURCE
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NAND
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_SOURCE
-
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
#define CONFIG_CMD_NAND 1
/* No NOR flash */
#define CONFIG_SYS_NO_FLASH
-
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NAND
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_FPGA
-
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
/* DataFlash */
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_ENV_SPI_MODE SPI_MODE_3
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_SOURCE
#undef CONFIG_CMD_USB
#define CONFIG_CMD_NAND 1
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NAND
/* DataFlash */
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SF_DEFAULT_SPEED 30000000
#endif
#define CONFIG_AT32AP7000
#define CONFIG_ATNGW100
-#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_SOURCE
-#undef CONFIG_CMD_XIMG
#define CONFIG_ATMEL_USART
#define CONFIG_MACB
#define CONFIG_GENERIC_MMC
#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SYS_DCACHE_LINESZ 32
#define CONFIG_AT32AP7000
#define CONFIG_ATNGW100MKII
-#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_SPI
#define CONFIG_CMD_MII
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_XIMG
#define CONFIG_ATMEL_USART
#define CONFIG_MACB
#define CONFIG_GENERIC_MMC
#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SYS_DCACHE_LINESZ 32
#define CONFIG_BOOTP_GATEWAY
/* generic board */
-#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MMC
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_SOURCE
-#undef CONFIG_CMD_XIMG
#define CONFIG_ATMEL_USART
#define CONFIG_MACB
/*
* Command line configuration
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
/*
* Bootloader Components Configuration
*/
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_ENV
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_USB
-#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#undef CONFIG_LCD
--- /dev/null
+/*
+ * am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_BALTOS_H
+#define __CONFIG_BALTOS_H
+
+#include <configs/ti_am335x_common.h>
+
+#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
+#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
+#define CONFIG_BOARD_LATE_INIT
+
+/* Clock Defines */
+#define V_OSCK 24000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+/* Custom script for NOR */
+#define CONFIG_SYS_LDSCRIPT "board/vscom/baltos/u-boot.lds"
+
+/* Always 128 KiB env size */
+#define CONFIG_ENV_SIZE (128 << 10)
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
+/* FIT support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
+#define CONFIG_OF_BOARD_SETUP
+
+/* UBI Support */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+
+/* I2C configuration */
+#undef CONFIG_SYS_OMAP24_I2C_SPEED
+#define CONFIG_SYS_OMAP24_I2C_SPEED 10000
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
+#define NANDARGS \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "${mtdparts} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "nandroot=ubi0:rootfs rw ubi.mtd=5\0" \
+ "nandrootfstype=ubifs rootwait=1\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "setenv loadaddr 0x84000000; " \
+ "ubi part UBI; " \
+ "ubifsmount ubi0:kernel; " \
+ "ubifsload $loadaddr kernel-fit.itb;" \
+ "ubifsumount; " \
+ "bootm ${loadaddr}#conf${board_name}\0"
+#else
+#define NANDARGS ""
+#endif
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ DEFAULT_LINUX_BOOT_ENV \
+ "boot_fdt=try\0" \
+ "bootpart=0:2\0" \
+ "bootdir=/boot\0" \
+ "bootfile=zImage\0" \
+ "fdtfile=undefined\0" \
+ "console=ttyO0,115200n8\0" \
+ "partitions=" \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
+ "optargs=\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 ro\0" \
+ "mmcrootfstype=ext4 rootwait\0" \
+ "rootpath=/export/rootfs\0" \
+ "nfsopts=nolock\0" \
+ "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
+ "::off\0" \
+ "ramroot=/dev/ram0 rw\0" \
+ "ramrootfstype=ext2\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "${mtdparts} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "spiroot=/dev/mtdblock4 rw\0" \
+ "spirootfstype=jffs2\0" \
+ "spisrcaddr=0xe0000\0" \
+ "spiimgsize=0x362000\0" \
+ "spibusno=0\0" \
+ "spiargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${spiroot} " \
+ "rootfstype=${spirootfstype}\0" \
+ "netargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=/dev/nfs " \
+ "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
+ "ip=dhcp\0" \
+ "bootenv=uEnv.txt\0" \
+ "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
+ "ramargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${ramroot} " \
+ "rootfstype=${ramrootfstype}\0" \
+ "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+ "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+ "mmcloados=run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdtaddr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "mmcboot=mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "echo Loaded environment from ${bootenv};" \
+ "run importbootenv;" \
+ "fi;" \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loadimage; then " \
+ "run mmcloados;" \
+ "fi;" \
+ "fi;\0" \
+ "spiboot=echo Booting from spi ...; " \
+ "run spiargs; " \
+ "sf probe ${spibusno}:0; " \
+ "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \
+ "bootz ${loadaddr}\0" \
+ "netboot=echo Booting from network ...; " \
+ "setenv autoload no; " \
+ "dhcp; " \
+ "tftp ${loadaddr} ${bootfile}; " \
+ "tftp ${fdtaddr} ${fdtfile}; " \
+ "run netargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+ "ramboot=echo Booting from ramdisk ...; " \
+ "run ramargs; " \
+ "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
+ "findfdt=setenv fdtfile am335x-baltos.dtb\0" \
+ NANDARGS
+ /*DFUARGS*/
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+ "run findfdt; " \
+ "run mmcboot;" \
+ "setenv mmcdev 1; " \
+ "setenv bootpart 1:2; " \
+ "run mmcboot;" \
+ "run nandboot;"
+
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
+#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
+#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
+#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
+#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+/* PMIC support */
+#define CONFIG_POWER_TPS65910
+
+/* SPL */
+#ifndef CONFIG_NOR_BOOT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+/* Bootcount using the RTC block */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_AM33XX
+
+/* USB gadget RNDIS */
+/*#define CONFIG_SPL_MUSB_NEW_SUPPORT*/
+
+/* General network SPL, both CPSW and USB gadget RNDIS */
+/*#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"*/
+
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#ifdef CONFIG_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ 34, 35, 36, 37, 38, 39, 40, 41, \
+ 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#endif
+#endif
+
+/*
+ * USB configuration. We enable MUSB support, both for host and for
+ * gadget. We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each. Then for host we
+ * add mass storage support and for gadget we add both RNDIS ethernet
+ * and DFU.
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_GADGET
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_USB_GADGET
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif
+
+#ifdef CONFIG_MUSB_GADGET
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
+
+/* USB TI's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x0403
+#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
+#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
+#endif /* CONFIG_MUSB_GADGET */
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
+/* disable host part of MUSB in SPL */
+#undef CONFIG_MUSB_HOST
+/* disable EFI partitions and partition UUID support */
+#undef CONFIG_PARTITION_UUIDS
+#undef CONFIG_EFI_PARTITION
+/*
+ * Disable CPSW SPL support so we fit within the 101KiB limit.
+ */
+#undef CONFIG_SPL_ETH_SUPPORT
+#endif
+
+/* Network. */
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR 0
+#define CONFIG_PHY_SMSC
+#define CONFIG_MII
+#define CONFIG_CMD_MII
+#define CONFIG_PHY_ATHEROS
+
+/* NAND support */
+#ifdef CONFIG_NAND
+#define CONFIG_CMD_NAND
+#define GPMC_NAND_ECC_LP_x8_LAYOUT 1
+#if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT)
+#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \
+ "128k(SPL.backup1)," \
+ "128k(SPL.backup2)," \
+ "128k(SPL.backup3)," \
+ "1920k(u-boot)," \
+ "-(UBI)"
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#endif
+
+#endif /* ! __CONFIG_BALTOS_H */
/* SPI flash. */
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_SPEED 24000000
*/
#if defined(CONFIG_NOR)
#undef CONFIG_SYS_NO_FLASH
-#define CONFIG_CMD_FLASH
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
/* No mtest functions as recommended */
-#undef CONFIG_CMD_MEMORY
/*
* This is the initial SP which is used only briefly for relocating the u-boot
#define CONFIG_BOOTCOMMAND ""
/* Commands */
-#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_BOOTZ
#define CONFIG_FAT_WRITE
-#undef CONFIG_CMD_NFS
#endif /* __BCM28155_AP_H */
/* Some commands use this as the default load address */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
-/* No mtest functions as recommended */
-#undef CONFIG_CMD_MEMORY
-
/*
* This is the initial SP which is used only briefly for relocating the u-boot
* image to the top of SDRAM. After relocation u-boot moves the stack to the
#define CONFIG_MX_CYCLIC
/* Commands */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_FAT
#define CONFIG_AM57XX
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_IODELAY_RECALIBRATION
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_ENV_SIZE (64 << 10)
#define FAT_ENV_DEVICE_AND_PART "0:1"
#define FAT_ENV_FILE "uboot.env"
-#define CONFIG_CMD_SAVEENV
-
#define CONSOLEDEV "ttyO2"
#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
#define CONFIG_EFI_PARTITION
/* CPSW Ethernet */
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_DHCP
#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
#define CONFIG_BOOTP_DNS2
/* SPI */
#define CONFIG_TEGRA20_SLINK
#define CONFIG_TEGRA_SLINK_CTRLS 6
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 71
-#define CONFIG_CMD_FLASH
#define CONFIG_MONITOR_IS_IN_RAM
*/
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
/*
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_BAUDRATE 115200
#define CONFIG_BFIN_SERIAL
-#define CONFIG_CMD_MEMORY
#undef CONFIG_GZIP
#undef CONFIG_ZLIB
#undef CONFIG_BOOTM_RTEMS
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SST
#define CONFIG_SPI_FLASH_STMICRO
/* support for serial flash */
#define CONFIG_BFIN_SPI
-#define CONFIG_SPI_FLASH
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_HZ 30000000
#define CONFIG_SPI_FLASH_EON
"sf read 0x1000000 0x20000 0x300000;" \
"bootm 0x1000000\0"
-/* this sets up the default list of enabled commands */
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_IMLS
-
#endif
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SST
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ALL
#define CONFIG_ENV_SPI_MAX_HZ 30000000
/*
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ALL
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
# define CONFIG_BOOTDELAY 5
#endif
-#include <config_cmd_default.h>
-
#ifdef CONFIG_BFIN_MAC
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_PING
-#else
-# undef CONFIG_CMD_NFS
#endif
#define CONFIG_CMD_BOOTLDR
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
-#undef CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_SF
#define CONFIG_BOOTCOMMAND "run ramboot"
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
# define CONFIG_BOOTDELAY 5
#endif
-#include <config_cmd_default.h>
-
#ifdef CONFIG_BFIN_MAC
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_PING
-#else
-# undef CONFIG_CMD_NFS
#endif
#define CONFIG_CMD_BOOTLDR
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
-#undef CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_SF
#define CONFIG_BOOTCOMMAND "run flashboot"
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ALL
#define CONFIG_ENV_SPI_MAX_HZ 30000000
/*
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ALL
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_SF_DEFAULT_SPEED 10000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ATMEL
* Env Storage Settings
*/
#define CONFIG_ENV_IS_IN_SPI_FLASH
-/* #define CONFIG_CMD_SAVEENV */
#define CONFIG_ENV_SECT_SIZE (1056 * 8)
#define CONFIG_ENV_OFFSET ((16 + 256) * 1056)
#define CONFIG_ENV_SIZE (8 * 1056)
/*
* Flash Settings
*/
-#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_JFFS2
#define CONFIG_SYS_FLASH_CFI_WIDTH 2
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_BFIN_SPI6XX
#define CONFIG_ENV_SPI_MAX_HZ 25000000
#define CONFIG_SF_DEFAULT_SPEED 25000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ALL
/*
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_UART_CONSOLE 0
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_SOFTSWITCH
#define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 20*1024*1024 + 4)
* Command Settings
*/
#ifndef _CONFIG_CMD_DEFAULT_H
-# include <config_cmd_default.h>
# ifdef ADI_CMDS_NETWORK
# define CONFIG_CMD_DHCP
# define CONFIG_BOOTP_SUBNETMASK
# ifdef CONFIG_BFIN_MAC
# define CONFIG_CMD_MII
# endif
-# else
-# undef CONFIG_CMD_BOOTD
-# undef CONFIG_CMD_NFS
# endif
# ifdef CONFIG_LIBATA
# define CONFIG_CMD_FAT
# define CONFIG_CMD_I2C
# define CONFIG_SOFT_I2C_READ_REPEATED_START
# endif
-# ifdef CONFIG_SYS_NO_FLASH
-# undef CONFIG_CMD_FLASH
-# undef CONFIG_CMD_IMLS
-# else
+# ifndef CONFIG_SYS_NO_FLASH
# define CONFIG_CMD_JFFS2
# endif
# ifdef CONFIG_CMD_JFFS2
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
/* SPI FLASH */
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SF_DEFAULT_BUS 2
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_AUTO_COMPLETE 1
#define CONFIG_ENV_OVERWRITE 1
-#include <config_cmd_default.h>
-
#ifdef CONFIG_SMC91111
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_PING
/* For the M25P64 SCK Should be Kept < 15Mhz */
#define CONFIG_ENV_SPI_MAX_HZ 15000000
#define CONFIG_SF_DEFAULT_SPEED 15000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
/*
* hardware don't support Parallel Flash at all.
*/
#define CONFIG_SYS_NO_FLASH
-#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_FLASH
#endif
#define CONFIG_ENV_SPI_MAX_HZ 15000000
#define CONFIG_SF_DEFAULT_SPEED 15000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
/*
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_AUTO_COMPLETE 1
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_BOOTLDR
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_CPLBINFO
* No Parallel Flash on this board
*/
#define CONFIG_SYS_NO_FLASH
-#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_FLASH
#endif
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
sizeof(CONFIG_SYS_PROMPT) + 16)
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/*
- * For commands to use, we take the default list and add a few other
- * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH
- * prior to this include, in order to skip a few commands. When we do
- * have flash, if we expect these commands they must be enabled in that
- * config. If desired, a specific list of desired commands can be used
- * instead.
- */
-#include <config_cmd_default.h>
-/* undefine commands, which we do not need */
-#undef CONFIG_CMD_EDITENV
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_ITEST
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_XIMG
-/* define command we need always */
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_SOURCE
/*
* Our platforms make use of SPL to initalize the hardware (primarily
/*
* U-Boot commands
*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_ENV
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_GPIO
#ifndef CONFIG_DRIVER_TI_EMAC
/* SPI support */
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_MMC_MBLOCK
/* U-Boot command configuration */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BDI
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP
/* SPI */
#define CONFIG_TEGRA20_SLINK
#define CONFIG_TEGRA_SLINK_CTRLS 6
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
/*
* Supported commands
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP
/* CMD */
#define CONFIG_CMD_GREPENV
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_XIMG
-#undef CONFIG_CMD_FPGA
/* MMC */
#define CONFIG_SYS_FSL_USDHC_NUM 3
/* SPI */
#define CONFIG_SPI
#define CONFIG_MXC_SPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SPI_FLASH_EON
#define CONFIG_SPI_FLASH_GIGADEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_CMD_USB
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_PING
#define CONFIG_CMD_GPIO
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_CMD_SAVEENV
/* Enhance our eMMC support / experience. */
#define CONFIG_HSMMC2_8BIT
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_NFS
-
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_LOADB
#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_LOADS
#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_IMI
#if 0
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_MII
#ifdef CONFIG_MCFFEC
/*
* Bootloader Components Configuration
*/
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_LOADB /* Both together */
-#undef CONFIG_CMD_LOADS /* saves 10 KB */
#define CONFIG_CMD_ENV
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_MMC
#define CONFIG_CMD_USB
-#define CONFIG_CMD_FLASH
/*
* Networking Configuration
#define CONFIG_ENV_SIZE (SZ_64K)
/* Debug commands */
-#define CONFIG_CMD_BDI
#define CONFIG_CMD_CACHE
/* Miscellaneous commands */
#define __CONFIG_H
#include <asm/arch/imx-regs.h>
-#include <config_cmd_default.h>
#define CONFIG_VF610
#define CONFIG_SYS_THUMB_BUILD
"512k(u-boot-env)," \
"-(ubi)"
-#undef CONFIG_CMD_IMLS
#define CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_HARD_SPI
#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_CMD_SF
#if defined(CONFIG_TRAILBLAZER)
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
-#undef CONFIG_CMD_SAVEENV
#elif defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#include <config_cmd_default.h>
-
#ifndef CONFIG_TRAILBLAZER
#define CONFIG_CMD_ELF
* eSPI - Enhanced SPI
*/
#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_ERRATA
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NAND
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_IMLS
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NAND
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_USB
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_DHCP
#ifdef CONFIG_SYS_I2C_SOFT
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_ELF
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_ELF
#define CONFIG_ENV_SECT_SIZE 4096
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE
/*
* U-Boot commands
*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_ENV
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_MEMORY
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif
#ifdef CONFIG_USE_NAND
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#endif
#ifdef CONFIG_USE_SPIFLASH
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_FLASH
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
-#define CONFIG_CMD_SAVEENV
#endif
/* SD/MMC configuration */
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_SIZE (16 << 10)
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_ENV
#endif
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_CMD_SF
/*
* U-Boot commands
*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_ENV
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_MEMORY
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif
#ifdef CONFIG_USE_NAND
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_MTDPARTS
#endif
#ifdef CONFIG_USE_SPIFLASH
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_FLASH
#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SAVEENV
#endif
#if !defined(CONFIG_USE_NAND) && \
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_SIZE (16 << 10)
-#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_ENV
#endif
/* SPI */
#define CONFIG_TEGRA114_SPI
#define CONFIG_TEGRA114_SPI_CTRLS 6
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
/* NYET -- #define CONFIG_USB_DAVINCI */
/* U-Boot command configuration */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* U-Boot command configuration */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#endif /* CONFIG_MUSB_UDC */
/* U-Boot command configuration */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
"root=/dev/hda1 rw noinitrd ip=dhcp"
/* U-Boot commands */
-#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_I2C
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
#ifdef CONFIG_SYS_USE_NAND
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND
#endif
/*=================*/
/* U-Boot commands */
/*=================*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_BDI
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
#ifdef CONFIG_SYS_USE_NAND
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND
#elif defined(CONFIG_SYS_USE_NOR)
#define CONFIG_CMD_JFFS2
/*=================*/
/* U-Boot commands */
/*=================*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_NAND
#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
"nand read 87A00000 100000 300000;" \
"bootelf 87A00000"
/* U-Boot commands */
-#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_NAND
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF /* Needed to load Integrity kernel. */
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
/*=================*/
/* U-Boot commands */
/*=================*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
#ifdef CONFIG_SYS_USE_NAND
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND
#elif defined(CONFIG_SYS_USE_NOR)
#define CONFIG_CMD_JFFS2
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x10000000\0" \
+ "initrd_high=0x10000000\0"
+
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_I2C
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_BEDBUG
#undef CONFIG_CMD_ELF
-#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_FAT
-#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_RUN
-
#ifdef CONFIG_DBAU1550
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_LOADB
-
#undef CONFIG_CMD_I2C
#undef CONFIG_CMD_IDE
-#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_PCMCIA
#else
#define CONFIG_CMD_IDE
#define CONFIG_CMD_DHCP
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
-
#endif
/*
* NOR Flash
*/
-#define CONFIG_CMD_FLASH
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 71
#define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE
/*
* U-Boot Commands
*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
/*
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_SPI
#undef CONFIG_CMD_GPIO
#undef CONFIG_CMD_ASKENV
#define CONFIG_LZO
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_UBI /* UBI Support */
#define CONFIG_CMD_UBIFS /* UBIFS Support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_NAND /* NAND support */
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
-#undef CONFIG_CMD_IMLS /* List all found images */
-#undef CONFIG_CMD_NFS /* NFS support */
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#ifdef CONFIG_VIDEO
#define CONFIG_CMD_BMP
#endif
#undef CONFIG_CMD_ELF
#undef CONFIG_CMD_I2C
#undef CONFIG_CMD_IRQ
-#undef CONFIG_CMD_NFS
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
#undef CONFIG_CMD_ELF
#undef CONFIG_CMD_I2C
#undef CONFIG_CMD_IRQ
-#undef CONFIG_CMD_NFS
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
"cp.b 0x01000000 0x20030000 0x2c0000\0" \
"runme=bootm 0x01000000\0"
-/* this sets up the default list of enabled commands */
-#include <config_cmd_default.h>
-
-#ifndef CONFIG_BFIN_MAC
-# undef CONFIG_CMD_NFS
-#endif
-
#endif
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_NAND
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_MII
#define CONFIG_DRA7XX
#define CONFIG_BOARD_EARLY_INIT_F
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_IODELAY_RECALIBRATION
+#endif
+
#ifndef CONFIG_QSPI_BOOT
/* MMC ENV related defines */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#endif
-#define CONFIG_CMD_SAVEENV
#if (CONFIG_CONS_INDEX == 1)
#define CONSOLEDEV "ttyO0"
#define CONFIG_SYS_OMAP_ABE_SYSCK
+#ifndef CONFIG_SPL_BUILD
/* Define the default GPT table for eMMC */
#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \
#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x2F000000
#define CONFIG_FASTBOOT_FLASH
#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#endif
#include <configs/ti_omap5_common.h>
/* SPI */
#undef CONFIG_OMAP3_SPI
#define CONFIG_TI_QSPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH_BAR
#define CONFIG_TI_SPI_MMAP
#define CONFIG_SF_DEFAULT_SPEED 48000000
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
"128k(NAND.u-boot-env)," \
"128k(NAND.u-boot-env.backup1)," \
"8m(NAND.kernel)," \
- "-(NAND.rootfs)"
+ "-(NAND.file-system)"
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
/* NAND: SPL related configs */
#ifdef CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */
/* #define CONFIG_INIT_IGNORE_ERROR */
#undef CONFIG_SYS_NO_FLASH
-#define CONFIG_CMD_FLASH
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_CFI
#include "siemens-am33x-common.h"
-#define CONFIG_SYS_MPUCLK 275
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_MPUCLK 300
#define DDR_PLL_FREQ 303
#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
-#define BOARD_DFU_BUTTON_GPIO 27
-#define BOARD_DFU_BUTTON_LED 64 /* red LED */
-#define BOARD_STATUS_LED 103 /* green LED */
+#define BOARD_DFU_BUTTON_GPIO 27 /* Use as default */
#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */
+#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+ "button_dfu0=27\0" \
+ "led0=103,1,0\0" \
+ "led1=64,0,1\0"
+
#undef CONFIG_DOS_PARTITION
#undef CONFIG_CMD_FAT
+#define CONFIG_BOARD_LATE_INIT
/* Physical Memory Map */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* Watchdog */
#define CONFIG_OMAP_WATCHDOG
+/* Define own nand partitions */
+#define CONFIG_ENV_OFFSET_REDUND 0x2E0000
+#define CONFIG_ENV_SIZE_REDUND 0x2000
+#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE)
+
+
+#define MTDPARTS_DEFAULT MTDPARTS_DEFAULT_V2
+
#ifndef CONFIG_SPL_BUILD
/* Default env settings */
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hostname=draco\0" \
"nand_img_size=0x400000\0" \
"optargs=\0" \
- CONFIG_COMMON_ENV_SETTINGS
+ "preboot=draco_led 0\0" \
+ CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+ CONFIG_ENV_SETTINGS_V2 \
+ CONFIG_ENV_SETTINGS_NAND_V2
#ifndef CONFIG_RESTORE_FLASH
/* set to negative value for no autoboot */
"reset; " \
"fi;" \
"run nand_boot;" \
+"run nand_boot_backup;" \
"reset;"
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FAT
#endif
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH 1
#define CONFIG_HARD_SPI 1
#define CONFIG_KIRKWOOD_SPI 1
#define CONFIG_SPI_FLASH_MACRONIX 1
+++ /dev/null
-/*
- * (C) Copyright 2013 Siemens Schweiz AG
- * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- * U-Boot file:/include/configs/am335x_evm.h
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_DXR2_H
-#define __CONFIG_DXR2_H
-
-#define CONFIG_SIEMENS_DXR2
-#define MACH_TYPE_DXR2 4315
-#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_DXR2
-
-#include "siemens-am33x-common.h"
-
-#define CONFIG_SYS_MPUCLK 275
-#define DDR_PLL_FREQ 303
-#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
-
-#define BOARD_DFU_BUTTON_GPIO 27
-#define BOARD_DFU_BUTTON_LED 64 /* red LED */
-#define BOARD_STATUS_LED 103 /* green LED */
-#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */
-
-#undef CONFIG_DOS_PARTITION
-#undef CONFIG_CMD_FAT
-
-
- /* Physical Memory Map */
-#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
-
-/* I2C Configuration */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define EEPROM_ADDR_DDR3 0x90
-#define EEPROM_ADDR_CHIP 0x120
-
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300
-
-#undef CONFIG_SPL_NET_SUPPORT
-#undef CONFIG_SPL_NET_VCI_STRING
-#undef CONFIG_SPL_ETH_SUPPORT
-
-#undef CONFIG_MII
-#undef CONFIG_PHY_GIGE
-#define CONFIG_PHY_SMSC
-
-#define CONFIG_FACTORYSET
-
-/* Watchdog */
-#define CONFIG_OMAP_WATCHDOG
-
-#ifndef CONFIG_SPL_BUILD
-
-/* Default env settings */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hostname=dxr2\0" \
- "nand_img_size=0x400000\0" \
- "optargs=\0" \
- CONFIG_COMMON_ENV_SETTINGS
-
-#ifndef CONFIG_RESTORE_FLASH
-/* set to negative value for no autoboot */
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_BOOTCOMMAND \
-"if dfubutton; then " \
- "run dfu_start; " \
- "reset; " \
-"fi;" \
-"run nand_boot;" \
-"reset;"
-
-
-#else
-#define CONFIG_BOOTDELAY 0
-
-#define CONFIG_BOOTCOMMAND \
- "setenv autoload no; " \
- "dhcp; " \
- "if tftp 80000000 debrick.scr; then " \
- "source 80000000; " \
- "fi"
-#endif
-#endif /* CONFIG_SPL_BUILD */
-#endif /* ! __CONFIG_DXR2_H */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
/*
* U-Boot commands
*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_ENV
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_I2C
#define CONFIG_CMD_GPIO
/* NAND Setup */
#ifdef CONFIG_SYS_USE_NAND
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_MTDPARTS
/* SPI Flash */
#ifdef CONFIG_USE_SPIFLASH
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_FLASH
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
-#define CONFIG_CMD_SAVEENV
#endif
#if !defined(CONFIG_SYS_USE_NAND) && \
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_SIZE (16 << 10)
-#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_ENV
#endif
* Command line configuration.
*/
#define CONFIG_CMDLINE_EDITING
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_LOADB
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
/*
* Command line configuration
*/
-
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_BMP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000
#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_ENV
#define CONFIG_CMD_USB
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_SAVEENV
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */
/* Monitor configuration */
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_XIMG
-
#undef CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_JFFS2
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
/*
- * Commands configuration - using default command set for now
+ * Commands configuration
*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_IDE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_USB
#define CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#endif
-/* Command definition */
-#undef CONFIG_CMD_FPGA
-
#define CONFIG_CMD_BMODE
#define CONFIG_ARP_TIMEOUT 200UL
#define CONFIG_SYS_MAX_FLASH_SECT 128
#define CONFIG_FLASH_16BIT /* Flash is 16-bit */
-#define CONFIG_CMD_FLASH
-
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_SYS_MONITOR_LEN 0x80000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
/*
* U-Boot commands
*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_ENV
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_CACHE
#ifdef CONFIG_CMD_BDI
#endif
#ifdef CONFIG_USE_NAND
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_MTDPARTS
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_SIZE (16 << 10)
-#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_ENV
#endif
* Command line configuration.
*/
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SAVEENV
#define CONFIG_BOOTDELAY -1
#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
/* 512kB DataFlash at NPCS0 */
#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
#define CONFIG_HAS_DATAFLASH
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_ATMEL_DATAFLASH_SPI
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000
#define CONFIG_AT91_GPIO
/* Command line configuration */
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_LOADS
-
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_SPI
-#ifdef MINIMAL_LOADER
-#undef CONFIG_CMD_CONSOLE
-#undef CONFIG_CMD_EDITENV
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_ITEST
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_XIMG
-#else
+#ifndef MINIMAL_LOADER
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BSP
#define CONFIG_CMD_CACHE
#define CONFIG_PWM
/* Command definition*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_MMC
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_FAT_WRITE
/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH
-#undef CONFIG_CMD_IMLS
#include <config_distro_defaults.h>
#define CONFIG_MMC_SDMA
#define CONFIG_MMC_DEFAULT_DEV 0
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_MISC
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_XIMG
#undef CONFIG_CMD_ONENAND
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_DFU
/*
* Command definition
*/
-
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_MII
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SPI
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SPI_FLASH_SPANSION
/* SH Ether */
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
#define CONFIG_CMD_I2C
-#undef CONFIG_CMD_FPGA
#define CONFIG_CMD_USB
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_ENV_OFFSET 0x07C000
#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_EDITENV
-#define CONFIG_CMD_SAVEENV
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
/*
* Supported commands
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_AMBAPP
#define CONFIG_CMD_PING
/*
* Supported commands
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_AMBAPP
#define CONFIG_CMD_PING
/*
* Supported commands
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_AMBAPP
#define CONFIG_CMD_PING
#define CONFIG_USART_BASE ATMEL_BASE_USART1
#define CONFIG_USART_ID 1
-#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
-/* remove unneeded commands */
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-
/* add useful commands */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
* Supported commands
*/
#define CONFIG_CMD_AMBAPP /* AMBA Plyg&Play information */
-#define CONFIG_CMD_BDI /* bdinfo */
-#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ECHO /* echo arguments */
-#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ITEST /* Integer (and string) test */
-#define CONFIG_CMD_LOADB /* loadb */
-#define CONFIG_CMD_LOADS /* loads */
-#define CONFIG_CMD_MISC /* Misc functions like sleep etc */
#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_RUN /* run command in env variable */
-#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
-#define CONFIG_CMD_SOURCE /* "source" command support */
-#define CONFIG_CMD_XIMG /* Load part of Multi Image */
/*
* Autobooting
/*
* Supported commands
*/
-#define CONFIG_CMD_BDI /* bdinfo */
-#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ECHO /* echo arguments */
-#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ITEST /* Integer (and string) test */
-#define CONFIG_CMD_LOADB /* loadb */
-#define CONFIG_CMD_LOADS /* loads */
-#define CONFIG_CMD_MISC /* Misc functions like sleep etc */
#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_RUN /* run command in env variable */
-#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
-#define CONFIG_CMD_SOURCE /* "source" command support */
-#define CONFIG_CMD_XIMG /* Load part of Multi Image */
/*
* Autobooting
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
/* Driver Model */
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_DM
#define CONFIG_DM_GPIO
-#define CONFIG_DM_SERIAL
#define CONFIG_DM_THERMAL
-#define CONFIG_CMD_DM
#endif
/* GPIO */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 38400, 115200 }
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_SOURCE
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_IMI
-
#define CONFIG_FIT
#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_SETUP_MEMORY_TAGS
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_LOADS
#define CONFIG_CMD_SCSI
#define CONFIG_BOOT_RETRY_TIME -1
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PCI
*/
#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */
#define CONFIG_SYS_MVFS
-#include <config_cmd_default.h>
#define CONFIG_CMD_ENV
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_IDE
*/
#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */
#define CONFIG_SYS_MVFS
-#include <config_cmd_default.h>
#define CONFIG_CMD_ENV
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
/*
* U-Boot environment setup
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_MII
#define CONFIG_CMD_DATE
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_CMD_EDITENV
#define CONFIG_CMD_JFFS2
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
/* SPI FLASH - not used for environment */
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 25000000
#define CONFIG_BAUDRATE 115200
/* Command definition */
-#include <config_cmd_default.h>
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
/*
* U-Boot commands
*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
/***********************************************************
* Command definition
***********************************************************/
-
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SPI
/***********************************************************
* Command definition
***********************************************************/
-
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
* - SIB block
* - U-Boot environment
*/
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_ARMFLASH
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_BOOTDELAY 2
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyAM0 console=tty"
#define CONFIG_BOOTCOMMAND ""
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_BOOTDELAY 2
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
#define CONFIG_BOOTCOMMAND "tftpboot ; bootm"
#undef CONFIG_CMD_ELF
#undef CONFIG_CMD_I2C
#undef CONFIG_CMD_IRQ
-#undef CONFIG_CMD_NFS
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
#undef CONFIG_CMD_ELF
#undef CONFIG_CMD_I2C
#undef CONFIG_CMD_IRQ
-#undef CONFIG_CMD_NFS
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_WINBOND
/*
* U-Boot commands
*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_ENV
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_MEMORY
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#ifdef CONFIG_VIDEO
#define CONFIG_CMD_BMP /* BMP support */
#endif
/* SPI */
#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */
#define CONFIG_TEGRA114_SPI_CTRLS 6
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_MISC
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_XIMG
#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOTARGS "root=/dev/hda1 console=ttySA0,19200n8 console=tty1"
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#if defined(CONFIG_PCI)
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DEFAULTENV_VARS
#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_ECHO
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
*/
#define CONFIG_CMD_ELF
#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_NFS
/*
* Without NOR FLASH we need this
*/
#define CONFIG_SYS_NO_FLASH
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
/*
* NAND Flash configuration
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
/* SPI bus claim MPP configuration */
* eSPI - Enhanced SPI
*/
#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_SPANSION
/* we don't need flash support */
#define CONFIG_SYS_NO_FLASH
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_FLASH
#undef CONFIG_FLASH_CFI_MTD
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SPI
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SPI_FLASH_SPANSION
/* SH Ether */
/* SPI Configuration */
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_DAVINCI_SPI
#define CONFIG_CMD_SPI
#define CONFIG_USB_PHY_CFG_BASE KS2_USB_PHY_CFG_BASE
/* U-Boot command configuration */
-#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_OF_LIBFDT
-#include <config_cmd_default.h>
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
#define CONFIG_CMD_ENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
/* SPI */
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SYS_NO_FLASH
/*
* Bootloader Components Configuration
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ENV
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_MMC
#define CONFIG_CMD_USB
#undef CONFIG_LCD
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <config_cmd_default.h>
-
#define CONFIG_LS102XA
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
-/* QSPI */
+/* SPI */
#ifdef CONFIG_QSPI_BOOT
+/* QSPI */
#define CONFIG_FSL_QSPI
#define QSPI0_AMBA_BASE 0x40000000
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
+#define CONFIG_SPI_FLASH_SPANSION
+
+/* DSPI */
+#define CONFIG_FSL_DSPI
+/* DM SPI */
+#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_DM_SPI_FLASH
+#define CONFIG_SPI_FLASH_DATAFLASH
+#endif
#endif
/*
#define CONFIG_CMDLINE_TAG
#define CONFIG_CMDLINE_EDITING
-#ifdef CONFIG_QSPI_BOOT
-#undef CONFIG_CMD_IMLS
-#else
-#define CONFIG_CMD_IMLS
-#endif
-
#define CONFIG_ARMV7_NONSEC
#define CONFIG_ARMV7_VIRT
#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_CMD_ENV_EXISTS
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <config_cmd_default.h>
-
#define CONFIG_LS102XA
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
-/* QSPI */
+/* SPI */
#ifdef CONFIG_QSPI_BOOT
+/* QSPI */
#define CONFIG_FSL_QSPI
#define QSPI0_AMBA_BASE 0x40000000
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
+#define CONFIG_SPI_FLASH_STMICRO
+/* DM SPI */
+#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_DM_SPI_FLASH
+#endif
#endif
/*
#define CONFIG_CMDLINE_TAG
#define CONFIG_CMDLINE_EDITING
-#ifdef CONFIG_QSPI_BOOT
-#undef CONFIG_CMD_IMLS
-#else
-#define CONFIG_CMD_IMLS
-#endif
-
#define CONFIG_ARMV7_NONSEC
#define CONFIG_ARMV7_VIRT
#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_CMD_ENV_EXISTS
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
/* Command line configuration */
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_BDI
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_SOURCE
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
#define __LS2_QDS_H
#include "ls2085a_common.h"
-#include <config_cmd_default.h>
#define CONFIG_IDENT_STRING " LS2085A-QDS"
#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-QDS"
#define __LS2_RDB_H
#include "ls2085a_common.h"
-#include <config_cmd_default.h>
-
#define CONFIG_IDENT_STRING " LS2085A-RDB"
#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-RDB"
/*
* Commands configuration
*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_CMD_MMC
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
/* SPI FLASH */
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SF_DEFAULT_BUS 2
#define CONFIG_SF_DEFAULT_CS 0
/*
* U-Boot Commands
*/
-#include <config_cmd_default.h>
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
/*
* Commands
*/
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_NFS
-
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DISPLAY
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_MII
#define CONFIG_CMD_SNTP
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_I2C
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_BAR
/* Environment in SPI NOR flash */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_GPIO
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
-#undef CONFIG_CMD_IMLS /* List all found images */
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
/*
* Board NAND Info.
*/
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_EEPROM
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_IMLS
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NAND
# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
# define CONFIG_XILINX_SPI 1
# define CONFIG_SPI 1
-# define CONFIG_SPI_FLASH 1
# define CONFIG_SPI_FLASH_STMICRO 1
# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MFSL
-#define CONFIG_CMD_ECHO
#define CONFIG_CMD_GPIO
#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
# undef CONFIG_CMD_CACHE
#endif
-#ifndef CONFIG_SYS_ENET
-# undef CONFIG_CMD_NFS
-#else
+#ifdef CONFIG_SYS_ENET
# define CONFIG_CMD_PING
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_TFTPPUT
#endif
#if defined(FLASH)
-# define CONFIG_CMD_ECHO
-# define CONFIG_CMD_FLASH
-# define CONFIG_CMD_IMLS
# define CONFIG_CMD_JFFS2
# define CONFIG_CMD_UBI
# undef CONFIG_CMD_UBIFS
# if !defined(RAMENV)
-# define CONFIG_CMD_SAVEENV
# define CONFIG_CMD_SAVES
# endif
# define CONFIG_CMD_SF
# if !defined(RAMENV)
-# define CONFIG_CMD_SAVEENV
# define CONFIG_CMD_SAVES
# endif
#else
-# undef CONFIG_CMD_IMLS
-# undef CONFIG_CMD_FLASH
# undef CONFIG_CMD_JFFS2
# undef CONFIG_CMD_UBI
# undef CONFIG_CMD_UBIFS
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define __MPR2_H
/* Supported commands */
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_FLASH
/* Default environment variables */
#define CONFIG_BAUDRATE 115200
#define CONFIG_CPU_SH7720 1
#define CONFIG_MS7720SE 1
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PCMCIA
#define CONFIG_CMD_IDE
#define CONFIG_CPU_SH7722 1
#define CONFIG_MS7722SE 1
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_SAVEENV
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
/*
* Command line configuration.
*/
-/*#include <config_cmd_default.h>*/
-
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SAVEENV
-
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_BAUDRATE 38400
#define CONFIG_CONS_SCIF1 1
/*
* FPGA
*/
-#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_FPGA
#define CONFIG_FPGA_XILINX
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IMMAP
#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
#define CONFIG_PREBOOT
+#define CONFIG_OF_LIBFDT /* Device tree support */
+
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* Common SPI Flash configuration
*/
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH 1
#define CONFIG_SPI_FLASH_MACRONIX 1
#endif
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_ENV
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_NFS
-
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_LONGHELP
/* U-Boot commands */
-#include <config_cmd_default.h>
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_CACHE
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_CMD_USB
/* SPI Flash */
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
#define CONFIG_SF_DEFAULT_BUS 2
#define CONFIG_SF_DEFAULT_CS 0
/* this may vary and depends on the installed chip */
/***********************************************************
* Command definition
***********************************************************/
-
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SPI
/***********************************************************
* Command definition
***********************************************************/
-
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NAND
#define CONFIG_CMD_BOOTZ
-/*
- * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
- * that CFG_NO_FLASH is undefined).
- */
-#undef CONFIG_CMD_IMLS
-
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_BOOTDELAY 1
/*
* Command definition
*/
-
-#include <config_cmd_default.h>
-
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_PING
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <config_cmd_default.h>
-
/*
* High Level Board Configuration Options
*/
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_IDE
#define CONFIG_CMD_DATE
-#undef CONFIG_CMD_IMLS
/*
* Environmental settings
/* SPI FLASH */
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SST
#define CONFIG_SF_DEFAULT_CS 1
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
*/
#ifdef CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
-#ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#endif
#endif
/*
/***********************************************************
* Command definition
***********************************************************/
-
-#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTZ
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_DATE
#define CONFIG_BAUDRATE 115200
/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_IMLS
-
#define CONFIG_BOOTDELAY 3
#define CONFIG_ETHPRIME "smc911x"
#define CONFIG_BAUDRATE 115200
/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_IMLS
-
#define CONFIG_BOOTDELAY 3
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_BAUDRATE 115200
/* Command definition */
-#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTZ
#define CONFIG_SUPPORT_RAW_INITRD
-#undef CONFIG_CMD_IMLS
-
#define CONFIG_BOOTDELAY 1
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_BAUDRATE 115200
/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_IMLS
-
#define CONFIG_BOOTDELAY 3
#define CONFIG_ETHPRIME "FEC0"
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
-#include <config_cmd_default.h>
#ifndef CONFIG_MX6
#define CONFIG_MX6
#define CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#ifdef CONFIG_FSL_QSPI
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SYS_FSL_QSPI_LE
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
#define CONFIG_CMD_DATE
#undef CONFIG_CMD_ELF
#undef CONFIG_CMD_I2C
#undef CONFIG_CMD_IRQ
-#undef CONFIG_CMD_NFS
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */
/* commands */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NFS
-/* There is no NOR flash, so undefine these commands */
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
#define CONFIG_SYS_NO_FLASH
/* There is NAND storage */
#define CONFIG_NAND_NOMADIK
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BOOTD
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_ITEST
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_XIMG
-
#ifdef CONFIG_CMD_NET
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_PING
#define CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SYS_NO_FLASH
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_EXT4 /* EXT4 Support */
#define CONFIG_CMD_FAT /* FAT support */
#endif
-/* commands not needed from config_cmd_default.h */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
-#undef CONFIG_CMD_NFS /* NFS support */
-#undef CONFIG_CMD_SAVEENV /* saveenv */
-#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
-
#define CONFIG_OMAP3_SPI
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
/* SPI */
#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */
#define CONFIG_TEGRA114_SPI_CTRLS 6
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
*/
#include "o2dnt-common.h"
-/* additional commands */
-#define CONFIG_CMD_ITEST
-
/*
* GPIO configuration:
* CS1 SDRAM activate + no CAN + no PCI
/*
* Supported commands
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
*/
#include "o2dnt-common.h"
-/* additional commands */
-#define CONFIG_CMD_ITEST
-
/*
* GPIO configuration:
* CS1 SDRAM activate + no CAN + no PCI
#undef CONFIG_ENV_SIZE
#undef CONFIG_ENV_OFFSET
-#define CONFIG_ENV_SIZE 4096
-#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */
+#define CONFIG_ENV_SIZE (SZ_1K * 16)
+#define CONFIG_ENV_OFFSET (SZ_1K * 3136) /* ~3 MiB offset */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_EXYNOS
+/* DWC3 */
+#define CONFIG_USB_DWC3
+#define CONFIG_USB_DWC3_GADGET
+#define CONFIG_USB_DWC3_PHY_SAMSUNG
+
+/* USB gadget */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+/* Downloader */
+#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
+#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
+#define CONFIG_G_DNL_MANUFACTURER "Samsung"
+#define CONFIG_USBDOWNLOAD_GADGET
+
+/* DFU */
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+#define CONFIG_CMD_DFU
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
+#define DFU_DEFAULT_POLL_TIMEOUT 300
+
+/* THOR */
+#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
+#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
+#define CONFIG_THOR_FUNCTION
+#define CONFIG_CMD_THOR_DOWNLOAD
+
+/* UMS */
+#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
+#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_CMD_USB_MASS_STORAGE
+
/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */
#undef CONFIG_EXYNOS_TMU
#undef CONFIG_TMU_CMD_DTT
+#define CONFIG_DFU_ALT_SYSTEM \
+ "uImage fat 0 1;" \
+ "zImage fat 0 1;" \
+ "Image.itb fat 0 1;" \
+ "uInitrd fat 0 1;" \
+ "boot.scr fat 0 1;" \
+ "boot.cmd fat 0 1;" \
+ "exynos5422-odroidxu3.dtb fat 0 1;" \
+ "boot part 0 1;" \
+ "root part 0 2\0"
+
+#define CONFIG_DFU_ALT_BOOT_EMMC \
+ "u-boot raw 0x3e 0x800 mmcpart 1;" \
+ "bl1 raw 0x0 0x1e mmcpart 1;" \
+ "bl2 raw 0x1e 0x1d mmcpart 1;" \
+ "tzsw raw 0x83e 0x200 mmcpart 1;" \
+ "params.bin raw 0x1880 0x20\0"
+
+#define CONFIG_DFU_ALT_BOOT_SD \
+ "u-boot raw 0x3f 0x800;" \
+ "bl1 raw 0x1 0x1e;" \
+ "bl2 raw 0x1f 0x1d;" \
+ "tzsw raw 0x83f 0x200;" \
+ "params.bin raw 0x1880 0x20\0"
+
+/* Enable: board/samsung/common/misc.c to use set_dfu_alt_info() */
+#define CONFIG_MISC_COMMON
+#define CONFIG_SET_DFU_ALT_INFO
+#define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K)
+
+/* Define new extra env settings, including DFU settings */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXYNOS_DEVICE_SETTINGS \
+ EXYNOS_FDTFILE_SETTING \
+ MEM_LAYOUT_ENV_SETTINGS \
+ BOOTENV \
+ "bootdelay=0\0" \
+ "rootfstype=ext4\0" \
+ "console=" CONFIG_DEFAULT_CONSOLE \
+ "fdtfile=exynos5422-odroidxu3.dtb\0" \
+ "boardname=odroidxu3\0" \
+ "mmcbootdev=0\0" \
+ "mmcrootdev=0\0" \
+ "mmcbootpart=1\0" \
+ "mmcrootpart=2\0" \
+ "dfu_alt_system="CONFIG_DFU_ALT_SYSTEM \
+ "dfu_alt_info=Autoset by THOR/DFU command run.\0"
+
#endif /* __CONFIG_H */
#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_NAND
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_NAND_LOCK_UNLOCK
-/* Disable some commands */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
-
/*
* TWL4030
*/
* Supported U-boot commands
* ----------------------------------------------------------------------------
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
-#undef CONFIG_CMD_IMLS /* List all found images */
-
/* ----------------------------------------------------------------------------
* Supported U-boot features
* ----------------------------------------------------------------------------
#endif
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
-#define CONFIG_CMD_NFS /* NFS support */
/*#undef CONFIG_ENV_IS_NOWHERE*/
#define CONFIG_DOS_PARTITION
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
-#undef CONFIG_CMD_IMLS /* List all found images */
-
#define CONFIG_SYS_NO_FLASH
/*
#define CONFIG_SYS_NO_FLASH
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_IMI /* iminfo */
-#undef CONFIG_CMD_IMLS /* List all found images */
-#define CONFIG_CMD_NFS /* NFS support */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
-#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_SYS_I2C
/* commands to include */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_USB
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
-#undef CONFIG_CMD_NFS /* NFS support */
#ifdef CONFIG_NAND
#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */
#define CONFIG_SERIAL3 3
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE /* Cache control */
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
-#undef CONFIG_CMD_IMLS /* List all found images */
-#undef CONFIG_CMD_NFS /* NFS support */
/*
* Board NAND Info.
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
/*--------------------------------------------------------------------------*/
-/* commands to include */
-#include <config_cmd_default.h>
-
/* Enabled commands */
#define CONFIG_CMD_DHCP /* DHCP Support */
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_MMC /* MMC support */
-/* Disabled commands */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMLS /* List all found images */
-
/*--------------------------------------------------------------------------*/
/*
* MMC boot support
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
#endif
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
-#undef CONFIG_CMD_IMLS /* List all found images */
-#define CONFIG_CMD_NFS /* NFS support */
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_DEVICE_AND_PART "0:1"
#define FAT_ENV_FILE "uboot.env"
-#define CONFIG_CMD_SAVEENV
#define CONFIG_ENV_OVERWRITE
#endif /* __CONFIG_PANDA_H */
#define CONFIG_ENV_IS_IN_MMC 1
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
#define CONFIG_ENV_OFFSET 0xE0000
-#define CONFIG_CMD_SAVEENV
#endif /* __CONFIG_SDP4430_H */
#ifndef __CONFIG_OMAP5_EVM_H
#define __CONFIG_OMAP5_EVM_H
+#ifndef CONFIG_SPL_BUILD
/* Define the default GPT table for eMMC */
#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
+#endif
#include <configs/ti_omap5_common.h>
#define CONFIG_ENV_OFFSET 0xE0000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_CMD_SAVEENV
/* Enhance our eMMC support / experience. */
#define CONFIG_CMD_GPT
/* Enabled commands */
#define CONFIG_CMD_DHCP /* DHCP Support */
-#define CONFIG_CMD_NFS /* NFS support */
/* USB Networking options */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_DAVINCI_SPI
/*
* U-Boot commands
*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_ENV
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_MEMORY
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif
#endif
#ifdef CONFIG_USE_NAND
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_MTDPARTS
#endif
#ifdef CONFIG_USE_SPIFLASH
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_FLASH
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
-#define CONFIG_CMD_SAVEENV
#endif
#if !defined(CONFIG_USE_NAND) && \
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_SIZE (16 << 10)
-#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_ENV
#endif
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#define CONFIG_SYS_MVFS
-#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_MII
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
-
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ELF
#define CONFIG_CMD_BSP
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_BOOTZ
#define CONFIG_SUPPORT_RAW_INITRD
-#undef CONFIG_CMD_NFS
/* MMC SPL */
#define COPY_BL2_FNPTR_ADDR 0x02020030
/* SF Configs */
#define CONFIG_CMD_SF
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SPI_FLASH_MACRONIX
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_IMLS
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NAND
#define CONFIG_BOARDNAME "P1020RDB-PC"
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_P1020
-#define CONFIG_SPI_FLASH
#define CONFIG_VSC7385_ENET
#define CONFIG_SLIC
#define __SW_BOOT_MASK 0x03
#define CONFIG_BOARDNAME "P1020RDB-PD"
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_P1020
-#define CONFIG_SPI_FLASH
#define CONFIG_VSC7385_ENET
#define CONFIG_SLIC
#define __SW_BOOT_MASK 0x03
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_P1021
#define CONFIG_QE
-#define CONFIG_SPI_FLASH
#define CONFIG_VSC7385_ENET
#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
addresses in the LBC */
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_P1024
#define CONFIG_SLIC
-#define CONFIG_SPI_FLASH
#define __SW_BOOT_MASK 0xf3
#define __SW_BOOT_NOR 0x00
#define __SW_BOOT_SPI 0x08
#define CONFIG_P1025
#define CONFIG_QE
#define CONFIG_SLIC
-#define CONFIG_SPI_FLASH
#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
addresses in the LBC */
#define CONFIG_BOARDNAME "P2020RDB-PCA"
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_P2020
-#define CONFIG_SPI_FLASH
#define CONFIG_VSC7385_ENET
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xc8
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
/*
* Bootloader Components Configuration
*/
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_NFS
#define CONFIG_CMD_ENV
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_MMC
#define CONFIG_CMD_IDE
#define CONFIG_LCD
/*
* Bootloader Components Configuration
*/
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_NFS
#define CONFIG_CMD_ENV
#define CONFIG_CMD_MMC
#define CONFIG_LCD
/*
* Bootloader Components Configuration
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_SOURCE
-#undef CONFIG_CMD_XIMG
-
#define CONFIG_CMD_ENV
#define CONFIG_CMD_MMC
#define CONFIG_CMD_NAND
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
-#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_FAT
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IDE
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_RUN
-#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_ELF
-#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_BEDBUG
#endif /* __CONFIG_H */
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
+ (8 * 1024 * 1024))
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 24000000
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_IDE
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define __CONFIG_PEACH_PI_H
#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_SPI_FLASH
#define CONFIG_ENV_SPI_BASE 0x12D30000
#define FLASH_SIZE (0x4 << 20)
#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
#define __CONFIG_PEACH_PIT_H
#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_SPI_FLASH
#define CONFIG_ENV_SPI_BASE 0x12D30000
#define FLASH_SIZE (0x4 << 20)
#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_IMLS
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_IMLS
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMLS
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
/* NOR flash, not available */
#define CONFIG_SYS_NO_FLASH 1
-#undef CONFIG_CMD_FLASH
/* NAND flash */
#ifdef CONFIG_CMD_NAND
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#define CONFIG_SYS_MVFS
-#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_MII
/* FLASH */
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SPI_FLASH_QUAD
#define CONFIG_SYS_NO_FLASH
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_FAT
#define CONFIG_CMD_DHCP
#define DDR_PLL_FREQ 266
#define BOARD_DFU_BUTTON_GPIO 59
-#define BOARD_DFU_BUTTON_LED 117
#define BOARD_LCD_POWER 111
#define BOARD_BACK_LIGHT 112
#define BOARD_TOUCH_POWER 57
+#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+ "button_dfu0=59\0" \
+ "led0=117,0,1\0" \
+
/* Physical Memory Map */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */
#define CONFIG_FACTORYSET
-/* UBI Support */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#endif
/* Watchdog */
#define CONFIG_OMAP_WATCHDOG
#ifndef CONFIG_SPL_BUILD
+/* Use common default */
+#define MTDPARTS_DEFAULT MTDPARTS_DEFAULT_V1
+
/* Default env settings */
#define CONFIG_EXTRA_ENV_SETTINGS \
"hostname=pxm2\0" \
"nand_img_size=0x500000\0" \
"optargs=\0" \
+ "preboot=draco_led 0\0" \
+ CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
"splashpos=m,m\0" \
- CONFIG_COMMON_ENV_SETTINGS \
+ CONFIG_ENV_SETTINGS_V1 \
+ CONFIG_ENV_SETTINGS_NAND_V1 \
"mmc_dev=0\0" \
"mmc_root=/dev/mmcblk0p2 rw\0" \
"mmc_root_fs_type=ext4 rootwait\0" \
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_DHCP
#define CONFIG_DRIVER_NE2000
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_DHCP
#define CONFIG_DRIVER_NE2000
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_BOOTZ
/***********************************************************
* Command definition
***********************************************************/
-
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_SAVEENV
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_IDE
* Command line configuration.
*/
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_IDE
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION
--- /dev/null
+/*
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_RASTABAN_H
+#define __CONFIG_RASTABAN_H
+
+#include "siemens-am33x-common.h"
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_MPUCLK 300
+#define DDR_PLL_FREQ 303
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+
+/* FWD Button = 27
+ * SRV Button = 87 */
+#define BOARD_DFU_BUTTON_GPIO 27
+#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */
+/* In dfu mode keep led1 on */
+#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+ "button_dfu0=27\0" \
+ "button_dfu1=87\0" \
+ "led0=3,0,1\0" \
+ "led1=4,0,0\0" \
+ "led2=5,0,1\0" \
+ "led3=62,0,1\0" \
+ "led4=60,0,1\0" \
+ "led5=63,0,1\0"
+
+#undef CONFIG_DOS_PARTITION
+#undef CONFIG_CMD_FAT
+
+#define CONFIG_BOARD_LATE_INIT
+
+ /* Physical Memory Map */
+#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define EEPROM_ADDR_DDR3 0x90
+#define EEPROM_ADDR_CHIP 0x120
+
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300
+
+#undef CONFIG_SPL_NET_SUPPORT
+#undef CONFIG_SPL_NET_VCI_STRING
+#undef CONFIG_SPL_ETH_SUPPORT
+
+#undef CONFIG_MII
+#undef CONFIG_PHY_GIGE
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_FACTORYSET
+
+/* Watchdog */
+#define CONFIG_OMAP_WATCHDOG
+
+/* Define own nand partitions */
+#define CONFIG_ENV_OFFSET_REDUND 0x2E0000
+#define CONFIG_ENV_SIZE_REDUND 0x2000
+#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE)
+
+
+
+#define MTDPARTS_DEFAULT MTDPARTS_DEFAULT_V3
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Default env settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hostname=rastaban\0" \
+ "nand_img_size=0x400000\0" \
+ "optargs=\0" \
+ "preboot=draco_led 0\0" \
+ CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+ CONFIG_ENV_SETTINGS_V2 \
+ CONFIG_ENV_SETTINGS_NAND_V2
+
+#ifndef CONFIG_RESTORE_FLASH
+/* set to negative value for no autoboot */
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_BOOTCOMMAND \
+"if dfubutton; then " \
+ "run dfu_start; " \
+ "reset; " \
+"fi;" \
+"run nand_boot;" \
+"run nand_boot_backup;" \
+"reset;"
+
+
+#else
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv autoload no; " \
+ "dhcp; " \
+ "if tftp 80000000 debrick.scr; then " \
+ "source 80000000; " \
+ "fi"
+#endif
+#endif /* CONFIG_SPL_BUILD */
+#endif /* ! __CONFIG_RASTABAN_H */
#include <asm/arch/rmobile.h>
-#define CONFIG_CMD_EDITENV
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_LOADS
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_USB
#define CONFIG_CMD_FAT
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FAT
#define CONFIG_COMMAND_HISTORY
/* Commands */
-#include <config_cmd_default.h>
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_MMC
#define CONFIG_PARTITION_UUIDS
#include <config_distro_defaults.h>
-/* Some things don't make sense on this HW or yet */
-#undef CONFIG_CMD_FPGA
-
/* Environment */
#define ENV_DEVICE_SETTINGS \
"stdin=serial,lcd\0" \
#define CONFIG_CPU_SH7203 1
#define CONFIG_RSK7203 1
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_CACHE
#define CONFIG_BAUDRATE 115200
#define CONFIG_CPU_SH7264 1
#define CONFIG_RSK7264 1
-#ifndef _CONFIG_CMD_DEFAULT_H
-# include <config_cmd_default.h>
-#endif
-
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC3,115200"
#define CONFIG_BOOTDELAY 3
#define CONFIG_CPU_SH7269 1
#define CONFIG_RSK7269 1
-#ifndef _CONFIG_CMD_DEFAULT_H
-# include <config_cmd_default.h>
-#endif
-
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC7,115200"
#define CONFIG_BOOTDELAY 3
#define CONFIG_FACTORYSET
-/* UBI Support */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#endif
/* Watchdog */
#define WATCHDOG_TRIGGER_GPIO 14
#ifndef CONFIG_SPL_BUILD
+/* Use common default */
+#define MTDPARTS_DEFAULT MTDPARTS_DEFAULT_V1
+
/* Default env settings */
#define CONFIG_EXTRA_ENV_SETTINGS \
"hostname=rut\0" \
"nand_img_size=0x500000\0" \
"splashpos=m,m\0" \
"optargs=fixrtc --no-log consoleblank=0 \0" \
- CONFIG_COMMON_ENV_SETTINGS \
+ CONFIG_ENV_SETTINGS_V1 \
+ CONFIG_ENV_SETTINGS_NAND_V1 \
"mmc_dev=0\0" \
"mmc_root=/dev/mmcblk0p2 rw\0" \
"mmc_root_fs_type=ext4 rootwait\0" \
/* PWM */
#define CONFIG_PWM 1
-/* It should define before config_cmd_default.h */
#define CONFIG_SYS_NO_FLASH 1
-/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_MISC
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_XIMG
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_ONENAND
/* NOR flash */
#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_CMD_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SF_DEFAULT_SPEED 30000000
#endif
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
#define CONFIG_ATMEL_SPI0
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
#define CONFIG_ATMEL_SPI0
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_CMD_SF
#define CONFIG_CMD_SF_TEST
#define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SPI_FLASH_EON
#define CONFIG_SPI_FLASH_GIGADEVICE
#define CONFIG_SYS_NO_FLASH
/* include default commands */
-#include <config_cmd_default.h>
#include <config_distro_defaults.h>
#define BOOT_TARGET_DEVICES(func) \
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_BSP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_PCI
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#include <config_cmd_default.h>
- #define CONFIG_CMD_PING
- #define CONFIG_CMD_I2C
- #define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
-#undef CONFIG_CMD_CONSOLE
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_SOURCE
-
/*
* Boot options. Setting delay to -1 stops autostart count down.
* NOTE: Sending parameters to kernel depends on kernel version and
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+#endif /* CONFIG_CMD_FLASH */
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif
-#endif /* CONFIG_CMD_FLASH */
/*
* DDR SDRAM
#define CONFIG_SYS_TEXT_BASE 0x5ff80000
#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7752evb/u-boot.lds"
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SF
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_MD5SUM
#define CONFIG_MD5
-#define CONFIG_CMD_LOADS
#define CONFIG_CMD_MMC
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION
/* SPI */
#define CONFIG_SH_SPI 1
#define CONFIG_SH_SPI_BASE 0xfe002000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO 1
#define CONFIG_SPI_FLASH_MACRONIX 1
#define CONFIG_SYS_TEXT_BASE 0x5ff80000
#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7753evb/u-boot.lds"
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SF
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_MD5SUM
#define CONFIG_MD5
-#define CONFIG_CMD_LOADS
#define CONFIG_CMD_MMC
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION
/* SPI */
#define CONFIG_SH_SPI 1
#define CONFIG_SH_SPI_BASE 0xfe002000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO 1
#define CONFIG_SPI_FLASH_MACRONIX 1
#define CONFIG_SYS_TEXT_BASE 0x8ef80000
#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7757lcr/u-boot.lds"
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SF
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_MD5SUM
#define CONFIG_MD5
-#define CONFIG_CMD_LOADS
#define CONFIG_CMD_MMC
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION
/* SPI */
#define CONFIG_SH_SPI 1
#define CONFIG_SH_SPI_BASE 0xfe002000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO 1
/* MMCIF */
* Command line configuration.
*/
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_JFFS2
#define CONFIG_BOOTDELAY -1
#define CONFIG_CPU_SH7785 1
#define CONFIG_SH7785LCR 1
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SH_ZIMAGEBOOT
#define CONFIG_CMD_USB
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
/* T-SH7706LSR*/
/* #define CONFIG_T_SH7706LSR 1 */
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PING
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_SAVEENV
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC0,115200"
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_SIEMENS_MACH_TYPE
#define CONFIG_MACH_TYPE CONFIG_SIEMENS_MACH_TYPE
+#endif
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_CACHELINE_SIZE 64
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_ECHO
#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_TIME
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_MAXARGS 32
/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_CBSIZE 1024
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
#define CONFIG_SPI
#define CONFIG_OMAP3_SPI
#define CONFIG_MTD_DEVICE
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED (75000000)
/* NAND support */
#ifdef CONFIG_NAND
#define CONFIG_CMD_NAND
+
+/* UBI Support */
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+/* Commen environment */
+#define CONFIG_PREBOOT
+#define COMMON_ENV_DFU_ARGS "dfu_args=run bootargs_defaults;" \
+ "setenv bootargs ${bootargs};" \
+ "mtdparts default;" \
+ "draco_led 1;" \
+ "dfu 0 nand 0;" \
+ "draco_led 0;\0" \
+
+#define COMMON_ENV_NAND_BOOT \
+ "nand_boot=echo Booting from nand; " \
+ "if test ${upgrade_available} -eq 1; then " \
+ "if test ${bootcount} -gt ${bootlimit}; " \
+ "then " \
+ "setenv upgrade_available 0;" \
+ "setenv ${partitionset_active} true;" \
+ "if test -n ${A}; then " \
+ "setenv partitionset_active B; " \
+ "env delete A; " \
+ "fi;" \
+ "if test -n ${B}; then " \
+ "setenv partitionset_active A; " \
+ "env delete B; " \
+ "fi;" \
+ "saveenv; " \
+ "fi;" \
+ "fi;" \
+ "echo set ${partitionset_active}...;" \
+ "run nand_args; "
+
+#define COMMON_ENV_NAND_CMDS "flash_self=run nand_boot\0" \
+ "flash_self_test=setenv testargs test; " \
+ "run nand_boot\0" \
+ "dfu_start=echo Preparing for dfu mode ...; " \
+ "run dfu_args; \0"
+
+#define COMMON_ENV_SETTINGS \
+ "verify=no \0" \
+ "project_dir=targetdir\0" \
+ "upgrade_available=0\0" \
+ "altbootcmd=run bootcmd\0" \
+ "bootlimit=3\0" \
+ "partitionset_active=A\0" \
+ "loadaddr=0x82000000\0" \
+ "kloadaddr=0x81000000\0" \
+ "script_addr=0x81900000\0" \
+ "console=console=ttyMTD,mtdoops console=ttyO0,115200n8 panic=5\0" \
+ "nfsopts=nolock rw\0" \
+ "ip_method=none\0" \
+ "bootenv=uEnv.txt\0" \
+ "bootargs_defaults=setenv bootargs " \
+ "console=${console} " \
+ "${testargs} " \
+ "${optargs}\0" \
+ "siemens_help=echo; "\
+ "echo Type 'run flash_self' to use kernel and root " \
+ "filesystem on memory; echo Type 'run flash_self_test' to " \
+ "use kernel and root filesystem on memory, boot in test " \
+ "mode; echo Not ready yet: 'run flash_nfs' to use kernel " \
+ "from memory and root filesystem over NFS; echo Type " \
+ "'run net_nfs' to get Kernel over TFTP and mount root " \
+ "filesystem over NFS; " \
+ "echo Set partitionset_active variable to 'A' " \
+ "or 'B' to select kernel and rootfs partition; " \
+ "echo" \
+ "\0"
-#define MTDIDS_NAME_STR "omap2-nand.0"
-#define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR
-#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
- "128k(spl)," \
- "128k(spl.backup1)," \
- "128k(spl.backup2)," \
- "128k(spl.backup3)," \
- "1920k(u-boot)," \
- "128k(uboot.env)," \
- "5120k(kernel_a)," \
- "5120k(kernel_b)," \
- "8192k(mtdoops)," \
- "-(rootfs)"
/*
+ * Variant 1 partition layout
* chip-size = 256MiB
*| name | size | address area |
*-------------------------------------------------------
*| rootfs | 235.500 MiB | 0x 1480000..0x fffffff |
*-------------------------------------------------------
*/
+#define MTDIDS_NAME_STR "omap2-nand.0"
+#define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT_V1 "mtdparts=" MTDIDS_NAME_STR ":" \
+ "128k(spl)," \
+ "128k(spl.backup1)," \
+ "128k(spl.backup2)," \
+ "128k(spl.backup3)," \
+ "1920k(u-boot)," \
+ "128k(uboot.env)," \
+ "5120k(kernel_a)," \
+ "5120k(kernel_b)," \
+ "8192k(mtdoops)," \
+ "-(rootfs)"
-#define DFU_ALT_INFO_NAND \
+#define DFU_ALT_INFO_NAND_V1 \
"spl part 0 1;" \
"spl.backup1 part 0 2;" \
"spl.backup2 part 0 3;" \
"kernel_b part 0 8;" \
"rootfs partubi 0 10"
-#define CONFIG_COMMON_ENV_SETTINGS \
- "verify=no \0" \
- "project_dir=targetdir\0" \
- "upgrade_available=0\0" \
- "altbootcmd=run bootcmd\0" \
- "bootlimit=3\0" \
- "partitionset_active=A\0" \
- "loadaddr=0x82000000\0" \
- "kloadaddr=0x81000000\0" \
- "script_addr=0x81900000\0" \
- "console=console=ttyMTD,mtdoops console=ttyO0,115200n8 panic=5\0" \
+#define CONFIG_ENV_SETTINGS_NAND_V1 \
"nand_active_ubi_vol=rootfs_a\0" \
"nand_active_ubi_vol_A=rootfs_a\0" \
"nand_active_ubi_vol_B=rootfs_b\0" \
"nand_src_addr=0x280000\0" \
"nand_src_addr_A=0x280000\0" \
"nand_src_addr_B=0x780000\0" \
- "nfsopts=nolock rw mem=128M\0" \
- "ip_method=none\0" \
- "bootenv=uEnv.txt\0" \
- "bootargs_defaults=setenv bootargs " \
- "console=${console} " \
- "${testargs} " \
- "${optargs}\0" \
"nand_args=run bootargs_defaults;" \
"mtdparts default;" \
"setenv ${partitionset_active} true;" \
"rootfstype=${nand_root_fs_type} ip=${ip_method} " \
"console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \
"=mtdoops\0" \
- "dfu_args=run bootargs_defaults;" \
- "setenv bootargs ${bootargs} ;" \
- "mtdparts default; " \
- "led dfu 1;" \
- "led stat 0;" \
- "dfu 0 nand 0;" \
- "led dfu 0;" \
- "led stat 1;\0" \
- "dfu_alt_info=" DFU_ALT_INFO_NAND "\0" \
+ COMMON_ENV_DFU_ARGS \
+ "dfu_alt_info=" DFU_ALT_INFO_NAND_V1 "\0" \
+ COMMON_ENV_NAND_BOOT \
+ "nand read.i ${kloadaddr} ${nand_src_addr} " \
+ "${nand_img_size}; bootm ${kloadaddr}\0" \
+ COMMON_ENV_NAND_CMDS
+
+#define CONFIG_ENV_SETTINGS_V1 \
+ COMMON_ENV_SETTINGS \
"net_args=run bootargs_defaults;" \
"mtdparts default;" \
"setenv bootfile ${project_dir}/kernel/uImage;" \
"nfsroot=${serverip}:${rootpath},${nfsopts} " \
"ip=${ipaddr}:${serverip}:" \
"${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
- "nand_boot=echo Booting from nand; " \
- "if test ${upgrade_available} -eq 1; then " \
- "if test ${bootcount} -gt ${bootlimit}; " \
- "then " \
- "setenv upgrade_available 0;" \
- "setenv ${partitionset_active} true;" \
- "if test -n ${A}; then " \
- "setenv partitionset_active B; " \
- "env delete A; " \
- "fi;" \
- "if test -n ${B}; then " \
- "setenv partitionset_active A; " \
- "env delete B; " \
- "fi;" \
- "saveenv; " \
- "fi;" \
+ "net_nfs=echo Booting from network ...; " \
+ "run net_args; " \
+ "tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \
+ "bootm ${kloadaddr}\0"
+
+/*
+ * Variant 2 partition layout
+ * chip-size = 256MiB
+ *| name | size | address area |
+ *-------------------------------------------------------
+ *| spl | 128.000 KiB | 0x 0..0x 1ffff |
+ *| spl.backup1 | 128.000 KiB | 0x 20000..0x 3ffff |
+ *| spl.backup2 | 128.000 KiB | 0x 40000..0x 5ffff |
+ *| spl.backup3 | 128.000 KiB | 0x 60000..0x 7ffff |
+ *| u-boot | 1.875 MiB | 0x 80000..0x 25ffff |
+ *| uboot.env0 | 512.000 KiB | 0x 260000..0x 2Dffff |
+ *| uboot.env1 | 512.000 KiB | 0x 2E0000..0x 35ffff |
+ *| rootfs | 148.000 MiB | 0x 360000..0x 975ffff |
+ *| mtdoops | 512.000 KiB | 0x 9760000..0x 98Dffff |
+ *|configuration | 104.125 MiB | 0x 97E0000..0x fffffff |
+ *-------------------------------------------------------
+ */
+
+#define MTDPARTS_DEFAULT_V2 "mtdparts=" MTDIDS_NAME_STR ":" \
+ "128k(spl)," \
+ "128k(spl.backup1)," \
+ "128k(spl.backup2)," \
+ "128k(spl.backup3)," \
+ "1920k(u-boot)," \
+ "512k(u-boot.env0)," \
+ "512k(u-boot.env1)," \
+ "148m(rootfs)," \
+ "512k(mtdoops)," \
+ "-(configuration)"
+
+#define DFU_ALT_INFO_NAND_V2 \
+ "spl part 0 1;" \
+ "spl.backup1 part 0 2;" \
+ "spl.backup2 part 0 3;" \
+ "spl.backup3 part 0 4;" \
+ "u-boot part 0 5;" \
+ "u-boot.env0 part 0 6;" \
+ "u-boot.env1 part 0 7;" \
+ "rootfs partubi 0 8;" \
+ "configuration partubi 0 10"
+
+#define CONFIG_ENV_SETTINGS_NAND_V2 \
+ "nand_active_ubi_vol=rootfs_a\0" \
+ "rootfs_name=rootfs\0" \
+ "kernel_name=uImage\0"\
+ "nand_root_fs_type=ubifs rootwait=1\0" \
+ "nand_args=run bootargs_defaults;" \
+ "mtdparts default;" \
+ "setenv ${partitionset_active} true;" \
+ "if test -n ${A}; then " \
+ "setenv nand_active_ubi_vol ${rootfs_name}_a;" \
"fi;" \
- "echo set ${partitionset_active}...;" \
- "run nand_args; " \
- "nand read.i ${kloadaddr} ${nand_src_addr} " \
- "${nand_img_size}; bootm ${kloadaddr}\0" \
+ "if test -n ${B}; then " \
+ "setenv nand_active_ubi_vol ${rootfs_name}_b;" \
+ "fi;" \
+ "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
+ "ubi.mtd=7,2048 ubi.mtd=9,2048;" \
+ "setenv bootargs ${bootargs} " \
+ "root=${nand_root} noinitrd ${mtdparts} " \
+ "rootfstype=${nand_root_fs_type} ip=${ip_method} " \
+ "console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \
+ "=mtdoops\0" \
+ COMMON_ENV_DFU_ARGS \
+ "dfu_alt_info=" DFU_ALT_INFO_NAND_V2 "\0" \
+ COMMON_ENV_NAND_BOOT \
+ "ubi part rootfs 2048;" \
+ "ubifsmount ubi0:${nand_active_ubi_vol};" \
+ "ubifsload ${kloadaddr} boot/${kernel_name};" \
+ "ubifsload ${loadaddr} boot/${dtb_name}.dtb;" \
+ "bootm ${kloadaddr} - ${loadaddr}\0" \
+ "nand_boot_backup=ubifsload ${loadaddr} boot/am335x-draco.dtb;" \
+ "bootm ${kloadaddr} - ${loadaddr}\0" \
+ COMMON_ENV_NAND_CMDS
+
+#define CONFIG_ENV_SETTINGS_V2 \
+ COMMON_ENV_SETTINGS \
+ "net_args=run bootargs_defaults;" \
+ "mtdparts default;" \
+ "setenv bootfile ${project_dir}/kernel/uImage;" \
+ "setenv bootdtb ${project_dir}/kernel/dtb;" \
+ "setenv rootpath /home/projects/${project_dir}/rootfs;" \
+ "setenv bootargs ${bootargs} " \
+ "root=/dev/nfs ${mtdparts} " \
+ "nfsroot=${serverip}:${rootpath},${nfsopts} " \
+ "ip=${ipaddr}:${serverip}:" \
+ "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
"net_nfs=echo Booting from network ...; " \
"run net_args; " \
"tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \
- "bootm ${kloadaddr}\0" \
- "flash_self=run nand_boot\0" \
- "flash_self_test=setenv testargs test; " \
- "run nand_boot\0" \
- "dfu_start=echo Preparing for dfu mode ...; " \
- "run dfu_args; \0" \
- "preboot=echo; "\
- "echo Type 'run flash_self' to use kernel and root " \
- "filesystem on memory; echo Type 'run flash_self_test' to " \
- "use kernel and root filesystem on memory, boot in test " \
- "mode; echo Not ready yet: 'run flash_nfs' to use kernel " \
- "from memory and root filesystem over NFS; echo Type " \
- "'run net_nfs' to get Kernel over TFTP and mount root " \
- "filesystem over NFS; " \
- "echo Set partitionset_active variable to 'A' " \
- "or 'B' to select kernel and rootfs partition; " \
- "echo" \
- "\0"
+ "tftpboot ${loadaddr} ${serverip}:${bootdtb}; " \
+ "bootm ${kloadaddr} - ${loadaddr}\0"
+
+/*
+ * Variant 3 partition layout
+ * chip-size = 512MiB
+ *| name | size | address area |
+ *-------------------------------------------------------
+ *| spl | 128.000 KiB | 0x 0..0x 1ffff |
+ *| spl.backup1 | 128.000 KiB | 0x 20000..0x 3ffff |
+ *| spl.backup2 | 128.000 KiB | 0x 40000..0x 5ffff |
+ *| spl.backup3 | 128.000 KiB | 0x 60000..0x 7ffff |
+ *| u-boot | 1.875 MiB | 0x 80000..0x 25ffff |
+ *| uboot.env0 | 512.000 KiB | 0x 260000..0x 2Dffff |
+ *| uboot.env1 | 512.000 KiB | 0x 2E0000..0x 35ffff |
+ *| rootfs | 300.000 MiB | 0x 360000..0x12f5ffff |
+ *| mtdoops | 512.000 KiB | 0x12f60000..0x12fdffff |
+ *|configuration | 104.125 MiB | 0x12fe0000..0x1fffffff |
+ *-------------------------------------------------------
+ */
+
+#define MTDPARTS_DEFAULT_V3 "mtdparts=" MTDIDS_NAME_STR ":" \
+ "128k(spl)," \
+ "128k(spl.backup1)," \
+ "128k(spl.backup2)," \
+ "128k(spl.backup3)," \
+ "1920k(u-boot)," \
+ "512k(u-boot.env0)," \
+ "512k(u-boot.env1)," \
+ "300m(rootfs)," \
+ "512k(mtdoops)," \
+ "-(configuration)"
+
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_ELM
#define CONFIG_OMAP_GPIO
+/* Gpio cmd support */
+#define CONFIG_CMD_GPIO
+
/* Watchdog */
#define CONFIG_HW_WATCHDOG
/* FLASH */
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SPI_FLASH_QUAD
#define CONFIG_SYS_NO_FLASH
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_BSP
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define __CONFIG_SMDK_H
#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_SPI_FLASH
#define CONFIG_ENV_SPI_BASE 0x12D30000
#define FLASH_SIZE (0x4 << 20)
#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
#define __CONFIG_SMDK5420_H
#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_SPI_FLASH
#define CONFIG_ENV_SPI_BASE 0x12D30000
#define FLASH_SIZE (0x4 << 20)
#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
/***********************************************************
* Command definition
***********************************************************/
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_NAND
#define CONFIG_CMD_CACHE
#define CONFIG_SYS_MALLOC_LEN (1 << 20)
/* Command line configuration */
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_SOURCE
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_FAT
#define __CONFIG_SNOW_H
#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_SPI_FLASH
#define CONFIG_ENV_SPI_BASE 0x12D30000
#define FLASH_SIZE (0x4 << 20)
#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_SAVEENV
#define CONFIG_ENV_OFFSET 0x0118000
#define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */
/*
* Commands
*/
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MMC
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_SOURCE
#ifndef CONFIG_BOOTDELAY
#define CONFIG_BOOTDELAY 1
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#include <config_cmd_default.h>
#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MII
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_BAR
/*
#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
#define CONFIG_CADENCE_QSPI
/* Enable multiple SPI NOR flash manufacturers */
-#define CONFIG_SPI_FLASH /* SPI flash subsystem */
#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */
#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */
#define CONFIG_SPI_FLASH_MTD
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#include <config_cmd_default.h>
#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MII
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_BMP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_MII
-#undef CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NAND
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_RUN
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <config_cmd_default.h>
-
/*
* Default Environment Varible definitions
*/
"bootm 22000000"
/* Command line & features configuration */
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
-
#define CONFIG_CMD_NAND
#define CONFIG_CMD_USB
#define CONFIG_CMD_FAT
#ifdef CONFIG_MACB
# define CONFIG_CMD_PING
# define CONFIG_CMD_DHCP
-#else
-# undef CONFIG_CMD_BOOTD
-# undef CONFIG_CMD_NFS
#endif /* CONFIG_MACB */
#endif /* __CONFIG_H */
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "U-Boot > "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_MEM
-#define CONFIG_CMD_MISC
#define CONFIG_CMD_TIMER
#endif /* __CONFIG_H */
#define CONFIG_CMD_PING
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
-#include "config_cmd_default.h"
-#undef CONFIG_CMD_SAVEENV
-
#define CONFIG_SYS_MEMTEST_START 0x0000
#define CONFIG_SYS_MEMTEST_END 1024*1024
#define CONFIG_CMD_MEMTEST
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_REGINFO
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#else
+#if !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_CMD_ELF
#endif
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_MII
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#else
+#if !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_CMD_ELF
#endif
#endif
#define CONFIG_SUNXI_USB_PHYS 3
-#define CONFIG_NAND_SUNXI_GPC_PORTS {16, 17, 18, 19, 20, 21, 22, 24}
/*
* Include common sunxi configuration where most the settings are
#define CONFIG_SUNXI_USB_PHYS 2
-/* \todo A13 only defines port 19, whereas A10s requires each of these */
-#define CONFIG_NAND_SUNXI_GPC_PORTS {16, 17, 18, 19}
-
/*
* Include common sunxi configuration where most the settings are
*/
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
#define CONFIG_TIMER_CLK_FREQ 24000000
-#define CONFIG_NAND_SUNXI_GPC_PORTS {24, 25, 26}
-
/*
* Include common sunxi configuration where most the settings are
*/
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
#define CONFIG_TIMER_CLK_FREQ 24000000
-#define CONFIG_NAND_SUNXI_GPC_PORTS {16, 17, 18, 19, 20, 21, 22, 24}
-
/*
* Include common sunxi configuration where most the settings are
*/
#define CONFIG_ARMV7_PSCI 1
#if defined(CONFIG_MACH_SUN8I_A23)
#define CONFIG_ARMV7_PSCI_NR_CPUS 2
-#define CONFIG_NAND_SUNXI_GPC_PORTS {16, 17, 18}
#elif defined(CONFIG_MACH_SUN8I_A33)
#define CONFIG_ARMV7_PSCI_NR_CPUS 4
-#define CONFIG_NAND_SUNXI_GPC_PORTS {16}
#else
#error Unsupported sun8i variant
#endif
#define CONFIG_CMD_SCSI
#endif
-#define CONFIG_CMD_MEMORY
-
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_CMD_MMC
#define CONFIG_MMC_SUNXI
#define CONFIG_MMC_SUNXI_SLOT 0
-#if !defined(CONFIG_SPL_NAND_SUPPORT)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */
-#endif /* CONFIG_SPL_NAND_SUPPORT */
#endif
/* 4MB of malloc() pool */
/*
* Miscellaneous configurable options
*/
-#define CONFIG_CMD_ECHO
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_FPGA
-
#define CONFIG_FAT_WRITE /* enable write access */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_ENV_IS_NOWHERE
#endif
-#ifdef CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_NAND
-#define CONFIG_SYS_NAND_SELF_INIT
-#define CONFIG_NAND_SUNXI
-#define CONFIG_CMD_SPL_WRITE_SIZE 0x000400
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x008000
-
-/* \todo Make these parameterisable in kernel config ? */
-#define CONFIG_NAND_SUNXI_PAGE_SIZE 8192
-#define CONFIG_NAND_SUNXI_ECC_STEP 1024
-#define CONFIG_NAND_SUNXI_ECC_STRENGTH 40
-#define CONFIG_NAND_SUNXI_ADDR_CYCLES 5
-
-#ifndef CONFIG_NAND_SUNXI_GPC_PORTS
-#error "No NAND GPC ports defined, NAND unsupported"
-#endif
-#endif /* CONFIG_SPL_NAND_SUPPORT */
-
#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_ERRATA
#define CONFIG_USB_STORAGE
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC /* MMC support */
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
#define CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_FLASH /* only NAND on the SOM */
-#undef CONFIG_CMD_IMLS
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
+#define CONFIG_NAND_OMAP_GPMC_PREFETCH
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
-#undef CONFIG_CMD_IMLS /* List all found images */
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_OMAP34XX
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_SOURCE
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NAND
#define CONFIG_SPI
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
#define CONFIG_ATMEL_SPI
#define CONFIG_SPI_FLASH_STMICRO
#define TAURUS_SPI_MASK (1 << 4)
/*
* Command line configuration
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_PING
/* SPI */
#define CONFIG_TEGRA20_SLINK
#define CONFIG_TEGRA_SLINK_CTRLS 6
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
-/* include default commands */
-#include <config_cmd_default.h>
-
-/* remove unused commands */
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA /* FPGA configuration support */
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_NFS /* NFS support */
-
/* turn on command-line edit/hist/auto */
#define CONFIG_COMMAND_HISTORY
--- /dev/null
+/*
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_THUBAN_H
+#define __CONFIG_THUBAN_H
+
+#include "siemens-am33x-common.h"
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_MPUCLK 300
+#define DDR_PLL_FREQ 303
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+
+#define BOARD_DFU_BUTTON_GPIO 27 /* Use as default */
+#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */
+
+#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+ "button_dfu0=27\0" \
+ "led0=103,1,0\0" \
+ "led1=64,0,1\0"
+
+#undef CONFIG_DOS_PARTITION
+#undef CONFIG_CMD_FAT
+
+#define CONFIG_BOARD_LATE_INIT
+
+ /* Physical Memory Map */
+#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define EEPROM_ADDR_DDR3 0x90
+#define EEPROM_ADDR_CHIP 0x120
+
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300
+
+#undef CONFIG_SPL_NET_SUPPORT
+#undef CONFIG_SPL_NET_VCI_STRING
+#undef CONFIG_SPL_ETH_SUPPORT
+
+#undef CONFIG_MII
+#undef CONFIG_PHY_GIGE
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_FACTORYSET
+
+/* Watchdog */
+#define CONFIG_OMAP_WATCHDOG
+
+/* Define own nand partitions */
+#define CONFIG_ENV_OFFSET_REDUND 0x2E0000
+#define CONFIG_ENV_SIZE_REDUND 0x2000
+#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE)
+
+
+#define MTDPARTS_DEFAULT MTDPARTS_DEFAULT_V2
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Default env settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hostname=thuban\0" \
+ "nand_img_size=0x400000\0" \
+ "optargs=\0" \
+ "preboot=draco_led 0\0" \
+ CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+ CONFIG_ENV_SETTINGS_V2 \
+ CONFIG_ENV_SETTINGS_NAND_V2
+
+#ifndef CONFIG_RESTORE_FLASH
+/* set to negative value for no autoboot */
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_BOOTCOMMAND \
+"if dfubutton; then " \
+ "run dfu_start; " \
+ "reset; " \
+"fi;" \
+"run nand_boot;" \
+"run nand_boot_backup;" \
+"reset;"
+
+
+#else
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv autoload no; " \
+ "dhcp; " \
+ "if tftp 80000000 debrick.scr; then " \
+ "source 80000000; " \
+ "fi"
+#endif
+#endif /* CONFIG_SPL_BUILD */
+#endif /* ! __CONFIG_THUBAN_H */
#define CONFIG_INITRD_TAG /* for ramdisk support */
/* commands to include */
-# include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_VERSION_VARIABLE
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#define CONFIG_CMD_ECHO
-
/* max number of command args */
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG /* required for ramdisk support */
-#include <config_cmd_default.h> /* u-boot default commands */
-
#define CONFIG_VERSION_VARIABLE
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
#define CONFIG_CMD_ASKEN
-#define CONFIG_CMD_ECHO
#define CONFIG_OMAP_GPIO
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_MTDPARTS
#endif
-/*
- * For commands to use, we take the default list and add a few other
- * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH
- * prior to this include, in order to skip a few commands. When we do
- * have flash, if we expect these commands they must be enabled in that
- * config. If desired, a specific list of desired commands can be used
- * instead.
- */
-#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_ECHO
#define CONFIG_CMD_BOOTZ
#define CONFIG_SUPPORT_RAW_INITRD
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_EXT_SUPPORT
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */
#endif
/* General parts of the framework, required. */
"run netloadfdt; " \
"run netargs; " \
"bootz ${loadaddr} - ${fdtaddr}\0"
-
+#else
+#define NETARGS ""
#endif
#endif /* __CONFIG_TI_ARMV7_COMMON_H__ */
#define CONFIG_USB_TTY 1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-/* Per-Soc commands */
-#undef CONFIG_CMD_NFS
-
/*
* Environment setup
*/
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 << 20))
-/* SPL: Allow to use an EXT partition */
-#define CONFIG_SPL_EXT_SUPPORT
-
#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
#endif
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 48000000
-/* Per-SoC commands */
-#undef CONFIG_CMD_NFS
-
/*
* Environment setup
*/
#define DFUARGS
#endif
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"setenv mmcroot /dev/mmcblk0p2 rw; " \
"run mmcboot;" \
""
+#endif
/*
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
-#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_EXT2
#define CONFIG_MXC_SPI
/* SPI Flash */
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K
/* Command definition */
#define CONFIG_CMD_BMODE
-#define CONFIG_CMD_ITEST
#define CONFIG_ENV_SIZE (SZ_8K)
/* Size of malloc() pool */
#define CONFIG_SYS_NAND_MAX_ECCPOS 56
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_UBIFS /* UBIFS commands */
#define CONFIG_LZO /* LZO is needed for UBIFS */
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_JFFS2 /* JFFS2 Support */
/* needed for ubi */
/* SPI */
#define CONFIG_TEGRA20_SFLASH
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_CMD_SPI
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_FAT
-#define CONFIG_CMD_IMLS
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
"kernel=zImage\0" \
"ramdisk=rootfs.cpio.uboot\0" \
"console=ttyO0,115200n8\0" \
-"optargs=consoleblank=0 quiet lpj=1191936 panic=2\0" \
+"optargs=consoleblank=0 quiet panic=2\0" \
"nfsroot=/tftpboot/tseries/rootfs-small\0" \
"nfsopts=nolock\0" \
"ramargs=setenv bootargs ${optargs} console=${console} root=/dev/ram0\0" \
#define CONFIG_OMAP3_SPI
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SF_DEFAULT_SPEED 24000000
/*
* Command definition
*/
-
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_NAND
/*
* #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support
#define CONFIG_SYS_LONGHELP
/* U-Boot commands */
-#include <config_cmd_default.h>
#define CONFIG_CMD_NAND
#define CONFIG_CMD_CACHE
/*
* Commands
*/
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MMC
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_SOURCE
#define CONFIG_CMD_I2C
#ifndef CONFIG_BOOTDELAY
#define CONFIG_MMC_DEV_NUM 1
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_SAVEENV /* CMD_ENV is obsolete but used in env_emmc.c */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET 0x13F80000
#define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_ITEST
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NAND
#define CONFIG_MXC_GPIO
#include <asm/arch/imx-regs.h>
-#include <config_cmd_default.h>
#include <config_distro_defaults.h>
/* U-Boot commands */
#define CONFIG_CMD_MEMTEST
-#undef CONFIG_CMD_IMLS
/* U-Boot environment */
#define CONFIG_ENV_OVERWRITE
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
/*
* Commands
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EEPROM
!defined(CONFIG_VCT_SMALL_IMAGE)
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
-#else
-#undef CONFIG_CMD_NFS
#endif
/*
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
#endif /* CONFIG_CMD_USB */
-#if !defined(CONFIG_VCT_NOR)
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#endif
-
#if defined(CONFIG_VCT_NAND)
#define CONFIG_CMD_NAND
#endif
*/
#if defined(CONFIG_VCT_SMALL_IMAGE)
#undef CONFIG_CMD_ASKENV
-#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_BEDBUG
#undef CONFIG_CMD_CACHE
-#undef CONFIG_CMD_CONSOLE
#undef CONFIG_CMD_DHCP
#undef CONFIG_CMD_EEPROM
#undef CONFIG_CMD_EEPROM
#undef CONFIG_CMD_I2C
#undef CONFIG_CMD_I2C
#undef CONFIG_CMD_IRQ
-#undef CONFIG_CMD_ITEST
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADY
#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_MISC
#undef CONFIG_CMD_PING
#undef CONFIG_CMD_REGINFO
#undef CONFIG_CMD_SNTP
-#undef CONFIG_CMD_SOURCE
#undef CONFIG_CMD_STRINGS
#undef CONFIG_CMD_TERMINAL
#undef CONFIG_CMD_USB
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
/* SPI */
#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */
#define CONFIG_TEGRA114_SPI_CTRLS 6
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
/*
* Command line configuration.
*/
-#define CONFIG_CMD_BDI
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVEENV
/*
* BOOTP options
/* We use generic board and device manager for v8 Versatile Express */
#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_DM
#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#ifndef CONFIG_SEMIHOSTING
#endif /* !CONFIG_GICV3 */
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_F_LEN 0x2000
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
/* Ethernet Configuration */
#endif
/* PL011 Serial Configuration */
-#define CONFIG_DM_SERIAL
#define CONFIG_BAUDRATE 115200
#define CONFIG_CONS_INDEX 0
#define CONFIG_PL01X_SERIAL
#define CONFIG_MENU
/*#define CONFIG_MENU_SHOW*/
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_BDI
#define CONFIG_CMD_BOOTI
#define CONFIG_CMD_UNZIP
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PXE
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_SOURCE
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_SYS_NO_FLASH
#else
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_ARMFLASH
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_SERIAL1 V2M_UART1
/* Command line configuration */
-#define CONFIG_CMD_BDI
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PXE
#define CONFIG_MENU
#define CONFIG_CMD_ELF
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_RUN
#define CONFIG_CMD_BOOTZ
#define CONFIG_SUPPORT_RAW_INITRD
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
-#define CONFIG_CMD_SOURCE
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_SYS_MAXARGS 16 /* max command args */
#define __CONFIG_H
#include <asm/arch/imx-regs.h>
-#include <config_cmd_default.h>
#define CONFIG_VF610
#define CONFIG_SYS_UART_PORT (1)
#define CONFIG_BAUDRATE 115200
-#undef CONFIG_CMD_IMLS
-
/* NAND support */
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
#ifdef CONFIG_FSL_QSPI
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
#define CONFIG_FSL_SF
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
/*
* Command definition
***********************************************************/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_SPI
-#undef CONFIG_CMD_IMLS
#define CONFIG_BOOTDELAY 3
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_LOADS
-
#define CONFIG_CMD_BMP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_ENV
- #undef CONFIG_CMD_LOADS
#endif
#define CONFIG_CMD_ELF
/*
* Bootloader Components Configuration
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ENV
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_MMC
#define CONFIG_CMD_USB
#undef CONFIG_LCD
#define CONFIG_CMD_IDE
#ifdef CONFIG_ONENAND
-#undef CONFIG_CMD_FLASH
#define CONFIG_CMD_ONENAND
#else
-#define CONFIG_CMD_FLASH
#undef CONFIG_CMD_ONENAND
#endif
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
#define CONFIG_SUPPORT_EMMC_BOOT
-/* Command definition */
-#undef CONFIG_CMD_NFS
-
/* Watchdog */
#define CONFIG_HW_WATCHDOG
#define CONFIG_IMX_WATCHDOG
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* no NOR or SPI flash */
-#include <config_cmd_default.h>
#define CONFIG_CMD_ENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
/*
* Command definition
*/
-
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_ENV_OFFSET_REDUND 0x00120000
#define CONFIG_ENV_ADDR 0x80000100
-/*
- * U-Boot Commands
- */
-#include <config_cmd_default.h>
-
/*
* Boot Linux
*/
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MII
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
-#define CONFIG_CMD_RUN
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_LZO
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <config_cmd_default.h>
-
#define CONFIG_BOOTDELAY 3
#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
/*-----------------------------------------------------------------------
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_ECHO
-#undef CONFIG_CMD_FLASH
-#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_GPIO
-#define CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_IO
#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ITEST
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-#undef CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_SETGETDCR
-#define CONFIG_CMD_SOURCE
#define CONFIG_CMD_TIME
#define CONFIG_CMD_GETTIME
-#define CONFIG_CMD_XIMG
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_FAT
* FLASH configuration
*/
#define CONFIG_ICH_SPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_MACRONIX
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SPI_FLASH_GIGADEVICE
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
/*Cmd*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DIAG
#undef CONFIG_CMD_PING
#undef CONFIG_CMD_DHCP
#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_NFS
/*Misc*/
#define CONFIG_BOOTDELAY 5/* autoboot after 5 seconds */
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_MEMORY
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_ELF
#define CONFIG_MP
/* SPI */
#ifdef CONFIG_ZYNQ_SPI
-# define CONFIG_SPI_FLASH
# define CONFIG_SPI_FLASH_SST
# define CONFIG_CMD_SF
#endif
/*
* Command configuration
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SNTP
/*
/*
* Command configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_JFFS2
/*
* Command configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
/*
* Command configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PCI_ENUM
#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_REGINFO
/*
* Command configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_PCI_ENUM
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
/*
* Bootloader Components Configuration
*/
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_NFS
#define CONFIG_CMD_ENV
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_MMC
#define CONFIG_CMD_SPI
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
/*
/* SPI */
#ifdef CONFIG_ZYNQ_SPI
-# define CONFIG_SPI_FLASH
# define CONFIG_SPI_FLASH_SST
# define CONFIG_CMD_SF
#endif
# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
# define CONFIG_ENV_OFFSET 0xE0000
-# define CONFIG_CMD_SAVEENV
#endif
/* Default environment */
#define CONFIG_FPGA
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_ZYNQPL
-#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_FPGA_LOADP
#define CONFIG_CMD_FPGA_LOADBP
#define CONFIG_SYS_LDSCRIPT "arch/arm/mach-zynq/u-boot.lds"
/* Commands */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
int del_mtd_device(struct mtd_info *mtd);
int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int);
int del_mtd_partitions(struct mtd_info *);
+
+int mtd_arg_off(const char *arg, int *idx, loff_t *off, loff_t *size,
+ loff_t *maxsize, int devtype, int chipsize);
+int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off,
+ loff_t *size, loff_t *maxsize, int devtype, int chipsize);
#endif
#endif /* __MTD_MTD_H__ */
--- /dev/null
+/* include/samsung-usb-phy-uboot.h
+ *
+ * Copyright (c) 2015 Samsung Electronics
+ *
+ * USB3 (DWC3) PHY uboot init
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SAMSUNG_USB_PHY_UBOOT_H_
+#define __SAMSUNG_USB_PHY_UBOOT_H_
+
+#include <asm/arch/xhci-exynos.h>
+
+void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy);
+#endif /* __SAMSUNG_USB_PHY_UBOOT_H_ */
#define SCSI_MED_REMOVL 0x1E /* Prevent/Allow medium Removal (O) */
#define SCSI_READ6 0x08 /* Read 6-byte (MANDATORY) */
#define SCSI_READ10 0x28 /* Read 10-byte (MANDATORY) */
+#define SCSI_READ16 0x48
#define SCSI_RD_CAPAC 0x25 /* Read Capacity (MANDATORY) */
#define SCSI_RD_CAPAC10 SCSI_RD_CAPAC /* Read Capacity (10) */
#define SCSI_RD_CAPAC16 0x9e /* Read Capacity (16) */
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
-#define SPI_DEFAULT_WORDLEN 8
+#define SPI_DEFAULT_WORDLEN 8
#ifdef CONFIG_DM_SPI
/* TODO(sjg@chromium.org): Remove this and use max_hz from struct spi_slave */
* struct spi_flash - SPI flash structure
*
* @spi: SPI slave
+ * @dev: SPI flash device
+ * @flags: Indication of spi flash flags
* @name: Name of SPI flash
- * @dual_flash: Indicates dual flash memories - dual stacked, parallel
+ * @dual_flash: Indicates dual flash memories - dual stacked, parallel
* @shift: Flash shift useful in dual parallel
* @size: Total flash size
* @page_size: Write (page) size
* @sector_size: Sector size
- * @erase_size: Erase size
+ * @erase_size: Erase size
* @bank_read_cmd: Bank read cmd
* @bank_write_cmd: Bank write cmd
* @bank_curr: Current flash bank
* @erase_cmd: Erase cmd 4K, 32K, 64K
* @read_cmd: Read cmd - Array Fast, Extn read and quad read.
* @write_cmd: Write cmd - page and quad program.
- * @dummy_byte: Dummy cycles for read operation.
- * @memory_map: Address of read-only SPI flash access
+ * @dummy_byte: Dummy cycles for read operation.
+ * @memory_map: Address of read-only SPI flash access
* @read: Flash read ops: Read len bytes at offset into buf
* Supported cmds: Fast Array Read
* @write: Flash write ops: Write len bytes from buf into offset
* this is how the lowlevel part communicate with the outer world
*/
-#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \
- defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_OHCI_NEW) || \
- defined(CONFIG_USB_SL811HS) || defined(CONFIG_USB_ISP116X_HCD) || \
- defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI) || \
- defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \
- defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X) || \
- defined(CONFIG_USB_MUSB_DSPS) || defined(CONFIG_USB_MUSB_AM35X) || \
- defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_MUSB_SUNXI) || \
- defined(CONFIG_USB_XHCI) || defined(CONFIG_USB_DWC2) || \
- defined(CONFIG_USB_EMUL)
-
int usb_lowlevel_init(int index, enum usb_init_type init, void **controller);
int usb_lowlevel_stop(int index);
* in boards init functions e.g. udc_disconnect() used for
* forced device disconnection from host.
*/
-#elif defined(CONFIG_USB_GADGET_PXA2XX)
-
extern void udc_disconnect(void);
-#endif
-
/*
* board-specific hardware initialization, called by
* usb drivers and u-boot commands
*/
void print_grouped_ull(unsigned long long int_val, int digits);
+bool str2off(const char *p, loff_t *num);
+bool str2long(const char *p, ulong *num);
#endif
grab = 3;
}
}
+
+bool str2off(const char *p, loff_t *num)
+{
+ char *endptr;
+
+ *num = simple_strtoull(p, &endptr, 16);
+ return *p != '\0' && *endptr == '\0';
+}
+
+bool str2long(const char *p, ulong *num)
+{
+ char *endptr;
+
+ *num = simple_strtoul(p, &endptr, 16);
+ return *p != '\0' && *endptr == '\0';
+}
If the environment variable 'srctree' was set when the Config was
created, get_defconfig_filename() will first look relative to that
directory before looking in the current directory; see
- Config.__init__()."""
+ Config.__init__().
+
+ WARNING: A wart here is that scripts/kconfig/Makefile sometimes uses the
+ --defconfig=<defconfig> option when calling the C implementation of e.g.
+ 'make defconfig'. This option overrides the 'option defconfig_list'
+ symbol, meaning the result from get_defconfig_filename() might not
+ match what 'make defconfig' would use. That probably ought to be worked
+ around somehow, so that this function always gives the "expected"
+ result."""
if self.defconfig_sym is None:
return None
For example, if FOO and BAR are tristate symbols at least one of which
has the value "y", then config.eval("y && (FOO || BAR)") => "y"
- This functions always yields a tristate value. To get the value of
+ This function always yields a tristate value. To get the value of
non-bool, non-tristate symbols, use Symbol.get_value().
The result of this function is consistent with how evaluation works for
choice.block = self._parse_block(line_feeder,
T_ENDCHOICE,
choice,
- None,
+ deps,
visible_if_deps)
choice._determine_actual_symbols()
elif tokens.check(T_MODULES):
self._warn("the 'modules' option is not supported. "
"Let me know if this is a problem for you; "
- "it shouldn't be that hard to implement.",
+ "it shouldn't be that hard to implement. "
+ "(Note that modules are still supported -- "
+ "Kconfiglib just assumes the symbol name "
+ "MODULES.)",
filename,
linenr)
+ elif tokens.check(T_ALLNOCONFIG_Y):
+ if not isinstance(stmt, Symbol):
+ _parse_error(line,
+ "the 'allnoconfig_y' option is only valid for symbols.",
+ filename,
+ linenr)
+ stmt.allnoconfig_y = True
+
else:
_parse_error(line, "unrecognized option.", filename, linenr)
T_OPTIONAL, T_PROMPT, T_DEFAULT,
T_BOOL, T_TRISTATE, T_HEX, T_INT, T_STRING,
T_DEF_BOOL, T_DEF_TRISTATE,
- T_SELECT, T_RANGE, T_OPTION, T_ENV,
- T_DEFCONFIG_LIST, T_MODULES, T_VISIBLE) = range(0, 38)
+ T_SELECT, T_RANGE, T_OPTION, T_ALLNOCONFIG_Y, T_ENV,
+ T_DEFCONFIG_LIST, T_MODULES, T_VISIBLE) = range(0, 39)
# Keyword to token map
keywords = {
"select" : T_SELECT,
"range" : T_RANGE,
"option" : T_OPTION,
+ "allnoconfig_y" : T_ALLNOCONFIG_Y,
"env" : T_ENV,
"defconfig_list" : T_DEFCONFIG_LIST,
"modules" : T_MODULES,
unset_re = re.compile(r"# CONFIG_(\w+) is not set")
# Regular expression for finding $-references to symbols in strings
-sym_ref_re = re.compile(r"\$[A-Za-z_]+")
+sym_ref_re = re.compile(r"\$[A-Za-z0-9_]+")
# Integers representing symbol types
UNKNOWN, BOOL, TRISTATE, STRING, HEX, INT = range(0, 6)
and sym.get_parent().get_selection() is sym'."""
return self.is_choice_symbol_ and self.parent.get_selection() is self
+ def is_allnoconfig_y(self):
+ """Returns True if the symbol has the 'allnoconfig_y' option set;
+ otherwise, returns False."""
+ return self.allnoconfig_y
+
def __str__(self):
"""Returns a string containing various information about the symbol."""
return self.config._get_sym_or_choice_str(self)
# Does the symbol get its value from the environment?
self.is_from_env = False
+ # Does the symbol have the 'allnoconfig_y' option set?
+ self.allnoconfig_y = False
+
def _invalidate(self):
if self.is_special_:
return
*/
/* Pull in the current config to define the default environment */
+#include <linux/kconfig.h>
+
#ifndef __ASSEMBLY__
#define __ASSEMBLY__ /* get only #defines from config.h */
#include <config.h>
#else
#include <config.h>
#endif
-#include <generated/autoconf.h>
/*
* To build the utility with the static configuration
*hasext = 1;
}
+#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS)
+ if (headersz > CONFIG_SYS_SPI_U_BOOT_OFFS) {
+ fprintf(stderr, "Error: Image header (incl. SPL image) too big!\n");
+ fprintf(stderr, "header=0x%x CONFIG_SYS_SPI_U_BOOT_OFFS=0x%x!\n",
+ (int)headersz, CONFIG_SYS_SPI_U_BOOT_OFFS);
+ fprintf(stderr, "Increase CONFIG_SYS_SPI_U_BOOT_OFFS!\n");
+ return 0;
+ } else {
+ headersz = CONFIG_SYS_SPI_U_BOOT_OFFS;
+ }
+#endif
+
/*
* The payload should be aligned on some reasonable
* boundary
sizeof(struct ext_hdr_v0);
} else {
alloc_len = image_headersz_v1(params, NULL);
-#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS)
- if (alloc_len > CONFIG_SYS_SPI_U_BOOT_OFFS) {
- fprintf(stderr, "Error: Image header (incl. SPL image) too big!\n");
- fprintf(stderr, "header=0x%x CONFIG_SYS_SPI_U_BOOT_OFFS=0x%x!\n",
- alloc_len, CONFIG_SYS_SPI_U_BOOT_OFFS);
- fprintf(stderr, "Increase CONFIG_SYS_SPI_U_BOOT_OFFS!\n");
- } else {
- alloc_len = CONFIG_SYS_SPI_U_BOOT_OFFS;
- }
-#endif
}
hdr = malloc(alloc_len);
kwboot_usage(FILE *stream, char *progname)
{
fprintf(stream,
- "Usage: %s [-d | -a | -b <image> | -D <image> ] [ -t ] [-B <baud> ] <TTY>\n",
+ "Usage: %s [-d | -a | -q <req-delay> | -s <resp-timeo> | -b <image> | -D <image> ] [ -t ] [-B <baud> ] <TTY>\n",
progname);
fprintf(stream, "\n");
fprintf(stream,
" -D <image>: boot <image> without preamble (Dove)\n");
fprintf(stream, " -d: enter debug mode\n");
fprintf(stream, " -a: use timings for Armada XP\n");
+ fprintf(stream, " -q <req-delay>: use specific request-delay\n");
+ fprintf(stream, " -s <resp-timeo>: use specific response-timeout\n");
fprintf(stream, "\n");
fprintf(stream, " -t: mini terminal\n");
fprintf(stream, "\n");
kwboot_verbose = isatty(STDOUT_FILENO);
do {
- int c = getopt(argc, argv, "hb:ptaB:dD:");
+ int c = getopt(argc, argv, "hb:ptaB:dD:q:s:");
if (c < 0)
break;
msg_rsp_timeo = KWBOOT_MSG_RSP_TIMEO_AXP;
break;
+ case 'q':
+ msg_req_delay = atoi(optarg);
+ break;
+
+ case 's':
+ msg_rsp_timeo = atoi(optarg);
+ break;
+
case 'B':
speed = kwboot_tty_speed(atoi(optarg));
if (speed == -1)
projects / u-boot / commitdiff