#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35)
#include <asm/arch/imx-regs.h>
#endif
+#include <fsl_nfc.h>
#define DRIVER_NAME "mxc_nand"
-/*
- * TODO: Use same register defs here as nand_spl mxc nand driver.
- */
-/*
- * Register map and bit definitions for the Freescale NAND Flash Controller
- * present in various i.MX devices.
- *
- * MX31 and MX27 have version 1 which has
- * 4 512 byte main buffers and
- * 4 16 byte spare buffers
- * to support up to 2K byte pagesize nand.
- * Reading or writing a 2K page requires 4 FDI/FDO cycles.
- *
- * MX25 has version 1.1 which has
- * 8 512 byte main buffers and
- * 8 64 byte spare buffers
- * to support up to 4K byte pagesize nand.
- * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
- * Also some of registers are moved and/or changed meaning as seen below.
- */
-#if defined(CONFIG_MX31) || defined(CONFIG_MX27)
-#define MXC_NFC_V1
-#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
-#define MXC_NFC_V1_1
-#else
-#warning "MXC NFC version not defined"
-#endif
-
-#if defined(MXC_NFC_V1)
-#define NAND_MXC_NR_BUFS 4
-#define NAND_MXC_SPARE_BUF_SIZE 16
-#define NAND_MXC_REG_OFFSET 0xe00
-#define is_mxc_nfc_11() 0
-#elif defined(MXC_NFC_V1_1)
-#define NAND_MXC_NR_BUFS 8
-#define NAND_MXC_SPARE_BUF_SIZE 64
-#define NAND_MXC_REG_OFFSET 0x1e00
-#define is_mxc_nfc_11() 1
-#else
-#error "define CONFIG_NAND_MXC_VXXX to use mtd mxc nand driver"
-#endif
-struct nfc_regs {
- uint8_t main_area[NAND_MXC_NR_BUFS][0x200];
- uint8_t spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
- /*
- * reserved size is offset of nfc registers
- * minus total main and spare sizes
- */
- uint8_t reserved1[NAND_MXC_REG_OFFSET
- - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
-#if defined(MXC_NFC_V1)
- uint16_t nfc_buf_size;
- uint16_t reserved2;
- uint16_t nfc_buf_addr;
- uint16_t nfc_flash_addr;
- uint16_t nfc_flash_cmd;
- uint16_t nfc_config;
- uint16_t nfc_ecc_status_result;
- uint16_t nfc_rsltmain_area;
- uint16_t nfc_rsltspare_area;
- uint16_t nfc_wrprot;
- uint16_t nfc_unlockstart_blkaddr;
- uint16_t nfc_unlockend_blkaddr;
- uint16_t nfc_nf_wrprst;
- uint16_t nfc_config1;
- uint16_t nfc_config2;
-#elif defined(MXC_NFC_V1_1)
- uint16_t reserved2[2];
- uint16_t nfc_buf_addr;
- uint16_t nfc_flash_addr;
- uint16_t nfc_flash_cmd;
- uint16_t nfc_config;
- uint16_t nfc_ecc_status_result;
- uint16_t nfc_ecc_status_result2;
- uint16_t nfc_spare_area_size;
- uint16_t nfc_wrprot;
- uint16_t reserved3[2];
- uint16_t nfc_nf_wrprst;
- uint16_t nfc_config1;
- uint16_t nfc_config2;
- uint16_t reserved4;
- uint16_t nfc_unlockstart_blkaddr;
- uint16_t nfc_unlockend_blkaddr;
- uint16_t nfc_unlockstart_blkaddr1;
- uint16_t nfc_unlockend_blkaddr1;
- uint16_t nfc_unlockstart_blkaddr2;
- uint16_t nfc_unlockend_blkaddr2;
- uint16_t nfc_unlockstart_blkaddr3;
- uint16_t nfc_unlockend_blkaddr3;
-#endif
-};
-
-/*
- * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
- * for Command operation
- */
-#define NFC_CMD 0x1
-
-/*
- * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
- * for Address operation
- */
-#define NFC_ADDR 0x2
-
-/*
- * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
- * for Input operation
- */
-#define NFC_INPUT 0x4
-
-/*
- * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
- * for Data Output operation
- */
-#define NFC_OUTPUT 0x8
-
-/*
- * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
- * for Read ID operation
- */
-#define NFC_ID 0x10
-
-/*
- * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
- * for Read Status operation
- */
-#define NFC_STATUS 0x20
-
-/*
- * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
- * Status operation
- */
-#define NFC_INT 0x8000
-
-#ifdef MXC_NFC_V1_1
-#define NFC_4_8N_ECC (1 << 0)
-#else
-#define NFC_4_8N_ECC 0
-#endif
-#define NFC_SP_EN (1 << 2)
-#define NFC_ECC_EN (1 << 3)
-#define NFC_BIG (1 << 5)
-#define NFC_RST (1 << 6)
-#define NFC_CE (1 << 7)
-#define NFC_ONE_CYCLE (1 << 8)
-
typedef enum {false, true} bool;
struct mxc_nand_host {
- struct mtd_info mtd;
- struct nand_chip *nand;
-
- struct nfc_regs __iomem *regs;
- int spare_only;
- int status_request;
- int pagesize_2k;
- int clk_act;
- uint16_t col_addr;
- unsigned int page_addr;
+ struct mtd_info mtd;
+ struct nand_chip *nand;
+
+ struct fsl_nfc_regs __iomem *regs;
+ int spare_only;
+ int status_request;
+ int pagesize_2k;
+ int clk_act;
+ uint16_t col_addr;
+ unsigned int page_addr;
};
static struct mxc_nand_host mxc_host;
uint32_t tmp;
while (max_retries-- > 0) {
- if (readw(&host->regs->nfc_config2) & NFC_INT) {
- tmp = readw(&host->regs->nfc_config2);
+ if (readw(&host->regs->config2) & NFC_INT) {
+ tmp = readw(&host->regs->config2);
tmp &= ~NFC_INT;
- writew(tmp, &host->regs->nfc_config2);
+ writew(tmp, &host->regs->config2);
break;
}
udelay(1);
{
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
- writew(cmd, &host->regs->nfc_flash_cmd);
- writew(NFC_CMD, &host->regs->nfc_config2);
+ writew(cmd, &host->regs->flash_cmd);
+ writew(NFC_CMD, &host->regs->config2);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, cmd);
{
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
- writew(addr, &host->regs->nfc_flash_addr);
- writew(NFC_ADDR, &host->regs->nfc_config2);
+ writew(addr, &host->regs->flash_addr);
+ writew(NFC_ADDR, &host->regs->config2);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, addr);
}
}
- writew(buf_id, &host->regs->nfc_buf_addr);
+ writew(buf_id, &host->regs->buf_addr);
/* Configure spare or page+spare access */
if (!host->pagesize_2k) {
- uint16_t config1 = readw(&host->regs->nfc_config1);
+ uint16_t config1 = readw(&host->regs->config1);
if (spare_only)
config1 |= NFC_SP_EN;
else
config1 &= ~(NFC_SP_EN);
- writew(config1, &host->regs->nfc_config1);
+ writew(config1, &host->regs->config1);
}
- writew(NFC_INPUT, &host->regs->nfc_config2);
+ writew(NFC_INPUT, &host->regs->config2);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, spare_only);
{
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
- writew(buf_id, &host->regs->nfc_buf_addr);
+ writew(buf_id, &host->regs->buf_addr);
/* Configure spare or page+spare access */
if (!host->pagesize_2k) {
- uint32_t config1 = readw(&host->regs->nfc_config1);
+ uint32_t config1 = readw(&host->regs->config1);
if (spare_only)
config1 |= NFC_SP_EN;
else
config1 &= ~NFC_SP_EN;
- writew(config1, &host->regs->nfc_config1);
+ writew(config1, &host->regs->config1);
}
- writew(NFC_OUTPUT, &host->regs->nfc_config2);
+ writew(NFC_OUTPUT, &host->regs->config2);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, spare_only);
uint16_t tmp;
/* NANDFC buffer 0 is used for device ID output */
- writew(0x0, &host->regs->nfc_buf_addr);
+ writew(0x0, &host->regs->buf_addr);
/* Read ID into main buffer */
- tmp = readw(&host->regs->nfc_config1);
+ tmp = readw(&host->regs->config1);
tmp &= ~NFC_SP_EN;
- writew(tmp, &host->regs->nfc_config1);
+ writew(tmp, &host->regs->config1);
- writew(NFC_ID, &host->regs->nfc_config2);
+ writew(NFC_ID, &host->regs->config2);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, 0);
/* store the main area1 first word, later do recovery */
store = readl(main_buf);
/* NANDFC buffer 1 is used for device status */
- writew(1, &host->regs->nfc_buf_addr);
+ writew(1, &host->regs->buf_addr);
/* Read status into main buffer */
- tmp = readw(&host->regs->nfc_config1);
+ tmp = readw(&host->regs->config1);
tmp &= ~NFC_SP_EN;
- writew(tmp, &host->regs->nfc_config1);
+ writew(tmp, &host->regs->config1);
- writew(NFC_STATUS, &host->regs->nfc_config2);
+ writew(NFC_STATUS, &host->regs->config2);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, 0);
{
struct nand_chip *nand_chip = mtd->priv;
struct mxc_nand_host *host = nand_chip->priv;
- uint16_t tmp = readw(&host->regs->nfc_config1);
+ uint16_t tmp = readw(&host->regs->config1);
if (on)
tmp |= NFC_ECC_EN;
else
tmp &= ~NFC_ECC_EN;
- writew(tmp, &host->regs->nfc_config1);
+ writew(tmp, &host->regs->config1);
}
static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
{
struct nand_chip *nand_chip = mtd->priv;
struct mxc_nand_host *host = nand_chip->priv;
- uint16_t ecc_status = readw(&host->regs->nfc_ecc_status_result);
+ uint16_t ecc_status = readw(&host->regs->ecc_status_result);
int subpages = mtd->writesize / nand_chip->subpagesize;
int pg2blk_shift = nand_chip->phys_erase_shift -
nand_chip->page_shift;
* additional correction. 2-Bit errors cannot be corrected by
* HW ECC, so we need to return failure
*/
- uint16_t ecc_status = readw(&host->regs->nfc_ecc_status_result);
+ uint16_t ecc_status = readw(&host->regs->ecc_status_result);
if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
MTDDEBUG(MTD_DEBUG_LEVEL0,
{
uint16_t tmp;
- tmp = readw(&host->regs->nfc_config1);
+ tmp = readw(&host->regs->config1);
tmp |= NFC_ONE_CYCLE;
tmp |= NFC_4_8N_ECC;
- writew(tmp, &host->regs->nfc_config1);
+ writew(tmp, &host->regs->config1);
if (host->pagesize_2k)
- writew(64/2, &host->regs->nfc_spare_area_size);
+ writew(64/2, &host->regs->spare_area_size);
else
- writew(16/2, &host->regs->nfc_spare_area_size);
+ writew(16/2, &host->regs->spare_area_size);
}
#else
#define mxc_setup_config1()
this->read_buf = mxc_nand_read_buf;
this->verify_buf = mxc_nand_verify_buf;
- host->regs = (struct nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
+ host->regs = (struct fsl_nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
host->clk_act = 1;
#ifdef CONFIG_MXC_NAND_HWECC
host->pagesize_2k = 0;
this->ecc.size = 512;
- tmp = readw(&host->regs->nfc_config1);
+ tmp = readw(&host->regs->config1);
tmp |= NFC_ECC_EN;
- writew(tmp, &host->regs->nfc_config1);
+ writew(tmp, &host->regs->config1);
#else
this->ecc.layout = &nand_soft_eccoob;
this->ecc.mode = NAND_ECC_SOFT;
- tmp = readw(&host->regs->nfc_config1);
+ tmp = readw(&host->regs->config1);
tmp &= ~NFC_ECC_EN;
- writew(tmp, &host->regs->nfc_config1);
+ writew(tmp, &host->regs->config1);
#endif
/* Reset NAND */
this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
* preset operation
* Unlock the internal RAM Buffer
*/
- writew(0x2, &host->regs->nfc_config);
+ writew(0x2, &host->regs->config);
/* Blocks to be unlocked */
- writew(0x0, &host->regs->nfc_unlockstart_blkaddr);
+ writew(0x0, &host->regs->unlockstart_blkaddr);
/* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
* unlockend_blkaddr, but the magic 0x4000 does not always work
* when writing more than some 32 megabytes (on 2k page nands)
* This might be NAND chip specific and the i.MX31 datasheet is
* extremely vague about the semantics of this register.
*/
- writew(0xFFFF, &host->regs->nfc_unlockend_blkaddr);
+ writew(0xFFFF, &host->regs->unlockend_blkaddr);
/* Unlock Block Command for given address range */
- writew(0x4, &host->regs->nfc_wrprot);
+ writew(0x4, &host->regs->wrprot);
/* NAND bus width determines access functions used by upper layer */
if (is_16bit_nand())
#define __FSL_NFC_H
/*
- * TODO: Use same register defs for nand_spl mxc nand driver
- * and mtd mxc nand driver.
+ * Register map and bit definitions for the Freescale NAND Flash Controller
+ * present in various i.MX devices.
*
- * Register map and bit definitions for the Freescale NAND Flash
- * Controller present in various i.MX devices.
+ * MX31 and MX27 have version 1, which has:
+ * 4 512-byte main buffers and
+ * 4 16-byte spare buffers
+ * to support up to 2K byte pagesize nand.
+ * Reading or writing a 2K page requires 4 FDI/FDO cycles.
*
- * MX31 and MX27 have version 1 which has
- * 4 512 byte main buffers and
- * 4 16 byte spare buffers
- * to support up to 2K byte pagesize nand.
- * Reading or writing a 2K page requires 4 FDI/FDO cycles.
- *
- * MX25 has version 1.1 which has
- * 8 512 byte main buffers and
- * 8 64 byte spare buffers
- * to support up to 4K byte pagesize nand.
- * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
- * Also some of registers are moved and/or changed meaning as seen below.
+ * MX25 and MX35 have version 1.1, which has:
+ * 8 512-byte main buffers and
+ * 8 64-byte spare buffers
+ * to support up to 4K byte pagesize nand.
+ * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
+ * Also some of registers are moved and/or changed meaning as seen below.
*/
-#if defined(CONFIG_MX31) || defined(CONFIG_MX27)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX31)
#define MXC_NFC_V1
-#elif defined(CONFIG_MX25)
+#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
#define MXC_NFC_V1_1
#else
#warning "MXC NFC version not defined"
#define NAND_MXC_NR_BUFS 4
#define NAND_MXC_SPARE_BUF_SIZE 16
#define NAND_MXC_REG_OFFSET 0xe00
-#define NAND_MXC_2K_MULTI_CYCLE 1
+#define NAND_MXC_2K_MULTI_CYCLE
+#define is_mxc_nfc_11() 0
#elif defined(MXC_NFC_V1_1)
#define NAND_MXC_NR_BUFS 8
#define NAND_MXC_SPARE_BUF_SIZE 64
#define NAND_MXC_REG_OFFSET 0x1e00
+#define is_mxc_nfc_11() 1
#else
-#error "define CONFIG_NAND_MXC_VXXX to use the mxc spl_nand driver"
+#error "define CONFIG_NAND_MXC_VXXX to use the mxc nand driver"
#endif
struct fsl_nfc_regs {
- u32 main_area[NAND_MXC_NR_BUFS][512/4];
- u32 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE/4];
+ u8 main_area[NAND_MXC_NR_BUFS][0x200];
+ u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
/*
* reserved size is offset of nfc registers
* minus total main and spare sizes
u8 reserved1[NAND_MXC_REG_OFFSET
- NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
#if defined(MXC_NFC_V1)
- u16 bufsiz;
+ u16 buf_size;
u16 reserved2;
- u16 buffer_address;
- u16 flash_add;
+ u16 buf_addr;
+ u16 flash_addr;
u16 flash_cmd;
- u16 configuration;
+ u16 config;
u16 ecc_status_result;
- u16 ecc_rslt_main_area;
- u16 ecc_rslt_spare_area;
- u16 nf_wr_prot;
- u16 unlock_start_blk_add;
- u16 unlock_end_blk_add;
- u16 nand_flash_wr_pr_st;
- u16 nand_flash_config1;
- u16 nand_flash_config2;
+ u16 rsltmain_area;
+ u16 rsltspare_area;
+ u16 wrprot;
+ u16 unlockstart_blkaddr;
+ u16 unlockend_blkaddr;
+ u16 nf_wrprst;
+ u16 config1;
+ u16 config2;
#elif defined(MXC_NFC_V1_1)
u16 reserved2[2];
- u16 buffer_address;
- u16 flash_add;
+ u16 buf_addr;
+ u16 flash_addr;
u16 flash_cmd;
- u16 configuration;
+ u16 config;
u16 ecc_status_result;
u16 ecc_status_result2;
u16 spare_area_size;
- u16 nf_wr_prot;
+ u16 wrprot;
u16 reserved3[2];
- u16 nand_flash_wr_pr_st;
- u16 nand_flash_config1;
- u16 nand_flash_config2;
+ u16 nf_wrprst;
+ u16 config1;
+ u16 config2;
u16 reserved4;
- u16 unlock_start_blk_add0;
- u16 unlock_end_blk_add0;
- u16 unlock_start_blk_add1;
- u16 unlock_end_blk_add1;
- u16 unlock_start_blk_add2;
- u16 unlock_end_blk_add2;
- u16 unlock_start_blk_add3;
- u16 unlock_end_blk_add3;
+ u16 unlockstart_blkaddr;
+ u16 unlockend_blkaddr;
+ u16 unlockstart_blkaddr1;
+ u16 unlockend_blkaddr1;
+ u16 unlockstart_blkaddr2;
+ u16 unlockend_blkaddr2;
+ u16 unlockstart_blkaddr3;
+ u16 unlockend_blkaddr3;
#endif
};
{
uint32_t tmp;
- while (!(readw(&nfc->nand_flash_config2) & NFC_INT))
+ while (!(readw(&nfc->config2) & NFC_INT))
;
/* Reset interrupt flag */
- tmp = readw(&nfc->nand_flash_config2);
+ tmp = readw(&nfc->config2);
tmp &= ~NFC_INT;
- writew(tmp, &nfc->nand_flash_config2);
+ writew(tmp, &nfc->config2);
}
void nfc_nand_init(void)
writew(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size);
/* unlocking RAM Buff */
- writew(0x2, &nfc->configuration);
+ writew(0x2, &nfc->config);
/* hardware ECC checking and correct */
- config1 = readw(&nfc->nand_flash_config1) | NFC_ECC_EN | 0x800;
+ config1 = readw(&nfc->config1) | NFC_ECC_EN | 0x800;
/*
* if spare size is larger that 16 bytes per 512 byte hunk
* then use 8 symbol correction instead of 4
config1 &= ~NFC_4_8N_ECC;
else
config1 |= NFC_4_8N_ECC;
- writew(config1, &nfc->nand_flash_config1);
+ writew(config1, &nfc->config1);
#elif defined(MXC_NFC_V1)
/* unlocking RAM Buff */
- writew(0x2, &nfc->configuration);
+ writew(0x2, &nfc->config);
/* hardware ECC checking and correct */
- writew(NFC_ECC_EN, &nfc->nand_flash_config1);
+ writew(NFC_ECC_EN, &nfc->config1);
#endif
}
static void nfc_nand_command(unsigned short command)
{
writew(command, &nfc->flash_cmd);
- writew(NFC_CMD, &nfc->nand_flash_config2);
+ writew(NFC_CMD, &nfc->config2);
nfc_wait_ready();
}
{
unsigned int page_count;
- writew(0x00, &nfc->flash_add);
- writew(NFC_ADDR, &nfc->nand_flash_config2);
+ writew(0x00, &nfc->flash_addr);
+ writew(NFC_ADDR, &nfc->config2);
nfc_wait_ready();
/* code only for large page flash */
if (CONFIG_SYS_NAND_PAGE_SIZE > 512) {
- writew(0x00, &nfc->flash_add);
- writew(NFC_ADDR, &nfc->nand_flash_config2);
+ writew(0x00, &nfc->flash_addr);
+ writew(NFC_ADDR, &nfc->config2);
nfc_wait_ready();
}
if (page_address <= page_count) {
page_count--; /* transform 0x01000000 to 0x00ffffff */
do {
- writew(page_address & 0xff, &nfc->flash_add);
- writew(NFC_ADDR, &nfc->nand_flash_config2);
+ writew(page_address & 0xff, &nfc->flash_addr);
+ writew(NFC_ADDR, &nfc->config2);
nfc_wait_ready();
page_address = page_address >> 8;
page_count = page_count >> 8;
} while (page_count);
}
- writew(0x00, &nfc->flash_add);
- writew(NFC_ADDR, &nfc->nand_flash_config2);
+ writew(0x00, &nfc->flash_addr);
+ writew(NFC_ADDR, &nfc->config2);
nfc_wait_ready();
}
static void nfc_nand_data_output(void)
{
- int config1 = readw(&nfc->nand_flash_config1);
+ int config1 = readw(&nfc->config1);
#ifdef NAND_MXC_2K_MULTI_CYCLE
int i;
#endif
config1 |= NFC_ECC_EN | NFC_INT_MSK;
- writew(config1, &nfc->nand_flash_config1);
- writew(0, &nfc->buffer_address);
- writew(NFC_OUTPUT, &nfc->nand_flash_config2);
+ writew(config1, &nfc->config1);
+ writew(0, &nfc->buf_addr);
+ writew(NFC_OUTPUT, &nfc->config2);
nfc_wait_ready();
#ifdef NAND_MXC_2K_MULTI_CYCLE
/*
* for pages larger than 512 bytes.
*/
for (i = 1; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) {
- config1 = readw(&nfc->nand_flash_config1);
+ config1 = readw(&nfc->config1);
config1 |= NFC_ECC_EN | NFC_INT_MSK;
- writew(config1, &nfc->nand_flash_config1);
- writew(i, &nfc->buffer_address);
- writew(NFC_OUTPUT, &nfc->nand_flash_config2);
+ writew(config1, &nfc->config1);
+ writew(i, &nfc->buf_addr);
+ writew(NFC_OUTPUT, &nfc->config2);
nfc_wait_ready();
}
#endif
u32 *src;
u32 *dst;
- writew(0, &nfc->buffer_address); /* read in first 0 buffer */
+ writew(0, &nfc->buf_addr); /* read in first 0 buffer */
nfc_nand_command(NAND_CMD_READ0);
nfc_nand_page_address(page_address);
if (nfc_nand_check_ecc())
return -1;
- src = &nfc->main_area[0][0];
+ src = (u32 *)&nfc->main_area[0][0];
dst = (u32 *)buf;
/* main copy loop from NAND-buffer to SDRAM memory */
/* Check the first two pages for bad block markers */
for (page = pagenumber; page < pagenumber + 2; page++) {
- writew(0, &nfc->buffer_address); /* read in first 0 buffer */
+ writew(0, &nfc->buf_addr); /* read in first 0 buffer */
nfc_nand_command(NAND_CMD_READ0);
nfc_nand_page_address(page);
nfc_nand_data_output(); /* fill the main buffer 0 */
- src = &nfc->spare_area[0][0];
+ src = (u32 *)&nfc->spare_area[0][0];
/*
* IMPORTANT NOTE: The nand flash controller uses a non-
projects / u-boot / commitdiff