{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */
- writel (0x00000000, ®s->wcr);
+ writew(0, ®s->wcr);
/* Write Service Sequence */
- writel (0x00005555, ®s->wsr);
- writel (0x0000AAAA, ®s->wsr);
+ writew(WSR_UNLOCK1, ®s->wsr);
+ writew(WSR_UNLOCK2, ®s->wsr);
/* Enable watchdog */
- writel (WCR_WDE, ®s->wcr);
+ writew(WCR_WDE, ®s->wcr);
while (1) ;
}
/* Watchdog Timer (WDOG) registers */
struct wdog_regs {
- u32 wcr; /* Control */
- u32 wsr; /* Service */
- u32 wrsr; /* Reset Status */
- u32 wicr; /* Interrupt Control */
- u32 wmcr; /* Misc Control */
+ u16 wcr; /* Control */
+ u16 wsr; /* Service */
+ u16 wrsr; /* Reset Status */
+ u16 wicr; /* Interrupt Control */
+ u16 wmcr; /* Misc Control */
};
/* IIM control registers */
#define GPT_CTRL_TEN 1 /* Timer enable */
/* WDOG enable */
-#define WCR_WDE 0x04
+#define WCR_WDE 0x04
+#define WSR_UNLOCK1 0x5555
+#define WSR_UNLOCK2 0xAAAA
/* FUSE bank offsets */
#define IIM0_MAC 0x1a