T: git git://git.denx.de/u-boot-atmel.git
F: arch/arm/mach-at91/
+ARM BROADCOM BCM283X
+M: Stephen Warren <swarren@wwwdotorg.org>
+S: Maintained
+F: arch/arm/mach-bcm283x/
+F: drivers/gpio/bcm2835_gpio.c
+F: drivers/mmc/bcm2835_sdhci.c
+F: drivers/serial/serial_bcm283x_mu.c
+F: drivers/video/bcm2835.c
+F: include/dm/platform_data/serial_bcm283x_mu.h
+
ARM FREESCALE IMX
M: Stefano Babic <sbabic@denx.de>
S: Maintained
F: arch/arm/cpu/armv7/s5p-common/
F: arch/arm/include/asm/arch-s3c24x0/
+ARM SNAPDRAGON
+M: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+S: Maintained
+F: arch/arm/mach-snapdragon/
+
ARM STM SPEAR
#M: Vipin Kumar <vipin.kumar@st.com>
S: Orphaned (Since 2016-02)
F: net/
NAND FLASH
-M: Scott Wood <scottwood@freescale.com>
+M: Scott Wood <oss@buserror.net>
S: Maintained
T: git git://git.denx.de/u-boot-nand-flash.git
F: drivers/mtd/nand/
F: drivers/spi/
F: include/spi*
+SPMI
+M: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+S: Maintained
+F: drivers/spmi/
+F: include/spmi/
+
TQ GROUP
#M: Martin Krause <martin.krause@tq-systems.de>
S: Orphaned (Since 2016-02)
#
VERSION = 2016
-PATCHLEVEL = 03
+PATCHLEVEL = 05
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
libs-y += drivers/serial/
libs-y += drivers/usb/dwc3/
+libs-y += drivers/usb/common/
libs-y += drivers/usb/emul/
libs-y += drivers/usb/eth/
libs-y += drivers/usb/gadget/
git log --no-merges U-Boot-1_1_5.. | \
unexpand -a | sed -e 's/\s\s*$$//' > $@
-include/license.h: tools/bin2header COPYING
- cat COPYING | gzip -9 -c | ./tools/bin2header license_gzip > include/license.h
#########################################################################
###
$(foreach d, spl tpl, $(patsubst %,$d/%, \
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
-CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
+CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h include/license.h \
boot* u-boot* MLO* SPL System.map
# Directories & files removed with 'make mrproper'
XXX - this list needs to get updated!
+- Removal of commands
+ If no commands are needed to boot, you can disable
+ CONFIG_CMDLINE to remove them. In this case, the command line
+ will not be available, and when U-Boot wants to execute the
+ boot command (on start-up) it will call board_run_command()
+ instead. This can reduce image size significantly for very
+ simple boot procedures.
+
- Regular expression support:
CONFIG_REGEX
If this variable is defined, U-Boot is linked against
The DIU driver will look for the 'video-mode' environment
variable, and if defined, enable the DIU as a console during
- boot. See the documentation file README.video for a
+ boot. See the documentation file doc/README.video for a
description of this variable.
- LCD Support: CONFIG_LCD
If this option is set, then U-Boot will prevent the environment
variable "splashimage" from being set to a problematic address
- (see README.displaying-bmps).
+ (see doc/README.displaying-bmps).
This option is useful for targets where, due to alignment
restrictions, an improperly aligned BMP image will cause a data
abort. If you think you will not have problems with unaligned
/* Architecture-specific global data */
struct arch_global_data {
- int running_on_hw;
};
#include <asm-generic/global_data.h>
#define setbits_8(addr, set) setbits(8, addr, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+static inline phys_addr_t virt_to_phys(void *vaddr)
+{
+ return (phys_addr_t)((unsigned long)vaddr);
+}
+
#endif /* __ASM_ARC_IO_H */
{
timer_init();
-/* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */
- if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xffffff00) == 0xffffff00)
- gd->arch.running_on_hw = 0;
- else
- gd->arch.running_on_hw = 1;
-
gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
config ARM64
bool
+config DMA_ADDR_T_64BIT
+ bool
+ default y if ARM64
+
config HAS_VBAR
bool
select CPU_ARM926EJS
config ARCH_MVEBU
- bool "Marvell MVEBU family (Armada XP/38x)"
+ bool "Marvell MVEBU family (Armada XP/375/38x)"
select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
bool "Renesas ARM SoCs"
select CPU_V7
+config ARCH_SNAPDRAGON
+ bool "Qualcomm Snapdragon SoCs"
+ select ARM64
+ select DM
+ select DM_GPIO
+ select DM_SERIAL
+ select SPMI
+ select OF_CONTROL
+ select OF_SEPARATE
+
config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select CPU_V7
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
+ select CMD_GPIO
select CMD_USB
select DM
select DM_ETH
select DM_KEYBOARD
select DM_SERIAL
select DM_USB
+ select OF_BOARD_SETUP
select OF_CONTROL
select OF_SEPARATE
- select SPL_STACK_R if !MACH_SUN9I
- select SPL_SYS_MALLOC_SIMPLE if !MACH_SUN9I
+ select SPL_STACK_R if SUPPORT_SPL
+ select SPL_SYS_MALLOC_SIMPLE if SUPPORT_SPL
select SYS_NS16550
select USB
select USB_STORAGE
bool "Support h2200"
select CPU_PXA
+config TARGET_ZIPITZ2
+ bool "Support zipitz2"
+ select CPU_PXA
+
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA
source "arch/arm/mach-s5pc1xx/Kconfig"
+source "arch/arm/mach-snapdragon/Kconfig"
+
source "arch/arm/mach-socfpga/Kconfig"
source "arch/arm/mach-stm32/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/woodburn/Kconfig"
source "board/work-microwave/work_92105/Kconfig"
+source "board/zipitz2/Kconfig"
source "arch/arm/Kconfig.debug"
arch-$(CONFIG_CPU_PXA) =
arch-$(CONFIG_CPU_ARM1136) =-march=armv5
arch-$(CONFIG_CPU_ARM1176) =-march=armv5t
-arch-$(CONFIG_CPU_V7) =$(call cc-option, -march=armv7-a, -march=armv5)
+arch-$(CONFIG_CPU_V7) =$(call cc-option, -march=armv7-a, \
+ $(call cc-option, -march=armv7, -march=armv5))
arch-$(CONFIG_ARM64) =-march=armv8-a
# Evaluate arch cc-option calls now
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
+machine-$(CONFIG_ARCH_SUNXI) += sunxi
+machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_STM32) += stm32
PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
+# LLVM support
+LLVMS_RELFLAGS := $(call cc-option,-mllvm,) \
+ $(call cc-option,-target arm-none-eabi,) \
+ $(call cc-option,-arm-use-movt=0,)
+PLATFORM_RELFLAGS += $(LLVM_RELFLAGS)
+
PLATFORM_CPPFLAGS += -D__ARM__
# Choose between ARM/Thumb instruction sets
---help---
Say Y here to boot in hypervisor (HYP) mode when booting non-secure.
+config ARMV7_LPAE
+ boolean "Use LPAE page table format" if EXPERT
+ depends on CPU_V7
+ default n
+ ---help---
+ Say Y here to use the long descriptor page table format. This is
+ required if U-Boot runs in HYP mode.
+
endif
extra-y := start.o
-obj-y += cache_v7.o
+obj-y += cache_v7.o cache_v7_asm.o
obj-y += cpu.o cp15.o
obj-y += syslib.o
#include <asm/armv7.h>
#include <asm/utils.h>
-#define ARMV7_DCACHE_INVAL_ALL 1
-#define ARMV7_DCACHE_CLEAN_INVAL_ALL 2
-#define ARMV7_DCACHE_INVAL_RANGE 3
-#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4
+#define ARMV7_DCACHE_INVAL_RANGE 1
+#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2
#ifndef CONFIG_SYS_DCACHE_OFF
+
+/* Asm functions from cache_v7_asm.S */
+void v7_flush_dcache_all(void);
+void v7_invalidate_dcache_all(void);
+
static int check_cache_range(unsigned long start, unsigned long stop)
{
int ok = 1;
return ok;
}
-/*
- * Write the level and type you want to Cache Size Selection Register(CSSELR)
- * to get size details from Current Cache Size ID Register(CCSIDR)
- */
-static void set_csselr(u32 level, u32 type)
-{
- u32 csselr = level << 1 | type;
-
- /* Write to Cache Size Selection Register(CSSELR) */
- asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
-}
-
static u32 get_ccsidr(void)
{
u32 ccsidr;
return ccsidr;
}
-static u32 get_clidr(void)
-{
- u32 clidr;
-
- /* Read current CP15 Cache Level ID Register */
- asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr));
- return clidr;
-}
-
-static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
- u32 num_ways, u32 way_shift,
- u32 log2_line_len)
-{
- int way, set;
- u32 setway;
-
- /*
- * For optimal assembly code:
- * a. count down
- * b. have bigger loop inside
- */
- for (way = num_ways - 1; way >= 0 ; way--) {
- for (set = num_sets - 1; set >= 0; set--) {
- setway = (level << 1) | (set << log2_line_len) |
- (way << way_shift);
- /* Invalidate data/unified cache line by set/way */
- asm volatile (" mcr p15, 0, %0, c7, c6, 2"
- : : "r" (setway));
- }
- }
- /* DSB to make sure the operation is complete */
- DSB;
-}
-
-static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
- u32 num_ways, u32 way_shift,
- u32 log2_line_len)
-{
- int way, set;
- u32 setway;
-
- /*
- * For optimal assembly code:
- * a. count down
- * b. have bigger loop inside
- */
- for (way = num_ways - 1; way >= 0 ; way--) {
- for (set = num_sets - 1; set >= 0; set--) {
- setway = (level << 1) | (set << log2_line_len) |
- (way << way_shift);
- /*
- * Clean & Invalidate data/unified
- * cache line by set/way
- */
- asm volatile (" mcr p15, 0, %0, c7, c14, 2"
- : : "r" (setway));
- }
- }
- /* DSB to make sure the operation is complete */
- DSB;
-}
-
-static void v7_maint_dcache_level_setway(u32 level, u32 operation)
-{
- u32 ccsidr;
- u32 num_sets, num_ways, log2_line_len, log2_num_ways;
- u32 way_shift;
-
- set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED);
-
- ccsidr = get_ccsidr();
-
- log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
- CCSIDR_LINE_SIZE_OFFSET) + 2;
- /* Converting from words to bytes */
- log2_line_len += 2;
-
- num_ways = ((ccsidr & CCSIDR_ASSOCIATIVITY_MASK) >>
- CCSIDR_ASSOCIATIVITY_OFFSET) + 1;
- num_sets = ((ccsidr & CCSIDR_NUM_SETS_MASK) >>
- CCSIDR_NUM_SETS_OFFSET) + 1;
- /*
- * According to ARMv7 ARM number of sets and number of ways need
- * not be a power of 2
- */
- log2_num_ways = log_2_n_round_up(num_ways);
-
- way_shift = (32 - log2_num_ways);
- if (operation == ARMV7_DCACHE_INVAL_ALL) {
- v7_inval_dcache_level_setway(level, num_sets, num_ways,
- way_shift, log2_line_len);
- } else if (operation == ARMV7_DCACHE_CLEAN_INVAL_ALL) {
- v7_clean_inval_dcache_level_setway(level, num_sets, num_ways,
- way_shift, log2_line_len);
- }
-}
-
-static void v7_maint_dcache_all(u32 operation)
-{
- u32 level, cache_type, level_start_bit = 0;
- u32 clidr = get_clidr();
-
- for (level = 0; level < 7; level++) {
- cache_type = (clidr >> level_start_bit) & 0x7;
- if ((cache_type == ARMV7_CLIDR_CTYPE_DATA_ONLY) ||
- (cache_type == ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA) ||
- (cache_type == ARMV7_CLIDR_CTYPE_UNIFIED))
- v7_maint_dcache_level_setway(level, operation);
- level_start_bit += 3;
- }
-}
-
static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len)
{
u32 mva;
void invalidate_dcache_all(void)
{
- v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
+ v7_invalidate_dcache_all();
v7_outer_cache_inval_all();
}
*/
void flush_dcache_all(void)
{
- v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL);
+ v7_flush_dcache_all();
v7_outer_cache_flush_all();
}
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <linux/sizes.h>
+#include <asm/system.h>
+
+#ifdef CONFIG_SYS_THUMB_BUILD
+#define ARM(x...)
+#define THUMB(x...) x
+#else
+#define ARM(x...) x
+#define THUMB(x...)
+#endif
+
+/*
+ * v7_flush_dcache_all()
+ *
+ * Flush the whole D-cache.
+ *
+ * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
+ *
+ * Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
+ */
+ENTRY(__v7_flush_dcache_all)
+ dmb @ ensure ordering with previous memory accesses
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
+ mov r3, r0, lsr #23 @ move LoC into position
+ ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
+ beq finished @ if loc is 0, then no need to clean
+start_flush_levels:
+ mov r10, #0 @ start clean at cache level 0
+flush_levels:
+ add r2, r10, r10, lsr #1 @ work out 3x current cache level
+ mov r1, r0, lsr r2 @ extract cache type bits from clidr
+ and r1, r1, #7 @ mask of the bits for current cache only
+ cmp r1, #2 @ see what cache we have at this level
+ blt skip @ skip if no cache, or just i-cache
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ isb @ isb to sych the new cssr&csidr
+ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
+ and r2, r1, #7 @ extract the length of the cache lines
+ add r2, r2, #4 @ add 4 (line length offset)
+ movw r4, #0x3ff
+ ands r4, r4, r1, lsr #3 @ find maximum number on the way size
+ clz r5, r4 @ find bit position of way size increment
+ movw r7, #0x7fff
+ ands r7, r7, r1, lsr #13 @ extract max number of the index size
+loop1:
+ mov r9, r7 @ create working copy of max index
+loop2:
+ ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
+ THUMB( lsl r6, r4, r5 )
+ THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
+ ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
+ THUMB( lsl r6, r9, r2 )
+ THUMB( orr r11, r11, r6 ) @ factor index number into r11
+ mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
+ subs r9, r9, #1 @ decrement the index
+ bge loop2
+ subs r4, r4, #1 @ decrement the way
+ bge loop1
+skip:
+ add r10, r10, #2 @ increment cache number
+ cmp r3, r10
+ bgt flush_levels
+finished:
+ mov r10, #0 @ swith back to cache level 0
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ dsb st
+ isb
+ bx lr
+ENDPROC(__v7_flush_dcache_all)
+
+ENTRY(v7_flush_dcache_all)
+ ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
+ THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
+ bl __v7_flush_dcache_all
+ ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
+ THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
+ bx lr
+ENDPROC(v7_flush_dcache_all)
+
+/*
+ * v7_invalidate_dcache_all()
+ *
+ * Invalidate the whole D-cache.
+ *
+ * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
+ *
+ * Note: copied from __v7_flush_dcache_all above with
+ * mcr p15, 0, r11, c7, c14, 2
+ * Replaced with:
+ * mcr p15, 0, r11, c7, c6, 2
+ */
+ENTRY(__v7_invalidate_dcache_all)
+ dmb @ ensure ordering with previous memory accesses
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
+ mov r3, r0, lsr #23 @ move LoC into position
+ ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
+ beq inval_finished @ if loc is 0, then no need to clean
+ mov r10, #0 @ start clean at cache level 0
+inval_levels:
+ add r2, r10, r10, lsr #1 @ work out 3x current cache level
+ mov r1, r0, lsr r2 @ extract cache type bits from clidr
+ and r1, r1, #7 @ mask of the bits for current cache only
+ cmp r1, #2 @ see what cache we have at this level
+ blt inval_skip @ skip if no cache, or just i-cache
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ isb @ isb to sych the new cssr&csidr
+ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
+ and r2, r1, #7 @ extract the length of the cache lines
+ add r2, r2, #4 @ add 4 (line length offset)
+ movw r4, #0x3ff
+ ands r4, r4, r1, lsr #3 @ find maximum number on the way size
+ clz r5, r4 @ find bit position of way size increment
+ movw r7, #0x7fff
+ ands r7, r7, r1, lsr #13 @ extract max number of the index size
+inval_loop1:
+ mov r9, r7 @ create working copy of max index
+inval_loop2:
+ ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
+ THUMB( lsl r6, r4, r5 )
+ THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
+ ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
+ THUMB( lsl r6, r9, r2 )
+ THUMB( orr r11, r11, r6 ) @ factor index number into r11
+ mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
+ subs r9, r9, #1 @ decrement the index
+ bge inval_loop2
+ subs r4, r4, #1 @ decrement the way
+ bge inval_loop1
+inval_skip:
+ add r10, r10, #2 @ increment cache number
+ cmp r3, r10
+ bgt inval_levels
+inval_finished:
+ mov r10, #0 @ swith back to cache level 0
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ dsb st
+ isb
+ bx lr
+ENDPROC(__v7_invalidate_dcache_all)
+
+ENTRY(v7_invalidate_dcache_all)
+ ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
+ THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
+ bl __v7_invalidate_dcache_all
+ ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
+ THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
+ bx lr
+ENDPROC(v7_invalidate_dcache_all)
source "board/technexion/tao3530/Kconfig"
source "board/technexion/twister/Kconfig"
source "board/quipos/cairo/Kconfig"
-source "board/lge/sniper/Kconfig"
+source "board/lg/sniper/Kconfig"
endif
return reg;
}
-static int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
- int niodelays)
+int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
+ int niodelays)
{
struct iodelay_cfg_entry *iodelay = (struct iodelay_cfg_entry *)array;
u32 reg, cpde, fpde, i;
return 0;
}
-void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
- struct iodelay_cfg_entry const *iodelay,
- int niodelays)
+int __recalibrate_iodelay_start(void)
{
int ret = 0;
/* IO recalibration should be done only from SRAM */
if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
- return;
+ return -1;
}
/* unlock IODELAY CONFIG registers */
goto err;
ret = update_delay_mechanism((*ctrl)->iodelay_config_base);
- if (ret)
- goto err;
- /* Configure Mux settings */
- do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);
+err:
+ return ret;
+}
- /* Configure Manual IO timing modes */
- ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
- if (ret)
- goto err;
+void __recalibrate_iodelay_end(int ret)
+{
- ret = isolate_io(DEISOLATE_IO);
+ /* IO recalibration should be done only from SRAM */
+ if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
+ puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
+ return;
+ }
+
+ if (!ret)
+ ret = isolate_io(DEISOLATE_IO);
-err:
/* lock IODELAY CONFIG registers */
writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base +
CFG_REG_8_OFFSET);
+
/*
* UART cannot be used during IO recalibration sequence as IOs are in
* isolation. So error handling and debug prints are done after
case ERR_FPDE:
puts("IODELAY: FPDE calculation failed\n");
break;
+ case -1:
+ puts("IODELAY: Wrong Context call?\n");
+ break;
default:
debug("IODELAY: IO delay recalibration successfully completed\n");
}
+
+ return;
+}
+
+void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
+ struct iodelay_cfg_entry const *iodelay,
+ int niodelays)
+{
+ int ret = 0;
+
+ /* IO recalibration should be done only from SRAM */
+ if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
+ puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
+ return;
+ }
+
+ ret = __recalibrate_iodelay_start();
+ if (ret)
+ goto err;
+
+ /* Configure Mux settings */
+ do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);
+
+ /* Configure Manual IO timing modes */
+ ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
+ if (ret)
+ goto err;
+
+err:
+ __recalibrate_iodelay_end(ret);
+
}
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};
+const struct ctrl_ioregs ioregs_dra72x_es2 = {
+ .ctrl_ddrch = 0x40404040,
+ .ctrl_lpddr2ch = 0x40404040,
+ .ctrl_ddr3ch = 0x60606060,
+ .ctrl_ddrio_0 = 0x00094A40,
+ .ctrl_ddrio_1 = 0x00000000,
+ .ctrl_ddrio_2 = 0x00000000,
+ .ctrl_emif_sdram_config_ext = 0x0001C1A7,
+ .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
+ .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
+};
+
void __weak hw_data_init(void)
{
u32 omap_rev = omap_revision();
break;
case DRA722_ES1_0:
+ case DRA722_ES2_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra72x_dplls;
*omap_vcores = &dra722_volts;
case DRA722_ES1_0:
*regs = &ioregs_dra72x_es1;
break;
+ case DRA722_ES2_0:
+ *regs = &ioregs_dra72x_es2;
+ break;
default:
printf("\n INVALID OMAP REVISION ");
case DRA722_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = DRA722_ES1_0;
break;
+ case DRA722_CONTROL_ID_CODE_ES2_0:
+ *omap_si_rev = DRA722_ES2_0;
+ break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
}
0x0
};
+const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = {
+ 0x04040100,
+ 0x006B009F,
+ 0x006B00A2,
+ 0x006B00A8,
+ 0x006B00A8,
+ 0x006B00B2,
+ 0x002F002F,
+ 0x002F002F,
+ 0x002F002F,
+ 0x002F002F,
+ 0x002F002F,
+ 0x00600073,
+ 0x00600071,
+ 0x0060007C,
+ 0x0060007E,
+ 0x00600084,
+ 0x00400053,
+ 0x00400051,
+ 0x0040005C,
+ 0x0040005E,
+ 0x00400064,
+ 0x00800080,
+ 0x00800080,
+ 0x40010080,
+ 0x08102040,
+ 0x005B008F,
+ 0x005B0092,
+ 0x005B0098,
+ 0x005B0098,
+ 0x005B00A2,
+ 0x00300043,
+ 0x00300041,
+ 0x0030004C,
+ 0x0030004E,
+ 0x00300054,
+ 0x00000077
+};
+
const struct lpddr2_mr_regs mr_regs = {
.mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
.mr2 = 0x6,
*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
break;
+ case DRA722_ES2_0:
+ *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
+ *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
+ break;
default:
*regs = ddr3_ext_phy_ctrl_const_base_es2;
*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
case DRA752_ES1_1:
case DRA752_ES2_0:
case DRA722_ES1_0:
+ case DRA722_ES2_0:
bug_00339_regs_ptr = dra_bug_00339_regs;
*iterations = sizeof(dra_bug_00339_regs)/
sizeof(dra_bug_00339_regs[0]);
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += timer.o
-obj-y += board.o
-obj-y += clock.o
-obj-y += cpu_info.o
-obj-y += dram_helpers.o
-obj-y += pinmux.o
-ifndef CONFIG_MACH_SUN9I
-obj-y += usb_phy.o
-endif
-obj-$(CONFIG_MACH_SUN6I) += prcm.o
-obj-$(CONFIG_MACH_SUN8I) += prcm.o
-obj-$(CONFIG_MACH_SUN9I) += prcm.o
-obj-$(CONFIG_MACH_SUN6I) += p2wi.o
-obj-$(CONFIG_MACH_SUN8I) += rsb.o
-obj-$(CONFIG_MACH_SUN9I) += rsb.o
-obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
-obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
-obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
-obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o
-ifdef CONFIG_MACH_SUN8I_A83T
-obj-y += clock_sun8i_a83t.o
-else
-obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
-endif
-obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o
+
obj-$(CONFIG_MACH_SUN6I) += tzpc.o
obj-$(CONFIG_MACH_SUN8I_H3) += tzpc.o
-obj-$(CONFIG_AXP152_POWER) += pmic_bus.o
-obj-$(CONFIG_AXP209_POWER) += pmic_bus.o
-obj-$(CONFIG_AXP221_POWER) += pmic_bus.o
-obj-$(CONFIG_AXP818_POWER) += pmic_bus.o
-
ifndef CONFIG_SPL_BUILD
ifdef CONFIG_ARMV7_PSCI
obj-$(CONFIG_MACH_SUN6I) += psci_sun6i.o
endif
ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o
-obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
-obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
-obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
-obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o
-obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o
-obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o
-obj-$(CONFIG_MACH_SUN8I_H3) += dram_sun8i_h3.o
obj-y += fel_utils.o
endif
+++ /dev/null
-/*
- * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
- *
- * (C) Copyright 2007-2011
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- *
- * Some init for sunxi platform.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mmc.h>
-#include <i2c.h>
-#include <serial.h>
-#ifdef CONFIG_SPL_BUILD
-#include <spl.h>
-#endif
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/spl.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/timer.h>
-#include <asm/arch/tzpc.h>
-#include <asm/arch/mmc.h>
-
-#include <linux/compiler.h>
-
-struct fel_stash {
- uint32_t sp;
- uint32_t lr;
- uint32_t cpsr;
- uint32_t sctlr;
- uint32_t vbar;
- uint32_t cr;
-};
-
-struct fel_stash fel_stash __attribute__((section(".data")));
-
-static int gpio_init(void)
-{
-#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
- /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
- sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
-#endif
-#if defined(CONFIG_MACH_SUN8I)
- sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
-#else
- sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
-#endif
- sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
-#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
- sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
- sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
- sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
- sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
- sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
- sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
- sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
- sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
- sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
- sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
- sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
- sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
- sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
- sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
- sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
- sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
- sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
- sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
- sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
- sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
- sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
- sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
-#else
-#error Unsupported console port number. Please fix pin mux settings in board.c
-#endif
-
- return 0;
-}
-
-int spl_board_load_image(void)
-{
- debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
- return_to_fel(fel_stash.sp, fel_stash.lr);
-
- return 0;
-}
-
-void s_init(void)
-{
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
- /* Magic (undocmented) value taken from boot0, without this DRAM
- * access gets messed up (seems cache related) */
- setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
-#endif
-#if defined CONFIG_MACH_SUN6I || \
- defined CONFIG_MACH_SUN7I || \
- defined CONFIG_MACH_SUN8I
- /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
- asm volatile(
- "mrc p15, 0, r0, c1, c0, 1\n"
- "orr r0, r0, #1 << 6\n"
- "mcr p15, 0, r0, c1, c0, 1\n");
-#endif
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
- /* Enable non-secure access to some peripherals */
- tzpc_init();
-#endif
-
- clock_init();
- timer_init();
- gpio_init();
- i2c_init_board();
-}
-
-#ifdef CONFIG_SPL_BUILD
-DECLARE_GLOBAL_DATA_PTR;
-
-/* The sunxi internal brom will try to loader external bootloader
- * from mmc0, nand flash, mmc2.
- */
-u32 spl_boot_device(void)
-{
- __maybe_unused struct mmc *mmc0, *mmc1;
- /*
- * When booting from the SD card or NAND memory, the "eGON.BT0"
- * signature is expected to be found in memory at the address 0x0004
- * (see the "mksunxiboot" tool, which generates this header).
- *
- * When booting in the FEL mode over USB, this signature is patched in
- * memory and replaced with something else by the 'fel' tool. This other
- * signature is selected in such a way, that it can't be present in a
- * valid bootable SD card image (because the BROM would refuse to
- * execute the SPL in this case).
- *
- * This checks for the signature and if it is not found returns to
- * the FEL code in the BROM to wait and receive the main u-boot
- * binary over USB. If it is found, it determines where SPL was
- * read from.
- */
- if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
- return BOOT_DEVICE_BOARD;
-
- /* The BROM will try to boot from mmc0 first, so try that first. */
-#ifdef CONFIG_MMC
- mmc_initialize(gd->bd);
- mmc0 = find_mmc_device(0);
- if (sunxi_mmc_has_egon_boot_signature(mmc0))
- return BOOT_DEVICE_MMC1;
-#endif
-
- /* Fallback to booting NAND if enabled. */
- if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT))
- return BOOT_DEVICE_NAND;
-
-#ifdef CONFIG_MMC
- if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) {
- mmc1 = find_mmc_device(1);
- if (sunxi_mmc_has_egon_boot_signature(mmc1))
- return BOOT_DEVICE_MMC2;
- }
-#endif
-
- panic("Could not determine boot source\n");
- return -1; /* Never reached */
-}
-
-/* No confirmation data available in SPL yet. Hardcode bootmode */
-u32 spl_boot_mode(void)
-{
- return MMCSD_MODE_RAW;
-}
-
-void board_init_f(ulong dummy)
-{
- spl_init();
- preloader_console_init();
-
-#ifdef CONFIG_SPL_I2C_SUPPORT
- /* Needed early by sunxi_board_init if PMU is enabled */
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
- sunxi_board_init();
-}
-#endif
-
-void reset_cpu(ulong addr)
-{
-#ifdef CONFIG_SUNXI_GEN_SUN4I
- static const struct sunxi_wdog *wdog =
- &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
-
- /* Set the watchdog for its shortest interval (.5s) and wait */
- writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
- writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
-
- while (1) {
- /* sun5i sometimes gets stuck without this */
- writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
- }
-#endif
-#ifdef CONFIG_SUNXI_GEN_SUN6I
- static const struct sunxi_wdog *wdog =
- ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
-
- /* Set the watchdog for its shortest interval (.5s) and wait */
- writel(WDT_CFG_RESET, &wdog->cfg);
- writel(WDT_MODE_EN, &wdog->mode);
- writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
- while (1) { }
-#endif
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
-
-#ifdef CONFIG_CMD_NET
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
- __maybe_unused int rc;
-
-#ifdef CONFIG_MACPWR
- gpio_request(CONFIG_MACPWR, "macpwr");
- gpio_direction_output(CONFIG_MACPWR, 1);
- mdelay(200);
-#endif
-
-#ifdef CONFIG_SUNXI_GMAC
- rc = sunxi_gmac_initialize(bis);
- if (rc < 0) {
- printf("sunxi: failed to initialize gmac\n");
- return rc;
- }
-#endif
-
- return 0;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2007-2012
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- *
- * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/sys_proto.h>
-
-__weak void clock_init_sec(void)
-{
-}
-
-int clock_init(void)
-{
-#ifdef CONFIG_SPL_BUILD
- clock_init_safe();
-#endif
- clock_init_uart();
- clock_init_sec();
-
- return 0;
-}
+++ /dev/null
-/*
- * sun4i, sun5i and sun7i specific clock code
- *
- * (C) Copyright 2007-2012
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- *
- * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/sys_proto.h>
-
-#ifdef CONFIG_SPL_BUILD
-void clock_init_safe(void)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- /* Set safe defaults until PMU is configured */
- writel(AXI_DIV_1 << AXI_DIV_SHIFT |
- AHB_DIV_2 << AHB_DIV_SHIFT |
- APB0_DIV_1 << APB0_DIV_SHIFT |
- CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
- &ccm->cpu_ahb_apb0_cfg);
- writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
- sdelay(200);
- writel(AXI_DIV_1 << AXI_DIV_SHIFT |
- AHB_DIV_2 << AHB_DIV_SHIFT |
- APB0_DIV_1 << APB0_DIV_SHIFT |
- CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
- &ccm->cpu_ahb_apb0_cfg);
-#ifdef CONFIG_MACH_SUN7I
- setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
-#endif
- writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
-#ifdef CONFIG_SUNXI_AHCI
- setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
- setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);
-#endif
-}
-#endif
-
-void clock_init_uart(void)
-{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- /* uart clock source is apb1 */
- writel(APB1_CLK_SRC_OSC24M|
- APB1_CLK_RATE_N_1|
- APB1_CLK_RATE_M(1),
- &ccm->apb1_clk_div_cfg);
-
- /* open the clock for uart */
- setbits_le32(&ccm->apb1_gate,
- CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX - 1));
-}
-
-int clock_twi_onoff(int port, int state)
-{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- /* set the apb clock gate for twi */
- if (state)
- setbits_le32(&ccm->apb1_gate,
- CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
- else
- clrbits_le32(&ccm->apb1_gate,
- CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-#define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \
- 0 << CCM_PLL1_CFG_VCO_RST_SHIFT | \
- 8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \
- 0 << CCM_PLL1_CFG_PLL4_EXCH_SHIFT | \
- 16 << CCM_PLL1_CFG_BIAS_CUR_SHIFT | \
- (P)<< CCM_PLL1_CFG_DIVP_SHIFT | \
- 2 << CCM_PLL1_CFG_LCK_TMR_SHIFT | \
- (N)<< CCM_PLL1_CFG_FACTOR_N_SHIFT | \
- (K)<< CCM_PLL1_CFG_FACTOR_K_SHIFT | \
- 0 << CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT | \
- 0 << CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT | \
- (M)<< CCM_PLL1_CFG_FACTOR_M_SHIFT)
-
-static struct {
- u32 pll1_cfg;
- unsigned int freq;
-} pll1_para[] = {
- /* This array must be ordered by frequency. */
- { PLL1_CFG(31, 1, 0, 0), 1488000000},
- { PLL1_CFG(30, 1, 0, 0), 1440000000},
- { PLL1_CFG(29, 1, 0, 0), 1392000000},
- { PLL1_CFG(28, 1, 0, 0), 1344000000},
- { PLL1_CFG(27, 1, 0, 0), 1296000000},
- { PLL1_CFG(26, 1, 0, 0), 1248000000},
- { PLL1_CFG(25, 1, 0, 0), 1200000000},
- { PLL1_CFG(24, 1, 0, 0), 1152000000},
- { PLL1_CFG(23, 1, 0, 0), 1104000000},
- { PLL1_CFG(22, 1, 0, 0), 1056000000},
- { PLL1_CFG(21, 1, 0, 0), 1008000000},
- { PLL1_CFG(20, 1, 0, 0), 960000000 },
- { PLL1_CFG(19, 1, 0, 0), 912000000 },
- { PLL1_CFG(16, 1, 0, 0), 768000000 },
- /* Final catchall entry 384MHz*/
- { PLL1_CFG(16, 0, 0, 0), 0 },
-
-};
-
-void clock_set_pll1(unsigned int hz)
-{
- int i = 0;
- int axi, ahb, apb0;
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- /* Find target frequency */
- while (pll1_para[i].freq > hz)
- i++;
-
- hz = pll1_para[i].freq;
- if (! hz)
- hz = 384000000;
-
- /* Calculate system clock divisors */
- axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */
- ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */
- apb0 = 2; /* Max 150MHz */
-
- printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0);
-
- /* Map divisors to register values */
- axi = axi - 1;
- if (ahb > 4)
- ahb = 3;
- else if (ahb > 2)
- ahb = 2;
- else if (ahb > 1)
- ahb = 1;
- else
- ahb = 0;
-
- apb0 = apb0 - 1;
-
- /* Switch to 24MHz clock while changing PLL1 */
- writel(AXI_DIV_1 << AXI_DIV_SHIFT |
- AHB_DIV_2 << AHB_DIV_SHIFT |
- APB0_DIV_1 << APB0_DIV_SHIFT |
- CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
- &ccm->cpu_ahb_apb0_cfg);
- sdelay(20);
-
- /* Configure sys clock divisors */
- writel(axi << AXI_DIV_SHIFT |
- ahb << AHB_DIV_SHIFT |
- apb0 << APB0_DIV_SHIFT |
- CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
- &ccm->cpu_ahb_apb0_cfg);
-
- /* Configure PLL1 at the desired frequency */
- writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg);
- sdelay(200);
-
- /* Switch CPU to PLL1 */
- writel(axi << AXI_DIV_SHIFT |
- ahb << AHB_DIV_SHIFT |
- apb0 << APB0_DIV_SHIFT |
- CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
- &ccm->cpu_ahb_apb0_cfg);
- sdelay(20);
-}
-#endif
-
-void clock_set_pll3(unsigned int clk)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- if (clk == 0) {
- clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
- return;
- }
-
- /* PLL3 rate = 3000000 * m */
- writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
- CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg);
-}
-
-unsigned int clock_get_pll3(void)
-{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- uint32_t rval = readl(&ccm->pll3_cfg);
- int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT);
- return 3000000 * m;
-}
-
-unsigned int clock_get_pll5p(void)
-{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- uint32_t rval = readl(&ccm->pll5_cfg);
- int n = ((rval & CCM_PLL5_CTRL_N_MASK) >> CCM_PLL5_CTRL_N_SHIFT);
- int k = ((rval & CCM_PLL5_CTRL_K_MASK) >> CCM_PLL5_CTRL_K_SHIFT) + 1;
- int p = ((rval & CCM_PLL5_CTRL_P_MASK) >> CCM_PLL5_CTRL_P_SHIFT);
- return (24000000 * n * k) >> p;
-}
-
-unsigned int clock_get_pll6(void)
-{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- uint32_t rval = readl(&ccm->pll6_cfg);
- int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
- int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
- return 24000000 * n * k / 2;
-}
-
-void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
-{
- int pll = clock_get_pll5p();
- int div = 1;
-
- while ((pll / div) > hz)
- div++;
-
- writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_RST | CCM_DE_CTRL_PLL5P |
- CCM_DE_CTRL_M(div), clk_cfg);
-}
+++ /dev/null
-/*
- * sun6i specific clock code
- *
- * (C) Copyright 2007-2012
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- *
- * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/prcm.h>
-#include <asm/arch/sys_proto.h>
-
-#ifdef CONFIG_SPL_BUILD
-void clock_init_safe(void)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- struct sunxi_prcm_reg * const prcm =
- (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
-
- /* Set PLL ldo voltage without this PLL6 does not work properly */
- clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
- PRCM_PLL_CTRL_LDO_KEY);
- clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
- PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
- PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
- clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
-
- clock_set_pll1(408000000);
-
- writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
- while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
- ;
-
- writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
-
- writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
- writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
-}
-#endif
-
-void clock_init_sec(void)
-{
-#ifdef CONFIG_MACH_SUN8I_H3
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- setbits_le32(&ccm->ccu_sec_switch,
- CCM_SEC_SWITCH_MBUS_NONSEC |
- CCM_SEC_SWITCH_BUS_NONSEC |
- CCM_SEC_SWITCH_PLL_NONSEC);
-#endif
-}
-
-void clock_init_uart(void)
-{
-#if CONFIG_CONS_INDEX < 5
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- /* uart clock source is apb2 */
- writel(APB2_CLK_SRC_OSC24M|
- APB2_CLK_RATE_N_1|
- APB2_CLK_RATE_M(1),
- &ccm->apb2_div);
-
- /* open the clock for uart */
- setbits_le32(&ccm->apb2_gate,
- CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
- CONFIG_CONS_INDEX - 1));
-
- /* deassert uart reset */
- setbits_le32(&ccm->apb2_reset_cfg,
- 1 << (APB2_RESET_UART_SHIFT +
- CONFIG_CONS_INDEX - 1));
-#else
- /* enable R_PIO and R_UART clocks, and de-assert resets */
- prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
-#endif
-}
-
-int clock_twi_onoff(int port, int state)
-{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- if (port == 5) {
- if (state)
- prcm_apb0_enable(
- PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
- else
- prcm_apb0_disable(
- PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
- return 0;
- }
-
- /* set the apb clock gate for twi */
- if (state)
- setbits_le32(&ccm->apb2_gate,
- CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
- else
- clrbits_le32(&ccm->apb2_gate,
- CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-void clock_set_pll1(unsigned int clk)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- const int p = 0;
- int k = 1;
- int m = 1;
-
- if (clk > 1152000000) {
- k = 2;
- } else if (clk > 768000000) {
- k = 3;
- m = 2;
- }
-
- /* Switch to 24MHz clock while changing PLL1 */
- writel(AXI_DIV_3 << AXI_DIV_SHIFT |
- ATB_DIV_2 << ATB_DIV_SHIFT |
- CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
- &ccm->cpu_axi_cfg);
-
- /*
- * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
- * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
- */
- writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
- CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
- CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
- sdelay(200);
-
- /* Switch CPU to PLL1 */
- writel(AXI_DIV_3 << AXI_DIV_SHIFT |
- ATB_DIV_2 << ATB_DIV_SHIFT |
- CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
- &ccm->cpu_axi_cfg);
-}
-#endif
-
-void clock_set_pll3(unsigned int clk)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
-
- if (clk == 0) {
- clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
- return;
- }
-
- /* PLL3 rate = 24000000 * n / m */
- writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
- CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
- &ccm->pll3_cfg);
-}
-
-void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- const int max_n = 32;
- int k = 1, m = 2;
-
- if (sigma_delta_enable)
- writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
-
- /* PLL5 rate = 24000000 * n * k / m */
- if (clk > 24000000 * k * max_n / m) {
- m = 1;
- if (clk > 24000000 * k * max_n / m)
- k = 2;
- }
- writel(CCM_PLL5_CTRL_EN |
- (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
- CCM_PLL5_CTRL_UPD |
- CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
- CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
-
- udelay(5500);
-}
-
-#ifdef CONFIG_MACH_SUN6I
-void clock_set_mipi_pll(unsigned int clk)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- unsigned int k, m, n, value, diff;
- unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
- unsigned int src = clock_get_pll3();
-
- /* All calculations are in KHz to avoid overflows */
- clk /= 1000;
- src /= 1000;
-
- /* Pick the closest lower clock */
- for (k = 1; k <= 4; k++) {
- for (m = 1; m <= 16; m++) {
- for (n = 1; n <= 16; n++) {
- value = src * n * k / m;
- if (value > clk)
- continue;
-
- diff = clk - value;
- if (diff < best_diff) {
- best_diff = diff;
- best_k = k;
- best_m = m;
- best_n = n;
- }
- if (diff == 0)
- goto done;
- }
- }
- }
-
-done:
- writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN |
- CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) |
- CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
-}
-#endif
-
-#ifdef CONFIG_MACH_SUN8I_A33
-void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- if (sigma_delta_enable)
- writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg);
-
- writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
- (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
- CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
-
- while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
- ;
-}
-#endif
-
-unsigned int clock_get_pll3(void)
-{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- uint32_t rval = readl(&ccm->pll3_cfg);
- int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
- int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;
-
- /* Multiply by 1000 after dividing by m to avoid integer overflows */
- return (24000 * n / m) * 1000;
-}
-
-unsigned int clock_get_pll6(void)
-{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- uint32_t rval = readl(&ccm->pll6_cfg);
- int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
- int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
- return 24000000 * n * k / 2;
-}
-
-unsigned int clock_get_mipi_pll(void)
-{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- uint32_t rval = readl(&ccm->mipi_pll_cfg);
- unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
- unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
- unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
- unsigned int src = clock_get_pll3();
-
- /* Multiply by 1000 after dividing by m to avoid integer overflows */
- return ((src / 1000) * n * k / m) * 1000;
-}
-
-void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
-{
- int pll = clock_get_pll6() * 2;
- int div = 1;
-
- while ((pll / div) > hz)
- div++;
-
- writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
- clk_cfg);
-}
+++ /dev/null
-/*
- * A83 specific clock code
- *
- * (C) Copyright 2007-2012
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- *
- * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/prcm.h>
-#include <asm/arch/sys_proto.h>
-
-#ifdef CONFIG_SPL_BUILD
-void clock_init_safe(void)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- clock_set_pll1(408000000);
- /* enable pll_hsic, default is 480M */
- writel(PLL8_CFG_DEFAULT, &ccm->pll8_cfg);
- writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg);
- while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {}
-
- /* switch to default 24MHz before changing to hsic */
- writel(0x0, &ccm->cci400_cfg);
- sdelay(50);
- writel(CCM_CCI400_CLK_SEL_HSIC, &ccm->cci400_cfg);
- sdelay(100);
-
- /* switch before changing pll6 */
- clrsetbits_le32(&ccm->ahb1_apb1_div, AHB1_CLK_SRC_MASK,
- AHB1_CLK_SRC_OSC24M);
- writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
- while (!(readl(&ccm->pll_stable_status) & (1 << 6))) {}
-
- writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
- writel(CCM_MBUS_RESET_RESET, &ccm->mbus_reset);
- writel(MBUS_CLK_DEFAULT, &ccm->mbus_clk_cfg);
-
- /* timestamp */
- writel(1, 0x01720000);
-}
-#endif
-
-void clock_init_uart(void)
-{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- /* uart clock source is apb2 */
- writel(APB2_CLK_SRC_OSC24M|
- APB2_CLK_RATE_N_1|
- APB2_CLK_RATE_M(1),
- &ccm->apb2_div);
-
- /* open the clock for uart */
- setbits_le32(&ccm->apb2_gate,
- CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
- CONFIG_CONS_INDEX - 1));
-
- /* deassert uart reset */
- setbits_le32(&ccm->apb2_reset_cfg,
- 1 << (APB2_RESET_UART_SHIFT +
- CONFIG_CONS_INDEX - 1));
-}
-
-#ifdef CONFIG_SPL_BUILD
-void clock_set_pll1(unsigned int clk)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- const int p = 0;
-
- /* Switch to 24MHz clock while changing PLL1 */
- writel(AXI_DIV_2 << AXI0_DIV_SHIFT |
- AXI_DIV_2 << AXI1_DIV_SHIFT |
- CPU_CLK_SRC_OSC24M << C0_CPUX_CLK_SRC_SHIFT |
- CPU_CLK_SRC_OSC24M << C1_CPUX_CLK_SRC_SHIFT,
- &ccm->cpu_axi_cfg);
-
- /* clk = 24*n/p, p is ignored if clock is >288MHz */
- writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 |
- CCM_PLL1_CTRL_N(clk / 24000000),
- &ccm->pll1_c0_cfg);
- while (!(readl(&ccm->pll_stable_status) & 0x01)) {}
-
- writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 |
- CCM_PLL1_CTRL_N(clk / (24000000)),
- &ccm->pll1_c1_cfg);
- while (!(readl(&ccm->pll_stable_status) & 0x02)) {}
-
- /* Switch CPU to PLL1 */
- writel(AXI_DIV_2 << AXI0_DIV_SHIFT |
- AXI_DIV_2 << AXI1_DIV_SHIFT |
- CPU_CLK_SRC_PLL1 << C0_CPUX_CLK_SRC_SHIFT |
- CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT,
- &ccm->cpu_axi_cfg);
-}
-#endif
-
-void clock_set_pll5(unsigned int clk)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- unsigned int div1 = 0, div2 = 0;
-
- /* A83T PLL5 DDR rate = 24000000 * (n+1)/(div1+1)/(div2+1) */
- writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
- CCM_PLL5_CTRL_N(clk / (24000000)) |
- div2 << CCM_PLL5_DIV2_SHIFT |
- div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg);
-
- udelay(5500);
-}
-
-
-unsigned int clock_get_pll6(void)
-{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- uint32_t rval = readl(&ccm->pll6_cfg);
- int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
- int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
- CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
- int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
- CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
- return 24000000 * n / div1 / div2;
-}
+++ /dev/null
-/*
- * sun9i specific clock code
- *
- * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/prcm.h>
-#include <asm/arch/sys_proto.h>
-
-void clock_init_uart(void)
-{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- /* open the clock for uart */
- setbits_le32(&ccm->apb1_gate,
- CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT +
- CONFIG_CONS_INDEX - 1));
- /* deassert uart reset */
- setbits_le32(&ccm->apb1_reset_cfg,
- 1 << (APB1_RESET_UART_SHIFT +
- CONFIG_CONS_INDEX - 1));
-
- /* Dup with clock_init_safe(), drop once sun9i SPL support lands */
- writel(PLL4_CFG_DEFAULT, &ccm->pll4_periph0_cfg);
-}
-
-int clock_twi_onoff(int port, int state)
-{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- if (port > 4)
- return -1;
-
- /* set the apb reset and clock gate for twi */
- if (state) {
- setbits_le32(&ccm->apb1_gate,
- CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
- setbits_le32(&ccm->apb1_reset_cfg,
- 1 << (APB1_RESET_UART_SHIFT + port));
- } else {
- clrbits_le32(&ccm->apb1_reset_cfg,
- 1 << (APB1_RESET_UART_SHIFT + port));
- clrbits_le32(&ccm->apb1_gate,
- CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
- }
-
- return 0;
-}
-
-unsigned int clock_get_pll4_periph0(void)
-{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- uint32_t rval = readl(&ccm->pll4_periph0_cfg);
- int n = ((rval & CCM_PLL4_CTRL_N_MASK) >> CCM_PLL4_CTRL_N_SHIFT);
- int p = ((rval & CCM_PLL4_CTRL_P_MASK) >> CCM_PLL4_CTRL_P_SHIFT);
- int m = ((rval & CCM_PLL4_CTRL_M_MASK) >> CCM_PLL4_CTRL_M_SHIFT) + 1;
- const int k = 1;
-
- return ((24000000 * n * k) >> p) / m;
-}
+++ /dev/null
-/*
- * (C) Copyright 2007-2011
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <axp_pmic.h>
-#include <errno.h>
-
-#ifdef CONFIG_MACH_SUN6I
-int sunxi_get_ss_bonding_id(void)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- static int bonding_id = -1;
-
- if (bonding_id != -1)
- return bonding_id;
-
- /* Enable Security System */
- setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS);
- setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS);
-
- bonding_id = readl(SUNXI_SS_BASE);
- bonding_id = (bonding_id >> 16) & 0x7;
-
- /* Disable Security System again */
- clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS);
- clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS);
-
- return bonding_id;
-}
-#endif
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-int print_cpuinfo(void)
-{
-#ifdef CONFIG_MACH_SUN4I
- puts("CPU: Allwinner A10 (SUN4I)\n");
-#elif defined CONFIG_MACH_SUN5I
- u32 val = readl(SUNXI_SID_BASE + 0x08);
- switch ((val >> 12) & 0xf) {
- case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break;
- case 3: puts("CPU: Allwinner A13 (SUN5I)\n"); break;
- case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break;
- default: puts("CPU: Allwinner A1X (SUN5I)\n");
- }
-#elif defined CONFIG_MACH_SUN6I
- switch (sunxi_get_ss_bonding_id()) {
- case SUNXI_SS_BOND_ID_A31:
- puts("CPU: Allwinner A31 (SUN6I)\n");
- break;
- case SUNXI_SS_BOND_ID_A31S:
- puts("CPU: Allwinner A31s (SUN6I)\n");
- break;
- default:
- printf("CPU: Allwinner A31? (SUN6I, id: %d)\n",
- sunxi_get_ss_bonding_id());
- }
-#elif defined CONFIG_MACH_SUN7I
- puts("CPU: Allwinner A20 (SUN7I)\n");
-#elif defined CONFIG_MACH_SUN8I_A23
- puts("CPU: Allwinner A23 (SUN8I)\n");
-#elif defined CONFIG_MACH_SUN8I_A33
- puts("CPU: Allwinner A33 (SUN8I)\n");
-#elif defined CONFIG_MACH_SUN8I_H3
- puts("CPU: Allwinner H3 (SUN8I)\n");
-#elif defined CONFIG_MACH_SUN9I
- puts("CPU: Allwinner A80 (SUN9I)\n");
-#elif defined CONFIG_MACH_SUN8I_A83T
- puts("CPU: Allwinner A83T (SUN8I)\n");
-#else
-#warning Please update cpu_info.c with correct CPU information
- puts("CPU: SUNXI Family\n");
-#endif
- return 0;
-}
-#endif
-
-int sunxi_get_sid(unsigned int *sid)
-{
-#ifdef CONFIG_AXP221_POWER
- return axp_get_sid(sid);
-#elif defined SUNXI_SID_BASE
- int i;
-
- for (i = 0; i< 4; i++)
- sid[i] = readl(SUNXI_SID_BASE + 4 * i);
-
- return 0;
-#else
- return -ENODEV;
-#endif
-}
+++ /dev/null
-/*
- * DRAM init helper functions
- *
- * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/dram.h>
-
-/*
- * Wait up to 1s for value to be set in given part of reg.
- */
-void mctl_await_completion(u32 *reg, u32 mask, u32 val)
-{
- unsigned long tmo = timer_get_us() + 1000000;
-
- while ((readl(reg) & mask) != val) {
- if (timer_get_us() > tmo)
- panic("Timeout initialising DRAM\n");
- }
-}
-
-/*
- * Test if memory at offset offset matches memory at begin of DRAM
- */
-bool mctl_mem_matches(u32 offset)
-{
- /* Try to write different values to RAM at two addresses */
- writel(0, CONFIG_SYS_SDRAM_BASE);
- writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset);
- /* Check if the same value is actually observed when reading back */
- return readl(CONFIG_SYS_SDRAM_BASE) ==
- readl(CONFIG_SYS_SDRAM_BASE + offset);
-}
+++ /dev/null
-/*
- * sunxi DRAM controller initialization
- * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
- * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
- *
- * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
- * and earlier U-Boot Allwiner A10 SPL work
- *
- * (C) Copyright 2007-2012
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Berg Xing <bergxing@allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Unfortunately the only documentation we have on the sun7i DRAM
- * controller is Allwinner boot0 + boot1 code, and that code uses
- * magic numbers & shifts with no explanations. Hence this code is
- * rather undocumented and full of magic.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/dram.h>
-#include <asm/arch/timer.h>
-#include <asm/arch/sys_proto.h>
-
-#define CPU_CFG_CHIP_VER(n) ((n) << 6)
-#define CPU_CFG_CHIP_VER_MASK CPU_CFG_CHIP_VER(0x3)
-#define CPU_CFG_CHIP_REV_A 0x0
-#define CPU_CFG_CHIP_REV_C1 0x1
-#define CPU_CFG_CHIP_REV_C2 0x2
-#define CPU_CFG_CHIP_REV_B 0x3
-
-/*
- * Wait up to 1s for mask to be clear in given reg.
- */
-static inline void await_bits_clear(u32 *reg, u32 mask)
-{
- mctl_await_completion(reg, mask, 0);
-}
-
-/*
- * Wait up to 1s for mask to be set in given reg.
- */
-static inline void await_bits_set(u32 *reg, u32 mask)
-{
- mctl_await_completion(reg, mask, mask);
-}
-
-/*
- * This performs the external DRAM reset by driving the RESET pin low and
- * then high again. According to the DDR3 spec, the RESET pin needs to be
- * kept low for at least 200 us.
- */
-static void mctl_ddr3_reset(void)
-{
- struct sunxi_dram_reg *dram =
- (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-
-#ifdef CONFIG_MACH_SUN4I
- struct sunxi_timer_reg *timer =
- (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
- u32 reg_val;
-
- writel(0, &timer->cpu_cfg);
- reg_val = readl(&timer->cpu_cfg);
-
- if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
- CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
- setbits_le32(&dram->mcr, DRAM_MCR_RESET);
- udelay(200);
- clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
- } else
-#endif
- {
- clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
- udelay(200);
- setbits_le32(&dram->mcr, DRAM_MCR_RESET);
- }
- /* After the RESET pin is de-asserted, the DDR3 spec requires to wait
- * for additional 500 us before driving the CKE pin (Clock Enable)
- * high. The duration of this delay can be configured in the SDR_IDCR
- * (Initialization Delay Configuration Register) and applied
- * automatically by the DRAM controller during the DDR3 initialization
- * step. But SDR_IDCR has limited range on sun4i/sun5i hardware and
- * can't provide sufficient delay at DRAM clock frequencies higher than
- * 524 MHz (while Allwinner A13 supports DRAM clock frequency up to
- * 533 MHz according to the datasheet). Additionally, there is no
- * official documentation for the SDR_IDCR register anywhere, and
- * there is always a chance that we are interpreting it wrong.
- * Better be safe than sorry, so add an explicit delay here. */
- udelay(500);
-}
-
-static void mctl_set_drive(void)
-{
- struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-
-#ifdef CONFIG_MACH_SUN7I
- clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
-#else
- clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
-#endif
- DRAM_MCR_MODE_EN(0x3) |
- 0xffc);
-}
-
-static void mctl_itm_disable(void)
-{
- struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-
- clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF);
-}
-
-static void mctl_itm_enable(void)
-{
- struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-
- clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF);
-}
-
-static void mctl_itm_reset(void)
-{
- mctl_itm_disable();
- udelay(1); /* ITM reset needs a bit of delay */
- mctl_itm_enable();
- udelay(1);
-}
-
-static void mctl_enable_dll0(u32 phase)
-{
- struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-
- clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
- ((phase >> 16) & 0x3f) << 6);
- clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE);
- udelay(2);
-
- clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE);
- udelay(22);
-
- clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET);
- udelay(22);
-}
-
-/* Get the number of DDR byte lanes */
-static u32 mctl_get_number_of_lanes(void)
-{
- struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
- if ((readl(&dram->dcr) & DRAM_DCR_BUS_WIDTH_MASK) ==
- DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
- return 4;
- else
- return 2;
-}
-
-/*
- * Note: This differs from pm/standby in that it checks the bus width
- */
-static void mctl_enable_dllx(u32 phase)
-{
- struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
- u32 i, number_of_lanes;
-
- number_of_lanes = mctl_get_number_of_lanes();
-
- for (i = 1; i <= number_of_lanes; i++) {
- clrsetbits_le32(&dram->dllcr[i], 0xf << 14,
- (phase & 0xf) << 14);
- clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,
- DRAM_DLLCR_DISABLE);
- phase >>= 4;
- }
- udelay(2);
-
- for (i = 1; i <= number_of_lanes; i++)
- clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET |
- DRAM_DLLCR_DISABLE);
- udelay(22);
-
- for (i = 1; i <= number_of_lanes; i++)
- clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE,
- DRAM_DLLCR_NRESET);
- udelay(22);
-}
-
-static u32 hpcr_value[32] = {
-#ifdef CONFIG_MACH_SUN5I
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0x1031, 0x1031, 0x0735, 0x1035,
- 0x1035, 0x0731, 0x1031, 0,
- 0x0301, 0x0301, 0x0301, 0x0301,
- 0x0301, 0x0301, 0x0301, 0
-#endif
-#ifdef CONFIG_MACH_SUN4I
- 0x0301, 0x0301, 0x0301, 0x0301,
- 0x0301, 0x0301, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0x1031, 0x1031, 0x0735, 0x5031,
- 0x1035, 0x0731, 0x1031, 0x0735,
- 0x1035, 0x1031, 0x0731, 0x1035,
- 0x1031, 0x0301, 0x0301, 0x0731
-#endif
-#ifdef CONFIG_MACH_SUN7I
- 0x0301, 0x0301, 0x0301, 0x0301,
- 0x0301, 0x0301, 0x0301, 0x0301,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0x1031, 0x1031, 0x0735, 0x1035,
- 0x1035, 0x0731, 0x1031, 0x0735,
- 0x1035, 0x1031, 0x0731, 0x1035,
- 0x0001, 0x1031, 0, 0x1031
- /* last row differs from boot0 source table
- * 0x1031, 0x0301, 0x0301, 0x0731
- * but boot0 code skips #28 and #30, and sets #29 and #31 to the
- * value from #28 entry (0x1031)
- */
-#endif
-};
-
-static void mctl_configure_hostport(void)
-{
- struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
- u32 i;
-
- for (i = 0; i < 32; i++)
- writel(hpcr_value[i], &dram->hpcr[i]);
-}
-
-static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
-{
- u32 reg_val;
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- u32 pll5p_clk, pll6x_clk;
- u32 pll5p_div, pll6x_div;
- u32 pll5p_rate, pll6x_rate;
-
- /* setup DRAM PLL */
- reg_val = readl(&ccm->pll5_cfg);
- reg_val &= ~CCM_PLL5_CTRL_M_MASK; /* set M to 0 (x1) */
- reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */
- reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */
- reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */
-#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
- /* Old kernels are hardcoded to P=1 (divide by 2) */
- reg_val |= CCM_PLL5_CTRL_P(1);
-#endif
- if (clk >= 540 && clk < 552) {
- /* dram = 540MHz */
- reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
- reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
- reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
- } else if (clk >= 512 && clk < 528) {
- /* dram = 512MHz */
- reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
- reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
- reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
- } else if (clk >= 496 && clk < 504) {
- /* dram = 496MHz */
- reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
- reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
- reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
- } else if (clk >= 468 && clk < 480) {
- /* dram = 468MHz */
- reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
- reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
- reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
- } else if (clk >= 396 && clk < 408) {
- /* dram = 396MHz */
- reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
- reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
- reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
- } else {
- /* any other frequency that is a multiple of 24 */
- reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
- reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
- reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));
- }
- reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN; /* PLL VCO Gain off */
- reg_val |= CCM_PLL5_CTRL_EN; /* PLL On */
- writel(reg_val, &ccm->pll5_cfg);
- udelay(5500);
-
- setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);
-
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
- /* reset GPS */
- clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
- setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
- udelay(1);
- clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
-#endif
-
- /* setup MBUS clock */
- if (!mbus_clk)
- mbus_clk = 300;
-
- /* PLL5P and PLL6 are the potential clock sources for MBUS */
- pll6x_clk = clock_get_pll6() / 1000000;
-#ifdef CONFIG_MACH_SUN7I
- pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
-#endif
- pll5p_clk = clock_get_pll5p() / 1000000;
- pll6x_div = DIV_ROUND_UP(pll6x_clk, mbus_clk);
- pll5p_div = DIV_ROUND_UP(pll5p_clk, mbus_clk);
- pll6x_rate = pll6x_clk / pll6x_div;
- pll5p_rate = pll5p_clk / pll5p_div;
-
- if (pll6x_div <= 16 && pll6x_rate > pll5p_rate) {
- /* use PLL6 as the MBUS clock source */
- reg_val = CCM_MBUS_CTRL_GATE |
- CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
- CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
- CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll6x_div));
- } else if (pll5p_div <= 16) {
- /* use PLL5P as the MBUS clock source */
- reg_val = CCM_MBUS_CTRL_GATE |
- CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
- CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
- CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll5p_div));
- } else {
- panic("Bad mbus_clk\n");
- }
- writel(reg_val, &ccm->mbus_clk_cfg);
-
- /*
- * open DRAMC AHB & DLL register clock
- * close it first
- */
-#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
- clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
-#else
- clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
-#endif
- udelay(22);
-
- /* then open it */
-#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
- setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
-#else
- setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
-#endif
- udelay(22);
-}
-
-/*
- * The data from rslrX and rdgrX registers (X=rank) is stored
- * in a single 32-bit value using the following format:
- * bits [31:26] - DQS gating system latency for byte lane 3
- * bits [25:24] - DQS gating phase select for byte lane 3
- * bits [23:18] - DQS gating system latency for byte lane 2
- * bits [17:16] - DQS gating phase select for byte lane 2
- * bits [15:10] - DQS gating system latency for byte lane 1
- * bits [ 9:8 ] - DQS gating phase select for byte lane 1
- * bits [ 7:2 ] - DQS gating system latency for byte lane 0
- * bits [ 1:0 ] - DQS gating phase select for byte lane 0
- */
-static void mctl_set_dqs_gating_delay(int rank, u32 dqs_gating_delay)
-{
- struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
- u32 lane, number_of_lanes = mctl_get_number_of_lanes();
- /* rank0 gating system latency (3 bits per lane: cycles) */
- u32 slr = readl(rank == 0 ? &dram->rslr0 : &dram->rslr1);
- /* rank0 gating phase select (2 bits per lane: 90, 180, 270, 360) */
- u32 dgr = readl(rank == 0 ? &dram->rdgr0 : &dram->rdgr1);
- for (lane = 0; lane < number_of_lanes; lane++) {
- u32 tmp = dqs_gating_delay >> (lane * 8);
- slr &= ~(7 << (lane * 3));
- slr |= ((tmp >> 2) & 7) << (lane * 3);
- dgr &= ~(3 << (lane * 2));
- dgr |= (tmp & 3) << (lane * 2);
- }
- writel(slr, rank == 0 ? &dram->rslr0 : &dram->rslr1);
- writel(dgr, rank == 0 ? &dram->rdgr0 : &dram->rdgr1);
-}
-
-static int dramc_scan_readpipe(void)
-{
- struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
- u32 reg_val;
-
- /* data training trigger */
- clrbits_le32(&dram->csr, DRAM_CSR_FAILED);
- setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
-
- /* check whether data training process has completed */
- await_bits_clear(&dram->ccr, DRAM_CCR_DATA_TRAINING);
-
- /* check data training result */
- reg_val = readl(&dram->csr);
- if (reg_val & DRAM_CSR_FAILED)
- return -1;
-
- return 0;
-}
-
-static void dramc_clock_output_en(u32 on)
-{
-#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
- struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-
- if (on)
- setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
- else
- clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
-#endif
-#ifdef CONFIG_MACH_SUN4I
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- if (on)
- setbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT);
- else
- clrbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT);
-#endif
-}
-
-/* tRFC in nanoseconds for different densities (from the DDR3 spec) */
-static const u16 tRFC_DDR3_table[6] = {
- /* 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb */
- 90, 90, 110, 160, 300, 350
-};
-
-static void dramc_set_autorefresh_cycle(u32 clk, u32 density)
-{
- struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
- u32 tRFC, tREFI;
-
- tRFC = (tRFC_DDR3_table[density] * clk + 999) / 1000;
- tREFI = (7987 * clk) >> 10; /* <= 7.8us */
-
- writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr);
-}
-
-/* Calculate the value for A11, A10, A9 bits in MR0 (write recovery) */
-static u32 ddr3_write_recovery(u32 clk)
-{
- u32 twr_ns = 15; /* DDR3 spec says that it is 15ns for all speed bins */
- u32 twr_ck = (twr_ns * clk + 999) / 1000;
- if (twr_ck < 5)
- return 1;
- else if (twr_ck <= 8)
- return twr_ck - 4;
- else if (twr_ck <= 10)
- return 5;
- else
- return 6;
-}
-
-/*
- * If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this
- * means that DRAM is currently in self-refresh mode and retaining the old
- * data. Since we have no idea what to do in this situation yet, just set this
- * register to 0 and initialize DRAM in the same way as on any normal reboot
- * (discarding whatever was stored there).
- *
- * Note: on sun7i hardware, the highest 16 bits need to be set to 0x1651 magic
- * value for this write operation to have any effect. On sun5i hadware this
- * magic value is not necessary. And on sun4i hardware the writes to this
- * register seem to have no effect at all.
- */
-static void mctl_disable_power_save(void)
-{
- struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
- writel(0x16510000, &dram->ppwrsctl);
-}
-
-/*
- * After the DRAM is powered up or reset, the DDR3 spec requires to wait at
- * least 500 us before driving the CKE pin (Clock Enable) high. The dram->idct
- * (SDR_IDCR) register appears to configure this delay, which gets applied
- * right at the time when the DRAM initialization is activated in the
- * 'mctl_ddr3_initialize' function.
- */
-static void mctl_set_cke_delay(void)
-{
- struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-
- /* The CKE delay is represented in DRAM clock cycles, multiplied by N
- * (where N=2 for sun4i/sun5i and N=3 for sun7i). Here it is set to
- * the maximum possible value 0x1ffff, just like in the Allwinner's
- * boot0 bootloader. The resulting delay value is somewhere between
- * ~0.4 ms (sun5i with 648 MHz DRAM clock speed) and ~1.1 ms (sun7i
- * with 360 MHz DRAM clock speed). */
- setbits_le32(&dram->idcr, 0x1ffff);
-}
-
-/*
- * This triggers the DRAM initialization. It performs sending the mode registers
- * to the DRAM among other things. Very likely the ZQCL command is also getting
- * executed (to do the initial impedance calibration on the DRAM side of the
- * wire). The memory controller and the PHY must be already configured before
- * calling this function.
- */
-static void mctl_ddr3_initialize(void)
-{
- struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
- setbits_le32(&dram->ccr, DRAM_CCR_INIT);
- await_bits_clear(&dram->ccr, DRAM_CCR_INIT);
-}
-
-/*
- * Perform impedance calibration on the DRAM controller side of the wire.
- */
-static void mctl_set_impedance(u32 zq, bool odt_en)
-{
- struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
- u32 reg_val;
- u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF;
-
-#ifndef CONFIG_MACH_SUN7I
- /* Appears that some kind of automatically initiated default
- * ZQ calibration is already in progress at this point on sun4i/sun5i
- * hardware, but not on sun7i. So it is reasonable to wait for its
- * completion before doing anything else. */
- await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);
-#endif
-
- /* ZQ calibration is not really useful unless ODT is enabled */
- if (!odt_en)
- return;
-
-#ifdef CONFIG_MACH_SUN7I
- /* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock
- * unless bit 24 is set in SDR_ZQCR1. Not much is known about the
- * SDR_ZQCR1 register, but there are hints indicating that it might
- * be related to periodic impedance re-calibration. This particular
- * magic value is borrowed from the Allwinner boot0 bootloader, and
- * using it helps to avoid troubles */
- writel((1 << 24) | (1 << 1), &dram->zqcr1);
-#endif
-
- /* Needed at least for sun5i, because it does not self clear there */
- clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);
-
- if (zdata) {
- /* Set the user supplied impedance data */
- reg_val = DRAM_ZQCR0_ZDEN | zdata;
- writel(reg_val, &dram->zqcr0);
- /* no need to wait, this takes effect immediately */
- } else {
- /* Do the calibration using the external resistor */
- reg_val = DRAM_ZQCR0_ZCAL | DRAM_ZQCR0_IMP_DIV(zprog);
- writel(reg_val, &dram->zqcr0);
- /* Wait for the new impedance configuration to settle */
- await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);
- }
-
- /* Needed at least for sun5i, because it does not self clear there */
- clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);
-
- /* Set I/O configure register */
- writel(DRAM_IOCR_ODT_EN, &dram->iocr);
-}
-
-static unsigned long dramc_init_helper(struct dram_para *para)
-{
- struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
- u32 reg_val;
- u32 density;
- int ret_val;
-
- /*
- * only single rank DDR3 is supported by this code even though the
- * hardware can theoretically support DDR2 and up to two ranks
- */
- if (para->type != DRAM_MEMORY_TYPE_DDR3 || para->rank_num != 1)
- return 0;
-
- /* setup DRAM relative clock */
- mctl_setup_dram_clock(para->clock, para->mbus_clock);
-
- /* Disable any pad power save control */
- mctl_disable_power_save();
-
- mctl_set_drive();
-
- /* dram clock off */
- dramc_clock_output_en(0);
-
-#ifdef CONFIG_MACH_SUN4I
- /* select dram controller 1 */
- writel(DRAM_CSEL_MAGIC, &dram->csel);
-#endif
-
- mctl_itm_disable();
- mctl_enable_dll0(para->tpr3);
-
- /* configure external DRAM */
- reg_val = DRAM_DCR_TYPE_DDR3;
- reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3);
-
- if (para->density == 256)
- density = DRAM_DCR_CHIP_DENSITY_256M;
- else if (para->density == 512)
- density = DRAM_DCR_CHIP_DENSITY_512M;
- else if (para->density == 1024)
- density = DRAM_DCR_CHIP_DENSITY_1024M;
- else if (para->density == 2048)
- density = DRAM_DCR_CHIP_DENSITY_2048M;
- else if (para->density == 4096)
- density = DRAM_DCR_CHIP_DENSITY_4096M;
- else if (para->density == 8192)
- density = DRAM_DCR_CHIP_DENSITY_8192M;
- else
- density = DRAM_DCR_CHIP_DENSITY_256M;
-
- reg_val |= DRAM_DCR_CHIP_DENSITY(density);
- reg_val |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1);
- reg_val |= DRAM_DCR_RANK_SEL(para->rank_num - 1);
- reg_val |= DRAM_DCR_CMD_RANK_ALL;
- reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
- writel(reg_val, &dram->dcr);
-
- dramc_clock_output_en(1);
-
- mctl_set_impedance(para->zq, para->odt_en);
-
- mctl_set_cke_delay();
-
- mctl_ddr3_reset();
-
- udelay(1);
-
- await_bits_clear(&dram->ccr, DRAM_CCR_INIT);
-
- mctl_enable_dllx(para->tpr3);
-
- /* set refresh period */
- dramc_set_autorefresh_cycle(para->clock, density);
-
- /* set timing parameters */
- writel(para->tpr0, &dram->tpr0);
- writel(para->tpr1, &dram->tpr1);
- writel(para->tpr2, &dram->tpr2);
-
- reg_val = DRAM_MR_BURST_LENGTH(0x0);
-#if (defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I))
- reg_val |= DRAM_MR_POWER_DOWN;
-#endif
- reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
- reg_val |= DRAM_MR_WRITE_RECOVERY(ddr3_write_recovery(para->clock));
- writel(reg_val, &dram->mr);
-
- writel(para->emr1, &dram->emr);
- writel(para->emr2, &dram->emr2);
- writel(para->emr3, &dram->emr3);
-
- /* disable drift compensation and set passive DQS window mode */
- clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
-
-#ifdef CONFIG_MACH_SUN7I
- /* Command rate timing mode 2T & 1T */
- if (para->tpr4 & 0x1)
- setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
-#endif
- /* initialize external DRAM */
- mctl_ddr3_initialize();
-
- /* scan read pipe value */
- mctl_itm_enable();
-
- /* Hardware DQS gate training */
- ret_val = dramc_scan_readpipe();
-
- if (ret_val < 0)
- return 0;
-
- /* allow to override the DQS training results with a custom delay */
- if (para->dqs_gating_delay)
- mctl_set_dqs_gating_delay(0, para->dqs_gating_delay);
-
- /* set the DQS gating window type */
- if (para->active_windowing)
- clrbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);
- else
- setbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);
-
- mctl_itm_reset();
-
- /* configure all host port */
- mctl_configure_hostport();
-
- return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
-}
-
-unsigned long dramc_init(struct dram_para *para)
-{
- unsigned long dram_size, actual_density;
-
- /* If the dram configuration is not provided, use a default */
- if (!para)
- return 0;
-
- /* if everything is known, then autodetection is not necessary */
- if (para->io_width && para->bus_width && para->density)
- return dramc_init_helper(para);
-
- /* try to autodetect the DRAM bus width and density */
- para->io_width = 16;
- para->bus_width = 32;
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I)
- /* only A0-A14 address lines on A10/A13, limiting max density to 4096 */
- para->density = 4096;
-#else
- /* all A0-A15 address lines on A20, which allow density 8192 */
- para->density = 8192;
-#endif
-
- dram_size = dramc_init_helper(para);
- if (!dram_size) {
- /* if 32-bit bus width failed, try 16-bit bus width instead */
- para->bus_width = 16;
- dram_size = dramc_init_helper(para);
- if (!dram_size) {
- /* if 16-bit bus width also failed, then bail out */
- return dram_size;
- }
- }
-
- /* check if we need to adjust the density */
- actual_density = (dram_size >> 17) * para->io_width / para->bus_width;
-
- if (actual_density != para->density) {
- /* update the density and re-initialize DRAM again */
- para->density = actual_density;
- dram_size = dramc_init_helper(para);
- }
-
- return dram_size;
-}
+++ /dev/null
-/*
- * Sun6i platform dram controller init.
- *
- * (C) Copyright 2007-2012
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Berg Xing <bergxing@allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- *
- * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/dram.h>
-#include <asm/arch/prcm.h>
-
-#define DRAM_CLK (CONFIG_DRAM_CLK * 1000000)
-
-struct dram_sun6i_para {
- u8 bus_width;
- u8 chan;
- u8 rank;
- u8 rows;
- u16 page_size;
-};
-
-static void mctl_sys_init(void)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- const int dram_clk_div = 2;
-
- clock_set_pll5(DRAM_CLK * dram_clk_div, false);
-
- clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK,
- CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST |
- CCM_DRAMCLK_CFG_UPD);
- mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
-
- writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg);
-
- /* deassert mctl reset */
- setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
-
- /* enable mctl clock */
- setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
-}
-
-static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para)
-{
- struct sunxi_mctl_phy_reg *mctl_phy;
-
- if (ch_index == 0)
- mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
- else
- mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
-
- /* disable + reset dlls */
- writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr);
- writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr);
- writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr);
- if (para->bus_width == 32) {
- writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr);
- writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr);
- }
- udelay(2);
-
- /* enable + reset dlls */
- writel(0, &mctl_phy->acdllcr);
- writel(0, &mctl_phy->dx0dllcr);
- writel(0, &mctl_phy->dx1dllcr);
- if (para->bus_width == 32) {
- writel(0, &mctl_phy->dx2dllcr);
- writel(0, &mctl_phy->dx3dllcr);
- }
- udelay(22);
-
- /* enable and release reset of dlls */
- writel(MCTL_DLLCR_NRESET, &mctl_phy->acdllcr);
- writel(MCTL_DLLCR_NRESET, &mctl_phy->dx0dllcr);
- writel(MCTL_DLLCR_NRESET, &mctl_phy->dx1dllcr);
- if (para->bus_width == 32) {
- writel(MCTL_DLLCR_NRESET, &mctl_phy->dx2dllcr);
- writel(MCTL_DLLCR_NRESET, &mctl_phy->dx3dllcr);
- }
- udelay(22);
-}
-
-static bool mctl_rank_detect(u32 *gsr0, int rank)
-{
- const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank;
- const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank;
-
- mctl_await_completion(gsr0, done, done);
- mctl_await_completion(gsr0 + 0x10, done, done);
-
- return !(readl(gsr0) & err) && !(readl(gsr0 + 0x10) & err);
-}
-
-static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- struct sunxi_mctl_ctl_reg *mctl_ctl;
- struct sunxi_mctl_phy_reg *mctl_phy;
-
- if (ch_index == 0) {
- mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
- mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
- } else {
- mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE;
- mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
- }
-
- writel(MCTL_MCMD_NOP, &mctl_ctl->mcmd);
- mctl_await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0);
-
- /* PHY initialization */
- writel(MCTL_PGCR, &mctl_phy->pgcr);
- writel(MCTL_MR0, &mctl_phy->mr0);
- writel(MCTL_MR1, &mctl_phy->mr1);
- writel(MCTL_MR2, &mctl_phy->mr2);
- writel(MCTL_MR3, &mctl_phy->mr3);
-
- writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST,
- &mctl_phy->ptr0);
-
- writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1);
- writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2);
-
- writel((MCTL_TCCD << 31) | (MCTL_TRC << 25) | (MCTL_TRRD << 21) |
- (MCTL_TRAS << 16) | (MCTL_TRCD << 12) | (MCTL_TRP << 8) |
- (MCTL_TWTR << 5) | (MCTL_TRTP << 2) | (MCTL_TMRD << 0),
- &mctl_phy->dtpr0);
-
- writel((MCTL_TDQSCKMAX << 27) | (MCTL_TDQSCK << 24) |
- (MCTL_TRFC << 16) | (MCTL_TRTODT << 11) |
- ((MCTL_TMOD - 12) << 9) | (MCTL_TFAW << 3) | (0 << 2) |
- (MCTL_TAOND << 0), &mctl_phy->dtpr1);
-
- writel((MCTL_TDLLK << 19) | (MCTL_TCKE << 15) | (MCTL_TXPDLL << 10) |
- (MCTL_TEXSR << 0), &mctl_phy->dtpr2);
-
- writel(1, &mctl_ctl->dfitphyupdtype0);
- writel(MCTL_DCR_DDR3, &mctl_phy->dcr);
- writel(MCTL_DSGCR, &mctl_phy->dsgcr);
- writel(MCTL_DXCCR, &mctl_phy->dxccr);
- writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx0gcr);
- writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx1gcr);
- writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx2gcr);
- writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx3gcr);
-
- mctl_await_completion(&mctl_phy->pgsr, 0x03, 0x03);
-
- writel(CONFIG_DRAM_ZQ, &mctl_phy->zq0cr1);
-
- setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
- writel(MCTL_PIR_STEP1, &mctl_phy->pir);
- udelay(10);
- mctl_await_completion(&mctl_phy->pgsr, 0x1f, 0x1f);
-
- /* rank detect */
- if (!mctl_rank_detect(&mctl_phy->dx0gsr0, 1)) {
- para->rank = 1;
- clrbits_le32(&mctl_phy->pgcr, MCTL_PGCR_RANK);
- }
-
- /*
- * channel detect, check channel 1 dx0 and dx1 have rank 0, if not
- * assume nothing is connected to channel 1.
- */
- if (ch_index == 1 && !mctl_rank_detect(&mctl_phy->dx0gsr0, 0)) {
- para->chan = 1;
- clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
- return;
- }
-
- /* bus width detect, if dx2 and dx3 don't have rank 0, assume 16 bit */
- if (!mctl_rank_detect(&mctl_phy->dx2gsr0, 0)) {
- para->bus_width = 16;
- para->page_size = 2048;
- setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE);
- setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE);
- clrbits_le32(&mctl_phy->dx2gcr, MCTL_DX_GCR_EN);
- clrbits_le32(&mctl_phy->dx3gcr, MCTL_DX_GCR_EN);
- }
-
- setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
- writel(MCTL_PIR_STEP2, &mctl_phy->pir);
- udelay(10);
- mctl_await_completion(&mctl_phy->pgsr, 0x11, 0x11);
-
- if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK)
- panic("Training error initialising DRAM\n");
-
- /* Move to configure state */
- writel(MCTL_SCTL_CONFIG, &mctl_ctl->sctl);
- mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x01);
-
- /* Set number of clks per micro-second */
- writel(DRAM_CLK / 1000000, &mctl_ctl->togcnt1u);
- /* Set number of clks per 100 nano-seconds */
- writel(DRAM_CLK / 10000000, &mctl_ctl->togcnt100n);
- /* Set memory timing registers */
- writel(MCTL_TREFI, &mctl_ctl->trefi);
- writel(MCTL_TMRD, &mctl_ctl->tmrd);
- writel(MCTL_TRFC, &mctl_ctl->trfc);
- writel((MCTL_TPREA << 16) | MCTL_TRP, &mctl_ctl->trp);
- writel(MCTL_TRTW, &mctl_ctl->trtw);
- writel(MCTL_TAL, &mctl_ctl->tal);
- writel(MCTL_TCL, &mctl_ctl->tcl);
- writel(MCTL_TCWL, &mctl_ctl->tcwl);
- writel(MCTL_TRAS, &mctl_ctl->tras);
- writel(MCTL_TRC, &mctl_ctl->trc);
- writel(MCTL_TRCD, &mctl_ctl->trcd);
- writel(MCTL_TRRD, &mctl_ctl->trrd);
- writel(MCTL_TRTP, &mctl_ctl->trtp);
- writel(MCTL_TWR, &mctl_ctl->twr);
- writel(MCTL_TWTR, &mctl_ctl->twtr);
- writel(MCTL_TEXSR, &mctl_ctl->texsr);
- writel(MCTL_TXP, &mctl_ctl->txp);
- writel(MCTL_TXPDLL, &mctl_ctl->txpdll);
- writel(MCTL_TZQCS, &mctl_ctl->tzqcs);
- writel(MCTL_TZQCSI, &mctl_ctl->tzqcsi);
- writel(MCTL_TDQS, &mctl_ctl->tdqs);
- writel(MCTL_TCKSRE, &mctl_ctl->tcksre);
- writel(MCTL_TCKSRX, &mctl_ctl->tcksrx);
- writel(MCTL_TCKE, &mctl_ctl->tcke);
- writel(MCTL_TMOD, &mctl_ctl->tmod);
- writel(MCTL_TRSTL, &mctl_ctl->trstl);
- writel(MCTL_TZQCL, &mctl_ctl->tzqcl);
- writel(MCTL_TMRR, &mctl_ctl->tmrr);
- writel(MCTL_TCKESR, &mctl_ctl->tckesr);
- writel(MCTL_TDPD, &mctl_ctl->tdpd);
-
- /* Unknown magic performed by boot0 */
- setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3);
- clrbits_le32(&mctl_ctl->dfiodtcfg1, 0x1f);
-
- /* Select 16/32-bits mode for MCTL */
- if (para->bus_width == 16)
- setbits_le32(&mctl_ctl->ppcfg, 1);
-
- /* Set DFI timing registers */
- writel(MCTL_TCWL, &mctl_ctl->dfitphywrl);
- writel(MCTL_TCL - 1, &mctl_ctl->dfitrdden);
- writel(MCTL_DFITPHYRDL, &mctl_ctl->dfitphyrdl);
- writel(MCTL_DFISTCFG0, &mctl_ctl->dfistcfg0);
-
- writel(MCTL_MCFG_DDR3, &mctl_ctl->mcfg);
-
- /* DFI update configuration register */
- writel(MCTL_DFIUPDCFG_UPD, &mctl_ctl->dfiupdcfg);
-
- /* Move to access state */
- writel(MCTL_SCTL_ACCESS, &mctl_ctl->sctl);
- mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x03);
-}
-
-static void mctl_com_init(struct dram_sun6i_para *para)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- struct sunxi_mctl_phy_reg * const mctl_phy1 =
- (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
- struct sunxi_prcm_reg * const prcm =
- (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
-
- writel(MCTL_CR_UNKNOWN | MCTL_CR_CHANNEL(para->chan) | MCTL_CR_DDR3 |
- ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) |
- MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
- MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr);
-
- /* Unknown magic performed by boot0 */
- setbits_le32(&mctl_com->dbgcr, (1 << 6));
-
- if (para->chan == 1) {
- /* Shutdown channel 1 */
- setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE);
- setbits_le32(&mctl_phy1->dxccr, MCTL_DXCCR_DISABLE);
- clrbits_le32(&mctl_phy1->dsgcr, MCTL_DSGCR_ENABLE);
- /*
- * CH0 ?? this is what boot0 does. Leave as is until we can
- * confirm this.
- */
- setbits_le32(&prcm->vdd_sys_pwroff,
- PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF);
- }
-}
-
-static void mctl_port_cfg(void)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- /* enable DRAM AXI clock for CPU access */
- setbits_le32(&ccm->axi_gate, 1 << AXI_GATE_OFFSET_DRAM);
-
- /* Bunch of magic writes performed by boot0 */
- writel(0x00400302, &mctl_com->rmcr[0]);
- writel(0x01000307, &mctl_com->rmcr[1]);
- writel(0x00400302, &mctl_com->rmcr[2]);
- writel(0x01000307, &mctl_com->rmcr[3]);
- writel(0x01000307, &mctl_com->rmcr[4]);
- writel(0x01000303, &mctl_com->rmcr[6]);
- writel(0x01000303, &mctl_com->mmcr[0]);
- writel(0x00400310, &mctl_com->mmcr[1]);
- writel(0x01000307, &mctl_com->mmcr[2]);
- writel(0x01000303, &mctl_com->mmcr[3]);
- writel(0x01800303, &mctl_com->mmcr[4]);
- writel(0x01800303, &mctl_com->mmcr[5]);
- writel(0x01800303, &mctl_com->mmcr[6]);
- writel(0x01800303, &mctl_com->mmcr[7]);
- writel(0x01000303, &mctl_com->mmcr[8]);
- writel(0x00000002, &mctl_com->mmcr[15]);
- writel(0x00000310, &mctl_com->mbagcr[0]);
- writel(0x00400310, &mctl_com->mbagcr[1]);
- writel(0x00400310, &mctl_com->mbagcr[2]);
- writel(0x00000307, &mctl_com->mbagcr[3]);
- writel(0x00000317, &mctl_com->mbagcr[4]);
- writel(0x00000307, &mctl_com->mbagcr[5]);
-}
-
-unsigned long sunxi_dram_init(void)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- u32 offset;
- int bank, bus, columns;
-
- /* Set initial parameters, these get modified by the autodetect code */
- struct dram_sun6i_para para = {
- .bus_width = 32,
- .chan = 2,
- .rank = 2,
- .page_size = 4096,
- .rows = 16,
- };
-
- /* A31s only has one channel */
- if (sunxi_get_ss_bonding_id() == SUNXI_SS_BOND_ID_A31S)
- para.chan = 1;
-
- mctl_sys_init();
-
- mctl_dll_init(0, ¶);
- setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN);
-
- if (para.chan == 2) {
- mctl_dll_init(1, ¶);
- setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
- }
-
- setbits_le32(&mctl_com->ccr, MCTL_CCR_MASTER_CLK_EN);
-
- mctl_channel_init(0, ¶);
- if (para.chan == 2)
- mctl_channel_init(1, ¶);
-
- mctl_com_init(¶);
- mctl_port_cfg();
-
- /*
- * Change to 1 ch / sequence / 8192 byte pages / 16 rows /
- * 8 bit banks / 1 rank mode.
- */
- clrsetbits_le32(&mctl_com->cr,
- MCTL_CR_CHANNEL_MASK | MCTL_CR_PAGE_SIZE_MASK |
- MCTL_CR_ROW_MASK | MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
- MCTL_CR_CHANNEL(1) | MCTL_CR_SEQUENCE |
- MCTL_CR_PAGE_SIZE(8192) | MCTL_CR_ROW(16) |
- MCTL_CR_BANK(1) | MCTL_CR_RANK(1));
-
- /* Detect and set page size */
- for (columns = 7; columns < 20; columns++) {
- if (mctl_mem_matches(1 << columns))
- break;
- }
- bus = (para.bus_width == 32) ? 2 : 1;
- columns -= bus;
- para.page_size = (1 << columns) * (bus << 1);
- clrsetbits_le32(&mctl_com->cr, MCTL_CR_PAGE_SIZE_MASK,
- MCTL_CR_PAGE_SIZE(para.page_size));
-
- /* Detect and set rows */
- for (para.rows = 11; para.rows < 16; para.rows++) {
- offset = 1 << (para.rows + columns + bus);
- if (mctl_mem_matches(offset))
- break;
- }
- clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
- MCTL_CR_ROW(para.rows));
-
- /* Detect bank size */
- offset = 1 << (para.rows + columns + bus + 2);
- bank = mctl_mem_matches(offset) ? 0 : 1;
-
- /* Restore interleave, chan and rank values, set bank size */
- clrsetbits_le32(&mctl_com->cr,
- MCTL_CR_CHANNEL_MASK | MCTL_CR_SEQUENCE |
- MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
- MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) |
- MCTL_CR_RANK(para.rank));
-
- return 1 << (para.rank + para.rows + bank + columns + para.chan + bus);
-}
+++ /dev/null
-/*
- * Sun8i platform dram controller init.
- *
- * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Note this code uses a lot of magic hex values, that is because this code
- * simply replays the init sequence as done by the Allwinner boot0 code, so
- * we do not know what these values mean. There are no symbolic constants for
- * these magic values, since we do not know how to name them and making up
- * names for them is not useful.
- *
- * The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one
- * found in the TI Keystone2 documentation:
- * http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf
- * "Table4-2 DDR3 PHY Registers"
- * This may be used as a (possible) reference for future work / cleanups.
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/dram.h>
-#include <asm/arch/prcm.h>
-
-static const struct dram_para dram_para = {
- .clock = CONFIG_DRAM_CLK,
- .type = 3,
- .zq = CONFIG_DRAM_ZQ,
- .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN),
- .odt_correction = CONFIG_DRAM_ODT_CORRECTION,
- .para1 = 0, /* not used (only used when tpr13 bit 31 is set */
- .para2 = 0, /* not used (only used when tpr13 bit 31 is set */
- .mr0 = 6736,
- .mr1 = 4,
- .mr2 = 16,
- .mr3 = 0,
- /* tpr0 - 10 contain timing constants or-ed together in u32 vals */
- .tpr0 = 0x2ab83def,
- .tpr1 = 0x18082356,
- .tpr2 = 0x00034156,
- .tpr3 = 0x448c5533,
- .tpr4 = 0x08010d00,
- .tpr5 = 0x0340b20f,
- .tpr6 = 0x20d118cc,
- .tpr7 = 0x14062485,
- .tpr8 = 0x220d1d52,
- .tpr9 = 0x1e078c22,
- .tpr10 = 0x3c,
- .tpr11 = 0, /* not used */
- .tpr12 = 0, /* not used */
- .tpr13 = 0x30000,
-};
-
-static void mctl_sys_init(void)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- /* enable pll5, note the divide by 2 is deliberate! */
- clock_set_pll5(dram_para.clock * 1000000 / 2,
- dram_para.tpr13 & 0x40000);
-
- /* deassert ahb mctl reset */
- setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
-
- /* enable ahb mctl clock */
- setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
-}
-
-static void mctl_apply_odt_correction(u32 *reg, int correction)
-{
- int val;
-
- val = (readl(reg) >> 8) & 0xff;
- val += correction;
-
- /* clamp */
- if (val < 0)
- val = 0;
- else if (val > 255)
- val = 255;
-
- clrsetbits_le32(reg, 0xff00, val << 8);
-}
-
-static void mctl_init(u32 *bus_width)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
- struct sunxi_mctl_phy_reg * const mctl_phy =
- (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
-
- if (dram_para.tpr13 & 0x20)
- writel(0x40b, &mctl_phy->dcr);
- else
- writel(0x1000040b, &mctl_phy->dcr);
-
- if (dram_para.clock >= 480)
- writel(0x5c000, &mctl_phy->dllgcr);
- else
- writel(0xdc000, &mctl_phy->dllgcr);
-
- writel(0x0a003e3f, &mctl_phy->pgcr0);
- writel(0x03008421, &mctl_phy->pgcr1);
-
- writel(dram_para.mr0, &mctl_phy->mr0);
- writel(dram_para.mr1, &mctl_phy->mr1);
- writel(dram_para.mr2, &mctl_phy->mr2);
- writel(dram_para.mr3, &mctl_phy->mr3);
-
- if (!(dram_para.tpr13 & 0x10000)) {
- clrsetbits_le32(&mctl_phy->dx0gcr, 0x3800, 0x2000);
- clrsetbits_le32(&mctl_phy->dx1gcr, 0x3800, 0x2000);
- }
-
- /*
- * All the masking and shifting below converts what I assume are DDR
- * timing constants from Allwinner dram_para tpr format to the actual
- * timing registers format.
- */
-
- writel((dram_para.tpr0 & 0x000fffff), &mctl_phy->ptr2);
- writel((dram_para.tpr1 & 0x1fffffff), &mctl_phy->ptr3);
- writel((dram_para.tpr0 & 0x3ff00000) >> 2 |
- (dram_para.tpr2 & 0x0003ffff), &mctl_phy->ptr4);
-
- writel(dram_para.tpr3, &mctl_phy->dtpr0);
- writel(dram_para.tpr4, &mctl_phy->dtpr2);
-
- writel(0x01000081, &mctl_phy->dtcr);
-
- if (dram_para.clock <= 240 || !dram_para.odt_en) {
- clrbits_le32(&mctl_phy->dx0gcr, 0x600);
- clrbits_le32(&mctl_phy->dx1gcr, 0x600);
- }
- if (dram_para.clock <= 240) {
- writel(0, &mctl_phy->odtcr);
- writel(0, &mctl_ctl->odtmap);
- }
-
- writel(((dram_para.tpr5 & 0x0f00) << 12) |
- ((dram_para.tpr5 & 0x00f8) << 9) |
- ((dram_para.tpr5 & 0x0007) << 8),
- &mctl_ctl->rfshctl0);
-
- writel(((dram_para.tpr5 & 0x0003f000) << 12) |
- ((dram_para.tpr5 & 0x00fc0000) >> 2) |
- ((dram_para.tpr5 & 0x3f000000) >> 16) |
- ((dram_para.tpr6 & 0x0000003f) >> 0),
- &mctl_ctl->dramtmg0);
-
- writel(((dram_para.tpr6 & 0x000007c0) << 10) |
- ((dram_para.tpr6 & 0x0000f800) >> 3) |
- ((dram_para.tpr6 & 0x003f0000) >> 16),
- &mctl_ctl->dramtmg1);
-
- writel(((dram_para.tpr6 & 0x0fc00000) << 2) |
- ((dram_para.tpr7 & 0x0000001f) << 16) |
- ((dram_para.tpr7 & 0x000003e0) << 3) |
- ((dram_para.tpr7 & 0x0000fc00) >> 10),
- &mctl_ctl->dramtmg2);
-
- writel(((dram_para.tpr7 & 0x03ff0000) >> 16) |
- ((dram_para.tpr6 & 0xf0000000) >> 16),
- &mctl_ctl->dramtmg3);
-
- writel(((dram_para.tpr7 & 0x3c000000) >> 2 ) |
- ((dram_para.tpr8 & 0x00000007) << 16) |
- ((dram_para.tpr8 & 0x00000038) << 5) |
- ((dram_para.tpr8 & 0x000003c0) >> 6),
- &mctl_ctl->dramtmg4);
-
- writel(((dram_para.tpr8 & 0x00003c00) << 14) |
- ((dram_para.tpr8 & 0x0003c000) << 2) |
- ((dram_para.tpr8 & 0x00fc0000) >> 10) |
- ((dram_para.tpr8 & 0x0f000000) >> 24),
- &mctl_ctl->dramtmg5);
-
- writel(0x00000008, &mctl_ctl->dramtmg8);
-
- writel(((dram_para.tpr8 & 0xf0000000) >> 4) |
- ((dram_para.tpr9 & 0x00007c00) << 6) |
- ((dram_para.tpr9 & 0x000003e0) << 3) |
- ((dram_para.tpr9 & 0x0000001f) >> 0),
- &mctl_ctl->pitmg0);
-
- setbits_le32(&mctl_ctl->pitmg1, 0x80000);
-
- writel(((dram_para.tpr9 & 0x003f8000) << 9) | 0x2001,
- &mctl_ctl->sched);
-
- writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3);
- writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4);
-
- writel(0x00000000, &mctl_ctl->pimisc);
- writel(0x80000000, &mctl_ctl->upd0);
-
- writel(((dram_para.tpr9 & 0xffc00000) >> 22) |
- ((dram_para.tpr10 & 0x00000fff) << 16),
- &mctl_ctl->rfshtmg);
-
- if (dram_para.tpr13 & 0x20)
- writel(0x01040001, &mctl_ctl->mstr);
- else
- writel(0x01040401, &mctl_ctl->mstr);
-
- if (!(dram_para.tpr13 & 0x20000)) {
- writel(0x00000002, &mctl_ctl->pwrctl);
- writel(0x00008001, &mctl_ctl->pwrtmg);
- }
-
- writel(0x00000001, &mctl_ctl->rfshctl3);
- writel(0x00000001, &mctl_ctl->pimisc);
-
- /* deassert dram_clk_cfg reset */
- setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
-
- setbits_le32(&mctl_com->ccr, 0x80000);
-
- /* zq stuff */
- writel((dram_para.zq >> 8) & 0xff, &mctl_phy->zqcr1);
-
- writel(0x00000003, &mctl_phy->pir);
- udelay(10);
- mctl_await_completion(&mctl_phy->pgsr0, 0x09, 0x09);
-
- writel(readl(&mctl_phy->zqsr0) | 0x10000000, &mctl_phy->zqcr2);
- writel(dram_para.zq & 0xff, &mctl_phy->zqcr1);
-
- /* A23-v1.0 SDK uses 0xfdf3, A23-v2.0 SDK uses 0x5f3 */
- writel(0x000005f3, &mctl_phy->pir);
- udelay(10);
- mctl_await_completion(&mctl_phy->pgsr0, 0x03, 0x03);
-
- if (readl(&mctl_phy->dx1gsr0) & 0x1000000) {
- *bus_width = 8;
- writel(0, &mctl_phy->dx1gcr);
- writel(dram_para.zq & 0xff, &mctl_phy->zqcr1);
- writel(0x5f3, &mctl_phy->pir);
- udelay(10000);
- setbits_le32(&mctl_ctl->mstr, 0x1000);
- } else
- *bus_width = 16;
-
- if (dram_para.odt_correction) {
- mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1,
- dram_para.odt_correction);
- mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1,
- dram_para.odt_correction);
- }
-
- mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01);
-
- writel(0x08003e3f, &mctl_phy->pgcr0);
- writel(0x00000000, &mctl_ctl->rfshctl3);
-}
-
-unsigned long sunxi_dram_init(void)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- const u32 columns = 13;
- u32 bus, bus_width, offset, page_size, rows;
-
- mctl_sys_init();
- mctl_init(&bus_width);
-
- if (bus_width == 16) {
- page_size = 8;
- bus = 1;
- } else {
- page_size = 7;
- bus = 0;
- }
-
- if (!(dram_para.tpr13 & 0x80000000)) {
- /* Detect and set rows */
- writel(0x000310f4 | MCTL_CR_PAGE_SIZE(page_size),
- &mctl_com->cr);
- setbits_le32(&mctl_com->swonr, 0x0003ffff);
- for (rows = 11; rows < 16; rows++) {
- offset = 1 << (rows + columns + bus);
- if (mctl_mem_matches(offset))
- break;
- }
- clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
- MCTL_CR_ROW(rows));
- } else {
- rows = (dram_para.para1 >> 16) & 0xff;
- writel(((dram_para.para2 & 0x000000f0) << 11) |
- ((rows - 1) << 4) |
- ((dram_para.para1 & 0x0f000000) >> 22) |
- 0x31000 | MCTL_CR_PAGE_SIZE(page_size),
- &mctl_com->cr);
- setbits_le32(&mctl_com->swonr, 0x0003ffff);
- }
-
- /* Setup DRAM master priority? If this is left out things still work */
- writel(0x00000008, &mctl_com->mcr0_0);
- writel(0x0001000d, &mctl_com->mcr1_0);
- writel(0x00000004, &mctl_com->mcr0_1);
- writel(0x00000080, &mctl_com->mcr1_1);
- writel(0x00000004, &mctl_com->mcr0_2);
- writel(0x00000019, &mctl_com->mcr1_2);
- writel(0x00000004, &mctl_com->mcr0_3);
- writel(0x00000080, &mctl_com->mcr1_3);
- writel(0x00000004, &mctl_com->mcr0_4);
- writel(0x01010040, &mctl_com->mcr1_4);
- writel(0x00000004, &mctl_com->mcr0_5);
- writel(0x0001002f, &mctl_com->mcr1_5);
- writel(0x00000004, &mctl_com->mcr0_6);
- writel(0x00010020, &mctl_com->mcr1_6);
- writel(0x00000004, &mctl_com->mcr0_7);
- writel(0x00010020, &mctl_com->mcr1_7);
- writel(0x00000008, &mctl_com->mcr0_8);
- writel(0x00000001, &mctl_com->mcr1_8);
- writel(0x00000008, &mctl_com->mcr0_9);
- writel(0x00000005, &mctl_com->mcr1_9);
- writel(0x00000008, &mctl_com->mcr0_10);
- writel(0x00000003, &mctl_com->mcr1_10);
- writel(0x00000008, &mctl_com->mcr0_11);
- writel(0x00000005, &mctl_com->mcr1_11);
- writel(0x00000008, &mctl_com->mcr0_12);
- writel(0x00000003, &mctl_com->mcr1_12);
- writel(0x00000008, &mctl_com->mcr0_13);
- writel(0x00000004, &mctl_com->mcr1_13);
- writel(0x00000008, &mctl_com->mcr0_14);
- writel(0x00000002, &mctl_com->mcr1_14);
- writel(0x00000008, &mctl_com->mcr0_15);
- writel(0x00000003, &mctl_com->mcr1_15);
- writel(0x00010138, &mctl_com->bwcr);
-
- return 1 << (rows + columns + bus);
-}
+++ /dev/null
-/*
- * Sun8i a33 platform dram controller init.
- *
- * (C) Copyright 2007-2015 Allwinner Technology Co.
- * Jerry Wang <wangflord@allwinnertech.com>
- * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
- * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/dram.h>
-#include <asm/arch/prcm.h>
-
-/* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */
-#define DRAM_CLK_MUL 2
-#define DRAM_CLK_DIV 4
-#define DRAM_SIGMA_DELTA_ENABLE 1
-
-struct dram_para {
- u8 cs1;
- u8 seq;
- u8 bank;
- u8 rank;
- u8 rows;
- u8 bus_width;
- u16 page_size;
-};
-
-static void mctl_set_cr(struct dram_para *para)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
-
- writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |
- MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 |
- (para->seq ? MCTL_CR_SEQUENCE : 0) |
- ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
- MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
- MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),
- &mctl_com->cr);
-}
-
-static void auto_detect_dram_size(struct dram_para *para)
-{
- u8 orig_rank = para->rank;
- int rows, columns;
-
- /* Row detect */
- para->page_size = 512;
- para->seq = 1;
- para->rows = 16;
- para->rank = 1;
- mctl_set_cr(para);
- for (rows = 11 ; rows < 16 ; rows++) {
- if (mctl_mem_matches(1 << (rows + 9))) /* row-column */
- break;
- }
-
- /* Column (page size) detect */
- para->rows = 11;
- para->page_size = 8192;
- mctl_set_cr(para);
- for (columns = 9 ; columns < 13 ; columns++) {
- if (mctl_mem_matches(1 << columns))
- break;
- }
-
- para->seq = 0;
- para->rank = orig_rank;
- para->rows = rows;
- para->page_size = 1 << columns;
- mctl_set_cr(para);
-}
-
-static inline int ns_to_t(int nanoseconds)
-{
- const unsigned int ctrl_freq =
- CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV;
-
- return (ctrl_freq * nanoseconds + 999) / 1000;
-}
-
-static void auto_set_timing_para(struct dram_para *para)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
- u32 reg_val;
-
- u8 tccd = 2;
- u8 tfaw = ns_to_t(50);
- u8 trrd = max(ns_to_t(10), 4);
- u8 trcd = ns_to_t(15);
- u8 trc = ns_to_t(53);
- u8 txp = max(ns_to_t(8), 3);
- u8 twtr = max(ns_to_t(8), 4);
- u8 trtp = max(ns_to_t(8), 4);
- u8 twr = max(ns_to_t(15), 3);
- u8 trp = ns_to_t(15);
- u8 tras = ns_to_t(38);
-
- u16 trefi = ns_to_t(7800) / 32;
- u16 trfc = ns_to_t(350);
-
- /* Fixed timing parameters */
- u8 tmrw = 0;
- u8 tmrd = 4;
- u8 tmod = 12;
- u8 tcke = 3;
- u8 tcksrx = 5;
- u8 tcksre = 5;
- u8 tckesr = 4;
- u8 trasmax = 24;
- u8 tcl = 6; /* CL 12 */
- u8 tcwl = 4; /* CWL 8 */
- u8 t_rdata_en = 4;
- u8 wr_latency = 2;
-
- u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
- u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
- u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
- u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
-
- u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
- u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
- u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
-
- /* Set work mode register */
- mctl_set_cr(para);
- /* Set mode register */
- writel(MCTL_MR0, &mctl_ctl->mr0);
- writel(MCTL_MR1, &mctl_ctl->mr1);
- writel(MCTL_MR2, &mctl_ctl->mr2);
- writel(MCTL_MR3, &mctl_ctl->mr3);
- /* Set dram timing */
- reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0);
- writel(reg_val, &mctl_ctl->dramtmg0);
- reg_val = (txp << 16) | (trtp << 8) | (trc << 0);
- writel(reg_val, &mctl_ctl->dramtmg1);
- reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0);
- writel(reg_val, &mctl_ctl->dramtmg2);
- reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0);
- writel(reg_val, &mctl_ctl->dramtmg3);
- reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0);
- writel(reg_val, &mctl_ctl->dramtmg4);
- reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0);
- writel(reg_val, &mctl_ctl->dramtmg5);
- /* Set two rank timing and exit self-refresh timing */
- reg_val = readl(&mctl_ctl->dramtmg8);
- reg_val &= ~(0xff << 8);
- reg_val &= ~(0xff << 0);
- reg_val |= (0x33 << 8);
- reg_val |= (0x8 << 0);
- writel(reg_val, &mctl_ctl->dramtmg8);
- /* Set phy interface time */
- reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
- | (wr_latency << 0);
- /* PHY interface write latency and read latency configure */
- writel(reg_val, &mctl_ctl->pitmg0);
- /* Set phy time PTR0-2 use default */
- writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3);
- writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4);
- /* Set refresh timing */
- reg_val = (trefi << 16) | (trfc << 0);
- writel(reg_val, &mctl_ctl->rfshtmg);
-}
-
-static void mctl_set_pir(u32 val)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- writel(val, &mctl_ctl->pir);
- mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1);
-}
-
-static void mctl_data_train_cfg(struct dram_para *para)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- if (para->rank == 2)
- clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);
- else
- clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);
-}
-
-static int mctl_train_dram(struct dram_para *para)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- mctl_data_train_cfg(para);
- mctl_set_pir(0x5f3);
-
- return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0;
-}
-
-static int mctl_channel_init(struct dram_para *para)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- u32 low_data_lines_status; /* Training status of datalines 0 - 7 */
- u32 high_data_lines_status; /* Training status of datalines 8 - 15 */
-
- auto_set_timing_para(para);
-
- /* Disable dram VTC */
- clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0);
-
- /* Set ODT */
- if ((CONFIG_DRAM_CLK > 400) && IS_ENABLED(CONFIG_DRAM_ODT_EN)) {
- setbits_le32(DXnGCR0(0), 0x3 << 9);
- setbits_le32(DXnGCR0(1), 0x3 << 9);
- } else {
- clrbits_le32(DXnGCR0(0), 0x3 << 9);
- clrbits_le32(DXnGCR0(1), 0x3 << 9);
- }
-
- /* set PLL configuration */
- if (CONFIG_DRAM_CLK >= 480)
- setbits_le32(&mctl_ctl->pllgcr, 0x1 << 18);
- else
- setbits_le32(&mctl_ctl->pllgcr, 0x3 << 18);
-
- /* Auto detect dram config, set 2 rank and 16bit bus-width */
- para->cs1 = 0;
- para->rank = 2;
- para->bus_width = 16;
- mctl_set_cr(para);
-
- /* Open DQS gating */
- clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
- clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));
-
- mctl_data_train_cfg(para);
-
- /* ZQ calibration */
- writel(CONFIG_DRAM_ZQ & 0xff, &mctl_ctl->zqcr1);
- /* CA calibration */
- mctl_set_pir(0x00000003);
- /* More ZQ calibration */
- writel(readl(&mctl_ctl->zqsr0) | 0x10000000, &mctl_ctl->zqcr2);
- writel((CONFIG_DRAM_ZQ >> 8) & 0xff, &mctl_ctl->zqcr1);
-
- /* DQS gate training */
- if (mctl_train_dram(para) != 0) {
- low_data_lines_status = (readl(DXnGSR0(0)) >> 24) & 0x03;
- high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03;
-
- if (low_data_lines_status == 0x3)
- return -EIO;
-
- /* DRAM has only one rank */
- para->rank = 1;
- mctl_set_cr(para);
-
- if (low_data_lines_status == high_data_lines_status)
- goto done; /* 16 bit bus, 1 rank */
-
- if (!(low_data_lines_status & high_data_lines_status)) {
- /* Retry 16 bit bus-width with CS1 set */
- para->cs1 = 1;
- mctl_set_cr(para);
- if (mctl_train_dram(para) == 0)
- goto done;
- }
-
- /* Try 8 bit bus-width */
- writel(0x0, DXnGCR0(1)); /* Disable high DQ */
- para->cs1 = 0;
- para->bus_width = 8;
- mctl_set_cr(para);
- if (mctl_train_dram(para) != 0)
- return -EIO;
- }
-done:
- /* Check the dramc status */
- mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
-
- /* Close DQS gating */
- setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);
-
- /* Enable master access */
- writel(0xffffffff, &mctl_com->maer);
-
- return 0;
-}
-
-static void mctl_sys_init(struct dram_para *para)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
-
- clrsetbits_le32(&ccm->dram_pll_cfg, CCM_DRAMPLL_CFG_SRC_MASK,
- CCM_DRAMPLL_CFG_SRC_PLL11);
-
- clock_set_pll11(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL,
- DRAM_SIGMA_DELTA_ENABLE);
-
- clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK,
- CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) |
- CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD);
- mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
-
- setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
- setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
- setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
- setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
-
- /* Set dram master access priority */
- writel(0x0, &mctl_com->mapr);
- writel(0x0f802f01, &mctl_ctl->sched);
- writel(0x0000400f, &mctl_ctl->clken); /* normal */
-
- udelay(250);
-}
-
-unsigned long sunxi_dram_init(void)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- struct dram_para para = {
- .cs1 = 0,
- .bank = 1,
- .rank = 1,
- .rows = 15,
- .bus_width = 16,
- .page_size = 2048,
- };
-
- mctl_sys_init(¶);
-
- if (mctl_channel_init(¶) != 0)
- return 0;
-
- auto_detect_dram_size(¶);
-
- /* Enable master software clk */
- writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr);
-
- /* Set DRAM ODT MAP */
- if (para.rank == 2)
- writel(0x00000303, &mctl_ctl->odtmap);
- else
- writel(0x00000201, &mctl_ctl->odtmap);
-
- return para.page_size * (para.bus_width / 8) *
- (1 << (para.bank + para.rank + para.rows));
-}
+++ /dev/null
-/*
- * Sun8i a33 platform dram controller init.
- *
- * (C) Copyright 2007-2015 Allwinner Technology Co.
- * Jerry Wang <wangflord@allwinnertech.com>
- * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
- * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/dram.h>
-#include <asm/arch/prcm.h>
-
-#define DRAM_CLK_MUL 2
-#define DRAM_CLK_DIV 1
-
-struct dram_para {
- u8 cs1;
- u8 seq;
- u8 bank;
- u8 rank;
- u8 rows;
- u8 bus_width;
- u8 dram_type;
- u16 page_size;
-};
-
-static void mctl_set_cr(struct dram_para *para)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
-
- writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |
- MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) |
- (para->seq ? MCTL_CR_SEQUENCE : 0) |
- ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
- MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
- MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),
- &mctl_com->cr);
-}
-
-static void auto_detect_dram_size(struct dram_para *para)
-{
- u8 orig_rank = para->rank;
- int rows, columns;
-
- /* Row detect */
- para->page_size = 512;
- para->seq = 1;
- para->rows = 16;
- para->rank = 1;
- mctl_set_cr(para);
- for (rows = 11 ; rows < 16 ; rows++) {
- if (mctl_mem_matches(1 << (rows + 9))) /* row-column */
- break;
- }
-
- /* Column (page size) detect */
- para->rows = 11;
- para->page_size = 8192;
- mctl_set_cr(para);
- for (columns = 9 ; columns < 13 ; columns++) {
- if (mctl_mem_matches(1 << columns))
- break;
- }
-
- para->seq = 0;
- para->rank = orig_rank;
- para->rows = rows;
- para->page_size = 1 << columns;
- mctl_set_cr(para);
-}
-
-static inline int ns_to_t(int nanoseconds)
-{
- const unsigned int ctrl_freq =
- CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV;
-
- return (ctrl_freq * nanoseconds + 999) / 1000;
-}
-
-static void auto_set_timing_para(struct dram_para *para)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- u32 reg_val;
-
- u8 tccd = 2;
- u8 tfaw = ns_to_t(50);
- u8 trrd = max(ns_to_t(10), 4);
- u8 trcd = ns_to_t(15);
- u8 trc = ns_to_t(53);
- u8 txp = max(ns_to_t(8), 3);
- u8 twtr = max(ns_to_t(8), 4);
- u8 trtp = max(ns_to_t(8), 4);
- u8 twr = max(ns_to_t(15), 3);
- u8 trp = ns_to_t(15);
- u8 tras = ns_to_t(38);
-
- u16 trefi = ns_to_t(7800) / 32;
- u16 trfc = ns_to_t(350);
-
- /* Fixed timing parameters */
- u8 tmrw = 0;
- u8 tmrd = 4;
- u8 tmod = 12;
- u8 tcke = 3;
- u8 tcksrx = 5;
- u8 tcksre = 5;
- u8 tckesr = 4;
- u8 trasmax = 24;
- u8 tcl = 6; /* CL 12 */
- u8 tcwl = 4; /* CWL 8 */
- u8 t_rdata_en = 4;
- u8 wr_latency = 2;
-
- u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
- u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
- u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
- u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
-
- u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
- u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
- u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
-
- /* Set work mode register */
- mctl_set_cr(para);
- /* Set mode register */
- if (para->dram_type == DRAM_TYPE_DDR3) {
- writel(MCTL_MR0, &mctl_ctl->mr0);
- writel(MCTL_MR1, &mctl_ctl->mr1);
- writel(MCTL_MR2, &mctl_ctl->mr2);
- writel(MCTL_MR3, &mctl_ctl->mr3);
- } else if (para->dram_type == DRAM_TYPE_LPDDR3) {
- writel(MCTL_LPDDR3_MR0, &mctl_ctl->mr0);
- writel(MCTL_LPDDR3_MR1, &mctl_ctl->mr1);
- writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr2);
- writel(MCTL_LPDDR3_MR3, &mctl_ctl->mr3);
-
- /* timing parameters for LPDDR3 */
- tfaw = max(ns_to_t(50), 4);
- trrd = max(ns_to_t(10), 2);
- trcd = max(ns_to_t(24), 2);
- trc = ns_to_t(70);
- txp = max(ns_to_t(8), 2);
- twtr = max(ns_to_t(8), 2);
- trtp = max(ns_to_t(8), 2);
- trp = max(ns_to_t(27), 2);
- tras = ns_to_t(42);
- trefi = ns_to_t(3900) / 32;
- trfc = ns_to_t(210);
- tmrw = 5;
- tmrd = 5;
- tckesr = 5;
- tcwl = 3; /* CWL 8 */
- t_rdata_en = 5;
- tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
- tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */
- tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 200us */
- tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
- twtp = tcwl + 4 + twr + 1; /* CWL + BL/2 + tWR */
- twr2rd = tcwl + 4 + 1 + twtr; /* WL + BL / 2 + tWTR */
- trd2wr = tcl + 4 + 5 - tcwl + 1; /* RL + BL / 2 + 2 - WL */
- }
- /* Set dram timing */
- reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0);
- writel(reg_val, &mctl_ctl->dramtmg0);
- reg_val = (txp << 16) | (trtp << 8) | (trc << 0);
- writel(reg_val, &mctl_ctl->dramtmg1);
- reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0);
- writel(reg_val, &mctl_ctl->dramtmg2);
- reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0);
- writel(reg_val, &mctl_ctl->dramtmg3);
- reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0);
- writel(reg_val, &mctl_ctl->dramtmg4);
- reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0);
- writel(reg_val, &mctl_ctl->dramtmg5);
- /* Set two rank timing and exit self-refresh timing */
- reg_val = readl(&mctl_ctl->dramtmg8);
- reg_val &= ~(0xff << 8);
- reg_val &= ~(0xff << 0);
- reg_val |= (0x33 << 8);
- reg_val |= (0x8 << 0);
- writel(reg_val, &mctl_ctl->dramtmg8);
- /* Set phy interface time */
- reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
- | (wr_latency << 0);
- /* PHY interface write latency and read latency configure */
- writel(reg_val, &mctl_ctl->pitmg0);
- /* Set phy time PTR0-2 use default */
- writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3);
- writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4);
- /* Set refresh timing */
- reg_val = (trefi << 16) | (trfc << 0);
- writel(reg_val, &mctl_ctl->rfshtmg);
-}
-
-static void mctl_set_pir(u32 val)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- writel(val, &mctl_ctl->pir);
- mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1);
-}
-
-static void mctl_data_train_cfg(struct dram_para *para)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- if (para->rank == 2)
- clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);
- else
- clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);
-}
-
-static int mctl_train_dram(struct dram_para *para)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- mctl_data_train_cfg(para);
- mctl_set_pir(0x5f3);
-
- return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0;
-}
-
-static void set_master_priority(void)
-{
- writel(0x00a0000d, MCTL_MASTER_CFG0(0));
- writel(0x00500064, MCTL_MASTER_CFG1(0));
- writel(0x07000009, MCTL_MASTER_CFG0(1));
- writel(0x00000600, MCTL_MASTER_CFG1(1));
- writel(0x01000009, MCTL_MASTER_CFG0(3));
- writel(0x00000064, MCTL_MASTER_CFG1(3));
- writel(0x08000009, MCTL_MASTER_CFG0(4));
- writel(0x00000640, MCTL_MASTER_CFG1(4));
- writel(0x20000308, MCTL_MASTER_CFG0(8));
- writel(0x00001000, MCTL_MASTER_CFG1(8));
- writel(0x02800009, MCTL_MASTER_CFG0(9));
- writel(0x00000100, MCTL_MASTER_CFG1(9));
- writel(0x01800009, MCTL_MASTER_CFG0(5));
- writel(0x00000100, MCTL_MASTER_CFG1(5));
- writel(0x01800009, MCTL_MASTER_CFG0(7));
- writel(0x00000100, MCTL_MASTER_CFG1(7));
- writel(0x00640009, MCTL_MASTER_CFG0(6));
- writel(0x00000032, MCTL_MASTER_CFG1(6));
- writel(0x0100000d, MCTL_MASTER_CFG0(2));
- writel(0x00500080, MCTL_MASTER_CFG1(2));
-}
-
-static int mctl_channel_init(struct dram_para *para)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- u32 low_data_lines_status; /* Training status of datalines 0 - 7 */
- u32 high_data_lines_status; /* Training status of datalines 8 - 15 */
- u32 i, rval;
-
- auto_set_timing_para(para);
-
- /* Set dram master access priority */
- writel(0x000101a0, &mctl_com->bwcr);
- /* set cpu high priority */
- writel(0x1, &mctl_com->mapr);
- set_master_priority();
- udelay(250);
-
- /* Disable dram VTC */
- clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0 | 0x1 << 30);
- clrsetbits_le32(&mctl_ctl->pgcr1, 0x1 << 24, 0x1 << 26);
-
- writel(0x94be6fa3, MCTL_PROTECT);
- udelay(100);
- clrsetbits_le32(MX_UPD2, 0xfff << 16, 0x50 << 26);
- writel(0x0, MCTL_PROTECT);
- udelay(100);
-
-
- /* Set ODT */
- if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
- rval = 0x0;
- else
- rval = 0x2;
-
- for (i = 0 ; i < 11 ; i++) {
- clrsetbits_le32(DATX0IOCR(i), (0x3 << 24) | (0x3 << 16),
- rval << 24);
- clrsetbits_le32(DATX1IOCR(i), (0x3 << 24) | (0x3 << 16),
- rval << 24);
- clrsetbits_le32(DATX2IOCR(i), (0x3 << 24) | (0x3 << 16),
- rval << 24);
- clrsetbits_le32(DATX3IOCR(i), (0x3 << 24) | (0x3 << 16),
- rval << 24);
- }
-
- for (i = 0; i < 31; i++)
- clrsetbits_le32(CAIOCR(i), 0x3 << 26 | 0x3 << 16, 0x2 << 26);
-
- /* set PLL configuration */
- if (CONFIG_DRAM_CLK >= 480)
- setbits_le32(&mctl_ctl->pllgcr, 0x1 << 19);
- else
- setbits_le32(&mctl_ctl->pllgcr, 0x3 << 19);
-
- /* Auto detect dram config, set 2 rank and 16bit bus-width */
- para->cs1 = 0;
- para->rank = 2;
- para->bus_width = 16;
- mctl_set_cr(para);
-
- /* Open DQS gating */
- clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
- clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));
-
- if (para->dram_type == DRAM_TYPE_LPDDR3)
- clrsetbits_le32(&mctl_ctl->dxccr, (0x1 << 27) | (0x3<<6) ,
- 0x1 << 31);
- if (readl(&mctl_com->cr) & 0x1)
- writel(0x00000303, &mctl_ctl->odtmap);
- else
- writel(0x00000201, &mctl_ctl->odtmap);
-
- mctl_data_train_cfg(para);
- /* ZQ calibration */
- clrsetbits_le32(ZQnPR(0), 0x000000ff, CONFIG_DRAM_ZQ & 0xff);
- clrsetbits_le32(ZQnPR(1), 0x000000ff, (CONFIG_DRAM_ZQ >> 8) & 0xff);
- /* CA calibration */
-
- if (para->dram_type == DRAM_TYPE_DDR3)
- mctl_set_pir(0x0201f3 | 0x1<<10);
- else
- mctl_set_pir(0x020173 | 0x1<<10);
-
- /* DQS gate training */
- if (mctl_train_dram(para) != 0) {
- low_data_lines_status = (readl(DXnGSR0(0)) >> 24) & 0x03;
- high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03;
-
- if (low_data_lines_status == 0x3)
- return -EIO;
-
- /* DRAM has only one rank */
- para->rank = 1;
- mctl_set_cr(para);
-
- if (low_data_lines_status == high_data_lines_status)
- goto done; /* 16 bit bus, 1 rank */
-
- if (!(low_data_lines_status & high_data_lines_status)) {
- /* Retry 16 bit bus-width with CS1 set */
- para->cs1 = 1;
- mctl_set_cr(para);
- if (mctl_train_dram(para) == 0)
- goto done;
- }
-
- /* Try 8 bit bus-width */
- writel(0x0, DXnGCR0(1)); /* Disable high DQ */
- para->cs1 = 0;
- para->bus_width = 8;
- mctl_set_cr(para);
- if (mctl_train_dram(para) != 0)
- return -EIO;
- }
-done:
- /* Check the dramc status */
- mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
-
- /* Close DQS gating */
- setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);
-
- /* set PGCR3,CKE polarity */
- writel(0x00aa0060, &mctl_ctl->pgcr3);
- /* Enable master access */
- writel(0xffffffff, &mctl_com->maer);
-
- return 0;
-}
-
-static void mctl_sys_init(struct dram_para *para)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- clrbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
- clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
- clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
- clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
- clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
- udelay(1000);
- clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31);
-
- clock_set_pll5(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL);
-
- clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK,
- CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) |
- CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD);
- mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
-
- setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
- setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
- setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
- setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
-
- para->rank = 2;
- para->bus_width = 16;
- mctl_set_cr(para);
-
- /* Set dram master access priority */
- writel(0x0000e00f, &mctl_ctl->clken); /* normal */
-
- udelay(250);
-}
-
-unsigned long sunxi_dram_init(void)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- struct dram_para para = {
- .cs1 = 0,
- .bank = 1,
- .rank = 1,
- .rows = 15,
- .bus_width = 16,
- .page_size = 2048,
- };
-
-#if defined(CONFIG_MACH_SUN8I_A83T)
-#if (CONFIG_DRAM_TYPE == 3) || (CONFIG_DRAM_TYPE == 7)
- para.dram_type = CONFIG_DRAM_TYPE;
-#else
-#error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3)
-#endif
-#endif
- setbits_le32(SUNXI_PRCM_BASE + 0x1e0, 0x1 << 8);
-
- writel(0, (SUNXI_PRCM_BASE + 0x1e8));
- udelay(10);
-
- mctl_sys_init(¶);
-
- if (mctl_channel_init(¶) != 0)
- return 0;
-
- auto_detect_dram_size(¶);
-
- /* Enable master software clk */
- writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr);
-
- /* Set DRAM ODT MAP */
- if (para.rank == 2)
- writel(0x00000303, &mctl_ctl->odtmap);
- else
- writel(0x00000201, &mctl_ctl->odtmap);
-
- return para.page_size * (para.bus_width / 8) *
- (1 << (para.bank + para.rank + para.rows));
-}
+++ /dev/null
-/*
- * sun8i H3 platform dram controller init
- *
- * (C) Copyright 2007-2015 Allwinner Technology Co.
- * Jerry Wang <wangflord@allwinnertech.com>
- * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
- * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
- * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/dram.h>
-#include <linux/kconfig.h>
-
-struct dram_para {
- u32 read_delays;
- u32 write_delays;
- u16 page_size;
- u8 bus_width;
- u8 dual_rank;
- u8 row_bits;
-};
-
-static inline int ns_to_t(int nanoseconds)
-{
- const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
-
- return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
-}
-
-static u32 bin_to_mgray(int val)
-{
- static const u8 lookup_table[32] = {
- 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
- 0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09,
- 0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d,
- 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11,
- };
-
- return lookup_table[clamp(val, 0, 31)];
-}
-
-static int mgray_to_bin(u32 val)
-{
- static const u8 lookup_table[32] = {
- 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
- 0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b,
- 0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b,
- 0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15,
- };
-
- return lookup_table[val & 0x1f];
-}
-
-static void mctl_phy_init(u32 val)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- writel(val | PIR_INIT, &mctl_ctl->pir);
- mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1);
-}
-
-static void mctl_dq_delay(u32 read, u32 write)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
- int i, j;
- u32 val;
-
- for (i = 0; i < 4; i++) {
- val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) |
- DATX_IOCR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2);
-
- for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++)
- writel(val, &mctl_ctl->datx[i].iocr[j]);
- }
-
- clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
-
- for (i = 0; i < 4; i++) {
- val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) |
- DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf);
-
- writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQS]);
- writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN]);
- }
-
- setbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
-
- udelay(1);
-}
-
-static void mctl_set_master_priority(void)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
-
- /* enable bandwidth limit windows and set windows size 1us */
- writel(0x00010190, &mctl_com->bwcr);
-
- /* set cpu high priority */
- writel(0x00000001, &mctl_com->mapr);
-
- writel(0x0200000d, &mctl_com->mcr[0][0]);
- writel(0x00800100, &mctl_com->mcr[0][1]);
- writel(0x06000009, &mctl_com->mcr[1][0]);
- writel(0x01000400, &mctl_com->mcr[1][1]);
- writel(0x0200000d, &mctl_com->mcr[2][0]);
- writel(0x00600100, &mctl_com->mcr[2][1]);
- writel(0x0100000d, &mctl_com->mcr[3][0]);
- writel(0x00200080, &mctl_com->mcr[3][1]);
- writel(0x07000009, &mctl_com->mcr[4][0]);
- writel(0x01000640, &mctl_com->mcr[4][1]);
- writel(0x0100000d, &mctl_com->mcr[5][0]);
- writel(0x00200080, &mctl_com->mcr[5][1]);
- writel(0x01000009, &mctl_com->mcr[6][0]);
- writel(0x00400080, &mctl_com->mcr[6][1]);
- writel(0x0100000d, &mctl_com->mcr[7][0]);
- writel(0x00400080, &mctl_com->mcr[7][1]);
- writel(0x0100000d, &mctl_com->mcr[8][0]);
- writel(0x00400080, &mctl_com->mcr[8][1]);
- writel(0x04000009, &mctl_com->mcr[9][0]);
- writel(0x00400100, &mctl_com->mcr[9][1]);
- writel(0x2000030d, &mctl_com->mcr[10][0]);
- writel(0x04001800, &mctl_com->mcr[10][1]);
- writel(0x04000009, &mctl_com->mcr[11][0]);
- writel(0x00400120, &mctl_com->mcr[11][1]);
-}
-
-static void mctl_set_timing_params(struct dram_para *para)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- u8 tccd = 2;
- u8 tfaw = ns_to_t(50);
- u8 trrd = max(ns_to_t(10), 4);
- u8 trcd = ns_to_t(15);
- u8 trc = ns_to_t(53);
- u8 txp = max(ns_to_t(8), 3);
- u8 twtr = max(ns_to_t(8), 4);
- u8 trtp = max(ns_to_t(8), 4);
- u8 twr = max(ns_to_t(15), 3);
- u8 trp = ns_to_t(15);
- u8 tras = ns_to_t(38);
- u16 trefi = ns_to_t(7800) / 32;
- u16 trfc = ns_to_t(350);
-
- u8 tmrw = 0;
- u8 tmrd = 4;
- u8 tmod = 12;
- u8 tcke = 3;
- u8 tcksrx = 5;
- u8 tcksre = 5;
- u8 tckesr = 4;
- u8 trasmax = 24;
-
- u8 tcl = 6; /* CL 12 */
- u8 tcwl = 4; /* CWL 8 */
- u8 t_rdata_en = 4;
- u8 wr_latency = 2;
-
- u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
- u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
- u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
- u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
-
- u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
- u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
- u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
-
- /* set mode register */
- writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */
- writel(0x40, &mctl_ctl->mr[1]);
- writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
- writel(0x0, &mctl_ctl->mr[3]);
-
- /* set DRAM timing */
- writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
- DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
- &mctl_ctl->dramtmg[0]);
- writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
- &mctl_ctl->dramtmg[1]);
- writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
- DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
- &mctl_ctl->dramtmg[2]);
- writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
- &mctl_ctl->dramtmg[3]);
- writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
- DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
- writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
- DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
- &mctl_ctl->dramtmg[5]);
-
- /* set two rank timing */
- clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
- (0x66 << 8) | (0x10 << 0));
-
- /* set PHY interface timing, write latency and read latency configure */
- writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
- (wr_latency << 0), &mctl_ctl->pitmg[0]);
-
- /* set PHY timing, PTR0-2 use default */
- writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
- writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
-
- /* set refresh timing */
- writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
-}
-
-static void mctl_zq_calibration(struct dram_para *para)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- int i;
- u16 zq_val[6];
- u8 val;
-
- writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
-
- for (i = 0; i < 6; i++) {
- u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
-
- writel((zq << 20) | (zq << 16) | (zq << 12) |
- (zq << 8) | (zq << 4) | (zq << 0),
- &mctl_ctl->zqcr);
-
- writel(PIR_CLRSR, &mctl_ctl->pir);
- mctl_phy_init(PIR_ZCAL);
-
- zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
- writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
-
- writel(PIR_CLRSR, &mctl_ctl->pir);
- mctl_phy_init(PIR_ZCAL);
-
- val = readl(&mctl_ctl->zqdr[0]) >> 24;
- zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
- }
-
- writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
- writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
- writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
-}
-
-static void mctl_set_cr(struct dram_para *para)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
-
- writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED |
- MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) |
- (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
- MCTL_CR_PAGE_SIZE(para->page_size) |
- MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
-}
-
-static void mctl_sys_init(struct dram_para *para)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
- clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
- clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
- clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
- clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
- udelay(10);
-
- clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
- udelay(1000);
-
- clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
- clrsetbits_le32(&ccm->dram_clk_cfg,
- CCM_DRAMCLK_CFG_DIV_MASK | CCM_DRAMCLK_CFG_SRC_MASK,
- CCM_DRAMCLK_CFG_DIV(1) | CCM_DRAMCLK_CFG_SRC_PLL5 |
- CCM_DRAMCLK_CFG_UPD);
- mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
-
- setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
- setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
- setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
- setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
-
- setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
- udelay(10);
-
- writel(0xc00e, &mctl_ctl->clken);
- udelay(500);
-}
-
-static int mctl_channel_init(struct dram_para *para)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- unsigned int i;
-
- mctl_set_cr(para);
- mctl_set_timing_params(para);
- mctl_set_master_priority();
-
- /* setting VTC, default disable all VT */
- clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f);
- clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
-
- /* increase DFI_PHY_UPD clock */
- writel(PROTECT_MAGIC, &mctl_com->protect);
- udelay(100);
- clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16);
- writel(0x0, &mctl_com->protect);
- udelay(100);
-
- /* set dramc odt */
- for (i = 0; i < 4; i++)
- clrsetbits_le32(&mctl_ctl->datx[i].gcr, (0x3 << 4) |
- (0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
- (0x3 << 14),
- IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2);
-
- /* AC PDR should always ON */
- setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);
-
- /* set DQS auto gating PD mode */
- setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);
-
- /* dx ddr_clk & hdr_clk dynamic mode */
- clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
-
- /* dphy & aphy phase select 270 degree */
- clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
- (0x1 << 10) | (0x2 << 8));
-
- /* set half DQ */
- if (para->bus_width != 32) {
- writel(0x0, &mctl_ctl->datx[2].gcr);
- writel(0x0, &mctl_ctl->datx[3].gcr);
- }
-
- /* data training configuration */
- clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24,
- (para->dual_rank ? 0x3 : 0x1) << 24);
-
-
- if (para->read_delays || para->write_delays) {
- mctl_dq_delay(para->read_delays, para->write_delays);
- udelay(50);
- }
-
- mctl_zq_calibration(para);
-
- mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | PIR_DRAMRST |
- PIR_DRAMINIT | PIR_QSGATE);
-
- /* detect ranks and bus width */
- if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) {
- /* only one rank */
- if (((readl(&mctl_ctl->datx[0].gsr[0]) >> 24) & 0x2) ||
- ((readl(&mctl_ctl->datx[1].gsr[0]) >> 24) & 0x2)) {
- clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
- para->dual_rank = 0;
- }
-
- /* only half DQ width */
- if (((readl(&mctl_ctl->datx[2].gsr[0]) >> 24) & 0x1) ||
- ((readl(&mctl_ctl->datx[3].gsr[0]) >> 24) & 0x1)) {
- writel(0x0, &mctl_ctl->datx[2].gcr);
- writel(0x0, &mctl_ctl->datx[3].gcr);
- para->bus_width = 16;
- }
-
- mctl_set_cr(para);
- udelay(20);
-
- /* re-train */
- mctl_phy_init(PIR_QSGATE);
- if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20))
- return 1;
- }
-
- /* check the dramc status */
- mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
-
- /* liuke added for refresh debug */
- setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
- udelay(10);
- clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
- udelay(10);
-
- /* set PGCR3, CKE polarity */
- writel(0x00aa0060, &mctl_ctl->pgcr[3]);
-
- /* power down zq calibration module for power save */
- setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN);
-
- /* enable master access */
- writel(0xffffffff, &mctl_com->maer);
-
- return 0;
-}
-
-static void mctl_auto_detect_dram_size(struct dram_para *para)
-{
- /* detect row address bits */
- para->page_size = 512;
- para->row_bits = 16;
- mctl_set_cr(para);
-
- for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
- if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size))
- break;
-
- /* detect page size */
- para->page_size = 8192;
- mctl_set_cr(para);
-
- for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2)
- if (mctl_mem_matches(para->page_size))
- break;
-}
-
-unsigned long sunxi_dram_init(void)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- struct dram_para para = {
- .read_delays = 0x00007979, /* dram_tpr12 */
- .write_delays = 0x6aaa0000, /* dram_tpr11 */
- .dual_rank = 0,
- .bus_width = 32,
- .row_bits = 15,
- .page_size = 4096,
- };
-
- mctl_sys_init(¶);
- if (mctl_channel_init(¶))
- return 0;
-
- if (para.dual_rank)
- writel(0x00000303, &mctl_ctl->odtmap);
- else
- writel(0x00000201, &mctl_ctl->odtmap);
- udelay(1);
-
- /* odt delay */
- writel(0x0c000400, &mctl_ctl->odtcfg);
-
- /* clear credit value */
- setbits_le32(&mctl_com->cccr, 1 << 31);
- udelay(10);
-
- mctl_auto_detect_dram_size(¶);
- mctl_set_cr(¶);
-
- return (1 << (para.row_bits + 3)) * para.page_size *
- (para.dual_rank ? 2 : 1);
-}
+++ /dev/null
-/*
- * Sunxi A31 Power Management Unit
- *
- * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
- * http://linux-sunxi.org
- *
- * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
- *
- * (C) Copyright 2006-2013
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Berg Xing <bergxing@allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/p2wi.h>
-#include <asm/arch/prcm.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-
-void p2wi_init(void)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
-
- /* Enable p2wi and PIO clk, and de-assert their resets */
- prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
-
- sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
- sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
-
- /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
- writel(P2WI_CTRL_RESET, &p2wi->ctrl);
- sdelay(0x100);
- writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
- &p2wi->cc);
-}
-
-int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
- unsigned long tmo = timer_get_us() + 1000000;
-
- writel(P2WI_PM_DEV_ADDR(slave_addr) |
- P2WI_PM_CTRL_ADDR(ctrl_reg) |
- P2WI_PM_INIT_DATA(init_data) |
- P2WI_PM_INIT_SEND,
- &p2wi->pm);
-
- while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) {
- if (timer_get_us() > tmo)
- return -ETIME;
- }
-
- return 0;
-}
-
-static int p2wi_await_trans(void)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
- unsigned long tmo = timer_get_us() + 1000000;
- int ret;
- u8 reg;
-
- while (1) {
- reg = readl(&p2wi->status);
- if (reg & P2WI_STAT_TRANS_ERR) {
- ret = -EIO;
- break;
- }
- if (reg & P2WI_STAT_TRANS_DONE) {
- ret = 0;
- break;
- }
- if (timer_get_us() > tmo) {
- ret = -ETIME;
- break;
- }
- }
- writel(reg, &p2wi->status); /* Clear status bits */
- return ret;
-}
-
-int p2wi_read(const u8 addr, u8 *data)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
- int ret;
-
- writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
- writel(P2WI_DATA_NUM_BYTES(1) |
- P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
- writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
- writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
-
- ret = p2wi_await_trans();
-
- *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
- return ret;
-}
-
-int p2wi_write(const u8 addr, u8 data)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
-
- writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
- writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
- writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
- writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
- writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
-
- return p2wi_await_trans();
-}
+++ /dev/null
-/*
- * (C) Copyright 2007-2011
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/gpio.h>
-
-void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
-{
- u32 index = GPIO_CFG_INDEX(bank_offset);
- u32 offset = GPIO_CFG_OFFSET(bank_offset);
-
- clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
-}
-
-void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
-{
- u32 bank = GPIO_BANK(pin);
- struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
-
- sunxi_gpio_set_cfgbank(pio, pin, val);
-}
-
-int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
-{
- u32 index = GPIO_CFG_INDEX(bank_offset);
- u32 offset = GPIO_CFG_OFFSET(bank_offset);
- u32 cfg;
-
- cfg = readl(&pio->cfg[0] + index);
- cfg >>= offset;
-
- return cfg & 0xf;
-}
-
-int sunxi_gpio_get_cfgpin(u32 pin)
-{
- u32 bank = GPIO_BANK(pin);
- struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
-
- return sunxi_gpio_get_cfgbank(pio, pin);
-}
-
-int sunxi_gpio_set_drv(u32 pin, u32 val)
-{
- u32 bank = GPIO_BANK(pin);
- u32 index = GPIO_DRV_INDEX(pin);
- u32 offset = GPIO_DRV_OFFSET(pin);
- struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
-
- clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset);
-
- return 0;
-}
-
-int sunxi_gpio_set_pull(u32 pin, u32 val)
-{
- u32 bank = GPIO_BANK(pin);
- u32 index = GPIO_PULL_INDEX(pin);
- u32 offset = GPIO_PULL_OFFSET(pin);
- struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
-
- clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset);
-
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
- *
- * Sunxi PMIC bus access helpers
- *
- * The axp152 & axp209 use an i2c bus, the axp221 uses the p2wi bus and the
- * axp223 uses the rsb bus, these functions abstract this.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/p2wi.h>
-#include <asm/arch/rsb.h>
-#include <i2c.h>
-#include <asm/arch/pmic_bus.h>
-
-#define AXP152_I2C_ADDR 0x30
-
-#define AXP209_I2C_ADDR 0x34
-
-#define AXP221_CHIP_ADDR 0x68
-#define AXP221_CTRL_ADDR 0x3e
-#define AXP221_INIT_DATA 0x3e
-
-/* AXP818 device and runtime addresses are same as AXP223 */
-#define AXP223_DEVICE_ADDR 0x3a3
-#define AXP223_RUNTIME_ADDR 0x2d
-
-int pmic_bus_init(void)
-{
- /* This cannot be 0 because it is used in SPL before BSS is ready */
- static int needs_init = 1;
- __maybe_unused int ret;
-
- if (!needs_init)
- return 0;
-
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
-# ifdef CONFIG_MACH_SUN6I
- p2wi_init();
- ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
- AXP221_INIT_DATA);
-# else
- ret = rsb_init();
- if (ret)
- return ret;
-
- ret = rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR);
-# endif
- if (ret)
- return ret;
-#endif
-
- needs_init = 0;
- return 0;
-}
-
-int pmic_bus_read(u8 reg, u8 *data)
-{
-#ifdef CONFIG_AXP152_POWER
- return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP209_POWER
- return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
-# ifdef CONFIG_MACH_SUN6I
- return p2wi_read(reg, data);
-# else
- return rsb_read(AXP223_RUNTIME_ADDR, reg, data);
-# endif
-#endif
-}
-
-int pmic_bus_write(u8 reg, u8 data)
-{
-#ifdef CONFIG_AXP152_POWER
- return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP209_POWER
- return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
-# ifdef CONFIG_MACH_SUN6I
- return p2wi_write(reg, data);
-# else
- return rsb_write(AXP223_RUNTIME_ADDR, reg, data);
-# endif
-#endif
-}
-
-int pmic_bus_setbits(u8 reg, u8 bits)
-{
- int ret;
- u8 val;
-
- ret = pmic_bus_read(reg, &val);
- if (ret)
- return ret;
-
- val |= bits;
- return pmic_bus_write(reg, val);
-}
-
-int pmic_bus_clrbits(u8 reg, u8 bits)
-{
- int ret;
- u8 val;
-
- ret = pmic_bus_read(reg, &val);
- if (ret)
- return ret;
-
- val &= ~bits;
- return pmic_bus_write(reg, val);
-}
+++ /dev/null
-/*
- * Sunxi A31 Power Management Unit
- *
- * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
- * http://linux-sunxi.org
- *
- * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
- *
- * (C) Copyright 2006-2013
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Berg Xing <bergxing@allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/prcm.h>
-#include <asm/arch/sys_proto.h>
-
-/* APB0 clock gate and reset bit offsets are the same. */
-void prcm_apb0_enable(u32 flags)
-{
- struct sunxi_prcm_reg *prcm =
- (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
-
- /* open the clock for module */
- setbits_le32(&prcm->apb0_gate, flags);
-
- /* deassert reset for module */
- setbits_le32(&prcm->apb0_reset, flags);
-}
-
-void prcm_apb0_disable(u32 flags)
-{
- struct sunxi_prcm_reg *prcm =
- (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
-
- /* assert reset for module */
- clrbits_le32(&prcm->apb0_reset, flags);
-
- /* close the clock for module */
- clrbits_le32(&prcm->apb0_gate, flags);
-}
+++ /dev/null
-/*
- * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
- *
- * Based on allwinner u-boot sources rsb code which is:
- * (C) Copyright 2007-2013
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * lixiang <lixiang@allwinnertech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/prcm.h>
-#include <asm/arch/rsb.h>
-
-static int rsb_set_device_mode(void);
-
-static void rsb_cfg_io(void)
-{
-#ifdef CONFIG_MACH_SUN8I
- sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
- sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
- sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
- sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
- sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
- sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
-#elif defined CONFIG_MACH_SUN9I
- sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
- sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
- sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
- sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
- sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
- sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
-#else
-#error unsupported MACH_SUNXI
-#endif
-}
-
-static void rsb_set_clk(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
- u32 div = 0;
- u32 cd_odly = 0;
-
- /* Source is Hosc24M, set RSB clk to 3Mhz */
- div = 24000000 / 3000000 / 2 - 1;
- cd_odly = div >> 1;
- if (!cd_odly)
- cd_odly = 1;
-
- writel((cd_odly << 8) | div, &rsb->ccr);
-}
-
-int rsb_init(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
-
- /* Enable RSB and PIO clk, and de-assert their resets */
- prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
-
- /* Setup external pins */
- rsb_cfg_io();
-
- writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
- rsb_set_clk();
-
- return rsb_set_device_mode();
-}
-
-static int rsb_await_trans(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
- unsigned long tmo = timer_get_us() + 1000000;
- u32 stat;
- int ret;
-
- while (1) {
- stat = readl(&rsb->stat);
- if (stat & RSB_STAT_LBSY_INT) {
- ret = -EBUSY;
- break;
- }
- if (stat & RSB_STAT_TERR_INT) {
- ret = -EIO;
- break;
- }
- if (stat & RSB_STAT_TOVER_INT) {
- ret = 0;
- break;
- }
- if (timer_get_us() > tmo) {
- ret = -ETIME;
- break;
- }
- }
- writel(stat, &rsb->stat); /* Clear status bits */
-
- return ret;
-}
-
-static int rsb_set_device_mode(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
- unsigned long tmo = timer_get_us() + 1000000;
-
- writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
- &rsb->dmcr);
-
- while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
- if (timer_get_us() > tmo)
- return -ETIME;
- }
-
- return rsb_await_trans();
-}
-
-static int rsb_do_trans(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
-
- setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS);
- return rsb_await_trans();
-}
-
-int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
-
- writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) |
- RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr);
- writel(RSB_CMD_SET_RTSADDR, &rsb->cmd);
-
- return rsb_do_trans();
-}
-
-int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
-
- writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
- writel(reg_addr, &rsb->addr);
- writel(data, &rsb->data);
- writel(RSB_CMD_BYTE_WRITE, &rsb->cmd);
-
- return rsb_do_trans();
-}
-
-int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
- int ret;
-
- writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
- writel(reg_addr, &rsb->addr);
- writel(RSB_CMD_BYTE_READ, &rsb->cmd);
-
- ret = rsb_do_trans();
- if (ret)
- return ret;
-
- *data = readl(&rsb->data) & 0xff;
-
- return 0;
-}
+++ /dev/null
-/*
- * Sunxi usb-phy code
- *
- * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
- * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
- *
- * Based on code from
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/usb_phy.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <errno.h>
-
-#define SUNXI_USB_PMU_IRQ_ENABLE 0x800
-#ifdef CONFIG_MACH_SUN8I_A33
-#define SUNXI_USB_CSR 0x410
-#else
-#define SUNXI_USB_CSR 0x404
-#endif
-#define SUNXI_USB_PASSBY_EN 1
-
-#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
-#define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9)
-#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8)
-#define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0)
-
-#define REG_PHY_UNK_H3 0x420
-#define REG_PMU_UNK_H3 0x810
-
-static struct sunxi_usb_phy {
- int usb_rst_mask;
- int gpio_vbus;
- int gpio_vbus_det;
- int gpio_id_det;
- int id;
- int init_count;
- int power_on_count;
- int base;
-} sunxi_usb_phy[] = {
- {
- .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
- .id = 0,
- .base = SUNXI_USB0_BASE,
- },
- {
- .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
- .id = 1,
- .base = SUNXI_USB1_BASE,
- },
-#if CONFIG_SUNXI_USB_PHYS >= 3
- {
- .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
- .id = 2,
- .base = SUNXI_USB2_BASE,
- },
-#endif
-#if CONFIG_SUNXI_USB_PHYS >= 4
- {
- .usb_rst_mask = CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK,
- .id = 3,
- .base = SUNXI_USB3_BASE,
- }
-#endif
-};
-
-static int get_vbus_gpio(int index)
-{
- switch (index) {
- case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
- case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
- case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
- }
- return -EINVAL;
-}
-
-static int get_vbus_detect_gpio(int index)
-{
- switch (index) {
- case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET);
- }
- return -EINVAL;
-}
-
-static int get_id_detect_gpio(int index)
-{
- switch (index) {
- case 0: return sunxi_name_to_gpio(CONFIG_USB0_ID_DET);
- }
- return -EINVAL;
-}
-
-static void usb_phy_write(struct sunxi_usb_phy *phy, int addr,
- int data, int len)
-{
- int j = 0, usbc_bit = 0;
- void *dest = (void *)SUNXI_USB0_BASE + SUNXI_USB_CSR;
-
-#ifdef CONFIG_MACH_SUN8I_A33
- /* CSR needs to be explicitly initialized to 0 on A33 */
- writel(0, dest);
-#endif
-
- usbc_bit = 1 << (phy->id * 2);
- for (j = 0; j < len; j++) {
- /* set the bit address to be written */
- clrbits_le32(dest, 0xff << 8);
- setbits_le32(dest, (addr + j) << 8);
-
- clrbits_le32(dest, usbc_bit);
- /* set data bit */
- if (data & 0x1)
- setbits_le32(dest, 1 << 7);
- else
- clrbits_le32(dest, 1 << 7);
-
- setbits_le32(dest, usbc_bit);
-
- clrbits_le32(dest, usbc_bit);
-
- data >>= 1;
- }
-}
-
-#if defined CONFIG_MACH_SUN8I_H3
-static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
-{
- if (phy->id == 0)
- clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
-
- clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02);
-}
-#else
-static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
-{
- /* The following comments are machine
- * translated from Chinese, you have been warned!
- */
-
- /* Regulation 45 ohms */
- if (phy->id == 0)
- usb_phy_write(phy, 0x0c, 0x01, 1);
-
- /* adjust PHY's magnitude and rate */
- usb_phy_write(phy, 0x20, 0x14, 5);
-
- /* threshold adjustment disconnect */
-#if defined CONFIG_MACH_SUN5I || defined CONFIG_MACH_SUN7I
- usb_phy_write(phy, 0x2a, 2, 2);
-#else
- usb_phy_write(phy, 0x2a, 3, 2);
-#endif
-
- return;
-}
-#endif
-
-static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable)
-{
- unsigned long bits = 0;
- void *addr;
-
- addr = (void *)phy->base + SUNXI_USB_PMU_IRQ_ENABLE;
-
- bits = SUNXI_EHCI_AHB_ICHR8_EN |
- SUNXI_EHCI_AHB_INCR4_BURST_EN |
- SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
- SUNXI_EHCI_ULPI_BYPASS_EN;
-
- if (enable)
- setbits_le32(addr, bits);
- else
- clrbits_le32(addr, bits);
-
- return;
-}
-
-void sunxi_usb_phy_enable_squelch_detect(int index, int enable)
-{
- struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
-
- usb_phy_write(phy, 0x3c, enable ? 0 : 2, 2);
-}
-
-void sunxi_usb_phy_init(int index)
-{
- struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- phy->init_count++;
- if (phy->init_count != 1)
- return;
-
- setbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
-
- sunxi_usb_phy_config(phy);
-
- if (phy->id != 0)
- sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN);
-}
-
-void sunxi_usb_phy_exit(int index)
-{
- struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- phy->init_count--;
- if (phy->init_count != 0)
- return;
-
- if (phy->id != 0)
- sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN);
-
- clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
-}
-
-void sunxi_usb_phy_power_on(int index)
-{
- struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
-
- phy->power_on_count++;
- if (phy->power_on_count != 1)
- return;
-
- if (phy->gpio_vbus >= 0)
- gpio_set_value(phy->gpio_vbus, 1);
-}
-
-void sunxi_usb_phy_power_off(int index)
-{
- struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
-
- phy->power_on_count--;
- if (phy->power_on_count != 0)
- return;
-
- if (phy->gpio_vbus >= 0)
- gpio_set_value(phy->gpio_vbus, 0);
-}
-
-int sunxi_usb_phy_power_is_on(int index)
-{
- struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
-
- return phy->power_on_count > 0;
-}
-
-int sunxi_usb_phy_vbus_detect(int index)
-{
- struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
- int err, retries = 3;
-
- if (phy->gpio_vbus_det < 0)
- return phy->gpio_vbus_det;
-
- err = gpio_get_value(phy->gpio_vbus_det);
- /*
- * Vbus may have been provided by the board and just been turned of
- * some milliseconds ago on reset, what we're measuring then is a
- * residual charge on Vbus, sleep a bit and try again.
- */
- while (err > 0 && retries--) {
- mdelay(100);
- err = gpio_get_value(phy->gpio_vbus_det);
- }
-
- return err;
-}
-
-int sunxi_usb_phy_id_detect(int index)
-{
- struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
-
- if (phy->gpio_id_det < 0)
- return phy->gpio_id_det;
-
- return gpio_get_value(phy->gpio_id_det);
-}
-
-int sunxi_usb_phy_probe(void)
-{
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- struct sunxi_usb_phy *phy;
- int i, ret = 0;
-
- for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
- phy = &sunxi_usb_phy[i];
-
- phy->gpio_vbus = get_vbus_gpio(i);
- if (phy->gpio_vbus >= 0) {
- ret = gpio_request(phy->gpio_vbus, "usb_vbus");
- if (ret)
- return ret;
- ret = gpio_direction_output(phy->gpio_vbus, 0);
- if (ret)
- return ret;
- }
-
- phy->gpio_vbus_det = get_vbus_detect_gpio(i);
- if (phy->gpio_vbus_det >= 0) {
- ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
- if (ret)
- return ret;
- ret = gpio_direction_input(phy->gpio_vbus_det);
- if (ret)
- return ret;
- }
-
- phy->gpio_id_det = get_id_detect_gpio(i);
- if (phy->gpio_id_det >= 0) {
- ret = gpio_request(phy->gpio_id_det, "usb_id_det");
- if (ret)
- return ret;
- ret = gpio_direction_input(phy->gpio_id_det);
- if (ret)
- return ret;
- sunxi_gpio_set_pull(phy->gpio_id_det,
- SUNXI_GPIO_PULL_UP);
- }
- }
-
- setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
-
- return 0;
-}
-
-int sunxi_usb_phy_remove(void)
-{
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- struct sunxi_usb_phy *phy;
- int i;
-
- clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
-
- for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
- phy = &sunxi_usb_phy[i];
-
- if (phy->gpio_vbus >= 0)
- gpio_free(phy->gpio_vbus);
-
- if (phy->gpio_vbus_det >= 0)
- gpio_free(phy->gpio_vbus_det);
-
- if (phy->gpio_id_det >= 0)
- gpio_free(phy->gpio_id_det);
- }
-
- return 0;
-}
}
/* Returns the estimated required size of all page tables */
-u64 get_page_table_size(void)
+__weak u64 get_page_table_size(void)
{
u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
u64 size = 0;
obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
endif
-ifneq ($(CONFIG_LS2085A),)
-obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
-endif
-
ifneq ($(CONFIG_LS1043A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
endif
*/
}
+u64 get_page_table_size(void)
+{
+ return 0x10000;
+}
+
int arch_cpu_init(void)
{
icache_enable();
struct sys_info sysinfo;
char buf[32];
unsigned int i, core;
- u32 type, rcw;
+ u32 type, rcw, svr = gur_in32(&gur->svr);
puts("SoC: ");
cpu_name(buf);
- printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr));
+ printf(" %s (0x%x)\n", buf, svr);
memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
get_sys_info(&sysinfo);
puts("Clock Configuration:");
printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
#endif
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
+ if (soc_has_dp_ddr()) {
+ printf(" DP-DDR: %-4s MT/s",
+ strmhz(buf, sysinfo.freq_ddrbus2));
+ }
#endif
puts("\n");
}
#endif
-/*
- * the burden is on the the caller to not request a count
- * exceeding the bounds of the stream_ids[] array
- */
-void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt)
-{
- int i;
-
- if (count > max_cnt) {
- printf("\n%s: ERROR: max per-device stream ID count exceed\n",
- __func__);
- return;
- }
-
- for (i = 0; i < count; i++)
- stream_ids[i] = start_id++;
-}
-
-/*
- * This function updates the mmu-masters property on the SMMU
- * node as per the SMMU binding-- phandle and list of stream IDs
- * for each MMU master.
- */
-void append_mmu_masters(void *blob, const char *smmu_path,
- const char *master_name, u32 *stream_ids, int count)
-{
- u32 phandle;
- int smmu_nodeoffset;
- int master_nodeoffset;
- int i;
-
- /* get phandle of mmu master device */
- master_nodeoffset = fdt_path_offset(blob, master_name);
- if (master_nodeoffset < 0) {
- printf("\n%s: ERROR: master not found\n", __func__);
- return;
- }
- phandle = fdt_get_phandle(blob, master_nodeoffset);
- if (!phandle) { /* if master has no phandle, create one */
- phandle = fdt_create_phandle(blob, master_nodeoffset);
- if (!phandle) {
- printf("\n%s: ERROR: unable to create phandle\n",
- __func__);
- return;
- }
- }
-
- /* append it to mmu-masters */
- smmu_nodeoffset = fdt_path_offset(blob, smmu_path);
- if (fdt_appendprop_u32(blob, smmu_nodeoffset, "mmu-masters",
- phandle) < 0) {
- printf("\n%s: ERROR: unable to update SMMU node\n", __func__);
- return;
- }
-
- /* for each stream ID, append to mmu-masters */
- for (i = 0; i < count; i++) {
- fdt_appendprop_u32(blob, smmu_nodeoffset, "mmu-masters",
- stream_ids[i]);
- }
-
- /* fix up #stream-id-cells with stream ID count */
- if (fdt_setprop_u32(blob, master_nodeoffset, "#stream-id-cells",
- count) < 0)
- printf("\n%s: ERROR: unable to update #stream-id-cells\n",
- __func__);
-}
-
-
-/*
- * The info below summarizes how streamID partitioning works
- * for ls2080a and how it is conveyed to the OS via the device tree.
- *
- * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
- * -all legacy devices get a unique ICID assigned and programmed in
- * their AMQR registers by u-boot
- * -u-boot updates the hardware device tree with streamID properties
- * for each platform/legacy device (smmu-masters property)
- *
- * -PCIe
- * -for each PCI controller that is active (as per RCW settings),
- * u-boot will allocate a range of ICID and convey that to Linux via
- * the device tree (smmu-masters property)
- *
- * -DPAA2
- * -u-boot will allocate a range of ICIDs to be used by the Management
- * Complex for containers and will set these values in the MC DPC image.
- * -the MC is responsible for allocating and setting up ICIDs
- * for all DPAA2 devices.
- *
- */
-#ifdef CONFIG_FSL_LSCH3
-static void fdt_fixup_smmu(void *blob)
-{
- int nodeoffset;
-
- nodeoffset = fdt_path_offset(blob, "/iommu@5000000");
- if (nodeoffset < 0) {
- printf("\n%s: WARNING: no SMMU node found\n", __func__);
- return;
- }
-
- /* fixup for all PCI controllers */
-#ifdef CONFIG_PCI
- fdt_fixup_smmu_pcie(blob);
-#endif
-}
-#endif
-
void ft_cpu_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_MP
fdt_fixup_esdhc(blob, bd);
#endif
-#ifdef CONFIG_FSL_LSCH3
- fdt_fixup_smmu(blob);
-#endif
-
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_firmware(blob);
#endif
#define HWA_CGA_M2_CLK_SEL 0x00000007
#define HWA_CGA_M2_CLK_SHIFT 0
#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
rcw_tmp = in_be32(&gur->rcwsr[15]);
rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
+#else
+ sys_info->freq_sdhc = sys_info->freq_systembus;
+#endif
#endif
#if defined(CONFIG_FSL_IFC)
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
+ if (soc_has_dp_ddr()) {
+ sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
+ } else {
+ sys_info->freq_ddrbus2 = 0;
+ }
#endif
for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
mov x29, lr /* Save LR */
#ifdef CONFIG_FSL_LSCH3
+
+ /* Set Wuo bit for RN-I 20 */
+#ifdef CONFIG_LS2080A
+ ldr x0, =CCI_AUX_CONTROL_BASE(20)
+ ldr x1, =0x00000010
+ bl ccn504_set_aux
+#endif
+
/* Add fully-coherent masters to DVM domain */
ldr x0, =CCI_MN_BASE
ldr x1, =CCI_MN_RNF_NODEID_LIST
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
- {0x03, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2 } },
+ {0x03, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
{0x05, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } },
{0x07, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
SGMII1 } },
{0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
{0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } },
{0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } },
- {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A,
- QSGMII_B} },
- {0x35, {QSGMII_C, QSGMII_D, QSGMII_A, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
+ {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B,
+ QSGMII_A} },
+ {0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
{}
};
static struct serdes_config serdes2_cfg_tbl[] = {
{0x42, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
{0x43, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
{0x44, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
- {0x45, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15,
- SGMII16 } },
- {0x47, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4,
+ {0x45, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4,
PCIE4 } },
+ {0x47, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15,
+ SGMII16 } },
{0x49, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
SATA2 } },
{0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+bool soc_has_dp_ddr(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 svr = gur_in32(&gur->svr);
+
+ /* LS2085A has DP_DDR */
+ if (SVR_SOC_VER(svr) == SVR_LS2085)
+ return true;
+
+ return false;
+}
+
+bool soc_has_aiop(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 svr = gur_in32(&gur->svr);
+
+ /* LS2085A has AIOP */
+ if (SVR_SOC_VER(svr) == SVR_LS2085)
+ return true;
+
+ return false;
+}
+
+#ifdef CONFIG_LS2080A
/*
* This erratum requires setting a value to eddrtqcr1 to
* optimal the DDR performance.
#endif
#endif
}
-
+void bypass_smmu(void)
+{
+ u32 val;
+ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_SCR0, val);
+ val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_NSCR0, val);
+}
void fsl_lsch3_early_init_f(void)
{
erratum_a008751();
erratum_a009203();
erratum_a008514();
erratum_a008336();
+#ifdef CONFIG_CHAIN_OF_TRUST
+ /* In case of Secure Boot, the IBR configures the SMMU
+ * to allow only Secure transactions.
+ * SMMU must be reset in bypass mode.
+ * Set the ClientPD bit and Clear the USFCFG Bit
+ */
+ if (fsl_check_boot_mode_secure() == 1)
+ bypass_smmu();
+#endif
}
#ifdef CONFIG_SCSI_AHCI_PLAT
init_early_memctl_regs(); /* tighten IFC timing */
#endif
-#ifdef CONFIG_FSL_QSPI
+#if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
/* Make SEC reads and writes snoopable */
{
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
arch_cpu_init();
#endif
#ifdef CONFIG_FSL_IFC
#endif
board_early_init_f();
timer_init();
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
env_init();
#endif
get_clocks();
mov x29, lr /* Save LR */
#ifndef CONFIG_ARMV8_MULTIENTRY
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
/*
* For single-entry systems the lowlevel init is very simple.
*/
ldr x0, =GICD_BASE
bl gic_init_secure
-
+#endif
#else /* CONFIG_ARMV8_MULTIENTRY is set */
-
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
branch_if_slave x0, 1f
ldr x0, =GICD_BASE
if ARCH_ZYNQMP
-choice
- prompt "Xilinx ZynqMP board select"
-
-config TARGET_ZYNQMP_EP
- bool "ZynqMP EP Board"
-
-endchoice
-
config SYS_BOARD
default "zynqmp"
default "zynqmp"
config SYS_CONFIG_NAME
- default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP
+ string "Board configuration name"
+ default "xilinx_zynqmp"
+ help
+ This option contains information about board configuration name.
+ Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+ will be used for board configuration.
config ZYNQMP_USB
bool "Configure ZynqMP USB"
obj-y += timer.o
obj-y += usb.o
obj-y += relocate.o
+obj-y += cache.o
--- /dev/null
+/*
+ * (C) Copyright 2016 Vasily Khoruzhick <anarsoul@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/types.h>
+#include <common.h>
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#endif
+
+void invalidate_dcache_all(void)
+{
+ /* Flush/Invalidate I cache */
+ asm volatile("mcr p15, 0, %0, c7, c5, 0\n" : : "r"(0));
+ /* Flush/Invalidate D cache */
+ asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
+}
+
+void flush_dcache_all(void)
+{
+ return invalidate_dcache_all();
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+ stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+
+ while (start <= stop) {
+ asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
+ start += CONFIG_SYS_CACHELINE_SIZE;
+ }
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ return invalidate_dcache_range(start, stop);
+}
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+/*
+ * Stub implementations for l2 cache operations
+ */
+
+__weak void l2_cache_disable(void) {}
+
+#if defined CONFIG_SYS_THUMB_BUILD
+__weak void invalidate_l2_cache(void) {}
+#endif
for (;;)
;
}
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+ icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+ dcache_enable();
+#endif
+}
#ifdef CONFIG_CPU_PXA25X
bl lock_cache_for_stack
#endif
-
+#ifdef CONFIG_CPU_PXA27X
+ /*
+ * enable clock for SRAM
+ */
+ ldr r0,=CKEN
+ ldr r1,[r0]
+ orr r1,r1,#(1 << 20)
+ str r1,[r0]
+#endif
bl _main
/*------------------------------------------------------------------------------*/
ENTRY(_start)
SECTIONS
{
+#ifndef CONFIG_CMDLINE
+ /DISCARD/ : { *(.u_boot_list_2_cmd_*) }
+#endif
#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC)
/*
* If CONFIG_ARMV7_SECURE_BASE is true, secure code will not
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_MVEBU) += \
+ armada-375-db.dtb \
armada-388-clearfog.dtb \
armada-388-gp.dtb \
armada-xp-gp.dtb \
armada-xp-theadorable.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
+ uniphier-ph1-ld11-ref.dtb \
+ uniphier-ph1-ld20-ref.dtb \
uniphier-ph1-ld4-ref.dtb \
uniphier-ph1-ld6b-ref.dtb \
uniphier-ph1-pro4-ace.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb
+dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
+
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
sun4i-a10-chuwi-v7-cw0825.dtb \
sun4i-a10-cubieboard.dtb \
+ sun4i-a10-dserve-dsrv9703c.dtb \
sun4i-a10-gemei-g9.dtb \
sun4i-a10-hackberry.dtb \
sun4i-a10-hyundai-a7hd.dtb \
sun4i-a10-mk802ii.dtb \
sun4i-a10-olinuxino-lime.dtb \
sun4i-a10-pcduino.dtb \
+ sun4i-a10-pcduino2.dtb \
sun4i-a10-pov-protab2-ips9.dtb
dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a10s-auxtek-t003.dtb \
sun5i-a10s-r7-tv-dongle.dtb \
sun5i-a10s-wobo-i5.dtb \
sun5i-a13-ampe-a76.dtb \
+ sun5i-a13-difrnce-dit4350.dtb \
sun5i-a13-empire-electronix-d709.dtb \
sun5i-a13-hsg-h702.dtb \
sun5i-a13-inet-86vs.dtb \
sun6i-a31-m9.dtb \
sun6i-a31-mele-a1000g-quad.dtb \
sun6i-a31-mixtile-loftq.dtb \
+ sun6i-a31s-colorfly-e708-q1.dtb \
sun6i-a31s-cs908.dtb \
sun6i-a31s-primo81.dtb \
- sun6i-a31s-sinovoip-bpi-m2.dtb
+ sun6i-a31s-sina31s.dtb \
+ sun6i-a31s-sinovoip-bpi-m2.dtb \
+ sun6i-a31s-yones-toptech-bs1078-v2.dtb
dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-ainol-aw1.dtb \
sun7i-a20-bananapi.dtb \
sun7i-a20-cubietruck.dtb \
sun7i-a20-hummingbird.dtb \
sun7i-a20-i12-tvbox.dtb \
+ sun7i-a20-icnova-swac.dtb \
+ sun7i-a20-itead-ibox.dtb \
sun7i-a20-lamobo-r1.dtb \
sun7i-a20-m3.dtb \
sun7i-a20-m5.dtb \
dtb-$(CONFIG_MACH_SUN8I_A23) += \
sun8i-a23-evb.dtb \
sun8i-a23-gt90h-v4.dtb \
+ sun8i-a23-polaroid-mid2809pxe04.dtb \
sun8i-a23-q8-tablet.dtb
dtb-$(CONFIG_MACH_SUN8I_A33) += \
sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-sinlinx-sina33.dtb
dtb-$(CONFIG_MACH_SUN8I_A83T) += \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
+ sun8i-a83t-cubietruck-plus.dtb \
sun8i-a83t-sinovoip-bpi-m3.dtb
dtb-$(CONFIG_MACH_SUN8I_H3) += \
+ sun8i-h3-orangepi-2.dtb \
+ sun8i-h3-orangepi-one.dtb \
sun8i-h3-orangepi-pc.dtb \
sun8i-h3-orangepi-plus.dtb
+dtb-$(CONFIG_MACH_SUN50I) += \
+ pine64_plus.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
--- /dev/null
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ * based on the Allwinner H3 dtsi:
+ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ compatible = "allwinner,a64";
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2", "arm,psci";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x40000000 0>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ pll1: clk@01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-a23-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll1";
+ };
+
+ pll6: clk@01c20028 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-pll6-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll6", "pll6x2";
+ };
+
+ pll6d2: pll6d2_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <2>;
+ clock-mult = <1>;
+ clocks = <&pll6 0>;
+ clock-output-names = "pll6d2";
+ };
+
+ /* dummy clock until pll6 can be reused */
+ pll8: pll8_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+ clock-output-names = "pll8";
+ };
+
+ cpu: cpu_clk@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-cpu-clk";
+ reg = <0x01c20050 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
+ clock-output-names = "cpu";
+ };
+
+ axi: axi_clk@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-axi-clk";
+ reg = <0x01c20050 0x4>;
+ clocks = <&cpu>;
+ clock-output-names = "axi";
+ };
+
+ ahb1: ahb1_clk@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-ahb1-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
+ clock-output-names = "ahb1";
+ };
+
+ ahb2: ahb2_clk@01c2005c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-h3-ahb2-clk";
+ reg = <0x01c2005c 0x4>;
+ clocks = <&ahb1>, <&pll6d2>;
+ clock-output-names = "ahb2";
+ };
+
+ apb1: apb1_clk@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb1>;
+ clock-output-names = "apb1";
+ };
+
+ apb2: apb2_clk@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
+ clock-output-names = "apb2";
+ };
+
+ bus_gates: clk@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,a64-bus-gates-clk",
+ "allwinner,sun8i-h3-bus-gates-clk";
+ reg = <0x01c20060 0x14>;
+ clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
+ clock-names = "ahb1", "ahb2", "apb1", "apb2";
+ clock-indices = <1>,
+ <5>, <6>, <8>,
+ <9>, <10>, <13>,
+ <14>, <17>, <18>,
+ <19>, <20>,
+ <21>, <23>,
+ <24>, <25>,
+ <28>, <29>,
+ <32>, <35>,
+ <36>, <37>,
+ <40>, <43>,
+ <44>, <52>, <53>,
+ <54>, <64>,
+ <65>, <69>, <72>,
+ <76>, <77>, <78>,
+ <96>, <97>, <98>,
+ <101>,
+ <112>, <113>,
+ <114>, <115>,
+ <116>, <135>;
+ clock-output-names = "bus_mipidsi",
+ "bus_ce", "bus_dma", "bus_mmc0",
+ "bus_mmc1", "bus_mmc2", "bus_nand",
+ "bus_sdram", "bus_gmac", "bus_ts",
+ "bus_hstimer", "bus_spi0",
+ "bus_spi1", "bus_otg",
+ "bus_otg_ehci0", "bus_ehci0",
+ "bus_otg_ohci0", "bus_ohci0",
+ "bus_ve", "bus_lcd0",
+ "bus_lcd1", "bus_deint",
+ "bus_csi", "bus_hdmi",
+ "bus_de", "bus_gpu", "bus_msgbox",
+ "bus_spinlock", "bus_codec",
+ "bus_spdif", "bus_pio", "bus_ths",
+ "bus_i2s0", "bus_i2s1", "bus_i2s2",
+ "bus_i2c0", "bus_i2c1", "bus_i2c2",
+ "bus_scr",
+ "bus_uart0", "bus_uart1",
+ "bus_uart2", "bus_uart3",
+ "bus_uart4", "bus_dbg";
+ };
+
+ mmc0_clk: clk@01c20088 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20088 0x4>;
+ clocks = <&osc24M>, <&pll6 0>, <&pll8>;
+ clock-output-names = "mmc0",
+ "mmc0_output",
+ "mmc0_sample";
+ };
+
+ mmc1_clk: clk@01c2008c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c2008c 0x4>;
+ clocks = <&osc24M>, <&pll6 0>, <&pll8>;
+ clock-output-names = "mmc1",
+ "mmc1_output",
+ "mmc1_sample";
+ };
+
+ mmc2_clk: clk@01c20090 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20090 0x4>;
+ clocks = <&osc24M>, <&pll6 0>, <&pll8>;
+ clock-output-names = "mmc2",
+ "mmc2_output",
+ "mmc2_sample";
+ };
+ };
+
+ regulators {
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&bus_gates 8>,
+ <&mmc0_clk 0>,
+ <&mmc0_clk 1>,
+ <&mmc0_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb_rst 8>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&bus_gates 9>,
+ <&mmc1_clk 0>,
+ <&mmc1_clk 1>,
+ <&mmc1_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb_rst 9>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&bus_gates 10>,
+ <&mmc2_clk 0>,
+ <&mmc2_clk 1>,
+ <&mmc2_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb_rst 10>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pio: pinctrl@01c20800 {
+ compatible = "allwinner,a64-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 69>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PB8", "PB9";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart0_pins_b: uart0@1 {
+ allwinner,pins = "PF2", "PF3";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart1_pins: uart1@0 {
+ allwinner,pins = "PG6", "PG7", "PG8", "PG9";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart2_pins: uart2@0 {
+ allwinner,pins = "PB0", "PB1", "PB2", "PB3";
+ allwinner,function = "uart2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart3_pins_a: uart3@0 {
+ allwinner,pins = "PD0", "PD1";
+ allwinner,function = "uart3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart3_pins_b: uart3@1 {
+ allwinner,pins = "PH4", "PH5", "PH6", "PH7";
+ allwinner,function = "uart3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart4_pins: uart4@0 {
+ allwinner,pins = "PD2", "PD3", "PD4", "PD5";
+ allwinner,function = "uart4";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_pins: mmc0@0 {
+ allwinner,pins = "PF0", "PF1", "PF2", "PF3",
+ "PF4", "PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_default_cd_pin: mmc0_cd_pin@0 {
+ allwinner,pins = "PF6";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ mmc1_pins: mmc1@0 {
+ allwinner,pins = "PG0", "PG1", "PG2", "PG3",
+ "PG4", "PG5";
+ allwinner,function = "mmc1";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc2_pins: mmc2@0 {
+ allwinner,pins = "PC1", "PC5", "PC6", "PC8",
+ "PC9", "PC10";
+ allwinner,function = "mmc2";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
+
+ ahb_rst: reset@01c202c0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-ahb1-reset";
+ reg = <0x01c202c0 0xc>;
+ };
+
+ apb1_rst: reset@01c202d0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d0 0x4>;
+ };
+
+ apb2_rst: reset@01c202d8 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d8 0x4>;
+ };
+
+ uart0: serial@01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 112>;
+ resets = <&apb2_rst 16>;
+ reset-names = "apb2";
+ status = "disabled";
+ };
+
+ uart1: serial@01c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 113>;
+ resets = <&apb2_rst 17>;
+ reset-names = "apb2";
+ status = "disabled";
+ };
+
+ uart2: serial@01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 114>;
+ resets = <&apb2_rst 18>;
+ reset-names = "apb2";
+ status = "disabled";
+ };
+
+ uart3: serial@01c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 115>;
+ resets = <&apb2_rst 19>;
+ reset-names = "apb2";
+ status = "disabled";
+ };
+
+ uart4: serial@01c29000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29000 0x400>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 116>;
+ resets = <&apb2_rst 20>;
+ reset-names = "apb2";
+ status = "disabled";
+ };
+
+ rtc: rtc@01f00000 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01f00000 0x54>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gic: interrupt-controller@{
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0x01C81000 0x1000>,
+ <0x01C82000 0x2000>,
+ <0x01C84000 0x2000>,
+ <0x01C86000 0x2000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+};
--- /dev/null
+/*
+ * Device Tree file for Marvell Armada 375 evaluation board
+ * (DB-88F6720)
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-375.dtsi"
+
+/ {
+ model = "Marvell Armada 375 Development Board";
+ compatible = "marvell,a375-db", "marvell,armada375";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ /* So that mvebu u-boot can update the MAC addresses */
+ ethernet0 = ð0;
+ ethernet1 = ð1;
+ spi0 = &spi0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>; /* 1 GB */
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
+ MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
+ MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
+
+ internal-regs {
+ spi@10600 {
+ pinctrl-0 = <&spi0_pins>;
+ pinctrl-names = "default";
+ /*
+ * SPI conflicts with NAND, so we disable it
+ * here, and select NAND as the enabled device
+ * by default.
+ */
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ spi-flash@0 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a13", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <108000000>;
+ };
+ };
+
+ i2c@11000 {
+ status = "okay";
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ };
+
+ i2c@11100 {
+ status = "okay";
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+ };
+
+ serial@12000 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+ };
+
+ pinctrl {
+ sdio_st_pins: sdio-st-pins {
+ marvell,pins = "mpp44", "mpp45";
+ marvell,function = "gpio";
+ };
+ };
+
+ sata@a0000 {
+ status = "okay";
+ nr-ports = <2>;
+ };
+
+ nand: nand@d0000 {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ num-cs = <1>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x800000>;
+ };
+ partition@800000 {
+ label = "Linux";
+ reg = <0x800000 0x800000>;
+ };
+ partition@1000000 {
+ label = "Filesystem";
+ reg = <0x1000000 0x3f000000>;
+ };
+ };
+
+ usb@54000 {
+ status = "okay";
+ };
+
+ usb3@58000 {
+ status = "okay";
+ };
+
+ mvsdio@d4000 {
+ pinctrl-0 = <&sdio_pins &sdio_st_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ };
+
+ mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ };
+
+ ethernet@f0000 {
+ status = "okay";
+
+ eth0@c4000 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ };
+
+ eth1@c5000 {
+ status = "okay";
+ phy = <&phy3>;
+ phy-mode = "gmii";
+ };
+ };
+ };
+
+ pcie-controller {
+ status = "okay";
+ /*
+ * The two PCIe units are accessible through
+ * standard PCIe slots on the board.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * Device Tree Include file for Marvell Armada 375 family SoC
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
+/ {
+ model = "Marvell Armada 375 family SoC";
+ compatible = "marvell,armada375";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ clocks {
+ /* 2 GHz fixed main PLL */
+ mainpll: mainpll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000000>;
+ };
+ /* 25 MHz reference crystal */
+ refclk: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "marvell,armada-375-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts-extended = <&mpic 3>;
+ };
+
+ soc {
+ compatible = "marvell,armada375-mbus", "simple-bus";
+ u-boot,dm-pre-reloc;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ controller = <&mbusc>;
+ interrupt-parent = <&gic>;
+ pcie-mem-aperture = <0xe0000000 0x8000000>;
+ pcie-io-aperture = <0xe8000000 0x100000>;
+
+ bootrom {
+ compatible = "marvell,bootrom";
+ reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
+ };
+
+ devbus-bootcs {
+ compatible = "marvell,mvebu-devbus";
+ reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
+ ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ devbus-cs0 {
+ compatible = "marvell,mvebu-devbus";
+ reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
+ ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ devbus-cs1 {
+ compatible = "marvell,mvebu-devbus";
+ reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
+ ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ devbus-cs2 {
+ compatible = "marvell,mvebu-devbus";
+ reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
+ ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ devbus-cs3 {
+ compatible = "marvell,mvebu-devbus";
+ reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
+ ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ internal-regs {
+ compatible = "simple-bus";
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+ L2: cache-controller@8000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x8000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ arm,double-linefill-incr = <1>;
+ arm,double-linefill-wrap = <0>;
+ arm,double-linefill = <1>;
+ prefetch-data = <1>;
+ };
+
+ scu@c000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xc000 0x58>;
+ };
+
+ timer@c600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0xc600 0x20>;
+ interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
+ clocks = <&coreclk 2>;
+ };
+
+ gic: interrupt-controller@d000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #size-cells = <0>;
+ interrupt-controller;
+ reg = <0xd000 0x1000>,
+ <0xc100 0x100>;
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0xc0054 0x4>;
+ clocks = <&gateclk 19>;
+ };
+
+ /* Network controller */
+ ethernet@f0000 {
+ compatible = "marvell,armada-375-pp2";
+ reg = <0xf0000 0xa000>, /* Packet Processor regs */
+ <0xc0000 0x3060>, /* LMS regs */
+ <0xc4000 0x100>, /* eth0 regs */
+ <0xc5000 0x100>; /* eth1 regs */
+ clocks = <&gateclk 3>, <&gateclk 19>;
+ clock-names = "pp_clk", "gop_clk";
+ status = "disabled";
+
+ eth0: eth0@c4000 {
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ port-id = <0>;
+ status = "disabled";
+ };
+
+ eth1: eth1@c5000 {
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ port-id = <1>;
+ status = "disabled";
+ };
+ };
+
+ rtc@10300 {
+ compatible = "marvell,orion-rtc";
+ reg = <0x10300 0x20>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ spi0: spi@10600 {
+ compatible = "marvell,armada-375-spi",
+ "marvell,orion-spi";
+ reg = <0x10600 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ spi1: spi@10680 {
+ compatible = "marvell,armada-375-spi",
+ "marvell,orion-spi";
+ reg = <0x10680 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@11000 {
+ compatible = "marvell,mv64xxx-i2c";
+ reg = <0x11000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ timeout-ms = <1000>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11100 {
+ compatible = "marvell,mv64xxx-i2c";
+ reg = <0x11100 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ timeout-ms = <1000>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ uart0: serial@12000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x12000 0x100>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ uart1: serial@12100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x12100 0x100>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ pinctrl {
+ compatible = "marvell,mv88f6720-pinctrl";
+ reg = <0x18000 0x24>;
+
+ i2c0_pins: i2c0-pins {
+ marvell,pins = "mpp14", "mpp15";
+ marvell,function = "i2c0";
+ };
+
+ i2c1_pins: i2c1-pins {
+ marvell,pins = "mpp61", "mpp62";
+ marvell,function = "i2c1";
+ };
+
+ nand_pins: nand-pins {
+ marvell,pins = "mpp0", "mpp1", "mpp2",
+ "mpp3", "mpp4", "mpp5",
+ "mpp6", "mpp7", "mpp8",
+ "mpp9", "mpp10", "mpp11",
+ "mpp12", "mpp13";
+ marvell,function = "nand";
+ };
+
+ sdio_pins: sdio-pins {
+ marvell,pins = "mpp24", "mpp25", "mpp26",
+ "mpp27", "mpp28", "mpp29";
+ marvell,function = "sd";
+ };
+
+ spi0_pins: spi0-pins {
+ marvell,pins = "mpp0", "mpp1", "mpp4",
+ "mpp5", "mpp8", "mpp9";
+ marvell,function = "spi0";
+ };
+ };
+
+ gpio0: gpio@18100 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18100 0x40>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpio1: gpio@18140 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18140 0x40>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpio2: gpio@18180 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18180 0x40>;
+ ngpios = <3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ system-controller@18200 {
+ compatible = "marvell,armada-375-system-controller";
+ reg = <0x18200 0x100>;
+ };
+
+ gateclk: clock-gating-control@18220 {
+ compatible = "marvell,armada-375-gating-clock";
+ reg = <0x18220 0x4>;
+ clocks = <&coreclk 0>;
+ #clock-cells = <1>;
+ };
+
+ usbcluster: usb-cluster@18400 {
+ compatible = "marvell,armada-375-usb-cluster";
+ reg = <0x18400 0x4>;
+ #phy-cells = <1>;
+ };
+
+ mbusc: mbus-controller@20000 {
+ compatible = "marvell,mbus-controller";
+ reg = <0x20000 0x100>, <0x20180 0x20>;
+ };
+
+ mpic: interrupt-controller@20a00 {
+ compatible = "marvell,mpic";
+ reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+ #interrupt-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ msi-controller;
+ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer@20300 {
+ compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
+ reg = <0x20300 0x30>, <0x21040 0x30>;
+ interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <&mpic 5>,
+ <&mpic 6>;
+ clocks = <&coreclk 0>, <&refclk>;
+ clock-names = "nbclk", "fixed";
+ };
+
+ watchdog@20300 {
+ compatible = "marvell,armada-375-wdt";
+ reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
+ clocks = <&coreclk 0>, <&refclk>;
+ clock-names = "nbclk", "fixed";
+ };
+
+ cpurst@20800 {
+ compatible = "marvell,armada-370-cpu-reset";
+ reg = <0x20800 0x10>;
+ };
+
+ coherency-fabric@21010 {
+ compatible = "marvell,armada-375-coherency-fabric";
+ reg = <0x21010 0x1c>;
+ };
+
+ usb@50000 {
+ compatible = "marvell,orion-ehci";
+ reg = <0x50000 0x500>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gateclk 18>;
+ phys = <&usbcluster PHY_TYPE_USB2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb@54000 {
+ compatible = "marvell,orion-ehci";
+ reg = <0x54000 0x500>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gateclk 26>;
+ status = "disabled";
+ };
+
+ usb3@58000 {
+ compatible = "marvell,armada-375-xhci";
+ reg = <0x58000 0x20000>,<0x5b880 0x80>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gateclk 16>;
+ phys = <&usbcluster PHY_TYPE_USB3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ xor@60800 {
+ compatible = "marvell,orion-xor";
+ reg = <0x60800 0x100
+ 0x60A00 0x100>;
+ clocks = <&gateclk 22>;
+ status = "okay";
+
+ xor00 {
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ dmacap,memcpy;
+ dmacap,xor;
+ };
+ xor01 {
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
+ };
+ };
+
+ xor@60900 {
+ compatible = "marvell,orion-xor";
+ reg = <0x60900 0x100
+ 0x60b00 0x100>;
+ clocks = <&gateclk 23>;
+ status = "okay";
+
+ xor10 {
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ dmacap,memcpy;
+ dmacap,xor;
+ };
+ xor11 {
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
+ };
+ };
+
+ crypto@90000 {
+ compatible = "marvell,armada-375-crypto";
+ reg = <0x90000 0x10000>;
+ reg-names = "regs";
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gateclk 30>, <&gateclk 31>,
+ <&gateclk 28>, <&gateclk 29>;
+ clock-names = "cesa0", "cesa1",
+ "cesaz0", "cesaz1";
+ marvell,crypto-srams = <&crypto_sram0>,
+ <&crypto_sram1>;
+ marvell,crypto-sram-size = <0x800>;
+ };
+
+ sata@a0000 {
+ compatible = "marvell,orion-sata";
+ reg = <0xa0000 0x5000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gateclk 14>, <&gateclk 20>;
+ clock-names = "0", "1";
+ status = "disabled";
+ };
+
+ nand@d0000 {
+ compatible = "marvell,armada370-nand";
+ reg = <0xd0000 0x54>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gateclk 11>;
+ status = "disabled";
+ };
+
+ mvsdio@d4000 {
+ compatible = "marvell,orion-sdio";
+ reg = <0xd4000 0x200>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gateclk 17>;
+ bus-width = <4>;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ status = "disabled";
+ };
+
+ thermal@e8078 {
+ compatible = "marvell,armada375-thermal";
+ reg = <0xe8078 0x4>, <0xe807c 0x8>;
+ status = "okay";
+ };
+
+ coreclk: mvebu-sar@e8204 {
+ compatible = "marvell,armada-375-core-clock";
+ reg = <0xe8204 0x04>;
+ #clock-cells = <1>;
+ };
+
+ coredivclk: corediv-clock@e8250 {
+ compatible = "marvell,armada-375-corediv-clock";
+ reg = <0xe8250 0xc>;
+ #clock-cells = <1>;
+ clocks = <&mainpll>;
+ clock-output-names = "nand";
+ };
+ };
+
+ pcie-controller {
+ compatible = "marvell,armada-370-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ msi-parent = <&mpic>;
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
+ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
+ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
+
+ pcie@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+
+ pcie@2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+ reg = <0x1000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+ 0x81000000 0 0 0x81000000 0x2 0 1 0>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <1>;
+ clocks = <&gateclk 6>;
+ status = "disabled";
+ };
+
+ };
+
+ crypto_sram0: sa-sram0 {
+ compatible = "mmio-sram";
+ reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
+ clocks = <&gateclk 30>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
+ };
+
+ crypto_sram1: sa-sram1 {
+ compatible = "mmio-sram";
+ reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
+ clocks = <&gateclk 31>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
+ };
+ };
+};
aliases {
spi0 = &spi0;
+ spi1 = &spi1;
ethernet0 = ð0;
};
reg = <0>; /* Chip select 0 */
spi-max-frequency = <27777777>;
};
+
+ fpga@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-generic-device";
+ reg = <1>; /* Chip select 1 */
+ spi-max-frequency = <27777777>;
+ };
+ };
+
+ spi1: spi@10680 {
+ status = "okay";
+
+ fpga@2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-generic-device";
+ reg = <2>; /* Chip select 2 */
+ spi-max-frequency = <27777777>;
+ };
};
};
};
--- /dev/null
+/*
+ * Copyright 2015 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * AXP221/221s/223 Integrated Power Management Chip
+ * http://www.x-powers.com/product/AXP22X.php
+ * http://dl.linux-sunxi.org/AXP/AXP221%20Datasheet%20V1.2%2020130326%20.pdf
+ */
+
+&axp22x {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ regulators {
+ /* Default work frequency for buck regulators */
+ x-powers,dcdc-freq = <3000>;
+
+ reg_dcdc1: dcdc1 {
+ regulator-name = "dcdc1";
+ };
+
+ reg_dcdc2: dcdc2 {
+ regulator-name = "dcdc2";
+ };
+
+ reg_dcdc3: dcdc3 {
+ regulator-name = "dcdc3";
+ };
+
+ reg_dcdc4: dcdc4 {
+ regulator-name = "dcdc4";
+ };
+
+ reg_dcdc5: dcdc5 {
+ regulator-name = "dcdc5";
+ };
+
+ reg_dc1sw: dc1sw {
+ regulator-name = "dc1sw";
+ };
+
+ reg_dc5ldo: dc5ldo {
+ regulator-name = "dc5ldo";
+ };
+
+ reg_aldo1: aldo1 {
+ regulator-name = "aldo1";
+ };
+
+ reg_aldo2: aldo2 {
+ regulator-name = "aldo2";
+ };
+
+ reg_aldo3: aldo3 {
+ regulator-name = "aldo3";
+ };
+
+ reg_dldo1: dldo1 {
+ regulator-name = "dldo1";
+ };
+
+ reg_dldo2: dldo2 {
+ regulator-name = "dldo2";
+ };
+
+ reg_dldo3: dldo3 {
+ regulator-name = "dldo3";
+ };
+
+ reg_dldo4: dldo4 {
+ regulator-name = "dldo4";
+ };
+
+ reg_eldo1: eldo1 {
+ regulator-name = "eldo1";
+ };
+
+ reg_eldo2: eldo2 {
+ regulator-name = "eldo2";
+ };
+
+ reg_eldo3: eldo3 {
+ regulator-name = "eldo3";
+ };
+
+ reg_ldo_io0: ldo_io0 {
+ regulator-name = "ldo_io0";
+ status = "disabled";
+ };
+
+ reg_ldo_io1: ldo_io1 {
+ regulator-name = "ldo_io1";
+ status = "disabled";
+ };
+
+ reg_rtc_ldo: rtc_ldo {
+ /* RTC_LDO is a fixed, always-on regulator */
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "rtc_ldo";
+ };
+ };
+};
--- /dev/null
+/*
+ * U-Boot addition to handle Dragonboard 410c pins
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&pm8916_gpios {
+ usb_hub_reset_pm {
+ gpios = <&pm8916_gpios 2 0>;
+ };
+
+ usb_sw_sel_pm {
+ gpios = <&pm8916_gpios 3 0>;
+ };
+};
+
+
+&pm8916_pon {
+ key_vol_down {
+ gpios = <&pm8916_pon 1 0>;
+ };
+
+ key_power {
+ gpios = <&pm8916_pon 0 0>;
+ };
+};
--- /dev/null
+/*
+ * Qualcomm APQ8016 based Dragonboard 410C board device tree source
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "skeleton64.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Dragonboard 410c";
+ compatible = "qcom,dragonboard", "qcom,apq8016-sbc";
+ qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>;
+ qcom,board-id = <0x10018 0x0>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0x3da00000>;
+ };
+
+ chosen {
+ stdout-path = "/soc/serial@78b0000";
+ };
+
+
+ soc {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ ranges = <0x0 0x0 0x0 0xffffffff>;
+ compatible = "simple-bus";
+
+ clkc: qcom,gcc@1800000 {
+ compatible = "qcom,gcc-apq8016";
+ reg = <0x1800000 0x80000>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ serial@78b0000 {
+ compatible = "qcom,msm-uartdm-v1.4";
+ reg = <0x78b0000 0x200>;
+ u-boot,dm-pre-reloc;
+ clock = <&clkc 4>;
+ };
+
+ restart@4ab000 {
+ compatible = "qcom,pshold";
+ reg = <0x4ab000 0x4>;
+ };
+
+ soc_gpios: pinctrl@1000000 {
+ compatible = "qcom,apq8016-pinctrl";
+ reg = <0x1000000 0x300000>;
+ gpio-controller;
+ gpio-count = <122>;
+ gpio-bank-name="soc";
+ #gpio-cells = <1>;
+ };
+
+ ehci@78d9000 {
+ compatible = "qcom,ehci-host";
+ reg = <0x78d9000 0x400>;
+ };
+
+ sdhci@07824000 {
+ compatible = "qcom,sdhci-msm-v4";
+ reg = <0x7824900 0x11c 0x7824000 0x800>;
+ bus-width = <0x8>;
+ index = <0x0>;
+ non-removable;
+ clock = <&clkc 0>;
+ clock-frequency = <100000000>;
+ };
+
+ sdhci@07864000 {
+ compatible = "qcom,sdhci-msm-v4";
+ reg = <0x7864900 0x11c 0x7864000 0x800>;
+ index = <0x1>;
+ bus-width = <0x4>;
+ clock = <&clkc 1>;
+ clock-frequency = <200000000>;
+ };
+
+ spmi@200f000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x200f800 0x200 0x2400000 0x400000 0x2c00000 0x400000>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ pmic0: pm8916@0 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x0 0x1>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+
+ pm8916_pon: pm8916_pon@800 {
+ compatible = "qcom,pm8916-pwrkey";
+ reg = <0x800 0x96>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ pm8916_gpios: pm8916_gpios@c000 {
+ compatible = "qcom,pm8916-gpio";
+ reg = <0xc000 0x400>;
+ gpio-controller;
+ gpio-count = <4>;
+ #gpio-cells = <2>;
+ gpio-bank-name="pmic";
+ };
+ };
+
+ pmic1: pm8916@1 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x1 0x1>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ user1 {
+ label = "green:user1";
+ gpios = <&soc_gpios 21 0>;
+ };
+
+ user2 {
+ label = "green:user2";
+ gpios = <&soc_gpios 120 0>;
+ };
+
+ user3 {
+ label = "green:user3";
+ gpios = <&pm8916_gpios 0 0>;
+ };
+
+ user4 {
+ label = "green:user4";
+ gpios = <&pm8916_gpios 1 0>;
+ };
+ };
+};
+
+#include "dragonboard410c-uboot.dtsi"
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
- reg = <0>;
spi-max-frequency = <1000000>; /* input clock */
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
};
dflash1: sst25wf040b {
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3500000>;
+ spi-cpol;
+ spi-cpha;
reg = <1>;
};
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3500000>;
+ spi-cpol;
+ spi-cpha;
reg = <2>;
};
};
model = "Phytec phyCORE-Vybrid";
compatible = "phytec,pcm052", "fsl,vf610";
- choosen {
+ chosen {
stdout-path = &uart1;
};
--- /dev/null
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x45000000 0x00200000;
+/memreserve/ 0x41010000 0x00010800;
+/memreserve/ 0x40100000 0x00006000;
+
+#include "pine64_common.dtsi"
+
+/ {
+ model = "Pine64";
+ compatible = "pine64,pine64", "allwinner,a64";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x40000000 0x20000000>;
+ };
+};
--- /dev/null
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "a64.dtsi"
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>;
+ vmmc-supply = <®_vcc3v3>;
+ cd-gpios = <&pio 5 6 0>;
+ cd-inverted;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins_a>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x45000000 0x00200000;
+/memreserve/ 0x41010000 0x00010800;
+/memreserve/ 0x40100000 0x00006000;
+
+#include "pine64_common.dtsi"
+
+/ {
+ model = "Pine64+";
+ compatible = "pine64,pine64_plus", "allwinner,a64";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ /* There is a model with 2GB of DRAM, but U-Boot fixes this for us. */
+ memory {
+ reg = <0x40000000 0x40000000>;
+ };
+};
#size-cells = <1>;
compatible = "n25q00", "spi-flash";
reg = <0>; /* chip select */
- spi-max-frequency = <50000000>;
+ spi-max-frequency = <100000000>;
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
status = "okay";
};
+&codec {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Chuwi V7 CW0825";
};
};
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+
+ ft5306de4: touchscreen@38 {
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>;
+ touchscreen-size-x = <1024>;
+ touchscreen-size-y = <768>;
+ };
+};
+
&lradc {
vref-supply = <®_vcc3v0>;
status = "okay";
status = "okay";
};
+&codec {
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <®_dcdc2>;
};
--- /dev/null
+/*
+ * Copyright 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Dserve DSRV9703C";
+ compatible = "dserve,dsrv9703c", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bl_en_pin_dsrv9703c>;
+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <8>;
+ enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ haptics {
+ compatible = "regulator-haptic";
+ haptic-supply = <®_motor>;
+ min-microvolt = <3000000>;
+ max-microvolt = <3000000>;
+ };
+
+ reg_motor: reg_motor {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&motor_pins>;
+ regulator-name = "vcc-motor";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ enable-active-high;
+ gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
+ };
+};
+
+&codec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&codec_pa_pin>;
+ allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ /* pull-ups and devices require AXP209 LDO3 */
+ status = "failed";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+
+ ft5406ee8: touchscreen@38 {
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+ reset-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>;
+ touchscreen-size-x = <1024>;
+ touchscreen-size-y = <768>;
+ };
+};
+
+&lradc {
+ vref-supply = <®_ldo2>;
+ status = "okay";
+
+ button@400 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+
+ button@800 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <800000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ bl_en_pin_dsrv9703c: bl_en_pin@0 {
+ allwinner,pins = "PH7";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ codec_pa_pin: codec_pa_pin@0 {
+ allwinner,pins = "PH15";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ motor_pins: motor_pins@0 {
+ allwinner,pins = "PB3";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ touchscreen_pins: touchscreen_pins@0 {
+ allwinner,pins = "PB13";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = "PH5";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins_a>;
+ status = "okay";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb0_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Gemei G9 Tablet";
/*
* TODO:
* 2x cameras via CSI
- * bma250 IRQs
* AXP battery management
* NAND
* OTG
* Touchscreen - gt801_2plus1 @ i2c adapter 2 @ 0x48
*/
+&codec {
+ /* PH15 controls power to external amplifier (ft2012q) */
+ pinctrl-names = "default";
+ pinctrl-0 = <&codec_pa_pin>;
+ allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
&ehci0 {
status = "okay";
status = "okay";
axp209: pmic@34 {
- compatible = "x-powers,axp209";
reg = <0x34>;
interrupts = <0>;
-
- interrupt-controller;
- #interrupt-cells = <1>;
};
};
+#include "axp209.dtsi"
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
bma250@18 {
compatible = "bosch,bma250";
reg = <0x18>;
-
- /*
- * TODO: interrupt pins:
- * int1 - PH00
- * int2 - PI10
- */
+ interrupt-parent = <&pio>;
+ interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH00 / EINT0 */
};
};
&lradc {
- vref-supply = <®_vcc3v0>;
+ vref-supply = <®_ldo2>;
status = "okay";
status = "okay";
};
+&pio {
+ codec_pa_pin: codec_pa_pin@0 {
+ allwinner,pins = "PH15";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
®_usb1_vbus {
status = "okay";
};
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/pwm/pwm.h>
/ {
model = "iNet-1";
serial0 = &uart0;
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bl_en_pin_inet>;
+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <8>;
+ enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
};
+&codec {
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <®_dcdc2>;
};
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
+
+ ft5x: touchscreen@38 {
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_wake_pin>;
+ wake-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* PB13 */
+ touchscreen-size-x = <600>;
+ touchscreen-size-y = <1024>;
+ touchscreen-swapped-x-y;
+ };
};
&lradc {
};
&pio {
+ bl_en_pin_inet: bl_en_pin@0 {
+ allwinner,pins = "PH7";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ touchscreen_wake_pin: touchscreen_wake_pin@0 {
+ allwinner,pins = "PB13";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
usb0_id_detect_pin: usb0_id_detect_pin@0 {
allwinner,pins = "PH4";
allwinner,function = "gpio_in";
};
};
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins_a>;
+ status = "okay";
+};
+
®_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "INet-97F Rev 02";
};
};
-&ehci0 {
- status = "okay";
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
};
&ehci1 {
status = "okay";
axp209: pmic@34 {
- compatible = "x-powers,axp209";
reg = <0x34>;
interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+
+ ft5406ee8: touchscreen@38 {
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>;
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ };
+};
+
+&lradc {
+ vref-supply = <®_ldo2>;
+ status = "okay";
+
+ button@200 {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button@600 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <600000>;
+ };
- interrupt-controller;
- #interrupt-cells = <1>;
+ button@800 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <800000>;
+ };
+
+ button@1000 {
+ label = "Home";
+ linux,code = <KEY_HOMEPAGE>;
+ channel = <0>;
+ voltage = <1000000>;
+ };
+
+ button@1200 {
+ label = "Esc";
+ linux,code = <KEY_ESC>;
+ channel = <0>;
+ voltage = <1200000>;
};
};
status = "okay";
};
-&ohci0 {
+&otg_sram {
status = "okay";
};
-&ohci1 {
- status = "okay";
+&pio {
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = "PH5";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ };
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
};
-®_usb1_vbus {
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb0_vbus {
status = "okay";
};
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&usbphy {
- usb1_vbus-supply = <®_usb1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_vbus-supply = <®_usb0_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
};
chosen {
stdout-path = "serial0:115200n8";
};
+
+ gpio_keys {
+ compatible = "gpio-keys-polled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_pins_inet9f>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <20>;
+
+ button@0 {
+ label = "Left Joystick Left";
+ linux,code = <ABS_X>;
+ linux,input-type = <EV_ABS>;
+ linux,input-value = <0xffffffff>; /* -1 */
+ gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */
+ };
+
+ button@1 {
+ label = "Left Joystick Right";
+ linux,code = <ABS_X>;
+ linux,input-type = <EV_ABS>;
+ linux,input-value = <1>;
+ gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */
+ };
+
+ button@2 {
+ label = "Left Joystick Up";
+ linux,code = <ABS_Y>;
+ linux,input-type = <EV_ABS>;
+ linux,input-value = <0xffffffff>; /* -1 */
+ gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
+ };
+
+ button@3 {
+ label = "Left Joystick Down";
+ linux,code = <ABS_Y>;
+ linux,input-type = <EV_ABS>;
+ linux,input-value = <1>;
+ gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
+ };
+
+ button@4 {
+ label = "Right Joystick Left";
+ linux,code = <ABS_Z>;
+ linux,input-type = <EV_ABS>;
+ linux,input-value = <0xffffffff>; /* -1 */
+ gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */
+ };
+
+ button@5 {
+ label = "Right Joystick Right";
+ linux,code = <ABS_Z>;
+ linux,input-type = <EV_ABS>;
+ linux,input-value = <1>;
+ gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */
+ };
+
+ button@6 {
+ label = "Right Joystick Up";
+ linux,code = <ABS_RZ>;
+ linux,input-type = <EV_ABS>;
+ linux,input-value = <0xffffffff>; /* -1 */
+ gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */
+ };
+
+ button@7 {
+ label = "Right Joystick Down";
+ linux,code = <ABS_RZ>;
+ linux,input-type = <EV_ABS>;
+ linux,input-value = <1>;
+ gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
+ };
+
+ button@8 {
+ label = "DPad Left";
+ linux,code = <ABS_HAT0X>;
+ linux,input-type = <EV_ABS>;
+ linux,input-value = <0xffffffff>; /* -1 */
+ gpios = <&pio 7 23 GPIO_ACTIVE_LOW>; /* PH23 */
+ };
+
+ button@9 {
+ label = "DPad Right";
+ linux,code = <ABS_HAT0X>;
+ linux,input-type = <EV_ABS>;
+ linux,input-value = <1>;
+ gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */
+ };
+
+ button@10 {
+ label = "DPad Up";
+ linux,code = <ABS_HAT0Y>;
+ linux,input-type = <EV_ABS>;
+ linux,input-value = <0xffffffff>; /* -1 */
+ gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */
+ };
+
+ button@11 {
+ label = "DPad Down";
+ linux,code = <ABS_HAT0Y>;
+ linux,input-type = <EV_ABS>;
+ linux,input-value = <1>;
+ gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */
+ };
+
+ button@12 {
+ label = "Button X";
+ linux,code = <BTN_X>;
+ gpios = <&pio 0 16 GPIO_ACTIVE_LOW>; /* PA16 */
+ };
+
+ button@13 {
+ label = "Button Y";
+ linux,code = <BTN_Y>;
+ gpios = <&pio 0 14 GPIO_ACTIVE_LOW>; /* PA14 */
+ };
+
+ button@14 {
+ label = "Button A";
+ linux,code = <BTN_A>;
+ gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */
+ };
+
+ button@15 {
+ label = "Button B";
+ linux,code = <BTN_B>;
+ gpios = <&pio 0 15 GPIO_ACTIVE_LOW>; /* PA15 */
+ };
+
+ button@16 {
+ label = "Select Button";
+ linux,code = <BTN_SELECT>;
+ gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */
+ };
+
+ button@17 {
+ label = "Start Button";
+ linux,code = <BTN_START>;
+ gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */
+ };
+
+ button@18 {
+ label = "Top Left Button";
+ linux,code = <BTN_TL>;
+ gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
+ };
+
+ button@19 {
+ label = "Top Right Button";
+ linux,code = <BTN_TR>;
+ gpios = <&pio 0 13 GPIO_ACTIVE_LOW>; /* PA13 */
+ };
+ };
};
&cpu0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
+
+ /* Accelerometer */
+ bma250@18 {
+ compatible = "bosch,bma250";
+ reg = <0x18>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */
+ };
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
+
+ ft5406ee8: touchscreen@38 {
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>;
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ };
};
&lradc {
};
&pio {
+ key_pins_inet9f: key_pins@0 {
+ allwinner,pins = "PA0", "PA1", "PA3", "PA4",
+ "PA5", "PA6", "PA8", "PA9",
+ "PA11", "PA12", "PA13",
+ "PA14", "PA15", "PA16", "PA17",
+ "PH22", "PH23", "PH24", "PH25", "PH26";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
usb0_id_detect_pin: usb0_id_detect_pin@0 {
allwinner,pins = "PH4";
allwinner,function = "gpio_in";
/*
* Copyright 2015 Josef Gajdusek <atx@atx.name>
+ * Copyright 2015 - Marcus Cooper <codekipper@gmail.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
/dts-v1/;
#include "sun4i-a10.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include "sunxi-itead-core-common.dtsi"
/ {
model = "Iteaduino Plus A10";
compatible = "itead,iteaduino-plus-a10", "allwinner,sun4i-a10";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
};
&ahci {
status = "okay";
};
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_pins_a>;
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
- status = "okay";
-
axp209: pmic@34 {
- reg = <0x34>;
interrupts = <0>;
};
};
status = "okay";
};
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
®_ahci_5v {
status = "okay";
};
-#include "axp209.dtsi"
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1450000>;
- regulator-name = "vdd-cpu";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1400000>;
- regulator-name = "vdd-int-dll";
-};
-
-®_ldo1 {
- regulator-name = "vdd-rtc";
-};
-
-®_ldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-name = "avcc";
-};
-
-®_usb1_vbus {
- status = "okay";
-};
-
-®_usb2_vbus {
- status = "okay";
-};
-
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins_a>,
<&spi0_cs0_pins_a>;
status = "okay";
};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
- status = "okay";
-};
-
-&usbphy {
- usb1_vbus-supply = <®_usb1_vbus>;
- usb2_vbus-supply = <®_usb2_vbus>;
- status = "okay";
-};
status = "okay";
};
+&otg_sram {
+ status = "okay";
+};
+
&pio {
emac_power_pin_q5: emac_power_pin@0 {
allwinner,pins = "PH19";
};
};
+®_usb0_vbus {
+ regulator-boot-on;
+ status = "okay";
+};
+
®_usb1_vbus {
status = "okay";
};
status = "okay";
};
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
&usbphy {
+ usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
status = "okay";
};
+&codec {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
status = "okay";
};
+&otg_sram {
+ status = "okay";
+};
+
&pio {
led_pins_marsboard: led_pins@0 {
allwinner,pins = "PB5", "PB6", "PB7", "PB8";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
};
®_usb1_vbus {
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
#include "sun4i-a10.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "MK802";
};
};
+&codec {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
status = "okay";
};
+&otg_sram {
+ status = "okay";
+};
+
&pio {
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = "PH5";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
usb2_vbus_pin_mk802: usb2_vbus_pin@0 {
allwinner,pins = "PH12";
allwinner,function = "gpio_out";
};
};
+®_usb0_vbus {
+ status = "okay";
+};
+
®_usb1_vbus {
status = "okay";
};
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+ usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
};
};
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
&mdio {
status = "okay";
};
};
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
&ehci0 {
status = "okay";
};
status = "okay";
axp209: pmic@34 {
- compatible = "x-powers,axp209";
reg = <0x34>;
interrupts = <0>;
-
- interrupt-controller;
- #interrupt-cells = <1>;
};
};
status = "okay";
};
+&otg_sram {
+ status = "okay";
+};
+
&pio {
led_pins_pcduino: led_pins@0 {
allwinner,pins = "PH15", "PH16";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
};
-®_usb1_vbus {
- status = "okay";
+#include "axp209.dtsi"
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
};
-®_usb2_vbus {
- status = "okay";
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
};
&uart0 {
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&usbphy {
- usb1_vbus-supply = <®_usb1_vbus>;
- usb2_vbus-supply = <®_usb2_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */
+ usb2_vbus-supply = <®_vcc5v0>; /* USB2 VBUS is always on */
status = "okay";
};
--- /dev/null
+/*
+ * Copyright 2015 Siarhei Siamashka <siarhei.siamashka@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * The LinkSprite pcDuino2 board is almost identical to the older
+ * LinkSprite pcDuino1 board. The only software visible difference
+ * is that the pcDuino2 board got a USB VBUS voltage regulator, which
+ * is controlled by the PD2 pin (pulled-up by default). Also one of
+ * the USB host ports has been replaced with a USB WIFI chip.
+ */
+
+#include "sun4i-a10-pcduino.dts"
+
+/ {
+ model = "LinkSprite pcDuino2";
+ compatible = "linksprite,a10-pcduino2", "allwinner,sun4i-a10";
+};
+
+&pio {
+ usb2_vbus_pin_pcduino2: usb2_vbus_pin@0 {
+ allwinner,pins = "PD2";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb2_vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_vbus_pin_pcduino2>;
+ gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_vcc3v3>; /* USB WIFI is always on */
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/pwm/pwm.h>
/ {
model = "Point of View Protab2-IPS9";
serial0 = &uart0;
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bl_en_pin_protab>;
+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <8>;
+ enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
};
+&codec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&codec_pa_pin>;
+ allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <®_dcdc2>;
};
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
+
+ /* Accelerometer */
+ bma250@18 {
+ compatible = "bosch,bma250";
+ reg = <0x18>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */
+ };
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
+
+ pixcir_ts@5c {
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+ compatible = "pixcir,pixcir_tangoc";
+ reg = <0x5c>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; /* EINT21 (PH21) */
+ attb-gpio = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* PH21 */
+ enable-gpios = <&pio 0 5 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>;
+ touchscreen-size-x = <1024>;
+ touchscreen-size-y = <768>;
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ };
};
&lradc {
};
&pio {
+ bl_en_pin_protab: bl_en_pin@0 {
+ allwinner,pins = "PH7";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ codec_pa_pin: codec_pa_pin@0 {
+ allwinner,pins = "PH15";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ touchscreen_pins: touchscreen_pins@0 {
+ allwinner,pins = "PA5", "PB13";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
usb0_id_detect_pin: usb0_id_detect_pin@0 {
allwinner,pins = "PH4";
allwinner,function = "gpio_in";
};
};
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins_a>;
+ status = "okay";
+};
+
®_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/clock/sun4i-a10-pll2.h>
#include <dt-bindings/dma/sun4i-a10.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
- <&ahb_gates 44>;
+ <&ahb_gates 44>, <&dram_gates 26>;
status = "disabled";
};
"simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
- <&ahb_gates 44>, <&ahb_gates 46>;
+ <&ahb_gates 44>, <&ahb_gates 46>,
+ <&dram_gates 25>, <&dram_gates 26>;
status = "disabled";
};
"simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0";
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
- <&ahb_gates 46>;
+ <&ahb_gates 46>, <&dram_gates 25>,
+ <&dram_gates 26>;
status = "disabled";
};
"simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
- <&ahb_gates 44>, <&ahb_gates 46>;
+ <&ahb_gates 44>, <&ahb_gates 46>,
+ <&dram_gates 25>, <&dram_gates 26>;
status = "disabled";
};
};
clock-output-names = "pll1";
};
+ pll2: clk@01c20008 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-pll2-clk";
+ reg = <0x01c20008 0x8>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll2-1x", "pll2-2x",
+ "pll2-4x", "pll2-8x";
+ };
+
pll4: clk@01c20018 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-pll1-clk";
compatible = "allwinner,sun4i-a10-axi-gates-clk";
reg = <0x01c2005c 0x4>;
clocks = <&axi>;
+ clock-indices = <0>;
clock-output-names = "axi_dram";
};
compatible = "allwinner,sun4i-a10-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <3>,
+ <4>, <5>, <6>,
+ <7>, <8>, <9>,
+ <10>, <11>, <12>,
+ <13>, <14>, <16>,
+ <17>, <18>, <20>,
+ <21>, <22>, <23>,
+ <24>, <25>, <26>,
+ <32>, <33>, <34>,
+ <35>, <36>, <37>,
+ <40>, <41>, <43>,
+ <44>, <45>,
+ <46>, <47>,
+ <50>, <52>;
clock-output-names = "ahb_usb0", "ahb_ehci0",
- "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
- "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
- "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
- "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
- "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
- "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
- "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
- "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
- "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
- "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+ "ahb_ohci0", "ahb_ehci1",
+ "ahb_ohci1", "ahb_ss", "ahb_dma",
+ "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+ "ahb_mmc2", "ahb_mmc3", "ahb_ms",
+ "ahb_nand", "ahb_sdram", "ahb_ace",
+ "ahb_emac", "ahb_ts", "ahb_spi0",
+ "ahb_spi1", "ahb_spi2", "ahb_spi3",
+ "ahb_pata", "ahb_sata", "ahb_gps",
+ "ahb_ve", "ahb_tvd", "ahb_tve0",
+ "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
+ "ahb_csi0", "ahb_csi1", "ahb_hdmi",
+ "ahb_de_be0", "ahb_de_be1",
+ "ahb_de_fe0", "ahb_de_fe1",
+ "ahb_mp", "ahb_mali400";
};
apb0: apb0@01c20054 {
compatible = "allwinner,sun4i-a10-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <1>,
+ <2>, <3>,
+ <5>, <6>,
+ <7>, <10>;
clock-output-names = "apb0_codec", "apb0_spdif",
- "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
- "apb0_ir1", "apb0_keypad";
+ "apb0_ac97", "apb0_iis",
+ "apb0_pio", "apb0_ir0",
+ "apb0_ir1", "apb0_keypad";
};
apb1: clk@01c20058 {
compatible = "allwinner,sun4i-a10-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <4>,
+ <5>, <6>,
+ <7>, <16>,
+ <17>, <18>,
+ <19>, <20>,
+ <21>, <22>,
+ <23>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_can", "apb1_scr",
- "apb1_ps20", "apb1_ps21", "apb1_uart0",
- "apb1_uart1", "apb1_uart2", "apb1_uart3",
- "apb1_uart4", "apb1_uart5", "apb1_uart6",
- "apb1_uart7";
+ "apb1_i2c2", "apb1_can",
+ "apb1_scr", "apb1_ps20",
+ "apb1_ps21", "apb1_uart0",
+ "apb1_uart1", "apb1_uart2",
+ "apb1_uart3", "apb1_uart4",
+ "apb1_uart5", "apb1_uart6",
+ "apb1_uart7";
};
nand_clk: clk@01c20080 {
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi3";
};
+
+ dram_gates: clk@01c20100 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-dram-gates-clk";
+ reg = <0x01c20100 0x4>;
+ clocks = <&pll5 0>;
+ clock-indices = <0>,
+ <1>, <2>,
+ <3>,
+ <4>,
+ <5>, <6>,
+ <15>,
+ <24>, <25>,
+ <26>, <27>,
+ <28>, <29>;
+ clock-output-names = "dram_ve",
+ "dram_csi0", "dram_csi1",
+ "dram_ts",
+ "dram_tvd",
+ "dram_tve0", "dram_tve1",
+ "dram_output",
+ "dram_de_fe1", "dram_de_fe0",
+ "dram_de_be0", "dram_de_be1",
+ "dram_de_mp", "dram_ace";
+ };
+
+ ve_clk: clk@01c2013c {
+ #clock-cells = <0>;
+ #reset-cells = <0>;
+ compatible = "allwinner,sun4i-a10-ve-clk";
+ reg = <0x01c2013c 0x4>;
+ clocks = <&pll4>;
+ clock-output-names = "ve";
+ };
+
+ codec_clk: clk@01c20140 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-codec-clk";
+ reg = <0x01c20140 0x4>;
+ clocks = <&pll2 SUN4I_A10_PLL2_1X>;
+ clock-output-names = "codec";
+ };
};
soc@01c00000 {
status = "disabled";
};
+ crypto: crypto-engine@01c15000 {
+ compatible = "allwinner,sun4i-a10-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <86>;
+ clocks = <&ahb_gates 5>, <&ss_clk>;
+ clock-names = "ahb", "mod";
+ };
+
spi2: spi@01c17000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c17000 0x1000>;
status = "disabled";
};
+ codec: codec@01c22c00 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun4i-a10-codec";
+ reg = <0x01c22c00 0x40>;
+ interrupts = <30>;
+ clocks = <&apb0_gates 0>, <&codec_clk>;
+ clock-names = "apb", "codec";
+ dmas = <&dma SUN4I_DMA_NORMAL 19>,
+ <&dma SUN4I_DMA_NORMAL 19>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
sid: eeprom@01c23800 {
compatible = "allwinner,sun4i-a10-sid";
reg = <0x01c23800 0x10>;
status = "okay";
};
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp152: pmic@30 {
+ compatible = "x-powers,axp152";
+ reg = <0x30>;
+ interrupts = <0>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t004>;
status = "okay";
at24@50 {
- compatible = "at,24c16";
+ compatible = "atmel,24c16";
pagesize = <16>;
reg = <0x50>;
read-only;
--- /dev/null
+/*
+ * Copyright 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-a13.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Difrnce DIT4350";
+ compatible = "difrnce,dit4350", "allwinner,sun5i-a13";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <8>;
+ /* TODO: backlight uses axp gpio1 as enable pin */
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&lradc {
+ vref-supply = <®_ldo2>;
+ status = "okay";
+
+ button@200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button@400 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
+ cd-inverted;
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_d709: mmc0_cd_pin@0 {
+ allwinner,pins = "PG0";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = "PG1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ };
+
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PG2";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins>;
+ status = "okay";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd-int-pll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_ldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+®_usb0_vbus {
+ gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_b>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb0_vbus_pin_a {
+ allwinner,pins = "PG12";
+};
+
+&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+ usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+ usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ usb1_vbus-supply = <®_ldo3>;
+ status = "okay";
+};
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_inet98fv2>;
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
status = "okay";
};
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins_a>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-
- mmccard: mmccard@0 {
- reg = <0>;
- compatible = "mmc-card";
- broken-hpi;
- };
-};
-
&otg_sram {
status = "okay";
};
&pio {
- mmc0_cd_pin_inet98fv2: mmc0_cd_pin@0 {
+ mmc0_cd_pin_d709: mmc0_cd_pin@0 {
allwinner,pins = "PG0";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
status = "okay";
};
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins_a>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-
- mmccard: mmccard@0 {
- reg = <0>;
- compatible = "mmc-card";
- broken-hpi;
- };
-};
-
&otg_sram {
status = "okay";
};
status = "okay";
};
-®_usb1_vbus {
- gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
- status = "okay";
-};
-
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_b>;
allwinner,pins = "PG12";
};
-&usb1_vbus_pin_a {
- allwinner,pins = "PG11";
-};
-
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
usb0_vbus-supply = <®_usb0_vbus>;
- usb1_vbus-supply = <®_usb1_vbus>;
+ usb1_vbus-supply = <®_ldo3>;
status = "okay";
};
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/pwm/pwm.h>
/ {
model = "Utoo P66";
compatible = "utoo,p66", "allwinner,sun5i-a13";
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ /* Note levels of 10 / 20% result in backlight off */
+ brightness-levels = <0 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <6>;
+ /* TODO: backlight uses axp gpio1 as enable pin */
+ };
+
i2c_lcd: i2c@0 {
/* The lcd panel i2c interface is hooked up via gpios */
compatible = "i2c-gpio";
};
};
+&codec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&codec_pa_pin>;
+ allwinner,pa-gpios = <&pio 6 3 GPIO_ACTIVE_HIGH>; /* PG3 */
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <®_dcdc2>;
};
};
&pio {
+ codec_pa_pin: codec_pa_pin@0 {
+ allwinner,pins = "PG3";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
mmc0_cd_pin_p66: mmc0_cd_pin@0 {
allwinner,pins = "PG0";
allwinner,function = "gpio_in";
};
};
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins>;
+ status = "okay";
+};
+
®_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
*/
#include "sunxi-q8-common.dtsi"
+#include <dt-bindings/pwm/pwm.h>
+
/ {
aliases {
serial0 = &uart1;
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <8>;
+ /* TODO: backlight uses axp gpio1 as enable pin */
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
chosen {
stdout-path = "serial0:115200n8";
};
+
+ wifi_reg_on: wifi_reg_on {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&chip_wifi_reg_on_pin>;
+
+ regulator-name = "wifi-reg-on";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pio 2 19 GPIO_ACTIVE_HIGH>; /* PC19 */
+ enable-active-high;
+ };
+};
+
+&codec {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
};
&ehci0 {
};
};
+&mmc0_pins_a {
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>;
- vmmc-supply = <®_vcc3v3>;
+ vmmc-supply = <&wifi_reg_on>;
bus-width = <4>;
non-removable;
status = "okay";
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ chip_wifi_reg_on_pin: chip_wifi_reg_on_pin@0 {
+ allwinner,pins = "PC19";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
chip_id_det_pin: chip_id_det_pin@0 {
allwinner,pins = "PG2";
allwinner,function = "gpio_in";
regulator-always-on;
};
+®_ldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vdd-wifi1";
+ regulator-always-on;
+};
+
+®_ldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vdd-wifi2";
+ regulator-always-on;
+};
+
®_ldo5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
#include "skeleton.dtsi"
+#include <dt-bindings/clock/sun4i-a10-pll2.h>
#include <dt-bindings/dma/sun4i-a10.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
clock-output-names = "pll1";
};
+ pll2: clk@01c20008 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun5i-a13-pll2-clk";
+ reg = <0x01c20008 0x8>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll2-1x", "pll2-2x",
+ "pll2-4x", "pll2-8x";
+ };
+
pll4: clk@01c20018 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-pll1-clk";
clock-output-names = "usb_ohci0", "usb_phy";
};
+ codec_clk: clk@01c20140 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-codec-clk";
+ reg = <0x01c20140 0x4>;
+ clocks = <&pll2 SUN4I_A10_PLL2_1X>;
+ clock-output-names = "codec";
+ };
+
mbus_clk: clk@01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun5i-a13-mbus-clk";
status = "disabled";
};
+ codec: codec@01c22c00 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun4i-a10-codec";
+ reg = <0x01c22c00 0x40>;
+ interrupts = <30>;
+ clocks = <&apb0_gates 0>, <&codec_clk>;
+ clock-names = "apb", "codec";
+ dmas = <&dma SUN4I_DMA_NORMAL 19>,
+ <&dma SUN4I_DMA_NORMAL 19>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
sid: eeprom@01c23800 {
compatible = "allwinner,sun4i-a10-sid";
reg = <0x01c23800 0x10>;
chosen {
stdout-path = "serial0:115200n8";
};
+
+ i2c_lcd: i2c@0 {
+ /* The lcd panel i2c interface is hooked up via gpios */
+ compatible = "i2c-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_lcd_pins>;
+ gpios = <&pio 0 23 GPIO_ACTIVE_HIGH>, /* PA23, sda */
+ <&pio 0 24 GPIO_ACTIVE_HIGH>; /* PA24, scl */
+ i2c-gpio,delay-us = <5>;
+ };
};
&ehci1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
+
+ mma8452: mma8452@1d {
+ compatible = "fsl,mma8452";
+ reg = <0x1d>;
+ interrupt-parent = <&pio>;
+ interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PA9 */
+ };
};
&mmc0 {
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+
+ i2c_lcd_pins: i2c_lcd_pin@0 {
+ allwinner,pins = "PA23", "PA24";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
};
®_usb2_vbus {
compatible = "merrii,a31-hummingbird", "allwinner,sun6i-a31";
aliases {
+ rtc0 = &pcf8563;
+ rtc1 = &rtc;
serial0 = &uart0;
};
};
};
+&cpu0 {
+ cpu-supply = <®_dcdc3>;
+};
+
&ehci0 {
status = "okay";
};
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>;
+ pinctrl-0 = <&gmac_pins_rgmii_a>, <&gmac_phy_reset_pin_hummingbird>;
phy = <&phy1>;
phy-mode = "rgmii";
snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>;
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>;
- vmmc-supply = <&vcc_3v0>;
+ vmmc-supply = <®_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
cd-inverted;
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>, <&wifi_reset_pin_hummingbird>;
- vmmc-supply = <&vcc_wifi>;
+ vmmc-supply = <®_aldo1>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
};
&pio {
+ gmac_phy_reset_pin_hummingbird: gmac_phy_reset_pin@0 {
+ allwinner,pins = "PA21";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
mmc0_cd_pin_hummingbird: mmc0_cd_pin@0 {
allwinner,pins = "PA8";
allwinner,function = "gpio_in";
&p2wi {
status = "okay";
- axp221: pmic@68 {
+ axp22x: pmic@68 {
compatible = "x-powers,axp221";
reg = <0x68>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
- #interrupt-cells = <1>;
- dcdc1-supply = <&vcc_3v0>;
- dcdc5-supply = <&vcc_dram>;
-
- regulators {
- x-powers,dcdc-freq = <3000>;
-
- vcc_3v0: dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-name = "vcc-3v0";
- };
-
- vdd_cpu: dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1320000>;
- regulator-name = "vdd-cpu";
- };
-
- vdd_gpu: dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1320000>;
- regulator-name = "vdd-gpu";
- };
-
- vdd_sys_dll: dcdc4 {
- regulator-always-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-name = "vdd-sys-dll";
- };
-
- vcc_dram: dcdc5 {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc-dram";
- };
-
- vcc_wifi: aldo1 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_wifi";
- };
-
- avcc: aldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-name = "avcc";
- };
- };
};
};
+#include "axp22x.dtsi"
+
+®_aldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "avcc";
+};
+
+®_dc5ldo {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-cpus";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v0";
+};
+
+®_dcdc2 {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-gpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc4 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-sys-dll";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
®_usb1_vbus {
gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */
status = "okay";
#size-cells = <1>;
ranges;
- framebuffer@0 {
+ simplefb_hdmi: framebuffer@0 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
status = "disabled";
};
- framebuffer@1 {
+ simplefb_lcd: framebuffer@1 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb1>;
+ clock-indices = <1>, <5>,
+ <6>, <8>, <9>,
+ <10>, <11>, <12>,
+ <13>, <14>,
+ <17>, <18>, <19>,
+ <20>, <21>, <22>,
+ <23>, <24>, <26>,
+ <27>, <29>,
+ <30>, <31>, <32>,
+ <36>, <37>, <40>,
+ <43>, <44>, <45>,
+ <46>, <47>, <50>,
+ <52>, <55>, <56>,
+ <57>, <58>;
clock-output-names = "ahb1_mipidsi", "ahb1_ss",
"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
compatible = "allwinner,sun6i-a31-apb1-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <4>,
+ <5>, <12>,
+ <13>;
clock-output-names = "apb1_codec", "apb1_digital_mic",
"apb1_pio", "apb1_daudio0",
"apb1_daudio1";
compatible = "allwinner,sun6i-a31-apb2-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb2>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <16>,
+ <17>, <18>, <19>,
+ <20>, <21>;
clock-output-names = "apb2_i2c0", "apb2_i2c1",
"apb2_i2c2", "apb2_i2c3",
"apb2_uart0", "apb2_uart1",
"mmc3_sample";
};
+ ss_clk: clk@01c2009c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2009c 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "ss";
+ };
+
spi0_clk: clk@01c200a0 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
compatible = "allwinner,sun6i-a31-usb-clk";
reg = <0x01c200cc 0x4>;
clocks = <&osc24M>;
+ clock-indices = <8>, <9>, <10>,
+ <16>, <17>,
+ <18>;
clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
"usb_ohci0", "usb_ohci1",
"usb_ohci2";
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ mmc3_8bit_emmc_pins: mmc3@1 {
+ allwinner,pins = "PC6", "PC7", "PC8", "PC9",
+ "PC10", "PC11", "PC12",
+ "PC13", "PC14", "PC15",
+ "PC24";
+ allwinner,function = "mmc3";
+ allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
gmac_pins_mii_a: gmac_mii@0 {
allwinner,pins = "PA0", "PA1", "PA2", "PA3",
"PA8", "PA9", "PA11",
reg = <0x01c20ca0 0x20>;
};
+ lradc: lradc@01c22800 {
+ compatible = "allwinner,sun4i-a10-lradc-keys";
+ reg = <0x01c22800 0x100>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
rtp: rtp@01c25000 {
compatible = "allwinner,sun6i-a31-ts";
reg = <0x01c25000 0x100>;
#size-cells = <0>;
};
+ crypto: crypto-engine@01c15000 {
+ compatible = "allwinner,sun4i-a10-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb1_gates 5>, <&ss_clk>;
+ clock-names = "ahb", "mod";
+ resets = <&ahb1_rst 5>;
+ reset-names = "ahb";
+ };
+
timer@01c60000 {
compatible = "allwinner,sun6i-a31-hstimer",
"allwinner,sun7i-a20-hstimer";
resets = <&apb0_rst 0>;
gpio-controller;
interrupt-controller;
- #interrupt-cells = <2>;
+ #interrupt-cells = <3>;
#size-cells = <0>;
#gpio-cells = <3>;
--- /dev/null
+/*
+ * Copyright 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun6i-a31s.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Colorfly E708 Q1 tablet";
+ compatible = "colorfly,e708-q1", "allwinner,sun6i-a31s";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc3>;
+};
+
+&ehci0 {
+ /* rtl8188etv wifi is connected here */
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <®_aldo3>;
+ status = "okay";
+
+ button@1000 {
+ label = "Home";
+ linux,code = <KEY_HOMEPAGE>;
+ channel = <0>;
+ voltage = <1000000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>;
+ vmmc-supply = <®_dcdc1>;
+ bus-width = <4>;
+ cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
+ cd-inverted;
+ status = "okay";
+};
+
+&pio {
+ mma8452_int_e708_q1: mma8452_int_pin@0 {
+ allwinner,pins = "PA9";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ mmc0_cd_pin_e708_q1: mmc0_cd_pin@0 {
+ allwinner,pins = "PA8";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+};
+
+&p2wi {
+ status = "okay";
+
+ axp22x: pmic@68 {
+ compatible = "x-powers,axp221";
+ reg = <0x68>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp22x.dtsi"
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-lcd";
+};
+
+®_dc5ldo {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-cpus"; /* This is an educated guess */
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v0";
+};
+
+®_dcdc2 {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-gpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc4 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-sys-dll";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+®_dldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg";
+};
+
+&simplefb_lcd {
+ vcc-lcd-supply = <®_dc1sw>;
+ vcc-pg-supply = <®_dldo2>;
+};
+
+/*
+ * FIXME for now we only support host mode and rely on u-boot to have
+ * turned on Vbus which is controlled by the axp221 pmic on the board.
+ *
+ * Once we have axp221 power-supply and vbus-usb support we should switch
+ * to fully supporting otg.
+ */
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_dldo1>;
+ status = "okay";
+};
/*
- * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ * Copyright 2014 Siarhei Siamashka <siarhei.siamashka@gmail.com>
+ * Copyright 2015 Karsten Merker <merker@debian.org>
+ * Copyright 2015 Chen-Yu Tsai <wens@csie.org>
*
- * Minimal dts file for the MSI Primo81 for u-boot only
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
*
- * SPDX-License-Identifier: GPL-2.0+ or X11
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun6i-a31s.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
- model = "MSI Primo81";
+ model = "MSI Primo81 tablet";
compatible = "msi,primo81", "allwinner,sun6i-a31s";
aliases {
};
};
-&uart0 {
+&cpu0 {
+ cpu-supply = <®_dcdc3>;
+};
+
+&ehci0 {
+ /* rtl8188etv wifi is connected here */
+ status = "okay";
+};
+
+&i2c0 {
+ /* pull-ups and device VDDIO use AXP221 DLDO3 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "failed";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+
+ ctp@5d {
+ pinctrl-names = "default";
+ pinctrl-0 = <>911_int_primo81>;
+ compatible = "goodix,gt911";
+ reg = <0x5d>;
+ interrupt-parent = <&pio>;
+ interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; /* PA3 */
+ touchscreen-swapped-x-y;
+ };
+};
+
+&i2c2 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+
+ accelerometer@1c {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mma8452_int_primo81>;
+ compatible = "fsl,mma8452";
+ reg = <0x1c>;
+ interrupt-parent = <&pio>;
+ interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; /* PA9 */
+ #io-channel-cells = <1>;
+ };
+};
+
+&lradc {
+ vref-supply = <®_aldo3>;
+ status = "okay";
+
+ button@158 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <158730>;
+ };
+
+ button@349 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <349206>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_primo81>;
+ vmmc-supply = <®_dcdc1>;
+ bus-width = <4>;
+ cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
+ cd-inverted;
+ status = "okay";
+};
+
+&pio {
+ gt911_int_primo81: gt911_int_pin@0 {
+ allwinner,pins = "PA3";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mma8452_int_primo81: mma8452_int_pin@0 {
+ allwinner,pins = "PA9";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ mmc0_cd_pin_primo81: mmc0_cd_pin@0 {
+ allwinner,pins = "PA8";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+};
+
+&p2wi {
+ status = "okay";
+
+ axp22x: pmic@68 {
+ compatible = "x-powers,axp221";
+ reg = <0x68>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp22x.dtsi"
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "avcc";
+};
+
+®_dc1sw {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-lcd";
+};
+
+®_dc5ldo {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-cpus"; /* This is an educated guess */
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v0";
+};
+
+®_dcdc2 {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-gpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc4 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-sys-dll";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+®_dldo3 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vddio-csi";
+};
+
+®_eldo3 {
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-mipi-bridge";
+};
+
+&simplefb_lcd {
+ vcc-lcd-supply = <®_dc1sw>;
+ vdd-mipi-bridge-supply = <®_eldo3>;
+};
+
+&usb_otg {
+ /* otg support requires support for AXP221 usb-power-supply and GPIO */
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_dldo1>;
status = "okay";
};
--- /dev/null
+/*
+ * Copyright 2015 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun6i-a31s.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Sinlinx SinA31s Core Board";
+ compatible = "sinlinx,sina31s", "allwinner,sun6i-a31s";
+
+ aliases {
+ serial0 = &uart0;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc3>;
+};
+
+/* eMMC on core board */
+&mmc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_8bit_emmc_pins>;
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_dcdc1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+/* AXP221s PMIC on core board */
+&p2wi {
+ status = "okay";
+
+ axp22x: pmic@68 {
+ compatible = "x-powers,axp221";
+ reg = <0x68>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp22x.dtsi"
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "avcc";
+};
+
+®_dc5ldo {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-cpus";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v0";
+};
+
+®_dcdc2 {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-gpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc4 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-sys-dll";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+/* UART0 pads available on core board */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
--- /dev/null
+/*
+ * Copyright 2015 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/* The SinA31s development board has the SinA31s core board soldered on */
+#include "sun6i-a31s-sina31s-core.dtsi"
+
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Sinlinx SinA31s Development Board";
+ compatible = "sinlinx,sina31s-sdk", "allwinner,sun6i-a31s";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pin_sina31s>;
+
+ status {
+ label = "sina31s:status:usr";
+ gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
+ };
+ };
+};
+
+&ehci0 {
+ /* USB 2.0 4 port hub IC */
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_mii_a>;
+ phy = <&phy1>;
+ phy-mode = "mii";
+ phy-supply = <®_dldo1>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <®_aldo3>;
+ status = "okay";
+
+ button@158 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <158730>;
+ };
+
+ button@349 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <349206>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina31s>;
+ vmmc-supply = <®_dcdc1>;
+ bus-width = <4>;
+ cd-gpios = <&pio 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ led_pin_sina31s: led_pin@0 {
+ allwinner,pins = "PH13";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_cd_pin_sina31s: mmc0_cd_pin@0 {
+ allwinner,pins = "PA4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+};
+
+®_dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-gmac-phy";
+};
+
+&usbphy {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Lawrence Yu <lyu@micile.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun6i-a31s.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Yones TopTech BS1078 v2 Tablet";
+ compatible = "yones-toptech,bs1078-v2", "allwinner,sun6i-a31s";
+
+ aliases {
+ serial0 = &uart0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_bs1078v2: mmc0_cd_pin@0 {
+ allwinner,pins = "PA8";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bs1078v2>;
+ vmmc-supply = <®_vcc3v0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc0_pins_a {
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&p2wi {
+ status = "okay";
+
+ axp22x: pmic@68 {
+ compatible = "x-powers,axp221";
+ reg = <0x68>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp22x.dtsi"
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-lcd-usb2";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+};
+
+®_dc5ldo {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-cpus";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v0";
+};
+
+®_dcdc2 {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-gpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc4 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-sys-dll";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+/* Voltage source for I2C pullup resistors for I2C Bus 0 */
+®_dldo3 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vddio-csi";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_dldo1>;
+ usb2_vbus-supply = <®_dc1sw>;
+ status = "okay";
+};
status = "okay";
};
+&codec {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+ operating-points = <
+ /* kHz uV */
+ 960000 1400000
+ 912000 1400000
+ 864000 1350000
+ 720000 1250000
+ 528000 1150000
+ 312000 1100000
+ 144000 1050000
+ >;
+};
+
&ehci0 {
status = "okay";
};
status = "okay";
axp209: pmic@34 {
- compatible = "x-powers,axp209";
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-
- interrupt-controller;
- #interrupt-cells = <1>;
};
};
status = "okay";
};
+&otg_sram {
+ status = "okay";
+};
+
&pio {
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
mmc0_cd_pin_bananapi: mmc0_cd_pin@0 {
allwinner,pins = "PH10";
allwinner,function = "gpio_in";
};
};
+#include "axp209.dtsi"
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb0_vbus {
+ status = "okay";
+};
+
®_usb1_vbus {
status = "okay";
};
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
status = "okay";
};
+&codec {
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <®_dcdc2>;
};
status = "okay";
};
+&otg_sram {
+ status = "okay";
+};
+
&pio {
led_pins_cubieboard2: led_pins@0 {
allwinner,pins = "PH20", "PH21";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
};
®_ahci_5v {
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
#include "axp209.dtsi"
®_dcdc2 {
};
&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
status = "okay";
};
+&codec {
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <®_dcdc2>;
};
--- /dev/null
+/*
+ * Copyright 2015 Stefan Roese <sr@denx.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "ICnova-A20 SWAC";
+ compatible = "swac,icnova-a20-swac", "incircuit,icnova-a20", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_mii_a>;
+ phy = <&phy1>;
+ phy-mode = "mii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 8 5 GPIO_ACTIVE_HIGH>; /* PI5 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+#include "axp209.dtsi"
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 - Marcus Cooper <codekipper@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-itead-core-common.dtsi"
+
+/ {
+ model = "Itead Ibox A20";
+ compatible = "itead,itead-ibox-a20", "allwinner,sun7i-a20";
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_itead_core>;
+
+ green {
+ label = "itead_core:green:usr";
+ gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ blue {
+ label = "itead_core:blue:usr";
+ gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+};
+
+&ahci {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+};
+
+&codec {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_mii_a>;
+ phy = <&phy1>;
+ phy-mode = "mii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ axp209: pmic@34 {
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_rx_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&pio {
+ led_pins_itead_core: led_pins@0 {
+ allwinner,pins = "PH20","PH21";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_ahci_5v {
+ status = "okay";
+};
&cpu0 {
cpu-supply = <®_dcdc2>;
- operating-points = <
- /* kHz uV */
- 960000 1400000
- 912000 1400000
- 864000 1350000
- 720000 1250000
- 528000 1150000
- 312000 1100000
- 144000 1050000
- >;
};
&ehci0 {
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "mk808c";
};
};
+&codec {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
status = "okay";
};
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = "PH5";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb0_vbus {
+ status = "okay";
+};
+
®_usb1_vbus {
status = "okay";
};
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+ usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
/*
* Copyright 2015 - Marcus Cooper <codekipper@gmail.com>
+ * Copyright 2015 - Karsten Merker <merker@debian.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
default-state = "on";
};
};
-
- reg_axp_ipsout: axp_ipsout {
- compatible = "regulator-fixed";
- regulator-name = "axp-ipsout";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
};
&ahci {
status = "okay";
};
+&codec {
+ status = "okay";
+};
+
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_pins_rgmii_a>;
};
};
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
+&lradc {
+ vref-supply = <®_vcc3v0>;
status = "okay";
+
+ button@190 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <190000>;
+ };
+
+ button@390 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <390000>;
+ };
+
+ button@600 {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ channel = <0>;
+ voltage = <600000>;
+ };
+
+ button@800 {
+ label = "Search";
+ linux,code = <KEY_SEARCH>;
+ channel = <0>;
+ voltage = <800000>;
+ };
+
+ button@980 {
+ label = "Home";
+ linux,code = <KEY_HOMEPAGE>;
+ channel = <0>;
+ voltage = <980000>;
+ };
+
+ button@1180 {
+ label = "Esc";
+ linux,code = <KEY_ESC>;
+ channel = <0>;
+ voltage = <1180000>;
+ };
+
+ button@1400 {
+ label = "Enter";
+ linux,code = <KEY_ENTER>;
+ channel = <0>;
+ voltage = <1400000>;
+ };
};
&mmc0 {
status = "okay";
};
+&mmc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olimex_som_evb>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */
+ cd-inverted;
+ status = "okay";
+};
+
&ohci0 {
status = "okay";
};
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ mmc3_cd_pin_olimex_som_evb: mmc3_cd_pin@0 {
+ allwinner,pins = "PH0";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH04";
+ allwinner,pins = "PH4";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PH05";
+ allwinner,pins = "PH5";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
®_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1425000>;
+ regulator-max-microvolt = <1400000>;
regulator-name = "vdd-cpu";
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpios = <&pio 7 04 GPIO_ACTIVE_HIGH>; /* PH04 */
- usb0_vbus_det-gpios = <&pio 7 05 GPIO_ACTIVE_HIGH>; /* PH05 */
+ usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH04 */
+ usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH05 */
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
};
};
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
};
&mmc0 {
status = "okay";
};
+&otg_sram {
+ status = "okay";
+};
+
&pio {
ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
allwinner,pins = "PC3";
allwinner,drive = <SUN4I_PINCTRL_20_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = "PH5";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ };
+
+ usb0_vbus_pin_lime2: usb0_vbus_pin@0 {
+ allwinner,pins = "PC17";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
};
®_ahci_5v {
status = "okay";
};
+®_usb0_vbus {
+ pinctrl-0 = <&usb0_vbus_pin_lime2>;
+ gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
®_usb1_vbus {
status = "okay";
};
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
};
&i2c2 {
status = "okay";
};
+&codec {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
status = "okay";
};
+&otg_sram {
+ status = "okay";
+};
+
&pio {
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
mmc0_cd_pin_orangepi: mmc0_cd_pin@0 {
allwinner,pins = "PH10";
allwinner,function = "gpio_in";
regulator-name = "avcc";
};
+®_usb0_vbus {
+ status = "okay";
+};
+
®_usb1_vbus {
pinctrl-0 = <&usb1_vbus_pin_bananapro>;
gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
status = "okay";
};
+&otg_sram {
+ status = "okay";
+};
+
&pio {
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
mmc0_cd_pin_orangepi: mmc0_cd_pin@0 {
allwinner,pins = "PH10";
allwinner,function = "gpio_in";
regulator-name = "avcc";
};
+®_usb0_vbus {
+ status = "okay";
+};
+
®_usb1_vbus {
pinctrl-0 = <&usb1_vbus_pin_bananapro>;
gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
status = "okay";
};
+&codec {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
&ehci0 {
status = "okay";
};
status = "okay";
axp209: pmic@34 {
- compatible = "x-powers,axp209";
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-
- interrupt-controller;
- #interrupt-cells = <1>;
};
};
status = "okay";
};
+&otg_sram {
+ status = "okay";
+};
+
&pio {
ahci_pwr_pin_pcduino3_nano: ahci_pwr_pin@0 {
allwinner,pins = "PH2";
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
usb1_vbus_pin_pcduino3_nano: usb1_vbus_pin@0 {
- allwinner,pins = "PH11";
+ allwinner,pins = "PD2";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
status = "okay";
};
-®_usb1_vbus {
- pinctrl-0 = <&usb1_vbus_pin_pcduino3_nano>;
- gpio = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
- status = "okay";
+#include "axp209.dtsi"
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-pll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
};
-®_usb2_vbus {
+/* A single regulator (U24) powers both USB host ports. */
+®_usb1_vbus {
+ pinctrl-0 = <&usb1_vbus_pin_pcduino3_nano>;
+ gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
status = "okay";
};
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb1_vbus-supply = <®_usb1_vbus>;
- usb2_vbus-supply = <®_usb2_vbus>;
+ usb2_vbus-supply = <®_usb1_vbus>;
status = "okay";
};
allwinner,pins = "PH2";
};
+&codec {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
&ehci0 {
status = "okay";
};
status = "okay";
axp209: pmic@34 {
- compatible = "x-powers,axp209";
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-
- interrupt-controller;
- #interrupt-cells = <1>;
};
};
+#include "axp209.dtsi"
+
&ir0 {
pinctrl-names = "default";
pinctrl-0 = <&ir0_rx_pins_a>;
status = "okay";
};
+&otg_sram {
+ status = "okay";
+};
+
&pio {
led_pins_pcduino3: led_pins@0 {
allwinner,pins = "PH15", "PH16";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
};
®_ahci_5v {
status = "okay";
};
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-pll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
®_usb1_vbus {
status = "okay";
};
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
/ {
model = "Wexler TAB7200";
serial0 = &uart0;
};
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bl_enable_pin>;
+ enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
};
+&codec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&codec_pa_pin>;
+ allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <®_dcdc2>;
};
};
};
+#include "axp209.dtsi"
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
+
+ gt911: touchscreen@5d {
+ compatible = "goodix,gt911";
+ reg = <0x5d>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; /* EINT21 (PH21) */
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_reset_pin>;
+ irq-gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* INT (PH21) */
+ reset-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* RST (PB13) */
+ touchscreen-swapped-x-y;
+ };
};
&lradc {
status = "okay";
};
-#include "axp209.dtsi"
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ bl_enable_pin: bl_enable_pin@0 {
+ allwinner,pins = "PH7";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ codec_pa_pin: codec_pa_pin@0 {
+ allwinner,pins = "PH15";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ ts_reset_pin: ts_reset_pin@0 {
+ allwinner,pins = "PB13";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins_a>;
+ status = "okay";
+};
®_dcdc2 {
regulator-always-on;
regulator-name = "avcc";
};
+®_usb0_vbus {
+ status = "okay";
+};
+
®_usb1_vbus {
status = "okay";
};
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
/*
- * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ * Copyright 2015 Jelle de Jong <jelledejong@powercraft.nl>
*
- * Minimal dts file for the Wits Pro A20 DKT for u-boot only
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
*
- * SPDX-License-Identifier: GPL-2.0+ or X11
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Wits Pro A20 DKT";
chosen {
stdout-path = "serial0:115200n8";
};
+
+ mmc3_pwrseq: mmc3_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vmmc3_pin_ap6xxx_wl_regon>;
+ reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
};
&ehci0 {
};
};
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+#include "axp209.dtsi"
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&mmc3_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&pio>;
+ interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */
+ interrupt-names = "host-wake";
+ };
+};
+
&ohci0 {
status = "okay";
};
status = "okay";
};
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ vmmc3_pin_ap6xxx_wl_regon: vmmc3_pin@0 {
+ allwinner,pins = "PH9";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb0_vbus {
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
+&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <®_usb0_vbus>;
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/clock/sun4i-a10-pll2.h>
#include <dt-bindings/dma/sun4i-a10.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
- <&ahb_gates 44>;
+ <&ahb_gates 44>, <&dram_gates 26>;
status = "disabled";
};
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
- clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
+ clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
+ <&dram_gates 26>;
status = "disabled";
};
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0";
clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
- <&ahb_gates 44>;
+ <&ahb_gates 44>, <&dram_gates 26>;
status = "disabled";
};
};
720000 1200000
528000 1100000
312000 1000000
- 144000 900000
+ 144000 1000000
>;
#cooling-cells = <2>;
cooling-min-level = <0>;
clock-output-names = "pll1";
};
+ pll2: clk@01c20008 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-pll2-clk";
+ reg = <0x01c20008 0x8>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll2-1x", "pll2-2x",
+ "pll2-4x", "pll2-8x";
+ };
+
pll4: clk@01c20018 {
#clock-cells = <0>;
compatible = "allwinner,sun7i-a20-pll4-clk";
compatible = "allwinner,sun7i-a20-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <5>, <6>, <7>, <8>,
+ <9>, <10>, <11>, <12>,
+ <13>, <14>, <16>,
+ <17>, <18>, <20>, <21>,
+ <22>, <23>, <25>,
+ <28>, <32>, <33>, <34>,
+ <35>, <36>, <37>, <40>,
+ <41>, <42>, <43>,
+ <44>, <45>, <46>,
+ <47>, <49>, <50>,
+ <52>;
clock-output-names = "ahb_usb0", "ahb_ehci0",
"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
compatible = "allwinner,sun7i-a20-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <5>, <6>, <7>,
+ <8>, <10>;
clock-output-names = "apb0_codec", "apb0_spdif",
"apb0_ac97", "apb0_iis0", "apb0_iis1",
"apb0_pio", "apb0_ir0", "apb0_ir1",
compatible = "allwinner,sun7i-a20-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <5>, <6>, <7>,
+ <15>, <16>, <17>,
+ <18>, <19>, <20>,
+ <21>, <22>, <23>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
"apb1_i2c2", "apb1_i2c3", "apb1_can",
"apb1_scr", "apb1_ps20", "apb1_ps21",
clock-output-names = "ir1";
};
+ keypad_clk: clk@01c200c4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200c4 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "keypad";
+ };
+
usb_clk: clk@01c200cc {
#clock-cells = <1>;
#reset-cells = <1>;
clock-output-names = "spi3";
};
+ dram_gates: clk@01c20100 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-dram-gates-clk";
+ reg = <0x01c20100 0x4>;
+ clocks = <&pll5 0>;
+ clock-indices = <0>,
+ <1>, <2>,
+ <3>,
+ <4>,
+ <5>, <6>,
+ <15>,
+ <24>, <25>,
+ <26>, <27>,
+ <28>, <29>;
+ clock-output-names = "dram_ve",
+ "dram_csi0", "dram_csi1",
+ "dram_ts",
+ "dram_tvd",
+ "dram_tve0", "dram_tve1",
+ "dram_output",
+ "dram_de_fe1", "dram_de_fe0",
+ "dram_de_be0", "dram_de_be1",
+ "dram_de_mp", "dram_ace";
+ };
+
+ ve_clk: clk@01c2013c {
+ #clock-cells = <0>;
+ #reset-cells = <0>;
+ compatible = "allwinner,sun4i-a10-ve-clk";
+ reg = <0x01c2013c 0x4>;
+ clocks = <&pll4>;
+ clock-output-names = "ve";
+ };
+
+ codec_clk: clk@01c20140 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-codec-clk";
+ reg = <0x01c20140 0x4>;
+ clocks = <&pll2 SUN4I_A10_PLL2_1X>;
+ clock-output-names = "codec";
+ };
+
mbus_clk: clk@01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun5i-a13-mbus-clk";
status = "disabled";
};
+ crypto: crypto-engine@01c15000 {
+ compatible = "allwinner,sun4i-a10-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb_gates 5>, <&ss_clk>;
+ clock-names = "ahb", "mod";
+ };
+
spi2: spi@01c17000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c17000 0x1000>;
status = "disabled";
};
+ codec: codec@01c22c00 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun7i-a20-codec";
+ reg = <0x01c22c00 0x40>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb0_gates 0>, <&codec_clk>;
+ clock-names = "apb", "codec";
+ dmas = <&dma SUN4I_DMA_NORMAL 19>,
+ <&dma SUN4I_DMA_NORMAL 19>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
sid: eeprom@01c23800 {
compatible = "allwinner,sun7i-a20-sid";
reg = <0x01c23800 0x200>;
#size-cells = <1>;
ranges;
- framebuffer@0 {
+ simplefb_lcd: framebuffer@0 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
clock-output-names = "apb1";
};
- ahb1_gates: clk@01c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
- reg = <0x01c20060 0x8>;
- clocks = <&ahb1>;
- clock-output-names = "ahb1_mipidsi", "ahb1_dma",
- "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
- "ahb1_nand", "ahb1_sdram",
- "ahb1_hstimer", "ahb1_spi0",
- "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
- "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
- "ahb1_csi", "ahb1_be", "ahb1_fe",
- "ahb1_gpu", "ahb1_spinlock",
- "ahb1_drc";
- };
-
apb1_gates: clk@01c20068 {
#clock-cells = <1>;
compatible = "allwinner,sun8i-a23-apb1-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <5>,
+ <12>, <13>;
clock-output-names = "apb1_codec", "apb1_pio",
"apb1_daudio0", "apb1_daudio1";
};
compatible = "allwinner,sun8i-a23-apb2-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb2>;
+ clock-indices = <0>, <1>,
+ <2>, <16>,
+ <17>, <18>,
+ <19>, <20>;
clock-output-names = "apb2_i2c0", "apb2_i2c1",
"apb2_i2c2", "apb2_uart0",
"apb2_uart1", "apb2_uart2",
allwinner,pins = "PC5", "PC6", "PC8",
"PC9", "PC10", "PC11",
"PC12", "PC13", "PC14",
- "PC15";
+ "PC15", "PC16";
allwinner,function = "mmc2";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ pwm0_pins: pwm0 {
+ allwinner,pins = "PH0";
+ allwinner,function = "pwm0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
i2c0_pins_a: i2c0@0 {
allwinner,pins = "PH2", "PH3";
allwinner,function = "i2c0";
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
};
+ pwm: pwm@01c21400 {
+ compatible = "allwinner,sun7i-a20-pwm";
+ reg = <0x01c21400 0xc>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
lradc: lradc@01c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
+ nmi_intc: interrupt-controller@01f00c0c {
+ compatible = "allwinner,sun6i-a31-sc-nmi";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x01f00c0c 0x38>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
prcm@01f01400 {
compatible = "allwinner,sun8i-a23-prcm";
reg = <0x01f01400 0x200>;
resets = <&apb0_rst 0>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <0>;
#gpio-cells = <3>;
+ r_rsb_pins: r_rsb {
+ allwinner,pins = "PL0", "PL1";
+ allwinner,function = "s_rsb";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
r_uart_pins_a: r_uart@0 {
allwinner,pins = "PL2", "PL3";
allwinner,function = "s_uart";
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
+
+ r_rsb: rsb@01f03400 {
+ compatible = "allwinner,sun8i-a23-rsb";
+ reg = <0x01f03400 0x400>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb0_gates 3>;
+ clock-frequency = <3000000>;
+ resets = <&apb0_rst 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_rsb_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/pwm/pwm.h>
/ {
- model = "Allwinner GT90H Quad Core Tablet (v4)";
- compatible = "allwinner,gt90h-v4", "allwinner,sun8i-a33";
+ model = "Allwinner GT90H Dual Core Tablet (v4)";
+ compatible = "allwinner,gt90h-v4", "allwinner,sun8i-a23";
aliases {
serial0 = &r_uart;
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bl_en_pin_gt90h>;
+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <8>;
+ enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_gt90h>;
- /* FIXME this really is aldo1, correct once we've pmic support */
- vmmc-supply = <®_vcc3v0>;
+ vmmc-supply = <®_aldo1>;
bus-width = <4>;
cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
cd-inverted;
};
&pio {
+ bl_en_pin_gt90h: bl_en_pin@0 {
+ allwinner,pins = "PH6";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
mmc0_cd_pin_gt90h: mmc0_cd_pin@0 {
allwinner,pins = "PB4";
allwinner,function = "gpio_in";
};
};
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins>;
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp22x: pmic@3a3 {
+ compatible = "x-powers,axp223";
+ reg = <0x3a3>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ eldoin-supply = <®_dcdc1>;
+ };
+};
+
&r_uart {
pinctrl-names = "default";
pinctrl-0 = <&r_uart_pins_a>;
status = "okay";
};
+#include "axp22x.dtsi"
+
+®_aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-io";
+};
+
+®_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <2350000>;
+ regulator-max-microvolt = <2650000>;
+ regulator-name = "vdd-dll";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-lcd";
+};
+
+®_dc5ldo {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpus";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v0";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-sys";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&simplefb_lcd {
+ vcc-lcd-supply = <®_dc1sw>;
+};
+
/*
* FIXME for now we only support host mode and rely on u-boot to have
* turned on Vbus which is controlled by the axp223 pmic on the board.
};
&usbphy {
+ usb1_vbus-supply = <®_dldo1>;
status = "okay";
};
--- /dev/null
+/*
+ * Copyright 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a23.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Polaroid MID2809PXE04 tablet";
+ compatible = "polaroid,mid2809pxe04", "allwinner,sun8i-a23";
+
+ aliases {
+ serial0 = &r_uart;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bl_en_pin_mid2809>;
+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <8>;
+ enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <®_vcc3v0>;
+ status = "okay";
+
+ button@200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button@400 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mid2809>;
+ vmmc-supply = <®_dcdc1>;
+ bus-width = <4>;
+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+ cd-inverted;
+ status = "okay";
+};
+
+&pio {
+ bl_en_pin_mid2809: bl_en_pin@0 {
+ allwinner,pins = "PH6";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_cd_pin_mid2809: mmc0_cd_pin@0 {
+ allwinner,pins = "PB4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins>;
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp22x: pmic@3a3 {
+ compatible = "x-powers,axp223";
+ reg = <0x3a3>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ eldoin-supply = <®_dcdc1>;
+ };
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins_a>;
+ status = "okay";
+};
+
+#include "axp22x.dtsi"
+
+®_aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-io";
+};
+
+®_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <2350000>;
+ regulator-max-microvolt = <2650000>;
+ regulator-name = "vdd-dll";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-lcd";
+};
+
+®_dc5ldo {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpus";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v0";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-sys";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&simplefb_lcd {
+ vcc-lcd-supply = <®_dc1sw>;
+};
+
+/*
+ * FIXME for now we only support host mode and rely on u-boot to have
+ * turned on Vbus which is controlled by the axp223 pmic on the board.
+ *
+ * Once we have axp223 support we should switch to fully supporting otg.
+ */
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
};
clocks {
+ ahb1_gates: clk@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
+ reg = <0x01c20060 0x8>;
+ clocks = <&ahb1>;
+ clock-indices = <1>, <6>,
+ <8>, <9>, <10>,
+ <13>, <14>,
+ <19>, <20>,
+ <21>, <24>, <26>,
+ <29>, <32>, <36>,
+ <40>, <44>, <46>,
+ <52>, <53>,
+ <54>, <57>;
+ clock-output-names = "ahb1_mipidsi", "ahb1_dma",
+ "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
+ "ahb1_nand", "ahb1_sdram",
+ "ahb1_hstimer", "ahb1_spi0",
+ "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
+ "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
+ "ahb1_csi", "ahb1_be", "ahb1_fe",
+ "ahb1_gpu", "ahb1_msgbox",
+ "ahb1_spinlock", "ahb1_drc";
+ };
+
mbus_clk: clk@01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-mbus-clk";
};
&lradc {
- vref-supply = <®_vcc3v0>;
+ vref-supply = <®_dcdc1>;
status = "okay";
button@200 {
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>;
- vmmc-supply = <®_vcc3v0>;
+ vmmc-supply = <®_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
cd-inverted;
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_8bit_pins>;
- vmmc-supply = <®_vcc3v0>;
+ vmmc-supply = <®_dcdc1>;
bus-width = <8>;
non-removable;
+ cap-mmc-hw-reset;
status = "okay";
};
&mmc2_8bit_pins {
+ /* Increase drive strength for DDR modes */
+ allwinner,drive = <SUN4I_PINCTRL_40_MA>;
/* eMMC is missing pull-ups */
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
};
};
};
+&r_rsb {
+ status = "okay";
+
+ axp22x: pmic@3a3 {
+ compatible = "x-powers,axp223";
+ reg = <0x3a3>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ eldoin-supply = <®_dcdc1>;
+ };
+};
+
+#include "axp22x.dtsi"
+
+®_aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-io";
+};
+
+®_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <2350000>;
+ regulator-max-microvolt = <2650000>;
+ regulator-name = "vdd-dll";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc5ldo {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpus";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v0";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-sys";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_b>;
clock-output-names = "pll11";
};
+ ahb1_gates: clk@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun8i-a33-ahb1-gates-clk";
+ reg = <0x01c20060 0x8>;
+ clocks = <&ahb1>;
+ clock-indices = <1>, <5>,
+ <6>, <8>, <9>,
+ <10>, <13>, <14>,
+ <19>, <20>,
+ <21>, <24>, <26>,
+ <29>, <32>, <36>,
+ <40>, <44>, <46>,
+ <52>, <53>,
+ <54>, <57>,
+ <58>;
+ clock-output-names = "ahb1_mipidsi", "ahb1_ss",
+ "ahb1_dma","ahb1_mmc0", "ahb1_mmc1",
+ "ahb1_mmc2", "ahb1_nand", "ahb1_sdram",
+ "ahb1_hstimer", "ahb1_spi0",
+ "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
+ "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
+ "ahb1_csi", "ahb1_be", "ahb1_fe",
+ "ahb1_gpu", "ahb1_msgbox",
+ "ahb1_spinlock", "ahb1_drc",
+ "ahb1_sat";
+ };
+
+ ss_clk: clk@01c2009c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2009c 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "ss";
+ };
+
mbus_clk: clk@01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-mbus-clk";
};
soc@01c00000 {
+ crypto: crypto-engine@01c15000 {
+ compatible = "allwinner,sun4i-a10-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb1_gates 5>, <&ss_clk>;
+ clock-names = "ahb", "mod";
+ resets = <&ahb1_rst 5>;
+ reset-names = "ahb";
+ };
+
usb_otg: usb@01c19000 {
compatible = "allwinner,sun8i-a33-musb";
reg = <0x01c19000 0x0400>;
};
};
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_b>;
status = "okay";
};
+
+&usb_otg {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+
+/ {
+ model = "Cubietech Cubietruck Plus";
+ compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_b>;
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+};
};
};
+&ehci0 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_b>;
status = "okay";
};
+
+&usb_otg {
+ status = "okay";
+};
/ {
interrupt-parent = <&gic>;
- chosen {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
device_type = "cpu";
reg = <3>;
};
+
cpu@100 {
compatible = "arm,cortex-a7";
device_type = "cpu";
device_type = "cpu";
reg = <0x101>;
};
+
cpu@102 {
compatible = "arm,cortex-a7";
device_type = "cpu";
};
};
- memory {
- reg = <0x40000000 0x80000000>;
- };
-
timer {
compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- clock-frequency = <24000000>;
- arm,cpu-registers-not-fw-configured;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
clocks {
#size-cells = <1>;
ranges;
+ /* TODO: PRCM block has a mux for this. */
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-output-names = "osc24M";
};
- osc32k: osc32k_clk {
+ /*
+ * This is called "internal OSC" in some places.
+ * It is an internal RC-based oscillator.
+ * TODO: Its controls are in the PRCM block.
+ */
+ osc16M: osc16M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "osc32k";
+ clock-frequency = <16000000>;
+ clock-output-names = "osc16M";
+ };
+
+ osc16Md512: osc16Md512_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <512>;
+ clock-mult = <1>;
+ clocks = <&osc16M>;
+ clock-output-names = "osc16M-d512";
};
};
- soc@01c00000 {
+ soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- gic: interrupt-controller@01c81000 {
- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
- reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
- <0x01c84000 0x2000>,
- <0x01c86000 0x2000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
pio: pinctrl@01c20800 {
compatible = "allwinner,sun8i-a83t-pinctrl";
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x01c20800 0x400>;
clocks = <&osc24M>;
gpio-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
- i2c0_pins_a: i2c0@0 {
- allwinner,pins = "PH0", "PH1";
- allwinner,function = "i2c0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- i2c1_pins_a: i2c1@0 {
- allwinner,pins = "PH2", "PH3";
- allwinner,function = "i2c1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- i2c2_pins_a: i2c2@0 {
- allwinner,pins = "PH4", "PH5";
- allwinner,function = "i2c2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
mmc0_pins_a: mmc0@0 {
allwinner,pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
- mmc1_pins_a: mmc1@0 {
- allwinner,pins = "PG0", "PG1", "PG2",
- "PG3", "PG4", "PG5";
- allwinner,function = "mmc1";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- mmc2_8bit_pins: mmc2_8bit {
- allwinner,pins = "PC5", "PC6", "PC8",
- "PC9", "PC10", "PC11",
- "PC12", "PC13", "PC14",
- "PC15";
- allwinner,function = "mmc2";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
uart0_pins_a: uart0@0 {
allwinner,pins = "PF2", "PF4";
allwinner,function = "uart0";
};
};
+ timer@01c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0xa0>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
+ watchdog@01c20ca0 {
+ compatible = "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
uart0: serial@01c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
clocks = <&osc24M>;
status = "disabled";
};
+
+ gic: interrupt-controller@01c81000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x1000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ usb_otg: usb@01c19000 {
+ compatible = "allwinner,sun8i-a33-musb";
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+ status = "disabled";
+ };
+
+ ehci0: usb@01c1a000 {
+ compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ohci0: usb@01c1a400 {
+ compatible = "allwinner,sun8i-a83t-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ehci1: usb@01c1b000 {
+ compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci";
+ reg = <0x01c1b000 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ r_pio: pinctrl@01f02c00 {
+ compatible = "allwinner,sun8i-a83t-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
};
--- /dev/null
+/*
+ * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Xunlong Orange Pi 2";
+ compatible = "xunlong,orangepi-2", "allwinner,sun8i-h3";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
+
+ status_led {
+ label = "orangepi:red:status";
+ gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>;
+ };
+
+ pwr_led {
+ label = "orangepi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ r_gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_r_opc>;
+
+ sw2 {
+ label = "sw2";
+ linux,code = <BTN_1>;
+ gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>;
+ };
+
+ sw4 {
+ label = "sw4";
+ linux,code = <BTN_0>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_pwrseq_pin_orangepi>;
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&pio {
+ leds_opc: led_pins@0 {
+ allwinner,pins = "PA15";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&r_pio {
+ leds_r_opc: led_pins@0 {
+ allwinner,pins = "PL10";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ sw_r_opc: key_pins@0 {
+ allwinner,pins = "PL3", "PL4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin@0 {
+ allwinner,pins = "PL7";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb1_vbus_pin_a {
+ allwinner,pins = "PG13";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Xunlong Orange Pi One";
+ compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
+
+ pwr_led {
+ label = "orangepi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ status_led {
+ label = "orangepi:red:status";
+ gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ r_gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_r_opc>;
+
+ sw4 {
+ label = "sw4";
+ linux,code = <BTN_0>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ leds_opc: led_pins@0 {
+ allwinner,pins = "PA15";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&r_pio {
+ leds_r_opc: led_pins@0 {
+ allwinner,pins = "PL10";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ sw_r_opc: key_pins@0 {
+ allwinner,pins = "PL3";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ /* USB VBUS is always on */
+ status = "okay";
+};
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_opc>;
+
+ status_led {
+ label = "status:red:user";
+ gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ r_leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_r_opc>;
+
+ tx {
+ label = "pwr:green:user";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ r_gpio_keys {
+ compatible = "gpio-keys";
+ input-name = "sw4";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_r_opc>;
+
+ sw4@0 {
+ label = "sw4";
+ linux,code = <BTN_0>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
};
&ehci1 {
status = "okay";
};
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
status = "okay";
};
+&pio {
+ leds_opc: led_pins@0 {
+ allwinner,pins = "PA15";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&r_pio {
+ leds_r_opc: led_pins@0 {
+ allwinner,pins = "PL10";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ sw_r_opc: key_pins@0 {
+ allwinner,pins = "PL03";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
enable-active-high;
gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
};
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_opc>;
+
+ status_led {
+ label = "status:red:user";
+ gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ r_leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_r_opc>;
+
+ tx {
+ label = "pwr:green:user";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ r_gpio_keys {
+ compatible = "gpio-keys";
+ input-name = "sw4";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_r_opc>;
+
+ sw4@0 {
+ label = "sw4";
+ linux,code = <BTN_0>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&pio {
+ leds_opc: led_pins@0 {
+ allwinner,pins = "PA15";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&r_pio {
+ leds_r_opc: led_pins@0 {
+ allwinner,pins = "PL10";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ sw_r_opc: key_pins@0 {
+ allwinner,pins = "PL03";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
};
&ehci1 {
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- clock-frequency = <24000000>;
- arm,cpu-registers-not-fw-configured;
- };
-
- memory {
- reg = <0x40000000 0x80000000>;
};
clocks {
compatible = "allwinner,sun6i-a31-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
- clock-output-names = "pll6", "pll6x2", "pll6d2";
+ clock-output-names = "pll6", "pll6x2";
};
- pll8: clk@01c20044 {
- #clock-cells = <1>;
- compatible = "allwinner,sun6i-a31-pll6-clk";
- reg = <0x01c20044 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll8", "pll8x2";
+ pll6d2: pll6d2_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <2>;
+ clock-mult = <1>;
+ clocks = <&pll6 0>;
+ clock-output-names = "pll6d2";
+ };
+
+ /* dummy clock until pll6 can be reused */
+ pll8: pll8_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+ clock-output-names = "pll8";
};
cpu: cpu_clk@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun8i-h3-ahb2-clk";
reg = <0x01c2005c 0x4>;
- clocks = <&ahb1>, <&pll6 2>;
+ clocks = <&ahb1>, <&pll6d2>;
clock-output-names = "ahb2";
};
<76>, <77>, <78>,
<96>, <97>, <98>,
<112>, <113>,
- <114>, <115>, <116>,
- <128>, <135>;
- clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0",
- "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand",
- "ahb1_sdram", "ahb2_gmac", "ahb1_ts",
- "ahb1_hstimer", "ahb1_spi0",
- "ahb1_spi1", "ahb1_otg",
- "ahb1_otg_ehci0", "ahb1_ehic1",
- "ahb1_ehic2", "ahb1_ehic3",
- "ahb1_otg_ohci0", "ahb2_ohic1",
- "ahb2_ohic2", "ahb2_ohic3", "ahb1_ve",
- "ahb1_lcd0", "ahb1_lcd1", "ahb1_deint",
- "ahb1_csi", "ahb1_tve", "ahb1_hdmi",
- "ahb1_de", "ahb1_gpu", "ahb1_msgbox",
- "ahb1_spinlock", "apb1_codec",
- "apb1_spdif", "apb1_pio", "apb1_ths",
- "apb1_i2s0", "apb1_i2s1", "apb1_i2s2",
- "apb2_i2c0", "apb2_i2c1", "apb2_i2c2",
- "apb2_uart0", "apb2_uart1",
- "apb2_uart2", "apb2_uart3", "apb2_scr",
- "ahb1_ephy", "ahb1_dbg";
+ <114>, <115>,
+ <116>, <128>, <135>;
+ clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
+ "bus_mmc1", "bus_mmc2", "bus_nand",
+ "bus_sdram", "bus_gmac", "bus_ts",
+ "bus_hstimer", "bus_spi0",
+ "bus_spi1", "bus_otg",
+ "bus_otg_ehci0", "bus_ehci1",
+ "bus_ehci2", "bus_ehci3",
+ "bus_otg_ohci0", "bus_ohci1",
+ "bus_ohci2", "bus_ohci3", "bus_ve",
+ "bus_lcd0", "bus_lcd1", "bus_deint",
+ "bus_csi", "bus_tve", "bus_hdmi",
+ "bus_de", "bus_gpu", "bus_msgbox",
+ "bus_spinlock", "bus_codec",
+ "bus_spdif", "bus_pio", "bus_ths",
+ "bus_i2s0", "bus_i2s1", "bus_i2s2",
+ "bus_i2c0", "bus_i2c1", "bus_i2c2",
+ "bus_uart0", "bus_uart1",
+ "bus_uart2", "bus_uart3",
+ "bus_scr", "bus_ephy", "bus_dbg";
};
mmc0_clk: clk@01c20088 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20088 0x4>;
- clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
+ clocks = <&osc24M>, <&pll6 0>, <&pll8>;
clock-output-names = "mmc0",
"mmc0_output",
"mmc0_sample";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c2008c 0x4>;
- clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
+ clocks = <&osc24M>, <&pll6 0>, <&pll8>;
clock-output-names = "mmc1",
"mmc1_output",
"mmc1_sample";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20090 0x4>;
- clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
+ clocks = <&osc24M>, <&pll6 0>, <&pll8>;
clock-output-names = "mmc2",
"mmc2_output",
"mmc2_sample";
clocks = <&osc24M>, <&pll6 1>, <&pll5>;
clock-output-names = "mbus";
};
+
+ apb0: apb0_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&osc24M>;
+ clock-output-names = "apb0";
+ };
+
+ apb0_gates: clk@01f01428 {
+ compatible = "allwinner,sun8i-h3-apb0-gates-clk",
+ "allwinner,sun4i-a10-gates-clk";
+ reg = <0x01f01428 0x4>;
+ #clock-cells = <1>;
+ clocks = <&apb0>;
+ clock-indices = <0>, <1>;
+ clock-output-names = "apb0_pio", "apb0_ir";
+ };
+
+ ir_clk: ir_clk@01f01454 {
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01f01454 0x4>;
+ #clock-cells = <0>;
+ clocks = <&osc32k>, <&osc24M>;
+ clock-output-names = "ir";
+ };
};
soc {
reg = <0x01c02000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 6>;
- resets = <&bus_rst 6>;
+ resets = <&ahb_rst 6>;
#dma-cells = <1>;
};
"mmc",
"output",
"sample";
- resets = <&bus_rst 8>;
+ resets = <&ahb_rst 8>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
"mmc",
"output",
"sample";
- resets = <&bus_rst 9>;
+ resets = <&ahb_rst 9>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
"mmc",
"output",
"sample";
- resets = <&bus_rst 10>;
+ resets = <&ahb_rst 10>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
reg = <0x01c1b000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 25>, <&bus_gates 29>;
- resets = <&bus_rst 25>, <&bus_rst 29>;
+ resets = <&ahb_rst 25>, <&ahb_rst 29>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 29>, <&bus_gates 25>,
<&usb_clk 17>;
- resets = <&bus_rst 29>, <&bus_rst 25>;
+ resets = <&ahb_rst 29>, <&ahb_rst 25>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
reg = <0x01c1c000 0x100>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 26>, <&bus_gates 30>;
- resets = <&bus_rst 26>, <&bus_rst 30>;
+ resets = <&ahb_rst 26>, <&ahb_rst 30>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 30>, <&bus_gates 26>,
<&usb_clk 18>;
- resets = <&bus_rst 30>, <&bus_rst 26>;
+ resets = <&ahb_rst 30>, <&ahb_rst 26>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
reg = <0x01c1d000 0x100>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 27>, <&bus_gates 31>;
- resets = <&bus_rst 27>, <&bus_rst 31>;
+ resets = <&ahb_rst 27>, <&ahb_rst 31>;
phys = <&usbphy 3>;
phy-names = "usb";
status = "disabled";
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 31>, <&bus_gates 27>,
<&usb_clk 19>;
- resets = <&bus_rst 31>, <&bus_rst 27>;
+ resets = <&ahb_rst 31>, <&ahb_rst 27>;
phys = <&usbphy 3>;
phy-names = "usb";
status = "disabled";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
- #interrupt-cells = <2>;
+ #interrupt-cells = <3>;
uart0_pins_a: uart0@0 {
allwinner,pins = "PA4", "PA5";
};
};
- bus_rst: reset@01c202c0 {
+ ahb_rst: reset@01c202c0 {
#reset-cells = <1>;
- compatible = "allwinner,sun8i-h3-bus-reset";
- reg = <0x01c202c0 0x1c>;
+ compatible = "allwinner,sun6i-a31-ahb1-reset";
+ reg = <0x01c202c0 0xc>;
+ };
+
+ apb1_rst: reset@01c202d0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d0 0x4>;
+ };
+
+ apb2_rst: reset@01c202d8 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d8 0x4>;
};
timer@01c20c00 {
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&bus_gates 112>;
- resets = <&bus_rst 144>;
+ resets = <&apb2_rst 16>;
dmas = <&dma 6>, <&dma 6>;
dma-names = "rx", "tx";
status = "disabled";
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&bus_gates 113>;
- resets = <&bus_rst 145>;
+ resets = <&apb2_rst 17>;
dmas = <&dma 7>, <&dma 7>;
dma-names = "rx", "tx";
status = "disabled";
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&bus_gates 114>;
- resets = <&bus_rst 146>;
+ resets = <&apb2_rst 18>;
dmas = <&dma 8>, <&dma 8>;
dma-names = "rx", "tx";
status = "disabled";
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&bus_gates 115>;
- resets = <&bus_rst 147>;
+ resets = <&apb2_rst 19>;
dmas = <&dma 9>, <&dma 9>;
dma-names = "rx", "tx";
status = "disabled";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ apb0_reset: reset@01f014b0 {
+ reg = <0x01f014b0 0x4>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ #reset-cells = <1>;
+ };
+
+ ir: ir@01f02000 {
+ compatible = "allwinner,sun5i-a13-ir";
+ clocks = <&apb0_gates 1>, <&ir_clk>;
+ clock-names = "apb", "ir";
+ resets = <&apb0_reset 1>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x01f02000 0x40>;
+ status = "disabled";
+ };
+
+ r_pio: pinctrl@01f02c00 {
+ compatible = "allwinner,sun8i-h3-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb0_gates 0>;
+ resets = <&apb0_reset 0>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ ir_pins_a: ir@0 {
+ allwinner,pins = "PL11";
+ allwinner,function = "s_cir_rx";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
};
};
*/
#include "sunxi-q8-common.dtsi"
+#include <dt-bindings/pwm/pwm.h>
+
/ {
aliases {
serial0 = &r_uart;
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bl_en_pin_q8>;
+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <8>;
+ enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>;
- vmmc-supply = <®_vcc3v0>;
+ vmmc-supply = <®_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
cd-inverted;
};
};
+&r_rsb {
+ status = "okay";
+
+ axp22x: pmic@3a3 {
+ compatible = "x-powers,axp223";
+ reg = <0x3a3>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ eldoin-supply = <®_dcdc1>;
+ };
+};
+
+#include "axp22x.dtsi"
+
+®_aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-io";
+};
+
+®_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <2350000>;
+ regulator-max-microvolt = <2650000>;
+ regulator-name = "vdd-dll";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-lcd";
+};
+
+®_dc5ldo {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpus";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v0";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-sys";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
&r_uart {
pinctrl-names = "default";
pinctrl-0 = <&r_uart_pins_a>;
status = "okay";
};
+
+&simplefb_lcd {
+ vcc-lcd-supply = <®_dc1sw>;
+};
stdout-path = "serial0:115200n8";
};
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_cubieboard4>;
+
+ green {
+ label = "cubieboard4:green:usr";
+ gpios = <&pio 7 17 GPIO_ACTIVE_HIGH>; /* PH17 */
+ };
+
+ red {
+ label = "cubieboard4:red:usr";
+ gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+ };
+ };
};
&pio {
+ led_pins_cubieboard4: led-pins@0 {
+ allwinner,pins = "PH6", "PH17";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
mmc0_cd_pin_cubieboard4: mmc0_cd_pin@0 {
allwinner,pins = "PH18";
allwinner,function = "gpio_in";
vmmc-supply = <®_vcc3v0>;
bus-width = <8>;
non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&mmc2_8bit_pins {
+ /* Increase drive strength for DDR modes */
+ allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+};
+
+&r_ir {
+ status = "okay";
+};
+
+&r_rsb {
status = "okay";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
- pinctrl-0 = <&led_pins_optimus>;
+ pinctrl-0 = <&led_pins_optimus>, <&led_r_pins_optimus>;
/* The LED names match those found on the board */
gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>;
};
- /* led3 is on PM15, in R_PIO */
+ led3 {
+ label = "optimus:led3:usr";
+ gpios = <&r_pio 1 15 GPIO_ACTIVE_HIGH>; /* PM15 */
+ };
led4 {
label = "optimus:led4:usr";
status = "okay";
};
-&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins_a>;
- status = "okay";
-};
-
-&i2c3_pins_a {
- /* Enable internal pull-up */
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
-};
-
&ohci0 {
status = "okay";
};
vmmc-supply = <®_vcc3v0>;
bus-width = <8>;
non-removable;
+ cap-mmc-hw-reset;
status = "okay";
};
+&mmc2_8bit_pins {
+ /* Increase drive strength for DDR modes */
+ allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+};
+
®_usb1_vbus {
pinctrl-0 = <&usb1_vbus_pin_optimus>;
gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
status = "okay";
};
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+&r_ir {
status = "okay";
};
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_pins_a>;
+&r_pio {
+ led_r_pins_optimus: led-pins@1 {
+ allwinner,pins = "PM15";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&r_rsb {
status = "okay";
};
-&uart4_pins_a {
- /* Enable internal pull-up */
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
};
&usbphy1 {
*/
ranges = <0 0 0 0x20000000>;
+ /*
+ * This clock is actually configurable from the PRCM address
+ * space. The external 24M oscillator can be turned off, and
+ * the clock switched to an internal 16M RC oscillator. Under
+ * normal operation there's no reason to do this, and the
+ * default is to use the external good one, so just model this
+ * as a fixed clock. Also it is not entirely clear if the
+ * osc24M mux in the PRCM affects the entire clock tree, which
+ * would also throw all the PLL clock rates off, or just the
+ * downstream clocks in the PRCM.
+ */
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-output-names = "osc24M";
};
+ /*
+ * The 32k clock is from an external source, normally the
+ * AC100 codec/RTC chip. This clock is by default enabled
+ * and clocked at 32768 Hz, from the oscillator connected
+ * to the AC100. It is configurable, but no such driver or
+ * bindings exist yet.
+ */
osc32k: osc32k_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
"usb_phy2", "usb_hsic_12M";
};
+ pll3: clk@06000008 {
+ /* placeholder until implemented */
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-rate = <0>;
+ clock-output-names = "pll3";
+ };
+
pll4: clk@0600000c {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-pll4-clk";
compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
reg = <0x06000580 0x4>;
clocks = <&ahb0>;
- clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>,
- <14>, <15>, <16>, <18>, <20>, <21>,
- <22>, <23>;
+ clock-indices = <0>, <1>, <3>,
+ <5>, <8>, <12>,
+ <13>, <14>,
+ <15>, <16>, <18>,
+ <20>, <21>, <22>,
+ <23>;
clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
"ahb0_ss", "ahb0_sd", "ahb0_nand1",
"ahb0_nand0", "ahb0_sdram",
compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
reg = <0x06000584 0x4>;
clocks = <&ahb1>;
- clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>;
+ clock-indices = <0>, <1>,
+ <17>, <21>,
+ <22>, <23>,
+ <24>;
clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
"ahb1_gmac", "ahb1_msgbox",
"ahb1_spinlock", "ahb1_hstimer",
compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
reg = <0x06000588 0x4>;
clocks = <&ahb2>;
- clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>,
- <11>;
+ clock-indices = <0>, <1>,
+ <2>, <4>, <5>,
+ <7>, <8>, <11>;
clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
"ahb2_edp", "ahb2_csi", "ahb2_hdmi",
"ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
compatible = "allwinner,sun9i-a80-apb0-gates-clk";
reg = <0x06000590 0x4>;
clocks = <&apb0>;
- clock-indices = <1>, <5>, <11>, <12>, <13>, <15>,
- <17>, <18>, <19>;
+ clock-indices = <1>, <5>,
+ <11>, <12>, <13>,
+ <15>, <17>, <18>,
+ <19>;
clock-output-names = "apb0_spdif", "apb0_pio",
"apb0_ac97", "apb0_i2s0", "apb0_i2s1",
"apb0_lradc", "apb0_gpadc", "apb0_twd",
compatible = "allwinner,sun9i-a80-apb1-gates-clk";
reg = <0x06000594 0x4>;
clocks = <&apb1>;
- clock-indices = <0>, <1>, <2>, <3>, <4>,
- <16>, <17>, <18>, <19>, <20>, <21>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <16>, <17>,
+ <18>, <19>,
+ <20>, <21>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
"apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
"apb1_uart0", "apb1_uart1",
"apb1_uart2", "apb1_uart3",
"apb1_uart4", "apb1_uart5";
};
+
+ cpus_clk: clk@08001410 {
+ compatible = "allwinner,sun9i-a80-cpus-clk";
+ reg = <0x08001410 0x4>;
+ #clock-cells = <0>;
+ clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
+ clock-output-names = "cpus";
+ };
+
+ ahbs: ahbs_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&cpus_clk>;
+ clock-output-names = "ahbs";
+ };
+
+ apbs: clk@0800141c {
+ compatible = "allwinner,sun8i-a23-apb0-clk";
+ reg = <0x0800141c 0x4>;
+ #clock-cells = <0>;
+ clocks = <&ahbs>;
+ clock-output-names = "apbs";
+ };
+
+ apbs_gates: clk@08001428 {
+ compatible = "allwinner,sun9i-a80-apbs-gates-clk";
+ reg = <0x08001428 0x4>;
+ #clock-cells = <1>;
+ clocks = <&apbs>;
+ clock-indices = <0>, <1>,
+ <2>, <3>,
+ <4>, <5>,
+ <6>, <7>,
+ <12>, <13>,
+ <16>, <17>,
+ <18>, <20>;
+ clock-output-names = "apbs_pio", "apbs_ir",
+ "apbs_timer", "apbs_rsb",
+ "apbs_uart", "apbs_1wire",
+ "apbs_i2c0", "apbs_i2c1",
+ "apbs_ps2_0", "apbs_ps2_1",
+ "apbs_dma", "apbs_i2s0",
+ "apbs_i2s1", "apbs_twd";
+ };
+
+ r_1wire_clk: clk@08001450 {
+ reg = <0x08001450 0x4>;
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ clocks = <&osc32k>, <&osc24M>;
+ clock-output-names = "r_1wire";
+ };
+
+ r_ir_clk: clk@08001454 {
+ reg = <0x08001454 0x4>;
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ clocks = <&osc32k>, <&osc24M>;
+ clock-output-names = "r_ir";
+ };
};
soc {
};
mmc0: mmc@01c0f000 {
- compatible = "allwinner,sun5i-a13-mmc";
+ compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
<&mmc0_clk 1>, <&mmc0_clk 2>;
};
mmc1: mmc@01c10000 {
- compatible = "allwinner,sun5i-a13-mmc";
+ compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
<&mmc1_clk 1>, <&mmc1_clk 2>;
};
mmc2: mmc@01c11000 {
- compatible = "allwinner,sun5i-a13-mmc";
+ compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c11000 0x1000>;
clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
<&mmc2_clk 1>, <&mmc2_clk 2>;
};
mmc3: mmc@01c12000 {
- compatible = "allwinner,sun5i-a13-mmc";
+ compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c12000 0x1000>;
clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
<&mmc3_clk 1>, <&mmc3_clk 2>;
clocks = <&apb0_gates 5>;
gpio-controller;
interrupt-controller;
- #interrupt-cells = <2>;
+ #interrupt-cells = <3>;
#size-cells = <0>;
#gpio-cells = <3>;
mmc2_8bit_pins: mmc2_8bit {
allwinner,pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11", "PC12",
- "PC13", "PC14", "PC15";
+ "PC13", "PC14", "PC15",
+ "PC16";
allwinner,function = "mmc2";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
};
+ apbs_rst: reset@080014b0 {
+ reg = <0x080014b0 0x4>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ #reset-cells = <1>;
+ };
+
+ nmi_intc: interrupt-controller@080015a0 {
+ compatible = "allwinner,sun9i-a80-nmi";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x080015a0 0xc>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ r_ir: ir@08002000 {
+ compatible = "allwinner,sun5i-a13-ir";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_pins>;
+ clocks = <&apbs_gates 1>, <&r_ir_clk>;
+ clock-names = "apb", "ir";
+ resets = <&apbs_rst 1>;
+ reg = <0x08002000 0x40>;
+ status = "disabled";
+ };
+
r_uart: serial@08002800 {
compatible = "snps,dw-apb-uart";
reg = <0x08002800 0x400>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc24M>;
+ clocks = <&apbs_gates 4>;
+ resets = <&apbs_rst 4>;
status = "disabled";
};
+
+ r_pio: pinctrl@08002c00 {
+ compatible = "allwinner,sun9i-a80-r-pinctrl";
+ reg = <0x08002c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbs_gates 0>;
+ resets = <&apbs_rst 0>;
+ gpio-controller;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ r_ir_pins: r_ir {
+ allwinner,pins = "PL6";
+ allwinner,function = "s_cir_rx";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ r_rsb_pins: r_rsb {
+ allwinner,pins = "PN0", "PN1";
+ allwinner,function = "s_rsb";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+ };
+
+ r_rsb: i2c@08003400 {
+ compatible = "allwinner,sun8i-a23-rsb";
+ reg = <0x08003400 0x400>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbs_gates 3>;
+ clock-frequency = <3000000>;
+ resets = <&apbs_rst 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_rsb_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
};
--- /dev/null
+/*
+ * Copyright 2015 - Marcus Cooper <codekipper@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+#include "axp209.dtsi"
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
voltage = <400000>;
};
};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier PH1-LD11 Reference Board
+ *
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-ld11.dtsi"
+/include/ "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier PH1-LD11 Reference Board";
+ compatible = "socionext,ph1-ld11-ref", "socionext,ph1-ld11";
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0x40000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ };
+};
+
+ðsc {
+ interrupts = <0 48 4>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier PH1-LD11 SoC
+ *
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/ {
+ compatible = "socionext,ph1-ld11";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0x000>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x80000100>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0x001>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x80000100>;
+ };
+ };
+
+ clocks {
+ uart_clk: uart_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <58820000>;
+ };
+
+ i2c_clk: i2c_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0xf01>,
+ <1 14 0xf01>,
+ <1 11 0xf01>,
+ <1 10 0xf01>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&uart_clk>;
+ clock-frequency = <58820000>;
+ };
+
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&uart_clk>;
+ clock-frequency = <58820000>;
+ };
+
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&uart_clk>;
+ clock-frequency = <58820000>;
+ };
+
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 177 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&uart_clk>;
+ clock-frequency = <58820000>;
+ };
+
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c4: i2c@58784000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58784000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 45 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ };
+
+ smpctrl@59800000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
+
+ pinctrl: pinctrl@5f801000 {
+ compatible = "socionext,ph1-ld11-pinctrl", "syscon";
+ reg = <0x5f801000 0xe00>;
+ };
+
+ gic: interrupt-controller@5fe00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x5fe00000 0x10000>, /* GICD */
+ <0x5fe40000 0x80000>; /* GICR */
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <1 9 4>;
+ };
+ };
+};
+
+/include/ "uniphier-pinctrl.dtsi"
--- /dev/null
+/*
+ * Device Tree Source for UniPhier PH1-LD20 Reference Board
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-ld20.dtsi"
+/include/ "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier PH1-LD20 Reference Board";
+ compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20";
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0xc0000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ };
+};
+
+ðsc {
+ interrupts = <0 48 4>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier PH1-LD20 SoC
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/ {
+ compatible = "socionext,ph1-ld20";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu2>;
+ };
+ core1 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x000>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x80000100>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x001>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x80000100>;
+ };
+
+ cpu2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0x100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x80000100>;
+ };
+
+ cpu3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0x101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x80000100>;
+ };
+ };
+
+ clocks {
+ uart_clk: uart_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <58820000>;
+ };
+
+ i2c_clk: i2c_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0xf01>,
+ <1 14 0xf01>,
+ <1 11 0xf01>,
+ <1 10 0xf01>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&uart_clk>;
+ clock-frequency = <58820000>;
+ };
+
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&uart_clk>;
+ clock-frequency = <58820000>;
+ };
+
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&uart_clk>;
+ clock-frequency = <58820000>;
+ };
+
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 177 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&uart_clk>;
+ clock-frequency = <58820000>;
+ };
+
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c4: i2c@58784000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58784000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 45 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ };
+
+ smpctrl@59800000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
+
+ pinctrl: pinctrl@5f801000 {
+ compatible = "socionext,ph1-ld20-pinctrl", "syscon";
+ reg = <0x5f801000 0xe00>;
+ };
+
+ gic: interrupt-controller@5fe00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x5fe00000 0x10000>, /* GICD */
+ <0x5fe80000 0x80000>; /* GICR */
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <1 9 4>;
+ };
+ };
+};
+
+/include/ "uniphier-pinctrl.dtsi"
/dts-v1/;
/include/ "uniphier-ph1-ld4.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
/ {
model = "UniPhier PH1-LD4 Reference Board";
};
};
+ðsc {
+ interrupts = <0 49 4>;
+};
+
&serial0 {
status = "okay";
};
/dts-v1/;
/include/ "uniphier-ph1-ld6b.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
/ {
model = "UniPhier PH1-LD6b Reference Board";
};
};
+ðsc {
+ interrupts = <0 52 4>;
+};
+
&serial0 {
status = "okay";
};
/dts-v1/;
/include/ "uniphier-ph1-pro4.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
/ {
model = "UniPhier PH1-Pro4 Reference Board";
};
};
+ðsc {
+ interrupts = <0 50 4>;
+};
+
&serial0 {
status = "okay";
};
/dts-v1/;
/include/ "uniphier-ph1-sld3.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
/ {
model = "UniPhier PH1-sLD3 Reference Board";
};
};
+ðsc {
+ interrupts = <0 49 4>;
+};
+
&serial0 {
status = "okay";
};
status = "okay";
};
+&emmc {
+ status = "okay";
+};
+
&sd {
status = "okay";
};
/dts-v1/;
/include/ "uniphier-ph1-sld8.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
/ {
model = "UniPhier PH1-sLD8 Reference Board";
};
};
+ðsc {
+ interrupts = <0 48 4>;
+};
+
&serial0 {
status = "okay";
};
function = "i2c3";
};
+ pinctrl_i2c4: i2c4_grp {
+ groups = "i2c4";
+ function = "i2c4";
+ };
+
+ pinctrl_nand: nand_grp {
+ groups = "nand";
+ function = "nand";
+ };
+
pinctrl_sd: sd_grp {
groups = "sd";
function = "sd";
--- /dev/null
+/*
+ * Device Tree Source for UniPhier Support Card (Expansion Board)
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+&system_bus {
+ status = "okay";
+ ranges = <1 0x00000000 0x42000000 0x02000000>;
+
+ support_card: support_card {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 1 0x01f00000 0x00100000>;
+
+ ethsc: ethernet@00000000 {
+ compatible = "smsc,lan9118", "smsc,lan9115";
+ reg = <0x00000000 0x1000>;
+ phy-mode = "mii";
+ reg-io-width = <4>;
+ };
+
+ serialsc: uart@000b0000 {
+ compatible = "ns16550a";
+ reg = <0x000b0000 0x20>;
+ clock-frequency = <12288000>;
+ reg-shift = <1>;
+ };
+ };
+};
model = "VF610 Tower Board";
compatible = "fsl,vf610-twr", "fsl,vf610";
- choosen {
+ chosen {
stdout-path = &uart1;
};
#define BOOT_DEVICE_NAND_I2C 0x06
#define BOOT_DEVICE_MMC1 0x08
#define BOOT_DEVICE_MMC2 0x09
-#define BOOT_DEVICE_SPI 0x15
+#define BOOT_DEVICE_SPI 0x0B
#define BOOT_DEVICE_UART 0x41
#define BOOT_DEVICE_USBETH 0x44
#define BOOT_DEVICE_CPGMAC 0x46
*/
#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
#define CONFIG_MAX_CPUS 16
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#ifdef CONFIG_LS2080A
-#define CONFIG_NUM_DDR_CONTROLLERS 2
-#endif
-#ifdef CONFIG_LS2085A
#define CONFIG_NUM_DDR_CONTROLLERS 3
-#define CONFIG_SYS_FSL_HAS_DP_DDR
-#endif
+#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
#define CONFIG_SYS_FSL_SRDS_1
/* SMMU Defintions */
#define SMMU_BASE 0x05000000 /* GR0 Base */
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* SEC */
+#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SEC_COMPAT 5
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
+
+/* DCFG - GUR */
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+
/* Cache Coherent Interconnect */
#define CCI_MN_BASE 0x04000000
#define CCI_MN_RNF_NODEID_LIST 0x180
#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
+#define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
+
/* TZ Protection Controller Definitions */
#define TZPC_BASE 0x02200000
#define TZPCR0SIZE_BASE (TZPC_BASE)
#define CONFIG_SYS_FSL_ERRATUM_A008751
#define CONFIG_SYS_FSL_ERRATUM_A009635
#define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_ERRATUM_A009803
#define CONFIG_SYS_FSL_ERRATUM_A009942
/* ARM A57 CORE ERRATA */
CPU_TYPE_ENTRY(LS2085, LS2085, 8),
CPU_TYPE_ENTRY(LS2045, LS2045, 4),
CPU_TYPE_ENTRY(LS1043, LS1043, 4),
+ CPU_TYPE_ENTRY(LS1023, LS1023, 2),
CPU_TYPE_ENTRY(LS2040, LS2040, 4),
};
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
- CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
+ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
#endif
};
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE,
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
- CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
+ CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL,
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
#endif
};
#endif
#include <config.h>
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
enum srds_prtcl {
NONE = 0,
PCIE1,
#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000)
#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000)
+/* SFP */
+#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
+
+/* SEC */
+#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x07000000)
+#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x07010000)
+
+/* Security Monitor */
+#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
+
+/* MMU 500 */
+#define SMMU_SCR0 (SMMU_BASE + 0x0)
+#define SMMU_SCR1 (SMMU_BASE + 0x4)
+#define SMMU_SCR2 (SMMU_BASE + 0x8)
+#define SMMU_SACR (SMMU_BASE + 0x10)
+#define SMMU_IDR0 (SMMU_BASE + 0x20)
+#define SMMU_IDR1 (SMMU_BASE + 0x24)
+
+#define SMMU_NSCR0 (SMMU_BASE + 0x400)
+#define SMMU_NSCR2 (SMMU_BASE + 0x408)
+#define SMMU_NSACR (SMMU_BASE + 0x410)
+
+#define SCR0_CLIENTPD_MASK 0x00000001
+#define SCR0_USFCFG_MASK 0x00000400
+
+
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define PCIE_LUT_BASE 0x80000
#define PCIE_LUT_LCTRL0 0x7F8
#define PCIE_LUT_DBG 0x7FC
+#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
+#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
+#define PCIE_LUT_ENABLE (1 << 31)
+#define PCIE_LUT_ENTRY_COUNT 32
/* Device Configuration */
#define DCFG_BASE 0x01e00000
#define DCFG_DCSR_BASE 0X700100000ULL
#define DCFG_DCSR_PORCR1 0x000
+/* Interrupt Sampling Control */
+#define ISC_BASE 0x01F70000
+#define IRQCR_OFFSET 0x14
+
/* Supplemental Configuration */
#define SCFG_BASE 0x01fc0000
#define SCFG_USB3PRM1CR 0x000
u8 res_008[0x20-0x8];
u32 gpporcr1; /* General-purpose POR configuration */
u32 gpporcr2; /* General-purpose POR configuration 2 */
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
u32 dcfg_fusesr; /* Fuse status register */
u32 gpporcr3;
u32 gpporcr4;
#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000
#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
+#define RCW_SB_EN_REG_INDEX 9
+#define RCW_SB_EN_MASK 0x00000400
u8 res_180[0x200-0x180];
u32 scratchrw[32]; /* Scratch Read/Write */
#ifndef __FSL_STREAM_ID_H
#define __FSL_STREAM_ID_H
-/* Stream IDs on ls2080a devices are not hardwired and are
+/*
+ * Stream IDs on ls2080a devices are not hardwired and are
* programmed by sw. There are a limited number of stream IDs
* available, and the partitioning of them is scenario dependent.
* This header defines the partitioning between legacy, PCI,
* and DPAA2 devices.
*
- * This partitiong can be customized in this file depending
- * on the specific hardware config-- e.g. perhaps not all
- * PEX controllers are in use.
+ * This partitioning can be customized in this file depending
+ * on the specific hardware config:
+ *
+ * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
+ * -all legacy devices get a unique stream ID assigned and programmed in
+ * their AMQR registers by u-boot
+ *
+ * -PCIe
+ * -there is a range of stream IDs set aside for PCI in this
+ * file. U-boot will scan the PCI bus and for each device discovered:
+ * -allocate a streamID
+ * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
+ * -set a msi-map entry in the PEXn controller node in the
+ * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
+ * for more info on the msi-map definition)
*
- * On LS2080 stream IDs are programmed in AMQ registers (32-bits) for
+ * -DPAA2
+ * -u-boot will allocate a range of stream IDs to be used by the Management
+ * Complex for containers and will set these values in the MC DPC image.
+ * -the MC is responsible for allocating and setting up 'isolation context
+ * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
+ *
+ * On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for
* each of the different bus masters. The relationship between
* the AMQ registers and stream IDs is defined in the table below:
* AMQ bit streamID bit
* ---------------------------
- * PL[18] 9
- * BMT[17] 8
- * VA[16] 7
- * [15] -
- * ICID[14:7] -
- * ICID[6:0] 6-0
+ * PL[18] 9 // privilege bit
+ * BMT[17] 8 // bypass translation
+ * VA[16] 7 // reserved
+ * [15] - // unused
+ * ICID[14:7] - // unused
+ * ICID[6:0] 6-0 // isolation context id
* ----------------------------
+ *
*/
#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */
#define FSL_SATA2_STREAM_ID 5
#define FSL_DMA_STREAM_ID 6
-/* PCI - programmed in PEXn_LUT by OS */
-/* 4 IDs per controller */
-#define FSL_PEX1_STREAM_ID_START 7
-#define FSL_PEX1_STREAM_ID_END 10
-#define FSL_PEX2_STREAM_ID_START 11
-#define FSL_PEX2_STREAM_ID_END 14
-#define FSL_PEX3_STREAM_ID_START 15
-#define FSL_PEX3_STREAM_ID_END 18
-#define FSL_PEX4_STREAM_ID_START 19
-#define FSL_PEX4_STREAM_ID_END 22
+/* PCI - programmed in PEXn_LUT */
+#define FSL_PEX_STREAM_ID_START 7
+#define FSL_PEX_STREAM_ID_END 22
/* DPAA2 - set in MC DPC and alloced by MC */
#define FSL_DPAA2_STREAM_ID_START 23
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
#define SVR_WO_E 0xFFFFFE
-#define SVR_LS1043 0x879204
+#define SVR_LS1043 0x879200
+#define SVR_LS1023 0x879208
#define SVR_LS2045 0x870120
#define SVR_LS2080 0x870110
#define SVR_LS2085 0x870100
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
void erratum_a009635(void);
#endif
+
+bool soc_has_dp_ddr(void);
+bool soc_has_aiop(void);
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
#endif
#define FSL_IFC_COMPAT "fsl,ifc"
-#define FSL_QSPI_COMPAT "fsl,ls1-qspi"
-#define FSL_DSPI_COMPAT "fsl,vf610-dspi"
+#define FSL_QSPI_COMPAT "fsl,ls1021a-qspi"
+#define FSL_DSPI_COMPAT "fsl,ls1021a-v1.0-dspi"
#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
CSU_CSLX_FTM5,
CSU_CSLX_FTM8,
CSU_CSLX_FTM7,
- CSU_CSLX_COP_DCSR,
CSU_CSLX_EPU,
- CSU_CSLX_GDI,
+ CSU_CSLX_COP_DCSR,
CSU_CSLX_DDI,
+ CSU_CSLX_GDI,
CSU_CSLX_RESERVED1,
- CSU_CSLX_USB3_PHY = 117,
+ CSU_CSLX_USB3_PHY = 116,
CSU_CSLX_RESERVED2,
CSU_CSLX_MAX,
};
u32 din; /* 0x1060c */
u32 irq_cause; /* 0x10610 */
u32 irq_mask; /* 0x10614 */
+ u32 timing1; /* 0x10618 */
+ u32 timing2; /* 0x1061c */
+ u32 dw_cfg; /* 0x10620 - Direct Write Configuration */
};
/* They are used to define CONFIG_SYS_KW_SPI_MPP
#define SCK_MPP10 (1 << 1)
#define MISO_MPP11 (1 << 2)
+/* Control Register */
+#define KWSPI_CSN_ACT (1 << 0) /* Activates serial memory interface */
+#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */
+#define KWSPI_CS_SHIFT 2 /* chip select shift */
+#define KWSPI_CS_MASK 0x7 /* chip select mask */
+
+/* Configuration Register */
#define KWSPI_CLKPRESCL_MASK 0x1f
#define KWSPI_CLKPRESCL_MIN 0x12
-#define KWSPI_CSN_ACT 1 /* Activates serial memory interface */
-#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */
-#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */
-#define KWSPI_IRQMASK 0 /* mask SPI interrupt */
-#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */
#define KWSPI_XFERLEN_1BYTE 0
#define KWSPI_XFERLEN_2BYTE (1 << 5)
#define KWSPI_XFERLEN_MASK (1 << 5)
#define KWSPI_ADRLEN_3BYTE (2 << 8)
#define KWSPI_ADRLEN_4BYTE (3 << 8)
#define KWSPI_ADRLEN_MASK (3 << 8)
+
+#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */
+#define KWSPI_IRQMASK 0 /* mask SPI interrupt */
+#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */
+
#define KWSPI_TIMEOUT 10000
#endif /* __KW_SPI_H__ */
void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
struct iodelay_cfg_entry const *iodelay,
int niodelays);
+int __recalibrate_iodelay_start(void);
+void __recalibrate_iodelay_end(int ret);
+int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
+ int niodelays);
#endif
#define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F
#define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F
#define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F
+#define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F
/* UART */
#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
u32 csr;
};
-struct stm32_flash_regs {
- u32 acr;
- u32 key;
- u32 optkeyr;
- u32 sr;
- u32 cr;
- u32 optcr;
- u32 optcr1;
-};
-
/*
* Registers access macros
*/
#define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000)
#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE)
-#define STM32_FLASH_BASE (STM32_AHB1PERIPH_BASE + 0x3C00)
-#define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_BASE)
-
-#define STM32_FLASH_SR_BSY (1 << 16)
-
-#define STM32_FLASH_CR_PG (1 << 0)
-#define STM32_FLASH_CR_SER (1 << 1)
-#define STM32_FLASH_CR_STRT (1 << 16)
-#define STM32_FLASH_CR_LOCK (1 << 31)
-#define STM32_FLASH_CR_SNB_OFFSET 3
-#define STM32_FLASH_CR_SNB_MASK (15 << STM32_FLASH_CR_SNB_OFFSET)
-
/*
* Peripheral base addresses
*/
#define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800)
#define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400)
+#define FLASH_CNTL_BASE (STM32_AHB1PERIPH_BASE + 0x3C00)
+
+static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
+ [0 ... 3] = 16 * 1024,
+ [4] = 64 * 1024,
+ [5 ... 11] = 128 * 1024
+};
+
enum clock {
CLOCK_CORE,
CLOCK_AHB,
int configure_clocks(void);
unsigned long clock_get(enum clock clck);
+void stm32_flash_latency_cfg(int latency);
#endif /* _MACH_STM32_H_ */
#define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x4A0000140)
+static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
+ [0 ... 3] = 32 * 1024,
+ [4] = 128 * 1024,
+ [5 ... 7] = 256 * 1024
+};
+
enum clock {
CLOCK_CORE,
CLOCK_AHB,
/* clock control module regs definition */
#if defined(CONFIG_MACH_SUN8I_A83T)
#include <asm/arch/clock_sun8i_a83t.h>
-#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
+#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
+ defined(CONFIG_MACH_SUN50I)
#include <asm/arch/clock_sun6i.h>
#elif defined(CONFIG_MACH_SUN9I)
#include <asm/arch/clock_sun9i.h>
#define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30)
#define CCM_HDMI_CTRL_GATE (0x1 << 31)
-#ifndef CONFIG_MACH_SUN8I
-#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */
-#else
+#if defined(CONFIG_MACH_SUN50I)
+#define MBUS_CLK_DEFAULT 0x81000002 /* PLL6x2 / 3 */
+#elif defined(CONFIG_MACH_SUN8I)
#define MBUS_CLK_DEFAULT 0x81000003 /* PLL6 / 4 */
+#else
+#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */
#endif
#define MBUS_CLK_GATE (0x1 << 31)
#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
-#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
+#define CCM_USB_CTRL_HSIC_RST (0x1 << 2)
/* There is no global phy clk gate on sun6i, define as 0 */
#define CCM_USB_CTRL_PHYGATE 0
#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8)
#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
-#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
+#define CCM_USB_CTRL_HSIC_CLK (0x1 << 10)
+#define CCM_USB_CTRL_12M_CLK (0x1 << 11)
#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
-#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
#define SUNXI_AD_DA_BASE 0x01c22c00
#define SUNXI_KEYPAD_BASE 0x01c23000
#define SUNXI_TZPC_BASE 0x01c23400
+
+#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3)
+/* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */
+#define SUNXI_SID_BASE 0x01c14200
+#else
#define SUNXI_SID_BASE 0x01c23800
+#endif
+
#define SUNXI_SJTAG_BASE 0x01c23c00
#define SUNXI_TP_BASE 0x01c25000
#define SUN8I_GPB_UART2 2
#define SUN8I_A33_GPB_UART0 3
#define SUN8I_A83T_GPB_UART0 2
+#define SUN50I_GPB_UART0 4
#define SUNXI_GPC_NAND 2
#define SUNXI_GPC_SDC2 3
#define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */
#define SPL_HEADER_VERSION 1
-/* Note: A80 will require special handling here: SPL_ADDR 0x10000 */
+#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
+#define SPL_ADDR 0x10000
+#else
#define SPL_ADDR 0x0
+#endif
/* boot head definition from sun4i boot code */
struct boot_file_head {
void return_to_fel(uint32_t lr, uint32_t sp);
/* Board / SoC level designware gmac init */
-int sunxi_gmac_initialize(bd_t *bis);
+#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUNXI_GMAC
+void eth_init_board(void);
+#else
+static inline void eth_init_board(void) {}
+#endif
#endif
#ifdef CONFIG_CHAIN_OF_TRUST
#define CONFIG_CMD_ESBC_VALIDATE
#define CONFIG_CMD_BLOB
+#define CONFIG_CMD_HASH
#define CONFIG_FSL_SEC_MON
+#define CONFIG_SHA_HW_ACCEL
#define CONFIG_SHA_PROG_HW_ACCEL
#define CONFIG_RSA_FREESCALE_EXP
* The feature is only applicable in case of NOR boot and is
* not applicable in case of RAMBOOT (NAND, SD, SPI).
*/
+#ifndef CONFIG_ESBC_HDR_LS
+/* Current Key EXT feature not available in LS ESBC Header */
#define CONFIG_FSL_ISBC_KEY_EXT
#endif
-#ifdef CONFIG_LS1043A
-/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */
+#endif
+
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A)
+/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
+ * Similiarly for LS2080
+ */
#define CONFIG_ESBC_ADDR_64BIT
#endif
+#ifdef CONFIG_LS2080A
+#define CONFIG_EXTRA_ENV \
+ "setenv fdt_high 0xa0000000;" \
+ "setenv initrd_high 0xcfffffff;" \
+ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
+#else
#define CONFIG_EXTRA_ENV \
"setenv fdt_high 0xcfffffff;" \
"setenv initrd_high 0xcfffffff;" \
"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
+#endif
-/* The address needs to be modified according to NOR memory map */
-#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a0000
+/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
+ * Non-XIP Memory (Nand/SD)*/
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A)
+#define CONFIG_BOOTSCRIPT_COPY_RAM
+#endif
+/* The address needs to be modified according to NOR and DDR memory map */
+#ifdef CONFIG_LS2080A
+#define CONFIG_BS_HDR_ADDR_FLASH 0x583920000
+#define CONFIG_BS_ADDR_FLASH 0x583900000
+#define CONFIG_BS_HDR_ADDR_RAM 0xa3920000
+#define CONFIG_BS_ADDR_RAM 0xa3900000
+#else
+#define CONFIG_BS_HDR_ADDR_FLASH 0x600a0000
+#define CONFIG_BS_ADDR_FLASH 0x60060000
+#define CONFIG_BS_HDR_ADDR_RAM 0xa0060000
+#define CONFIG_BS_ADDR_RAM 0xa0060000
+#endif
+
+#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
+#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
+#define CONFIG_BS_HDR_SIZE 0x00002000
+#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM
+#define CONFIG_BS_SIZE 0x00001000
+#else
+#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_FLASH
+/* BS_HDR_SIZE, BOOTSCRIPT_ADDR and BS_SIZE are not required */
+#endif
#include <config_fsl_chain_trust.h>
#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
*/
#ifndef __ASM_ARCH_MXC_MXC_I2C_H__
#define __ASM_ARCH_MXC_MXC_I2C_H__
+#include <asm-generic/gpio.h>
#include <asm/imx-common/iomux-v3.h>
struct i2c_pin_ctrl {
* The following two is only to be compatible with non-DM part.
* @idle_bus_fn: function to force bus idle
* @idle_bus_data: parameter for idle_bus_fun
+ * For DM:
+ * bus: The device structure for i2c bus controller
+ * scl-gpio: specify the gpio related to SCL pin
+ * sda-gpio: specify the gpio related to SDA pin
*/
struct mxc_i2c_bus {
/*
#ifndef CONFIG_DM_I2C
int (*idle_bus_fn)(void *p);
void *idle_bus_data;
+#else
+ struct udevice *bus;
+ /* Use gpio to force bus idle when bus state is abnormal */
+ struct gpio_desc scl_gpio;
+ struct gpio_desc sda_gpio;
#endif
};
#define insw_p(port,to,len) insw(port,to,len)
#define insl_p(port,to,len) insl(port,to,len)
+#define writesl(a, d, s) __raw_writesl((unsigned long)a, d, s)
+#define readsl(a, d, s) __raw_readsl((unsigned long)a, d, s)
+#define writesw(a, d, s) __raw_writesw((unsigned long)a, d, s)
+#define readsw(a, d, s) __raw_readsw((unsigned long)a, d, s)
+#define writesb(a, d, s) __raw_writesb((unsigned long)a, d, s)
+#define readsb(a, d, s) __raw_readsb((unsigned long)a, d, s)
+
/*
* ioremap and friends.
*
#define DRA752_ES1_1 0x07520110
#define DRA752_ES2_0 0x07520200
#define DRA722_ES1_0 0x07220100
+#define DRA722_ES2_0 0x07220200
/*
* SRAM scratch space entries
#define MMU_SECTION_SHIFT 21
#define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
+/* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */
enum dcache_option {
- DCACHE_OFF = 0x3,
+ DCACHE_OFF = 0 << 2,
+ DCACHE_WRITETHROUGH = 3 << 2,
+ DCACHE_WRITEBACK = 4 << 2,
+ DCACHE_WRITEALLOC = 4 << 2,
};
#define isb() \
#define CR_AFE (1 << 29) /* Access flag enable */
#define CR_TE (1 << 30) /* Thumb exception enable */
-#ifndef PGTABLE_SIZE
+#if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE)
+#define PGTABLE_SIZE (4096 * 5)
+#elif !defined(PGTABLE_SIZE)
#define PGTABLE_SIZE (4096 * 4)
#endif
#define wfi()
#endif
+static inline unsigned long get_cpsr(void)
+{
+ unsigned long cpsr;
+
+ asm volatile("mrs %0, cpsr" : "=r"(cpsr): );
+ return cpsr;
+}
+
+static inline int is_hyp(void)
+{
+#ifdef CONFIG_ARMV7_LPAE
+ /* HYP mode requires LPAE ... */
+ return ((get_cpsr() & 0x1f) == 0x1a);
+#else
+ /* ... so without LPAE support we can optimize all hyp code away */
+ return 0;
+#endif
+}
+
static inline unsigned int get_cr(void)
{
unsigned int val;
- asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
+
+ if (is_hyp())
+ asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val)
+ :
+ : "cc");
+ else
+ asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val)
+ :
+ : "cc");
return val;
}
static inline void set_cr(unsigned int val)
{
- asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
- : : "r" (val) : "cc");
+ if (is_hyp())
+ asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" :
+ : "r" (val)
+ : "cc");
+ else
+ asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" :
+ : "r" (val)
+ : "cc");
isb();
}
isb();
}
-#ifdef CONFIG_CPU_V7
+#ifdef CONFIG_ARMV7_LPAE
+/* Long-Descriptor Translation Table Level 1/2 Bits */
+#define TTB_SECT_XN_MASK (1ULL << 54)
+#define TTB_SECT_NG_MASK (1 << 11)
+#define TTB_SECT_AF (1 << 10)
+#define TTB_SECT_SH_MASK (3 << 8)
+#define TTB_SECT_NS_MASK (1 << 5)
+#define TTB_SECT_AP (1 << 6)
+/* Note: TTB AP bits are set elsewhere */
+#define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */
+#define TTB_SECT (1 << 0)
+#define TTB_PAGETABLE (3 << 0)
+
+/* TTBCR flags */
+#define TTBCR_EAE (1 << 31)
+#define TTBCR_T0SZ(x) ((x) << 0)
+#define TTBCR_T1SZ(x) ((x) << 16)
+#define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
+#define TTBCR_IRGN0_NC (0 << 8)
+#define TTBCR_IRGN0_WBWA (1 << 8)
+#define TTBCR_IRGN0_WT (2 << 8)
+#define TTBCR_IRGN0_WBNWA (3 << 8)
+#define TTBCR_IRGN0_MASK (3 << 8)
+#define TTBCR_ORGN0_NC (0 << 10)
+#define TTBCR_ORGN0_WBWA (1 << 10)
+#define TTBCR_ORGN0_WT (2 << 10)
+#define TTBCR_ORGN0_WBNWA (3 << 10)
+#define TTBCR_ORGN0_MASK (3 << 10)
+#define TTBCR_SHARED_NON (0 << 12)
+#define TTBCR_SHARED_OUTER (2 << 12)
+#define TTBCR_SHARED_INNER (3 << 12)
+#define TTBCR_EPD0 (0 << 7)
+
+/*
+ * Memory types
+ */
+#define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \
+ (0xcc << (2 * 8)) | (0xff << (3 * 8)))
+
+/* options available for data cache on each page */
+enum dcache_option {
+ DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0),
+ DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
+ DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
+ DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
+};
+#elif defined(CONFIG_CPU_V7)
/* Short-Descriptor Translation Table Level 1 Bits */
#define TTB_SECT_NS_MASK (1 << 19)
#define TTB_SECT_NG_MASK (1 << 17)
#define TTB_SECT_S_MASK (1 << 16)
/* Note: TTB AP bits are set elsewhere */
+#define TTB_SECT_AP (3 << 10)
#define TTB_SECT_TEX(x) ((x & 0x7) << 12)
#define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
#define TTB_SECT_XN_MASK (1 << 4)
DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
};
#else
+#define TTB_SECT_AP (3 << 10)
/* options available for data cache on each page */
enum dcache_option {
DCACHE_OFF = 0x12,
/* Size of an MMU section */
enum {
- MMU_SECTION_SHIFT = 20,
+#ifdef CONFIG_ARMV7_LPAE
+ MMU_SECTION_SHIFT = 21, /* 2MB */
+#else
+ MMU_SECTION_SHIFT = 20, /* 1MB */
+#endif
MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
};
#endif /* CONFIG_ARM64 */
#ifdef CONFIG_PHYS_64BIT
-typedef unsigned long long dma_addr_t;
typedef unsigned long long phys_addr_t;
typedef unsigned long long phys_size_t;
#else
/* DMA addresses are 32-bits wide */
-typedef u32 dma_addr_t;
typedef unsigned long phys_addr_t;
typedef unsigned long phys_size_t;
#endif
+/*
+ * A dma_addr_t can hold any valid DMA address, i.e., any address returned
+ * by the DMA API.
+ *
+ * If the DMA API only uses 32-bit addresses, dma_addr_t need only be 32
+ * bits wide. Bus addresses, e.g., PCI BARs, may be wider than 32 bits,
+ * but drivers do memory-mapped I/O to ioremapped kernel virtual addresses,
+ * so they don't care about the size of the actual bus addresses.
+ */
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+typedef unsigned long long dma_addr_t;
+#else
+typedef u32 dma_addr_t;
+#endif
+
#endif /* __KERNEL__ */
typedef unsigned long resource_size_t;
void set_section_dcache(int section, enum dcache_option option)
{
+#ifdef CONFIG_ARMV7_LPAE
+ u64 *page_table = (u64 *)gd->arch.tlb_addr;
+ /* Need to set the access flag to not fault */
+ u64 value = TTB_SECT_AP | TTB_SECT_AF;
+#else
u32 *page_table = (u32 *)gd->arch.tlb_addr;
- u32 value;
+ u32 value = TTB_SECT_AP;
+#endif
+
+ /* Add the page offset */
+ value |= ((u32)section << MMU_SECTION_SHIFT);
- value = (section << MMU_SECTION_SHIFT) | (3 << 10);
+ /* Add caching bits */
value |= option;
+
+ /* Set PTE */
page_table[section] = value;
}
int i;
debug("%s: bank: %d\n", __func__, bank);
- for (i = bd->bi_dram[bank].start >> 20;
- i < (bd->bi_dram[bank].start >> 20) + (bd->bi_dram[bank].size >> 20);
+ for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
+ i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
+ (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
i++) {
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
set_section_dcache(i, DCACHE_WRITETHROUGH);
arm_init_before_mmu();
/* Set up an identity-mapping for all 4GB, rw for everyone */
- for (i = 0; i < 4096; i++)
+ for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
set_section_dcache(i, DCACHE_OFF);
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
dram_bank_mmu_setup(i);
}
-#ifdef CONFIG_CPU_V7
+#ifdef CONFIG_ARMV7_LPAE
+ /* Set up 4 PTE entries pointing to our 4 1GB page tables */
+ for (i = 0; i < 4; i++) {
+ u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
+ u64 tpt = gd->arch.tlb_addr + (4096 * i);
+ page_table[i] = tpt | TTB_PAGETABLE;
+ }
+
+ reg = TTBCR_EAE;
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+ reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
+#else
+ reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
+#endif
+
+ if (is_hyp()) {
+ /* Set HCTR to enable LPAE */
+ asm volatile("mcr p15, 4, %0, c2, c0, 2"
+ : : "r" (reg) : "memory");
+ /* Set HTTBR0 */
+ asm volatile("mcrr p15, 4, %0, %1, c2"
+ :
+ : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
+ : "memory");
+ /* Set HMAIR */
+ asm volatile("mcr p15, 4, %0, c10, c2, 0"
+ : : "r" (MEMORY_ATTRIBUTES) : "memory");
+ } else {
+ /* Set TTBCR to enable LPAE */
+ asm volatile("mcr p15, 0, %0, c2, c0, 2"
+ : : "r" (reg) : "memory");
+ /* Set 64-bit TTBR0 */
+ asm volatile("mcrr p15, 0, %0, %1, c2"
+ :
+ : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
+ : "memory");
+ /* Set MAIR */
+ asm volatile("mcr p15, 0, %0, c10, c2, 0"
+ : : "r" (MEMORY_ATTRIBUTES) : "memory");
+ }
+#elif defined(CONFIG_CPU_V7)
/* Set TTBR0 */
reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
ret
ENDPROC(ccn504_set_qos)
+/*************************************************************************
+ *
+ * void ccn504_set_aux(CCI_AUX_CONTROL_BASE, Value);
+ *
+ * Initialize AUX control settings
+ *
+ *************************************************************************/
+ENTRY(ccn504_set_aux)
+ /*
+ * x0: CCI_AUX_CONTROL_BASE
+ * x1: Value
+ */
+
+ ldr x9, [x0]
+ mov x10, x1
+ orr x9, x9, x10
+ str x9, [x0]
+
+ ret
+ENDPROC(ccn504_set_aux)
+
/*
* In the context of SPL, board_init_f must ensure that any clocks/etc for
* DDR are enabled, ensure that the stack pointer is valid, clear the BSS
- * and call board_init_f. We provide this version by default but mark it
+ * and call board_init_r. We provide this version by default but mark it
* as __weak to allow for platforms to do this in their own way if needed.
*/
void __weak board_init_f(ulong dummy)
+config BCM2835
+ bool "Broadcom BCM2835 SoC support"
+ depends on ARCH_BCM283X
+ select CPU_ARM1176
+
+config BCM2836
+ bool "Broadcom BCM2836 SoC support"
+ depends on ARCH_BCM283X
+ select ARMV7_LPAE
+ select CPU_V7
+
+config BCM2837
+ bool "Broadcom BCM2837 SoC support"
+ depends on ARCH_BCM283X
+
+config BCM2837_32B
+ bool "Broadcom BCM2837 SoC 32-bit support"
+ depends on ARCH_BCM283X
+ select BCM2837
+ select ARMV7_LPAE
+ select CPU_V7
+
+config BCM2837_64B
+ bool "Broadcom BCM2837 SoC 64-bit support"
+ depends on ARCH_BCM283X
+ select BCM2837
+ select ARM64
+
menu "Broadcom BCM283X family"
depends on ARCH_BCM283X
optional
config TARGET_RPI
- bool "Raspberry Pi"
- select CPU_ARM1176
+ bool "Raspberry Pi (all BCM2835 variants)"
+ help
+ Support for all ARM1176-/BCM2835-based Raspberry Pi variants, such as
+ the A, A+, B, B+, Compute Module, and Zero. This option cannot
+ support BCM2836/BCM2837-based Raspberry Pis such as the RPi 2 and
+ RPi 3 due to different peripheral address maps.
+
+ This option creates a build targetting the ARM1176 ISA.
+ select BCM2835
config TARGET_RPI_2
bool "Raspberry Pi 2"
- select CPU_V7
+ help
+ Support for all BCM2836-based Raspberry Pi variants, such as
+ the RPi 2 model B.
+
+ This option also supports BCM2837-based variants such as the RPi 3
+ Model B, when run in 32-bit mode, provided you have configured the
+ VideoCore firmware to select the PL011 UART for the console by:
+ a) config.txt should contain dtoverlay=pi3-miniuart-bt.
+ b) You should run the following to tell the VC FW to process DT when
+ booting, and copy u-boot.bin.img (rather than u-boot.bin) to the SD
+ card as the kernel image:
+
+ path/to/kernel/scripts/mkknlimg --dtok u-boot.bin u-boot.bin.img
+
+ This works as of firmware.git commit 046effa13ebc "firmware:
+ arm_loader: emmc clock depends on core clock See:
+ https://github.com/raspberrypi/firmware/issues/572".
+
+ This option creates a build targetting the ARMv7/AArch32 ISA.
+ select BCM2836
+
+config TARGET_RPI_3_32B
+ bool "Raspberry Pi 3 32-bit build"
+ help
+ Support for all BCM2837-based Raspberry Pi variants, such as
+ the RPi 3 model B, in AArch32 (32-bit) mode.
+
+ This option assumes the VideoCore firmware is configured to use the
+ mini UART (rather than PL011) for the serial console. This is the
+ default on the RPi 3. To enable the UART console, the following non-
+ default option must be present in config.txt: enable_uart=1. This is
+ required for U-Boot to operate correctly, even if you only care
+ about the HDMI/usbkbd console.
+
+ This option creates a build targetting the ARMv7/AArch32 ISA.
+ select BCM2837_32B
+
+config TARGET_RPI_3
+ bool "Raspberry Pi 3 64-bit build"
+ help
+ Support for all BCM2837-based Raspberry Pi variants, such as
+ the RPi 3 model B, in AArch64 (64-bit) mode.
+
+ This option assumes the VideoCore firmware is configured to use the
+ mini UART (rather than PL011) for the serial console. This is the
+ default on the RPi 3. To enable the UART console, the following non-
+ default option must be present in config.txt: enable_uart=1. This is
+ required for U-Boot to operate correctly, even if you only care
+ about the HDMI/usbkbd console.
+
+ At the time of writing, the VC FW requires a non-default option in
+ config.txt to request the ARM CPU boot in 64-bit mode:
+ arm_control=0x200
+
+ The VC FW typically provides ARM "stub" code to set up the CPU and
+ quiesce secondary SMP CPUs. This is not currently true in 64-bit
+ mode. In order to boot U-Boot before the VC FW is enhanced, please
+ see the commit description for the commit which added RPi3 support
+ for a workaround. Since the instructions are temporary, they are not
+ duplicated here. The VC FW enhancement is tracked in
+ https://github.com/raspberrypi/firmware/issues/579.
+
+ This option creates a build targetting the ARMv8/AArch64 ISA.
+ select BCM2837_64B
endchoice
config SYS_BOARD
- default "rpi" if TARGET_RPI
- default "rpi_2" if TARGET_RPI_2
+ default "rpi"
config SYS_VENDOR
default "raspberrypi"
default "bcm283x"
config SYS_CONFIG_NAME
- default "rpi" if TARGET_RPI
- default "rpi_2" if TARGET_RPI_2
+ default "rpi"
endmenu
# SPDX-License-Identifier: GPL-2.0
#
-obj-$(CONFIG_TARGET_RPI) += lowlevel_init.o
+obj-$(CONFIG_BCM2835) += lowlevel_init.o
obj-y += init.o reset.o mbox.o phys2bus.o
#ifndef _BCM2835_GPIO_H_
#define _BCM2835_GPIO_H_
-#ifdef CONFIG_BCM2836
+#ifndef CONFIG_BCM2835
#define BCM2835_GPIO_BASE 0x3f200000
#else
#define BCM2835_GPIO_BASE 0x20200000
/* Raw mailbox HW */
-#ifdef CONFIG_BCM2836
+#ifndef CONFIG_BCM2835
#define BCM2835_MBOX_PHYSADDR 0x3f00b880
#else
#define BCM2835_MBOX_PHYSADDR 0x2000b880
#ifndef _BCM2835_SDHCI_H_
#define _BCM2835_SDHCI_H_
-#ifdef CONFIG_BCM2836
+#ifndef CONFIG_BCM2835
#define BCM2835_SDHCI_BASE 0x3f300000
#else
#define BCM2835_SDHCI_BASE 0x20300000
#ifndef _BCM2835_TIMER_H
#define _BCM2835_TIMER_H
-#ifdef CONFIG_BCM2836
+#ifndef CONFIG_BCM2835
#define BCM2835_TIMER_PHYSADDR 0x3f003000
#else
#define BCM2835_TIMER_PHYSADDR 0x20003000
#ifndef _BCM2835_WDOG_H
#define _BCM2835_WDOG_H
-#ifdef CONFIG_BCM2836
+#ifndef CONFIG_BCM2835
#define BCM2835_WDOG_PHYSADDR 0x3f100000
#else
#define BCM2835_WDOG_PHYSADDR 0x20100000
return 0;
}
+
+#ifdef CONFIG_ARMV7_LPAE
+void enable_caches(void)
+{
+ dcache_enable();
+}
+#endif
(unsigned long)((void *)buffer +
roundup(buffer->buf_size, ARCH_DMA_MINALIGN)));
- ret = bcm2835_mbox_call_raw(chan, phys_to_bus((u32)buffer), &rbuffer);
+ ret = bcm2835_mbox_call_raw(chan,
+ phys_to_bus((unsigned long)buffer),
+ &rbuffer);
if (ret)
return ret;
(unsigned long)((void *)buffer +
roundup(buffer->buf_size, ARCH_DMA_MINALIGN)));
- if (rbuffer != phys_to_bus((u32)buffer)) {
+ if (rbuffer != phys_to_bus((unsigned long)buffer)) {
printf("mbox: Response buffer mismatch\n");
return -1;
}
unsigned long phys_to_bus(unsigned long phys)
{
-#ifdef CONFIG_BCM2836
+#ifndef CONFIG_BCM2835
return 0xc0000000 | phys;
#else
return 0x40000000 | phys;
#define KS2_LPSC_PCIE_1 27
#define KS2_LPSC_XGE 50
-/* MSMC */
-#define KS2_MSMC_SEGMENT_PCIE1 13
-
/* Chip Interrupt Controller */
#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */
#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */
#define KS2_LPSC_FFTC_B 49
#define KS2_LPSC_IQN_AIL 50
-/* MSMC */
-#define KS2_MSMC_SEGMENT_PCIE1 14
-
/* Chip Interrupt Controller */
#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
/* MSMC control */
#define KS2_MSMC_CTRL_BASE 0x0bc00000
#define KS2_MSMC_DATA_BASE 0x0c000000
-#ifndef CONFIG_SOC_K2G
-#define KS2_MSMC_SEGMENT_TETRIS 8
-#define KS2_MSMC_SEGMENT_NETCP 9
-#define KS2_MSMC_SEGMENT_QM_PDSP 10
-#define KS2_MSMC_SEGMENT_PCIE0 11
-#else
-#define KS2_MSMC_SEGMENT_TETRIS 1
-#define KS2_MSMC_SEGMENT_NETCP 4
-#define KS2_MSMC_SEGMENT_PCIE0 5
-#endif
+
+/* KS2 Generic Privilege ID Settings for MSMC2 */
+#define KS2_MSMC_SEGMENT_C6X_0 0
+#define KS2_MSMC_SEGMENT_C6X_1 1
+#define KS2_MSMC_SEGMENT_C6X_2 2
+#define KS2_MSMC_SEGMENT_C6X_3 3
+#define KS2_MSMC_SEGMENT_C6X_4 4
+#define KS2_MSMC_SEGMENT_C6X_5 5
+#define KS2_MSMC_SEGMENT_C6X_6 6
+#define KS2_MSMC_SEGMENT_C6X_7 7
+
+#define KS2_MSMC_SEGMENT_DEBUG 12
+
+/* KS2 HK/L/E MSMC PRIVIDs for MSMC2 */
+#define K2HKLE_MSMC_SEGMENT_ARM 8
+#define K2HKLE_MSMC_SEGMENT_NETCP 9
+#define K2HKLE_MSMC_SEGMENT_QM_PDSP 10
+#define K2HKLE_MSMC_SEGMENT_PCIE0 11
+
+/* K2HK specific Privilege ID Settings */
+#define K2HKE_MSMC_SEGMENT_HYPERLINK 14
+
+/* K2L specific Privilege ID Settings */
+#define K2L_MSMC_SEGMENT_PCIE1 14
+
+/* K2E specific Privilege ID Settings */
+#define K2E_MSMC_SEGMENT_PCIE1 13
+#define K2E_MSMC_SEGMENT_TSIP 15
+
+/* K2G specific Privilege ID Settings */
+#define K2G_MSMC_SEGMENT_ARM 1
+#define K2G_MSMC_SEGMENT_ICSS0 2
+#define K2G_MSMC_SEGMENT_ICSS1 3
+#define K2G_MSMC_SEGMENT_NSS 4
+#define K2G_MSMC_SEGMENT_PCIE 5
+#define K2G_MSMC_SEGMENT_USB 6
+#define K2G_MSMC_SEGMENT_MLB 8
+#define K2G_MSMC_SEGMENT_PMMC 9
+#define K2G_MSMC_SEGMENT_DSS 10
+#define K2G_MSMC_SEGMENT_MMC 11
/* MSMC segment size shift bits */
#define KS2_MSMC_SEG_SIZE_SHIFT 12
#define PSC_REG_MDSTAT(x) (0x800 + (4 * (x)))
#define PSC_REG_MDCTL(x) (0xa00 + (4 * (x)))
-#define BOOTBITMASK(x, y) ((((((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \
- (u32)1)) << ((u32)y)))
-#define BOOT_READ_BITFIELD(z, x, y) ((((u32)z) & BOOTBITMASK(x, y)) >> (y))
-#define BOOT_SET_BITFIELD(z, f, x, y) ((((u32)z) & ~BOOTBITMASK(x, y)) | \
- ((((u32)f) << (y)) & BOOTBITMASK(x, y)))
+static inline u32 _boot_bit_mask(u32 x, u32 y)
+{
+ u32 val = (1 << (x - y + 1)) - 1;
+ return val << y;
+}
+
+static inline u32 boot_read_bitfield(u32 z, u32 x, u32 y)
+{
+ u32 val = z & _boot_bit_mask(x, y);
+ return val >> y;
+}
+
+static inline u32 boot_set_bitfield(u32 z, u32 f, u32 x, u32 y)
+{
+ u32 mask = _boot_bit_mask(x, y);
+
+ return (z & ~mask) | ((f << y) & mask);
+}
/* PDCTL */
-#define PSC_REG_PDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 0, 0)
-#define PSC_REG_PDCTL_SET_PDMODE(x, y) BOOT_SET_BITFIELD((x), (y), 15, 12)
+#define PSC_REG_PDCTL_SET_NEXT(x, y) boot_set_bitfield((x), (y), 0, 0)
+#define PSC_REG_PDCTL_SET_PDMODE(x, y) boot_set_bitfield((x), (y), 15, 12)
/* PDSTAT */
-#define PSC_REG_PDSTAT_GET_STATE(x) BOOT_READ_BITFIELD((x), 4, 0)
+#define PSC_REG_PDSTAT_GET_STATE(x) boot_read_bitfield((x), 4, 0)
/* MDCFG */
-#define PSC_REG_MDCFG_GET_PD(x) BOOT_READ_BITFIELD((x), 20, 16)
-#define PSC_REG_MDCFG_GET_RESET_ISO(x) BOOT_READ_BITFIELD((x), 14, 14)
+#define PSC_REG_MDCFG_GET_PD(x) boot_read_bitfield((x), 20, 16)
+#define PSC_REG_MDCFG_GET_RESET_ISO(x) boot_read_bitfield((x), 14, 14)
/* MDCTL */
-#define PSC_REG_MDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 4, 0)
-#define PSC_REG_MDCTL_SET_LRSTZ(x, y) BOOT_SET_BITFIELD((x), (y), 8, 8)
-#define PSC_REG_MDCTL_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8)
-#define PSC_REG_MDCTL_SET_RESET_ISO(x, y) BOOT_SET_BITFIELD((x), (y), \
+#define PSC_REG_MDCTL_SET_NEXT(x, y) boot_set_bitfield((x), (y), 4, 0)
+#define PSC_REG_MDCTL_SET_LRSTZ(x, y) boot_set_bitfield((x), (y), 8, 8)
+#define PSC_REG_MDCTL_GET_LRSTZ(x) boot_read_bitfield((x), 8, 8)
+#define PSC_REG_MDCTL_SET_RESET_ISO(x, y) boot_set_bitfield((x), (y), \
12, 12)
/* MDSTAT */
-#define PSC_REG_MDSTAT_GET_STATUS(x) BOOT_READ_BITFIELD((x), 5, 0)
-#define PSC_REG_MDSTAT_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8)
-#define PSC_REG_MDSTAT_GET_LRSTDONE(x) BOOT_READ_BITFIELD((x), 9, 9)
-#define PSC_REG_MDSTAT_GET_MRSTZ(x) BOOT_READ_BITFIELD((x), 10, 10)
-#define PSC_REG_MDSTAT_GET_MRSTDONE(x) BOOT_READ_BITFIELD((x), 11, 11)
+#define PSC_REG_MDSTAT_GET_STATUS(x) boot_read_bitfield((x), 5, 0)
+#define PSC_REG_MDSTAT_GET_LRSTZ(x) boot_read_bitfield((x), 8, 8)
+#define PSC_REG_MDSTAT_GET_LRSTDONE(x) boot_read_bitfield((x), 9, 9)
+#define PSC_REG_MDSTAT_GET_MRSTZ(x) boot_read_bitfield((x), 10, 10)
+#define PSC_REG_MDSTAT_GET_MRSTDONE(x) boot_read_bitfield((x), 11, 11)
/* PDCTL states */
#define PSC_REG_VAL_PDCTL_NEXT_ON 1
__raw_writel(val, KS2_DEVCFG);
}
+static void msmc_k2hkle_common_setup(void)
+{
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
+ msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM);
+ msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP);
+#ifdef KS2_MSMC_SEGMENT_QM_PDSP
+ msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP);
+#endif
+ msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0);
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
+}
+
+static void msmc_k2hk_setup(void)
+{
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_4);
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_5);
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_6);
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_7);
+ msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
+}
+
+static inline void msmc_k2l_setup(void)
+{
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
+ msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1);
+}
+
+static inline void msmc_k2e_setup(void)
+{
+ msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1);
+ msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
+ msmc_share_all_segments(K2E_MSMC_SEGMENT_TSIP);
+}
+
+static void msmc_k2g_setup(void)
+{
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
+ msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM);
+ msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS0);
+ msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS1);
+ msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS);
+ msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE);
+ msmc_share_all_segments(K2G_MSMC_SEGMENT_USB);
+ msmc_share_all_segments(K2G_MSMC_SEGMENT_MLB);
+ msmc_share_all_segments(K2G_MSMC_SEGMENT_PMMC);
+ msmc_share_all_segments(K2G_MSMC_SEGMENT_DSS);
+ msmc_share_all_segments(K2G_MSMC_SEGMENT_MMC);
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
+}
+
int arch_cpu_init(void)
{
chip_configuration_unlock();
icache_enable();
- msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
- msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
-#ifdef KS2_MSMC_SEGMENT_QM_PDSP
- msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
-#endif
- msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
+ if (cpu_is_k2g()) {
+ msmc_k2g_setup();
+ } else {
+ msmc_k2hkle_common_setup();
+ if (cpu_is_k2e())
+ msmc_k2e_setup();
+ else if (cpu_is_k2l())
+ msmc_k2l_setup();
+ else
+ msmc_k2hk_setup();
+ }
/* Initialize the PCIe-0 to work as Root Complex */
config_pcie_mode(0, ROOTCOMPLEX);
#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
- msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
/* Initialize the PCIe-1 to work as Root Complex */
config_pcie_mode(1, ROOTCOMPLEX);
#endif
if ARCH_MVEBU
+config ARMADA_375
+ bool
+
config ARMADA_38X
bool
select ARMADA_38X
choice
- prompt "Marvell MVEBU (Armada XP/38x) board select"
+ prompt "Marvell MVEBU (Armada XP/375/38x) board select"
optional
config TARGET_CLEARFOG
bool "Support ClearFog"
select DB_88F6820_GP
+config TARGET_DB_88F6720
+ bool "Support DB-88F6720 Armada 375"
+ select ARMADA_375
+
config TARGET_DB_88F6820_GP
bool "Support DB-88F6820-GP"
select DB_88F6820_GP
config SYS_BOARD
default "clearfog" if TARGET_CLEARFOG
+ default "db-88f6720" if TARGET_DB_88F6720
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
default "ds414" if TARGET_DS414
config SYS_CONFIG_NAME
default "clearfog" if TARGET_CLEARFOG
+ default "db-88f6720" if TARGET_DB_88F6720
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
default "ds414" if TARGET_DS414
config SYS_VENDOR
default "Marvell" if TARGET_DB_MV784MP_GP
+ default "Marvell" if TARGET_DB_88F6720
default "Marvell" if TARGET_DB_88F6820_GP
default "solidrun" if TARGET_CLEARFOG
default "Synology" if TARGET_DS414
obj-y = cpu.o
obj-y += dram.o
ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
endif
case SOC_MV78260_ID:
case SOC_MV78460_ID:
return MVEBU_SOC_AXP;
+
+ case SOC_88F6720_ID:
+ return MVEBU_SOC_A375;
+
case SOC_88F6810_ID:
case SOC_88F6820_ID:
case SOC_88F6828_ID:
return MVEBU_SOC_A38X;
}
+
return MVEBU_SOC_UNKNOWN;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
-#if defined(CONFIG_ARMADA_38X)
+#if defined(CONFIG_ARMADA_375)
+/* SAR frequency values for Armada 375 */
+static const struct sar_freq_modes sar_freq_tab[] = {
+ { 0, 0x0, 266, 133, 266 },
+ { 1, 0x0, 333, 167, 167 },
+ { 2, 0x0, 333, 167, 222 },
+ { 3, 0x0, 333, 167, 333 },
+ { 4, 0x0, 400, 200, 200 },
+ { 5, 0x0, 400, 200, 267 },
+ { 6, 0x0, 400, 200, 400 },
+ { 7, 0x0, 500, 250, 250 },
+ { 8, 0x0, 500, 250, 334 },
+ { 9, 0x0, 500, 250, 500 },
+ { 10, 0x0, 533, 267, 267 },
+ { 11, 0x0, 533, 267, 356 },
+ { 12, 0x0, 533, 267, 533 },
+ { 13, 0x0, 600, 300, 300 },
+ { 14, 0x0, 600, 300, 400 },
+ { 15, 0x0, 600, 300, 600 },
+ { 16, 0x0, 666, 333, 333 },
+ { 17, 0x0, 666, 333, 444 },
+ { 18, 0x0, 666, 333, 666 },
+ { 19, 0x0, 800, 400, 267 },
+ { 20, 0x0, 800, 400, 400 },
+ { 21, 0x0, 800, 400, 534 },
+ { 22, 0x0, 900, 450, 300 },
+ { 23, 0x0, 900, 450, 450 },
+ { 24, 0x0, 900, 450, 600 },
+ { 25, 0x0, 1000, 500, 500 },
+ { 26, 0x0, 1000, 500, 667 },
+ { 27, 0x0, 1000, 333, 500 },
+ { 28, 0x0, 400, 400, 400 },
+ { 29, 0x0, 1100, 550, 550 },
+ { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
+};
+#elif defined(CONFIG_ARMADA_38X)
/* SAR frequency values for Armada 38x */
static const struct sar_freq_modes sar_freq_tab[] = {
{ 0x0, 0x0, 666, 333, 333 },
u32 freq;
int i;
+#if defined(CONFIG_ARMADA_375)
+ val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
+#else
val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
+#endif
freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
-#if !defined(CONFIG_ARMADA_38X)
+#if defined(SAR2_CPU_FREQ_MASK)
/*
* Shift CPU0 clock frequency select bit from SAR2 register
* into correct position
#endif
for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
if (sar_freq_tab[i].val == freq) {
-#if defined(CONFIG_ARMADA_38X)
+#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X)
*sar_freq = sar_freq_tab[i];
return;
#else
case SOC_MV78460_ID:
puts("MV78460-");
break;
+ case SOC_88F6720_ID:
+ puts("MV88F6720-");
+ break;
case SOC_88F6810_ID:
puts("MV88F6810-");
break;
}
}
+ if (mvebu_soc_family() == MVEBU_SOC_A375) {
+ switch (revid) {
+ case MV_88F67XX_A0_ID:
+ puts("A0");
+ break;
+ default:
+ printf("?? (%x)", revid);
+ break;
+ }
+ }
+
if (mvebu_soc_family() == MVEBU_SOC_A38X) {
switch (revid) {
case MV_88F68XX_Z1_ID:
/* Avoid problem with e.g. neta ethernet driver */
invalidate_dcache_all();
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
+ /*
+ * Armada 375 still has some problems with d-cache enabled in the
+ * ethernet driver (mvpp2). So lets keep the d-cache disabled
+ * until this is solved.
+ */
+ if (mvebu_soc_family() != MVEBU_SOC_A375) {
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+ }
}
void v7_outer_cache_enable(void)
#include <asm/arch/soc.h>
-#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_38X)
+#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_375) \
+ || defined(CONFIG_ARMADA_38X)
/*
* Set this for the common xor register definitions needed in dram.c
* for A38x as well here.
#ifdef CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_MII /* expose smi ove miiphy interface */
+#if !defined(CONFIG_ARMADA_375)
#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */
#define CONFIG_PHYLIB
+#endif
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */
#define CONFIG_ARP_TIMEOUT 200
CPU_ATTR_DRAM_CS3 = 0x07,
CPU_ATTR_NANDFLASH = 0x2f,
CPU_ATTR_SPIFLASH = 0x1e,
+ CPU_ATTR_SPI0_CS0 = 0x1e,
+ CPU_ATTR_SPI0_CS1 = 0x5e,
+ CPU_ATTR_SPI1_CS2 = 0x9a,
CPU_ATTR_BOOTROM = 0x1d,
CPU_ATTR_PCIE_IO = 0xe0,
CPU_ATTR_PCIE_MEM = 0xe8,
enum {
MVEBU_SOC_AXP,
+ MVEBU_SOC_A375,
MVEBU_SOC_A38X,
MVEBU_SOC_UNKNOWN,
};
* Ref: Datasheet sec:A.28
*/
struct mvebu_system_registers {
+#if defined(CONFIG_ARMADA_375)
+ u8 pad1[0x54];
+#else
u8 pad1[0x60];
+#endif
u32 rstoutn_mask; /* 0x60 */
u32 sys_soft_rst; /* 0x64 */
};
#define SOC_MV78230_ID 0x7823
#define SOC_MV78260_ID 0x7826
#define SOC_MV78460_ID 0x7846
+#define SOC_88F6720_ID 0x6720
#define SOC_88F6810_ID 0x6810
#define SOC_88F6820_ID 0x6820
#define SOC_88F6828_ID 0x6828
+/* A375 revisions */
+#define MV_88F67XX_A0_ID 0x3
+
/* A38x revisions */
#define MV_88F68XX_Z1_ID 0x0
#define MV_88F68XX_A0_ID 0x4
#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
+#define MVEBU_TWSI1_BASE (MVEBU_REGISTER(0x11100))
#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100))
#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
#define BOOTROM_ERR_MODE_UART 0x6
-#if defined(CONFIG_ARMADA_38X)
+#if defined(CONFIG_ARMADA_375)
+/* SAR values for Armada 375 */
+#define CONFIG_SAR_REG (MVEBU_REGISTER(0xe8200))
+#define CONFIG_SAR2_REG (MVEBU_REGISTER(0xe8204))
+
+#define SAR_CPU_FREQ_OFFS 17
+#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
+
+#define BOOT_DEV_SEL_OFFS 3
+#define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS)
+
+#define BOOT_FROM_UART 0x30
+#define BOOT_FROM_SPI 0x38
+#elif defined(CONFIG_ARMADA_38X)
/* SAR values for Armada 38x */
#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600))
timer_init();
+ /* Armada 375 does not support SerDes and DDR3 init yet */
+#if !defined(CONFIG_ARMADA_375)
/* First init the serdes PHY's */
serdes_phy_config();
/* Setup DDR */
ddr3_init();
+#endif
/*
* Return to the BootROM to continue the Marvell xmodem
--- /dev/null
+if ARCH_SNAPDRAGON
+
+config SYS_SOC
+ default "snapdragon"
+
+choice
+ prompt "Snapdragon board select"
+
+config TARGET_DRAGONBOARD410C
+ bool "96Boards Dragonboard 410C"
+ help
+ Support for 96Boards Dragonboard 410C. This board complies with
+ 96Board Open Platform Specifications. Features:
+ - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
+ - 1GiB RAM
+ - 8GiB eMMC, uSD slot
+ - WiFi, Bluetooth and GPS module
+ - 2x Host, 1x Device USB port
+ - HDMI
+ - 20-pin low speed and 40-pin high speed expanders, 4 LED, 3 buttons
+
+endchoice
+
+source "board/qualcomm/dragonboard410c/Kconfig"
+
+endif
--- /dev/null
+#
+# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += clock-apq8016.o
+obj-y += sysmap-apq8016.o
+obj-y += reset.o
--- /dev/null
+/*
+ * Clock drivers for Qualcomm APQ8016
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * Based on Little Kernel driver, simplified
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+
+/* GPLL0 clock control registers */
+#define GPLL0_STATUS 0x2101C
+#define GPLL0_STATUS_ACTIVE BIT(17)
+
+#define APCS_GPLL_ENA_VOTE 0x45000
+#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
+
+/* vote reg for blsp1 clock */
+#define APCS_CLOCK_BRANCH_ENA_VOTE 0x45004
+#define APCS_CLOCK_BRANCH_ENA_VOTE_BLSP1 BIT(10)
+
+/* SDC(n) clock control registers; n=1,2 */
+
+/* block control register */
+#define SDCC_BCR(n) ((n * 0x1000) + 0x41000)
+/* cmd */
+#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004)
+/* cfg */
+#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008)
+/* m */
+#define SDCC_M(n) ((n * 0x1000) + 0x4100C)
+/* n */
+#define SDCC_N(n) ((n * 0x1000) + 0x41010)
+/* d */
+#define SDCC_D(n) ((n * 0x1000) + 0x41014)
+/* branch control */
+#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018)
+#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C)
+
+/* BLSP1 AHB clock (root clock for BLSP) */
+#define BLSP1_AHB_CBCR 0x1008
+
+/* Uart clock control registers */
+#define BLSP1_UART2_BCR 0x3028
+#define BLSP1_UART2_APPS_CBCR 0x302C
+#define BLSP1_UART2_APPS_CMD_RCGR 0x3034
+#define BLSP1_UART2_APPS_CFG_RCGR 0x3038
+#define BLSP1_UART2_APPS_M 0x303C
+#define BLSP1_UART2_APPS_N 0x3040
+#define BLSP1_UART2_APPS_D 0x3044
+
+/* CBCR register fields */
+#define CBCR_BRANCH_ENABLE_BIT BIT(0)
+#define CBCR_BRANCH_OFF_BIT BIT(31)
+
+struct msm_clk_priv {
+ phys_addr_t base;
+};
+
+/* Enable clock controlled by CBC soft macro */
+static void clk_enable_cbc(phys_addr_t cbcr)
+{
+ setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT);
+
+ while (readl(cbcr) & CBCR_BRANCH_OFF_BIT)
+ ;
+}
+
+/* clock has 800MHz */
+static void clk_enable_gpll0(phys_addr_t base)
+{
+ if (readl(base + GPLL0_STATUS) & GPLL0_STATUS_ACTIVE)
+ return; /* clock already enabled */
+
+ setbits_le32(base + APCS_GPLL_ENA_VOTE, APCS_GPLL_ENA_VOTE_GPLL0);
+
+ while ((readl(base + GPLL0_STATUS) & GPLL0_STATUS_ACTIVE) == 0)
+ ;
+}
+
+#define APPS_CMD_RGCR_UPDATE BIT(0)
+
+/* Update clock command via CMD_RGCR */
+static void clk_bcr_update(phys_addr_t apps_cmd_rgcr)
+{
+ setbits_le32(apps_cmd_rgcr, APPS_CMD_RGCR_UPDATE);
+
+ /* Wait for frequency to be updated. */
+ while (readl(apps_cmd_rgcr) & APPS_CMD_RGCR_UPDATE)
+ ;
+}
+
+struct bcr_regs {
+ uintptr_t cfg_rcgr;
+ uintptr_t cmd_rcgr;
+ uintptr_t M;
+ uintptr_t N;
+ uintptr_t D;
+};
+
+/* RCGR_CFG register fields */
+#define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */
+
+/* sources */
+#define CFG_CLK_SRC_CXO (0 << 8)
+#define CFG_CLK_SRC_GPLL0 (1 << 8)
+#define CFG_CLK_SRC_MASK (7 << 8)
+
+/* Mask for supported fields */
+#define CFG_MASK 0x3FFF
+
+#define CFG_DIVIDER_MASK 0x1F
+
+/* root set rate for clocks with half integer and MND divider */
+static void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
+ int div, int m, int n, int source)
+{
+ uint32_t cfg;
+ /* M value for MND divider. */
+ uint32_t m_val = m;
+ /* NOT(N-M) value for MND divider. */
+ uint32_t n_val = ~((n)-(m)) * !!(n);
+ /* NOT 2D value for MND divider. */
+ uint32_t d_val = ~(n);
+
+ /* Program MND values */
+ writel(m_val, base + regs->M);
+ writel(n_val, base + regs->N);
+ writel(d_val, base + regs->D);
+
+ /* setup src select and divider */
+ cfg = readl(base + regs->cfg_rcgr);
+ cfg &= ~CFG_MASK;
+ cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
+
+ /* Set the divider; HW permits fraction dividers (+0.5), but
+ for simplicity, we will support integers only */
+ if (div)
+ cfg |= (2 * div - 1) & CFG_DIVIDER_MASK;
+
+ if (n_val)
+ cfg |= CFG_MODE_DUAL_EDGE;
+
+ writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
+
+ /* Inform h/w to start using the new config. */
+ clk_bcr_update(base + regs->cmd_rcgr);
+}
+
+static const struct bcr_regs sdc_regs[] = {
+ {
+ .cfg_rcgr = SDCC_CFG_RCGR(1),
+ .cmd_rcgr = SDCC_CMD_RCGR(1),
+ .M = SDCC_M(1),
+ .N = SDCC_N(1),
+ .D = SDCC_D(1),
+ },
+ {
+ .cfg_rcgr = SDCC_CFG_RCGR(2),
+ .cmd_rcgr = SDCC_CMD_RCGR(2),
+ .M = SDCC_M(2),
+ .N = SDCC_N(2),
+ .D = SDCC_D(2),
+ }
+};
+
+/* Init clock for SDHCI controller */
+static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
+{
+ int div = 8; /* 100MHz default */
+
+ if (rate == 200000000)
+ div = 4;
+
+ clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot));
+ /* 800Mhz/div, gpll0 */
+ clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
+ CFG_CLK_SRC_GPLL0);
+ clk_enable_gpll0(priv->base);
+ clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
+
+ return rate;
+}
+
+static const struct bcr_regs uart2_regs = {
+ .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
+ .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
+ .M = BLSP1_UART2_APPS_M,
+ .N = BLSP1_UART2_APPS_N,
+ .D = BLSP1_UART2_APPS_D,
+};
+
+/* Init UART clock, 115200 */
+static int clk_init_uart(struct msm_clk_priv *priv)
+{
+ /* Enable iface clk */
+ clk_enable_cbc(priv->base + BLSP1_AHB_CBCR);
+ /* 7372800 uart block clock @ GPLL0 */
+ clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
+ CFG_CLK_SRC_GPLL0);
+ clk_enable_gpll0(priv->base);
+ /* Enable core clk */
+ clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
+
+ return 0;
+}
+
+ulong msm_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+{
+ struct msm_clk_priv *priv = dev_get_priv(dev);
+
+ switch (periph) {
+ case 0: /* SDC1 */
+ return clk_init_sdc(priv, 0, rate);
+ break;
+ case 1: /* SDC2 */
+ return clk_init_sdc(priv, 1, rate);
+ break;
+ case 4: /* UART2 */
+ return clk_init_uart(priv);
+ break;
+ default:
+ return 0;
+ }
+}
+
+static int msm_clk_probe(struct udevice *dev)
+{
+ struct msm_clk_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_get_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return 0;
+}
+
+static struct clk_ops msm_clk_ops = {
+ .set_periph_rate = msm_set_periph_rate,
+};
+
+static const struct udevice_id msm_clk_ids[] = {
+ { .compatible = "qcom,gcc-msm8916" },
+ { .compatible = "qcom,gcc-apq8016" },
+ { }
+};
+
+U_BOOT_DRIVER(clk_msm) = {
+ .name = "clk_msm",
+ .id = UCLASS_CLK,
+ .of_match = msm_clk_ids,
+ .ops = &msm_clk_ops,
+ .priv_auto_alloc_size = sizeof(struct msm_clk_priv),
+ .probe = msm_clk_probe,
+};
--- /dev/null
+/*
+ * Empty gpio.h
+ *
+ * This file must stay as arch/arm/include/asm/gpio.h requires it.
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
--- /dev/null
+/*
+ * Qualcomm APQ8916 sysmap
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _MACH_SYSMAP_APQ8016_H
+#define _MACH_SYSMAP_APQ8016_H
+
+#define GICD_BASE 0x0b000000
+#define GICC_BASE 0x0a20c000
+
+#endif
--- /dev/null
+/*
+ * Qualcomm APQ8016 reset controller driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <reset.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int msm_reset_request(struct udevice *dev, enum reset_t type)
+{
+ phys_addr_t addr = dev_get_addr(dev);
+ if (!addr)
+ return -EINVAL;
+ writel(0, addr);
+ return -EINPROGRESS;
+}
+
+static struct reset_ops msm_reset_ops = {
+ .request = msm_reset_request,
+};
+
+static const struct udevice_id msm_reset_ids[] = {
+ { .compatible = "qcom,pshold" },
+ { }
+};
+
+U_BOOT_DRIVER(msm_reset) = {
+ .name = "msm_reset",
+ .id = UCLASS_RESET,
+ .of_match = msm_reset_ids,
+ .ops = &msm_reset_ops,
+};
--- /dev/null
+/*
+ * Qualcomm APQ8016 memory map
+ *
+ * (C) Copyright 2016 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region apq8016_mem_map[] = {
+ {
+ .base = 0x0UL, /* Peripheral block */
+ .size = 0x8000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .base = 0x80000000UL, /* DDR */
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = apq8016_mem_map;
+++ /dev/null
-/*
- * (C) Copyright 2013 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SOCFPGA_DWMMC_H_
-#define _SOCFPGA_DWMMC_H_
-
-int socfpga_dwmmc_init(const void *blob);
-
-#endif /* _SOCFPGA_SDMMC_H_ */
#include <asm/arch/reset_manager.h>
#include <asm/arch/scan_manager.h>
#include <asm/arch/system_manager.h>
-#include <asm/arch/dwmmc.h>
#include <asm/arch/nic301.h>
#include <asm/arch/scu.h>
#include <asm/pl310.h>
* DesignWare Ethernet initialization
*/
#ifdef CONFIG_ETH_DESIGNWARE
-static void dwmac_deassert_reset(const unsigned int of_reset_id)
+static void dwmac_deassert_reset(const unsigned int of_reset_id,
+ const u32 phymode)
{
u32 physhift, reset;
/* configure to PHY interface select choosed */
setbits_le32(&sysmgr_regs->emacgrp_ctrl,
- SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
+ phymode << physhift);
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
}
+static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
+{
+ if (!phymode)
+ return -EINVAL;
+
+ if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
+ *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+ return 0;
+ }
+
+ if (!strcmp(phymode, "rgmii")) {
+ *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+ return 0;
+ }
+
+ if (!strcmp(phymode, "rmii")) {
+ *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
static int socfpga_eth_reset(void)
{
const void *fdt = gd->fdt_blob;
struct fdtdec_phandle_args args;
+ const char *phy_mode;
+ u32 phy_modereg;
int nodes[2]; /* Max. two GMACs */
int ret, count;
int i, node;
continue;
}
- dwmac_deassert_reset(args.args[0]);
+ phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
+ ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
+ if (ret) {
+ debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
+ continue;
+ }
+
+ dwmac_deassert_reset(args.args[0], phy_modereg);
}
return 0;
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += soc.o clock.o timer.o flash.o
+obj-y += soc.o clock.o timer.o
#define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1)
#define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0)
-#define FLASH_ACR_WS(n) n
-#define FLASH_ACR_PRFTEN (1 << 8)
-#define FLASH_ACR_ICEN (1 << 9)
-#define FLASH_ACR_DCEN (1 << 10)
-
/*
* RCC GPIO specific definitions
*/
while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
;
- /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
- writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
- | FLASH_ACR_DCEN, &STM32_FLASH->acr);
-
+ stm32_flash_latency_cfg(5);
clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
+++ /dev/null
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/stm32.h>
-
-#define STM32_FLASH_KEY1 0x45670123
-#define STM32_FLASH_KEY2 0xCDEF89AB
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
- [0 ... 3] = 16 * 1024,
- [4] = 64 * 1024,
- [5 ... 11] = 128 * 1024
-};
-
-static void stm32f4_flash_lock(u8 lock)
-{
- if (lock) {
- setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_LOCK);
- } else {
- writel(STM32_FLASH_KEY1, &STM32_FLASH->key);
- writel(STM32_FLASH_KEY2, &STM32_FLASH->key);
- }
-}
-
-unsigned long flash_init(void)
-{
- unsigned long total_size = 0;
- u8 i, j;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- flash_info[i].flash_id = FLASH_STM32F4;
- flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 20);
- flash_info[i].size = sect_sz_kb[0];
- for (j = 1; j < CONFIG_SYS_MAX_FLASH_SECT; j++) {
- flash_info[i].start[j] = flash_info[i].start[j - 1]
- + (sect_sz_kb[j - 1]);
- flash_info[i].size += sect_sz_kb[j];
- }
- total_size += flash_info[i].size;
- }
-
- return total_size;
-}
-
-void flash_print_info(flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("missing or unknown FLASH type\n");
- return;
- } else if (info->flash_id == FLASH_STM32F4) {
- printf("STM32F4 Embedded Flash\n");
- }
-
- printf(" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf("\n ");
- printf(" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf("\n");
- return;
-}
-
-int flash_erase(flash_info_t *info, int first, int last)
-{
- u8 bank = 0xFF;
- int i;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- if (info == &flash_info[i]) {
- bank = i;
- break;
- }
- }
- if (bank == 0xFF)
- return -1;
-
- stm32f4_flash_lock(0);
-
- for (i = first; i <= last; i++) {
- while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
- ;
-
- /* clear old sector number before writing a new one */
- clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SNB_MASK);
-
- if (bank == 0) {
- setbits_le32(&STM32_FLASH->cr,
- (i << STM32_FLASH_CR_SNB_OFFSET));
- } else if (bank == 1) {
- setbits_le32(&STM32_FLASH->cr,
- ((0x10 | i) << STM32_FLASH_CR_SNB_OFFSET));
- } else {
- stm32f4_flash_lock(1);
- return -1;
- }
- setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
- setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_STRT);
-
- while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
- ;
-
- clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
- }
-
- stm32f4_flash_lock(1);
- return 0;
-}
-
-int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong i;
-
- while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
- ;
-
- stm32f4_flash_lock(0);
-
- setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG);
- /* To make things simple use byte writes only */
- for (i = 0; i < cnt; i++) {
- *(uchar *)(addr + i) = src[i];
- while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
- ;
- }
- clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG);
- stm32f4_flash_lock(1);
-
- return 0;
-}
--- /dev/null
+#
+# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+#
+# Based on some other Makefile
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += board.o
+obj-y += clock.o
+obj-y += cpu_info.o
+obj-y += dram_helpers.o
+obj-y += pinmux.o
+ifndef CONFIG_MACH_SUN9I
+obj-y += usb_phy.o
+endif
+obj-$(CONFIG_MACH_SUN6I) += prcm.o
+obj-$(CONFIG_MACH_SUN8I) += prcm.o
+obj-$(CONFIG_MACH_SUN9I) += prcm.o
+obj-$(CONFIG_MACH_SUN6I) += p2wi.o
+obj-$(CONFIG_MACH_SUN8I) += rsb.o
+obj-$(CONFIG_MACH_SUN9I) += rsb.o
+obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
+obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
+obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
+obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o
+obj-$(CONFIG_MACH_SUN50I) += clock_sun6i.o
+ifdef CONFIG_MACH_SUN8I_A83T
+obj-y += clock_sun8i_a83t.o
+else
+obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
+endif
+obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o
+
+obj-$(CONFIG_AXP152_POWER) += pmic_bus.o
+obj-$(CONFIG_AXP209_POWER) += pmic_bus.o
+obj-$(CONFIG_AXP221_POWER) += pmic_bus.o
+obj-$(CONFIG_AXP818_POWER) += pmic_bus.o
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o
+obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
+obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
+obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
+obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o
+obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o
+obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o
+obj-$(CONFIG_MACH_SUN8I_H3) += dram_sun8i_h3.o
+endif
--- /dev/null
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Some init for sunxi platform.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <i2c.h>
+#include <serial.h>
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#endif
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/tzpc.h>
+#include <asm/arch/mmc.h>
+
+#include <linux/compiler.h>
+
+struct fel_stash {
+ uint32_t sp;
+ uint32_t lr;
+ uint32_t cpsr;
+ uint32_t sctlr;
+ uint32_t vbar;
+ uint32_t cr;
+};
+
+struct fel_stash fel_stash __attribute__((section(".data")));
+
+#ifdef CONFIG_MACH_SUN50I
+#include <asm/armv8/mmu.h>
+
+static struct mm_region sunxi_mem_map[] = {
+ {
+ /* SRAM, MMIO regions */
+ .base = 0x0UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ }, {
+ /* RAM */
+ .base = 0x40000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+struct mm_region *mem_map = sunxi_mem_map;
+#endif
+
+static int gpio_init(void)
+{
+#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+ /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
+#endif
+#if defined(CONFIG_MACH_SUN8I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
+#else
+ sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
+#endif
+ sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
+#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
+ sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
+ sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
+ sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
+#else
+#error Unsupported console port number. Please fix pin mux settings in board.c
+#endif
+
+ return 0;
+}
+
+int spl_board_load_image(void)
+{
+ debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
+ return_to_fel(fel_stash.sp, fel_stash.lr);
+
+ return 0;
+}
+
+void s_init(void)
+{
+ /*
+ * Undocumented magic taken from boot0, without this DRAM
+ * access gets messed up (seems cache related).
+ * The boot0 sources describe this as: "config ema for cache sram"
+ */
+#if defined CONFIG_MACH_SUN6I
+ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+#elif defined CONFIG_MACH_SUN8I
+ __maybe_unused uint version;
+
+ /* Unlock sram version info reg, read it, relock */
+ setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
+ version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
+ clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
+
+ /*
+ * Ideally this would be a switch case, but we do not know exactly
+ * which versions there are and which version needs which settings,
+ * so reproduce the per SoC code from the BSP.
+ */
+#if defined CONFIG_MACH_SUN8I_A23
+ if (version == 0x1650)
+ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+ else /* 0x1661 ? */
+ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
+#elif defined CONFIG_MACH_SUN8I_A33
+ if (version != 0x1667)
+ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
+#endif
+ /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
+ /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
+#endif
+
+#if defined CONFIG_MACH_SUN6I || \
+ defined CONFIG_MACH_SUN7I || \
+ defined CONFIG_MACH_SUN8I
+ /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
+ asm volatile(
+ "mrc p15, 0, r0, c1, c0, 1\n"
+ "orr r0, r0, #1 << 6\n"
+ "mcr p15, 0, r0, c1, c0, 1\n");
+#endif
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
+ /* Enable non-secure access to some peripherals */
+ tzpc_init();
+#endif
+
+ clock_init();
+ timer_init();
+ gpio_init();
+ i2c_init_board();
+ eth_init_board();
+}
+
+#ifdef CONFIG_SPL_BUILD
+DECLARE_GLOBAL_DATA_PTR;
+
+/* The sunxi internal brom will try to loader external bootloader
+ * from mmc0, nand flash, mmc2.
+ */
+u32 spl_boot_device(void)
+{
+ __maybe_unused struct mmc *mmc0, *mmc1;
+ /*
+ * When booting from the SD card or NAND memory, the "eGON.BT0"
+ * signature is expected to be found in memory at the address 0x0004
+ * (see the "mksunxiboot" tool, which generates this header).
+ *
+ * When booting in the FEL mode over USB, this signature is patched in
+ * memory and replaced with something else by the 'fel' tool. This other
+ * signature is selected in such a way, that it can't be present in a
+ * valid bootable SD card image (because the BROM would refuse to
+ * execute the SPL in this case).
+ *
+ * This checks for the signature and if it is not found returns to
+ * the FEL code in the BROM to wait and receive the main u-boot
+ * binary over USB. If it is found, it determines where SPL was
+ * read from.
+ */
+ if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
+ return BOOT_DEVICE_BOARD;
+
+ /* The BROM will try to boot from mmc0 first, so try that first. */
+#ifdef CONFIG_MMC
+ mmc_initialize(gd->bd);
+ mmc0 = find_mmc_device(0);
+ if (sunxi_mmc_has_egon_boot_signature(mmc0))
+ return BOOT_DEVICE_MMC1;
+#endif
+
+ /* Fallback to booting NAND if enabled. */
+ if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT))
+ return BOOT_DEVICE_NAND;
+
+#ifdef CONFIG_MMC
+ if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) {
+ mmc1 = find_mmc_device(1);
+ if (sunxi_mmc_has_egon_boot_signature(mmc1))
+ return BOOT_DEVICE_MMC2;
+ }
+#endif
+
+ panic("Could not determine boot source\n");
+ return -1; /* Never reached */
+}
+
+/* No confirmation data available in SPL yet. Hardcode bootmode */
+u32 spl_boot_mode(void)
+{
+ return MMCSD_MODE_RAW;
+}
+
+void board_init_f(ulong dummy)
+{
+ spl_init();
+ preloader_console_init();
+
+#ifdef CONFIG_SPL_I2C_SUPPORT
+ /* Needed early by sunxi_board_init if PMU is enabled */
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+ sunxi_board_init();
+}
+#endif
+
+void reset_cpu(ulong addr)
+{
+#ifdef CONFIG_SUNXI_GEN_SUN4I
+ static const struct sunxi_wdog *wdog =
+ &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
+
+ /* Set the watchdog for its shortest interval (.5s) and wait */
+ writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
+ writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
+
+ while (1) {
+ /* sun5i sometimes gets stuck without this */
+ writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
+ }
+#endif
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+ static const struct sunxi_wdog *wdog =
+ ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
+
+ /* Set the watchdog for its shortest interval (.5s) and wait */
+ writel(WDT_CFG_RESET, &wdog->cfg);
+ writel(WDT_MODE_EN, &wdog->mode);
+ writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
+ while (1) { }
+#endif
+}
+
+#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+__weak void clock_init_sec(void)
+{
+}
+
+int clock_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+ clock_init_safe();
+#endif
+ clock_init_uart();
+ clock_init_sec();
+
+ return 0;
+}
+
+/* These functions are shared between various SoCs so put them here. */
+#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I
+int clock_twi_onoff(int port, int state)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ if (port == 5) {
+ if (state)
+ prcm_apb0_enable(
+ PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
+ else
+ prcm_apb0_disable(
+ PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
+ return 0;
+ }
+
+ /* set the apb clock gate and reset for twi */
+ if (state) {
+ setbits_le32(&ccm->apb2_gate,
+ CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port));
+ setbits_le32(&ccm->apb2_reset_cfg,
+ 1 << (APB2_RESET_TWI_SHIFT + port));
+ } else {
+ clrbits_le32(&ccm->apb2_reset_cfg,
+ 1 << (APB2_RESET_TWI_SHIFT + port));
+ clrbits_le32(&ccm->apb2_gate,
+ CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port));
+ }
+
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * sun4i, sun5i and sun7i specific clock code
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+
+#ifdef CONFIG_SPL_BUILD
+void clock_init_safe(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* Set safe defaults until PMU is configured */
+ writel(AXI_DIV_1 << AXI_DIV_SHIFT |
+ AHB_DIV_2 << AHB_DIV_SHIFT |
+ APB0_DIV_1 << APB0_DIV_SHIFT |
+ CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_ahb_apb0_cfg);
+ writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
+ sdelay(200);
+ writel(AXI_DIV_1 << AXI_DIV_SHIFT |
+ AHB_DIV_2 << AHB_DIV_SHIFT |
+ APB0_DIV_1 << APB0_DIV_SHIFT |
+ CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_ahb_apb0_cfg);
+#ifdef CONFIG_MACH_SUN7I
+ setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
+#endif
+ writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+#ifdef CONFIG_SUNXI_AHCI
+ setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
+ setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);
+#endif
+}
+#endif
+
+void clock_init_uart(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* uart clock source is apb1 */
+ writel(APB1_CLK_SRC_OSC24M|
+ APB1_CLK_RATE_N_1|
+ APB1_CLK_RATE_M(1),
+ &ccm->apb1_clk_div_cfg);
+
+ /* open the clock for uart */
+ setbits_le32(&ccm->apb1_gate,
+ CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX - 1));
+}
+
+int clock_twi_onoff(int port, int state)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* set the apb clock gate for twi */
+ if (state)
+ setbits_le32(&ccm->apb1_gate,
+ CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
+ else
+ clrbits_le32(&ccm->apb1_gate,
+ CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \
+ 0 << CCM_PLL1_CFG_VCO_RST_SHIFT | \
+ 8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \
+ 0 << CCM_PLL1_CFG_PLL4_EXCH_SHIFT | \
+ 16 << CCM_PLL1_CFG_BIAS_CUR_SHIFT | \
+ (P)<< CCM_PLL1_CFG_DIVP_SHIFT | \
+ 2 << CCM_PLL1_CFG_LCK_TMR_SHIFT | \
+ (N)<< CCM_PLL1_CFG_FACTOR_N_SHIFT | \
+ (K)<< CCM_PLL1_CFG_FACTOR_K_SHIFT | \
+ 0 << CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT | \
+ 0 << CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT | \
+ (M)<< CCM_PLL1_CFG_FACTOR_M_SHIFT)
+
+static struct {
+ u32 pll1_cfg;
+ unsigned int freq;
+} pll1_para[] = {
+ /* This array must be ordered by frequency. */
+ { PLL1_CFG(31, 1, 0, 0), 1488000000},
+ { PLL1_CFG(30, 1, 0, 0), 1440000000},
+ { PLL1_CFG(29, 1, 0, 0), 1392000000},
+ { PLL1_CFG(28, 1, 0, 0), 1344000000},
+ { PLL1_CFG(27, 1, 0, 0), 1296000000},
+ { PLL1_CFG(26, 1, 0, 0), 1248000000},
+ { PLL1_CFG(25, 1, 0, 0), 1200000000},
+ { PLL1_CFG(24, 1, 0, 0), 1152000000},
+ { PLL1_CFG(23, 1, 0, 0), 1104000000},
+ { PLL1_CFG(22, 1, 0, 0), 1056000000},
+ { PLL1_CFG(21, 1, 0, 0), 1008000000},
+ { PLL1_CFG(20, 1, 0, 0), 960000000 },
+ { PLL1_CFG(19, 1, 0, 0), 912000000 },
+ { PLL1_CFG(16, 1, 0, 0), 768000000 },
+ /* Final catchall entry 384MHz*/
+ { PLL1_CFG(16, 0, 0, 0), 0 },
+
+};
+
+void clock_set_pll1(unsigned int hz)
+{
+ int i = 0;
+ int axi, ahb, apb0;
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* Find target frequency */
+ while (pll1_para[i].freq > hz)
+ i++;
+
+ hz = pll1_para[i].freq;
+ if (! hz)
+ hz = 384000000;
+
+ /* Calculate system clock divisors */
+ axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */
+ ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */
+ apb0 = 2; /* Max 150MHz */
+
+ printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0);
+
+ /* Map divisors to register values */
+ axi = axi - 1;
+ if (ahb > 4)
+ ahb = 3;
+ else if (ahb > 2)
+ ahb = 2;
+ else if (ahb > 1)
+ ahb = 1;
+ else
+ ahb = 0;
+
+ apb0 = apb0 - 1;
+
+ /* Switch to 24MHz clock while changing PLL1 */
+ writel(AXI_DIV_1 << AXI_DIV_SHIFT |
+ AHB_DIV_2 << AHB_DIV_SHIFT |
+ APB0_DIV_1 << APB0_DIV_SHIFT |
+ CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_ahb_apb0_cfg);
+ sdelay(20);
+
+ /* Configure sys clock divisors */
+ writel(axi << AXI_DIV_SHIFT |
+ ahb << AHB_DIV_SHIFT |
+ apb0 << APB0_DIV_SHIFT |
+ CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_ahb_apb0_cfg);
+
+ /* Configure PLL1 at the desired frequency */
+ writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg);
+ sdelay(200);
+
+ /* Switch CPU to PLL1 */
+ writel(axi << AXI_DIV_SHIFT |
+ ahb << AHB_DIV_SHIFT |
+ apb0 << APB0_DIV_SHIFT |
+ CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_ahb_apb0_cfg);
+ sdelay(20);
+}
+#endif
+
+void clock_set_pll3(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ if (clk == 0) {
+ clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
+ return;
+ }
+
+ /* PLL3 rate = 3000000 * m */
+ writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
+ CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg);
+}
+
+unsigned int clock_get_pll3(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ uint32_t rval = readl(&ccm->pll3_cfg);
+ int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT);
+ return 3000000 * m;
+}
+
+unsigned int clock_get_pll5p(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ uint32_t rval = readl(&ccm->pll5_cfg);
+ int n = ((rval & CCM_PLL5_CTRL_N_MASK) >> CCM_PLL5_CTRL_N_SHIFT);
+ int k = ((rval & CCM_PLL5_CTRL_K_MASK) >> CCM_PLL5_CTRL_K_SHIFT) + 1;
+ int p = ((rval & CCM_PLL5_CTRL_P_MASK) >> CCM_PLL5_CTRL_P_SHIFT);
+ return (24000000 * n * k) >> p;
+}
+
+unsigned int clock_get_pll6(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ uint32_t rval = readl(&ccm->pll6_cfg);
+ int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
+ int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
+ return 24000000 * n * k / 2;
+}
+
+void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
+{
+ int pll = clock_get_pll5p();
+ int div = 1;
+
+ while ((pll / div) > hz)
+ div++;
+
+ writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_RST | CCM_DE_CTRL_PLL5P |
+ CCM_DE_CTRL_M(div), clk_cfg);
+}
--- /dev/null
+/*
+ * sun6i specific clock code
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+#ifdef CONFIG_SPL_BUILD
+void clock_init_safe(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_prcm_reg * const prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+ /* Set PLL ldo voltage without this PLL6 does not work properly */
+ clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
+ PRCM_PLL_CTRL_LDO_KEY);
+ clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
+ PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
+ PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
+ clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
+
+ clock_set_pll1(408000000);
+
+ writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+ while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
+ ;
+
+ writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
+
+ writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
+ writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
+}
+#endif
+
+void clock_init_sec(void)
+{
+#ifdef CONFIG_MACH_SUN8I_H3
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ setbits_le32(&ccm->ccu_sec_switch,
+ CCM_SEC_SWITCH_MBUS_NONSEC |
+ CCM_SEC_SWITCH_BUS_NONSEC |
+ CCM_SEC_SWITCH_PLL_NONSEC);
+#endif
+}
+
+void clock_init_uart(void)
+{
+#if CONFIG_CONS_INDEX < 5
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* uart clock source is apb2 */
+ writel(APB2_CLK_SRC_OSC24M|
+ APB2_CLK_RATE_N_1|
+ APB2_CLK_RATE_M(1),
+ &ccm->apb2_div);
+
+ /* open the clock for uart */
+ setbits_le32(&ccm->apb2_gate,
+ CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
+ CONFIG_CONS_INDEX - 1));
+
+ /* deassert uart reset */
+ setbits_le32(&ccm->apb2_reset_cfg,
+ 1 << (APB2_RESET_UART_SHIFT +
+ CONFIG_CONS_INDEX - 1));
+#else
+ /* enable R_PIO and R_UART clocks, and de-assert resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
+#endif
+}
+
+#ifdef CONFIG_SPL_BUILD
+void clock_set_pll1(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ const int p = 0;
+ int k = 1;
+ int m = 1;
+
+ if (clk > 1152000000) {
+ k = 2;
+ } else if (clk > 768000000) {
+ k = 3;
+ m = 2;
+ }
+
+ /* Switch to 24MHz clock while changing PLL1 */
+ writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+ ATB_DIV_2 << ATB_DIV_SHIFT |
+ CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_axi_cfg);
+
+ /*
+ * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
+ * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
+ */
+ writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
+ CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
+ CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
+ sdelay(200);
+
+ /* Switch CPU to PLL1 */
+ writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+ ATB_DIV_2 << ATB_DIV_SHIFT |
+ CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_axi_cfg);
+}
+#endif
+
+void clock_set_pll3(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
+
+ if (clk == 0) {
+ clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
+ return;
+ }
+
+ /* PLL3 rate = 24000000 * n / m */
+ writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
+ CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
+ &ccm->pll3_cfg);
+}
+
+void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ const int max_n = 32;
+ int k = 1, m = 2;
+
+ if (sigma_delta_enable)
+ writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
+
+ /* PLL5 rate = 24000000 * n * k / m */
+ if (clk > 24000000 * k * max_n / m) {
+ m = 1;
+ if (clk > 24000000 * k * max_n / m)
+ k = 2;
+ }
+ writel(CCM_PLL5_CTRL_EN |
+ (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
+ CCM_PLL5_CTRL_UPD |
+ CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
+ CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
+
+ udelay(5500);
+}
+
+#ifdef CONFIG_MACH_SUN6I
+void clock_set_mipi_pll(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ unsigned int k, m, n, value, diff;
+ unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
+ unsigned int src = clock_get_pll3();
+
+ /* All calculations are in KHz to avoid overflows */
+ clk /= 1000;
+ src /= 1000;
+
+ /* Pick the closest lower clock */
+ for (k = 1; k <= 4; k++) {
+ for (m = 1; m <= 16; m++) {
+ for (n = 1; n <= 16; n++) {
+ value = src * n * k / m;
+ if (value > clk)
+ continue;
+
+ diff = clk - value;
+ if (diff < best_diff) {
+ best_diff = diff;
+ best_k = k;
+ best_m = m;
+ best_n = n;
+ }
+ if (diff == 0)
+ goto done;
+ }
+ }
+ }
+
+done:
+ writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN |
+ CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) |
+ CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
+}
+#endif
+
+#ifdef CONFIG_MACH_SUN8I_A33
+void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ if (sigma_delta_enable)
+ writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg);
+
+ writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
+ (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
+ CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
+
+ while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
+ ;
+}
+#endif
+
+unsigned int clock_get_pll3(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ uint32_t rval = readl(&ccm->pll3_cfg);
+ int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
+ int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;
+
+ /* Multiply by 1000 after dividing by m to avoid integer overflows */
+ return (24000 * n / m) * 1000;
+}
+
+unsigned int clock_get_pll6(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ uint32_t rval = readl(&ccm->pll6_cfg);
+ int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
+ int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
+ return 24000000 * n * k / 2;
+}
+
+unsigned int clock_get_mipi_pll(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ uint32_t rval = readl(&ccm->mipi_pll_cfg);
+ unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
+ unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
+ unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
+ unsigned int src = clock_get_pll3();
+
+ /* Multiply by 1000 after dividing by m to avoid integer overflows */
+ return ((src / 1000) * n * k / m) * 1000;
+}
+
+void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
+{
+ int pll = clock_get_pll6() * 2;
+ int div = 1;
+
+ while ((pll / div) > hz)
+ div++;
+
+ writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
+ clk_cfg);
+}
--- /dev/null
+/*
+ * A83 specific clock code
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+#ifdef CONFIG_SPL_BUILD
+void clock_init_safe(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ clock_set_pll1(408000000);
+ /* enable pll_hsic, default is 480M */
+ writel(PLL8_CFG_DEFAULT, &ccm->pll8_cfg);
+ writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg);
+ while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {}
+
+ /* switch to default 24MHz before changing to hsic */
+ writel(0x0, &ccm->cci400_cfg);
+ sdelay(50);
+ writel(CCM_CCI400_CLK_SEL_HSIC, &ccm->cci400_cfg);
+ sdelay(100);
+
+ /* switch before changing pll6 */
+ clrsetbits_le32(&ccm->ahb1_apb1_div, AHB1_CLK_SRC_MASK,
+ AHB1_CLK_SRC_OSC24M);
+ writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+ while (!(readl(&ccm->pll_stable_status) & (1 << 6))) {}
+
+ writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
+ writel(CCM_MBUS_RESET_RESET, &ccm->mbus_reset);
+ writel(MBUS_CLK_DEFAULT, &ccm->mbus_clk_cfg);
+
+ /* timestamp */
+ writel(1, 0x01720000);
+}
+#endif
+
+void clock_init_uart(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* uart clock source is apb2 */
+ writel(APB2_CLK_SRC_OSC24M|
+ APB2_CLK_RATE_N_1|
+ APB2_CLK_RATE_M(1),
+ &ccm->apb2_div);
+
+ /* open the clock for uart */
+ setbits_le32(&ccm->apb2_gate,
+ CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
+ CONFIG_CONS_INDEX - 1));
+
+ /* deassert uart reset */
+ setbits_le32(&ccm->apb2_reset_cfg,
+ 1 << (APB2_RESET_UART_SHIFT +
+ CONFIG_CONS_INDEX - 1));
+}
+
+#ifdef CONFIG_SPL_BUILD
+void clock_set_pll1(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ const int p = 0;
+
+ /* Switch to 24MHz clock while changing PLL1 */
+ writel(AXI_DIV_2 << AXI0_DIV_SHIFT |
+ AXI_DIV_2 << AXI1_DIV_SHIFT |
+ CPU_CLK_SRC_OSC24M << C0_CPUX_CLK_SRC_SHIFT |
+ CPU_CLK_SRC_OSC24M << C1_CPUX_CLK_SRC_SHIFT,
+ &ccm->cpu_axi_cfg);
+
+ /* clk = 24*n/p, p is ignored if clock is >288MHz */
+ writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 |
+ CCM_PLL1_CTRL_N(clk / 24000000),
+ &ccm->pll1_c0_cfg);
+ while (!(readl(&ccm->pll_stable_status) & 0x01)) {}
+
+ writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 |
+ CCM_PLL1_CTRL_N(clk / (24000000)),
+ &ccm->pll1_c1_cfg);
+ while (!(readl(&ccm->pll_stable_status) & 0x02)) {}
+
+ /* Switch CPU to PLL1 */
+ writel(AXI_DIV_2 << AXI0_DIV_SHIFT |
+ AXI_DIV_2 << AXI1_DIV_SHIFT |
+ CPU_CLK_SRC_PLL1 << C0_CPUX_CLK_SRC_SHIFT |
+ CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT,
+ &ccm->cpu_axi_cfg);
+}
+#endif
+
+void clock_set_pll5(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ unsigned int div1 = 0, div2 = 0;
+
+ /* A83T PLL5 DDR rate = 24000000 * (n+1)/(div1+1)/(div2+1) */
+ writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
+ CCM_PLL5_CTRL_N(clk / (24000000)) |
+ div2 << CCM_PLL5_DIV2_SHIFT |
+ div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg);
+
+ udelay(5500);
+}
+
+
+unsigned int clock_get_pll6(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ uint32_t rval = readl(&ccm->pll6_cfg);
+ int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
+ int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
+ CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
+ int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
+ CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
+ return 24000000 * n / div1 / div2;
+}
--- /dev/null
+/*
+ * sun9i specific clock code
+ *
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+void clock_init_uart(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* open the clock for uart */
+ setbits_le32(&ccm->apb1_gate,
+ CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT +
+ CONFIG_CONS_INDEX - 1));
+ /* deassert uart reset */
+ setbits_le32(&ccm->apb1_reset_cfg,
+ 1 << (APB1_RESET_UART_SHIFT +
+ CONFIG_CONS_INDEX - 1));
+
+ /* Dup with clock_init_safe(), drop once sun9i SPL support lands */
+ writel(PLL4_CFG_DEFAULT, &ccm->pll4_periph0_cfg);
+}
+
+int clock_twi_onoff(int port, int state)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ if (port > 4)
+ return -1;
+
+ /* set the apb reset and clock gate for twi */
+ if (state) {
+ setbits_le32(&ccm->apb1_gate,
+ CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
+ setbits_le32(&ccm->apb1_reset_cfg,
+ 1 << (APB1_RESET_TWI_SHIFT + port));
+ } else {
+ clrbits_le32(&ccm->apb1_reset_cfg,
+ 1 << (APB1_RESET_TWI_SHIFT + port));
+ clrbits_le32(&ccm->apb1_gate,
+ CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
+ }
+
+ return 0;
+}
+
+unsigned int clock_get_pll4_periph0(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ uint32_t rval = readl(&ccm->pll4_periph0_cfg);
+ int n = ((rval & CCM_PLL4_CTRL_N_MASK) >> CCM_PLL4_CTRL_N_SHIFT);
+ int p = ((rval & CCM_PLL4_CTRL_P_MASK) >> CCM_PLL4_CTRL_P_SHIFT);
+ int m = ((rval & CCM_PLL4_CTRL_M_MASK) >> CCM_PLL4_CTRL_M_SHIFT) + 1;
+ const int k = 1;
+
+ return ((24000000 * n * k) >> p) / m;
+}
--- /dev/null
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <axp_pmic.h>
+#include <errno.h>
+
+#ifdef CONFIG_MACH_SUN6I
+int sunxi_get_ss_bonding_id(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ static int bonding_id = -1;
+
+ if (bonding_id != -1)
+ return bonding_id;
+
+ /* Enable Security System */
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS);
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS);
+
+ bonding_id = readl(SUNXI_SS_BASE);
+ bonding_id = (bonding_id >> 16) & 0x7;
+
+ /* Disable Security System again */
+ clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS);
+ clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS);
+
+ return bonding_id;
+}
+#endif
+
+#ifdef CONFIG_MACH_SUN8I
+uint sunxi_get_sram_id(void)
+{
+ uint id;
+
+ /* Unlock sram info reg, read it, relock */
+ setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
+ id = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
+ clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
+
+ return id;
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+#ifdef CONFIG_MACH_SUN4I
+ puts("CPU: Allwinner A10 (SUN4I)\n");
+#elif defined CONFIG_MACH_SUN5I
+ u32 val = readl(SUNXI_SID_BASE + 0x08);
+ switch ((val >> 12) & 0xf) {
+ case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break;
+ case 3: puts("CPU: Allwinner A13 (SUN5I)\n"); break;
+ case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break;
+ default: puts("CPU: Allwinner A1X (SUN5I)\n");
+ }
+#elif defined CONFIG_MACH_SUN6I
+ switch (sunxi_get_ss_bonding_id()) {
+ case SUNXI_SS_BOND_ID_A31:
+ puts("CPU: Allwinner A31 (SUN6I)\n");
+ break;
+ case SUNXI_SS_BOND_ID_A31S:
+ puts("CPU: Allwinner A31s (SUN6I)\n");
+ break;
+ default:
+ printf("CPU: Allwinner A31? (SUN6I, id: %d)\n",
+ sunxi_get_ss_bonding_id());
+ }
+#elif defined CONFIG_MACH_SUN7I
+ puts("CPU: Allwinner A20 (SUN7I)\n");
+#elif defined CONFIG_MACH_SUN8I_A23
+ printf("CPU: Allwinner A23 (SUN8I %04x)\n", sunxi_get_sram_id());
+#elif defined CONFIG_MACH_SUN8I_A33
+ printf("CPU: Allwinner A33 (SUN8I %04x)\n", sunxi_get_sram_id());
+#elif defined CONFIG_MACH_SUN8I_A83T
+ printf("CPU: Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id());
+#elif defined CONFIG_MACH_SUN8I_H3
+ printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
+#elif defined CONFIG_MACH_SUN9I
+ puts("CPU: Allwinner A80 (SUN9I)\n");
+#elif defined CONFIG_MACH_SUN50I
+ puts("CPU: Allwinner A64 (SUN50I)\n");
+#else
+#warning Please update cpu_info.c with correct CPU information
+ puts("CPU: SUNXI Family\n");
+#endif
+ return 0;
+}
+#endif
+
+int sunxi_get_sid(unsigned int *sid)
+{
+#ifdef CONFIG_AXP221_POWER
+ return axp_get_sid(sid);
+#elif defined SUNXI_SID_BASE
+ int i;
+
+ for (i = 0; i< 4; i++)
+ sid[i] = readl((ulong)SUNXI_SID_BASE + 4 * i);
+
+ return 0;
+#else
+ return -ENODEV;
+#endif
+}
--- /dev/null
+/*
+ * DRAM init helper functions
+ *
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/dram.h>
+
+/*
+ * Wait up to 1s for value to be set in given part of reg.
+ */
+void mctl_await_completion(u32 *reg, u32 mask, u32 val)
+{
+ unsigned long tmo = timer_get_us() + 1000000;
+
+ while ((readl(reg) & mask) != val) {
+ if (timer_get_us() > tmo)
+ panic("Timeout initialising DRAM\n");
+ }
+}
+
+/*
+ * Test if memory at offset offset matches memory at begin of DRAM
+ */
+bool mctl_mem_matches(u32 offset)
+{
+ /* Try to write different values to RAM at two addresses */
+ writel(0, CONFIG_SYS_SDRAM_BASE);
+ writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
+ /* Check if the same value is actually observed when reading back */
+ return readl(CONFIG_SYS_SDRAM_BASE) ==
+ readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);
+}
--- /dev/null
+/*
+ * sunxi DRAM controller initialization
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
+ * and earlier U-Boot Allwiner A10 SPL work
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Unfortunately the only documentation we have on the sun7i DRAM
+ * controller is Allwinner boot0 + boot1 code, and that code uses
+ * magic numbers & shifts with no explanations. Hence this code is
+ * rather undocumented and full of magic.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/sys_proto.h>
+
+#define CPU_CFG_CHIP_VER(n) ((n) << 6)
+#define CPU_CFG_CHIP_VER_MASK CPU_CFG_CHIP_VER(0x3)
+#define CPU_CFG_CHIP_REV_A 0x0
+#define CPU_CFG_CHIP_REV_C1 0x1
+#define CPU_CFG_CHIP_REV_C2 0x2
+#define CPU_CFG_CHIP_REV_B 0x3
+
+/*
+ * Wait up to 1s for mask to be clear in given reg.
+ */
+static inline void await_bits_clear(u32 *reg, u32 mask)
+{
+ mctl_await_completion(reg, mask, 0);
+}
+
+/*
+ * Wait up to 1s for mask to be set in given reg.
+ */
+static inline void await_bits_set(u32 *reg, u32 mask)
+{
+ mctl_await_completion(reg, mask, mask);
+}
+
+/*
+ * This performs the external DRAM reset by driving the RESET pin low and
+ * then high again. According to the DDR3 spec, the RESET pin needs to be
+ * kept low for at least 200 us.
+ */
+static void mctl_ddr3_reset(void)
+{
+ struct sunxi_dram_reg *dram =
+ (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+#ifdef CONFIG_MACH_SUN4I
+ struct sunxi_timer_reg *timer =
+ (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
+ u32 reg_val;
+
+ writel(0, &timer->cpu_cfg);
+ reg_val = readl(&timer->cpu_cfg);
+
+ if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
+ CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
+ setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+ udelay(200);
+ clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
+ } else
+#endif
+ {
+ clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
+ udelay(200);
+ setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+ }
+ /* After the RESET pin is de-asserted, the DDR3 spec requires to wait
+ * for additional 500 us before driving the CKE pin (Clock Enable)
+ * high. The duration of this delay can be configured in the SDR_IDCR
+ * (Initialization Delay Configuration Register) and applied
+ * automatically by the DRAM controller during the DDR3 initialization
+ * step. But SDR_IDCR has limited range on sun4i/sun5i hardware and
+ * can't provide sufficient delay at DRAM clock frequencies higher than
+ * 524 MHz (while Allwinner A13 supports DRAM clock frequency up to
+ * 533 MHz according to the datasheet). Additionally, there is no
+ * official documentation for the SDR_IDCR register anywhere, and
+ * there is always a chance that we are interpreting it wrong.
+ * Better be safe than sorry, so add an explicit delay here. */
+ udelay(500);
+}
+
+static void mctl_set_drive(void)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+#ifdef CONFIG_MACH_SUN7I
+ clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
+#else
+ clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
+#endif
+ DRAM_MCR_MODE_EN(0x3) |
+ 0xffc);
+}
+
+static void mctl_itm_disable(void)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+ clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF);
+}
+
+static void mctl_itm_enable(void)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+ clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF);
+}
+
+static void mctl_itm_reset(void)
+{
+ mctl_itm_disable();
+ udelay(1); /* ITM reset needs a bit of delay */
+ mctl_itm_enable();
+ udelay(1);
+}
+
+static void mctl_enable_dll0(u32 phase)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+ clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
+ ((phase >> 16) & 0x3f) << 6);
+ clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE);
+ udelay(2);
+
+ clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE);
+ udelay(22);
+
+ clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET);
+ udelay(22);
+}
+
+/* Get the number of DDR byte lanes */
+static u32 mctl_get_number_of_lanes(void)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+ if ((readl(&dram->dcr) & DRAM_DCR_BUS_WIDTH_MASK) ==
+ DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
+ return 4;
+ else
+ return 2;
+}
+
+/*
+ * Note: This differs from pm/standby in that it checks the bus width
+ */
+static void mctl_enable_dllx(u32 phase)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+ u32 i, number_of_lanes;
+
+ number_of_lanes = mctl_get_number_of_lanes();
+
+ for (i = 1; i <= number_of_lanes; i++) {
+ clrsetbits_le32(&dram->dllcr[i], 0xf << 14,
+ (phase & 0xf) << 14);
+ clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,
+ DRAM_DLLCR_DISABLE);
+ phase >>= 4;
+ }
+ udelay(2);
+
+ for (i = 1; i <= number_of_lanes; i++)
+ clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET |
+ DRAM_DLLCR_DISABLE);
+ udelay(22);
+
+ for (i = 1; i <= number_of_lanes; i++)
+ clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE,
+ DRAM_DLLCR_NRESET);
+ udelay(22);
+}
+
+static u32 hpcr_value[32] = {
+#ifdef CONFIG_MACH_SUN5I
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0x1031, 0x1031, 0x0735, 0x1035,
+ 0x1035, 0x0731, 0x1031, 0,
+ 0x0301, 0x0301, 0x0301, 0x0301,
+ 0x0301, 0x0301, 0x0301, 0
+#endif
+#ifdef CONFIG_MACH_SUN4I
+ 0x0301, 0x0301, 0x0301, 0x0301,
+ 0x0301, 0x0301, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0x1031, 0x1031, 0x0735, 0x5031,
+ 0x1035, 0x0731, 0x1031, 0x0735,
+ 0x1035, 0x1031, 0x0731, 0x1035,
+ 0x1031, 0x0301, 0x0301, 0x0731
+#endif
+#ifdef CONFIG_MACH_SUN7I
+ 0x0301, 0x0301, 0x0301, 0x0301,
+ 0x0301, 0x0301, 0x0301, 0x0301,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0x1031, 0x1031, 0x0735, 0x1035,
+ 0x1035, 0x0731, 0x1031, 0x0735,
+ 0x1035, 0x1031, 0x0731, 0x1035,
+ 0x0001, 0x1031, 0, 0x1031
+ /* last row differs from boot0 source table
+ * 0x1031, 0x0301, 0x0301, 0x0731
+ * but boot0 code skips #28 and #30, and sets #29 and #31 to the
+ * value from #28 entry (0x1031)
+ */
+#endif
+};
+
+static void mctl_configure_hostport(void)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+ u32 i;
+
+ for (i = 0; i < 32; i++)
+ writel(hpcr_value[i], &dram->hpcr[i]);
+}
+
+static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
+{
+ u32 reg_val;
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ u32 pll5p_clk, pll6x_clk;
+ u32 pll5p_div, pll6x_div;
+ u32 pll5p_rate, pll6x_rate;
+
+ /* setup DRAM PLL */
+ reg_val = readl(&ccm->pll5_cfg);
+ reg_val &= ~CCM_PLL5_CTRL_M_MASK; /* set M to 0 (x1) */
+ reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */
+ reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */
+ reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */
+#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
+ /* Old kernels are hardcoded to P=1 (divide by 2) */
+ reg_val |= CCM_PLL5_CTRL_P(1);
+#endif
+ if (clk >= 540 && clk < 552) {
+ /* dram = 540MHz */
+ reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
+ reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
+ reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
+ } else if (clk >= 512 && clk < 528) {
+ /* dram = 512MHz */
+ reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
+ reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
+ reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
+ } else if (clk >= 496 && clk < 504) {
+ /* dram = 496MHz */
+ reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
+ reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
+ reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
+ } else if (clk >= 468 && clk < 480) {
+ /* dram = 468MHz */
+ reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
+ reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
+ reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
+ } else if (clk >= 396 && clk < 408) {
+ /* dram = 396MHz */
+ reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
+ reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
+ reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
+ } else {
+ /* any other frequency that is a multiple of 24 */
+ reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
+ reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
+ reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));
+ }
+ reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN; /* PLL VCO Gain off */
+ reg_val |= CCM_PLL5_CTRL_EN; /* PLL On */
+ writel(reg_val, &ccm->pll5_cfg);
+ udelay(5500);
+
+ setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+ /* reset GPS */
+ clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
+ setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
+ udelay(1);
+ clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
+#endif
+
+ /* setup MBUS clock */
+ if (!mbus_clk)
+ mbus_clk = 300;
+
+ /* PLL5P and PLL6 are the potential clock sources for MBUS */
+ pll6x_clk = clock_get_pll6() / 1000000;
+#ifdef CONFIG_MACH_SUN7I
+ pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
+#endif
+ pll5p_clk = clock_get_pll5p() / 1000000;
+ pll6x_div = DIV_ROUND_UP(pll6x_clk, mbus_clk);
+ pll5p_div = DIV_ROUND_UP(pll5p_clk, mbus_clk);
+ pll6x_rate = pll6x_clk / pll6x_div;
+ pll5p_rate = pll5p_clk / pll5p_div;
+
+ if (pll6x_div <= 16 && pll6x_rate > pll5p_rate) {
+ /* use PLL6 as the MBUS clock source */
+ reg_val = CCM_MBUS_CTRL_GATE |
+ CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
+ CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
+ CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll6x_div));
+ } else if (pll5p_div <= 16) {
+ /* use PLL5P as the MBUS clock source */
+ reg_val = CCM_MBUS_CTRL_GATE |
+ CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
+ CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
+ CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll5p_div));
+ } else {
+ panic("Bad mbus_clk\n");
+ }
+ writel(reg_val, &ccm->mbus_clk_cfg);
+
+ /*
+ * open DRAMC AHB & DLL register clock
+ * close it first
+ */
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+ clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
+#else
+ clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
+#endif
+ udelay(22);
+
+ /* then open it */
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+ setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
+#else
+ setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
+#endif
+ udelay(22);
+}
+
+/*
+ * The data from rslrX and rdgrX registers (X=rank) is stored
+ * in a single 32-bit value using the following format:
+ * bits [31:26] - DQS gating system latency for byte lane 3
+ * bits [25:24] - DQS gating phase select for byte lane 3
+ * bits [23:18] - DQS gating system latency for byte lane 2
+ * bits [17:16] - DQS gating phase select for byte lane 2
+ * bits [15:10] - DQS gating system latency for byte lane 1
+ * bits [ 9:8 ] - DQS gating phase select for byte lane 1
+ * bits [ 7:2 ] - DQS gating system latency for byte lane 0
+ * bits [ 1:0 ] - DQS gating phase select for byte lane 0
+ */
+static void mctl_set_dqs_gating_delay(int rank, u32 dqs_gating_delay)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+ u32 lane, number_of_lanes = mctl_get_number_of_lanes();
+ /* rank0 gating system latency (3 bits per lane: cycles) */
+ u32 slr = readl(rank == 0 ? &dram->rslr0 : &dram->rslr1);
+ /* rank0 gating phase select (2 bits per lane: 90, 180, 270, 360) */
+ u32 dgr = readl(rank == 0 ? &dram->rdgr0 : &dram->rdgr1);
+ for (lane = 0; lane < number_of_lanes; lane++) {
+ u32 tmp = dqs_gating_delay >> (lane * 8);
+ slr &= ~(7 << (lane * 3));
+ slr |= ((tmp >> 2) & 7) << (lane * 3);
+ dgr &= ~(3 << (lane * 2));
+ dgr |= (tmp & 3) << (lane * 2);
+ }
+ writel(slr, rank == 0 ? &dram->rslr0 : &dram->rslr1);
+ writel(dgr, rank == 0 ? &dram->rdgr0 : &dram->rdgr1);
+}
+
+static int dramc_scan_readpipe(void)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+ u32 reg_val;
+
+ /* data training trigger */
+ clrbits_le32(&dram->csr, DRAM_CSR_FAILED);
+ setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
+
+ /* check whether data training process has completed */
+ await_bits_clear(&dram->ccr, DRAM_CCR_DATA_TRAINING);
+
+ /* check data training result */
+ reg_val = readl(&dram->csr);
+ if (reg_val & DRAM_CSR_FAILED)
+ return -1;
+
+ return 0;
+}
+
+static void dramc_clock_output_en(u32 on)
+{
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+ if (on)
+ setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
+ else
+ clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
+#endif
+#ifdef CONFIG_MACH_SUN4I
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ if (on)
+ setbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT);
+ else
+ clrbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT);
+#endif
+}
+
+/* tRFC in nanoseconds for different densities (from the DDR3 spec) */
+static const u16 tRFC_DDR3_table[6] = {
+ /* 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb */
+ 90, 90, 110, 160, 300, 350
+};
+
+static void dramc_set_autorefresh_cycle(u32 clk, u32 density)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+ u32 tRFC, tREFI;
+
+ tRFC = (tRFC_DDR3_table[density] * clk + 999) / 1000;
+ tREFI = (7987 * clk) >> 10; /* <= 7.8us */
+
+ writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr);
+}
+
+/* Calculate the value for A11, A10, A9 bits in MR0 (write recovery) */
+static u32 ddr3_write_recovery(u32 clk)
+{
+ u32 twr_ns = 15; /* DDR3 spec says that it is 15ns for all speed bins */
+ u32 twr_ck = (twr_ns * clk + 999) / 1000;
+ if (twr_ck < 5)
+ return 1;
+ else if (twr_ck <= 8)
+ return twr_ck - 4;
+ else if (twr_ck <= 10)
+ return 5;
+ else
+ return 6;
+}
+
+/*
+ * If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this
+ * means that DRAM is currently in self-refresh mode and retaining the old
+ * data. Since we have no idea what to do in this situation yet, just set this
+ * register to 0 and initialize DRAM in the same way as on any normal reboot
+ * (discarding whatever was stored there).
+ *
+ * Note: on sun7i hardware, the highest 16 bits need to be set to 0x1651 magic
+ * value for this write operation to have any effect. On sun5i hadware this
+ * magic value is not necessary. And on sun4i hardware the writes to this
+ * register seem to have no effect at all.
+ */
+static void mctl_disable_power_save(void)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+ writel(0x16510000, &dram->ppwrsctl);
+}
+
+/*
+ * After the DRAM is powered up or reset, the DDR3 spec requires to wait at
+ * least 500 us before driving the CKE pin (Clock Enable) high. The dram->idct
+ * (SDR_IDCR) register appears to configure this delay, which gets applied
+ * right at the time when the DRAM initialization is activated in the
+ * 'mctl_ddr3_initialize' function.
+ */
+static void mctl_set_cke_delay(void)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+ /* The CKE delay is represented in DRAM clock cycles, multiplied by N
+ * (where N=2 for sun4i/sun5i and N=3 for sun7i). Here it is set to
+ * the maximum possible value 0x1ffff, just like in the Allwinner's
+ * boot0 bootloader. The resulting delay value is somewhere between
+ * ~0.4 ms (sun5i with 648 MHz DRAM clock speed) and ~1.1 ms (sun7i
+ * with 360 MHz DRAM clock speed). */
+ setbits_le32(&dram->idcr, 0x1ffff);
+}
+
+/*
+ * This triggers the DRAM initialization. It performs sending the mode registers
+ * to the DRAM among other things. Very likely the ZQCL command is also getting
+ * executed (to do the initial impedance calibration on the DRAM side of the
+ * wire). The memory controller and the PHY must be already configured before
+ * calling this function.
+ */
+static void mctl_ddr3_initialize(void)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+ setbits_le32(&dram->ccr, DRAM_CCR_INIT);
+ await_bits_clear(&dram->ccr, DRAM_CCR_INIT);
+}
+
+/*
+ * Perform impedance calibration on the DRAM controller side of the wire.
+ */
+static void mctl_set_impedance(u32 zq, bool odt_en)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+ u32 reg_val;
+ u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF;
+
+#ifndef CONFIG_MACH_SUN7I
+ /* Appears that some kind of automatically initiated default
+ * ZQ calibration is already in progress at this point on sun4i/sun5i
+ * hardware, but not on sun7i. So it is reasonable to wait for its
+ * completion before doing anything else. */
+ await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);
+#endif
+
+ /* ZQ calibration is not really useful unless ODT is enabled */
+ if (!odt_en)
+ return;
+
+#ifdef CONFIG_MACH_SUN7I
+ /* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock
+ * unless bit 24 is set in SDR_ZQCR1. Not much is known about the
+ * SDR_ZQCR1 register, but there are hints indicating that it might
+ * be related to periodic impedance re-calibration. This particular
+ * magic value is borrowed from the Allwinner boot0 bootloader, and
+ * using it helps to avoid troubles */
+ writel((1 << 24) | (1 << 1), &dram->zqcr1);
+#endif
+
+ /* Needed at least for sun5i, because it does not self clear there */
+ clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);
+
+ if (zdata) {
+ /* Set the user supplied impedance data */
+ reg_val = DRAM_ZQCR0_ZDEN | zdata;
+ writel(reg_val, &dram->zqcr0);
+ /* no need to wait, this takes effect immediately */
+ } else {
+ /* Do the calibration using the external resistor */
+ reg_val = DRAM_ZQCR0_ZCAL | DRAM_ZQCR0_IMP_DIV(zprog);
+ writel(reg_val, &dram->zqcr0);
+ /* Wait for the new impedance configuration to settle */
+ await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);
+ }
+
+ /* Needed at least for sun5i, because it does not self clear there */
+ clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);
+
+ /* Set I/O configure register */
+ writel(DRAM_IOCR_ODT_EN, &dram->iocr);
+}
+
+static unsigned long dramc_init_helper(struct dram_para *para)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+ u32 reg_val;
+ u32 density;
+ int ret_val;
+
+ /*
+ * only single rank DDR3 is supported by this code even though the
+ * hardware can theoretically support DDR2 and up to two ranks
+ */
+ if (para->type != DRAM_MEMORY_TYPE_DDR3 || para->rank_num != 1)
+ return 0;
+
+ /* setup DRAM relative clock */
+ mctl_setup_dram_clock(para->clock, para->mbus_clock);
+
+ /* Disable any pad power save control */
+ mctl_disable_power_save();
+
+ mctl_set_drive();
+
+ /* dram clock off */
+ dramc_clock_output_en(0);
+
+#ifdef CONFIG_MACH_SUN4I
+ /* select dram controller 1 */
+ writel(DRAM_CSEL_MAGIC, &dram->csel);
+#endif
+
+ mctl_itm_disable();
+ mctl_enable_dll0(para->tpr3);
+
+ /* configure external DRAM */
+ reg_val = DRAM_DCR_TYPE_DDR3;
+ reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3);
+
+ if (para->density == 256)
+ density = DRAM_DCR_CHIP_DENSITY_256M;
+ else if (para->density == 512)
+ density = DRAM_DCR_CHIP_DENSITY_512M;
+ else if (para->density == 1024)
+ density = DRAM_DCR_CHIP_DENSITY_1024M;
+ else if (para->density == 2048)
+ density = DRAM_DCR_CHIP_DENSITY_2048M;
+ else if (para->density == 4096)
+ density = DRAM_DCR_CHIP_DENSITY_4096M;
+ else if (para->density == 8192)
+ density = DRAM_DCR_CHIP_DENSITY_8192M;
+ else
+ density = DRAM_DCR_CHIP_DENSITY_256M;
+
+ reg_val |= DRAM_DCR_CHIP_DENSITY(density);
+ reg_val |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1);
+ reg_val |= DRAM_DCR_RANK_SEL(para->rank_num - 1);
+ reg_val |= DRAM_DCR_CMD_RANK_ALL;
+ reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
+ writel(reg_val, &dram->dcr);
+
+ dramc_clock_output_en(1);
+
+ mctl_set_impedance(para->zq, para->odt_en);
+
+ mctl_set_cke_delay();
+
+ mctl_ddr3_reset();
+
+ udelay(1);
+
+ await_bits_clear(&dram->ccr, DRAM_CCR_INIT);
+
+ mctl_enable_dllx(para->tpr3);
+
+ /* set refresh period */
+ dramc_set_autorefresh_cycle(para->clock, density);
+
+ /* set timing parameters */
+ writel(para->tpr0, &dram->tpr0);
+ writel(para->tpr1, &dram->tpr1);
+ writel(para->tpr2, &dram->tpr2);
+
+ reg_val = DRAM_MR_BURST_LENGTH(0x0);
+#if (defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I))
+ reg_val |= DRAM_MR_POWER_DOWN;
+#endif
+ reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
+ reg_val |= DRAM_MR_WRITE_RECOVERY(ddr3_write_recovery(para->clock));
+ writel(reg_val, &dram->mr);
+
+ writel(para->emr1, &dram->emr);
+ writel(para->emr2, &dram->emr2);
+ writel(para->emr3, &dram->emr3);
+
+ /* disable drift compensation and set passive DQS window mode */
+ clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
+
+#ifdef CONFIG_MACH_SUN7I
+ /* Command rate timing mode 2T & 1T */
+ if (para->tpr4 & 0x1)
+ setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
+#endif
+ /* initialize external DRAM */
+ mctl_ddr3_initialize();
+
+ /* scan read pipe value */
+ mctl_itm_enable();
+
+ /* Hardware DQS gate training */
+ ret_val = dramc_scan_readpipe();
+
+ if (ret_val < 0)
+ return 0;
+
+ /* allow to override the DQS training results with a custom delay */
+ if (para->dqs_gating_delay)
+ mctl_set_dqs_gating_delay(0, para->dqs_gating_delay);
+
+ /* set the DQS gating window type */
+ if (para->active_windowing)
+ clrbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);
+ else
+ setbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);
+
+ mctl_itm_reset();
+
+ /* configure all host port */
+ mctl_configure_hostport();
+
+ return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
+}
+
+unsigned long dramc_init(struct dram_para *para)
+{
+ unsigned long dram_size, actual_density;
+
+ /* If the dram configuration is not provided, use a default */
+ if (!para)
+ return 0;
+
+ /* if everything is known, then autodetection is not necessary */
+ if (para->io_width && para->bus_width && para->density)
+ return dramc_init_helper(para);
+
+ /* try to autodetect the DRAM bus width and density */
+ para->io_width = 16;
+ para->bus_width = 32;
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I)
+ /* only A0-A14 address lines on A10/A13, limiting max density to 4096 */
+ para->density = 4096;
+#else
+ /* all A0-A15 address lines on A20, which allow density 8192 */
+ para->density = 8192;
+#endif
+
+ dram_size = dramc_init_helper(para);
+ if (!dram_size) {
+ /* if 32-bit bus width failed, try 16-bit bus width instead */
+ para->bus_width = 16;
+ dram_size = dramc_init_helper(para);
+ if (!dram_size) {
+ /* if 16-bit bus width also failed, then bail out */
+ return dram_size;
+ }
+ }
+
+ /* check if we need to adjust the density */
+ actual_density = (dram_size >> 17) * para->io_width / para->bus_width;
+
+ if (actual_density != para->density) {
+ /* update the density and re-initialize DRAM again */
+ para->density = actual_density;
+ dram_size = dramc_init_helper(para);
+ }
+
+ return dram_size;
+}
--- /dev/null
+/*
+ * Sun6i platform dram controller init.
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/prcm.h>
+
+#define DRAM_CLK (CONFIG_DRAM_CLK * 1000000)
+
+struct dram_sun6i_para {
+ u8 bus_width;
+ u8 chan;
+ u8 rank;
+ u8 rows;
+ u16 page_size;
+};
+
+static void mctl_sys_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ const int dram_clk_div = 2;
+
+ clock_set_pll5(DRAM_CLK * dram_clk_div, false);
+
+ clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK,
+ CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST |
+ CCM_DRAMCLK_CFG_UPD);
+ mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
+
+ writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg);
+
+ /* deassert mctl reset */
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+
+ /* enable mctl clock */
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+}
+
+static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para)
+{
+ struct sunxi_mctl_phy_reg *mctl_phy;
+
+ if (ch_index == 0)
+ mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+ else
+ mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
+
+ /* disable + reset dlls */
+ writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr);
+ writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr);
+ writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr);
+ if (para->bus_width == 32) {
+ writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr);
+ writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr);
+ }
+ udelay(2);
+
+ /* enable + reset dlls */
+ writel(0, &mctl_phy->acdllcr);
+ writel(0, &mctl_phy->dx0dllcr);
+ writel(0, &mctl_phy->dx1dllcr);
+ if (para->bus_width == 32) {
+ writel(0, &mctl_phy->dx2dllcr);
+ writel(0, &mctl_phy->dx3dllcr);
+ }
+ udelay(22);
+
+ /* enable and release reset of dlls */
+ writel(MCTL_DLLCR_NRESET, &mctl_phy->acdllcr);
+ writel(MCTL_DLLCR_NRESET, &mctl_phy->dx0dllcr);
+ writel(MCTL_DLLCR_NRESET, &mctl_phy->dx1dllcr);
+ if (para->bus_width == 32) {
+ writel(MCTL_DLLCR_NRESET, &mctl_phy->dx2dllcr);
+ writel(MCTL_DLLCR_NRESET, &mctl_phy->dx3dllcr);
+ }
+ udelay(22);
+}
+
+static bool mctl_rank_detect(u32 *gsr0, int rank)
+{
+ const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank;
+ const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank;
+
+ mctl_await_completion(gsr0, done, done);
+ mctl_await_completion(gsr0 + 0x10, done, done);
+
+ return !(readl(gsr0) & err) && !(readl(gsr0 + 0x10) & err);
+}
+
+static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg *mctl_ctl;
+ struct sunxi_mctl_phy_reg *mctl_phy;
+
+ if (ch_index == 0) {
+ mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+ } else {
+ mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE;
+ mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
+ }
+
+ writel(MCTL_MCMD_NOP, &mctl_ctl->mcmd);
+ mctl_await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0);
+
+ /* PHY initialization */
+ writel(MCTL_PGCR, &mctl_phy->pgcr);
+ writel(MCTL_MR0, &mctl_phy->mr0);
+ writel(MCTL_MR1, &mctl_phy->mr1);
+ writel(MCTL_MR2, &mctl_phy->mr2);
+ writel(MCTL_MR3, &mctl_phy->mr3);
+
+ writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST,
+ &mctl_phy->ptr0);
+
+ writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1);
+ writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2);
+
+ writel((MCTL_TCCD << 31) | (MCTL_TRC << 25) | (MCTL_TRRD << 21) |
+ (MCTL_TRAS << 16) | (MCTL_TRCD << 12) | (MCTL_TRP << 8) |
+ (MCTL_TWTR << 5) | (MCTL_TRTP << 2) | (MCTL_TMRD << 0),
+ &mctl_phy->dtpr0);
+
+ writel((MCTL_TDQSCKMAX << 27) | (MCTL_TDQSCK << 24) |
+ (MCTL_TRFC << 16) | (MCTL_TRTODT << 11) |
+ ((MCTL_TMOD - 12) << 9) | (MCTL_TFAW << 3) | (0 << 2) |
+ (MCTL_TAOND << 0), &mctl_phy->dtpr1);
+
+ writel((MCTL_TDLLK << 19) | (MCTL_TCKE << 15) | (MCTL_TXPDLL << 10) |
+ (MCTL_TEXSR << 0), &mctl_phy->dtpr2);
+
+ writel(1, &mctl_ctl->dfitphyupdtype0);
+ writel(MCTL_DCR_DDR3, &mctl_phy->dcr);
+ writel(MCTL_DSGCR, &mctl_phy->dsgcr);
+ writel(MCTL_DXCCR, &mctl_phy->dxccr);
+ writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx0gcr);
+ writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx1gcr);
+ writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx2gcr);
+ writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx3gcr);
+
+ mctl_await_completion(&mctl_phy->pgsr, 0x03, 0x03);
+
+ writel(CONFIG_DRAM_ZQ, &mctl_phy->zq0cr1);
+
+ setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
+ writel(MCTL_PIR_STEP1, &mctl_phy->pir);
+ udelay(10);
+ mctl_await_completion(&mctl_phy->pgsr, 0x1f, 0x1f);
+
+ /* rank detect */
+ if (!mctl_rank_detect(&mctl_phy->dx0gsr0, 1)) {
+ para->rank = 1;
+ clrbits_le32(&mctl_phy->pgcr, MCTL_PGCR_RANK);
+ }
+
+ /*
+ * channel detect, check channel 1 dx0 and dx1 have rank 0, if not
+ * assume nothing is connected to channel 1.
+ */
+ if (ch_index == 1 && !mctl_rank_detect(&mctl_phy->dx0gsr0, 0)) {
+ para->chan = 1;
+ clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
+ return;
+ }
+
+ /* bus width detect, if dx2 and dx3 don't have rank 0, assume 16 bit */
+ if (!mctl_rank_detect(&mctl_phy->dx2gsr0, 0)) {
+ para->bus_width = 16;
+ para->page_size = 2048;
+ setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE);
+ setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE);
+ clrbits_le32(&mctl_phy->dx2gcr, MCTL_DX_GCR_EN);
+ clrbits_le32(&mctl_phy->dx3gcr, MCTL_DX_GCR_EN);
+ }
+
+ setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
+ writel(MCTL_PIR_STEP2, &mctl_phy->pir);
+ udelay(10);
+ mctl_await_completion(&mctl_phy->pgsr, 0x11, 0x11);
+
+ if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK)
+ panic("Training error initialising DRAM\n");
+
+ /* Move to configure state */
+ writel(MCTL_SCTL_CONFIG, &mctl_ctl->sctl);
+ mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x01);
+
+ /* Set number of clks per micro-second */
+ writel(DRAM_CLK / 1000000, &mctl_ctl->togcnt1u);
+ /* Set number of clks per 100 nano-seconds */
+ writel(DRAM_CLK / 10000000, &mctl_ctl->togcnt100n);
+ /* Set memory timing registers */
+ writel(MCTL_TREFI, &mctl_ctl->trefi);
+ writel(MCTL_TMRD, &mctl_ctl->tmrd);
+ writel(MCTL_TRFC, &mctl_ctl->trfc);
+ writel((MCTL_TPREA << 16) | MCTL_TRP, &mctl_ctl->trp);
+ writel(MCTL_TRTW, &mctl_ctl->trtw);
+ writel(MCTL_TAL, &mctl_ctl->tal);
+ writel(MCTL_TCL, &mctl_ctl->tcl);
+ writel(MCTL_TCWL, &mctl_ctl->tcwl);
+ writel(MCTL_TRAS, &mctl_ctl->tras);
+ writel(MCTL_TRC, &mctl_ctl->trc);
+ writel(MCTL_TRCD, &mctl_ctl->trcd);
+ writel(MCTL_TRRD, &mctl_ctl->trrd);
+ writel(MCTL_TRTP, &mctl_ctl->trtp);
+ writel(MCTL_TWR, &mctl_ctl->twr);
+ writel(MCTL_TWTR, &mctl_ctl->twtr);
+ writel(MCTL_TEXSR, &mctl_ctl->texsr);
+ writel(MCTL_TXP, &mctl_ctl->txp);
+ writel(MCTL_TXPDLL, &mctl_ctl->txpdll);
+ writel(MCTL_TZQCS, &mctl_ctl->tzqcs);
+ writel(MCTL_TZQCSI, &mctl_ctl->tzqcsi);
+ writel(MCTL_TDQS, &mctl_ctl->tdqs);
+ writel(MCTL_TCKSRE, &mctl_ctl->tcksre);
+ writel(MCTL_TCKSRX, &mctl_ctl->tcksrx);
+ writel(MCTL_TCKE, &mctl_ctl->tcke);
+ writel(MCTL_TMOD, &mctl_ctl->tmod);
+ writel(MCTL_TRSTL, &mctl_ctl->trstl);
+ writel(MCTL_TZQCL, &mctl_ctl->tzqcl);
+ writel(MCTL_TMRR, &mctl_ctl->tmrr);
+ writel(MCTL_TCKESR, &mctl_ctl->tckesr);
+ writel(MCTL_TDPD, &mctl_ctl->tdpd);
+
+ /* Unknown magic performed by boot0 */
+ setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3);
+ clrbits_le32(&mctl_ctl->dfiodtcfg1, 0x1f);
+
+ /* Select 16/32-bits mode for MCTL */
+ if (para->bus_width == 16)
+ setbits_le32(&mctl_ctl->ppcfg, 1);
+
+ /* Set DFI timing registers */
+ writel(MCTL_TCWL, &mctl_ctl->dfitphywrl);
+ writel(MCTL_TCL - 1, &mctl_ctl->dfitrdden);
+ writel(MCTL_DFITPHYRDL, &mctl_ctl->dfitphyrdl);
+ writel(MCTL_DFISTCFG0, &mctl_ctl->dfistcfg0);
+
+ writel(MCTL_MCFG_DDR3, &mctl_ctl->mcfg);
+
+ /* DFI update configuration register */
+ writel(MCTL_DFIUPDCFG_UPD, &mctl_ctl->dfiupdcfg);
+
+ /* Move to access state */
+ writel(MCTL_SCTL_ACCESS, &mctl_ctl->sctl);
+ mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x03);
+}
+
+static void mctl_com_init(struct dram_sun6i_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_phy_reg * const mctl_phy1 =
+ (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
+ struct sunxi_prcm_reg * const prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+ writel(MCTL_CR_UNKNOWN | MCTL_CR_CHANNEL(para->chan) | MCTL_CR_DDR3 |
+ ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) |
+ MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
+ MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr);
+
+ /* Unknown magic performed by boot0 */
+ setbits_le32(&mctl_com->dbgcr, (1 << 6));
+
+ if (para->chan == 1) {
+ /* Shutdown channel 1 */
+ setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE);
+ setbits_le32(&mctl_phy1->dxccr, MCTL_DXCCR_DISABLE);
+ clrbits_le32(&mctl_phy1->dsgcr, MCTL_DSGCR_ENABLE);
+ /*
+ * CH0 ?? this is what boot0 does. Leave as is until we can
+ * confirm this.
+ */
+ setbits_le32(&prcm->vdd_sys_pwroff,
+ PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF);
+ }
+}
+
+static void mctl_port_cfg(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* enable DRAM AXI clock for CPU access */
+ setbits_le32(&ccm->axi_gate, 1 << AXI_GATE_OFFSET_DRAM);
+
+ /* Bunch of magic writes performed by boot0 */
+ writel(0x00400302, &mctl_com->rmcr[0]);
+ writel(0x01000307, &mctl_com->rmcr[1]);
+ writel(0x00400302, &mctl_com->rmcr[2]);
+ writel(0x01000307, &mctl_com->rmcr[3]);
+ writel(0x01000307, &mctl_com->rmcr[4]);
+ writel(0x01000303, &mctl_com->rmcr[6]);
+ writel(0x01000303, &mctl_com->mmcr[0]);
+ writel(0x00400310, &mctl_com->mmcr[1]);
+ writel(0x01000307, &mctl_com->mmcr[2]);
+ writel(0x01000303, &mctl_com->mmcr[3]);
+ writel(0x01800303, &mctl_com->mmcr[4]);
+ writel(0x01800303, &mctl_com->mmcr[5]);
+ writel(0x01800303, &mctl_com->mmcr[6]);
+ writel(0x01800303, &mctl_com->mmcr[7]);
+ writel(0x01000303, &mctl_com->mmcr[8]);
+ writel(0x00000002, &mctl_com->mmcr[15]);
+ writel(0x00000310, &mctl_com->mbagcr[0]);
+ writel(0x00400310, &mctl_com->mbagcr[1]);
+ writel(0x00400310, &mctl_com->mbagcr[2]);
+ writel(0x00000307, &mctl_com->mbagcr[3]);
+ writel(0x00000317, &mctl_com->mbagcr[4]);
+ writel(0x00000307, &mctl_com->mbagcr[5]);
+}
+
+unsigned long sunxi_dram_init(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ u32 offset;
+ int bank, bus, columns;
+
+ /* Set initial parameters, these get modified by the autodetect code */
+ struct dram_sun6i_para para = {
+ .bus_width = 32,
+ .chan = 2,
+ .rank = 2,
+ .page_size = 4096,
+ .rows = 16,
+ };
+
+ /* A31s only has one channel */
+ if (sunxi_get_ss_bonding_id() == SUNXI_SS_BOND_ID_A31S)
+ para.chan = 1;
+
+ mctl_sys_init();
+
+ mctl_dll_init(0, ¶);
+ setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN);
+
+ if (para.chan == 2) {
+ mctl_dll_init(1, ¶);
+ setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
+ }
+
+ setbits_le32(&mctl_com->ccr, MCTL_CCR_MASTER_CLK_EN);
+
+ mctl_channel_init(0, ¶);
+ if (para.chan == 2)
+ mctl_channel_init(1, ¶);
+
+ mctl_com_init(¶);
+ mctl_port_cfg();
+
+ /*
+ * Change to 1 ch / sequence / 8192 byte pages / 16 rows /
+ * 8 bit banks / 1 rank mode.
+ */
+ clrsetbits_le32(&mctl_com->cr,
+ MCTL_CR_CHANNEL_MASK | MCTL_CR_PAGE_SIZE_MASK |
+ MCTL_CR_ROW_MASK | MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
+ MCTL_CR_CHANNEL(1) | MCTL_CR_SEQUENCE |
+ MCTL_CR_PAGE_SIZE(8192) | MCTL_CR_ROW(16) |
+ MCTL_CR_BANK(1) | MCTL_CR_RANK(1));
+
+ /* Detect and set page size */
+ for (columns = 7; columns < 20; columns++) {
+ if (mctl_mem_matches(1 << columns))
+ break;
+ }
+ bus = (para.bus_width == 32) ? 2 : 1;
+ columns -= bus;
+ para.page_size = (1 << columns) * (bus << 1);
+ clrsetbits_le32(&mctl_com->cr, MCTL_CR_PAGE_SIZE_MASK,
+ MCTL_CR_PAGE_SIZE(para.page_size));
+
+ /* Detect and set rows */
+ for (para.rows = 11; para.rows < 16; para.rows++) {
+ offset = 1 << (para.rows + columns + bus);
+ if (mctl_mem_matches(offset))
+ break;
+ }
+ clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
+ MCTL_CR_ROW(para.rows));
+
+ /* Detect bank size */
+ offset = 1 << (para.rows + columns + bus + 2);
+ bank = mctl_mem_matches(offset) ? 0 : 1;
+
+ /* Restore interleave, chan and rank values, set bank size */
+ clrsetbits_le32(&mctl_com->cr,
+ MCTL_CR_CHANNEL_MASK | MCTL_CR_SEQUENCE |
+ MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
+ MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) |
+ MCTL_CR_RANK(para.rank));
+
+ return 1 << (para.rank + para.rows + bank + columns + para.chan + bus);
+}
--- /dev/null
+/*
+ * Sun8i platform dram controller init.
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Note this code uses a lot of magic hex values, that is because this code
+ * simply replays the init sequence as done by the Allwinner boot0 code, so
+ * we do not know what these values mean. There are no symbolic constants for
+ * these magic values, since we do not know how to name them and making up
+ * names for them is not useful.
+ *
+ * The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one
+ * found in the TI Keystone2 documentation:
+ * http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf
+ * "Table4-2 DDR3 PHY Registers"
+ * This may be used as a (possible) reference for future work / cleanups.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/prcm.h>
+
+static const struct dram_para dram_para = {
+ .clock = CONFIG_DRAM_CLK,
+ .type = 3,
+ .zq = CONFIG_DRAM_ZQ,
+ .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN),
+ .odt_correction = CONFIG_DRAM_ODT_CORRECTION,
+ .para1 = 0, /* not used (only used when tpr13 bit 31 is set */
+ .para2 = 0, /* not used (only used when tpr13 bit 31 is set */
+ .mr0 = 6736,
+ .mr1 = 4,
+ .mr2 = 16,
+ .mr3 = 0,
+ /* tpr0 - 10 contain timing constants or-ed together in u32 vals */
+ .tpr0 = 0x2ab83def,
+ .tpr1 = 0x18082356,
+ .tpr2 = 0x00034156,
+ .tpr3 = 0x448c5533,
+ .tpr4 = 0x08010d00,
+ .tpr5 = 0x0340b20f,
+ .tpr6 = 0x20d118cc,
+ .tpr7 = 0x14062485,
+ .tpr8 = 0x220d1d52,
+ .tpr9 = 0x1e078c22,
+ .tpr10 = 0x3c,
+ .tpr11 = 0, /* not used */
+ .tpr12 = 0, /* not used */
+ .tpr13 = 0x30000,
+};
+
+static void mctl_sys_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* enable pll5, note the divide by 2 is deliberate! */
+ clock_set_pll5(dram_para.clock * 1000000 / 2,
+ dram_para.tpr13 & 0x40000);
+
+ /* deassert ahb mctl reset */
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+
+ /* enable ahb mctl clock */
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+}
+
+static void mctl_apply_odt_correction(u32 *reg, int correction)
+{
+ int val;
+
+ val = (readl(reg) >> 8) & 0xff;
+ val += correction;
+
+ /* clamp */
+ if (val < 0)
+ val = 0;
+ else if (val > 255)
+ val = 255;
+
+ clrsetbits_le32(reg, 0xff00, val << 8);
+}
+
+static void mctl_init(u32 *bus_width)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ struct sunxi_mctl_phy_reg * const mctl_phy =
+ (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+
+ if (dram_para.tpr13 & 0x20)
+ writel(0x40b, &mctl_phy->dcr);
+ else
+ writel(0x1000040b, &mctl_phy->dcr);
+
+ if (dram_para.clock >= 480)
+ writel(0x5c000, &mctl_phy->dllgcr);
+ else
+ writel(0xdc000, &mctl_phy->dllgcr);
+
+ writel(0x0a003e3f, &mctl_phy->pgcr0);
+ writel(0x03008421, &mctl_phy->pgcr1);
+
+ writel(dram_para.mr0, &mctl_phy->mr0);
+ writel(dram_para.mr1, &mctl_phy->mr1);
+ writel(dram_para.mr2, &mctl_phy->mr2);
+ writel(dram_para.mr3, &mctl_phy->mr3);
+
+ if (!(dram_para.tpr13 & 0x10000)) {
+ clrsetbits_le32(&mctl_phy->dx0gcr, 0x3800, 0x2000);
+ clrsetbits_le32(&mctl_phy->dx1gcr, 0x3800, 0x2000);
+ }
+
+ /*
+ * All the masking and shifting below converts what I assume are DDR
+ * timing constants from Allwinner dram_para tpr format to the actual
+ * timing registers format.
+ */
+
+ writel((dram_para.tpr0 & 0x000fffff), &mctl_phy->ptr2);
+ writel((dram_para.tpr1 & 0x1fffffff), &mctl_phy->ptr3);
+ writel((dram_para.tpr0 & 0x3ff00000) >> 2 |
+ (dram_para.tpr2 & 0x0003ffff), &mctl_phy->ptr4);
+
+ writel(dram_para.tpr3, &mctl_phy->dtpr0);
+ writel(dram_para.tpr4, &mctl_phy->dtpr2);
+
+ writel(0x01000081, &mctl_phy->dtcr);
+
+ if (dram_para.clock <= 240 || !dram_para.odt_en) {
+ clrbits_le32(&mctl_phy->dx0gcr, 0x600);
+ clrbits_le32(&mctl_phy->dx1gcr, 0x600);
+ }
+ if (dram_para.clock <= 240) {
+ writel(0, &mctl_phy->odtcr);
+ writel(0, &mctl_ctl->odtmap);
+ }
+
+ writel(((dram_para.tpr5 & 0x0f00) << 12) |
+ ((dram_para.tpr5 & 0x00f8) << 9) |
+ ((dram_para.tpr5 & 0x0007) << 8),
+ &mctl_ctl->rfshctl0);
+
+ writel(((dram_para.tpr5 & 0x0003f000) << 12) |
+ ((dram_para.tpr5 & 0x00fc0000) >> 2) |
+ ((dram_para.tpr5 & 0x3f000000) >> 16) |
+ ((dram_para.tpr6 & 0x0000003f) >> 0),
+ &mctl_ctl->dramtmg0);
+
+ writel(((dram_para.tpr6 & 0x000007c0) << 10) |
+ ((dram_para.tpr6 & 0x0000f800) >> 3) |
+ ((dram_para.tpr6 & 0x003f0000) >> 16),
+ &mctl_ctl->dramtmg1);
+
+ writel(((dram_para.tpr6 & 0x0fc00000) << 2) |
+ ((dram_para.tpr7 & 0x0000001f) << 16) |
+ ((dram_para.tpr7 & 0x000003e0) << 3) |
+ ((dram_para.tpr7 & 0x0000fc00) >> 10),
+ &mctl_ctl->dramtmg2);
+
+ writel(((dram_para.tpr7 & 0x03ff0000) >> 16) |
+ ((dram_para.tpr6 & 0xf0000000) >> 16),
+ &mctl_ctl->dramtmg3);
+
+ writel(((dram_para.tpr7 & 0x3c000000) >> 2 ) |
+ ((dram_para.tpr8 & 0x00000007) << 16) |
+ ((dram_para.tpr8 & 0x00000038) << 5) |
+ ((dram_para.tpr8 & 0x000003c0) >> 6),
+ &mctl_ctl->dramtmg4);
+
+ writel(((dram_para.tpr8 & 0x00003c00) << 14) |
+ ((dram_para.tpr8 & 0x0003c000) << 2) |
+ ((dram_para.tpr8 & 0x00fc0000) >> 10) |
+ ((dram_para.tpr8 & 0x0f000000) >> 24),
+ &mctl_ctl->dramtmg5);
+
+ writel(0x00000008, &mctl_ctl->dramtmg8);
+
+ writel(((dram_para.tpr8 & 0xf0000000) >> 4) |
+ ((dram_para.tpr9 & 0x00007c00) << 6) |
+ ((dram_para.tpr9 & 0x000003e0) << 3) |
+ ((dram_para.tpr9 & 0x0000001f) >> 0),
+ &mctl_ctl->pitmg0);
+
+ setbits_le32(&mctl_ctl->pitmg1, 0x80000);
+
+ writel(((dram_para.tpr9 & 0x003f8000) << 9) | 0x2001,
+ &mctl_ctl->sched);
+
+ writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3);
+ writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4);
+
+ writel(0x00000000, &mctl_ctl->pimisc);
+ writel(0x80000000, &mctl_ctl->upd0);
+
+ writel(((dram_para.tpr9 & 0xffc00000) >> 22) |
+ ((dram_para.tpr10 & 0x00000fff) << 16),
+ &mctl_ctl->rfshtmg);
+
+ if (dram_para.tpr13 & 0x20)
+ writel(0x01040001, &mctl_ctl->mstr);
+ else
+ writel(0x01040401, &mctl_ctl->mstr);
+
+ if (!(dram_para.tpr13 & 0x20000)) {
+ writel(0x00000002, &mctl_ctl->pwrctl);
+ writel(0x00008001, &mctl_ctl->pwrtmg);
+ }
+
+ writel(0x00000001, &mctl_ctl->rfshctl3);
+ writel(0x00000001, &mctl_ctl->pimisc);
+
+ /* deassert dram_clk_cfg reset */
+ setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
+
+ setbits_le32(&mctl_com->ccr, 0x80000);
+
+ /* zq stuff */
+ writel((dram_para.zq >> 8) & 0xff, &mctl_phy->zqcr1);
+
+ writel(0x00000003, &mctl_phy->pir);
+ udelay(10);
+ mctl_await_completion(&mctl_phy->pgsr0, 0x09, 0x09);
+
+ writel(readl(&mctl_phy->zqsr0) | 0x10000000, &mctl_phy->zqcr2);
+ writel(dram_para.zq & 0xff, &mctl_phy->zqcr1);
+
+ /* A23-v1.0 SDK uses 0xfdf3, A23-v2.0 SDK uses 0x5f3 */
+ writel(0x000005f3, &mctl_phy->pir);
+ udelay(10);
+ mctl_await_completion(&mctl_phy->pgsr0, 0x03, 0x03);
+
+ if (readl(&mctl_phy->dx1gsr0) & 0x1000000) {
+ *bus_width = 8;
+ writel(0, &mctl_phy->dx1gcr);
+ writel(dram_para.zq & 0xff, &mctl_phy->zqcr1);
+ writel(0x5f3, &mctl_phy->pir);
+ udelay(10000);
+ setbits_le32(&mctl_ctl->mstr, 0x1000);
+ } else
+ *bus_width = 16;
+
+ if (dram_para.odt_correction) {
+ mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1,
+ dram_para.odt_correction);
+ mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1,
+ dram_para.odt_correction);
+ }
+
+ mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01);
+
+ writel(0x08003e3f, &mctl_phy->pgcr0);
+ writel(0x00000000, &mctl_ctl->rfshctl3);
+}
+
+unsigned long sunxi_dram_init(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ const u32 columns = 13;
+ u32 bus, bus_width, offset, page_size, rows;
+
+ mctl_sys_init();
+ mctl_init(&bus_width);
+
+ if (bus_width == 16) {
+ page_size = 8;
+ bus = 1;
+ } else {
+ page_size = 7;
+ bus = 0;
+ }
+
+ if (!(dram_para.tpr13 & 0x80000000)) {
+ /* Detect and set rows */
+ writel(0x000310f4 | MCTL_CR_PAGE_SIZE(page_size),
+ &mctl_com->cr);
+ setbits_le32(&mctl_com->swonr, 0x0003ffff);
+ for (rows = 11; rows < 16; rows++) {
+ offset = 1 << (rows + columns + bus);
+ if (mctl_mem_matches(offset))
+ break;
+ }
+ clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
+ MCTL_CR_ROW(rows));
+ } else {
+ rows = (dram_para.para1 >> 16) & 0xff;
+ writel(((dram_para.para2 & 0x000000f0) << 11) |
+ ((rows - 1) << 4) |
+ ((dram_para.para1 & 0x0f000000) >> 22) |
+ 0x31000 | MCTL_CR_PAGE_SIZE(page_size),
+ &mctl_com->cr);
+ setbits_le32(&mctl_com->swonr, 0x0003ffff);
+ }
+
+ /* Setup DRAM master priority? If this is left out things still work */
+ writel(0x00000008, &mctl_com->mcr0_0);
+ writel(0x0001000d, &mctl_com->mcr1_0);
+ writel(0x00000004, &mctl_com->mcr0_1);
+ writel(0x00000080, &mctl_com->mcr1_1);
+ writel(0x00000004, &mctl_com->mcr0_2);
+ writel(0x00000019, &mctl_com->mcr1_2);
+ writel(0x00000004, &mctl_com->mcr0_3);
+ writel(0x00000080, &mctl_com->mcr1_3);
+ writel(0x00000004, &mctl_com->mcr0_4);
+ writel(0x01010040, &mctl_com->mcr1_4);
+ writel(0x00000004, &mctl_com->mcr0_5);
+ writel(0x0001002f, &mctl_com->mcr1_5);
+ writel(0x00000004, &mctl_com->mcr0_6);
+ writel(0x00010020, &mctl_com->mcr1_6);
+ writel(0x00000004, &mctl_com->mcr0_7);
+ writel(0x00010020, &mctl_com->mcr1_7);
+ writel(0x00000008, &mctl_com->mcr0_8);
+ writel(0x00000001, &mctl_com->mcr1_8);
+ writel(0x00000008, &mctl_com->mcr0_9);
+ writel(0x00000005, &mctl_com->mcr1_9);
+ writel(0x00000008, &mctl_com->mcr0_10);
+ writel(0x00000003, &mctl_com->mcr1_10);
+ writel(0x00000008, &mctl_com->mcr0_11);
+ writel(0x00000005, &mctl_com->mcr1_11);
+ writel(0x00000008, &mctl_com->mcr0_12);
+ writel(0x00000003, &mctl_com->mcr1_12);
+ writel(0x00000008, &mctl_com->mcr0_13);
+ writel(0x00000004, &mctl_com->mcr1_13);
+ writel(0x00000008, &mctl_com->mcr0_14);
+ writel(0x00000002, &mctl_com->mcr1_14);
+ writel(0x00000008, &mctl_com->mcr0_15);
+ writel(0x00000003, &mctl_com->mcr1_15);
+ writel(0x00010138, &mctl_com->bwcr);
+
+ return 1 << (rows + columns + bus);
+}
--- /dev/null
+/*
+ * Sun8i a33 platform dram controller init.
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ * Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/prcm.h>
+
+/* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */
+#define DRAM_CLK_MUL 2
+#define DRAM_CLK_DIV 4
+#define DRAM_SIGMA_DELTA_ENABLE 1
+
+struct dram_para {
+ u8 cs1;
+ u8 seq;
+ u8 bank;
+ u8 rank;
+ u8 rows;
+ u8 bus_width;
+ u16 page_size;
+};
+
+static void mctl_set_cr(struct dram_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |
+ MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 |
+ (para->seq ? MCTL_CR_SEQUENCE : 0) |
+ ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
+ MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
+ MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),
+ &mctl_com->cr);
+}
+
+static void auto_detect_dram_size(struct dram_para *para)
+{
+ u8 orig_rank = para->rank;
+ int rows, columns;
+
+ /* Row detect */
+ para->page_size = 512;
+ para->seq = 1;
+ para->rows = 16;
+ para->rank = 1;
+ mctl_set_cr(para);
+ for (rows = 11 ; rows < 16 ; rows++) {
+ if (mctl_mem_matches(1 << (rows + 9))) /* row-column */
+ break;
+ }
+
+ /* Column (page size) detect */
+ para->rows = 11;
+ para->page_size = 8192;
+ mctl_set_cr(para);
+ for (columns = 9 ; columns < 13 ; columns++) {
+ if (mctl_mem_matches(1 << columns))
+ break;
+ }
+
+ para->seq = 0;
+ para->rank = orig_rank;
+ para->rows = rows;
+ para->page_size = 1 << columns;
+ mctl_set_cr(para);
+}
+
+static inline int ns_to_t(int nanoseconds)
+{
+ const unsigned int ctrl_freq =
+ CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV;
+
+ return (ctrl_freq * nanoseconds + 999) / 1000;
+}
+
+static void auto_set_timing_para(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ u32 reg_val;
+
+ u8 tccd = 2;
+ u8 tfaw = ns_to_t(50);
+ u8 trrd = max(ns_to_t(10), 4);
+ u8 trcd = ns_to_t(15);
+ u8 trc = ns_to_t(53);
+ u8 txp = max(ns_to_t(8), 3);
+ u8 twtr = max(ns_to_t(8), 4);
+ u8 trtp = max(ns_to_t(8), 4);
+ u8 twr = max(ns_to_t(15), 3);
+ u8 trp = ns_to_t(15);
+ u8 tras = ns_to_t(38);
+
+ u16 trefi = ns_to_t(7800) / 32;
+ u16 trfc = ns_to_t(350);
+
+ /* Fixed timing parameters */
+ u8 tmrw = 0;
+ u8 tmrd = 4;
+ u8 tmod = 12;
+ u8 tcke = 3;
+ u8 tcksrx = 5;
+ u8 tcksre = 5;
+ u8 tckesr = 4;
+ u8 trasmax = 24;
+ u8 tcl = 6; /* CL 12 */
+ u8 tcwl = 4; /* CWL 8 */
+ u8 t_rdata_en = 4;
+ u8 wr_latency = 2;
+
+ u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
+ u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
+ u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
+ u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
+
+ u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
+ u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
+ u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
+
+ /* Set work mode register */
+ mctl_set_cr(para);
+ /* Set mode register */
+ writel(MCTL_MR0, &mctl_ctl->mr0);
+ writel(MCTL_MR1, &mctl_ctl->mr1);
+ writel(MCTL_MR2, &mctl_ctl->mr2);
+ writel(MCTL_MR3, &mctl_ctl->mr3);
+ /* Set dram timing */
+ reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0);
+ writel(reg_val, &mctl_ctl->dramtmg0);
+ reg_val = (txp << 16) | (trtp << 8) | (trc << 0);
+ writel(reg_val, &mctl_ctl->dramtmg1);
+ reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0);
+ writel(reg_val, &mctl_ctl->dramtmg2);
+ reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0);
+ writel(reg_val, &mctl_ctl->dramtmg3);
+ reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0);
+ writel(reg_val, &mctl_ctl->dramtmg4);
+ reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0);
+ writel(reg_val, &mctl_ctl->dramtmg5);
+ /* Set two rank timing and exit self-refresh timing */
+ reg_val = readl(&mctl_ctl->dramtmg8);
+ reg_val &= ~(0xff << 8);
+ reg_val &= ~(0xff << 0);
+ reg_val |= (0x33 << 8);
+ reg_val |= (0x8 << 0);
+ writel(reg_val, &mctl_ctl->dramtmg8);
+ /* Set phy interface time */
+ reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
+ | (wr_latency << 0);
+ /* PHY interface write latency and read latency configure */
+ writel(reg_val, &mctl_ctl->pitmg0);
+ /* Set phy time PTR0-2 use default */
+ writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3);
+ writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4);
+ /* Set refresh timing */
+ reg_val = (trefi << 16) | (trfc << 0);
+ writel(reg_val, &mctl_ctl->rfshtmg);
+}
+
+static void mctl_set_pir(u32 val)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ writel(val, &mctl_ctl->pir);
+ mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1);
+}
+
+static void mctl_data_train_cfg(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ if (para->rank == 2)
+ clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);
+ else
+ clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);
+}
+
+static int mctl_train_dram(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ mctl_data_train_cfg(para);
+ mctl_set_pir(0x5f3);
+
+ return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0;
+}
+
+static int mctl_channel_init(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ u32 low_data_lines_status; /* Training status of datalines 0 - 7 */
+ u32 high_data_lines_status; /* Training status of datalines 8 - 15 */
+
+ auto_set_timing_para(para);
+
+ /* Disable dram VTC */
+ clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0);
+
+ /* Set ODT */
+ if ((CONFIG_DRAM_CLK > 400) && IS_ENABLED(CONFIG_DRAM_ODT_EN)) {
+ setbits_le32(DXnGCR0(0), 0x3 << 9);
+ setbits_le32(DXnGCR0(1), 0x3 << 9);
+ } else {
+ clrbits_le32(DXnGCR0(0), 0x3 << 9);
+ clrbits_le32(DXnGCR0(1), 0x3 << 9);
+ }
+
+ /* set PLL configuration */
+ if (CONFIG_DRAM_CLK >= 480)
+ setbits_le32(&mctl_ctl->pllgcr, 0x1 << 18);
+ else
+ setbits_le32(&mctl_ctl->pllgcr, 0x3 << 18);
+
+ /* Auto detect dram config, set 2 rank and 16bit bus-width */
+ para->cs1 = 0;
+ para->rank = 2;
+ para->bus_width = 16;
+ mctl_set_cr(para);
+
+ /* Open DQS gating */
+ clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
+ clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));
+
+ mctl_data_train_cfg(para);
+
+ /* ZQ calibration */
+ writel(CONFIG_DRAM_ZQ & 0xff, &mctl_ctl->zqcr1);
+ /* CA calibration */
+ mctl_set_pir(0x00000003);
+ /* More ZQ calibration */
+ writel(readl(&mctl_ctl->zqsr0) | 0x10000000, &mctl_ctl->zqcr2);
+ writel((CONFIG_DRAM_ZQ >> 8) & 0xff, &mctl_ctl->zqcr1);
+
+ /* DQS gate training */
+ if (mctl_train_dram(para) != 0) {
+ low_data_lines_status = (readl(DXnGSR0(0)) >> 24) & 0x03;
+ high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03;
+
+ if (low_data_lines_status == 0x3)
+ return -EIO;
+
+ /* DRAM has only one rank */
+ para->rank = 1;
+ mctl_set_cr(para);
+
+ if (low_data_lines_status == high_data_lines_status)
+ goto done; /* 16 bit bus, 1 rank */
+
+ if (!(low_data_lines_status & high_data_lines_status)) {
+ /* Retry 16 bit bus-width with CS1 set */
+ para->cs1 = 1;
+ mctl_set_cr(para);
+ if (mctl_train_dram(para) == 0)
+ goto done;
+ }
+
+ /* Try 8 bit bus-width */
+ writel(0x0, DXnGCR0(1)); /* Disable high DQ */
+ para->cs1 = 0;
+ para->bus_width = 8;
+ mctl_set_cr(para);
+ if (mctl_train_dram(para) != 0)
+ return -EIO;
+ }
+done:
+ /* Check the dramc status */
+ mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
+
+ /* Close DQS gating */
+ setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);
+
+ /* Enable master access */
+ writel(0xffffffff, &mctl_com->maer);
+
+ return 0;
+}
+
+static void mctl_sys_init(struct dram_para *para)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ clrsetbits_le32(&ccm->dram_pll_cfg, CCM_DRAMPLL_CFG_SRC_MASK,
+ CCM_DRAMPLL_CFG_SRC_PLL11);
+
+ clock_set_pll11(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL,
+ DRAM_SIGMA_DELTA_ENABLE);
+
+ clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK,
+ CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) |
+ CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD);
+ mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
+
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+ setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
+ setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
+
+ /* Set dram master access priority */
+ writel(0x0, &mctl_com->mapr);
+ writel(0x0f802f01, &mctl_ctl->sched);
+ writel(0x0000400f, &mctl_ctl->clken); /* normal */
+
+ udelay(250);
+}
+
+unsigned long sunxi_dram_init(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ struct dram_para para = {
+ .cs1 = 0,
+ .bank = 1,
+ .rank = 1,
+ .rows = 15,
+ .bus_width = 16,
+ .page_size = 2048,
+ };
+
+ mctl_sys_init(¶);
+
+ if (mctl_channel_init(¶) != 0)
+ return 0;
+
+ auto_detect_dram_size(¶);
+
+ /* Enable master software clk */
+ writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr);
+
+ /* Set DRAM ODT MAP */
+ if (para.rank == 2)
+ writel(0x00000303, &mctl_ctl->odtmap);
+ else
+ writel(0x00000201, &mctl_ctl->odtmap);
+
+ return para.page_size * (para.bus_width / 8) *
+ (1 << (para.bank + para.rank + para.rows));
+}
--- /dev/null
+/*
+ * Sun8i a33 platform dram controller init.
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ * Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/prcm.h>
+
+#define DRAM_CLK_MUL 2
+#define DRAM_CLK_DIV 1
+
+struct dram_para {
+ u8 cs1;
+ u8 seq;
+ u8 bank;
+ u8 rank;
+ u8 rows;
+ u8 bus_width;
+ u8 dram_type;
+ u16 page_size;
+};
+
+static void mctl_set_cr(struct dram_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |
+ MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) |
+ (para->seq ? MCTL_CR_SEQUENCE : 0) |
+ ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
+ MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
+ MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),
+ &mctl_com->cr);
+}
+
+static void auto_detect_dram_size(struct dram_para *para)
+{
+ u8 orig_rank = para->rank;
+ int rows, columns;
+
+ /* Row detect */
+ para->page_size = 512;
+ para->seq = 1;
+ para->rows = 16;
+ para->rank = 1;
+ mctl_set_cr(para);
+ for (rows = 11 ; rows < 16 ; rows++) {
+ if (mctl_mem_matches(1 << (rows + 9))) /* row-column */
+ break;
+ }
+
+ /* Column (page size) detect */
+ para->rows = 11;
+ para->page_size = 8192;
+ mctl_set_cr(para);
+ for (columns = 9 ; columns < 13 ; columns++) {
+ if (mctl_mem_matches(1 << columns))
+ break;
+ }
+
+ para->seq = 0;
+ para->rank = orig_rank;
+ para->rows = rows;
+ para->page_size = 1 << columns;
+ mctl_set_cr(para);
+}
+
+static inline int ns_to_t(int nanoseconds)
+{
+ const unsigned int ctrl_freq =
+ CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV;
+
+ return (ctrl_freq * nanoseconds + 999) / 1000;
+}
+
+static void auto_set_timing_para(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ u32 reg_val;
+
+ u8 tccd = 2;
+ u8 tfaw = ns_to_t(50);
+ u8 trrd = max(ns_to_t(10), 4);
+ u8 trcd = ns_to_t(15);
+ u8 trc = ns_to_t(53);
+ u8 txp = max(ns_to_t(8), 3);
+ u8 twtr = max(ns_to_t(8), 4);
+ u8 trtp = max(ns_to_t(8), 4);
+ u8 twr = max(ns_to_t(15), 3);
+ u8 trp = ns_to_t(15);
+ u8 tras = ns_to_t(38);
+
+ u16 trefi = ns_to_t(7800) / 32;
+ u16 trfc = ns_to_t(350);
+
+ /* Fixed timing parameters */
+ u8 tmrw = 0;
+ u8 tmrd = 4;
+ u8 tmod = 12;
+ u8 tcke = 3;
+ u8 tcksrx = 5;
+ u8 tcksre = 5;
+ u8 tckesr = 4;
+ u8 trasmax = 24;
+ u8 tcl = 6; /* CL 12 */
+ u8 tcwl = 4; /* CWL 8 */
+ u8 t_rdata_en = 4;
+ u8 wr_latency = 2;
+
+ u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
+ u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
+ u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
+ u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
+
+ u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
+ u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
+ u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
+
+ /* Set work mode register */
+ mctl_set_cr(para);
+ /* Set mode register */
+ if (para->dram_type == DRAM_TYPE_DDR3) {
+ writel(MCTL_MR0, &mctl_ctl->mr0);
+ writel(MCTL_MR1, &mctl_ctl->mr1);
+ writel(MCTL_MR2, &mctl_ctl->mr2);
+ writel(MCTL_MR3, &mctl_ctl->mr3);
+ } else if (para->dram_type == DRAM_TYPE_LPDDR3) {
+ writel(MCTL_LPDDR3_MR0, &mctl_ctl->mr0);
+ writel(MCTL_LPDDR3_MR1, &mctl_ctl->mr1);
+ writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr2);
+ writel(MCTL_LPDDR3_MR3, &mctl_ctl->mr3);
+
+ /* timing parameters for LPDDR3 */
+ tfaw = max(ns_to_t(50), 4);
+ trrd = max(ns_to_t(10), 2);
+ trcd = max(ns_to_t(24), 2);
+ trc = ns_to_t(70);
+ txp = max(ns_to_t(8), 2);
+ twtr = max(ns_to_t(8), 2);
+ trtp = max(ns_to_t(8), 2);
+ trp = max(ns_to_t(27), 2);
+ tras = ns_to_t(42);
+ trefi = ns_to_t(3900) / 32;
+ trfc = ns_to_t(210);
+ tmrw = 5;
+ tmrd = 5;
+ tckesr = 5;
+ tcwl = 3; /* CWL 8 */
+ t_rdata_en = 5;
+ tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
+ tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */
+ tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 200us */
+ tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
+ twtp = tcwl + 4 + twr + 1; /* CWL + BL/2 + tWR */
+ twr2rd = tcwl + 4 + 1 + twtr; /* WL + BL / 2 + tWTR */
+ trd2wr = tcl + 4 + 5 - tcwl + 1; /* RL + BL / 2 + 2 - WL */
+ }
+ /* Set dram timing */
+ reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0);
+ writel(reg_val, &mctl_ctl->dramtmg0);
+ reg_val = (txp << 16) | (trtp << 8) | (trc << 0);
+ writel(reg_val, &mctl_ctl->dramtmg1);
+ reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0);
+ writel(reg_val, &mctl_ctl->dramtmg2);
+ reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0);
+ writel(reg_val, &mctl_ctl->dramtmg3);
+ reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0);
+ writel(reg_val, &mctl_ctl->dramtmg4);
+ reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0);
+ writel(reg_val, &mctl_ctl->dramtmg5);
+ /* Set two rank timing and exit self-refresh timing */
+ reg_val = readl(&mctl_ctl->dramtmg8);
+ reg_val &= ~(0xff << 8);
+ reg_val &= ~(0xff << 0);
+ reg_val |= (0x33 << 8);
+ reg_val |= (0x8 << 0);
+ writel(reg_val, &mctl_ctl->dramtmg8);
+ /* Set phy interface time */
+ reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
+ | (wr_latency << 0);
+ /* PHY interface write latency and read latency configure */
+ writel(reg_val, &mctl_ctl->pitmg0);
+ /* Set phy time PTR0-2 use default */
+ writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3);
+ writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4);
+ /* Set refresh timing */
+ reg_val = (trefi << 16) | (trfc << 0);
+ writel(reg_val, &mctl_ctl->rfshtmg);
+}
+
+static void mctl_set_pir(u32 val)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ writel(val, &mctl_ctl->pir);
+ mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1);
+}
+
+static void mctl_data_train_cfg(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ if (para->rank == 2)
+ clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);
+ else
+ clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);
+}
+
+static int mctl_train_dram(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ mctl_data_train_cfg(para);
+ mctl_set_pir(0x5f3);
+
+ return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0;
+}
+
+static void set_master_priority(void)
+{
+ writel(0x00a0000d, MCTL_MASTER_CFG0(0));
+ writel(0x00500064, MCTL_MASTER_CFG1(0));
+ writel(0x07000009, MCTL_MASTER_CFG0(1));
+ writel(0x00000600, MCTL_MASTER_CFG1(1));
+ writel(0x01000009, MCTL_MASTER_CFG0(3));
+ writel(0x00000064, MCTL_MASTER_CFG1(3));
+ writel(0x08000009, MCTL_MASTER_CFG0(4));
+ writel(0x00000640, MCTL_MASTER_CFG1(4));
+ writel(0x20000308, MCTL_MASTER_CFG0(8));
+ writel(0x00001000, MCTL_MASTER_CFG1(8));
+ writel(0x02800009, MCTL_MASTER_CFG0(9));
+ writel(0x00000100, MCTL_MASTER_CFG1(9));
+ writel(0x01800009, MCTL_MASTER_CFG0(5));
+ writel(0x00000100, MCTL_MASTER_CFG1(5));
+ writel(0x01800009, MCTL_MASTER_CFG0(7));
+ writel(0x00000100, MCTL_MASTER_CFG1(7));
+ writel(0x00640009, MCTL_MASTER_CFG0(6));
+ writel(0x00000032, MCTL_MASTER_CFG1(6));
+ writel(0x0100000d, MCTL_MASTER_CFG0(2));
+ writel(0x00500080, MCTL_MASTER_CFG1(2));
+}
+
+static int mctl_channel_init(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ u32 low_data_lines_status; /* Training status of datalines 0 - 7 */
+ u32 high_data_lines_status; /* Training status of datalines 8 - 15 */
+ u32 i, rval;
+
+ auto_set_timing_para(para);
+
+ /* Set dram master access priority */
+ writel(0x000101a0, &mctl_com->bwcr);
+ /* set cpu high priority */
+ writel(0x1, &mctl_com->mapr);
+ set_master_priority();
+ udelay(250);
+
+ /* Disable dram VTC */
+ clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0 | 0x1 << 30);
+ clrsetbits_le32(&mctl_ctl->pgcr1, 0x1 << 24, 0x1 << 26);
+
+ writel(0x94be6fa3, MCTL_PROTECT);
+ udelay(100);
+ clrsetbits_le32(MX_UPD2, 0xfff << 16, 0x50 << 16);
+ writel(0x0, MCTL_PROTECT);
+ udelay(100);
+
+
+ /* Set ODT */
+ if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
+ rval = 0x0;
+ else
+ rval = 0x2;
+
+ for (i = 0 ; i < 11 ; i++) {
+ clrsetbits_le32(DATX0IOCR(i), (0x3 << 24) | (0x3 << 16),
+ rval << 24);
+ clrsetbits_le32(DATX1IOCR(i), (0x3 << 24) | (0x3 << 16),
+ rval << 24);
+ clrsetbits_le32(DATX2IOCR(i), (0x3 << 24) | (0x3 << 16),
+ rval << 24);
+ clrsetbits_le32(DATX3IOCR(i), (0x3 << 24) | (0x3 << 16),
+ rval << 24);
+ }
+
+ for (i = 0; i < 31; i++)
+ clrsetbits_le32(CAIOCR(i), 0x3 << 26 | 0x3 << 16, 0x2 << 26);
+
+ /* set PLL configuration */
+ if (CONFIG_DRAM_CLK >= 480)
+ setbits_le32(&mctl_ctl->pllgcr, 0x1 << 19);
+ else
+ setbits_le32(&mctl_ctl->pllgcr, 0x3 << 19);
+
+ /* Auto detect dram config, set 2 rank and 16bit bus-width */
+ para->cs1 = 0;
+ para->rank = 2;
+ para->bus_width = 16;
+ mctl_set_cr(para);
+
+ /* Open DQS gating */
+ clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
+ clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));
+
+ if (para->dram_type == DRAM_TYPE_LPDDR3)
+ clrsetbits_le32(&mctl_ctl->dxccr, (0x1 << 27) | (0x3<<6) ,
+ 0x1 << 31);
+ if (readl(&mctl_com->cr) & 0x1)
+ writel(0x00000303, &mctl_ctl->odtmap);
+ else
+ writel(0x00000201, &mctl_ctl->odtmap);
+
+ mctl_data_train_cfg(para);
+ /* ZQ calibration */
+ clrsetbits_le32(ZQnPR(0), 0x000000ff, CONFIG_DRAM_ZQ & 0xff);
+ clrsetbits_le32(ZQnPR(1), 0x000000ff, (CONFIG_DRAM_ZQ >> 8) & 0xff);
+ /* CA calibration */
+
+ if (para->dram_type == DRAM_TYPE_DDR3)
+ mctl_set_pir(0x0201f3 | 0x1<<10);
+ else
+ mctl_set_pir(0x020173 | 0x1<<10);
+
+ /* DQS gate training */
+ if (mctl_train_dram(para) != 0) {
+ low_data_lines_status = (readl(DXnGSR0(0)) >> 24) & 0x03;
+ high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03;
+
+ if (low_data_lines_status == 0x3)
+ return -EIO;
+
+ /* DRAM has only one rank */
+ para->rank = 1;
+ mctl_set_cr(para);
+
+ if (low_data_lines_status == high_data_lines_status)
+ goto done; /* 16 bit bus, 1 rank */
+
+ if (!(low_data_lines_status & high_data_lines_status)) {
+ /* Retry 16 bit bus-width with CS1 set */
+ para->cs1 = 1;
+ mctl_set_cr(para);
+ if (mctl_train_dram(para) == 0)
+ goto done;
+ }
+
+ /* Try 8 bit bus-width */
+ writel(0x0, DXnGCR0(1)); /* Disable high DQ */
+ para->cs1 = 0;
+ para->bus_width = 8;
+ mctl_set_cr(para);
+ if (mctl_train_dram(para) != 0)
+ return -EIO;
+ }
+done:
+ /* Check the dramc status */
+ mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
+
+ /* Close DQS gating */
+ setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);
+
+ /* set PGCR3,CKE polarity */
+ writel(0x00aa0060, &mctl_ctl->pgcr3);
+ /* Enable master access */
+ writel(0xffffffff, &mctl_com->maer);
+
+ return 0;
+}
+
+static void mctl_sys_init(struct dram_para *para)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ clrbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
+ clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
+ clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+ clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+ clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
+ udelay(1000);
+ clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31);
+
+ clock_set_pll5(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL);
+
+ clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK,
+ CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) |
+ CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD);
+ mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
+
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+ setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
+ setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
+
+ para->rank = 2;
+ para->bus_width = 16;
+ mctl_set_cr(para);
+
+ /* Set dram master access priority */
+ writel(0x0000e00f, &mctl_ctl->clken); /* normal */
+
+ udelay(250);
+}
+
+unsigned long sunxi_dram_init(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ struct dram_para para = {
+ .cs1 = 0,
+ .bank = 1,
+ .rank = 1,
+ .rows = 15,
+ .bus_width = 16,
+ .page_size = 2048,
+ };
+
+#if defined(CONFIG_MACH_SUN8I_A83T)
+#if (CONFIG_DRAM_TYPE == 3) || (CONFIG_DRAM_TYPE == 7)
+ para.dram_type = CONFIG_DRAM_TYPE;
+#else
+#error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3)
+#endif
+#endif
+ setbits_le32(SUNXI_PRCM_BASE + 0x1e0, 0x1 << 8);
+
+ writel(0, (SUNXI_PRCM_BASE + 0x1e8));
+ udelay(10);
+
+ mctl_sys_init(¶);
+
+ if (mctl_channel_init(¶) != 0)
+ return 0;
+
+ auto_detect_dram_size(¶);
+
+ /* Enable master software clk */
+ writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr);
+
+ /* Set DRAM ODT MAP */
+ if (para.rank == 2)
+ writel(0x00000303, &mctl_ctl->odtmap);
+ else
+ writel(0x00000201, &mctl_ctl->odtmap);
+
+ return para.page_size * (para.bus_width / 8) *
+ (1 << (para.bank + para.rank + para.rows));
+}
--- /dev/null
+/*
+ * sun8i H3 platform dram controller init
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ * Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <linux/kconfig.h>
+
+struct dram_para {
+ u32 read_delays;
+ u32 write_delays;
+ u16 page_size;
+ u8 bus_width;
+ u8 dual_rank;
+ u8 row_bits;
+};
+
+static inline int ns_to_t(int nanoseconds)
+{
+ const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
+
+ return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
+}
+
+static u32 bin_to_mgray(int val)
+{
+ static const u8 lookup_table[32] = {
+ 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
+ 0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09,
+ 0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d,
+ 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11,
+ };
+
+ return lookup_table[clamp(val, 0, 31)];
+}
+
+static int mgray_to_bin(u32 val)
+{
+ static const u8 lookup_table[32] = {
+ 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
+ 0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b,
+ 0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b,
+ 0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15,
+ };
+
+ return lookup_table[val & 0x1f];
+}
+
+static void mctl_phy_init(u32 val)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ writel(val | PIR_INIT, &mctl_ctl->pir);
+ mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1);
+}
+
+static void mctl_dq_delay(u32 read, u32 write)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ int i, j;
+ u32 val;
+
+ for (i = 0; i < 4; i++) {
+ val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) |
+ DATX_IOCR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2);
+
+ for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++)
+ writel(val, &mctl_ctl->datx[i].iocr[j]);
+ }
+
+ clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
+
+ for (i = 0; i < 4; i++) {
+ val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) |
+ DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf);
+
+ writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQS]);
+ writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN]);
+ }
+
+ setbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
+
+ udelay(1);
+}
+
+static void mctl_set_master_priority(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ /* enable bandwidth limit windows and set windows size 1us */
+ writel(0x00010190, &mctl_com->bwcr);
+
+ /* set cpu high priority */
+ writel(0x00000001, &mctl_com->mapr);
+
+ writel(0x0200000d, &mctl_com->mcr[0][0]);
+ writel(0x00800100, &mctl_com->mcr[0][1]);
+ writel(0x06000009, &mctl_com->mcr[1][0]);
+ writel(0x01000400, &mctl_com->mcr[1][1]);
+ writel(0x0200000d, &mctl_com->mcr[2][0]);
+ writel(0x00600100, &mctl_com->mcr[2][1]);
+ writel(0x0100000d, &mctl_com->mcr[3][0]);
+ writel(0x00200080, &mctl_com->mcr[3][1]);
+ writel(0x07000009, &mctl_com->mcr[4][0]);
+ writel(0x01000640, &mctl_com->mcr[4][1]);
+ writel(0x0100000d, &mctl_com->mcr[5][0]);
+ writel(0x00200080, &mctl_com->mcr[5][1]);
+ writel(0x01000009, &mctl_com->mcr[6][0]);
+ writel(0x00400080, &mctl_com->mcr[6][1]);
+ writel(0x0100000d, &mctl_com->mcr[7][0]);
+ writel(0x00400080, &mctl_com->mcr[7][1]);
+ writel(0x0100000d, &mctl_com->mcr[8][0]);
+ writel(0x00400080, &mctl_com->mcr[8][1]);
+ writel(0x04000009, &mctl_com->mcr[9][0]);
+ writel(0x00400100, &mctl_com->mcr[9][1]);
+ writel(0x2000030d, &mctl_com->mcr[10][0]);
+ writel(0x04001800, &mctl_com->mcr[10][1]);
+ writel(0x04000009, &mctl_com->mcr[11][0]);
+ writel(0x00400120, &mctl_com->mcr[11][1]);
+}
+
+static void mctl_set_timing_params(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ u8 tccd = 2;
+ u8 tfaw = ns_to_t(50);
+ u8 trrd = max(ns_to_t(10), 4);
+ u8 trcd = ns_to_t(15);
+ u8 trc = ns_to_t(53);
+ u8 txp = max(ns_to_t(8), 3);
+ u8 twtr = max(ns_to_t(8), 4);
+ u8 trtp = max(ns_to_t(8), 4);
+ u8 twr = max(ns_to_t(15), 3);
+ u8 trp = ns_to_t(15);
+ u8 tras = ns_to_t(38);
+ u16 trefi = ns_to_t(7800) / 32;
+ u16 trfc = ns_to_t(350);
+
+ u8 tmrw = 0;
+ u8 tmrd = 4;
+ u8 tmod = 12;
+ u8 tcke = 3;
+ u8 tcksrx = 5;
+ u8 tcksre = 5;
+ u8 tckesr = 4;
+ u8 trasmax = 24;
+
+ u8 tcl = 6; /* CL 12 */
+ u8 tcwl = 4; /* CWL 8 */
+ u8 t_rdata_en = 4;
+ u8 wr_latency = 2;
+
+ u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
+ u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
+ u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
+ u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
+
+ u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
+ u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
+ u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
+
+ /* set mode register */
+ writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */
+ writel(0x40, &mctl_ctl->mr[1]);
+ writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
+ writel(0x0, &mctl_ctl->mr[3]);
+
+ /* set DRAM timing */
+ writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
+ DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
+ &mctl_ctl->dramtmg[0]);
+ writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
+ &mctl_ctl->dramtmg[1]);
+ writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
+ DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
+ &mctl_ctl->dramtmg[2]);
+ writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
+ &mctl_ctl->dramtmg[3]);
+ writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
+ DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
+ writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
+ DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
+ &mctl_ctl->dramtmg[5]);
+
+ /* set two rank timing */
+ clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
+ (0x66 << 8) | (0x10 << 0));
+
+ /* set PHY interface timing, write latency and read latency configure */
+ writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
+ (wr_latency << 0), &mctl_ctl->pitmg[0]);
+
+ /* set PHY timing, PTR0-2 use default */
+ writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
+ writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
+
+ /* set refresh timing */
+ writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
+}
+
+static void mctl_zq_calibration(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ int i;
+ u16 zq_val[6];
+ u8 val;
+
+ writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
+
+ for (i = 0; i < 6; i++) {
+ u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
+
+ writel((zq << 20) | (zq << 16) | (zq << 12) |
+ (zq << 8) | (zq << 4) | (zq << 0),
+ &mctl_ctl->zqcr);
+
+ writel(PIR_CLRSR, &mctl_ctl->pir);
+ mctl_phy_init(PIR_ZCAL);
+
+ zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
+ writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
+
+ writel(PIR_CLRSR, &mctl_ctl->pir);
+ mctl_phy_init(PIR_ZCAL);
+
+ val = readl(&mctl_ctl->zqdr[0]) >> 24;
+ zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
+ }
+
+ writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
+ writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
+ writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
+}
+
+static void mctl_set_cr(struct dram_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED |
+ MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) |
+ (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
+ MCTL_CR_PAGE_SIZE(para->page_size) |
+ MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
+}
+
+static void mctl_sys_init(struct dram_para *para)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
+ clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
+ clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+ clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+ clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
+ udelay(10);
+
+ clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
+ udelay(1000);
+
+ clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
+ clrsetbits_le32(&ccm->dram_clk_cfg,
+ CCM_DRAMCLK_CFG_DIV_MASK | CCM_DRAMCLK_CFG_SRC_MASK,
+ CCM_DRAMCLK_CFG_DIV(1) | CCM_DRAMCLK_CFG_SRC_PLL5 |
+ CCM_DRAMCLK_CFG_UPD);
+ mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
+
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+ setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
+ setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
+
+ setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
+ udelay(10);
+
+ writel(0xc00e, &mctl_ctl->clken);
+ udelay(500);
+}
+
+static int mctl_channel_init(struct dram_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ unsigned int i;
+
+ mctl_set_cr(para);
+ mctl_set_timing_params(para);
+ mctl_set_master_priority();
+
+ /* setting VTC, default disable all VT */
+ clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f);
+ clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
+
+ /* increase DFI_PHY_UPD clock */
+ writel(PROTECT_MAGIC, &mctl_com->protect);
+ udelay(100);
+ clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16);
+ writel(0x0, &mctl_com->protect);
+ udelay(100);
+
+ /* set dramc odt */
+ for (i = 0; i < 4; i++)
+ clrsetbits_le32(&mctl_ctl->datx[i].gcr, (0x3 << 4) |
+ (0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
+ (0x3 << 14),
+ IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2);
+
+ /* AC PDR should always ON */
+ setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);
+
+ /* set DQS auto gating PD mode */
+ setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);
+
+ /* dx ddr_clk & hdr_clk dynamic mode */
+ clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
+
+ /* dphy & aphy phase select 270 degree */
+ clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
+ (0x1 << 10) | (0x2 << 8));
+
+ /* set half DQ */
+ if (para->bus_width != 32) {
+ writel(0x0, &mctl_ctl->datx[2].gcr);
+ writel(0x0, &mctl_ctl->datx[3].gcr);
+ }
+
+ /* data training configuration */
+ clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24,
+ (para->dual_rank ? 0x3 : 0x1) << 24);
+
+
+ if (para->read_delays || para->write_delays) {
+ mctl_dq_delay(para->read_delays, para->write_delays);
+ udelay(50);
+ }
+
+ mctl_zq_calibration(para);
+
+ mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | PIR_DRAMRST |
+ PIR_DRAMINIT | PIR_QSGATE);
+
+ /* detect ranks and bus width */
+ if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) {
+ /* only one rank */
+ if (((readl(&mctl_ctl->datx[0].gsr[0]) >> 24) & 0x2) ||
+ ((readl(&mctl_ctl->datx[1].gsr[0]) >> 24) & 0x2)) {
+ clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
+ para->dual_rank = 0;
+ }
+
+ /* only half DQ width */
+ if (((readl(&mctl_ctl->datx[2].gsr[0]) >> 24) & 0x1) ||
+ ((readl(&mctl_ctl->datx[3].gsr[0]) >> 24) & 0x1)) {
+ writel(0x0, &mctl_ctl->datx[2].gcr);
+ writel(0x0, &mctl_ctl->datx[3].gcr);
+ para->bus_width = 16;
+ }
+
+ mctl_set_cr(para);
+ udelay(20);
+
+ /* re-train */
+ mctl_phy_init(PIR_QSGATE);
+ if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20))
+ return 1;
+ }
+
+ /* check the dramc status */
+ mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
+
+ /* liuke added for refresh debug */
+ setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
+ udelay(10);
+ clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
+ udelay(10);
+
+ /* set PGCR3, CKE polarity */
+ writel(0x00aa0060, &mctl_ctl->pgcr[3]);
+
+ /* power down zq calibration module for power save */
+ setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN);
+
+ /* enable master access */
+ writel(0xffffffff, &mctl_com->maer);
+
+ return 0;
+}
+
+static void mctl_auto_detect_dram_size(struct dram_para *para)
+{
+ /* detect row address bits */
+ para->page_size = 512;
+ para->row_bits = 16;
+ mctl_set_cr(para);
+
+ for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
+ if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size))
+ break;
+
+ /* detect page size */
+ para->page_size = 8192;
+ mctl_set_cr(para);
+
+ for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2)
+ if (mctl_mem_matches(para->page_size))
+ break;
+}
+
+unsigned long sunxi_dram_init(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ struct dram_para para = {
+ .read_delays = 0x00007979, /* dram_tpr12 */
+ .write_delays = 0x6aaa0000, /* dram_tpr11 */
+ .dual_rank = 0,
+ .bus_width = 32,
+ .row_bits = 15,
+ .page_size = 4096,
+ };
+
+ mctl_sys_init(¶);
+ if (mctl_channel_init(¶))
+ return 0;
+
+ if (para.dual_rank)
+ writel(0x00000303, &mctl_ctl->odtmap);
+ else
+ writel(0x00000201, &mctl_ctl->odtmap);
+ udelay(1);
+
+ /* odt delay */
+ writel(0x0c000400, &mctl_ctl->odtcfg);
+
+ /* clear credit value */
+ setbits_le32(&mctl_com->cccr, 1 << 31);
+ udelay(10);
+
+ mctl_auto_detect_dram_size(¶);
+ mctl_set_cr(¶);
+
+ return (1 << (para.row_bits + 3)) * para.page_size *
+ (para.dual_rank ? 2 : 1);
+}
--- /dev/null
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/p2wi.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+void p2wi_init(void)
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
+
+ /* Enable p2wi and PIO clk, and de-assert their resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
+
+ /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
+ writel(P2WI_CTRL_RESET, &p2wi->ctrl);
+ sdelay(0x100);
+ writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
+ &p2wi->cc);
+}
+
+int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
+ unsigned long tmo = timer_get_us() + 1000000;
+
+ writel(P2WI_PM_DEV_ADDR(slave_addr) |
+ P2WI_PM_CTRL_ADDR(ctrl_reg) |
+ P2WI_PM_INIT_DATA(init_data) |
+ P2WI_PM_INIT_SEND,
+ &p2wi->pm);
+
+ while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) {
+ if (timer_get_us() > tmo)
+ return -ETIME;
+ }
+
+ return 0;
+}
+
+static int p2wi_await_trans(void)
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
+ unsigned long tmo = timer_get_us() + 1000000;
+ int ret;
+ u8 reg;
+
+ while (1) {
+ reg = readl(&p2wi->status);
+ if (reg & P2WI_STAT_TRANS_ERR) {
+ ret = -EIO;
+ break;
+ }
+ if (reg & P2WI_STAT_TRANS_DONE) {
+ ret = 0;
+ break;
+ }
+ if (timer_get_us() > tmo) {
+ ret = -ETIME;
+ break;
+ }
+ }
+ writel(reg, &p2wi->status); /* Clear status bits */
+ return ret;
+}
+
+int p2wi_read(const u8 addr, u8 *data)
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
+ int ret;
+
+ writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
+ writel(P2WI_DATA_NUM_BYTES(1) |
+ P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
+ writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
+ writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
+
+ ret = p2wi_await_trans();
+
+ *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
+ return ret;
+}
+
+int p2wi_write(const u8 addr, u8 data)
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
+
+ writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
+ writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
+ writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
+ writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
+ writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
+
+ return p2wi_await_trans();
+}
--- /dev/null
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+
+void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
+{
+ u32 index = GPIO_CFG_INDEX(bank_offset);
+ u32 offset = GPIO_CFG_OFFSET(bank_offset);
+
+ clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
+}
+
+void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
+{
+ u32 bank = GPIO_BANK(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ sunxi_gpio_set_cfgbank(pio, pin, val);
+}
+
+int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
+{
+ u32 index = GPIO_CFG_INDEX(bank_offset);
+ u32 offset = GPIO_CFG_OFFSET(bank_offset);
+ u32 cfg;
+
+ cfg = readl(&pio->cfg[0] + index);
+ cfg >>= offset;
+
+ return cfg & 0xf;
+}
+
+int sunxi_gpio_get_cfgpin(u32 pin)
+{
+ u32 bank = GPIO_BANK(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ return sunxi_gpio_get_cfgbank(pio, pin);
+}
+
+int sunxi_gpio_set_drv(u32 pin, u32 val)
+{
+ u32 bank = GPIO_BANK(pin);
+ u32 index = GPIO_DRV_INDEX(pin);
+ u32 offset = GPIO_DRV_OFFSET(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset);
+
+ return 0;
+}
+
+int sunxi_gpio_set_pull(u32 pin, u32 val)
+{
+ u32 bank = GPIO_BANK(pin);
+ u32 index = GPIO_PULL_INDEX(pin);
+ u32 offset = GPIO_PULL_OFFSET(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset);
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Sunxi PMIC bus access helpers
+ *
+ * The axp152 & axp209 use an i2c bus, the axp221 uses the p2wi bus and the
+ * axp223 uses the rsb bus, these functions abstract this.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/p2wi.h>
+#include <asm/arch/rsb.h>
+#include <i2c.h>
+#include <asm/arch/pmic_bus.h>
+
+#define AXP152_I2C_ADDR 0x30
+
+#define AXP209_I2C_ADDR 0x34
+
+#define AXP221_CHIP_ADDR 0x68
+#define AXP221_CTRL_ADDR 0x3e
+#define AXP221_INIT_DATA 0x3e
+
+/* AXP818 device and runtime addresses are same as AXP223 */
+#define AXP223_DEVICE_ADDR 0x3a3
+#define AXP223_RUNTIME_ADDR 0x2d
+
+int pmic_bus_init(void)
+{
+ /* This cannot be 0 because it is used in SPL before BSS is ready */
+ static int needs_init = 1;
+ __maybe_unused int ret;
+
+ if (!needs_init)
+ return 0;
+
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+# ifdef CONFIG_MACH_SUN6I
+ p2wi_init();
+ ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
+ AXP221_INIT_DATA);
+# else
+ ret = rsb_init();
+ if (ret)
+ return ret;
+
+ ret = rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR);
+# endif
+ if (ret)
+ return ret;
+#endif
+
+ needs_init = 0;
+ return 0;
+}
+
+int pmic_bus_read(u8 reg, u8 *data)
+{
+#ifdef CONFIG_AXP152_POWER
+ return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1);
+#elif defined CONFIG_AXP209_POWER
+ return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+# ifdef CONFIG_MACH_SUN6I
+ return p2wi_read(reg, data);
+# else
+ return rsb_read(AXP223_RUNTIME_ADDR, reg, data);
+# endif
+#endif
+}
+
+int pmic_bus_write(u8 reg, u8 data)
+{
+#ifdef CONFIG_AXP152_POWER
+ return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1);
+#elif defined CONFIG_AXP209_POWER
+ return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+# ifdef CONFIG_MACH_SUN6I
+ return p2wi_write(reg, data);
+# else
+ return rsb_write(AXP223_RUNTIME_ADDR, reg, data);
+# endif
+#endif
+}
+
+int pmic_bus_setbits(u8 reg, u8 bits)
+{
+ int ret;
+ u8 val;
+
+ ret = pmic_bus_read(reg, &val);
+ if (ret)
+ return ret;
+
+ val |= bits;
+ return pmic_bus_write(reg, val);
+}
+
+int pmic_bus_clrbits(u8 reg, u8 bits)
+{
+ int ret;
+ u8 val;
+
+ ret = pmic_bus_read(reg, &val);
+ if (ret)
+ return ret;
+
+ val &= ~bits;
+ return pmic_bus_write(reg, val);
+}
--- /dev/null
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+/* APB0 clock gate and reset bit offsets are the same. */
+void prcm_apb0_enable(u32 flags)
+{
+ struct sunxi_prcm_reg *prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+ /* open the clock for module */
+ setbits_le32(&prcm->apb0_gate, flags);
+
+ /* deassert reset for module */
+ setbits_le32(&prcm->apb0_reset, flags);
+}
+
+void prcm_apb0_disable(u32 flags)
+{
+ struct sunxi_prcm_reg *prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+ /* assert reset for module */
+ clrbits_le32(&prcm->apb0_reset, flags);
+
+ /* close the clock for module */
+ clrbits_le32(&prcm->apb0_gate, flags);
+}
--- /dev/null
+/*
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Based on allwinner u-boot sources rsb code which is:
+ * (C) Copyright 2007-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * lixiang <lixiang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/rsb.h>
+
+static int rsb_set_device_mode(void);
+
+static void rsb_cfg_io(void)
+{
+#ifdef CONFIG_MACH_SUN8I
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
+ sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
+ sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
+ sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
+ sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
+#elif defined CONFIG_MACH_SUN9I
+ sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
+ sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
+ sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
+ sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
+ sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
+ sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
+#else
+#error unsupported MACH_SUNXI
+#endif
+}
+
+static void rsb_set_clk(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+ u32 div = 0;
+ u32 cd_odly = 0;
+
+ /* Source is Hosc24M, set RSB clk to 3Mhz */
+ div = 24000000 / 3000000 / 2 - 1;
+ cd_odly = div >> 1;
+ if (!cd_odly)
+ cd_odly = 1;
+
+ writel((cd_odly << 8) | div, &rsb->ccr);
+}
+
+int rsb_init(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ /* Enable RSB and PIO clk, and de-assert their resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
+
+ /* Setup external pins */
+ rsb_cfg_io();
+
+ writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
+ rsb_set_clk();
+
+ return rsb_set_device_mode();
+}
+
+static int rsb_await_trans(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+ unsigned long tmo = timer_get_us() + 1000000;
+ u32 stat;
+ int ret;
+
+ while (1) {
+ stat = readl(&rsb->stat);
+ if (stat & RSB_STAT_LBSY_INT) {
+ ret = -EBUSY;
+ break;
+ }
+ if (stat & RSB_STAT_TERR_INT) {
+ ret = -EIO;
+ break;
+ }
+ if (stat & RSB_STAT_TOVER_INT) {
+ ret = 0;
+ break;
+ }
+ if (timer_get_us() > tmo) {
+ ret = -ETIME;
+ break;
+ }
+ }
+ writel(stat, &rsb->stat); /* Clear status bits */
+
+ return ret;
+}
+
+static int rsb_set_device_mode(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+ unsigned long tmo = timer_get_us() + 1000000;
+
+ writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
+ &rsb->dmcr);
+
+ while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
+ if (timer_get_us() > tmo)
+ return -ETIME;
+ }
+
+ return rsb_await_trans();
+}
+
+static int rsb_do_trans(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS);
+ return rsb_await_trans();
+}
+
+int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) |
+ RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr);
+ writel(RSB_CMD_SET_RTSADDR, &rsb->cmd);
+
+ return rsb_do_trans();
+}
+
+int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
+ writel(reg_addr, &rsb->addr);
+ writel(data, &rsb->data);
+ writel(RSB_CMD_BYTE_WRITE, &rsb->cmd);
+
+ return rsb_do_trans();
+}
+
+int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+ int ret;
+
+ writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
+ writel(reg_addr, &rsb->addr);
+ writel(RSB_CMD_BYTE_READ, &rsb->cmd);
+
+ ret = rsb_do_trans();
+ if (ret)
+ return ret;
+
+ *data = readl(&rsb->data) & 0xff;
+
+ return 0;
+}
--- /dev/null
+/*
+ * Sunxi usb-phy code
+ *
+ * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
+ * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/usb_phy.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <errno.h>
+
+#define SUNXI_USB_PMU_IRQ_ENABLE 0x800
+#ifdef CONFIG_MACH_SUN8I_A33
+#define SUNXI_USB_CSR 0x410
+#else
+#define SUNXI_USB_CSR 0x404
+#endif
+#define SUNXI_USB_PASSBY_EN 1
+
+#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
+#define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9)
+#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8)
+#define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0)
+
+#define REG_PHY_UNK_H3 0x420
+#define REG_PMU_UNK_H3 0x810
+
+/* A83T specific control bits for PHY0 */
+#define SUNXI_PHY_CTL_VBUSVLDEXT BIT(5)
+#define SUNXI_PHY_CTL_SIDDQ BIT(3)
+
+/* A83T HSIC specific bits */
+#define SUNXI_EHCI_HS_FORCE BIT(20)
+#define SUNXI_EHCI_CONNECT_DET BIT(17)
+#define SUNXI_EHCI_CONNECT_INT BIT(16)
+#define SUNXI_EHCI_HSIC BIT(1)
+
+static struct sunxi_usb_phy {
+ int usb_rst_mask;
+ int gpio_vbus;
+ int gpio_vbus_det;
+ int gpio_id_det;
+ int id;
+ int init_count;
+ int power_on_count;
+ ulong base;
+} sunxi_usb_phy[] = {
+ {
+ .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
+ .id = 0,
+ .base = SUNXI_USB0_BASE,
+ },
+ {
+ .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
+ .id = 1,
+ .base = SUNXI_USB1_BASE,
+ },
+#if CONFIG_SUNXI_USB_PHYS >= 3
+ {
+#ifdef CONFIG_MACH_SUN8I_A83T
+ .usb_rst_mask = CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |
+ CCM_USB_CTRL_12M_CLK,
+#else
+ .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
+#endif
+ .id = 2,
+ .base = SUNXI_USB2_BASE,
+ },
+#endif
+#if CONFIG_SUNXI_USB_PHYS >= 4
+ {
+ .usb_rst_mask = CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK,
+ .id = 3,
+ .base = SUNXI_USB3_BASE,
+ }
+#endif
+};
+
+static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
+
+static int get_vbus_gpio(int index)
+{
+ switch (index) {
+ case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
+ case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
+ case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
+ case 3: return sunxi_name_to_gpio(CONFIG_USB3_VBUS_PIN);
+ }
+ return -EINVAL;
+}
+
+static int get_vbus_detect_gpio(int index)
+{
+ switch (index) {
+ case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET);
+ }
+ return -EINVAL;
+}
+
+static int get_id_detect_gpio(int index)
+{
+ switch (index) {
+ case 0: return sunxi_name_to_gpio(CONFIG_USB0_ID_DET);
+ }
+ return -EINVAL;
+}
+
+__maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr,
+ int data, int len)
+{
+ int j = 0, usbc_bit = 0;
+ void *dest = (void *)SUNXI_USB0_BASE + SUNXI_USB_CSR;
+
+#ifdef CONFIG_MACH_SUN8I_A33
+ /* CSR needs to be explicitly initialized to 0 on A33 */
+ writel(0, dest);
+#endif
+
+ usbc_bit = 1 << (phy->id * 2);
+ for (j = 0; j < len; j++) {
+ /* set the bit address to be written */
+ clrbits_le32(dest, 0xff << 8);
+ setbits_le32(dest, (addr + j) << 8);
+
+ clrbits_le32(dest, usbc_bit);
+ /* set data bit */
+ if (data & 0x1)
+ setbits_le32(dest, 1 << 7);
+ else
+ clrbits_le32(dest, 1 << 7);
+
+ setbits_le32(dest, usbc_bit);
+
+ clrbits_le32(dest, usbc_bit);
+
+ data >>= 1;
+ }
+}
+
+#if defined CONFIG_MACH_SUN8I_H3
+static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
+{
+ if (phy->id == 0)
+ clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
+
+ clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02);
+}
+#elif defined CONFIG_MACH_SUN8I_A83T
+static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
+{
+}
+#else
+static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
+{
+ /* The following comments are machine
+ * translated from Chinese, you have been warned!
+ */
+
+ /* Regulation 45 ohms */
+ if (phy->id == 0)
+ usb_phy_write(phy, 0x0c, 0x01, 1);
+
+ /* adjust PHY's magnitude and rate */
+ usb_phy_write(phy, 0x20, 0x14, 5);
+
+ /* threshold adjustment disconnect */
+#if defined CONFIG_MACH_SUN5I || defined CONFIG_MACH_SUN7I
+ usb_phy_write(phy, 0x2a, 2, 2);
+#else
+ usb_phy_write(phy, 0x2a, 3, 2);
+#endif
+
+ return;
+}
+#endif
+
+static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable)
+{
+ unsigned long bits = 0;
+ void *addr;
+
+ addr = (void *)phy->base + SUNXI_USB_PMU_IRQ_ENABLE;
+
+ bits = SUNXI_EHCI_AHB_ICHR8_EN |
+ SUNXI_EHCI_AHB_INCR4_BURST_EN |
+ SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
+ SUNXI_EHCI_ULPI_BYPASS_EN;
+
+#ifdef CONFIG_MACH_SUN8I_A83T
+ if (phy->id == 2)
+ bits |= SUNXI_EHCI_HS_FORCE |
+ SUNXI_EHCI_CONNECT_INT |
+ SUNXI_EHCI_HSIC;
+#endif
+
+ if (enable)
+ setbits_le32(addr, bits);
+ else
+ clrbits_le32(addr, bits);
+
+ return;
+}
+
+void sunxi_usb_phy_enable_squelch_detect(int index, int enable)
+{
+#ifndef CONFIG_MACH_SUN8I_A83T
+ struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
+
+ usb_phy_write(phy, 0x3c, enable ? 0 : 2, 2);
+#endif
+}
+
+void sunxi_usb_phy_init(int index)
+{
+ struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ phy->init_count++;
+ if (phy->init_count != 1)
+ return;
+
+ setbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
+
+ sunxi_usb_phy_config(phy);
+
+ if (phy->id != 0)
+ sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN);
+
+#ifdef CONFIG_MACH_SUN8I_A83T
+ if (phy->id == 0) {
+ setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
+ SUNXI_PHY_CTL_VBUSVLDEXT);
+ clrbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
+ SUNXI_PHY_CTL_SIDDQ);
+ }
+#endif
+}
+
+void sunxi_usb_phy_exit(int index)
+{
+ struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ phy->init_count--;
+ if (phy->init_count != 0)
+ return;
+
+ if (phy->id != 0)
+ sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN);
+
+#ifdef CONFIG_MACH_SUN8I_A83T
+ if (phy->id == 0) {
+ setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
+ SUNXI_PHY_CTL_SIDDQ);
+ }
+#endif
+
+ clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
+}
+
+void sunxi_usb_phy_power_on(int index)
+{
+ struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
+
+ if (initial_usb_scan_delay) {
+ mdelay(initial_usb_scan_delay);
+ initial_usb_scan_delay = 0;
+ }
+
+ phy->power_on_count++;
+ if (phy->power_on_count != 1)
+ return;
+
+ if (phy->gpio_vbus >= 0)
+ gpio_set_value(phy->gpio_vbus, 1);
+}
+
+void sunxi_usb_phy_power_off(int index)
+{
+ struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
+
+ phy->power_on_count--;
+ if (phy->power_on_count != 0)
+ return;
+
+ if (phy->gpio_vbus >= 0)
+ gpio_set_value(phy->gpio_vbus, 0);
+}
+
+int sunxi_usb_phy_power_is_on(int index)
+{
+ struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
+
+ return phy->power_on_count > 0;
+}
+
+int sunxi_usb_phy_vbus_detect(int index)
+{
+ struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
+ int err, retries = 3;
+
+ if (phy->gpio_vbus_det < 0)
+ return phy->gpio_vbus_det;
+
+ err = gpio_get_value(phy->gpio_vbus_det);
+ /*
+ * Vbus may have been provided by the board and just been turned of
+ * some milliseconds ago on reset, what we're measuring then is a
+ * residual charge on Vbus, sleep a bit and try again.
+ */
+ while (err > 0 && retries--) {
+ mdelay(100);
+ err = gpio_get_value(phy->gpio_vbus_det);
+ }
+
+ return err;
+}
+
+int sunxi_usb_phy_id_detect(int index)
+{
+ struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
+
+ if (phy->gpio_id_det < 0)
+ return phy->gpio_id_det;
+
+ return gpio_get_value(phy->gpio_id_det);
+}
+
+int sunxi_usb_phy_probe(void)
+{
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_usb_phy *phy;
+ int i, ret = 0;
+
+ for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
+ phy = &sunxi_usb_phy[i];
+
+ phy->gpio_vbus = get_vbus_gpio(i);
+ if (phy->gpio_vbus >= 0) {
+ ret = gpio_request(phy->gpio_vbus, "usb_vbus");
+ if (ret)
+ return ret;
+ ret = gpio_direction_output(phy->gpio_vbus, 0);
+ if (ret)
+ return ret;
+ }
+
+ phy->gpio_vbus_det = get_vbus_detect_gpio(i);
+ if (phy->gpio_vbus_det >= 0) {
+ ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
+ if (ret)
+ return ret;
+ ret = gpio_direction_input(phy->gpio_vbus_det);
+ if (ret)
+ return ret;
+ }
+
+ phy->gpio_id_det = get_id_detect_gpio(i);
+ if (phy->gpio_id_det >= 0) {
+ ret = gpio_request(phy->gpio_id_det, "usb_id_det");
+ if (ret)
+ return ret;
+ ret = gpio_direction_input(phy->gpio_id_det);
+ if (ret)
+ return ret;
+ sunxi_gpio_set_pull(phy->gpio_id_det,
+ SUNXI_GPIO_PULL_UP);
+ }
+ }
+
+ setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
+
+ return 0;
+}
+
+int sunxi_usb_phy_remove(void)
+{
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_usb_phy *phy;
+ int i;
+
+ clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
+
+ for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
+ phy = &sunxi_usb_phy[i];
+
+ if (phy->gpio_vbus >= 0)
+ gpio_free(phy->gpio_vbus);
+
+ if (phy->gpio_vbus_det >= 0)
+ gpio_free(phy->gpio_vbus_det);
+
+ if (phy->gpio_id_det >= 0)
+ gpio_free(phy->gpio_id_det);
+ }
+
+ return 0;
+}
#define PLLE_MISC_IDDQ_SWCTL (1 << 14)
#define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13)
#define PLLE_MISC_LOCK (1 << 11)
+#define PLLE_PTS (1 << 8)
#define PLLE_MISC_KCP(x) (((x) & 0x3) << 6)
#define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
#define PLLE_MISC_KVCO (1 << 0)
writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+ value |= PLLE_PTS;
value &= ~PLLE_MISC_KCP(3);
value &= ~PLLE_MISC_VREG_CTRL(3);
value &= ~PLLE_MISC_KVCO;
choice
prompt "UniPhier SoC select"
- default ARCH_UNIPHIER_PH1_PRO4
+ default ARCH_UNIPHIER_PRO4
-config ARCH_UNIPHIER_PH1_SLD3
+config ARCH_UNIPHIER_SLD3
bool "UniPhier PH1-sLD3 SoC"
select CPU_V7
bool "UniPhier PH1-LD4/PH1-sLD8 SoC"
select CPU_V7
-config ARCH_UNIPHIER_PH1_PRO4
+config ARCH_UNIPHIER_PRO4
bool "UniPhier PH1-Pro4 SoC"
select CPU_V7
endchoice
-config ARCH_UNIPHIER_PH1_LD4
+config ARCH_UNIPHIER_LD4
bool "Enable UniPhier PH1-LD4 SoC support"
depends on ARCH_UNIPHIER_LD4_SLD8
default y
-config ARCH_UNIPHIER_PH1_SLD8
+config ARCH_UNIPHIER_SLD8
bool "Enable UniPhier PH1-sLD8 SoC support"
depends on ARCH_UNIPHIER_LD4_SLD8
default y
-config ARCH_UNIPHIER_PH1_PRO5
+config ARCH_UNIPHIER_PRO5
bool "Enable UniPhier PH1-Pro5 SoC support"
depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
default y
-config ARCH_UNIPHIER_PROXSTREAM2
+config ARCH_UNIPHIER_PXS2
bool "Enable UniPhier ProXstream2 SoC support"
depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
default y
-config ARCH_UNIPHIER_PH1_LD6B
+config ARCH_UNIPHIER_LD6B
bool "Enable UniPhier PH1-LD6b SoC support"
depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
default y
config CMD_DDRPHY_DUMP
bool "Enable dump command of DDR PHY parameters"
- depends on ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_PRO4 || \
- ARCH_UNIPHIER_PH1_SLD8
+ depends on ARCH_UNIPHIER_LD4 || ARCH_UNIPHIER_PRO4 || ARCH_UNIPHIER_SLD8
+ default y
help
The command "ddrphy" shows the resulting parameters of DDR PHY
training; it is useful for the evaluation of DDR PHY training.
config CMD_DDRMPHY_DUMP
bool "Enable dump command of DDR Multi PHY parameters"
- depends on ARCH_UNIPHIER_PROXSTREAM2 || ARCH_UNIPHIER_PH1_LD6B
+ depends on ARCH_UNIPHIER_PXS2 || ARCH_UNIPHIER_LD6B
+ default y
help
The command "ddrmphy" shows the resulting parameters of DDR Multi PHY
training; it is useful for the evaluation of DDR Multi PHY training.
obj-y += dram/
obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
+obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/
obj-$(CONFIG_CPU_V7) += arm32/
and r1, r1, #SG_REVISION_TYPE_MASK
mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
-#define PH1_SLD3_UART_CLK 36864000
+#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
+#define UNIPHIER_SLD3_UART_CLK 36864000
cmp r1, #0x25
- bne ph1_sld3_end
+ bne sld3_end
sg_set_pinsel 64, 1, 4, 4, r0, r1 @ TXD0 -> TXD0
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
- ldr r3, =DIV_ROUND(PH1_SLD3_UART_CLK, 16 * BAUDRATE)
+ ldr r3, =DIV_ROUND(UNIPHIER_SLD3_UART_CLK, 16 * BAUDRATE)
b init_uart
-ph1_sld3_end:
+sld3_end:
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
-#define PH1_LD4_UART_CLK 36864000
+#if defined(CONFIG_ARCH_UNIPHIER_LD4)
+#define UNIPHIER_LD4_UART_CLK 36864000
cmp r1, #0x26
- bne ph1_ld4_end
+ bne ld4_end
ldr r0, =SG_IECTRL
ldr r1, [r0]
sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0
- ldr r3, =DIV_ROUND(PH1_LD4_UART_CLK, 16 * BAUDRATE)
+ ldr r3, =DIV_ROUND(UNIPHIER_LD4_UART_CLK, 16 * BAUDRATE)
b init_uart
-ph1_ld4_end:
+ld4_end:
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
-#define PH1_PRO4_UART_CLK 73728000
+#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
+#define UNIPHIER_PRO4_UART_CLK 73728000
cmp r1, #0x28
- bne ph1_pro4_end
+ bne pro4_end
sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
- ldr r3, =DIV_ROUND(PH1_PRO4_UART_CLK, 16 * BAUDRATE)
+ ldr r3, =DIV_ROUND(UNIPHIER_PRO4_UART_CLK, 16 * BAUDRATE)
b init_uart
-ph1_pro4_end:
+pro4_end:
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
-#define PH1_SLD8_UART_CLK 80000000
+#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
+#define UNIPHIER_SLD8_UART_CLK 80000000
cmp r1, #0x29
- bne ph1_sld8_end
+ bne sld8_end
ldr r0, =SG_IECTRL
ldr r1, [r0]
sg_set_pinsel 70, 3, 8, 4, r0, r1 @ HSDOUT0 -> TXD0
- ldr r3, =DIV_ROUND(PH1_SLD8_UART_CLK, 16 * BAUDRATE)
+ ldr r3, =DIV_ROUND(UNIPHIER_SLD8_UART_CLK, 16 * BAUDRATE)
b init_uart
-ph1_sld8_end:
+sld8_end:
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
-#define PH1_PRO5_UART_CLK 73728000
+#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
+#define UNIPHIER_PRO5_UART_CLK 73728000
cmp r1, #0x2A
- bne ph1_pro5_end
+ bne pro5_end
sg_set_pinsel 47, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
sg_set_pinsel 49, 0, 4, 8, r0, r1 @ TXD1 -> TXD1
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
- ldr r3, =DIV_ROUND(PH1_PRO5_UART_CLK, 16 * BAUDRATE)
+ ldr r3, =DIV_ROUND(UNIPHIER_PRO5_UART_CLK, 16 * BAUDRATE)
b init_uart
-ph1_pro5_end:
+pro5_end:
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
-#define PROXSTREAM2_UART_CLK 88900000
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
+#define UNIPHIER_PXS2_UART_CLK 88900000
cmp r1, #0x2E
- bne proxstream2_end
+ bne pxs2_end
ldr r0, =SG_IECTRL
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
- ldr r3, =DIV_ROUND(PROXSTREAM2_UART_CLK, 16 * BAUDRATE)
+ ldr r3, =DIV_ROUND(UNIPHIER_PXS2_UART_CLK, 16 * BAUDRATE)
b init_uart
-proxstream2_end:
+pxs2_end:
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
-#define PH1_LD6B_UART_CLK 88900000
+#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
+#define UNIPHIER_LD6B_UART_CLK 88900000
cmp r1, #0x2F
- bne ph1_ld6b_end
+ bne ld6b_end
ldr r0, =SG_IECTRL
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
- ldr r3, =DIV_ROUND(PH1_LD6B_UART_CLK, 16 * BAUDRATE)
+ ldr r3, =DIV_ROUND(UNIPHIER_LD6B_UART_CLK, 16 * BAUDRATE)
b init_uart
-ph1_ld6b_end:
+ld6b_end:
#endif
mov pc, lr
* to do next is to create a page table and switch over to it.
*/
bl create_page_table
- bl v7_flush_dcache_all
+ bl __v7_flush_dcache_all
/* Disable MMU and Dcache before switching Page Table */
mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
str r0, [r12, #4] @ mark the second section as Normal
mov pc, lr
ENDPROC(create_page_table)
-
-/* We don't use Thumb instructions for now */
-#define ARM(x...) x
-#define THUMB(x...)
-
-/*
- * v7_flush_dcache_all()
- *
- * Flush the whole D-cache.
- *
- * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
- *
- * - mm - mm_struct describing address space
- *
- * Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
- */
-ENTRY(v7_flush_dcache_all)
- dmb @ ensure ordering with previous memory accesses
- mrc p15, 1, r0, c0, c0, 1 @ read clidr
- mov r3, r0, lsr #23 @ move LoC into position
- ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
- beq finished @ if loc is 0, then no need to clean
-start_flush_levels:
- mov r10, #0 @ start clean at cache level 0
-flush_levels:
- add r2, r10, r10, lsr #1 @ work out 3x current cache level
- mov r1, r0, lsr r2 @ extract cache type bits from clidr
- and r1, r1, #7 @ mask of the bits for current cache only
- cmp r1, #2 @ see what cache we have at this level
- blt skip @ skip if no cache, or just i-cache
- mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
- isb @ isb to sych the new cssr&csidr
- mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
- and r2, r1, #7 @ extract the length of the cache lines
- add r2, r2, #4 @ add 4 (line length offset)
- movw r4, #0x3ff
- ands r4, r4, r1, lsr #3 @ find maximum number on the way size
- clz r5, r4 @ find bit position of way size increment
- movw r7, #0x7fff
- ands r7, r7, r1, lsr #13 @ extract max number of the index size
-loop1:
- mov r9, r7 @ create working copy of max index
-loop2:
- ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
- THUMB( lsl r6, r4, r5 )
- THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
- ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
- THUMB( lsl r6, r9, r2 )
- THUMB( orr r11, r11, r6 ) @ factor index number into r11
- mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
- subs r9, r9, #1 @ decrement the index
- bge loop2
- subs r4, r4, #1 @ decrement the way
- bge loop1
-skip:
- add r10, r10, #2 @ increment cache number
- cmp r3, r10
- bgt flush_levels
-finished:
- mov r10, #0 @ swith back to cache level 0
- mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
- dsb st
- isb
- mov pc, lr
-ENDPROC(v7_flush_dcache_all)
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += bcu-ph1-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += bcu-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += bcu-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += bcu-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4) += bcu-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += bcu-ld4.o
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "bcu-regs.h"
+
+#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
+
+int uniphier_ld4_bcu_init(const struct uniphier_board_data *bd)
+{
+ int shift;
+
+ writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */
+ writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
+ writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
+ writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
+ writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
+
+ /* Specify DDR channel */
+ shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4;
+ writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
+
+ shift -= 32;
+ writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
+
+ shift -= 32;
+ writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
+
+ return 0;
+}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "bcu-regs.h"
-
-#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
-
-int ph1_ld4_bcu_init(const struct uniphier_board_data *bd)
-{
- int shift;
-
- writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */
- writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
- writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
- writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
- writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
-
- /* Specify DDR channel */
- shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4;
- writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
-
- shift -= 32;
- writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
-
- shift -= 32;
- writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "bcu-regs.h"
-
-#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
-
-int ph1_sld3_bcu_init(const struct uniphier_board_data *bd)
-{
- int shift;
-
- writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
- writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
- writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
- /*
- * 0xe0000000-0xefffffff: Ex-bus
- * 0xf0000000-0xfbffffff: ASM bus
- * 0xfc000000-0xffffffff: OCM bus
- */
- writel(0x24440000, BCSCR5);
-
- /* Specify DDR channel */
- shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4;
- writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
-
- shift -= 32;
- writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
-
- shift -= 32;
- writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
-
- return 0;
-}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "bcu-regs.h"
+
+#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
+
+int uniphier_sld3_bcu_init(const struct uniphier_board_data *bd)
+{
+ int shift;
+
+ writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
+ writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
+ writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
+ /*
+ * 0xe0000000-0xefffffff: Ex-bus
+ * 0xf0000000-0xfbffffff: ASM bus
+ * 0xfc000000-0xffffffff: OCM bus
+ */
+ writel(0x24440000, BCSCR5);
+
+ /* Specify DDR channel */
+ shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4;
+ writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
+
+ shift -= 32;
+ writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
+
+ shift -= 32;
+ writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
+
+ return 0;
+}
led_puts("U0");
switch (uniphier_get_soc_type()) {
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
- case SOC_UNIPHIER_PH1_SLD3:
- ph1_sld3_pin_init();
+#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
+ case SOC_UNIPHIER_SLD3:
+ uniphier_sld3_pin_init();
led_puts("U1");
- ph1_ld4_clk_init();
+ uniphier_ld4_clk_init();
break;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
- case SOC_UNIPHIER_PH1_LD4:
- ph1_ld4_pin_init();
+#if defined(CONFIG_ARCH_UNIPHIER_LD4)
+ case SOC_UNIPHIER_LD4:
+ uniphier_ld4_pin_init();
led_puts("U1");
- ph1_ld4_clk_init();
+ uniphier_ld4_clk_init();
break;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
- case SOC_UNIPHIER_PH1_PRO4:
- ph1_pro4_pin_init();
+#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
+ case SOC_UNIPHIER_PRO4:
+ uniphier_pro4_pin_init();
led_puts("U1");
- ph1_pro4_clk_init();
+ uniphier_pro4_clk_init();
break;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
- case SOC_UNIPHIER_PH1_SLD8:
- ph1_sld8_pin_init();
+#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
+ case SOC_UNIPHIER_SLD8:
+ uniphier_sld8_pin_init();
led_puts("U1");
- ph1_ld4_clk_init();
+ uniphier_ld4_clk_init();
break;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
- case SOC_UNIPHIER_PH1_PRO5:
- ph1_pro5_pin_init();
+#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
+ case SOC_UNIPHIER_PRO5:
+ uniphier_pro5_pin_init();
led_puts("U1");
- ph1_pro5_clk_init();
+ uniphier_pro5_clk_init();
break;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
- case SOC_UNIPHIER_PROXSTREAM2:
- proxstream2_pin_init();
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
+ case SOC_UNIPHIER_PXS2:
+ uniphier_pxs2_pin_init();
led_puts("U1");
- proxstream2_clk_init();
+ uniphier_pxs2_clk_init();
break;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
- case SOC_UNIPHIER_PH1_LD6B:
- ph1_ld6b_pin_init();
+#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
+ case SOC_UNIPHIER_LD6B:
+ uniphier_ld6b_pin_init();
led_puts("U1");
- proxstream2_clk_init();
+ uniphier_pxs2_clk_init();
break;
#endif
default:
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
-static const struct uniphier_board_data ph1_sld3_data = {
+#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
+static const struct uniphier_board_data uniphier_sld3_data = {
.dram_freq = 1600,
.dram_nr_ch = 3,
.dram_ch[0] = {
};
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
-static const struct uniphier_board_data ph1_ld4_data = {
+#if defined(CONFIG_ARCH_UNIPHIER_LD4)
+static const struct uniphier_board_data uniphier_ld4_data = {
.dram_freq = 1600,
.dram_nr_ch = 2,
.dram_ddr3plus = true,
};
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
+#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
/* 1GB RAM board */
-static const struct uniphier_board_data ph1_pro4_data = {
+static const struct uniphier_board_data uniphier_pro4_data = {
.dram_freq = 1600,
.dram_nr_ch = 2,
.dram_ch[0] = {
};
/* 2GB RAM board */
-static const struct uniphier_board_data ph1_pro4_2g_data = {
+static const struct uniphier_board_data uniphier_pro4_2g_data = {
.dram_freq = 1600,
.dram_nr_ch = 2,
.dram_ch[0] = {
};
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
-static const struct uniphier_board_data ph1_sld8_data = {
+#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
+static const struct uniphier_board_data uniphier_sld8_data = {
.dram_freq = 1333,
.dram_nr_ch = 2,
.dram_ddr3plus = true,
};
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
-static const struct uniphier_board_data ph1_pro5_data = {
+#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
+static const struct uniphier_board_data uniphier_pro5_data = {
.dram_freq = 1866,
.dram_nr_ch = 2,
.dram_ch[0] = {
};
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
-static const struct uniphier_board_data proxstream2_data = {
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
+static const struct uniphier_board_data uniphier_pxs2_data = {
.dram_freq = 2133,
.dram_nr_ch = 3,
.dram_ch[0] = {
};
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
-static const struct uniphier_board_data ph1_ld6b_data = {
+#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
+static const struct uniphier_board_data uniphier_ld6b_data = {
.dram_freq = 1866,
.dram_nr_ch = 3,
.dram_ch[0] = {
};
static const struct uniphier_board_id uniphier_boards[] = {
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
- { "socionext,ph1-sld3", &ph1_sld3_data, },
+#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
+ { "socionext,ph1-sld3", &uniphier_sld3_data, },
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
- { "socionext,ph1-ld4", &ph1_ld4_data, },
+#if defined(CONFIG_ARCH_UNIPHIER_LD4)
+ { "socionext,ph1-ld4", &uniphier_ld4_data, },
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
- { "socionext,ph1-pro4-ace", &ph1_pro4_2g_data, },
- { "socionext,ph1-pro4-sanji", &ph1_pro4_2g_data, },
- { "socionext,ph1-pro4", &ph1_pro4_data, },
+#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
+ { "socionext,ph1-pro4-ace", &uniphier_pro4_2g_data, },
+ { "socionext,ph1-pro4-sanji", &uniphier_pro4_2g_data, },
+ { "socionext,ph1-pro4", &uniphier_pro4_data, },
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
- { "socionext,ph1-sld8", &ph1_sld8_data, },
+#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
+ { "socionext,ph1-sld8", &uniphier_sld8_data, },
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
- { "socionext,ph1-pro5", &ph1_pro5_data, },
+#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
+ { "socionext,ph1-pro5", &uniphier_pro5_data, },
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
- { "socionext,proxstream2", &proxstream2_data, },
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
+ { "socionext,proxstream2", &uniphier_pxs2_data, },
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
- { "socionext,ph1-ld6b", &ph1_ld6b_data, },
+#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
+ { "socionext,ph1-ld6b", &uniphier_ld6b_data, },
#endif
};
obj-y += boot-mode.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += boot-mode-ph1-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += boot-mode-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += boot-mode-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += boot-mode-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += boot-mode-ph1-pro5.o
-obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += boot-mode-proxstream2.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += boot-mode-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += boot-mode-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4) += boot-mode-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += boot-mode-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += boot-mode-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += boot-mode-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += boot-mode-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-mode-pxs2.o
obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
char *info;
};
-u32 ph1_sld3_boot_device(void);
-u32 ph1_ld4_boot_device(void);
-u32 ph1_pro5_boot_device(void);
-u32 proxstream2_boot_device(void);
+u32 uniphier_sld3_boot_device(void);
+u32 uniphier_ld4_boot_device(void);
+u32 uniphier_pro5_boot_device(void);
+u32 uniphier_pxs2_boot_device(void);
-void ph1_sld3_boot_mode_show(void);
-void ph1_ld4_boot_mode_show(void);
-void ph1_pro5_boot_mode_show(void);
-void proxstream2_boot_mode_show(void);
+void uniphier_sld3_boot_mode_show(void);
+void uniphier_ld4_boot_mode_show(void);
+void uniphier_pro5_boot_mode_show(void);
+void uniphier_pxs2_boot_mode_show(void);
u32 spl_boot_device_raw(void);
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
+
+struct boot_device_info boot_device_table[] = {
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"},
+ {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NOR, "NOR Boot"},
+};
+
+static int get_boot_mode_sel(void)
+{
+ return (readl(SG_PINMON0) >> 1) & 0x1f;
+}
+
+u32 uniphier_ld4_boot_device(void)
+{
+ int boot_mode;
+
+ boot_mode = get_boot_mode_sel();
+
+ return boot_device_table[boot_mode].type;
+}
+
+void uniphier_ld4_boot_mode_show(void)
+{
+ int mode_sel, i;
+
+ mode_sel = get_boot_mode_sel();
+
+ puts("Boot Mode Pin:\n");
+
+ for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
+ printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+ boot_device_table[i].info);
+}
+++ /dev/null
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/io.h>
-
-#include "../sg-regs.h"
-#include "boot-device.h"
-
-struct boot_device_info boot_device_table[] = {
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"},
- {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
-};
-
-static int get_boot_mode_sel(void)
-{
- return (readl(SG_PINMON0) >> 1) & 0x1f;
-}
-
-u32 ph1_ld4_boot_device(void)
-{
- int boot_mode;
-
- boot_mode = get_boot_mode_sel();
-
- return boot_device_table[boot_mode].type;
-}
-
-void ph1_ld4_boot_mode_show(void)
-{
- int mode_sel, i;
-
- mode_sel = get_boot_mode_sel();
-
- puts("Boot Mode Pin:\n");
-
- for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
- printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
- boot_device_table[i].info);
-}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/io.h>
-
-#include "../sg-regs.h"
-#include "boot-device.h"
-
-static struct boot_device_info boot_device_table[] = {
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128MB, Addr 4)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512MB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128MB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
- { /* sentinel */ }
-};
-
-static int get_boot_mode_sel(void)
-{
- return (readl(SG_PINMON0) >> 1) & 0x1f;
-}
-
-u32 ph1_pro5_boot_device(void)
-{
- int boot_mode;
-
- boot_mode = get_boot_mode_sel();
-
- return boot_device_table[boot_mode].type;
-}
-
-void ph1_pro5_boot_mode_show(void)
-{
- int mode_sel, i;
-
- mode_sel = get_boot_mode_sel();
-
- puts("Boot Mode Pin:\n");
-
- for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
- printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
- boot_device_table[i].info);
-}
+++ /dev/null
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/io.h>
-
-#include "../sg-regs.h"
-#include "boot-device.h"
-
-static struct boot_device_info boot_device_table[] = {
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "External Master"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
-};
-
-static int get_boot_mode_sel(void)
-{
- return readl(SG_PINMON0) & 0x3f;
-}
-
-u32 ph1_sld3_boot_device(void)
-{
- int boot_mode;
-
- boot_mode = get_boot_mode_sel();
-
- return boot_device_table[boot_mode].type;
-}
-
-void ph1_sld3_boot_mode_show(void)
-{
- int mode_sel, i;
-
- mode_sel = get_boot_mode_sel();
-
- puts("Boot Mode Pin:\n");
-
- for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
- printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
- boot_device_table[i].info);
-}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
+
+static struct boot_device_info boot_device_table[] = {
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128MB, Addr 4)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512MB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128MB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+ { /* sentinel */ }
+};
+
+static int get_boot_mode_sel(void)
+{
+ return (readl(SG_PINMON0) >> 1) & 0x1f;
+}
+
+u32 uniphier_pro5_boot_device(void)
+{
+ int boot_mode;
+
+ boot_mode = get_boot_mode_sel();
+
+ return boot_device_table[boot_mode].type;
+}
+
+void uniphier_pro5_boot_mode_show(void)
+{
+ int mode_sel, i;
+
+ mode_sel = get_boot_mode_sel();
+
+ puts("Boot Mode Pin:\n");
+
+ for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
+ printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+ boot_device_table[i].info);
+}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/io.h>
-
-#include "../sg-regs.h"
-#include "boot-device.h"
-
-static struct boot_device_info boot_device_table[] = {
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
- {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 4)"},
- {BOOT_DEVICE_SPI, "SPI 3Byte CS0"},
- {BOOT_DEVICE_SPI, "SPI 4Byte CS0"},
- {BOOT_DEVICE_SPI, "SPI 3Byte CS1"},
- {BOOT_DEVICE_SPI, "SPI 4Byte CS1"},
- {BOOT_DEVICE_SPI, "SPI 4Byte CS0"},
- {BOOT_DEVICE_SPI, "SPI 3Byte CS0"},
- {BOOT_DEVICE_NONE, "Reserved"},
-};
-
-static int get_boot_mode_sel(void)
-{
- return (readl(SG_PINMON0) >> 1) & 0x1f;
-}
-
-u32 proxstream2_boot_device(void)
-{
- int boot_mode;
-
- if (readl(SG_PINMON0) & BIT(6))
- return BOOT_DEVICE_USB;
-
- boot_mode = get_boot_mode_sel();
-
- return boot_device_table[boot_mode].type;
-}
-
-void proxstream2_boot_mode_show(void)
-{
- int mode_sel, i;
-
- mode_sel = get_boot_mode_sel();
-
- puts("Boot Mode Pin:\n");
-
- for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
- printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
- boot_device_table[i].info);
-}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
+
+static struct boot_device_info boot_device_table[] = {
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
+ {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 4)"},
+ {BOOT_DEVICE_SPI, "SPI 3Byte CS0"},
+ {BOOT_DEVICE_SPI, "SPI 4Byte CS0"},
+ {BOOT_DEVICE_SPI, "SPI 3Byte CS1"},
+ {BOOT_DEVICE_SPI, "SPI 4Byte CS1"},
+ {BOOT_DEVICE_SPI, "SPI 4Byte CS0"},
+ {BOOT_DEVICE_SPI, "SPI 3Byte CS0"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+};
+
+static int get_boot_mode_sel(void)
+{
+ return (readl(SG_PINMON0) >> 1) & 0x1f;
+}
+
+u32 uniphier_pxs2_boot_device(void)
+{
+ int boot_mode;
+
+ if (readl(SG_PINMON0) & BIT(6))
+ return BOOT_DEVICE_USB;
+
+ boot_mode = get_boot_mode_sel();
+
+ return boot_device_table[boot_mode].type;
+}
+
+void uniphier_pxs2_boot_mode_show(void)
+{
+ int mode_sel, i;
+
+ mode_sel = get_boot_mode_sel();
+
+ puts("Boot Mode Pin:\n");
+
+ for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
+ printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+ boot_device_table[i].info);
+}
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
+
+static struct boot_device_info boot_device_table[] = {
+ {BOOT_DEVICE_NOR, "NOR boot"},
+ {BOOT_DEVICE_NONE, "External Master"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+};
+
+static int get_boot_mode_sel(void)
+{
+ return readl(SG_PINMON0) & 0x3f;
+}
+
+u32 uniphier_sld3_boot_device(void)
+{
+ int boot_mode;
+
+ boot_mode = get_boot_mode_sel();
+
+ return boot_device_table[boot_mode].type;
+}
+
+void uniphier_sld3_boot_mode_show(void)
+{
+ int mode_sel, i;
+
+ mode_sel = get_boot_mode_sel();
+
+ puts("Boot Mode Pin:\n");
+
+ for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
+ printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+ boot_device_table[i].info);
+}
return BOOT_DEVICE_NOR;
switch (uniphier_get_soc_type()) {
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
- case SOC_UNIPHIER_PH1_SLD3:
- return ph1_sld3_boot_device();
+#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
+ case SOC_UNIPHIER_SLD3:
+ return uniphier_sld3_boot_device();
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
- defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) || \
- defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
- case SOC_UNIPHIER_PH1_LD4:
- case SOC_UNIPHIER_PH1_PRO4:
- case SOC_UNIPHIER_PH1_SLD8:
- return ph1_ld4_boot_device();
+#if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_PRO4) || \
+ defined(CONFIG_ARCH_UNIPHIER_SLD8)
+ case SOC_UNIPHIER_LD4:
+ case SOC_UNIPHIER_PRO4:
+ case SOC_UNIPHIER_SLD8:
+ return uniphier_ld4_boot_device();
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
- case SOC_UNIPHIER_PH1_PRO5:
- return ph1_pro5_boot_device();
+#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
+ case SOC_UNIPHIER_PRO5:
+ return uniphier_pro5_boot_device();
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
- defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
- case SOC_UNIPHIER_PROXSTREAM2:
- case SOC_UNIPHIER_PH1_LD6B:
- return proxstream2_boot_device();
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
+ case SOC_UNIPHIER_PXS2:
+ case SOC_UNIPHIER_LD6B:
+ return uniphier_pxs2_boot_device();
#endif
default:
return BOOT_DEVICE_NONE;
printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
switch (uniphier_get_soc_type()) {
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
- case SOC_UNIPHIER_PH1_SLD3:
- ph1_sld3_boot_mode_show();
+#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
+ case SOC_UNIPHIER_SLD3:
+ uniphier_sld3_boot_mode_show();
break;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
- defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) || \
- defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
- case SOC_UNIPHIER_PH1_LD4:
- case SOC_UNIPHIER_PH1_PRO4:
- case SOC_UNIPHIER_PH1_SLD8:
- ph1_ld4_boot_mode_show();
+#if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_PRO4) || \
+ defined(CONFIG_ARCH_UNIPHIER_SLD8)
+ case SOC_UNIPHIER_LD4:
+ case SOC_UNIPHIER_PRO4:
+ case SOC_UNIPHIER_SLD8:
+ uniphier_ld4_boot_mode_show();
break;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
- case SOC_UNIPHIER_PH1_PRO5:
- ph1_pro5_boot_mode_show();
+#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
+ case SOC_UNIPHIER_PRO5:
+ uniphier_pro5_boot_mode_show();
break;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
- defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
- case SOC_UNIPHIER_PROXSTREAM2:
- case SOC_UNIPHIER_PH1_LD6B:
- proxstream2_boot_mode_show();
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
+ case SOC_UNIPHIER_PXS2:
+ case SOC_UNIPHIER_LD6B:
+ uniphier_pxs2_boot_mode_show();
break;
#endif
default:
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += clk-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += clk-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += clk-ph1-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += clk-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += clk-ph1-pro5.o
-obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += clk-proxstream2.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += clk-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+void uniphier_ld4_clk_init(void)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL);
+#ifdef CONFIG_UNIPHIER_ETH
+ tmp |= SC_RSTCTRL_NRST_ETHER;
+#endif
+#ifdef CONFIG_USB_EHCI
+ tmp |= SC_RSTCTRL_NRST_STDMAC;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
+ writel(tmp, SC_RSTCTRL);
+ readl(SC_RSTCTRL); /* dummy read */
+
+ /* provide clocks */
+ tmp = readl(SC_CLKCTRL);
+#ifdef CONFIG_UNIPHIER_ETH
+ tmp |= SC_CLKCTRL_CEN_ETHER;
+#endif
+#ifdef CONFIG_USB_EHCI
+ tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
+ writel(tmp, SC_CLKCTRL);
+ readl(SC_CLKCTRL); /* dummy read */
+}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-
-void ph1_ld4_clk_init(void)
-{
- u32 tmp;
-
- /* deassert reset */
- tmp = readl(SC_RSTCTRL);
-#ifdef CONFIG_UNIPHIER_ETH
- tmp |= SC_RSTCTRL_NRST_ETHER;
-#endif
-#ifdef CONFIG_USB_EHCI
- tmp |= SC_RSTCTRL_NRST_STDMAC;
-#endif
-#ifdef CONFIG_NAND_DENALI
- tmp |= SC_RSTCTRL_NRST_NAND;
-#endif
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
-
- /* privide clocks */
- tmp = readl(SC_CLKCTRL);
-#ifdef CONFIG_UNIPHIER_ETH
- tmp |= SC_CLKCTRL_CEN_ETHER;
-#endif
-#ifdef CONFIG_USB_EHCI
- tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
-#endif
-#ifdef CONFIG_NAND_DENALI
- tmp |= SC_CLKCTRL_CEN_NAND;
-#endif
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-
-void ph1_pro4_clk_init(void)
-{
- u32 tmp;
-
- /* deassert reset */
- tmp = readl(SC_RSTCTRL);
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
- SC_RSTCTRL_NRST_GIO;
-#endif
-#ifdef CONFIG_UNIPHIER_ETH
- tmp |= SC_RSTCTRL_NRST_ETHER;
-#endif
-#ifdef CONFIG_USB_EHCI
- tmp |= SC_RSTCTRL_NRST_STDMAC;
-#endif
-#ifdef CONFIG_NAND_DENALI
- tmp |= SC_RSTCTRL_NRST_NAND;
-#endif
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
-
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- tmp = readl(SC_RSTCTRL2);
- tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1;
- writel(tmp, SC_RSTCTRL2);
- readl(SC_RSTCTRL2); /* dummy read */
-#endif
-
- /* privide clocks */
- tmp = readl(SC_CLKCTRL);
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
- SC_CLKCTRL_CEN_GIO;
-#endif
-#ifdef CONFIG_UNIPHIER_ETH
- tmp |= SC_CLKCTRL_CEN_ETHER;
-#endif
-#ifdef CONFIG_USB_EHCI
- tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
-#endif
-#ifdef CONFIG_NAND_DENALI
- tmp |= SC_CLKCTRL_CEN_NAND;
-#endif
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
-}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-
-void ph1_pro5_clk_init(void)
-{
- u32 tmp;
-
- /* deassert reset */
- tmp = readl(SC_RSTCTRL);
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
-#endif
-#ifdef CONFIG_NAND_DENALI
- tmp |= SC_RSTCTRL_NRST_NAND;
-#endif
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
-
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- tmp = readl(SC_RSTCTRL2);
- tmp |= SC_RSTCTRL2_NRST_USB3B1;
- writel(tmp, SC_RSTCTRL2);
- readl(SC_RSTCTRL2); /* dummy read */
-#endif
-
- /* privide clocks */
- tmp = readl(SC_CLKCTRL);
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
- SC_CLKCTRL_CEN_GIO;
-#endif
-#ifdef CONFIG_NAND_DENALI
- tmp |= SC_CLKCTRL_CEN_NAND;
-#endif
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
-}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+void uniphier_pro4_clk_init(void)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
+ SC_RSTCTRL_NRST_GIO;
+#endif
+#ifdef CONFIG_UNIPHIER_ETH
+ tmp |= SC_RSTCTRL_NRST_ETHER;
+#endif
+#ifdef CONFIG_USB_EHCI
+ tmp |= SC_RSTCTRL_NRST_STDMAC;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
+ writel(tmp, SC_RSTCTRL);
+ readl(SC_RSTCTRL); /* dummy read */
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp = readl(SC_RSTCTRL2);
+ tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1;
+ writel(tmp, SC_RSTCTRL2);
+ readl(SC_RSTCTRL2); /* dummy read */
+#endif
+
+ /* provide clocks */
+ tmp = readl(SC_CLKCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+ SC_CLKCTRL_CEN_GIO;
+#endif
+#ifdef CONFIG_UNIPHIER_ETH
+ tmp |= SC_CLKCTRL_CEN_ETHER;
+#endif
+#ifdef CONFIG_USB_EHCI
+ tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
+ writel(tmp, SC_CLKCTRL);
+ readl(SC_CLKCTRL); /* dummy read */
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+void uniphier_pro5_clk_init(void)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
+ writel(tmp, SC_RSTCTRL);
+ readl(SC_RSTCTRL); /* dummy read */
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp = readl(SC_RSTCTRL2);
+ tmp |= SC_RSTCTRL2_NRST_USB3B1;
+ writel(tmp, SC_RSTCTRL2);
+ readl(SC_RSTCTRL2); /* dummy read */
+#endif
+
+ /* provide clocks */
+ tmp = readl(SC_CLKCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+ SC_CLKCTRL_CEN_GIO;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
+ writel(tmp, SC_CLKCTRL);
+ readl(SC_CLKCTRL); /* dummy read */
+}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-
-void proxstream2_clk_init(void)
-{
- u32 tmp;
-
- /* deassert reset */
- tmp = readl(SC_RSTCTRL);
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
-#endif
-#ifdef CONFIG_UNIPHIER_ETH
- tmp |= SC_RSTCTRL_NRST_ETHER;
-#endif
-#ifdef CONFIG_NAND_DENALI
- tmp |= SC_RSTCTRL_NRST_NAND;
-#endif
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
-
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- tmp = readl(SC_RSTCTRL2);
- tmp |= SC_RSTCTRL2_NRST_USB3B1;
- writel(tmp, SC_RSTCTRL2);
- readl(SC_RSTCTRL2); /* dummy read */
-#endif
-
- /* privide clocks */
- tmp = readl(SC_CLKCTRL);
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
- SC_CLKCTRL_CEN_GIO;
-#endif
-#ifdef CONFIG_UNIPHIER_ETH
- tmp |= SC_CLKCTRL_CEN_ETHER;
-#endif
-#ifdef CONFIG_NAND_DENALI
- tmp |= SC_CLKCTRL_CEN_NAND;
-#endif
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
-}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+void uniphier_pxs2_clk_init(void)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
+#endif
+#ifdef CONFIG_UNIPHIER_ETH
+ tmp |= SC_RSTCTRL_NRST_ETHER;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
+ writel(tmp, SC_RSTCTRL);
+ readl(SC_RSTCTRL); /* dummy read */
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp = readl(SC_RSTCTRL2);
+ tmp |= SC_RSTCTRL2_NRST_USB3B1;
+ writel(tmp, SC_RSTCTRL2);
+ readl(SC_RSTCTRL2); /* dummy read */
+#endif
+
+ /* provide clocks */
+ tmp = readl(SC_CLKCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+ SC_CLKCTRL_CEN_GIO;
+#endif
+#ifdef CONFIG_UNIPHIER_ETH
+ tmp |= SC_CLKCTRL_CEN_ETHER;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
+ writel(tmp, SC_CLKCTRL);
+ readl(SC_CLKCTRL); /* dummy read */
+}
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += debug-uart-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4) += debug-uart-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += debug-uart-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += debug-uart-sld8.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += debug-uart-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += debug-uart-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += debug-uart-ld6b.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += debug-uart-ld20.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += debug-uart-ld20.o
+endif
+
+obj-y += debug-uart.o
--- /dev/null
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "../sc64-regs.h"
+#include "../sg-regs.h"
+#include "debug-uart.h"
+
+#define UNIPHIER_LD20_UART_CLK 58820000
+
+unsigned int uniphier_ld20_debug_uart_init(void)
+{
+ u32 tmp;
+
+ sg_set_iectrl(54); /* TXD0 */
+ sg_set_iectrl(58); /* TXD1 */
+ sg_set_iectrl(90); /* TXD2 */
+ sg_set_iectrl(94); /* TXD3 */
+ sg_set_pinsel(54, 0, 8, 4); /* TXD0 -> TXD0 */
+ sg_set_pinsel(58, 1, 8, 4); /* SPITXD1 -> TXD1 */
+ sg_set_pinsel(90, 1, 8, 4); /* PC0WE -> TXD2 */
+ sg_set_pinsel(94, 1, 8, 4); /* PCD00 -> TXD3 */
+
+ tmp = readl(SC_CLKCTRL4);
+ tmp |= SC_CLKCTRL4_PERI;
+ writel(tmp, SC_CLKCTRL4);
+
+ return DIV_ROUND_CLOSEST(UNIPHIER_LD20_UART_CLK, 16 * CONFIG_BAUDRATE);
+}
--- /dev/null
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/kernel.h>
+
+#include "../sg-regs.h"
+#include "debug-uart.h"
+
+#define UNIPHIER_LD4_UART_CLK 36864000
+
+unsigned int uniphier_ld4_debug_uart_init(void)
+{
+ sg_set_iectrl(0);
+ sg_set_pinsel(88, 1, 8, 4); /* HSDOUT6 -> TXD0 */
+
+ return DIV_ROUND_CLOSEST(UNIPHIER_LD4_UART_CLK, 16 * CONFIG_BAUDRATE);
+}
--- /dev/null
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "../sc-regs.h"
+#include "../sg-regs.h"
+#include "debug-uart.h"
+
+#define UNIPHIER_LD6B_UART_CLK 88888888
+
+unsigned int uniphier_ld6b_debug_uart_init(void)
+{
+ u32 tmp;
+
+ sg_set_iectrl(0);
+ sg_set_pinsel(135, 3, 8, 4); /* PORT10 -> TXD0 */
+ sg_set_pinsel(115, 0, 8, 4); /* TXD1 -> TXD1 */
+ sg_set_pinsel(113, 2, 8, 4); /* SBO0 -> TXD2 */
+
+ tmp = readl(SC_CLKCTRL);
+ tmp |= SC_CLKCTRL_CEN_PERI;
+ writel(tmp, SC_CLKCTRL);
+
+ return DIV_ROUND_CLOSEST(UNIPHIER_LD6B_UART_CLK, 16 * CONFIG_BAUDRATE);
+}
--- /dev/null
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "../sc-regs.h"
+#include "../sg-regs.h"
+#include "debug-uart.h"
+
+#define UNIPHIER_PRO4_UART_CLK 73728000
+
+unsigned int uniphier_pro4_debug_uart_init(void)
+{
+ u32 tmp;
+
+ sg_set_iectrl(0);
+ sg_set_pinsel(128, 0, 4, 8); /* TXD0 -> TXD0 */
+
+ writel(1, SG_LOADPINCTRL);
+
+ tmp = readl(SC_CLKCTRL);
+ tmp |= SC_CLKCTRL_CEN_PERI;
+ writel(tmp, SC_CLKCTRL);
+
+ return DIV_ROUND_CLOSEST(UNIPHIER_PRO4_UART_CLK, 16 * CONFIG_BAUDRATE);
+}
--- /dev/null
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "../sc-regs.h"
+#include "../sg-regs.h"
+#include "debug-uart.h"
+
+#define UNIPHIER_PRO5_UART_CLK 73728000
+
+unsigned int uniphier_pro5_debug_uart_init(void)
+{
+ u32 tmp;
+
+ sg_set_iectrl(0);
+ sg_set_pinsel(47, 0, 4, 8); /* TXD0 -> TXD0 */
+ sg_set_pinsel(49, 0, 4, 8); /* TXD1 -> TXD1 */
+ sg_set_pinsel(51, 0, 4, 8); /* TXD2 -> TXD2 */
+ sg_set_pinsel(53, 0, 4, 8); /* TXD3 -> TXD3 */
+
+ writel(1, SG_LOADPINCTRL);
+
+ tmp = readl(SC_CLKCTRL);
+ tmp |= SC_CLKCTRL_CEN_PERI;
+ writel(tmp, SC_CLKCTRL);
+
+ return DIV_ROUND_CLOSEST(UNIPHIER_PRO5_UART_CLK, 16 * CONFIG_BAUDRATE);
+}
--- /dev/null
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "../sc-regs.h"
+#include "../sg-regs.h"
+#include "debug-uart.h"
+
+#define UNIPHIER_PXS2_UART_CLK 88888888
+
+unsigned int uniphier_pxs2_debug_uart_init(void)
+{
+ u32 tmp;
+
+ sg_set_iectrl(0);
+ sg_set_pinsel(217, 8, 8, 4); /* TXD0 -> TXD0 */
+ sg_set_pinsel(115, 8, 8, 4); /* TXD1 -> TXD1 */
+ sg_set_pinsel(113, 8, 8, 4); /* TXD2 -> TXD2 */
+ sg_set_pinsel(219, 8, 8, 4); /* TXD3 -> TXD3 */
+
+ tmp = readl(SC_CLKCTRL);
+ tmp |= SC_CLKCTRL_CEN_PERI;
+ writel(tmp, SC_CLKCTRL);
+
+ return DIV_ROUND_CLOSEST(UNIPHIER_PXS2_UART_CLK, 16 * CONFIG_BAUDRATE);
+}
--- /dev/null
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "../bcu/bcu-regs.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
+#include "debug-uart.h"
+
+#define UNIPHIER_SLD3_UART_CLK 36864000
+
+unsigned int uniphier_sld3_debug_uart_init(void)
+{
+ u32 tmp;
+
+ sg_set_pinsel(64, 1, 4, 4); /* TXD0 -> TXD0 */
+
+ writel(0x24440000, BCSCR5);
+
+ tmp = readl(SC_CLKCTRL);
+ tmp |= SC_CLKCTRL_CEN_PERI;
+ writel(tmp, SC_CLKCTRL);
+
+ return DIV_ROUND_CLOSEST(UNIPHIER_SLD3_UART_CLK, 16 * CONFIG_BAUDRATE);
+}
--- /dev/null
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/kernel.h>
+
+#include "../sg-regs.h"
+#include "debug-uart.h"
+
+#define UNIPHIER_SLD8_UART_CLK 80000000
+
+unsigned int uniphier_sld8_debug_uart_init(void)
+{
+ sg_set_iectrl(0);
+ sg_set_pinsel(70, 3, 8, 4); /* HSDOUT6 -> TXD0 */
+
+ return DIV_ROUND_CLOSEST(UNIPHIER_SLD8_UART_CLK, 16 * CONFIG_BAUDRATE);
+}
--- /dev/null
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <linux/io.h>
+#include <linux/serial_reg.h>
+
+#include "../soc-info.h"
+#include "debug-uart.h"
+
+#define UNIPHIER_UART_TX 0x00
+#define UNIPHIER_UART_LCR_MCR 0x10
+#define UNIPHIER_UART_LSR 0x14
+#define UNIPHIER_UART_LDR 0x24
+
+static void _debug_uart_putc(int c)
+{
+ void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+
+ while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE))
+ ;
+
+ writel(c, base + UNIPHIER_UART_TX);
+}
+
+void _debug_uart_init(void)
+{
+ void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+ unsigned int divisor;
+
+ switch (uniphier_get_soc_type()) {
+#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
+ case SOC_UNIPHIER_SLD3:
+ divisor = uniphier_sld3_debug_uart_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD4)
+ case SOC_UNIPHIER_LD4:
+ divisor = uniphier_ld4_debug_uart_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
+ case SOC_UNIPHIER_PRO4:
+ divisor = uniphier_pro4_debug_uart_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
+ case SOC_UNIPHIER_SLD8:
+ divisor = uniphier_sld8_debug_uart_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
+ case SOC_UNIPHIER_PRO5:
+ divisor = uniphier_pro5_debug_uart_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
+ case SOC_UNIPHIER_PXS2:
+ divisor = uniphier_pxs2_debug_uart_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
+ case SOC_UNIPHIER_LD6B:
+ divisor = uniphier_ld6b_debug_uart_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
+ case SOC_UNIPHIER_LD11:
+ case SOC_UNIPHIER_LD20:
+ divisor = uniphier_ld20_debug_uart_init();
+ break;
+#endif
+ default:
+ return;
+ }
+
+ writel(UART_LCR_WLEN8 << 8, base + UNIPHIER_UART_LCR_MCR);
+
+ writel(divisor, base + UNIPHIER_UART_LDR);
+}
+DEBUG_UART_FUNCS
--- /dev/null
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _MACH_DEBUG_UART_H
+#define _MACH_DEBUG_UART_H
+
+unsigned int uniphier_sld3_debug_uart_init(void);
+unsigned int uniphier_ld4_debug_uart_init(void);
+unsigned int uniphier_pro4_debug_uart_init(void);
+unsigned int uniphier_sld8_debug_uart_init(void);
+unsigned int uniphier_pro5_debug_uart_init(void);
+unsigned int uniphier_pxs2_debug_uart_init(void);
+unsigned int uniphier_ld6b_debug_uart_init(void);
+unsigned int uniphier_ld11_debug_uart_init(void);
+unsigned int uniphier_ld20_debug_uart_init(void);
+
+#endif /* _MACH_DEBUG_UART_H */
ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o \
- ddrphy-training.o ddrphy-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o \
- ddrphy-training.o ddrphy-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o \
- ddrphy-training.o ddrphy-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += umc-proxstream2.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += umc-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4) += umc-ld4.o \
+ ddrphy-training.o ddrphy-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += umc-pro4.o \
+ ddrphy-training.o ddrphy-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += umc-sld8.o \
+ ddrphy-training.o ddrphy-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o
else
*/
#include <common.h>
+#include <mapmem.h>
#include <linux/io.h>
+#include <linux/sizes.h>
+#include "../soc-info.h"
#include "ddrphy-regs.h"
/* Select either decimal or hexadecimal */
/* field separator */
#define FS " "
+static unsigned long uniphier_ld4_base[] = {
+ 0x5bc01000,
+ 0x5be01000,
+ 0 /* sentinel */
+};
+
+static unsigned long uniphier_pro4_base[] = {
+ 0x5bc01000,
+ 0x5be01000,
+ 0 /* sentinel */
+};
+
+static unsigned long uniphier_sld8_base[] = {
+ 0x5bc01000,
+ 0x5be01000,
+ 0 /* sentinel */
+};
+
static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index)
{
return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f;
}
-static void dump_loop(void (*callback)(struct ddrphy_datx8 __iomem *))
+static void dump_loop(unsigned long *base,
+ void (*callback)(struct ddrphy_datx8 __iomem *))
{
- int ch, p, dx;
struct ddrphy __iomem *phy;
+ int p, dx;
- for (ch = 0; ch < NR_DDRCH; ch++) {
- for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
- phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
+ for (p = 0; *base; base++, p++) {
+ phy = map_sysmem(*base, SZ_4K);
- for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
- printf("CH%dP%dDX%d:", ch, p, dx);
- (*callback)(&phy->dx[dx]);
- printf("\n");
- }
+ for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
+ printf("PHY%dDX%d:", p, dx);
+ (*callback)(&phy->dx[dx]);
+ printf("\n");
}
+
+ unmap_sysmem(phy);
}
}
printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff);
}
-static void wbdl_dump(void)
+static void wbdl_dump(unsigned long *base)
{
printf("\n--- Write Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
- dump_loop(&__wbdl_dump);
+ dump_loop(base, &__wbdl_dump);
}
static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx)
printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff);
}
-static void rbdl_dump(void)
+static void rbdl_dump(unsigned long *base)
{
printf("\n--- Read Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
- dump_loop(&__rbdl_dump);
+ dump_loop(base, &__rbdl_dump);
}
static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
}
}
-static void wld_dump(void)
+static void wld_dump(unsigned long *base)
{
printf("\n--- Write Leveling Delay ---\n");
printf(" Rank0 Rank1 Rank2 Rank3\n");
- dump_loop(&__wld_dump);
+ dump_loop(base, &__wld_dump);
}
static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
}
}
-static void dqsgd_dump(void)
+static void dqsgd_dump(unsigned long *base)
{
printf("\n--- DQS Gating Delay ---\n");
printf(" Rank0 Rank1 Rank2 Rank3\n");
- dump_loop(&__dqsgd_dump);
+ dump_loop(base, &__dqsgd_dump);
}
static void __mdl_dump(struct ddrphy_datx8 __iomem *dx)
printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
}
-static void mdl_dump(void)
+static void mdl_dump(unsigned long *base)
{
printf("\n--- Master Delay Line ---\n");
printf(" IPRD TPRD MDLD\n");
- dump_loop(&__mdl_dump);
+ dump_loop(base, &__mdl_dump);
}
#define REG_DUMP(x) \
{ u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
p - (u32 *)phy, #x, p, readl(p)); }
-static void reg_dump(void)
+static void reg_dump(unsigned long *base)
{
- int ch, p;
struct ddrphy __iomem *phy;
+ int p;
printf("\n--- DDR PHY registers ---\n");
- for (ch = 0; ch < NR_DDRCH; ch++) {
- for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
- printf("== Ch%d, PHY%d ==\n", ch, p);
- printf(" No: Name : Address : Data\n");
-
- phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
-
- REG_DUMP(ridr);
- REG_DUMP(pir);
- REG_DUMP(pgcr[0]);
- REG_DUMP(pgcr[1]);
- REG_DUMP(pgsr[0]);
- REG_DUMP(pgsr[1]);
- REG_DUMP(pllcr);
- REG_DUMP(ptr[0]);
- REG_DUMP(ptr[1]);
- REG_DUMP(ptr[2]);
- REG_DUMP(ptr[3]);
- REG_DUMP(ptr[4]);
- REG_DUMP(acmdlr);
- REG_DUMP(acbdlr);
- REG_DUMP(dxccr);
- REG_DUMP(dsgcr);
- REG_DUMP(dcr);
- REG_DUMP(dtpr[0]);
- REG_DUMP(dtpr[1]);
- REG_DUMP(dtpr[2]);
- REG_DUMP(mr0);
- REG_DUMP(mr1);
- REG_DUMP(mr2);
- REG_DUMP(mr3);
- REG_DUMP(dx[0].gcr);
- REG_DUMP(dx[0].gtr);
- REG_DUMP(dx[1].gcr);
- REG_DUMP(dx[1].gtr);
- }
+ for (p = 0; *base; base++, p++) {
+ phy = map_sysmem(*base, SZ_4K);
+
+ printf("== PHY%d (base: %p) ==\n", p, phy);
+ printf(" No: Name : Address : Data\n");
+
+ REG_DUMP(ridr);
+ REG_DUMP(pir);
+ REG_DUMP(pgcr[0]);
+ REG_DUMP(pgcr[1]);
+ REG_DUMP(pgsr[0]);
+ REG_DUMP(pgsr[1]);
+ REG_DUMP(pllcr);
+ REG_DUMP(ptr[0]);
+ REG_DUMP(ptr[1]);
+ REG_DUMP(ptr[2]);
+ REG_DUMP(ptr[3]);
+ REG_DUMP(ptr[4]);
+ REG_DUMP(acmdlr);
+ REG_DUMP(acbdlr);
+ REG_DUMP(dxccr);
+ REG_DUMP(dsgcr);
+ REG_DUMP(dcr);
+ REG_DUMP(dtpr[0]);
+ REG_DUMP(dtpr[1]);
+ REG_DUMP(dtpr[2]);
+ REG_DUMP(mr0);
+ REG_DUMP(mr1);
+ REG_DUMP(mr2);
+ REG_DUMP(mr3);
+ REG_DUMP(dx[0].gcr);
+ REG_DUMP(dx[0].gtr);
+ REG_DUMP(dx[1].gcr);
+ REG_DUMP(dx[1].gtr);
+
+ unmap_sysmem(phy);
}
}
static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *cmd = argv[1];
+ unsigned long *base;
+
+ switch (uniphier_get_soc_type()) {
+ case SOC_UNIPHIER_LD4:
+ base = uniphier_ld4_base;
+ break;
+ case SOC_UNIPHIER_PRO4:
+ base = uniphier_pro4_base;
+ break;
+ case SOC_UNIPHIER_SLD8:
+ base = uniphier_sld8_base;
+ break;
+ default:
+ printf("unsupported SoC\n");
+ return CMD_RET_FAILURE;
+ }
if (argc == 1)
cmd = "all";
if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
- wbdl_dump();
+ wbdl_dump(base);
if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
- rbdl_dump();
+ rbdl_dump(base);
if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
- wld_dump();
+ wld_dump(base);
if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
- dqsgd_dump();
+ dqsgd_dump(base);
if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
- mdl_dump();
+ mdl_dump(base);
if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
- reg_dump();
+ reg_dump(base);
- return 0;
+ return CMD_RET_SUCCESS;
}
U_BOOT_CMD(
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/types.h>
+#include <linux/io.h>
+
+#include "ddrphy-regs.h"
+
+enum dram_freq {
+ DRAM_FREQ_1333M,
+ DRAM_FREQ_1600M,
+ DRAM_FREQ_NR,
+};
+
+static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0a806844, 0x0c807d04};
+static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x208e0124, 0x2710015E};
+static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x0f051616, 0x12061A80};
+static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x06ae08d6, 0x08027100};
+static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x85589955, 0x999cbb66};
+static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x1a8363c0, 0x1a878400};
+static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x5002c200, 0xa00214f8};
+static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71};
+static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298};
+
+int uniphier_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq,
+ bool ddr3plus)
+{
+ enum dram_freq freq_e;
+ u32 tmp;
+
+ switch (freq) {
+ case 1333:
+ freq_e = DRAM_FREQ_1333M;
+ break;
+ case 1600:
+ freq_e = DRAM_FREQ_1600M;
+ break;
+ default:
+ printf("unsupported DRAM frequency %d MHz\n", freq);
+ return -EINVAL;
+ }
+
+ writel(0x0300c473, &phy->pgcr[1]);
+ writel(ddrphy_ptr0[freq_e], &phy->ptr[0]);
+ writel(ddrphy_ptr1[freq_e], &phy->ptr[1]);
+ writel(0x00083DEF, &phy->ptr[2]);
+ writel(ddrphy_ptr3[freq_e], &phy->ptr[3]);
+ writel(ddrphy_ptr4[freq_e], &phy->ptr[4]);
+ writel(0xF004001A, &phy->dsgcr);
+
+ /* change the value of the on-die pull-up/pull-down registors */
+ tmp = readl(&phy->dxccr);
+ tmp &= ~0x0ee0;
+ tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+ writel(tmp, &phy->dxccr);
+
+ writel(0x0000040B, &phy->dcr);
+ writel(ddrphy_dtpr0[freq_e], &phy->dtpr[0]);
+ writel(ddrphy_dtpr1[freq_e], &phy->dtpr[1]);
+ writel(ddrphy_dtpr2[freq_e], &phy->dtpr[2]);
+ writel(ddrphy_mr0[freq_e], &phy->mr0);
+ writel(0x00000006, &phy->mr1);
+ writel(ddrphy_mr2[freq_e], &phy->mr2);
+ writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);
+
+ while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+ ;
+
+ writel(0x0300C473, &phy->pgcr[1]);
+ writel(0x0000005D, &phy->zq[0].cr[1]);
+
+ return 0;
+}
+++ /dev/null
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/types.h>
-#include <linux/io.h>
-
-#include "ddrphy-regs.h"
-
-enum dram_freq {
- DRAM_FREQ_1333M,
- DRAM_FREQ_1600M,
- DRAM_FREQ_NR,
-};
-
-static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0a806844, 0x0c807d04};
-static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x208e0124, 0x2710015E};
-static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x0f051616, 0x12061A80};
-static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x06ae08d6, 0x08027100};
-static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x85589955, 0x999cbb66};
-static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x1a8363c0, 0x1a878400};
-static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x5002c200, 0xa00214f8};
-static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71};
-static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298};
-
-int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus)
-{
- enum dram_freq freq_e;
- u32 tmp;
-
- switch (freq) {
- case 1333:
- freq_e = DRAM_FREQ_1333M;
- break;
- case 1600:
- freq_e = DRAM_FREQ_1600M;
- break;
- default:
- printf("unsupported DRAM frequency %d MHz\n", freq);
- return -EINVAL;
- }
-
- writel(0x0300c473, &phy->pgcr[1]);
- writel(ddrphy_ptr0[freq_e], &phy->ptr[0]);
- writel(ddrphy_ptr1[freq_e], &phy->ptr[1]);
- writel(0x00083DEF, &phy->ptr[2]);
- writel(ddrphy_ptr3[freq_e], &phy->ptr[3]);
- writel(ddrphy_ptr4[freq_e], &phy->ptr[4]);
- writel(0xF004001A, &phy->dsgcr);
-
- /* change the value of the on-die pull-up/pull-down registors */
- tmp = readl(&phy->dxccr);
- tmp &= ~0x0ee0;
- tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
- writel(tmp, &phy->dxccr);
-
- writel(0x0000040B, &phy->dcr);
- writel(ddrphy_dtpr0[freq_e], &phy->dtpr[0]);
- writel(ddrphy_dtpr1[freq_e], &phy->dtpr[1]);
- writel(ddrphy_dtpr2[freq_e], &phy->dtpr[2]);
- writel(ddrphy_mr0[freq_e], &phy->mr0);
- writel(0x00000006, &phy->mr1);
- writel(ddrphy_mr2[freq_e], &phy->mr2);
- writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);
-
- while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
- ;
-
- writel(0x0300C473, &phy->pgcr[1]);
- writel(0x0000005D, &phy->zq[0].cr[1]);
-
- return 0;
-}
/* SoC-specific parameters */
#define NR_DATX8_PER_DDRPHY 2
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
- defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
-#define NR_DDRPHY_PER_CH 1
-#else
-#define NR_DDRPHY_PER_CH 2
-#endif
-
-#define NR_DDRCH 2
-
-#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
-
#ifndef __ASSEMBLY__
-int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus);
+int uniphier_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq,
+ bool ddr3plus);
void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
int ddrphy_training(struct ddrphy __iomem *phy);
#endif
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <asm/processor.h>
+
+#include "../init.h"
+#include "ddrphy-regs.h"
+#include "umc-regs.h"
+
+#define DRAM_CH_NR 2
+
+enum dram_freq {
+ DRAM_FREQ_1333M,
+ DRAM_FREQ_1600M,
+ DRAM_FREQ_NR,
+};
+
+enum dram_size {
+ DRAM_SZ_128M,
+ DRAM_SZ_256M,
+ DRAM_SZ_NR,
+};
+
+static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x36bb0f17};
+static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6aa24};
+static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+ {0x00240512, 0x00350512},
+ {0x002b0617, 0x003f0617},
+};
+static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
+static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ae};
+
+static int umc_get_rank(int ch)
+{
+ return ch; /* ch0: rank0, ch1: rank1 for this SoC */
+}
+
+static void umc_start_ssif(void __iomem *ssif_base)
+{
+ writel(0x00000000, ssif_base + 0x0000b004);
+ writel(0xffffffff, ssif_base + 0x0000c004);
+ writel(0x000fffcf, ssif_base + 0x0000c008);
+ writel(0x00000001, ssif_base + 0x0000b000);
+ writel(0x00000001, ssif_base + 0x0000c000);
+ writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+ writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+
+ writel(0x00000001, ssif_base + UMC_CPURST);
+ writel(0x00000001, ssif_base + UMC_IDSRST);
+ writel(0x00000001, ssif_base + UMC_IXMRST);
+ writel(0x00000001, ssif_base + UMC_MDMRST);
+ writel(0x00000001, ssif_base + UMC_MDDRST);
+ writel(0x00000001, ssif_base + UMC_SIORST);
+ writel(0x00000001, ssif_base + UMC_VIORST);
+ writel(0x00000001, ssif_base + UMC_FRCRST);
+ writel(0x00000001, ssif_base + UMC_RGLRST);
+ writel(0x00000001, ssif_base + UMC_AIORST);
+ writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
+ int freq, unsigned long size, bool ddr3plus)
+{
+ enum dram_freq freq_e;
+ enum dram_size size_e;
+
+ if (!ddr3plus) {
+ pr_err("DDR3 standard is not supported\n");
+ return -EINVAL;
+ }
+
+ switch (freq) {
+ case 1333:
+ freq_e = DRAM_FREQ_1333M;
+ break;
+ case 1600:
+ freq_e = DRAM_FREQ_1600M;
+ break;
+ default:
+ pr_err("unsupported DRAM frequency %d MHz\n", freq);
+ return -EINVAL;
+ }
+
+ switch (size) {
+ case 0:
+ return 0;
+ case SZ_128M:
+ size_e = DRAM_SZ_128M;
+ break;
+ case SZ_256M:
+ size_e = DRAM_SZ_256M;
+ break;
+ default:
+ pr_err("unsupported DRAM size 0x%08lx\n", size);
+ return -EINVAL;
+ }
+
+ writel(umc_cmdctla_plus[freq_e], dc_base + UMC_CMDCTLA);
+ writel(umc_cmdctlb_plus[freq_e], dc_base + UMC_CMDCTLB);
+ writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA);
+ writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB);
+ writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
+ writel(0x04060806, dc_base + UMC_WDATACTL_D0);
+ writel(0x04a02000, dc_base + UMC_DATASET);
+ writel(0x00000000, ca_base + 0x2300);
+ writel(0x00400020, dc_base + UMC_DCCGCTL);
+ writel(0x00000003, dc_base + 0x7000);
+ writel(0x0000000f, dc_base + 0x8000);
+ writel(0x000000c3, dc_base + 0x8004);
+ writel(0x00000071, dc_base + 0x8008);
+ writel(0x0000003b, dc_base + UMC_DICGCTLA);
+ writel(0x020a0808, dc_base + UMC_DICGCTLB);
+ writel(0x00000004, dc_base + UMC_FLOWCTLG);
+ writel(0x80000201, ca_base + 0xc20);
+ writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
+ writel(0x00200000, dc_base + UMC_FLOWCTLB);
+ writel(0x00004444, dc_base + UMC_FLOWCTLC);
+ writel(0x200a0a00, dc_base + UMC_SPCSETB);
+ writel(0x00000000, dc_base + UMC_SPCSETD);
+ writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
+
+ return 0;
+}
+
+static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
+ int freq, unsigned long size, bool ddr3plus, int ch)
+{
+ void __iomem *phy_base = dc_base + 0x00001000;
+ int ret;
+
+ writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
+ while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
+ cpu_relax();
+
+ writel(0x00000101, dc_base + UMC_DIOCTLA);
+
+ ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
+ if (ret)
+ return ret;
+
+ ddrphy_prepare_training(phy_base, umc_get_rank(ch));
+ ret = ddrphy_training(phy_base);
+ if (ret)
+ return ret;
+
+ return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
+}
+
+int uniphier_ld4_umc_init(const struct uniphier_board_data *bd)
+{
+ void __iomem *umc_base = (void __iomem *)0x5b800000;
+ void __iomem *ca_base = umc_base + 0x00001000;
+ void __iomem *dc_base = umc_base + 0x00400000;
+ void __iomem *ssif_base = umc_base;
+ int ch, ret;
+
+ for (ch = 0; ch < DRAM_CH_NR; ch++) {
+ ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
+ bd->dram_ch[ch].size,
+ bd->dram_ddr3plus, ch);
+ if (ret) {
+ pr_err("failed to initialize UMC ch%d\n", ch);
+ return ret;
+ }
+
+ ca_base += 0x00001000;
+ dc_base += 0x00200000;
+ }
+
+ umc_start_ssif(ssif_base);
+
+ return 0;
+}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-#include <asm/processor.h>
-
-#include "../init.h"
-#include "ddrphy-regs.h"
-#include "umc-regs.h"
-
-#define DRAM_CH_NR 2
-
-enum dram_freq {
- DRAM_FREQ_1333M,
- DRAM_FREQ_1600M,
- DRAM_FREQ_NR,
-};
-
-enum dram_size {
- DRAM_SZ_128M,
- DRAM_SZ_256M,
- DRAM_SZ_NR,
-};
-
-static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x36bb0f17};
-static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6aa24};
-static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
- {0x00240512, 0x00350512},
- {0x002b0617, 0x003f0617},
-};
-static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
-static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ae};
-
-static int umc_get_rank(int ch)
-{
- return ch; /* ch0: rank0, ch1: rank1 for this SoC */
-}
-
-static void umc_start_ssif(void __iomem *ssif_base)
-{
- writel(0x00000000, ssif_base + 0x0000b004);
- writel(0xffffffff, ssif_base + 0x0000c004);
- writel(0x000fffcf, ssif_base + 0x0000c008);
- writel(0x00000001, ssif_base + 0x0000b000);
- writel(0x00000001, ssif_base + 0x0000c000);
- writel(0x03010101, ssif_base + UMC_MDMCHSEL);
- writel(0x03010100, ssif_base + UMC_DMDCHSEL);
-
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
-
- writel(0x00000001, ssif_base + UMC_CPURST);
- writel(0x00000001, ssif_base + UMC_IDSRST);
- writel(0x00000001, ssif_base + UMC_IXMRST);
- writel(0x00000001, ssif_base + UMC_MDMRST);
- writel(0x00000001, ssif_base + UMC_MDDRST);
- writel(0x00000001, ssif_base + UMC_SIORST);
- writel(0x00000001, ssif_base + UMC_VIORST);
- writel(0x00000001, ssif_base + UMC_FRCRST);
- writel(0x00000001, ssif_base + UMC_RGLRST);
- writel(0x00000001, ssif_base + UMC_AIORST);
- writel(0x00000001, ssif_base + UMC_DMDRST);
-}
-
-static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
- int freq, unsigned long size, bool ddr3plus)
-{
- enum dram_freq freq_e;
- enum dram_size size_e;
-
- if (!ddr3plus) {
- pr_err("DDR3 standard is not supported\n");
- return -EINVAL;
- }
-
- switch (freq) {
- case 1333:
- freq_e = DRAM_FREQ_1333M;
- break;
- case 1600:
- freq_e = DRAM_FREQ_1600M;
- break;
- default:
- pr_err("unsupported DRAM frequency %d MHz\n", freq);
- return -EINVAL;
- }
-
- switch (size) {
- case 0:
- return 0;
- case SZ_128M:
- size_e = DRAM_SZ_128M;
- break;
- case SZ_256M:
- size_e = DRAM_SZ_256M;
- break;
- default:
- pr_err("unsupported DRAM size 0x%08lx\n", size);
- return -EINVAL;
- }
-
- writel(umc_cmdctla_plus[freq_e], dc_base + UMC_CMDCTLA);
- writel(umc_cmdctlb_plus[freq_e], dc_base + UMC_CMDCTLB);
- writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA);
- writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB);
- writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
- writel(0x04060806, dc_base + UMC_WDATACTL_D0);
- writel(0x04a02000, dc_base + UMC_DATASET);
- writel(0x00000000, ca_base + 0x2300);
- writel(0x00400020, dc_base + UMC_DCCGCTL);
- writel(0x00000003, dc_base + 0x7000);
- writel(0x0000000f, dc_base + 0x8000);
- writel(0x000000c3, dc_base + 0x8004);
- writel(0x00000071, dc_base + 0x8008);
- writel(0x0000003b, dc_base + UMC_DICGCTLA);
- writel(0x020a0808, dc_base + UMC_DICGCTLB);
- writel(0x00000004, dc_base + UMC_FLOWCTLG);
- writel(0x80000201, ca_base + 0xc20);
- writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
- writel(0x00200000, dc_base + UMC_FLOWCTLB);
- writel(0x00004444, dc_base + UMC_FLOWCTLC);
- writel(0x200a0a00, dc_base + UMC_SPCSETB);
- writel(0x00000000, dc_base + UMC_SPCSETD);
- writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
-
- return 0;
-}
-
-static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
- int freq, unsigned long size, bool ddr3plus, int ch)
-{
- void __iomem *phy_base = dc_base + 0x00001000;
- int ret;
-
- writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
- while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
- cpu_relax();
-
- writel(0x00000101, dc_base + UMC_DIOCTLA);
-
- ret = ph1_ld4_ddrphy_init(phy_base, freq, ddr3plus);
- if (ret)
- return ret;
-
- ddrphy_prepare_training(phy_base, umc_get_rank(ch));
- ret = ddrphy_training(phy_base);
- if (ret)
- return ret;
-
- return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
-}
-
-int ph1_ld4_umc_init(const struct uniphier_board_data *bd)
-{
- void __iomem *umc_base = (void __iomem *)0x5b800000;
- void __iomem *ca_base = umc_base + 0x00001000;
- void __iomem *dc_base = umc_base + 0x00400000;
- void __iomem *ssif_base = umc_base;
- int ch, ret;
-
- for (ch = 0; ch < DRAM_CH_NR; ch++) {
- ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
- bd->dram_ch[ch].size,
- bd->dram_ddr3plus, ch);
- if (ret) {
- pr_err("failed to initialize UMC ch%d\n", ch);
- return ret;
- }
-
- ca_base += 0x00001000;
- dc_base += 0x00200000;
- }
-
- umc_start_ssif(ssif_base);
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-#include <asm/processor.h>
-
-#include "../init.h"
-#include "ddrphy-regs.h"
-#include "umc-regs.h"
-
-#define DRAM_CH_NR 2
-
-enum dram_size {
- DRAM_SZ_128M,
- DRAM_SZ_256M,
- DRAM_SZ_512M,
- DRAM_SZ_NR,
-};
-
-static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617};
-
-static void umc_start_ssif(void __iomem *ssif_base)
-{
- writel(0x00000000, ssif_base + 0x0000b004);
- writel(0xffffffff, ssif_base + 0x0000c004);
- writel(0x000fffcf, ssif_base + 0x0000c008);
- writel(0x00000001, ssif_base + 0x0000b000);
- writel(0x00000001, ssif_base + 0x0000c000);
-
- writel(0x03010100, ssif_base + UMC_HDMCHSEL);
- writel(0x03010101, ssif_base + UMC_MDMCHSEL);
- writel(0x03010100, ssif_base + UMC_DVCCHSEL);
- writel(0x03010100, ssif_base + UMC_DMDCHSEL);
-
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
- writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */
-
- writel(0x00000001, ssif_base + UMC_CPURST);
- writel(0x00000001, ssif_base + UMC_IDSRST);
- writel(0x00000001, ssif_base + UMC_IXMRST);
- writel(0x00000001, ssif_base + UMC_HDMRST);
- writel(0x00000001, ssif_base + UMC_MDMRST);
- writel(0x00000001, ssif_base + UMC_HDDRST);
- writel(0x00000001, ssif_base + UMC_MDDRST);
- writel(0x00000001, ssif_base + UMC_SIORST);
- writel(0x00000001, ssif_base + UMC_GIORST);
- writel(0x00000001, ssif_base + UMC_HD2RST);
- writel(0x00000001, ssif_base + UMC_VIORST);
- writel(0x00000001, ssif_base + UMC_DVCRST);
- writel(0x00000001, ssif_base + UMC_RGLRST);
- writel(0x00000001, ssif_base + UMC_VPERST);
- writel(0x00000001, ssif_base + UMC_AIORST);
- writel(0x00000001, ssif_base + UMC_DMDRST);
-}
-
-static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
- int freq, unsigned long size, bool ddr3plus)
-{
- enum dram_size size_e;
-
- if (freq != 1600) {
- pr_err("Unsupported DDR frequency %d MHz\n", freq);
- return -EINVAL;
- }
-
- if (ddr3plus) {
- pr_err("DDR3+ is not supported\n");
- return -EINVAL;
- }
-
- switch (size) {
- case SZ_128M:
- size_e = DRAM_SZ_128M;
- break;
- case SZ_256M:
- size_e = DRAM_SZ_256M;
- break;
- case SZ_512M:
- size_e = DRAM_SZ_512M;
- break;
- default:
- pr_err("unsupported DRAM size 0x%08lx (per 16bit)\n", size);
- return -EINVAL;
- }
-
- writel(0x66bb0f17, dc_base + UMC_CMDCTLA);
- writel(0x18c6aa44, dc_base + UMC_CMDCTLB);
- writel(umc_spcctla[size_e], dc_base + UMC_SPCCTLA);
- writel(0x00ff0008, dc_base + UMC_SPCCTLB);
- writel(0x000c00ae, dc_base + UMC_RDATACTL_D0);
- writel(0x000c00ae, dc_base + UMC_RDATACTL_D1);
- writel(0x04060802, dc_base + UMC_WDATACTL_D0);
- writel(0x04060802, dc_base + UMC_WDATACTL_D1);
- writel(0x04a02000, dc_base + UMC_DATASET);
- writel(0x00000000, ca_base + 0x2300);
- writel(0x00400020, dc_base + UMC_DCCGCTL);
- writel(0x0000000f, dc_base + 0x7000);
- writel(0x0000000f, dc_base + 0x8000);
- writel(0x000000c3, dc_base + 0x8004);
- writel(0x00000071, dc_base + 0x8008);
- writel(0x00000004, dc_base + UMC_FLOWCTLG);
- writel(0x00000000, dc_base + 0x0060);
- writel(0x80000201, ca_base + 0xc20);
- writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
- writel(0x00200000, dc_base + UMC_FLOWCTLB);
- writel(0x00004444, dc_base + UMC_FLOWCTLC);
- writel(0x200a0a00, dc_base + UMC_SPCSETB);
- writel(0x00010000, dc_base + UMC_SPCSETD);
- writel(0x80000020, dc_base + UMC_DFICUPDCTLA);
-
- return 0;
-}
-
-static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
- int freq, unsigned long size, unsigned int width,
- bool ddr3plus)
-{
- void __iomem *phy_base = dc_base + 0x00001000;
- int nr_phy = width / 16;
- int phy, ret;
-
- writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
- while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
- cpu_relax();
-
- for (phy = 0; phy < nr_phy; phy++) {
- writel(0x00000100 | ((1 << (phy + 1)) - 1),
- dc_base + UMC_DIOCTLA);
-
- ret = ph1_ld4_ddrphy_init(phy_base, freq, ddr3plus);
- if (ret)
- return ret;
-
- ddrphy_prepare_training(phy_base, phy);
- ret = ddrphy_training(phy_base);
- if (ret)
- return ret;
-
- phy_base += 0x00001000;
- }
-
- return umc_dramcont_init(dc_base, ca_base, freq, size / (width / 16),
- ddr3plus);
-}
-
-int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
-{
- void __iomem *umc_base = (void __iomem *)0x5b800000;
- void __iomem *ca_base = umc_base + 0x00001000;
- void __iomem *dc_base = umc_base + 0x00400000;
- void __iomem *ssif_base = umc_base;
- int ch, ret;
-
- for (ch = 0; ch < DRAM_CH_NR; ch++) {
- ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
- bd->dram_ch[ch].size,
- bd->dram_ch[ch].width,
- bd->dram_ddr3plus);
- if (ret) {
- pr_err("failed to initialize UMC ch%d\n", ch);
- return ret;
- }
-
- ca_base += 0x00001000;
- dc_base += 0x00200000;
- }
-
- umc_start_ssif(ssif_base);
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-#include <asm/processor.h>
-
-#include "../init.h"
-#include "ddrphy-regs.h"
-#include "umc-regs.h"
-
-#define DRAM_CH_NR 2
-
-enum dram_freq {
- DRAM_FREQ_1333M,
- DRAM_FREQ_1600M,
- DRAM_FREQ_NR,
-};
-
-enum dram_size {
- DRAM_SZ_128M,
- DRAM_SZ_256M,
- DRAM_SZ_512M,
- DRAM_SZ_NR,
-};
-
-static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x55990b11, 0x66bb0f17};
-static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x46bb0f17};
-static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x16958944, 0x18c6ab44};
-static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6ab24};
-static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
- {0x00240512, 0x00350512, 0x00000000}, /* no data for 1333MHz,128MB */
- {0x002b0617, 0x003f0617, 0x00670617},
-};
-static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
-static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ac};
-
-static int umc_get_rank(int ch)
-{
- return ch; /* ch0: rank0, ch1: rank1 for this SoC */
-}
-
-static void umc_start_ssif(void __iomem *ssif_base)
-{
- writel(0x00000000, ssif_base + 0x0000b004);
- writel(0xffffffff, ssif_base + 0x0000c004);
- writel(0x000fffcf, ssif_base + 0x0000c008);
- writel(0x00000001, ssif_base + 0x0000b000);
- writel(0x00000001, ssif_base + 0x0000c000);
- writel(0x03010101, ssif_base + UMC_MDMCHSEL);
- writel(0x03010100, ssif_base + UMC_DMDCHSEL);
-
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
-
- writel(0x00000001, ssif_base + UMC_CPURST);
- writel(0x00000001, ssif_base + UMC_IDSRST);
- writel(0x00000001, ssif_base + UMC_IXMRST);
- writel(0x00000001, ssif_base + UMC_MDMRST);
- writel(0x00000001, ssif_base + UMC_MDDRST);
- writel(0x00000001, ssif_base + UMC_SIORST);
- writel(0x00000001, ssif_base + UMC_VIORST);
- writel(0x00000001, ssif_base + UMC_FRCRST);
- writel(0x00000001, ssif_base + UMC_RGLRST);
- writel(0x00000001, ssif_base + UMC_AIORST);
- writel(0x00000001, ssif_base + UMC_DMDRST);
-}
-
-static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
- int freq, unsigned long size, bool ddr3plus)
-{
- enum dram_freq freq_e;
- enum dram_size size_e;
-
- switch (freq) {
- case 1333:
- freq_e = DRAM_FREQ_1333M;
- break;
- case 1600:
- freq_e = DRAM_FREQ_1600M;
- break;
- default:
- pr_err("unsupported DRAM frequency %d MHz\n", freq);
- return -EINVAL;
- }
-
- switch (size) {
- case 0:
- return 0;
- case SZ_128M:
- size_e = DRAM_SZ_128M;
- break;
- case SZ_256M:
- size_e = DRAM_SZ_256M;
- break;
- case SZ_512M:
- size_e = DRAM_SZ_512M;
- break;
- default:
- pr_err("unsupported DRAM size 0x%08lx\n", size);
- return -EINVAL;
- }
-
- writel((ddr3plus ? umc_cmdctla_plus : umc_cmdctla)[freq_e],
- dc_base + UMC_CMDCTLA);
- writel((ddr3plus ? umc_cmdctlb_plus : umc_cmdctlb)[freq_e],
- dc_base + UMC_CMDCTLB);
- writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA);
- writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB);
- writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
- writel(0x04060806, dc_base + UMC_WDATACTL_D0);
- writel(0x04a02000, dc_base + UMC_DATASET);
- writel(0x00000000, ca_base + 0x2300);
- writel(0x00400020, dc_base + UMC_DCCGCTL);
- writel(0x00000003, dc_base + 0x7000);
- writel(0x0000004f, dc_base + 0x8000);
- writel(0x000000c3, dc_base + 0x8004);
- writel(0x00000077, dc_base + 0x8008);
- writel(0x0000003b, dc_base + UMC_DICGCTLA);
- writel(0x020a0808, dc_base + UMC_DICGCTLB);
- writel(0x00000004, dc_base + UMC_FLOWCTLG);
- writel(0x80000201, ca_base + 0xc20);
- writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
- writel(0x00200000, dc_base + UMC_FLOWCTLB);
- writel(0x00004444, dc_base + UMC_FLOWCTLC);
- writel(0x200a0a00, dc_base + UMC_SPCSETB);
- writel(0x00000000, dc_base + UMC_SPCSETD);
- writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
-
- return 0;
-}
-
-static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
- int freq, unsigned long size, bool ddr3plus, int ch)
-{
- void __iomem *phy_base = dc_base + 0x00001000;
- int ret;
-
- writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
- while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
- cpu_relax();
-
- writel(0x00000101, dc_base + UMC_DIOCTLA);
-
- ret = ph1_ld4_ddrphy_init(phy_base, freq, ddr3plus);
- if (ret)
- return ret;
-
- ddrphy_prepare_training(phy_base, umc_get_rank(ch));
- ret = ddrphy_training(phy_base);
- if (ret)
- return ret;
-
- return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
-}
-
-int ph1_sld8_umc_init(const struct uniphier_board_data *bd)
-{
- void __iomem *umc_base = (void __iomem *)0x5b800000;
- void __iomem *ca_base = umc_base + 0x00001000;
- void __iomem *dc_base = umc_base + 0x00400000;
- void __iomem *ssif_base = umc_base;
- int ch, ret;
-
- for (ch = 0; ch < DRAM_CH_NR; ch++) {
- ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
- bd->dram_ch[ch].size,
- bd->dram_ddr3plus, ch);
- if (ret) {
- pr_err("failed to initialize UMC ch%d\n", ch);
- return ret;
- }
-
- ca_base += 0x00001000;
- dc_base += 0x00200000;
- }
-
- umc_start_ssif(ssif_base);
-
- return 0;
-}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <asm/processor.h>
+
+#include "../init.h"
+#include "ddrphy-regs.h"
+#include "umc-regs.h"
+
+#define DRAM_CH_NR 2
+
+enum dram_size {
+ DRAM_SZ_128M,
+ DRAM_SZ_256M,
+ DRAM_SZ_512M,
+ DRAM_SZ_NR,
+};
+
+static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617};
+
+static void umc_start_ssif(void __iomem *ssif_base)
+{
+ writel(0x00000000, ssif_base + 0x0000b004);
+ writel(0xffffffff, ssif_base + 0x0000c004);
+ writel(0x000fffcf, ssif_base + 0x0000c008);
+ writel(0x00000001, ssif_base + 0x0000b000);
+ writel(0x00000001, ssif_base + 0x0000c000);
+
+ writel(0x03010100, ssif_base + UMC_HDMCHSEL);
+ writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+ writel(0x03010100, ssif_base + UMC_DVCCHSEL);
+ writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+ writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */
+
+ writel(0x00000001, ssif_base + UMC_CPURST);
+ writel(0x00000001, ssif_base + UMC_IDSRST);
+ writel(0x00000001, ssif_base + UMC_IXMRST);
+ writel(0x00000001, ssif_base + UMC_HDMRST);
+ writel(0x00000001, ssif_base + UMC_MDMRST);
+ writel(0x00000001, ssif_base + UMC_HDDRST);
+ writel(0x00000001, ssif_base + UMC_MDDRST);
+ writel(0x00000001, ssif_base + UMC_SIORST);
+ writel(0x00000001, ssif_base + UMC_GIORST);
+ writel(0x00000001, ssif_base + UMC_HD2RST);
+ writel(0x00000001, ssif_base + UMC_VIORST);
+ writel(0x00000001, ssif_base + UMC_DVCRST);
+ writel(0x00000001, ssif_base + UMC_RGLRST);
+ writel(0x00000001, ssif_base + UMC_VPERST);
+ writel(0x00000001, ssif_base + UMC_AIORST);
+ writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
+ int freq, unsigned long size, bool ddr3plus)
+{
+ enum dram_size size_e;
+
+ if (freq != 1600) {
+ pr_err("Unsupported DDR frequency %d MHz\n", freq);
+ return -EINVAL;
+ }
+
+ if (ddr3plus) {
+ pr_err("DDR3+ is not supported\n");
+ return -EINVAL;
+ }
+
+ switch (size) {
+ case SZ_128M:
+ size_e = DRAM_SZ_128M;
+ break;
+ case SZ_256M:
+ size_e = DRAM_SZ_256M;
+ break;
+ case SZ_512M:
+ size_e = DRAM_SZ_512M;
+ break;
+ default:
+ pr_err("unsupported DRAM size 0x%08lx (per 16bit)\n", size);
+ return -EINVAL;
+ }
+
+ writel(0x66bb0f17, dc_base + UMC_CMDCTLA);
+ writel(0x18c6aa44, dc_base + UMC_CMDCTLB);
+ writel(umc_spcctla[size_e], dc_base + UMC_SPCCTLA);
+ writel(0x00ff0008, dc_base + UMC_SPCCTLB);
+ writel(0x000c00ae, dc_base + UMC_RDATACTL_D0);
+ writel(0x000c00ae, dc_base + UMC_RDATACTL_D1);
+ writel(0x04060802, dc_base + UMC_WDATACTL_D0);
+ writel(0x04060802, dc_base + UMC_WDATACTL_D1);
+ writel(0x04a02000, dc_base + UMC_DATASET);
+ writel(0x00000000, ca_base + 0x2300);
+ writel(0x00400020, dc_base + UMC_DCCGCTL);
+ writel(0x0000000f, dc_base + 0x7000);
+ writel(0x0000000f, dc_base + 0x8000);
+ writel(0x000000c3, dc_base + 0x8004);
+ writel(0x00000071, dc_base + 0x8008);
+ writel(0x00000004, dc_base + UMC_FLOWCTLG);
+ writel(0x00000000, dc_base + 0x0060);
+ writel(0x80000201, ca_base + 0xc20);
+ writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
+ writel(0x00200000, dc_base + UMC_FLOWCTLB);
+ writel(0x00004444, dc_base + UMC_FLOWCTLC);
+ writel(0x200a0a00, dc_base + UMC_SPCSETB);
+ writel(0x00010000, dc_base + UMC_SPCSETD);
+ writel(0x80000020, dc_base + UMC_DFICUPDCTLA);
+
+ return 0;
+}
+
+static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
+ int freq, unsigned long size, unsigned int width,
+ bool ddr3plus)
+{
+ void __iomem *phy_base = dc_base + 0x00001000;
+ int nr_phy = width / 16;
+ int phy, ret;
+
+ writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
+ while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
+ cpu_relax();
+
+ for (phy = 0; phy < nr_phy; phy++) {
+ writel(0x00000100 | ((1 << (phy + 1)) - 1),
+ dc_base + UMC_DIOCTLA);
+
+ ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
+ if (ret)
+ return ret;
+
+ ddrphy_prepare_training(phy_base, phy);
+ ret = ddrphy_training(phy_base);
+ if (ret)
+ return ret;
+
+ phy_base += 0x00001000;
+ }
+
+ return umc_dramcont_init(dc_base, ca_base, freq, size / (width / 16),
+ ddr3plus);
+}
+
+int uniphier_pro4_umc_init(const struct uniphier_board_data *bd)
+{
+ void __iomem *umc_base = (void __iomem *)0x5b800000;
+ void __iomem *ca_base = umc_base + 0x00001000;
+ void __iomem *dc_base = umc_base + 0x00400000;
+ void __iomem *ssif_base = umc_base;
+ int ch, ret;
+
+ for (ch = 0; ch < DRAM_CH_NR; ch++) {
+ ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
+ bd->dram_ch[ch].size,
+ bd->dram_ch[ch].width,
+ bd->dram_ddr3plus);
+ if (ret) {
+ pr_err("failed to initialize UMC ch%d\n", ch);
+ return ret;
+ }
+
+ ca_base += 0x00001000;
+ dc_base += 0x00200000;
+ }
+
+ umc_start_ssif(ssif_base);
+
+ return 0;
+}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * based on commit 21b6e480f92ccc38fe0502e3116411d6509d3bf2 of Diag by:
- * Copyright (C) 2015 Socionext Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-#include <asm/processor.h>
-
-#include "../init.h"
-#include "../soc-info.h"
-#include "ddrmphy-regs.h"
-#include "umc-regs.h"
-
-#define DRAM_CH_NR 3
-
-enum dram_freq {
- DRAM_FREQ_1866M,
- DRAM_FREQ_2133M,
- DRAM_FREQ_NR,
-};
-
-enum dram_size {
- DRAM_SZ_256M,
- DRAM_SZ_512M,
- DRAM_SZ_NR,
-};
-
-static u32 ddrphy_pgcr2[DRAM_FREQ_NR] = {0x00FC7E5D, 0x00FC90AB};
-static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0EA09205, 0x10C0A6C6};
-static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x0DAC041B, 0x0FA104B1};
-static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x15171e45, 0x18182357};
-static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x0e9ad8e9, 0x10b34157};
-static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x35a00d88, 0x39e40e88};
-static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x2288cc2c, 0x228a04d0};
-static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x50005e00, 0x50006a00};
-static u32 ddrphy_dtpr3[DRAM_FREQ_NR] = {0x0010cb49, 0x0010ec89};
-static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000115, 0x00000125};
-static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x000002a0, 0x000002a8};
-
-/* dependent on package and board design */
-static u32 ddrphy_acbdlr0[DRAM_CH_NR] = {0x0000000c, 0x0000000c, 0x00000009};
-
-static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x66DD131D, 0x77EE1722};
-/*
- * The ch2 is a different generation UMC core.
- * The register spec is different, unfortunately.
- */
-static u32 umc_cmdctlb_ch01[DRAM_FREQ_NR] = {0x13E87C44, 0x18F88C44};
-static u32 umc_cmdctlb_ch2[DRAM_FREQ_NR] = {0x19E8DC44, 0x1EF8EC44};
-static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
- {0x004A071D, 0x0078071D},
- {0x0055081E, 0x0089081E},
-};
-
-static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B};
-/* The ch2 is different for some reason only hardware guys know... */
-static u32 umc_flowctla_ch01[] = {0x0800001E, 0x08000022};
-static u32 umc_flowctla_ch2[] = {0x0800001E, 0x0800001E};
-
-/* DDR multiPHY */
-static inline int ddrphy_get_rank(int dx)
-{
- return dx / 2;
-}
-
-static void ddrphy_fifo_reset(void __iomem *phy_base)
-{
- u32 tmp;
-
- tmp = readl(phy_base + DMPHY_PGCR0);
- tmp &= ~DMPHY_PGCR0_PHYFRST;
- writel(tmp, phy_base + DMPHY_PGCR0);
-
- udelay(1);
-
- tmp |= DMPHY_PGCR0_PHYFRST;
- writel(tmp, phy_base + DMPHY_PGCR0);
-
- udelay(1);
-}
-
-static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)
-{
- u32 tmp;
-
- tmp = readl(phy_base + DMPHY_PGCR1);
-
- if (enable)
- tmp &= ~DMPHY_PGCR1_INHVT;
- else
- tmp |= DMPHY_PGCR1_INHVT;
-
- writel(tmp, phy_base + DMPHY_PGCR1);
-
- if (!enable) {
- while (!(readl(phy_base + DMPHY_PGSR1) & DMPHY_PGSR1_VTSTOP))
- cpu_relax();
- }
-}
-
-static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step)
-{
- int dx;
- u32 lcdlr1, rdqsd;
- void __iomem *dx_base = phy_base + DMPHY_DX_BASE;
-
- ddrphy_vt_ctrl(phy_base, 0);
-
- for (dx = 0; dx < nr_dx; dx++) {
- lcdlr1 = readl(dx_base + DMPHY_DX_LCDLR1);
- rdqsd = (lcdlr1 >> 8) & 0xff;
- rdqsd = clamp(rdqsd + step, 0U, 0xffU);
- lcdlr1 = (lcdlr1 & ~(0xff << 8)) | (rdqsd << 8);
- writel(lcdlr1, dx_base + DMPHY_DX_LCDLR1);
- readl(dx_base + DMPHY_DX_LCDLR1); /* relax */
- dx_base += DMPHY_DX_STRIDE;
- }
-
- ddrphy_vt_ctrl(phy_base, 1);
-}
-
-static int ddrphy_get_system_latency(void __iomem *phy_base, int width)
-{
- void __iomem *dx_base = phy_base + DMPHY_DX_BASE;
- const int nr_dx = width / 8;
- int dx, rank;
- u32 gtr;
- int dgsl, dgsl_min = INT_MAX, dgsl_max = 0;
-
- for (dx = 0; dx < nr_dx; dx++) {
- gtr = readl(dx_base + DMPHY_DX_GTR);
- for (rank = 0; rank < 4; rank++) {
- dgsl = gtr & 0x7;
- /* if dgsl is zero, this rank was not trained. skip. */
- if (dgsl) {
- dgsl_min = min(dgsl_min, dgsl);
- dgsl_max = max(dgsl_max, dgsl);
- }
- gtr >>= 3;
- }
- dx_base += DMPHY_DX_STRIDE;
- }
-
- if (dgsl_min != dgsl_max)
- printf("DQS Gateing System Latencies are not all leveled.\n");
-
- return dgsl_max;
-}
-
-static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width,
- int ch)
-{
- u32 tmp;
- void __iomem *zq_base, *dx_base;
- int zq, dx;
- int nr_dx;
-
- nr_dx = width / 8;
-
- writel(DMPHY_PIR_ZCALBYP, phy_base + DMPHY_PIR);
- /*
- * Disable RGLVT bit (Read DQS Gating LCDL Delay VT Compensation)
- * to avoid read error issue.
- */
- writel(0x07d81e37, phy_base + DMPHY_PGCR0);
- writel(0x0200c4e0, phy_base + DMPHY_PGCR1);
-
- tmp = ddrphy_pgcr2[freq];
- if (width >= 32)
- tmp |= DMPHY_PGCR2_DUALCHN | DMPHY_PGCR2_ACPDDC;
- writel(tmp, phy_base + DMPHY_PGCR2);
-
- writel(ddrphy_ptr0[freq], phy_base + DMPHY_PTR0);
- writel(ddrphy_ptr1[freq], phy_base + DMPHY_PTR1);
- writel(0x00083def, phy_base + DMPHY_PTR2);
- writel(ddrphy_ptr3[freq], phy_base + DMPHY_PTR3);
- writel(ddrphy_ptr4[freq], phy_base + DMPHY_PTR4);
-
- writel(ddrphy_acbdlr0[ch], phy_base + DMPHY_ACBDLR0);
-
- writel(0x55555555, phy_base + DMPHY_ACIOCR1);
- writel(0x00000000, phy_base + DMPHY_ACIOCR2);
- writel(0x55555555, phy_base + DMPHY_ACIOCR3);
- writel(0x00000000, phy_base + DMPHY_ACIOCR4);
- writel(0x00000055, phy_base + DMPHY_ACIOCR5);
- writel(0x00181aa4, phy_base + DMPHY_DXCCR);
-
- writel(0x0024641e, phy_base + DMPHY_DSGCR);
- writel(0x0000040b, phy_base + DMPHY_DCR);
- writel(ddrphy_dtpr0[freq], phy_base + DMPHY_DTPR0);
- writel(ddrphy_dtpr1[freq], phy_base + DMPHY_DTPR1);
- writel(ddrphy_dtpr2[freq], phy_base + DMPHY_DTPR2);
- writel(ddrphy_dtpr3[freq], phy_base + DMPHY_DTPR3);
- writel(ddrphy_mr0[freq], phy_base + DMPHY_MR0);
- writel(0x00000006, phy_base + DMPHY_MR1);
- writel(ddrphy_mr2[freq], phy_base + DMPHY_MR2);
- writel(0x00000000, phy_base + DMPHY_MR3);
-
- tmp = 0;
- for (dx = 0; dx < nr_dx; dx++)
- tmp |= BIT(DMPHY_DTCR_RANKEN_SHIFT + ddrphy_get_rank(dx));
- writel(0x90003087 | tmp, phy_base + DMPHY_DTCR);
-
- writel(0x00000000, phy_base + DMPHY_DTAR0);
- writel(0x00000008, phy_base + DMPHY_DTAR1);
- writel(0x00000010, phy_base + DMPHY_DTAR2);
- writel(0x00000018, phy_base + DMPHY_DTAR3);
- writel(0xdd22ee11, phy_base + DMPHY_DTDR0);
- writel(0x7788bb44, phy_base + DMPHY_DTDR1);
-
- /* impedance control settings */
- writel(0x04048900, phy_base + DMPHY_ZQCR);
-
- zq_base = phy_base + DMPHY_ZQ_BASE;
- for (zq = 0; zq < 4; zq++) {
- /*
- * board-dependent
- * PXS2: CH0ZQ0=0x5B, CH1ZQ0=0x5B, CH2ZQ0=0x59, others=0x5D
- */
- writel(0x0007BB5D, zq_base + DMPHY_ZQ_PR);
- zq_base += DMPHY_ZQ_STRIDE;
- }
-
- /* DATX8 settings */
- dx_base = phy_base + DMPHY_DX_BASE;
- for (dx = 0; dx < 4; dx++) {
- tmp = readl(dx_base + DMPHY_DX_GCR0);
- tmp &= ~DMPHY_DX_GCR0_WLRKEN_MASK;
- tmp |= BIT(DMPHY_DX_GCR0_WLRKEN_SHIFT + ddrphy_get_rank(dx)) &
- DMPHY_DX_GCR0_WLRKEN_MASK;
- writel(tmp, dx_base + DMPHY_DX_GCR0);
-
- writel(0x00000000, dx_base + DMPHY_DX_GCR1);
- writel(0x00000000, dx_base + DMPHY_DX_GCR2);
- writel(0x00000000, dx_base + DMPHY_DX_GCR3);
- dx_base += DMPHY_DX_STRIDE;
- }
-
- while (!(readl(phy_base + DMPHY_PGSR0) & DMPHY_PGSR0_IDONE))
- cpu_relax();
-
- ddrphy_dqs_delay_fixup(phy_base, nr_dx, -4);
-}
-
-struct ddrphy_init_sequence {
- char *description;
- u32 init_flag;
- u32 done_flag;
- u32 err_flag;
-};
-
-static const struct ddrphy_init_sequence impedance_calibration_sequence[] = {
- {
- "Impedance Calibration",
- DMPHY_PIR_ZCAL,
- DMPHY_PGSR0_ZCDONE,
- DMPHY_PGSR0_ZCERR,
- },
- { /* sentinel */ }
-};
-
-static const struct ddrphy_init_sequence dram_init_sequence[] = {
- {
- "DRAM Initialization",
- DMPHY_PIR_DRAMRST | DMPHY_PIR_DRAMINIT,
- DMPHY_PGSR0_DIDONE,
- 0,
- },
- { /* sentinel */ }
-};
-
-static const struct ddrphy_init_sequence training_sequence[] = {
- {
- "Write Leveling",
- DMPHY_PIR_WL,
- DMPHY_PGSR0_WLDONE,
- DMPHY_PGSR0_WLERR,
- },
- {
- "Read DQS Gate Training",
- DMPHY_PIR_QSGATE,
- DMPHY_PGSR0_QSGDONE,
- DMPHY_PGSR0_QSGERR,
- },
- {
- "Write Leveling Adjustment",
- DMPHY_PIR_WLADJ,
- DMPHY_PGSR0_WLADONE,
- DMPHY_PGSR0_WLAERR,
- },
- {
- "Read Bit Deskew",
- DMPHY_PIR_RDDSKW,
- DMPHY_PGSR0_RDDONE,
- DMPHY_PGSR0_RDERR,
- },
- {
- "Write Bit Deskew",
- DMPHY_PIR_WRDSKW,
- DMPHY_PGSR0_WDDONE,
- DMPHY_PGSR0_WDERR,
- },
- {
- "Read Eye Training",
- DMPHY_PIR_RDEYE,
- DMPHY_PGSR0_REDONE,
- DMPHY_PGSR0_REERR,
- },
- {
- "Write Eye Training",
- DMPHY_PIR_WREYE,
- DMPHY_PGSR0_WEDONE,
- DMPHY_PGSR0_WEERR,
- },
- { /* sentinel */ }
-};
-
-static int __ddrphy_training(void __iomem *phy_base,
- const struct ddrphy_init_sequence *seq)
-{
- const struct ddrphy_init_sequence *s;
- u32 pgsr0;
- u32 init_flag = DMPHY_PIR_INIT;
- u32 done_flag = DMPHY_PGSR0_IDONE;
- int timeout = 50000; /* 50 msec is long enough */
-#ifdef DISPLAY_ELAPSED_TIME
- ulong start = get_timer(0);
-#endif
-
- for (s = seq; s->description; s++) {
- init_flag |= s->init_flag;
- done_flag |= s->done_flag;
- }
-
- writel(init_flag, phy_base + DMPHY_PIR);
-
- do {
- if (--timeout < 0) {
- pr_err("%s: error: timeout during DDR training\n",
- __func__);
- return -ETIMEDOUT;
- }
- udelay(1);
- pgsr0 = readl(phy_base + DMPHY_PGSR0);
- } while ((pgsr0 & done_flag) != done_flag);
-
- for (s = seq; s->description; s++) {
- if (pgsr0 & s->err_flag) {
- pr_err("%s: error: %s failed\n", __func__,
- s->description);
- return -EIO;
- }
- }
-
-#ifdef DISPLAY_ELAPSED_TIME
- printf("%s: info: elapsed time %ld msec\n", get_timer(start));
-#endif
-
- return 0;
-}
-
-static int ddrphy_impedance_calibration(void __iomem *phy_base)
-{
- int ret;
- u32 tmp;
-
- ret = __ddrphy_training(phy_base, impedance_calibration_sequence);
- if (ret)
- return ret;
-
- /*
- * Because of a hardware bug, IDONE flag is set when the first ZQ block
- * is calibrated. The flag does not guarantee the completion for all
- * the ZQ blocks. Wait a little more just in case.
- */
- udelay(1);
-
- /* reflect ZQ settings and enable average algorithm*/
- tmp = readl(phy_base + DMPHY_ZQCR);
- tmp |= DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
- writel(tmp, phy_base + DMPHY_ZQCR);
- tmp &= ~DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
- tmp |= DMPHY_ZQCR_AVGEN;
- writel(tmp, phy_base + DMPHY_ZQCR);
-
- return 0;
-}
-
-static int ddrphy_dram_init(void __iomem *phy_base)
-{
- return __ddrphy_training(phy_base, dram_init_sequence);
-}
-
-static int ddrphy_training(void __iomem *phy_base)
-{
- return __ddrphy_training(phy_base, training_sequence);
-}
-
-/* UMC */
-static void umc_set_system_latency(void __iomem *dc_base, int phy_latency)
-{
- u32 val;
- int latency;
-
- val = readl(dc_base + UMC_RDATACTL_D0);
- latency = (val & UMC_RDATACTL_RADLTY_MASK) >> UMC_RDATACTL_RADLTY_SHIFT;
- latency += (val & UMC_RDATACTL_RAD2LTY_MASK) >>
- UMC_RDATACTL_RAD2LTY_SHIFT;
- /*
- * UMC works at the half clock rate of the PHY.
- * The LSB of latency is ignored
- */
- latency += phy_latency & ~1;
-
- val &= ~(UMC_RDATACTL_RADLTY_MASK | UMC_RDATACTL_RAD2LTY_MASK);
- if (latency > 0xf) {
- val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
- val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
- } else {
- val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
- }
-
- writel(val, dc_base + UMC_RDATACTL_D0);
- writel(val, dc_base + UMC_RDATACTL_D1);
-
- readl(dc_base + UMC_RDATACTL_D1); /* relax */
-}
-
-/* enable/disable auto refresh */
-void umc_refresh_ctrl(void __iomem *dc_base, int enable)
-{
- u32 tmp;
-
- tmp = readl(dc_base + UMC_SPCSETB);
- tmp &= ~UMC_SPCSETB_AREFMD_MASK;
-
- if (enable)
- tmp |= UMC_SPCSETB_AREFMD_ARB;
- else
- tmp |= UMC_SPCSETB_AREFMD_REG;
-
- writel(tmp, dc_base + UMC_SPCSETB);
- udelay(1);
-}
-
-static void umc_ud_init(void __iomem *umc_base, int ch)
-{
- writel(0x00000003, umc_base + UMC_BITPERPIXELMODE_D0);
-
- if (ch == 2)
- writel(0x00000033, umc_base + UMC_PAIR1DOFF_D0);
-}
-
-static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
- unsigned long size, int width, int ch)
-{
- enum dram_size size_e;
- int latency;
- u32 val;
-
- switch (size) {
- case 0:
- return 0;
- case SZ_256M:
- size_e = DRAM_SZ_256M;
- break;
- case SZ_512M:
- size_e = DRAM_SZ_512M;
- break;
- default:
- pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n",
- size, ch);
- return -EINVAL;
- }
-
- writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
-
- writel(ch == 2 ? umc_cmdctlb_ch2[freq] : umc_cmdctlb_ch01[freq],
- dc_base + UMC_CMDCTLB);
-
- writel(umc_spcctla[freq][size_e], dc_base + UMC_SPCCTLA);
- writel(umc_spcctlb[freq], dc_base + UMC_SPCCTLB);
-
- val = 0x000e000e;
- latency = 12;
- /* ES2 inserted one more FF to the logic. */
- if (uniphier_get_soc_model() >= 2)
- latency += 2;
-
- if (latency > 0xf) {
- val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
- val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
- } else {
- val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
- }
-
- writel(val, dc_base + UMC_RDATACTL_D0);
- if (width >= 32)
- writel(val, dc_base + UMC_RDATACTL_D1);
-
- writel(0x04060A02, dc_base + UMC_WDATACTL_D0);
- if (width >= 32)
- writel(0x04060A02, dc_base + UMC_WDATACTL_D1);
- writel(0x04000000, dc_base + UMC_DATASET);
- writel(0x00400020, dc_base + UMC_DCCGCTL);
- writel(0x00000084, dc_base + UMC_FLOWCTLG);
- writel(0x00000000, dc_base + UMC_ACSSETA);
-
- writel(ch == 2 ? umc_flowctla_ch2[freq] : umc_flowctla_ch01[freq],
- dc_base + UMC_FLOWCTLA);
-
- writel(0x00004400, dc_base + UMC_FLOWCTLC);
- writel(0x200A0A00, dc_base + UMC_SPCSETB);
- writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
- writel(0x0000000D, dc_base + UMC_RESPCTL);
-
- if (ch != 2) {
- writel(0x00202000, dc_base + UMC_FLOWCTLB);
- writel(0xFDBFFFFF, dc_base + UMC_FLOWCTLOB0);
- writel(0xFFFFFFFF, dc_base + UMC_FLOWCTLOB1);
- writel(0x00080700, dc_base + UMC_BSICMAPSET);
- } else {
- writel(0x00200000, dc_base + UMC_FLOWCTLB);
- writel(0x00000000, dc_base + UMC_BSICMAPSET);
- }
-
- writel(0x00000000, dc_base + UMC_ERRMASKA);
- writel(0x00000000, dc_base + UMC_ERRMASKB);
-
- return 0;
-}
-
-static int umc_ch_init(void __iomem *umc_ch_base, enum dram_freq freq,
- unsigned long size, unsigned int width, int ch)
-{
- void __iomem *dc_base = umc_ch_base + 0x00011000;
- void __iomem *phy_base = umc_ch_base + 0x00030000;
- int ret;
-
- writel(0x00000002, dc_base + UMC_INITSET);
- while (readl(dc_base + UMC_INITSTAT) & BIT(2))
- cpu_relax();
-
- /* deassert PHY reset signals */
- writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
- dc_base + UMC_DIOCTLA);
-
- ddrphy_init(phy_base, freq, width, ch);
-
- ret = ddrphy_impedance_calibration(phy_base);
- if (ret)
- return ret;
-
- ddrphy_dram_init(phy_base);
- if (ret)
- return ret;
-
- ret = umc_dc_init(dc_base, freq, size, width, ch);
- if (ret)
- return ret;
-
- umc_ud_init(umc_ch_base, ch);
-
- ret = ddrphy_training(phy_base);
- if (ret)
- return ret;
-
- udelay(1);
-
- /* match the system latency between UMC and PHY */
- umc_set_system_latency(dc_base,
- ddrphy_get_system_latency(phy_base, width));
-
- udelay(1);
-
- /* stop auto refresh before clearing FIFO in PHY */
- umc_refresh_ctrl(dc_base, 0);
- ddrphy_fifo_reset(phy_base);
- umc_refresh_ctrl(dc_base, 1);
-
- udelay(10);
-
- return 0;
-}
-
-static void um_init(void __iomem *um_base)
-{
- writel(0x000000ff, um_base + UMC_MBUS0);
- writel(0x000000ff, um_base + UMC_MBUS1);
- writel(0x000000ff, um_base + UMC_MBUS2);
- writel(0x000000ff, um_base + UMC_MBUS3);
-}
-
-int proxstream2_umc_init(const struct uniphier_board_data *bd)
-{
- void __iomem *um_base = (void __iomem *)0x5b600000;
- void __iomem *umc_ch_base = (void __iomem *)0x5b800000;
- enum dram_freq freq;
- int ch, ret;
-
- switch (bd->dram_freq) {
- case 1866:
- freq = DRAM_FREQ_1866M;
- break;
- case 2133:
- freq = DRAM_FREQ_2133M;
- break;
- default:
- pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
- return -EINVAL;
- }
-
- for (ch = 0; ch < bd->dram_nr_ch; ch++) {
- unsigned long size = bd->dram_ch[ch].size;
- unsigned int width = bd->dram_ch[ch].width;
-
- ret = umc_ch_init(umc_ch_base, freq, size / (width / 16),
- width, ch);
- if (ret) {
- pr_err("failed to initialize UMC ch%d\n", ch);
- return ret;
- }
-
- umc_ch_base += 0x00200000;
- }
-
- um_init(um_base);
-
- return 0;
-}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * based on commit 21b6e480f92ccc38fe0502e3116411d6509d3bf2 of Diag by:
+ * Copyright (C) 2015 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <asm/processor.h>
+
+#include "../init.h"
+#include "../soc-info.h"
+#include "ddrmphy-regs.h"
+#include "umc-regs.h"
+
+#define DRAM_CH_NR 3
+
+enum dram_freq {
+ DRAM_FREQ_1866M,
+ DRAM_FREQ_2133M,
+ DRAM_FREQ_NR,
+};
+
+enum dram_size {
+ DRAM_SZ_256M,
+ DRAM_SZ_512M,
+ DRAM_SZ_NR,
+};
+
+static u32 ddrphy_pgcr2[DRAM_FREQ_NR] = {0x00FC7E5D, 0x00FC90AB};
+static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0EA09205, 0x10C0A6C6};
+static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x0DAC041B, 0x0FA104B1};
+static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x15171e45, 0x18182357};
+static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x0e9ad8e9, 0x10b34157};
+static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x35a00d88, 0x39e40e88};
+static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x2288cc2c, 0x228a04d0};
+static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x50005e00, 0x50006a00};
+static u32 ddrphy_dtpr3[DRAM_FREQ_NR] = {0x0010cb49, 0x0010ec89};
+static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000115, 0x00000125};
+static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x000002a0, 0x000002a8};
+
+/* dependent on package and board design */
+static u32 ddrphy_acbdlr0[DRAM_CH_NR] = {0x0000000c, 0x0000000c, 0x00000009};
+
+static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x66DD131D, 0x77EE1722};
+/*
+ * The ch2 is a different generation UMC core.
+ * The register spec is different, unfortunately.
+ */
+static u32 umc_cmdctlb_ch01[DRAM_FREQ_NR] = {0x13E87C44, 0x18F88C44};
+static u32 umc_cmdctlb_ch2[DRAM_FREQ_NR] = {0x19E8DC44, 0x1EF8EC44};
+static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+ {0x004A071D, 0x0078071D},
+ {0x0055081E, 0x0089081E},
+};
+
+static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B};
+/* The ch2 is different for some reason only hardware guys know... */
+static u32 umc_flowctla_ch01[] = {0x0800001E, 0x08000022};
+static u32 umc_flowctla_ch2[] = {0x0800001E, 0x0800001E};
+
+/* DDR multiPHY */
+static inline int ddrphy_get_rank(int dx)
+{
+ return dx / 2;
+}
+
+static void ddrphy_fifo_reset(void __iomem *phy_base)
+{
+ u32 tmp;
+
+ tmp = readl(phy_base + DMPHY_PGCR0);
+ tmp &= ~DMPHY_PGCR0_PHYFRST;
+ writel(tmp, phy_base + DMPHY_PGCR0);
+
+ udelay(1);
+
+ tmp |= DMPHY_PGCR0_PHYFRST;
+ writel(tmp, phy_base + DMPHY_PGCR0);
+
+ udelay(1);
+}
+
+static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)
+{
+ u32 tmp;
+
+ tmp = readl(phy_base + DMPHY_PGCR1);
+
+ if (enable)
+ tmp &= ~DMPHY_PGCR1_INHVT;
+ else
+ tmp |= DMPHY_PGCR1_INHVT;
+
+ writel(tmp, phy_base + DMPHY_PGCR1);
+
+ if (!enable) {
+ while (!(readl(phy_base + DMPHY_PGSR1) & DMPHY_PGSR1_VTSTOP))
+ cpu_relax();
+ }
+}
+
+static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step)
+{
+ int dx;
+ u32 lcdlr1, rdqsd;
+ void __iomem *dx_base = phy_base + DMPHY_DX_BASE;
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ for (dx = 0; dx < nr_dx; dx++) {
+ lcdlr1 = readl(dx_base + DMPHY_DX_LCDLR1);
+ rdqsd = (lcdlr1 >> 8) & 0xff;
+ rdqsd = clamp(rdqsd + step, 0U, 0xffU);
+ lcdlr1 = (lcdlr1 & ~(0xff << 8)) | (rdqsd << 8);
+ writel(lcdlr1, dx_base + DMPHY_DX_LCDLR1);
+ readl(dx_base + DMPHY_DX_LCDLR1); /* relax */
+ dx_base += DMPHY_DX_STRIDE;
+ }
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static int ddrphy_get_system_latency(void __iomem *phy_base, int width)
+{
+ void __iomem *dx_base = phy_base + DMPHY_DX_BASE;
+ const int nr_dx = width / 8;
+ int dx, rank;
+ u32 gtr;
+ int dgsl, dgsl_min = INT_MAX, dgsl_max = 0;
+
+ for (dx = 0; dx < nr_dx; dx++) {
+ gtr = readl(dx_base + DMPHY_DX_GTR);
+ for (rank = 0; rank < 4; rank++) {
+ dgsl = gtr & 0x7;
+ /* if dgsl is zero, this rank was not trained. skip. */
+ if (dgsl) {
+ dgsl_min = min(dgsl_min, dgsl);
+ dgsl_max = max(dgsl_max, dgsl);
+ }
+ gtr >>= 3;
+ }
+ dx_base += DMPHY_DX_STRIDE;
+ }
+
+ if (dgsl_min != dgsl_max)
+ printf("DQS Gateing System Latencies are not all leveled.\n");
+
+ return dgsl_max;
+}
+
+static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width,
+ int ch)
+{
+ u32 tmp;
+ void __iomem *zq_base, *dx_base;
+ int zq, dx;
+ int nr_dx;
+
+ nr_dx = width / 8;
+
+ writel(DMPHY_PIR_ZCALBYP, phy_base + DMPHY_PIR);
+ /*
+ * Disable RGLVT bit (Read DQS Gating LCDL Delay VT Compensation)
+ * to avoid read error issue.
+ */
+ writel(0x07d81e37, phy_base + DMPHY_PGCR0);
+ writel(0x0200c4e0, phy_base + DMPHY_PGCR1);
+
+ tmp = ddrphy_pgcr2[freq];
+ if (width >= 32)
+ tmp |= DMPHY_PGCR2_DUALCHN | DMPHY_PGCR2_ACPDDC;
+ writel(tmp, phy_base + DMPHY_PGCR2);
+
+ writel(ddrphy_ptr0[freq], phy_base + DMPHY_PTR0);
+ writel(ddrphy_ptr1[freq], phy_base + DMPHY_PTR1);
+ writel(0x00083def, phy_base + DMPHY_PTR2);
+ writel(ddrphy_ptr3[freq], phy_base + DMPHY_PTR3);
+ writel(ddrphy_ptr4[freq], phy_base + DMPHY_PTR4);
+
+ writel(ddrphy_acbdlr0[ch], phy_base + DMPHY_ACBDLR0);
+
+ writel(0x55555555, phy_base + DMPHY_ACIOCR1);
+ writel(0x00000000, phy_base + DMPHY_ACIOCR2);
+ writel(0x55555555, phy_base + DMPHY_ACIOCR3);
+ writel(0x00000000, phy_base + DMPHY_ACIOCR4);
+ writel(0x00000055, phy_base + DMPHY_ACIOCR5);
+ writel(0x00181aa4, phy_base + DMPHY_DXCCR);
+
+ writel(0x0024641e, phy_base + DMPHY_DSGCR);
+ writel(0x0000040b, phy_base + DMPHY_DCR);
+ writel(ddrphy_dtpr0[freq], phy_base + DMPHY_DTPR0);
+ writel(ddrphy_dtpr1[freq], phy_base + DMPHY_DTPR1);
+ writel(ddrphy_dtpr2[freq], phy_base + DMPHY_DTPR2);
+ writel(ddrphy_dtpr3[freq], phy_base + DMPHY_DTPR3);
+ writel(ddrphy_mr0[freq], phy_base + DMPHY_MR0);
+ writel(0x00000006, phy_base + DMPHY_MR1);
+ writel(ddrphy_mr2[freq], phy_base + DMPHY_MR2);
+ writel(0x00000000, phy_base + DMPHY_MR3);
+
+ tmp = 0;
+ for (dx = 0; dx < nr_dx; dx++)
+ tmp |= BIT(DMPHY_DTCR_RANKEN_SHIFT + ddrphy_get_rank(dx));
+ writel(0x90003087 | tmp, phy_base + DMPHY_DTCR);
+
+ writel(0x00000000, phy_base + DMPHY_DTAR0);
+ writel(0x00000008, phy_base + DMPHY_DTAR1);
+ writel(0x00000010, phy_base + DMPHY_DTAR2);
+ writel(0x00000018, phy_base + DMPHY_DTAR3);
+ writel(0xdd22ee11, phy_base + DMPHY_DTDR0);
+ writel(0x7788bb44, phy_base + DMPHY_DTDR1);
+
+ /* impedance control settings */
+ writel(0x04048900, phy_base + DMPHY_ZQCR);
+
+ zq_base = phy_base + DMPHY_ZQ_BASE;
+ for (zq = 0; zq < 4; zq++) {
+ /*
+ * board-dependent
+ * PXS2: CH0ZQ0=0x5B, CH1ZQ0=0x5B, CH2ZQ0=0x59, others=0x5D
+ */
+ writel(0x0007BB5D, zq_base + DMPHY_ZQ_PR);
+ zq_base += DMPHY_ZQ_STRIDE;
+ }
+
+ /* DATX8 settings */
+ dx_base = phy_base + DMPHY_DX_BASE;
+ for (dx = 0; dx < 4; dx++) {
+ tmp = readl(dx_base + DMPHY_DX_GCR0);
+ tmp &= ~DMPHY_DX_GCR0_WLRKEN_MASK;
+ tmp |= BIT(DMPHY_DX_GCR0_WLRKEN_SHIFT + ddrphy_get_rank(dx)) &
+ DMPHY_DX_GCR0_WLRKEN_MASK;
+ writel(tmp, dx_base + DMPHY_DX_GCR0);
+
+ writel(0x00000000, dx_base + DMPHY_DX_GCR1);
+ writel(0x00000000, dx_base + DMPHY_DX_GCR2);
+ writel(0x00000000, dx_base + DMPHY_DX_GCR3);
+ dx_base += DMPHY_DX_STRIDE;
+ }
+
+ while (!(readl(phy_base + DMPHY_PGSR0) & DMPHY_PGSR0_IDONE))
+ cpu_relax();
+
+ ddrphy_dqs_delay_fixup(phy_base, nr_dx, -4);
+}
+
+struct ddrphy_init_sequence {
+ char *description;
+ u32 init_flag;
+ u32 done_flag;
+ u32 err_flag;
+};
+
+static const struct ddrphy_init_sequence impedance_calibration_sequence[] = {
+ {
+ "Impedance Calibration",
+ DMPHY_PIR_ZCAL,
+ DMPHY_PGSR0_ZCDONE,
+ DMPHY_PGSR0_ZCERR,
+ },
+ { /* sentinel */ }
+};
+
+static const struct ddrphy_init_sequence dram_init_sequence[] = {
+ {
+ "DRAM Initialization",
+ DMPHY_PIR_DRAMRST | DMPHY_PIR_DRAMINIT,
+ DMPHY_PGSR0_DIDONE,
+ 0,
+ },
+ { /* sentinel */ }
+};
+
+static const struct ddrphy_init_sequence training_sequence[] = {
+ {
+ "Write Leveling",
+ DMPHY_PIR_WL,
+ DMPHY_PGSR0_WLDONE,
+ DMPHY_PGSR0_WLERR,
+ },
+ {
+ "Read DQS Gate Training",
+ DMPHY_PIR_QSGATE,
+ DMPHY_PGSR0_QSGDONE,
+ DMPHY_PGSR0_QSGERR,
+ },
+ {
+ "Write Leveling Adjustment",
+ DMPHY_PIR_WLADJ,
+ DMPHY_PGSR0_WLADONE,
+ DMPHY_PGSR0_WLAERR,
+ },
+ {
+ "Read Bit Deskew",
+ DMPHY_PIR_RDDSKW,
+ DMPHY_PGSR0_RDDONE,
+ DMPHY_PGSR0_RDERR,
+ },
+ {
+ "Write Bit Deskew",
+ DMPHY_PIR_WRDSKW,
+ DMPHY_PGSR0_WDDONE,
+ DMPHY_PGSR0_WDERR,
+ },
+ {
+ "Read Eye Training",
+ DMPHY_PIR_RDEYE,
+ DMPHY_PGSR0_REDONE,
+ DMPHY_PGSR0_REERR,
+ },
+ {
+ "Write Eye Training",
+ DMPHY_PIR_WREYE,
+ DMPHY_PGSR0_WEDONE,
+ DMPHY_PGSR0_WEERR,
+ },
+ { /* sentinel */ }
+};
+
+static int __ddrphy_training(void __iomem *phy_base,
+ const struct ddrphy_init_sequence *seq)
+{
+ const struct ddrphy_init_sequence *s;
+ u32 pgsr0;
+ u32 init_flag = DMPHY_PIR_INIT;
+ u32 done_flag = DMPHY_PGSR0_IDONE;
+ int timeout = 50000; /* 50 msec is long enough */
+#ifdef DISPLAY_ELAPSED_TIME
+ ulong start = get_timer(0);
+#endif
+
+ for (s = seq; s->description; s++) {
+ init_flag |= s->init_flag;
+ done_flag |= s->done_flag;
+ }
+
+ writel(init_flag, phy_base + DMPHY_PIR);
+
+ do {
+ if (--timeout < 0) {
+ pr_err("%s: error: timeout during DDR training\n",
+ __func__);
+ return -ETIMEDOUT;
+ }
+ udelay(1);
+ pgsr0 = readl(phy_base + DMPHY_PGSR0);
+ } while ((pgsr0 & done_flag) != done_flag);
+
+ for (s = seq; s->description; s++) {
+ if (pgsr0 & s->err_flag) {
+ pr_err("%s: error: %s failed\n", __func__,
+ s->description);
+ return -EIO;
+ }
+ }
+
+#ifdef DISPLAY_ELAPSED_TIME
+ printf("%s: info: elapsed time %ld msec\n", get_timer(start));
+#endif
+
+ return 0;
+}
+
+static int ddrphy_impedance_calibration(void __iomem *phy_base)
+{
+ int ret;
+ u32 tmp;
+
+ ret = __ddrphy_training(phy_base, impedance_calibration_sequence);
+ if (ret)
+ return ret;
+
+ /*
+ * Because of a hardware bug, IDONE flag is set when the first ZQ block
+ * is calibrated. The flag does not guarantee the completion for all
+ * the ZQ blocks. Wait a little more just in case.
+ */
+ udelay(1);
+
+ /* reflect ZQ settings and enable average algorithm*/
+ tmp = readl(phy_base + DMPHY_ZQCR);
+ tmp |= DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
+ writel(tmp, phy_base + DMPHY_ZQCR);
+ tmp &= ~DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
+ tmp |= DMPHY_ZQCR_AVGEN;
+ writel(tmp, phy_base + DMPHY_ZQCR);
+
+ return 0;
+}
+
+static int ddrphy_dram_init(void __iomem *phy_base)
+{
+ return __ddrphy_training(phy_base, dram_init_sequence);
+}
+
+static int ddrphy_training(void __iomem *phy_base)
+{
+ return __ddrphy_training(phy_base, training_sequence);
+}
+
+/* UMC */
+static void umc_set_system_latency(void __iomem *dc_base, int phy_latency)
+{
+ u32 val;
+ int latency;
+
+ val = readl(dc_base + UMC_RDATACTL_D0);
+ latency = (val & UMC_RDATACTL_RADLTY_MASK) >> UMC_RDATACTL_RADLTY_SHIFT;
+ latency += (val & UMC_RDATACTL_RAD2LTY_MASK) >>
+ UMC_RDATACTL_RAD2LTY_SHIFT;
+ /*
+ * UMC works at the half clock rate of the PHY.
+ * The LSB of latency is ignored
+ */
+ latency += phy_latency & ~1;
+
+ val &= ~(UMC_RDATACTL_RADLTY_MASK | UMC_RDATACTL_RAD2LTY_MASK);
+ if (latency > 0xf) {
+ val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
+ val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
+ } else {
+ val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
+ }
+
+ writel(val, dc_base + UMC_RDATACTL_D0);
+ writel(val, dc_base + UMC_RDATACTL_D1);
+
+ readl(dc_base + UMC_RDATACTL_D1); /* relax */
+}
+
+/* enable/disable auto refresh */
+void umc_refresh_ctrl(void __iomem *dc_base, int enable)
+{
+ u32 tmp;
+
+ tmp = readl(dc_base + UMC_SPCSETB);
+ tmp &= ~UMC_SPCSETB_AREFMD_MASK;
+
+ if (enable)
+ tmp |= UMC_SPCSETB_AREFMD_ARB;
+ else
+ tmp |= UMC_SPCSETB_AREFMD_REG;
+
+ writel(tmp, dc_base + UMC_SPCSETB);
+ udelay(1);
+}
+
+static void umc_ud_init(void __iomem *umc_base, int ch)
+{
+ writel(0x00000003, umc_base + UMC_BITPERPIXELMODE_D0);
+
+ if (ch == 2)
+ writel(0x00000033, umc_base + UMC_PAIR1DOFF_D0);
+}
+
+static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
+ unsigned long size, int width, int ch)
+{
+ enum dram_size size_e;
+ int latency;
+ u32 val;
+
+ switch (size) {
+ case 0:
+ return 0;
+ case SZ_256M:
+ size_e = DRAM_SZ_256M;
+ break;
+ case SZ_512M:
+ size_e = DRAM_SZ_512M;
+ break;
+ default:
+ pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n",
+ size, ch);
+ return -EINVAL;
+ }
+
+ writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
+
+ writel(ch == 2 ? umc_cmdctlb_ch2[freq] : umc_cmdctlb_ch01[freq],
+ dc_base + UMC_CMDCTLB);
+
+ writel(umc_spcctla[freq][size_e], dc_base + UMC_SPCCTLA);
+ writel(umc_spcctlb[freq], dc_base + UMC_SPCCTLB);
+
+ val = 0x000e000e;
+ latency = 12;
+ /* ES2 inserted one more FF to the logic. */
+ if (uniphier_get_soc_model() >= 2)
+ latency += 2;
+
+ if (latency > 0xf) {
+ val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
+ val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
+ } else {
+ val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
+ }
+
+ writel(val, dc_base + UMC_RDATACTL_D0);
+ if (width >= 32)
+ writel(val, dc_base + UMC_RDATACTL_D1);
+
+ writel(0x04060A02, dc_base + UMC_WDATACTL_D0);
+ if (width >= 32)
+ writel(0x04060A02, dc_base + UMC_WDATACTL_D1);
+ writel(0x04000000, dc_base + UMC_DATASET);
+ writel(0x00400020, dc_base + UMC_DCCGCTL);
+ writel(0x00000084, dc_base + UMC_FLOWCTLG);
+ writel(0x00000000, dc_base + UMC_ACSSETA);
+
+ writel(ch == 2 ? umc_flowctla_ch2[freq] : umc_flowctla_ch01[freq],
+ dc_base + UMC_FLOWCTLA);
+
+ writel(0x00004400, dc_base + UMC_FLOWCTLC);
+ writel(0x200A0A00, dc_base + UMC_SPCSETB);
+ writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
+ writel(0x0000000D, dc_base + UMC_RESPCTL);
+
+ if (ch != 2) {
+ writel(0x00202000, dc_base + UMC_FLOWCTLB);
+ writel(0xFDBFFFFF, dc_base + UMC_FLOWCTLOB0);
+ writel(0xFFFFFFFF, dc_base + UMC_FLOWCTLOB1);
+ writel(0x00080700, dc_base + UMC_BSICMAPSET);
+ } else {
+ writel(0x00200000, dc_base + UMC_FLOWCTLB);
+ writel(0x00000000, dc_base + UMC_BSICMAPSET);
+ }
+
+ writel(0x00000000, dc_base + UMC_ERRMASKA);
+ writel(0x00000000, dc_base + UMC_ERRMASKB);
+
+ return 0;
+}
+
+static int umc_ch_init(void __iomem *umc_ch_base, enum dram_freq freq,
+ unsigned long size, unsigned int width, int ch)
+{
+ void __iomem *dc_base = umc_ch_base + 0x00011000;
+ void __iomem *phy_base = umc_ch_base + 0x00030000;
+ int ret;
+
+ writel(0x00000002, dc_base + UMC_INITSET);
+ while (readl(dc_base + UMC_INITSTAT) & BIT(2))
+ cpu_relax();
+
+ /* deassert PHY reset signals */
+ writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
+ dc_base + UMC_DIOCTLA);
+
+ ddrphy_init(phy_base, freq, width, ch);
+
+ ret = ddrphy_impedance_calibration(phy_base);
+ if (ret)
+ return ret;
+
+ ddrphy_dram_init(phy_base);
+ if (ret)
+ return ret;
+
+ ret = umc_dc_init(dc_base, freq, size, width, ch);
+ if (ret)
+ return ret;
+
+ umc_ud_init(umc_ch_base, ch);
+
+ ret = ddrphy_training(phy_base);
+ if (ret)
+ return ret;
+
+ udelay(1);
+
+ /* match the system latency between UMC and PHY */
+ umc_set_system_latency(dc_base,
+ ddrphy_get_system_latency(phy_base, width));
+
+ udelay(1);
+
+ /* stop auto refresh before clearing FIFO in PHY */
+ umc_refresh_ctrl(dc_base, 0);
+ ddrphy_fifo_reset(phy_base);
+ umc_refresh_ctrl(dc_base, 1);
+
+ udelay(10);
+
+ return 0;
+}
+
+static void um_init(void __iomem *um_base)
+{
+ writel(0x000000ff, um_base + UMC_MBUS0);
+ writel(0x000000ff, um_base + UMC_MBUS1);
+ writel(0x000000ff, um_base + UMC_MBUS2);
+ writel(0x000000ff, um_base + UMC_MBUS3);
+}
+
+int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd)
+{
+ void __iomem *um_base = (void __iomem *)0x5b600000;
+ void __iomem *umc_ch_base = (void __iomem *)0x5b800000;
+ enum dram_freq freq;
+ int ch, ret;
+
+ switch (bd->dram_freq) {
+ case 1866:
+ freq = DRAM_FREQ_1866M;
+ break;
+ case 2133:
+ freq = DRAM_FREQ_2133M;
+ break;
+ default:
+ pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
+ return -EINVAL;
+ }
+
+ for (ch = 0; ch < bd->dram_nr_ch; ch++) {
+ unsigned long size = bd->dram_ch[ch].size;
+ unsigned int width = bd->dram_ch[ch].width;
+
+ ret = umc_ch_init(umc_ch_base, freq, size / (width / 16),
+ width, ch);
+ if (ret) {
+ pr_err("failed to initialize UMC ch%d\n", ch);
+ return ret;
+ }
+
+ umc_ch_base += 0x00200000;
+ }
+
+ um_init(um_base);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <asm/processor.h>
+
+#include "../init.h"
+#include "ddrphy-regs.h"
+#include "umc-regs.h"
+
+#define DRAM_CH_NR 2
+
+enum dram_freq {
+ DRAM_FREQ_1333M,
+ DRAM_FREQ_1600M,
+ DRAM_FREQ_NR,
+};
+
+enum dram_size {
+ DRAM_SZ_128M,
+ DRAM_SZ_256M,
+ DRAM_SZ_512M,
+ DRAM_SZ_NR,
+};
+
+static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x55990b11, 0x66bb0f17};
+static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x46bb0f17};
+static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x16958944, 0x18c6ab44};
+static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6ab24};
+static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+ {0x00240512, 0x00350512, 0x00000000}, /* no data for 1333MHz,128MB */
+ {0x002b0617, 0x003f0617, 0x00670617},
+};
+static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
+static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ac};
+
+static int umc_get_rank(int ch)
+{
+ return ch; /* ch0: rank0, ch1: rank1 for this SoC */
+}
+
+static void umc_start_ssif(void __iomem *ssif_base)
+{
+ writel(0x00000000, ssif_base + 0x0000b004);
+ writel(0xffffffff, ssif_base + 0x0000c004);
+ writel(0x000fffcf, ssif_base + 0x0000c008);
+ writel(0x00000001, ssif_base + 0x0000b000);
+ writel(0x00000001, ssif_base + 0x0000c000);
+ writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+ writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+
+ writel(0x00000001, ssif_base + UMC_CPURST);
+ writel(0x00000001, ssif_base + UMC_IDSRST);
+ writel(0x00000001, ssif_base + UMC_IXMRST);
+ writel(0x00000001, ssif_base + UMC_MDMRST);
+ writel(0x00000001, ssif_base + UMC_MDDRST);
+ writel(0x00000001, ssif_base + UMC_SIORST);
+ writel(0x00000001, ssif_base + UMC_VIORST);
+ writel(0x00000001, ssif_base + UMC_FRCRST);
+ writel(0x00000001, ssif_base + UMC_RGLRST);
+ writel(0x00000001, ssif_base + UMC_AIORST);
+ writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
+ int freq, unsigned long size, bool ddr3plus)
+{
+ enum dram_freq freq_e;
+ enum dram_size size_e;
+
+ switch (freq) {
+ case 1333:
+ freq_e = DRAM_FREQ_1333M;
+ break;
+ case 1600:
+ freq_e = DRAM_FREQ_1600M;
+ break;
+ default:
+ pr_err("unsupported DRAM frequency %d MHz\n", freq);
+ return -EINVAL;
+ }
+
+ switch (size) {
+ case 0:
+ return 0;
+ case SZ_128M:
+ size_e = DRAM_SZ_128M;
+ break;
+ case SZ_256M:
+ size_e = DRAM_SZ_256M;
+ break;
+ case SZ_512M:
+ size_e = DRAM_SZ_512M;
+ break;
+ default:
+ pr_err("unsupported DRAM size 0x%08lx\n", size);
+ return -EINVAL;
+ }
+
+ writel((ddr3plus ? umc_cmdctla_plus : umc_cmdctla)[freq_e],
+ dc_base + UMC_CMDCTLA);
+ writel((ddr3plus ? umc_cmdctlb_plus : umc_cmdctlb)[freq_e],
+ dc_base + UMC_CMDCTLB);
+ writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA);
+ writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB);
+ writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
+ writel(0x04060806, dc_base + UMC_WDATACTL_D0);
+ writel(0x04a02000, dc_base + UMC_DATASET);
+ writel(0x00000000, ca_base + 0x2300);
+ writel(0x00400020, dc_base + UMC_DCCGCTL);
+ writel(0x00000003, dc_base + 0x7000);
+ writel(0x0000004f, dc_base + 0x8000);
+ writel(0x000000c3, dc_base + 0x8004);
+ writel(0x00000077, dc_base + 0x8008);
+ writel(0x0000003b, dc_base + UMC_DICGCTLA);
+ writel(0x020a0808, dc_base + UMC_DICGCTLB);
+ writel(0x00000004, dc_base + UMC_FLOWCTLG);
+ writel(0x80000201, ca_base + 0xc20);
+ writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
+ writel(0x00200000, dc_base + UMC_FLOWCTLB);
+ writel(0x00004444, dc_base + UMC_FLOWCTLC);
+ writel(0x200a0a00, dc_base + UMC_SPCSETB);
+ writel(0x00000000, dc_base + UMC_SPCSETD);
+ writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
+
+ return 0;
+}
+
+static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
+ int freq, unsigned long size, bool ddr3plus, int ch)
+{
+ void __iomem *phy_base = dc_base + 0x00001000;
+ int ret;
+
+ writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
+ while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
+ cpu_relax();
+
+ writel(0x00000101, dc_base + UMC_DIOCTLA);
+
+ ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
+ if (ret)
+ return ret;
+
+ ddrphy_prepare_training(phy_base, umc_get_rank(ch));
+ ret = ddrphy_training(phy_base);
+ if (ret)
+ return ret;
+
+ return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
+}
+
+int uniphier_sld8_umc_init(const struct uniphier_board_data *bd)
+{
+ void __iomem *umc_base = (void __iomem *)0x5b800000;
+ void __iomem *ca_base = umc_base + 0x00001000;
+ void __iomem *dc_base = umc_base + 0x00400000;
+ void __iomem *ssif_base = umc_base;
+ int ch, ret;
+
+ for (ch = 0; ch < DRAM_CH_NR; ch++) {
+ ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
+ bd->dram_ch[ch].size,
+ bd->dram_ddr3plus, ch);
+ if (ret) {
+ pr_err("failed to initialize UMC ch%d\n", ch);
+ return ret;
+ }
+
+ ca_base += 0x00001000;
+ dc_base += 0x00200000;
+ }
+
+ umc_start_ssif(ssif_base);
+
+ return 0;
+}
int dram_init(void)
{
+ const void *fdt = gd->fdt_blob;
const fdt32_t *val;
- int len;
+ int ac, sc, len;
- val = get_memory_reg_prop(gd->fdt_blob, &len);
- if (len < sizeof(*val))
+ ac = fdt_address_cells(fdt, 0);
+ sc = fdt_size_cells(fdt, 0);
+ if (ac < 0 || sc < 1 || sc > 2) {
+ printf("invalid address/size cells\n");
return -EINVAL;
+ }
+
+ val = get_memory_reg_prop(fdt, &len);
+ if (len / sizeof(*val) < ac + sc)
+ return -EINVAL;
+
+ val += ac;
- gd->ram_size = fdt32_to_cpu(*(val + 1));
+ gd->ram_size = sc == 2 ? fdt64_to_cpu(*(fdt64_t *)val) :
+ fdt32_to_cpu(*val);
debug("DRAM size = %08lx\n", (unsigned long)gd->ram_size);
void dram_init_banksize(void)
{
+ const void *fdt = gd->fdt_blob;
const fdt32_t *val;
- int len, i;
+ int ac, sc, cells, len, i;
- val = get_memory_reg_prop(gd->fdt_blob, &len);
+ val = get_memory_reg_prop(fdt, &len);
if (len < 0)
return;
+ ac = fdt_address_cells(fdt, 0);
+ sc = fdt_size_cells(fdt, 0);
+ if (ac < 1 || sc > 2 || sc < 1 || sc > 2) {
+ printf("invalid address/size cells\n");
+ return;
+ }
+
+ cells = ac + sc;
+
len /= sizeof(*val);
- len /= 2;
- for (i = 0; i < len; i++) {
- gd->bd->bi_dram[i].start = fdt32_to_cpu(*val++);
- gd->bd->bi_dram[i].size = fdt32_to_cpu(*val++);
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS && len >= cells;
+ i++, len -= cells) {
+ gd->bd->bi_dram[i].start = ac == 2 ?
+ fdt64_to_cpu(*(fdt64_t *)val) : fdt32_to_cpu(*val);
+ val += ac;
+ gd->bd->bi_dram[i].size = sc == 2 ?
+ fdt64_to_cpu(*(fdt64_t *)val) : fdt32_to_cpu(*val);
+ val += sc;
debug("DRAM bank %d: start = %08lx, size = %08lx\n",
i, (unsigned long)gd->bd->bi_dram[i].start,
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += early-clk-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += early-clk-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += early-clk-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += early-clk-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += early-clk-ph1-pro5.o
-obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += early-clk-proxstream2.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += early-clk-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-clk-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4) += early-clk-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += early-clk-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL);
+
+ tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
+ if (spl_boot_device() != BOOT_DEVICE_NAND)
+ tmp &= ~SC_RSTCTRL_NRST_NAND;
+ writel(tmp, SC_RSTCTRL);
+ readl(SC_RSTCTRL); /* dummy read */
+
+ /* provide clocks */
+ tmp = readl(SC_CLKCTRL);
+ tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
+ writel(tmp, SC_CLKCTRL);
+ readl(SC_CLKCTRL); /* dummy read */
+
+ return 0;
+}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-
-int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd)
-{
- u32 tmp;
-
- /* deassert reset */
- tmp = readl(SC_RSTCTRL);
-
- tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
- if (spl_boot_device() != BOOT_DEVICE_NAND)
- tmp &= ~SC_RSTCTRL_NRST_NAND;
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
-
- /* privide clocks */
- tmp = readl(SC_CLKCTRL);
- tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-
-int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd)
-{
- u32 tmp;
-
- /*
- * deassert reset
- * UMCA2: Ch1 (DDR3)
- * UMCA1, UMC31: Ch0 (WIO1)
- * UMCA0, UMC30: Ch0 (WIO0)
- */
- tmp = readl(SC_RSTCTRL4);
- tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
- SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
- SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30;
- writel(tmp, SC_RSTCTRL4);
- readl(SC_RSTCTRL); /* dummy read */
-
- /* privide clocks */
- tmp = readl(SC_CLKCTRL);
- tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
- writel(tmp, SC_CLKCTRL);
- tmp = readl(SC_CLKCTRL4);
- tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 |
- SC_CLKCTRL4_CEN_UMC0;
- writel(tmp, SC_CLKCTRL4);
- readl(SC_CLKCTRL4); /* dummy read */
-
- return 0;
-}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+
+ /*
+ * deassert reset
+ * UMCA2: Ch1 (DDR3)
+ * UMCA1, UMC31: Ch0 (WIO1)
+ * UMCA0, UMC30: Ch0 (WIO0)
+ */
+ tmp = readl(SC_RSTCTRL4);
+ tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
+ SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
+ SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30;
+ writel(tmp, SC_RSTCTRL4);
+ readl(SC_RSTCTRL); /* dummy read */
+
+ /* provide clocks */
+ tmp = readl(SC_CLKCTRL);
+ tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
+ writel(tmp, SC_CLKCTRL);
+ tmp = readl(SC_CLKCTRL4);
+ tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 |
+ SC_CLKCTRL4_CEN_UMC0;
+ writel(tmp, SC_CLKCTRL4);
+ readl(SC_CLKCTRL4); /* dummy read */
+
+ return 0;
+}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-
-int proxstream2_early_clk_init(const struct uniphier_board_data *bd)
-{
- u32 tmp;
-
- /* deassert reset */
- if (spl_boot_device() != BOOT_DEVICE_NAND) {
- tmp = readl(SC_RSTCTRL);
- tmp &= ~SC_RSTCTRL_NRST_NAND;
- writel(tmp, SC_RSTCTRL);
- };
-
- tmp = readl(SC_RSTCTRL4);
- tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
- SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
- SC_RSTCTRL4_NRST_UMC32 | SC_RSTCTRL4_NRST_UMC31 |
- SC_RSTCTRL4_NRST_UMC30;
- writel(tmp, SC_RSTCTRL4);
- readl(SC_RSTCTRL4); /* dummy read */
-
- /* privide clocks */
- tmp = readl(SC_CLKCTRL);
- tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
- writel(tmp, SC_CLKCTRL);
-
- tmp = readl(SC_CLKCTRL4);
- tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC2 |
- SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0;
- writel(tmp, SC_CLKCTRL4);
- readl(SC_CLKCTRL4); /* dummy read */
-
- return 0;
-}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ if (spl_boot_device() != BOOT_DEVICE_NAND) {
+ tmp = readl(SC_RSTCTRL);
+ tmp &= ~SC_RSTCTRL_NRST_NAND;
+ writel(tmp, SC_RSTCTRL);
+ };
+
+ tmp = readl(SC_RSTCTRL4);
+ tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
+ SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
+ SC_RSTCTRL4_NRST_UMC32 | SC_RSTCTRL4_NRST_UMC31 |
+ SC_RSTCTRL4_NRST_UMC30;
+ writel(tmp, SC_RSTCTRL4);
+ readl(SC_RSTCTRL4); /* dummy read */
+
+ /* provide clocks */
+ tmp = readl(SC_CLKCTRL);
+ tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
+ writel(tmp, SC_CLKCTRL);
+
+ tmp = readl(SC_CLKCTRL4);
+ tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC2 |
+ SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0;
+ writel(tmp, SC_CLKCTRL4);
+ readl(SC_CLKCTRL4); /* dummy read */
+
+ return 0;
+}
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += early-pinctrl-ph1-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-pinctrl-sld3.o
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
- sg_set_pinsel(63, 0, 4, 4); /* RXD0 */
- sg_set_pinsel(64, 1, 4, 4); /* TXD0 */
-
- sg_set_pinsel(65, 0, 4, 4); /* RXD1 */
- sg_set_pinsel(66, 1, 4, 4); /* TXD1 */
-
- sg_set_pinsel(96, 2, 4, 4); /* RXD2 */
- sg_set_pinsel(102, 2, 4, 4); /* TXD2 */
-#endif
-
- return 0;
-}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_UNIPHIER_SERIAL
+ sg_set_pinsel(63, 0, 4, 4); /* RXD0 */
+ sg_set_pinsel(64, 1, 4, 4); /* TXD0 */
+
+ sg_set_pinsel(65, 0, 4, 4); /* RXD1 */
+ sg_set_pinsel(66, 1, 4, 4); /* TXD1 */
+
+ sg_set_pinsel(96, 2, 4, 4); /* RXD2 */
+ sg_set_pinsel(102, 2, 4, 4); /* TXD2 */
+#endif
+
+ return 0;
+}
const struct uniphier_board_data *uniphier_get_board_param(void);
-int ph1_sld3_init(const struct uniphier_board_data *bd);
-int ph1_ld4_init(const struct uniphier_board_data *bd);
-int ph1_pro4_init(const struct uniphier_board_data *bd);
-int ph1_sld8_init(const struct uniphier_board_data *bd);
-int ph1_pro5_init(const struct uniphier_board_data *bd);
-int proxstream2_init(const struct uniphier_board_data *bd);
+int uniphier_sld3_init(const struct uniphier_board_data *bd);
+int uniphier_ld4_init(const struct uniphier_board_data *bd);
+int uniphier_pro4_init(const struct uniphier_board_data *bd);
+int uniphier_sld8_init(const struct uniphier_board_data *bd);
+int uniphier_pro5_init(const struct uniphier_board_data *bd);
+int uniphier_pxs2_init(const struct uniphier_board_data *bd);
#if defined(CONFIG_MICRO_SUPPORT_CARD)
-int ph1_sld3_sbc_init(const struct uniphier_board_data *bd);
-int ph1_ld4_sbc_init(const struct uniphier_board_data *bd);
-int ph1_pro4_sbc_init(const struct uniphier_board_data *bd);
-int proxstream2_sbc_init(const struct uniphier_board_data *bd);
+int uniphier_sbc_init_admulti(const struct uniphier_board_data *bd);
+int uniphier_sbc_init_savepin(const struct uniphier_board_data *bd);
+int uniphier_sld3_sbc_init(const struct uniphier_board_data *bd);
+int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd);
+int uniphier_pxs2_sbc_init(const struct uniphier_board_data *bd);
#else
-static inline int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
+static inline int uniphier_sbc_init_admulti(
+ const struct uniphier_board_data *bd)
{
return 0;
}
-static inline int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
+static inline int uniphier_sbc_init_savepin(
+ const struct uniphier_board_data *bd)
{
return 0;
}
-static inline int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
+static inline int uniphier_sld3_sbc_init(const struct uniphier_board_data *bd)
{
return 0;
}
-static inline int proxstream2_sbc_init(const struct uniphier_board_data *bd)
+static inline int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
+
+static inline int uniphier_pxs2_sbc_init(const struct uniphier_board_data *bd)
{
return 0;
}
#endif
-int ph1_sld3_bcu_init(const struct uniphier_board_data *bd);
-int ph1_ld4_bcu_init(const struct uniphier_board_data *bd);
+int uniphier_sld3_bcu_init(const struct uniphier_board_data *bd);
+int uniphier_ld4_bcu_init(const struct uniphier_board_data *bd);
int memconf_init(const struct uniphier_board_data *bd);
-int ph1_sld3_memconf_init(const struct uniphier_board_data *bd);
-int proxstream2_memconf_init(const struct uniphier_board_data *bd);
-
-int ph1_sld3_pll_init(const struct uniphier_board_data *bd);
-int ph1_ld4_pll_init(const struct uniphier_board_data *bd);
-int ph1_pro4_pll_init(const struct uniphier_board_data *bd);
-int ph1_sld8_pll_init(const struct uniphier_board_data *bd);
-
-int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd);
-int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
-
-int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd);
-int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd);
-int proxstream2_early_clk_init(const struct uniphier_board_data *bd);
-
-int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd);
-
-int ph1_ld4_umc_init(const struct uniphier_board_data *bd);
-int ph1_pro4_umc_init(const struct uniphier_board_data *bd);
-int ph1_sld8_umc_init(const struct uniphier_board_data *bd);
-int proxstream2_umc_init(const struct uniphier_board_data *bd);
-
-void ph1_sld3_pin_init(void);
-void ph1_ld4_pin_init(void);
-void ph1_pro4_pin_init(void);
-void ph1_sld8_pin_init(void);
-void ph1_pro5_pin_init(void);
-void proxstream2_pin_init(void);
-void ph1_ld6b_pin_init(void);
-
-void ph1_ld4_clk_init(void);
-void ph1_pro4_clk_init(void);
-void ph1_pro5_clk_init(void);
-void proxstream2_clk_init(void);
+int uniphier_sld3_memconf_init(const struct uniphier_board_data *bd);
+int uniphier_pxs2_memconf_init(const struct uniphier_board_data *bd);
+
+int uniphier_sld3_pll_init(const struct uniphier_board_data *bd);
+int uniphier_ld4_pll_init(const struct uniphier_board_data *bd);
+int uniphier_pro4_pll_init(const struct uniphier_board_data *bd);
+int uniphier_sld8_pll_init(const struct uniphier_board_data *bd);
+
+int uniphier_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd);
+int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
+
+int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd);
+int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd);
+int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd);
+
+int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd);
+
+int uniphier_ld4_umc_init(const struct uniphier_board_data *bd);
+int uniphier_pro4_umc_init(const struct uniphier_board_data *bd);
+int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
+int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd);
+
+void uniphier_sld3_pin_init(void);
+void uniphier_ld4_pin_init(void);
+void uniphier_pro4_pin_init(void);
+void uniphier_sld8_pin_init(void);
+void uniphier_pro5_pin_init(void);
+void uniphier_pxs2_pin_init(void);
+void uniphier_ld6b_pin_init(void);
+
+void uniphier_ld4_clk_init(void);
+void uniphier_pro4_clk_init(void);
+void uniphier_pro5_clk_init(void);
+void uniphier_pxs2_clk_init(void);
#define pr_err(fmt, args...) printf(fmt, ##args)
obj-y += init.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += init-ph1-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += init-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += init-ph1-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += init-ph1-sld8.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += init-ph1-pro5.o
-obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += init-proxstream2.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += init-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += init-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4) += init-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += init-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += init-sld8.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += init-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += init-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += init-pxs2.o
--- /dev/null
+/*
+ * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
+
+int uniphier_ld4_init(const struct uniphier_board_data *bd)
+{
+ uniphier_ld4_bcu_init(bd);
+
+ uniphier_sbc_init_savepin(bd);
+ uniphier_ld4_sbc_init(bd);
+
+ support_card_reset();
+
+ uniphier_ld4_pll_init(bd);
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+
+ led_puts("L1");
+
+ uniphier_ld4_early_clk_init(bd);
+
+ led_puts("L2");
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ {
+ int res;
+
+ res = uniphier_ld4_umc_init(bd);
+ if (res < 0) {
+ while (1)
+ ;
+ }
+ }
+
+ led_puts("L5");
+
+ uniphier_ld4_enable_dpll_ssc(bd);
+
+ led_puts("L6");
+
+ return 0;
+}
+++ /dev/null
-/*
- * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-
-#include "../init.h"
-#include "../micro-support-card.h"
-
-int ph1_ld4_init(const struct uniphier_board_data *bd)
-{
- ph1_ld4_bcu_init(bd);
-
- ph1_ld4_sbc_init(bd);
-
- support_card_reset();
-
- ph1_ld4_pll_init(bd);
-
- support_card_init();
-
- led_puts("L0");
-
- memconf_init(bd);
-
- led_puts("L1");
-
- ph1_ld4_early_clk_init(bd);
-
- led_puts("L2");
-
- led_puts("L3");
-
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
- preloader_console_init();
-#endif
-
- led_puts("L4");
-
- {
- int res;
-
- res = ph1_ld4_umc_init(bd);
- if (res < 0) {
- while (1)
- ;
- }
- }
-
- led_puts("L5");
-
- ph1_ld4_enable_dpll_ssc(bd);
-
- led_puts("L6");
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-
-#include "../init.h"
-#include "../micro-support-card.h"
-
-int ph1_pro4_init(const struct uniphier_board_data *bd)
-{
- ph1_pro4_sbc_init(bd);
-
- support_card_reset();
-
- ph1_pro4_pll_init(bd);
-
- support_card_init();
-
- led_puts("L0");
-
- memconf_init(bd);
-
- led_puts("L1");
-
- ph1_ld4_early_clk_init(bd);
-
- led_puts("L2");
-
- led_puts("L3");
-
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
- preloader_console_init();
-#endif
-
- led_puts("L4");
-
- {
- int res;
-
- res = ph1_pro4_umc_init(bd);
- if (res < 0) {
- while (1)
- ;
- }
- }
-
- led_puts("L5");
-
- ph1_ld4_enable_dpll_ssc(bd);
-
- led_puts("L6");
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-
-#include "../init.h"
-#include "../micro-support-card.h"
-
-int ph1_pro5_init(const struct uniphier_board_data *bd)
-{
- ph1_pro4_sbc_init(bd);
-
- support_card_reset();
-
- support_card_init();
-
- led_puts("L0");
-
- memconf_init(bd);
-
- led_puts("L1");
-
- ph1_pro5_early_clk_init(bd);
-
- led_puts("L2");
-
- led_puts("L3");
-
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
- preloader_console_init();
-#endif
-
- led_puts("L4");
-
- led_puts("L5");
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-
-#include "../init.h"
-#include "../micro-support-card.h"
-
-int ph1_sld3_init(const struct uniphier_board_data *bd)
-{
- ph1_sld3_bcu_init(bd);
-
- ph1_sld3_sbc_init(bd);
-
- support_card_reset();
-
- ph1_sld3_pll_init(bd);
-
- support_card_init();
-
- led_puts("L0");
-
- memconf_init(bd);
- ph1_sld3_memconf_init(bd);
-
- led_puts("L1");
-
- ph1_ld4_early_clk_init(bd);
-
- led_puts("L2");
-
- ph1_sld3_early_pin_init(bd);
-
- led_puts("L3");
-
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
- preloader_console_init();
-#endif
-
- led_puts("L4");
-
- led_puts("L5");
-
- ph1_sld3_enable_dpll_ssc(bd);
-
- led_puts("L6");
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-
-#include "../init.h"
-#include "../micro-support-card.h"
-
-int ph1_sld8_init(const struct uniphier_board_data *bd)
-{
- ph1_ld4_bcu_init(bd);
-
- ph1_ld4_sbc_init(bd);
-
- support_card_reset();
-
- ph1_sld8_pll_init(bd);
-
- support_card_init();
-
- led_puts("L0");
-
- memconf_init(bd);
-
- led_puts("L1");
-
- ph1_ld4_early_clk_init(bd);
-
- led_puts("L2");
-
- led_puts("L3");
-
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
- preloader_console_init();
-#endif
-
- led_puts("L4");
-
- {
- int res;
-
- res = ph1_sld8_umc_init(bd);
- if (res < 0) {
- while (1)
- ;
- }
- }
-
- led_puts("L5");
-
- ph1_ld4_enable_dpll_ssc(bd);
-
- led_puts("L6");
-
- return 0;
-}
--- /dev/null
+/*
+ * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
+
+int uniphier_pro4_init(const struct uniphier_board_data *bd)
+{
+ uniphier_sbc_init_savepin(bd);
+
+ support_card_reset();
+
+ uniphier_pro4_pll_init(bd);
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+
+ led_puts("L1");
+
+ uniphier_ld4_early_clk_init(bd);
+
+ led_puts("L2");
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ {
+ int res;
+
+ res = uniphier_pro4_umc_init(bd);
+ if (res < 0) {
+ while (1)
+ ;
+ }
+ }
+
+ led_puts("L5");
+
+ uniphier_ld4_enable_dpll_ssc(bd);
+
+ led_puts("L6");
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
+
+int uniphier_pro5_init(const struct uniphier_board_data *bd)
+{
+ uniphier_sbc_init_savepin(bd);
+
+ support_card_reset();
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+
+ led_puts("L1");
+
+ uniphier_pro5_early_clk_init(bd);
+
+ led_puts("L2");
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ led_puts("L5");
+
+ return 0;
+}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-
-#include "../init.h"
-#include "../micro-support-card.h"
-
-int proxstream2_init(const struct uniphier_board_data *bd)
-{
- int ret;
-
- proxstream2_sbc_init(bd);
-
- support_card_reset();
-
- support_card_init();
-
- led_puts("L0");
-
- memconf_init(bd);
- proxstream2_memconf_init(bd);
-
- led_puts("L1");
-
- proxstream2_early_clk_init(bd);
-
- led_puts("L2");
-
- led_puts("L3");
-
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
- preloader_console_init();
-#endif
-
- led_puts("L4");
-
- ret = proxstream2_umc_init(bd);
- if (ret)
- return ret;
-
- led_puts("L5");
-
- return 0;
-}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
+
+int uniphier_pxs2_init(const struct uniphier_board_data *bd)
+{
+ int ret;
+
+ uniphier_sbc_init_savepin(bd);
+ uniphier_pxs2_sbc_init(bd);
+
+ support_card_reset();
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+ uniphier_pxs2_memconf_init(bd);
+
+ led_puts("L1");
+
+ uniphier_pxs2_early_clk_init(bd);
+
+ led_puts("L2");
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ ret = uniphier_pxs2_umc_init(bd);
+ if (ret)
+ return ret;
+
+ led_puts("L5");
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
+
+int uniphier_sld3_init(const struct uniphier_board_data *bd)
+{
+ uniphier_sld3_bcu_init(bd);
+
+ uniphier_sbc_init_admulti(bd);
+ uniphier_sld3_sbc_init(bd);
+
+ support_card_reset();
+
+ uniphier_sld3_pll_init(bd);
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+ uniphier_sld3_memconf_init(bd);
+
+ led_puts("L1");
+
+ uniphier_ld4_early_clk_init(bd);
+
+ led_puts("L2");
+
+ uniphier_sld3_early_pin_init(bd);
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ led_puts("L5");
+
+ uniphier_sld3_enable_dpll_ssc(bd);
+
+ led_puts("L6");
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
+
+int uniphier_sld8_init(const struct uniphier_board_data *bd)
+{
+ uniphier_ld4_bcu_init(bd);
+
+ uniphier_sbc_init_savepin(bd);
+ uniphier_ld4_sbc_init(bd);
+
+ support_card_reset();
+
+ uniphier_sld8_pll_init(bd);
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+
+ led_puts("L1");
+
+ uniphier_ld4_early_clk_init(bd);
+
+ led_puts("L2");
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ {
+ int res;
+
+ res = uniphier_sld8_umc_init(bd);
+ if (res < 0) {
+ while (1)
+ ;
+ }
+ }
+
+ led_puts("L5");
+
+ uniphier_ld4_enable_dpll_ssc(bd);
+
+ led_puts("L6");
+
+ return 0;
+}
*/
#include <common.h>
+#include <debug_uart.h>
#include <spl.h>
#include "../init.h"
{
const struct uniphier_board_data *param;
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+
param = uniphier_get_board_param();
if (!param)
hang();
switch (uniphier_get_soc_type()) {
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
- case SOC_UNIPHIER_PH1_SLD3:
- ph1_sld3_init(param);
+#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
+ case SOC_UNIPHIER_SLD3:
+ uniphier_sld3_init(param);
break;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
- case SOC_UNIPHIER_PH1_LD4:
- ph1_ld4_init(param);
+#if defined(CONFIG_ARCH_UNIPHIER_LD4)
+ case SOC_UNIPHIER_LD4:
+ uniphier_ld4_init(param);
break;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
- case SOC_UNIPHIER_PH1_PRO4:
- ph1_pro4_init(param);
+#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
+ case SOC_UNIPHIER_PRO4:
+ uniphier_pro4_init(param);
break;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
- case SOC_UNIPHIER_PH1_SLD8:
- ph1_sld8_init(param);
+#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
+ case SOC_UNIPHIER_SLD8:
+ uniphier_sld8_init(param);
break;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
- case SOC_UNIPHIER_PH1_PRO5:
- ph1_pro5_init(param);
+#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
+ case SOC_UNIPHIER_PRO5:
+ uniphier_pro5_init(param);
break;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
- defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
- case SOC_UNIPHIER_PROXSTREAM2:
- case SOC_UNIPHIER_PH1_LD6B:
- proxstream2_init(param);
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
+ case SOC_UNIPHIER_PXS2:
+ case SOC_UNIPHIER_LD6B:
+ uniphier_pxs2_init(param);
break;
#endif
default:
#
obj-y += memconf.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += memconf-ph1-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += memconf-proxstream2.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += memconf-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += memconf-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += memconf-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += memconf-pxs2.o
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-int ph1_sld3_memconf_init(const struct uniphier_board_data *bd)
-{
- u32 tmp;
- unsigned long size_per_word;
-
- tmp = readl(SG_MEMCONF);
-
- tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
-
- switch (bd->dram_ch[2].width) {
- case 16:
- tmp |= SG_MEMCONF_CH2_NUM_1;
- size_per_word = bd->dram_ch[2].size;
- break;
- case 32:
- tmp |= SG_MEMCONF_CH2_NUM_2;
- size_per_word = bd->dram_ch[2].size >> 1;
- break;
- default:
- pr_err("error: unsupported DRAM Ch2 width\n");
- return -EINVAL;
- }
-
- /* Set DDR size */
- switch (size_per_word) {
- case SZ_64M:
- tmp |= SG_MEMCONF_CH2_SZ_64M;
- break;
- case SZ_128M:
- tmp |= SG_MEMCONF_CH2_SZ_128M;
- break;
- case SZ_256M:
- tmp |= SG_MEMCONF_CH2_SZ_256M;
- break;
- case SZ_512M:
- tmp |= SG_MEMCONF_CH2_SZ_512M;
- break;
- default:
- pr_err("error: unsupported DRAM Ch2 size\n");
- return -EINVAL;
- }
-
- writel(tmp, SG_MEMCONF);
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-int proxstream2_memconf_init(const struct uniphier_board_data *bd)
-{
- u32 tmp;
- unsigned long size_per_word;
-
- tmp = readl(SG_MEMCONF);
-
- tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
-
- switch (bd->dram_ch[2].width) {
- case 16:
- tmp |= SG_MEMCONF_CH2_NUM_1;
- size_per_word = bd->dram_ch[2].size;
- break;
- case 32:
- tmp |= SG_MEMCONF_CH2_NUM_2;
- size_per_word = bd->dram_ch[2].size >> 1;
- break;
- default:
- pr_err("error: unsupported DRAM Ch2 width\n");
- return -EINVAL;
- }
-
- /* Set DDR size */
- switch (size_per_word) {
- case SZ_64M:
- tmp |= SG_MEMCONF_CH2_SZ_64M;
- break;
- case SZ_128M:
- tmp |= SG_MEMCONF_CH2_SZ_128M;
- break;
- case SZ_256M:
- tmp |= SG_MEMCONF_CH2_SZ_256M;
- break;
- case SZ_512M:
- tmp |= SG_MEMCONF_CH2_SZ_512M;
- break;
- default:
- pr_err("error: unsupported DRAM Ch2 size\n");
- return -EINVAL;
- }
-
- if (size_per_word)
- tmp &= ~SG_MEMCONF_CH2_DISABLE;
- else
- tmp |= SG_MEMCONF_CH2_DISABLE;
-
- writel(tmp, SG_MEMCONF);
-
- return 0;
-}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+int uniphier_pxs2_memconf_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+ unsigned long size_per_word;
+
+ tmp = readl(SG_MEMCONF);
+
+ tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
+
+ switch (bd->dram_ch[2].width) {
+ case 16:
+ tmp |= SG_MEMCONF_CH2_NUM_1;
+ size_per_word = bd->dram_ch[2].size;
+ break;
+ case 32:
+ tmp |= SG_MEMCONF_CH2_NUM_2;
+ size_per_word = bd->dram_ch[2].size >> 1;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch2 width\n");
+ return -EINVAL;
+ }
+
+ /* Set DDR size */
+ switch (size_per_word) {
+ case SZ_64M:
+ tmp |= SG_MEMCONF_CH2_SZ_64M;
+ break;
+ case SZ_128M:
+ tmp |= SG_MEMCONF_CH2_SZ_128M;
+ break;
+ case SZ_256M:
+ tmp |= SG_MEMCONF_CH2_SZ_256M;
+ break;
+ case SZ_512M:
+ tmp |= SG_MEMCONF_CH2_SZ_512M;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch2 size\n");
+ return -EINVAL;
+ }
+
+ if (size_per_word)
+ tmp &= ~SG_MEMCONF_CH2_DISABLE;
+ else
+ tmp |= SG_MEMCONF_CH2_DISABLE;
+
+ writel(tmp, SG_MEMCONF);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+int uniphier_sld3_memconf_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+ unsigned long size_per_word;
+
+ tmp = readl(SG_MEMCONF);
+
+ tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
+
+ switch (bd->dram_ch[2].width) {
+ case 16:
+ tmp |= SG_MEMCONF_CH2_NUM_1;
+ size_per_word = bd->dram_ch[2].size;
+ break;
+ case 32:
+ tmp |= SG_MEMCONF_CH2_NUM_2;
+ size_per_word = bd->dram_ch[2].size >> 1;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch2 width\n");
+ return -EINVAL;
+ }
+
+ /* Set DDR size */
+ switch (size_per_word) {
+ case SZ_64M:
+ tmp |= SG_MEMCONF_CH2_SZ_64M;
+ break;
+ case SZ_128M:
+ tmp |= SG_MEMCONF_CH2_SZ_128M;
+ break;
+ case SZ_256M:
+ tmp |= SG_MEMCONF_CH2_SZ_256M;
+ break;
+ case SZ_512M:
+ tmp |= SG_MEMCONF_CH2_SZ_512M;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch2 size\n");
+ return -EINVAL;
+ }
+
+ writel(tmp, SG_MEMCONF);
+
+ return 0;
+}
*/
void support_card_reset_deassert(void)
{
- writel(0, MICRO_SUPPORT_CARD_RESET);
+ writel(0x00010000, MICRO_SUPPORT_CARD_RESET);
}
void support_card_reset(void)
{
- writel(3, MICRO_SUPPORT_CARD_RESET);
+ writel(0x00020003, MICRO_SUPPORT_CARD_RESET);
}
static int support_card_show_revision(void)
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += pinctrl-ph1-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += pinctrl-ph1-pro5.o
-obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += pinctrl-proxstream2.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += pinctrl-ph1-ld6b.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += pinctrl-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4) += pinctrl-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += pinctrl-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pinctrl-sld8.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += pinctrl-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += pinctrl-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += pinctrl-ld6b.o
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+void uniphier_ld4_pin_init(void)
+{
+ u32 tmp;
+
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(158, 0, 8, 4); /* XNFRE -> XNFRE_GB */
+ sg_set_pinsel(159, 0, 8, 4); /* XNFWE -> XNFWE_GB */
+ sg_set_pinsel(160, 0, 8, 4); /* XFALE -> NFALE_GB */
+ sg_set_pinsel(161, 0, 8, 4); /* XFCLE -> NFCLE_GB */
+ sg_set_pinsel(162, 0, 8, 4); /* XNFWP -> XFNWP_GB */
+ sg_set_pinsel(163, 0, 8, 4); /* XNFCE0 -> XNFCE0_GB */
+ sg_set_pinsel(164, 0, 8, 4); /* NANDRYBY0 -> NANDRYBY0_GB */
+ sg_set_pinsel(22, 0, 8, 4); /* MMCCLK -> XFNCE1_GB */
+ sg_set_pinsel(23, 0, 8, 4); /* MMCCMD -> NANDRYBY1_GB */
+ sg_set_pinsel(24, 0, 8, 4); /* MMCDAT0 -> NFD0_GB */
+ sg_set_pinsel(25, 0, 8, 4); /* MMCDAT1 -> NFD1_GB */
+ sg_set_pinsel(26, 0, 8, 4); /* MMCDAT2 -> NFD2_GB */
+ sg_set_pinsel(27, 0, 8, 4); /* MMCDAT3 -> NFD3_GB */
+ sg_set_pinsel(28, 0, 8, 4); /* MMCDAT4 -> NFD4_GB */
+ sg_set_pinsel(29, 0, 8, 4); /* MMCDAT5 -> NFD5_GB */
+ sg_set_pinsel(30, 0, 8, 4); /* MMCDAT6 -> NFD6_GB */
+ sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */
+#endif
+
+ tmp = readl(SG_IECTRL);
+ tmp |= 0x41;
+ writel(tmp, SG_IECTRL);
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+void uniphier_ld6b_pin_init(void)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(30, 0, 8, 4); /* XNFRE -> XNFRE */
+ sg_set_pinsel(31, 0, 8, 4); /* XNFWE -> XNFWE */
+ sg_set_pinsel(32, 0, 8, 4); /* NFALE -> NFALE */
+ sg_set_pinsel(33, 0, 8, 4); /* NFCLE -> NFCLE */
+ sg_set_pinsel(34, 0, 8, 4); /* XNFWP -> XNFWP */
+ sg_set_pinsel(35, 0, 8, 4); /* XNFCE0 -> XNFCE0 */
+ sg_set_pinsel(36, 0, 8, 4); /* NRYBY0 -> NRYBY0 */
+ sg_set_pinsel(37, 0, 8, 4); /* XNFCE1 -> NRYBY1 */
+ sg_set_pinsel(38, 0, 8, 4); /* NRYBY1 -> XNFCE1 */
+ sg_set_pinsel(39, 0, 8, 4); /* NFD0 -> NFD0 */
+ sg_set_pinsel(40, 0, 8, 4); /* NFD1 -> NFD1 */
+ sg_set_pinsel(41, 0, 8, 4); /* NFD2 -> NFD2 */
+ sg_set_pinsel(42, 0, 8, 4); /* NFD3 -> NFD3 */
+ sg_set_pinsel(43, 0, 8, 4); /* NFD4 -> NFD4 */
+ sg_set_pinsel(44, 0, 8, 4); /* NFD5 -> NFD5 */
+ sg_set_pinsel(45, 0, 8, 4); /* NFD6 -> NFD6 */
+ sg_set_pinsel(46, 0, 8, 4); /* NFD7 -> NFD7 */
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ sg_set_pinsel(56, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(57, 0, 8, 4); /* USB0OD -> USB0OD */
+ sg_set_pinsel(58, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(59, 0, 8, 4); /* USB1OD -> USB1OD */
+ sg_set_pinsel(60, 0, 8, 4); /* USB2VBUS -> USB2VBUS */
+ sg_set_pinsel(61, 0, 8, 4); /* USB2OD -> USB2OD */
+ sg_set_pinsel(62, 0, 8, 4); /* USB3VBUS -> USB3VBUS */
+ sg_set_pinsel(63, 0, 8, 4); /* USB3OD -> USB3OD */
+#endif
+}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-void ph1_ld4_pin_init(void)
-{
- u32 tmp;
-
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(158, 0, 8, 4); /* XNFRE -> XNFRE_GB */
- sg_set_pinsel(159, 0, 8, 4); /* XNFWE -> XNFWE_GB */
- sg_set_pinsel(160, 0, 8, 4); /* XFALE -> NFALE_GB */
- sg_set_pinsel(161, 0, 8, 4); /* XFCLE -> NFCLE_GB */
- sg_set_pinsel(162, 0, 8, 4); /* XNFWP -> XFNWP_GB */
- sg_set_pinsel(163, 0, 8, 4); /* XNFCE0 -> XNFCE0_GB */
- sg_set_pinsel(164, 0, 8, 4); /* NANDRYBY0 -> NANDRYBY0_GB */
- sg_set_pinsel(22, 0, 8, 4); /* MMCCLK -> XFNCE1_GB */
- sg_set_pinsel(23, 0, 8, 4); /* MMCCMD -> NANDRYBY1_GB */
- sg_set_pinsel(24, 0, 8, 4); /* MMCDAT0 -> NFD0_GB */
- sg_set_pinsel(25, 0, 8, 4); /* MMCDAT1 -> NFD1_GB */
- sg_set_pinsel(26, 0, 8, 4); /* MMCDAT2 -> NFD2_GB */
- sg_set_pinsel(27, 0, 8, 4); /* MMCDAT3 -> NFD3_GB */
- sg_set_pinsel(28, 0, 8, 4); /* MMCDAT4 -> NFD4_GB */
- sg_set_pinsel(29, 0, 8, 4); /* MMCDAT5 -> NFD5_GB */
- sg_set_pinsel(30, 0, 8, 4); /* MMCDAT6 -> NFD6_GB */
- sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */
-#endif
-
- tmp = readl(SG_IECTRL);
- tmp |= 0x41;
- writel(tmp, SG_IECTRL);
-}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-void ph1_ld6b_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(30, 0, 8, 4); /* XNFRE -> XNFRE */
- sg_set_pinsel(31, 0, 8, 4); /* XNFWE -> XNFWE */
- sg_set_pinsel(32, 0, 8, 4); /* NFALE -> NFALE */
- sg_set_pinsel(33, 0, 8, 4); /* NFCLE -> NFCLE */
- sg_set_pinsel(34, 0, 8, 4); /* XNFWP -> XNFWP */
- sg_set_pinsel(35, 0, 8, 4); /* XNFCE0 -> XNFCE0 */
- sg_set_pinsel(36, 0, 8, 4); /* NRYBY0 -> NRYBY0 */
- sg_set_pinsel(37, 0, 8, 4); /* XNFCE1 -> NRYBY1 */
- sg_set_pinsel(38, 0, 8, 4); /* NRYBY1 -> XNFCE1 */
- sg_set_pinsel(39, 0, 8, 4); /* NFD0 -> NFD0 */
- sg_set_pinsel(40, 0, 8, 4); /* NFD1 -> NFD1 */
- sg_set_pinsel(41, 0, 8, 4); /* NFD2 -> NFD2 */
- sg_set_pinsel(42, 0, 8, 4); /* NFD3 -> NFD3 */
- sg_set_pinsel(43, 0, 8, 4); /* NFD4 -> NFD4 */
- sg_set_pinsel(44, 0, 8, 4); /* NFD5 -> NFD5 */
- sg_set_pinsel(45, 0, 8, 4); /* NFD6 -> NFD6 */
- sg_set_pinsel(46, 0, 8, 4); /* NFD7 -> NFD7 */
-#endif
-
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- sg_set_pinsel(56, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(57, 0, 8, 4); /* USB0OD -> USB0OD */
- sg_set_pinsel(58, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(59, 0, 8, 4); /* USB1OD -> USB1OD */
- sg_set_pinsel(60, 0, 8, 4); /* USB2VBUS -> USB2VBUS */
- sg_set_pinsel(61, 0, 8, 4); /* USB2OD -> USB2OD */
- sg_set_pinsel(62, 0, 8, 4); /* USB3VBUS -> USB3VBUS */
- sg_set_pinsel(63, 0, 8, 4); /* USB3OD -> USB3OD */
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-void ph1_pro4_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(40, 0, 4, 8); /* NFD0 -> NFD0 */
- sg_set_pinsel(41, 0, 4, 8); /* NFD1 -> NFD1 */
- sg_set_pinsel(42, 0, 4, 8); /* NFD2 -> NFD2 */
- sg_set_pinsel(43, 0, 4, 8); /* NFD3 -> NFD3 */
- sg_set_pinsel(44, 0, 4, 8); /* NFD4 -> NFD4 */
- sg_set_pinsel(45, 0, 4, 8); /* NFD5 -> NFD5 */
- sg_set_pinsel(46, 0, 4, 8); /* NFD6 -> NFD6 */
- sg_set_pinsel(47, 0, 4, 8); /* NFD7 -> NFD7 */
- sg_set_pinsel(48, 0, 4, 8); /* NFALE -> NFALE */
- sg_set_pinsel(49, 0, 4, 8); /* NFCLE -> NFCLE */
- sg_set_pinsel(50, 0, 4, 8); /* XNFRE -> XNFRE */
- sg_set_pinsel(51, 0, 4, 8); /* XNFWE -> XNFWE */
- sg_set_pinsel(52, 0, 4, 8); /* XNFWP -> XNFWP */
- sg_set_pinsel(53, 0, 4, 8); /* XNFCE0 -> XNFCE0 */
- sg_set_pinsel(54, 0, 4, 8); /* NRYBY0 -> NRYBY0 */
- /* sg_set_pinsel(131, 1, 4, 8); */ /* RXD2 -> NRYBY1 */
- /* sg_set_pinsel(132, 1, 4, 8); */ /* TXD2 -> XNFCE1 */
-#endif
-
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- sg_set_pinsel(180, 0, 4, 8); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(181, 0, 4, 8); /* USB0OD -> USB0OD */
- sg_set_pinsel(182, 0, 4, 8); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */
-#endif
-
- writel(1, SG_LOADPINCTRL);
-}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-void ph1_pro5_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(19, 0, 4, 8); /* XNFRE -> XNFRE */
- sg_set_pinsel(20, 0, 4, 8); /* XNFWE -> XNFWE */
- sg_set_pinsel(21, 0, 4, 8); /* NFALE -> NFALE */
- sg_set_pinsel(22, 0, 4, 8); /* NFCLE -> NFCLE */
- sg_set_pinsel(23, 0, 4, 8); /* XNFWP -> XNFWP */
- sg_set_pinsel(24, 0, 4, 8); /* XNFCE0 -> XNFCE0 */
- sg_set_pinsel(25, 0, 4, 8); /* NRYBY0 -> NRYBY0 */
- sg_set_pinsel(26, 0, 4, 8); /* XNFCE1 -> XNFCE1 */
- sg_set_pinsel(27, 0, 4, 8); /* NRYBY1 -> NRYBY1 */
- sg_set_pinsel(28, 0, 4, 8); /* NFD0 -> NFD0 */
- sg_set_pinsel(29, 0, 4, 8); /* NFD1 -> NFD1 */
- sg_set_pinsel(30, 0, 4, 8); /* NFD2 -> NFD2 */
- sg_set_pinsel(31, 0, 4, 8); /* NFD3 -> NFD3 */
- sg_set_pinsel(32, 0, 4, 8); /* NFD4 -> NFD4 */
- sg_set_pinsel(33, 0, 4, 8); /* NFD5 -> NFD5 */
- sg_set_pinsel(34, 0, 4, 8); /* NFD6 -> NFD6 */
- sg_set_pinsel(35, 0, 4, 8); /* NFD7 -> NFD7 */
-#endif
-
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- sg_set_pinsel(124, 0, 4, 8); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(125, 0, 4, 8); /* USB0OD -> USB0OD */
- sg_set_pinsel(126, 0, 4, 8); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(127, 0, 4, 8); /* USB1OD -> USB1OD */
-#endif
-
- writel(1, SG_LOADPINCTRL);
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-void ph1_sld3_pin_init(void)
-{
-#ifdef CONFIG_USB_EHCI
- sg_set_pinsel(13, 0, 4, 4); /* USB0OC */
- sg_set_pinsel(14, 1, 4, 4); /* USB0VBUS */
-
- sg_set_pinsel(15, 0, 4, 4); /* USB1OC */
- sg_set_pinsel(16, 1, 4, 4); /* USB1VBUS */
-
- sg_set_pinsel(17, 0, 4, 4); /* USB2OC */
- sg_set_pinsel(18, 1, 4, 4); /* USB2VBUS */
-
- sg_set_pinsel(19, 0, 4, 4); /* USB3OC */
- sg_set_pinsel(20, 1, 4, 4); /* USB3VBUS */
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-void ph1_sld8_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(15, 0, 8, 4); /* XNFRE_GB -> XNFRE_GB */
- sg_set_pinsel(16, 0, 8, 4); /* XNFWE_GB -> XNFWE_GB */
- sg_set_pinsel(17, 0, 8, 4); /* XFALE_GB -> NFALE_GB */
- sg_set_pinsel(18, 0, 8, 4); /* XFCLE_GB -> NFCLE_GB */
- sg_set_pinsel(19, 0, 8, 4); /* XNFWP_GB -> XFNWP_GB */
- sg_set_pinsel(20, 0, 8, 4); /* XNFCE0_GB -> XNFCE0_GB */
- sg_set_pinsel(21, 0, 8, 4); /* NANDRYBY0_GB -> NANDRYBY0_GB */
- sg_set_pinsel(22, 0, 8, 4); /* XFNCE1_GB -> XFNCE1_GB */
- sg_set_pinsel(23, 0, 8, 4); /* NANDRYBY1_GB -> NANDRYBY1_GB */
- sg_set_pinsel(24, 0, 8, 4); /* NFD0_GB -> NFD0_GB */
- sg_set_pinsel(25, 0, 8, 4); /* NFD1_GB -> NFD1_GB */
- sg_set_pinsel(26, 0, 8, 4); /* NFD2_GB -> NFD2_GB */
- sg_set_pinsel(27, 0, 8, 4); /* NFD3_GB -> NFD3_GB */
- sg_set_pinsel(28, 0, 8, 4); /* NFD4_GB -> NFD4_GB */
- sg_set_pinsel(29, 0, 8, 4); /* NFD5_GB -> NFD5_GB */
- sg_set_pinsel(30, 0, 8, 4); /* NFD6_GB -> NFD6_GB */
- sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */
-#endif
-}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+void uniphier_pro4_pin_init(void)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(40, 0, 4, 8); /* NFD0 -> NFD0 */
+ sg_set_pinsel(41, 0, 4, 8); /* NFD1 -> NFD1 */
+ sg_set_pinsel(42, 0, 4, 8); /* NFD2 -> NFD2 */
+ sg_set_pinsel(43, 0, 4, 8); /* NFD3 -> NFD3 */
+ sg_set_pinsel(44, 0, 4, 8); /* NFD4 -> NFD4 */
+ sg_set_pinsel(45, 0, 4, 8); /* NFD5 -> NFD5 */
+ sg_set_pinsel(46, 0, 4, 8); /* NFD6 -> NFD6 */
+ sg_set_pinsel(47, 0, 4, 8); /* NFD7 -> NFD7 */
+ sg_set_pinsel(48, 0, 4, 8); /* NFALE -> NFALE */
+ sg_set_pinsel(49, 0, 4, 8); /* NFCLE -> NFCLE */
+ sg_set_pinsel(50, 0, 4, 8); /* XNFRE -> XNFRE */
+ sg_set_pinsel(51, 0, 4, 8); /* XNFWE -> XNFWE */
+ sg_set_pinsel(52, 0, 4, 8); /* XNFWP -> XNFWP */
+ sg_set_pinsel(53, 0, 4, 8); /* XNFCE0 -> XNFCE0 */
+ sg_set_pinsel(54, 0, 4, 8); /* NRYBY0 -> NRYBY0 */
+ /* sg_set_pinsel(131, 1, 4, 8); */ /* RXD2 -> NRYBY1 */
+ /* sg_set_pinsel(132, 1, 4, 8); */ /* TXD2 -> XNFCE1 */
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ sg_set_pinsel(180, 0, 4, 8); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(181, 0, 4, 8); /* USB0OD -> USB0OD */
+ sg_set_pinsel(182, 0, 4, 8); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */
+#endif
+
+ writel(1, SG_LOADPINCTRL);
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+void uniphier_pro5_pin_init(void)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(19, 0, 4, 8); /* XNFRE -> XNFRE */
+ sg_set_pinsel(20, 0, 4, 8); /* XNFWE -> XNFWE */
+ sg_set_pinsel(21, 0, 4, 8); /* NFALE -> NFALE */
+ sg_set_pinsel(22, 0, 4, 8); /* NFCLE -> NFCLE */
+ sg_set_pinsel(23, 0, 4, 8); /* XNFWP -> XNFWP */
+ sg_set_pinsel(24, 0, 4, 8); /* XNFCE0 -> XNFCE0 */
+ sg_set_pinsel(25, 0, 4, 8); /* NRYBY0 -> NRYBY0 */
+ sg_set_pinsel(26, 0, 4, 8); /* XNFCE1 -> XNFCE1 */
+ sg_set_pinsel(27, 0, 4, 8); /* NRYBY1 -> NRYBY1 */
+ sg_set_pinsel(28, 0, 4, 8); /* NFD0 -> NFD0 */
+ sg_set_pinsel(29, 0, 4, 8); /* NFD1 -> NFD1 */
+ sg_set_pinsel(30, 0, 4, 8); /* NFD2 -> NFD2 */
+ sg_set_pinsel(31, 0, 4, 8); /* NFD3 -> NFD3 */
+ sg_set_pinsel(32, 0, 4, 8); /* NFD4 -> NFD4 */
+ sg_set_pinsel(33, 0, 4, 8); /* NFD5 -> NFD5 */
+ sg_set_pinsel(34, 0, 4, 8); /* NFD6 -> NFD6 */
+ sg_set_pinsel(35, 0, 4, 8); /* NFD7 -> NFD7 */
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ sg_set_pinsel(124, 0, 4, 8); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(125, 0, 4, 8); /* USB0OD -> USB0OD */
+ sg_set_pinsel(126, 0, 4, 8); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(127, 0, 4, 8); /* USB1OD -> USB1OD */
+#endif
+
+ writel(1, SG_LOADPINCTRL);
+}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-void proxstream2_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(30, 8, 8, 4); /* XNFRE -> XNFRE */
- sg_set_pinsel(31, 8, 8, 4); /* XNFWE -> XNFWE */
- sg_set_pinsel(32, 8, 8, 4); /* NFALE -> NFALE */
- sg_set_pinsel(33, 8, 8, 4); /* NFCLE -> NFCLE */
- sg_set_pinsel(34, 8, 8, 4); /* XNFWP -> XNFWP */
- sg_set_pinsel(35, 8, 8, 4); /* XNFCE0 -> XNFCE0 */
- sg_set_pinsel(36, 8, 8, 4); /* NRYBY0 -> NRYBY0 */
- sg_set_pinsel(37, 8, 8, 4); /* XNFCE1 -> NRYBY1 */
- sg_set_pinsel(38, 8, 8, 4); /* NRYBY1 -> XNFCE1 */
- sg_set_pinsel(39, 8, 8, 4); /* NFD0 -> NFD0 */
- sg_set_pinsel(40, 8, 8, 4); /* NFD1 -> NFD1 */
- sg_set_pinsel(41, 8, 8, 4); /* NFD2 -> NFD2 */
- sg_set_pinsel(42, 8, 8, 4); /* NFD3 -> NFD3 */
- sg_set_pinsel(43, 8, 8, 4); /* NFD4 -> NFD4 */
- sg_set_pinsel(44, 8, 8, 4); /* NFD5 -> NFD5 */
- sg_set_pinsel(45, 8, 8, 4); /* NFD6 -> NFD6 */
- sg_set_pinsel(46, 8, 8, 4); /* NFD7 -> NFD7 */
-#endif
-
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- sg_set_pinsel(56, 8, 8, 4); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(57, 8, 8, 4); /* USB0OD -> USB0OD */
- sg_set_pinsel(58, 8, 8, 4); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(59, 8, 8, 4); /* USB1OD -> USB1OD */
- sg_set_pinsel(60, 8, 8, 4); /* USB2VBUS -> USB2VBUS */
- sg_set_pinsel(61, 8, 8, 4); /* USB2OD -> USB2OD */
- sg_set_pinsel(62, 8, 8, 4); /* USB3VBUS -> USB3VBUS */
- sg_set_pinsel(63, 8, 8, 4); /* USB3OD -> USB3OD */
-#endif
-}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+void uniphier_pxs2_pin_init(void)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(30, 8, 8, 4); /* XNFRE -> XNFRE */
+ sg_set_pinsel(31, 8, 8, 4); /* XNFWE -> XNFWE */
+ sg_set_pinsel(32, 8, 8, 4); /* NFALE -> NFALE */
+ sg_set_pinsel(33, 8, 8, 4); /* NFCLE -> NFCLE */
+ sg_set_pinsel(34, 8, 8, 4); /* XNFWP -> XNFWP */
+ sg_set_pinsel(35, 8, 8, 4); /* XNFCE0 -> XNFCE0 */
+ sg_set_pinsel(36, 8, 8, 4); /* NRYBY0 -> NRYBY0 */
+ sg_set_pinsel(37, 8, 8, 4); /* XNFCE1 -> NRYBY1 */
+ sg_set_pinsel(38, 8, 8, 4); /* NRYBY1 -> XNFCE1 */
+ sg_set_pinsel(39, 8, 8, 4); /* NFD0 -> NFD0 */
+ sg_set_pinsel(40, 8, 8, 4); /* NFD1 -> NFD1 */
+ sg_set_pinsel(41, 8, 8, 4); /* NFD2 -> NFD2 */
+ sg_set_pinsel(42, 8, 8, 4); /* NFD3 -> NFD3 */
+ sg_set_pinsel(43, 8, 8, 4); /* NFD4 -> NFD4 */
+ sg_set_pinsel(44, 8, 8, 4); /* NFD5 -> NFD5 */
+ sg_set_pinsel(45, 8, 8, 4); /* NFD6 -> NFD6 */
+ sg_set_pinsel(46, 8, 8, 4); /* NFD7 -> NFD7 */
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ sg_set_pinsel(56, 8, 8, 4); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(57, 8, 8, 4); /* USB0OD -> USB0OD */
+ sg_set_pinsel(58, 8, 8, 4); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(59, 8, 8, 4); /* USB1OD -> USB1OD */
+ sg_set_pinsel(60, 8, 8, 4); /* USB2VBUS -> USB2VBUS */
+ sg_set_pinsel(61, 8, 8, 4); /* USB2OD -> USB2OD */
+ sg_set_pinsel(62, 8, 8, 4); /* USB3VBUS -> USB3VBUS */
+ sg_set_pinsel(63, 8, 8, 4); /* USB3OD -> USB3OD */
+#endif
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+void uniphier_sld3_pin_init(void)
+{
+#ifdef CONFIG_USB_EHCI
+ sg_set_pinsel(13, 0, 4, 4); /* USB0OC */
+ sg_set_pinsel(14, 1, 4, 4); /* USB0VBUS */
+
+ sg_set_pinsel(15, 0, 4, 4); /* USB1OC */
+ sg_set_pinsel(16, 1, 4, 4); /* USB1VBUS */
+
+ sg_set_pinsel(17, 0, 4, 4); /* USB2OC */
+ sg_set_pinsel(18, 1, 4, 4); /* USB2VBUS */
+
+ sg_set_pinsel(19, 0, 4, 4); /* USB3OC */
+ sg_set_pinsel(20, 1, 4, 4); /* USB3VBUS */
+#endif
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(38, 1, 4, 4); /* NFALE_GB, NFCLE_GB */
+ sg_set_pinsel(39, 1, 4, 4); /* XNFRYBY0_GB */
+ sg_set_pinsel(40, 1, 4, 4); /* XNFCE0_GB, XNFRE_GB, XNFWE_GB, XNFWP_GB */
+ sg_set_pinsel(41, 1, 4, 4); /* XNFRYBY1_GB, XNFCE1_GB */
+ sg_set_pinsel(58, 1, 4, 4); /* NFD[0-3]_GB */
+ sg_set_pinsel(59, 1, 4, 4); /* NFD[4-7]_GB */
+#endif
+
+#ifdef CONFIG_MMC_UNIPHIER
+ /* eMMC */
+ sg_set_pinsel(55, 1, 4, 4); /* XERST */
+ sg_set_pinsel(56, 1, 4, 4); /* MMCDAT[0-3] */
+ sg_set_pinsel(57, 1, 4, 4); /* MMCDAT[4-7] */
+ sg_set_pinsel(60, 1, 4, 4); /* MMCCLK, MMCCMD */
+
+ /* SD card */
+ sg_set_pinsel(42, 1, 4, 4); /* SD1CLK, SD1CMD, SD1DAT[0-3] */
+ sg_set_pinsel(43, 1, 4, 4); /* SD1CD */
+ sg_set_pinsel(44, 1, 4, 4); /* SD1WP */
+ sg_set_pinsel(45, 1, 4, 4); /* SDVTCG */
+#endif
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+void uniphier_sld8_pin_init(void)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(15, 0, 8, 4); /* XNFRE_GB -> XNFRE_GB */
+ sg_set_pinsel(16, 0, 8, 4); /* XNFWE_GB -> XNFWE_GB */
+ sg_set_pinsel(17, 0, 8, 4); /* XFALE_GB -> NFALE_GB */
+ sg_set_pinsel(18, 0, 8, 4); /* XFCLE_GB -> NFCLE_GB */
+ sg_set_pinsel(19, 0, 8, 4); /* XNFWP_GB -> XFNWP_GB */
+ sg_set_pinsel(20, 0, 8, 4); /* XNFCE0_GB -> XNFCE0_GB */
+ sg_set_pinsel(21, 0, 8, 4); /* NANDRYBY0_GB -> NANDRYBY0_GB */
+ sg_set_pinsel(22, 0, 8, 4); /* XFNCE1_GB -> XFNCE1_GB */
+ sg_set_pinsel(23, 0, 8, 4); /* NANDRYBY1_GB -> NANDRYBY1_GB */
+ sg_set_pinsel(24, 0, 8, 4); /* NFD0_GB -> NFD0_GB */
+ sg_set_pinsel(25, 0, 8, 4); /* NFD1_GB -> NFD1_GB */
+ sg_set_pinsel(26, 0, 8, 4); /* NFD2_GB -> NFD2_GB */
+ sg_set_pinsel(27, 0, 8, 4); /* NFD3_GB -> NFD3_GB */
+ sg_set_pinsel(28, 0, 8, 4); /* NFD4_GB -> NFD4_GB */
+ sg_set_pinsel(29, 0, 8, 4); /* NFD5_GB -> NFD5_GB */
+ sg_set_pinsel(30, 0, 8, 4); /* NFD6_GB -> NFD6_GB */
+ sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */
+#endif
+}
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += pll-init-ph1-sld3.o \
- pll-spectrum-ph1-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += pll-init-ph1-ld4.o \
- pll-spectrum-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += pll-init-ph1-pro4.o \
- pll-spectrum-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += pll-init-ph1-sld8.o \
- pll-spectrum-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += pll-init-sld3.o pll-spectrum-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4) += pll-init-ld4.o pll-spectrum-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += pll-init-pro4.o pll-spectrum-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pll-init-sld8.o pll-spectrum-ld4.o
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
+
+#undef DPLL_SSC_RATE_1PER
+
+static int dpll_init(unsigned int dram_freq)
+{
+ u32 tmp;
+
+ /*
+ * Set Frequency
+ * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
+ * to FOUT (DPLLCTRL.bit[29:20])
+ */
+ tmp = readl(SC_DPLLCTRL);
+ tmp &= ~0x000f0000;
+ switch (dram_freq) {
+ case 1333:
+ tmp |= 0x000d0000;
+ break;
+ case 1600:
+ tmp |= 0x000c0000;
+ break;
+ default:
+ pr_err("Unsupported frequency");
+ return -EINVAL;
+ }
+
+#if defined(DPLL_SSC_RATE_1PER)
+ tmp &= ~SC_DPLLCTRL_SSC_RATE;
+#else
+ tmp |= SC_DPLLCTRL_SSC_RATE;
+#endif
+ writel(tmp, SC_DPLLCTRL);
+
+ tmp = readl(SC_DPLLCTRL2);
+ tmp |= SC_DPLLCTRL2_NRSTDS;
+ writel(tmp, SC_DPLLCTRL2);
+
+ return 0;
+}
+
+static void upll_init(void)
+{
+ u32 tmp, clk_mode_upll, clk_mode_axosel;
+
+ tmp = readl(SG_PINMON0);
+ clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
+ clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+ /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
+ tmp = readl(SC_UPLLCTRL);
+ tmp &= ~0x18000000;
+ writel(tmp, SC_UPLLCTRL);
+
+ if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+ /* AXO: 25MHz */
+ tmp &= ~0x07ffffff;
+ tmp |= 0x0228f5c0;
+ } else {
+ /* AXO: default 24.576MHz */
+ tmp &= ~0x07ffffff;
+ tmp |= 0x02328000;
+ }
+ }
+
+ writel(tmp, SC_UPLLCTRL);
+
+ /* set 1 to K_LD(UPLLCTRL.bit[27]) */
+ tmp |= 0x08000000;
+ writel(tmp, SC_UPLLCTRL);
+
+ /* wait 10 usec */
+ udelay(10);
+
+ /* set 1 to SNRT(UPLLCTRL.bit[28]) */
+ tmp |= 0x10000000;
+ writel(tmp, SC_UPLLCTRL);
+}
+
+static void vpll_init(void)
+{
+ u32 tmp, clk_mode_axosel;
+
+ tmp = readl(SG_PINMON0);
+ clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+ /* set 1 to VPLA27WP and VPLA27WP */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+
+ /* Set 0 to VPLA_K_LD and VPLB_K_LD */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* Set 0 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+ /* AXO: 25MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066664;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066664;
+ writel(tmp, SC_VPLL27BCTRL3);
+ } else {
+ /* AXO: default 24.576MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27BCTRL3);
+ }
+
+ /* Set 1 to VPLA_K_LD and VPLB_K_LD */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* wait 10 usec */
+ udelay(10);
+
+ /* Set 0 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ /* set 0 to VPLA27WP and VPLA27WP */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp &= ~0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp |= ~0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+}
+
+int uniphier_ld4_pll_init(const struct uniphier_board_data *bd)
+{
+ int ret;
+
+ ret = dpll_init(bd->dram_freq);
+ if (ret)
+ return ret;
+ upll_init();
+ vpll_init();
+
+ /*
+ * Wait 500 usec until dpll get stable
+ * We wait 10 usec in upll_init() and vpll_init()
+ * so 20 usec can be saved here.
+ */
+ udelay(480);
+
+ return 0;
+}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-#include "../sg-regs.h"
-
-#undef DPLL_SSC_RATE_1PER
-
-static int dpll_init(unsigned int dram_freq)
-{
- u32 tmp;
-
- /*
- * Set Frequency
- * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
- * to FOUT (DPLLCTRL.bit[29:20])
- */
- tmp = readl(SC_DPLLCTRL);
- tmp &= ~0x000f0000;
- switch (dram_freq) {
- case 1333:
- tmp |= 0x000d0000;
- break;
- case 1600:
- tmp |= 0x000c0000;
- break;
- default:
- pr_err("Unsupported frequency");
- return -EINVAL;
- }
-
-#if defined(DPLL_SSC_RATE_1PER)
- tmp &= ~SC_DPLLCTRL_SSC_RATE;
-#else
- tmp |= SC_DPLLCTRL_SSC_RATE;
-#endif
- writel(tmp, SC_DPLLCTRL);
-
- tmp = readl(SC_DPLLCTRL2);
- tmp |= SC_DPLLCTRL2_NRSTDS;
- writel(tmp, SC_DPLLCTRL2);
-
- return 0;
-}
-
-static void upll_init(void)
-{
- u32 tmp, clk_mode_upll, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
- tmp = readl(SC_UPLLCTRL);
- tmp &= ~0x18000000;
- writel(tmp, SC_UPLLCTRL);
-
- if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x0228f5c0;
- } else {
- /* AXO: default 24.576MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x02328000;
- }
- }
-
- writel(tmp, SC_UPLLCTRL);
-
- /* set 1 to K_LD(UPLLCTRL.bit[27]) */
- tmp |= 0x08000000;
- writel(tmp, SC_UPLLCTRL);
-
- /* wait 10 usec */
- udelay(10);
-
- /* set 1 to SNRT(UPLLCTRL.bit[28]) */
- tmp |= 0x10000000;
- writel(tmp, SC_UPLLCTRL);
-}
-
-static void vpll_init(void)
-{
- u32 tmp, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 1 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-
- /* Set 0 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
-
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27BCTRL3);
- } else {
- /* AXO: default 24.576MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
- }
-
- /* Set 1 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* wait 10 usec */
- udelay(10);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* set 0 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-}
-
-int ph1_ld4_pll_init(const struct uniphier_board_data *bd)
-{
- int ret;
-
- ret = dpll_init(bd->dram_freq);
- if (ret)
- return ret;
- upll_init();
- vpll_init();
-
- /*
- * Wait 500 usec until dpll get stable
- * We wait 10 usec in upll_init() and vpll_init()
- * so 20 usec can be saved here.
- */
- udelay(480);
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-#include "../sg-regs.h"
-
-#undef DPLL_SSC_RATE_1PER
-
-static int dpll_init(unsigned int dram_freq)
-{
- u32 tmp;
-
- /*
- * Set Frequency
- * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
- * to FOUT ( DPLLCTRL.bit[29:20] )
- */
- tmp = readl(SC_DPLLCTRL);
- tmp &= ~(0x000f0000);
- switch (dram_freq) {
- case 1333:
- tmp |= 0x000d0000;
- break;
- case 1600:
- tmp |= 0x000c0000;
- break;
- default:
- pr_err("Unsupported frequency");
- return -EINVAL;
- }
-
- /*
- * Set Moduration rate
- * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
- */
-#if defined(DPLL_SSC_RATE_1PER)
- tmp &= ~0x00008000;
-#else
- tmp |= 0x00008000;
-#endif
- writel(tmp, SC_DPLLCTRL);
-
- tmp = readl(SC_DPLLCTRL2);
- tmp |= SC_DPLLCTRL2_NRSTDS;
- writel(tmp, SC_DPLLCTRL2);
-
- return 0;
-}
-
-static void vpll_init(void)
-{
- u32 tmp, clk_mode_axosel;
-
- /* Set VPLL27A & VPLL27B */
- tmp = readl(SG_PINMON0);
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
- return;
-
- /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
- tmp = readl(SC_VPLL27ACTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-
- /* Unset VPLA_K_LD and VPLB_K_LD bit */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Set VPLA_M and VPLB_M to 0x20 */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
-
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
- /* Set VPLA_K and VPLB_K for AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066666;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066666;
- writel(tmp, SC_VPLL27BCTRL3);
- } else {
- /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
- }
-
- /* wait 1 usec */
- udelay(1);
-
- /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Unset VPLA_SNRST and VPLB_SNRST bit */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
- tmp = readl(SC_VPLL27ACTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-}
-
-int ph1_pro4_pll_init(const struct uniphier_board_data *bd)
-{
- int ret;
-
- ret = dpll_init(bd->dram_freq);
- if (ret)
- return ret;
- vpll_init();
-
- /*
- * Wait 500 usec until dpll get stable
- * We wait 1 usec in vpll_init() so 1 usec can be saved here.
- */
- udelay(499);
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include "../init.h"
-
-int ph1_sld3_pll_init(const struct uniphier_board_data *bd)
-{
- /* add pll init code here */
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-#include "../sg-regs.h"
-
-static void dpll_init(void)
-{
- u32 tmp;
- /*
- * Set DPLL SSC parameters for DPLLCTRL3
- * [23] DIVN_TEST 0x1
- * [22:16] DIVN 0x50
- * [10] FREFSEL_TEST 0x1
- * [9:8] FREFSEL 0x2
- * [4] ICPD_TEST 0x1
- * [3:0] ICPD 0xb
- */
- tmp = readl(SC_DPLLCTRL3);
- tmp &= ~0x00ff0717;
- tmp |= 0x00d0061b;
- writel(tmp, SC_DPLLCTRL3);
-
- /*
- * Set DPLL SSC parameters for DPLLCTRL
- * <-1%> <-2%>
- * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
- * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
- */
- tmp = readl(SC_DPLLCTRL);
- tmp &= ~0x3ff07fff;
-#ifdef CONFIG_DPLL_SSC_RATE_1PER
- tmp |= 0x084018bf;
-#else
- tmp |= 0x084031a6;
-#endif
- writel(tmp, SC_DPLLCTRL);
-
- /*
- * Set DPLL SSC parameters for DPLLCTRL2
- * [31:29] SSC_STEP 0
- * [27] SSC_REG_REF 1
- * [26:20] SSC_M 79 (0x4f)
- * [19:0] SSC_K 964689 (0xeb851)
- */
- tmp = readl(SC_DPLLCTRL2);
- tmp &= ~0xefffffff;
- tmp |= 0x0cfeb851;
- writel(tmp, SC_DPLLCTRL2);
-}
-
-static void upll_init(void)
-{
- u32 tmp, clk_mode_upll, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
- tmp = readl(SC_UPLLCTRL);
- tmp &= ~0x18000000;
- writel(tmp, SC_UPLLCTRL);
-
- if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x0228f5c0;
- } else {
- /* AXO: default 24.576MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x02328000;
- }
- }
-
- writel(tmp, SC_UPLLCTRL);
-
- /* set 1 to K_LD(UPLLCTRL.bit[27]) */
- tmp |= 0x08000000;
- writel(tmp, SC_UPLLCTRL);
-
- /* wait 10 usec */
- udelay(10);
-
- /* set 1 to SNRT(UPLLCTRL.bit[28]) */
- tmp |= 0x10000000;
- writel(tmp, SC_UPLLCTRL);
-}
-
-static void vpll_init(void)
-{
- u32 tmp, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 1 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-
- /* Set 0 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
-
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27BCTRL3);
- } else {
- /* AXO: default 24.576MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
- }
-
- /* Set 1 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* wait 10 usec */
- udelay(10);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* set 0 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-}
-
-int ph1_sld8_pll_init(const struct uniphier_board_data *bd)
-{
- dpll_init();
- upll_init();
- vpll_init();
-
- /*
- * Wait 500 usec until dpll get stable
- * We wait 10 usec in upll_init() and vpll_init()
- * so 20 usec can be saved here.
- */
- udelay(480);
-
- return 0;
-}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
+
+#undef DPLL_SSC_RATE_1PER
+
+static int dpll_init(unsigned int dram_freq)
+{
+ u32 tmp;
+
+ /*
+ * Set Frequency
+ * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
+ * to FOUT ( DPLLCTRL.bit[29:20] )
+ */
+ tmp = readl(SC_DPLLCTRL);
+ tmp &= ~(0x000f0000);
+ switch (dram_freq) {
+ case 1333:
+ tmp |= 0x000d0000;
+ break;
+ case 1600:
+ tmp |= 0x000c0000;
+ break;
+ default:
+ pr_err("Unsupported frequency");
+ return -EINVAL;
+ }
+
+ /*
+ * Set Moduration rate
+ * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
+ */
+#if defined(DPLL_SSC_RATE_1PER)
+ tmp &= ~0x00008000;
+#else
+ tmp |= 0x00008000;
+#endif
+ writel(tmp, SC_DPLLCTRL);
+
+ tmp = readl(SC_DPLLCTRL2);
+ tmp |= SC_DPLLCTRL2_NRSTDS;
+ writel(tmp, SC_DPLLCTRL2);
+
+ return 0;
+}
+
+static void vpll_init(void)
+{
+ u32 tmp, clk_mode_axosel;
+
+ /* Set VPLL27A & VPLL27B */
+ tmp = readl(SG_PINMON0);
+ clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+ /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
+ return;
+
+ /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+
+ /* Unset VPLA_K_LD and VPLB_K_LD bit */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* Set VPLA_M and VPLB_M to 0x20 */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
+ /* Set VPLA_K and VPLB_K for AXO: 25MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066666;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066666;
+ writel(tmp, SC_VPLL27BCTRL3);
+ } else {
+ /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27BCTRL3);
+ }
+
+ /* wait 1 usec */
+ udelay(1);
+
+ /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* Unset VPLA_SNRST and VPLB_SNRST bit */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp &= ~0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp &= ~0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+}
+
+int uniphier_pro4_pll_init(const struct uniphier_board_data *bd)
+{
+ int ret;
+
+ ret = dpll_init(bd->dram_freq);
+ if (ret)
+ return ret;
+ vpll_init();
+
+ /*
+ * Wait 500 usec until dpll get stable
+ * We wait 1 usec in vpll_init() so 1 usec can be saved here.
+ */
+ udelay(499);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "../init.h"
+
+int uniphier_sld3_pll_init(const struct uniphier_board_data *bd)
+{
+ /* add pll init code here */
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
+
+static void dpll_init(void)
+{
+ u32 tmp;
+ /*
+ * Set DPLL SSC parameters for DPLLCTRL3
+ * [23] DIVN_TEST 0x1
+ * [22:16] DIVN 0x50
+ * [10] FREFSEL_TEST 0x1
+ * [9:8] FREFSEL 0x2
+ * [4] ICPD_TEST 0x1
+ * [3:0] ICPD 0xb
+ */
+ tmp = readl(SC_DPLLCTRL3);
+ tmp &= ~0x00ff0717;
+ tmp |= 0x00d0061b;
+ writel(tmp, SC_DPLLCTRL3);
+
+ /*
+ * Set DPLL SSC parameters for DPLLCTRL
+ * <-1%> <-2%>
+ * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
+ * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
+ */
+ tmp = readl(SC_DPLLCTRL);
+ tmp &= ~0x3ff07fff;
+#ifdef CONFIG_DPLL_SSC_RATE_1PER
+ tmp |= 0x084018bf;
+#else
+ tmp |= 0x084031a6;
+#endif
+ writel(tmp, SC_DPLLCTRL);
+
+ /*
+ * Set DPLL SSC parameters for DPLLCTRL2
+ * [31:29] SSC_STEP 0
+ * [27] SSC_REG_REF 1
+ * [26:20] SSC_M 79 (0x4f)
+ * [19:0] SSC_K 964689 (0xeb851)
+ */
+ tmp = readl(SC_DPLLCTRL2);
+ tmp &= ~0xefffffff;
+ tmp |= 0x0cfeb851;
+ writel(tmp, SC_DPLLCTRL2);
+}
+
+static void upll_init(void)
+{
+ u32 tmp, clk_mode_upll, clk_mode_axosel;
+
+ tmp = readl(SG_PINMON0);
+ clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
+ clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+ /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
+ tmp = readl(SC_UPLLCTRL);
+ tmp &= ~0x18000000;
+ writel(tmp, SC_UPLLCTRL);
+
+ if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+ /* AXO: 25MHz */
+ tmp &= ~0x07ffffff;
+ tmp |= 0x0228f5c0;
+ } else {
+ /* AXO: default 24.576MHz */
+ tmp &= ~0x07ffffff;
+ tmp |= 0x02328000;
+ }
+ }
+
+ writel(tmp, SC_UPLLCTRL);
+
+ /* set 1 to K_LD(UPLLCTRL.bit[27]) */
+ tmp |= 0x08000000;
+ writel(tmp, SC_UPLLCTRL);
+
+ /* wait 10 usec */
+ udelay(10);
+
+ /* set 1 to SNRT(UPLLCTRL.bit[28]) */
+ tmp |= 0x10000000;
+ writel(tmp, SC_UPLLCTRL);
+}
+
+static void vpll_init(void)
+{
+ u32 tmp, clk_mode_axosel;
+
+ tmp = readl(SG_PINMON0);
+ clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+ /* set 1 to VPLA27WP and VPLA27WP */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+
+ /* Set 0 to VPLA_K_LD and VPLB_K_LD */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* Set 0 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+ /* AXO: 25MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066664;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066664;
+ writel(tmp, SC_VPLL27BCTRL3);
+ } else {
+ /* AXO: default 24.576MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27BCTRL3);
+ }
+
+ /* Set 1 to VPLA_K_LD and VPLB_K_LD */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* wait 10 usec */
+ udelay(10);
+
+ /* Set 0 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ /* set 0 to VPLA27WP and VPLA27WP */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp &= ~0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp |= ~0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+}
+
+int uniphier_sld8_pll_init(const struct uniphier_board_data *bd)
+{
+ dpll_init();
+ upll_init();
+ vpll_init();
+
+ /*
+ * Wait 500 usec until dpll get stable
+ * We wait 10 usec in upll_init() and vpll_init()
+ * so 20 usec can be saved here.
+ */
+ udelay(480);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+
+ tmp = readl(SC_DPLLCTRL);
+ tmp |= SC_DPLLCTRL_SSC_EN;
+ writel(tmp, SC_DPLLCTRL);
+
+ return 0;
+}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-
-int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd)
-{
- u32 tmp;
-
- tmp = readl(SC_DPLLCTRL);
- tmp |= SC_DPLLCTRL_SSC_EN;
- writel(tmp, SC_DPLLCTRL);
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-
-int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd)
-{
- u32 tmp;
-
- tmp = readl(SC_DPLLCTRL);
- tmp |= SC_DPLLCTRL_SSC_EN;
- writel(tmp, SC_DPLLCTRL);
-
- return 0;
-}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+int uniphier_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+
+ tmp = readl(SC_DPLLCTRL);
+ tmp |= SC_DPLLCTRL_SSC_EN;
+ writel(tmp, SC_DPLLCTRL);
+
+ return 0;
+}
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += sbc-ph1-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += sbc-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += sbc-ph1-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += sbc-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += sbc-ph1-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += sbc-proxstream2.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += sbc-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += sbc-admulti.o sbc-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4) += sbc-savepin.o sbc-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += sbc-savepin.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += sbc-savepin.o sbc-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += sbc-savepin.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-savepin.o sbc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-savepin.o sbc-pxs2.o
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+#include "sbc-regs.h"
+
+#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
+#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
+#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
+
+#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
+#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
+#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
+
+int uniphier_sbc_init_admulti(const struct uniphier_board_data *bd)
+{
+ /*
+ * Only CS1 is connected to support card.
+ * BKSZ[1:0] should be set to "01".
+ */
+ writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
+ writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
+ writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
+
+ if (boot_is_swapped()) {
+ /*
+ * Boot Swap On: boot from external NOR/SRAM
+ * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
+ *
+ * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
+ * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
+ */
+ writel(0x0000bc01, SBBASE0);
+ } else {
+ /*
+ * Boot Swap Off: boot from mask ROM
+ * 0x40000000-0x41ffffff: mask ROM
+ * 0x42000000-0x43efffff: memory bank (31MB)
+ * 0x43f00000-0x43ffffff: peripherals (1MB)
+ */
+ writel(0x0000be01, SBBASE0); /* dummy */
+ writel(0x0200be01, SBBASE1);
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "sbc-regs.h"
+
+int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+
+ /* system bus output enable */
+ tmp = readl(PC0CTRL);
+ tmp &= 0xfffffcff;
+ writel(tmp, PC0CTRL);
+
+ return 0;
+}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-#include "sbc-regs.h"
-
-int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
-{
- u32 tmp;
-
- /* system bus output enable */
- tmp = readl(PC0CTRL);
- tmp &= 0xfffffcff;
- writel(tmp, PC0CTRL);
-
- /*
- * Only CS1 is connected to support card.
- * BKSZ[1:0] should be set to "01".
- */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
-
- if (boot_is_swapped()) {
- /*
- * Boot Swap On: boot from external NOR/SRAM
- * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
- *
- * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
- * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
- */
- writel(0x0000bc01, SBBASE0);
- } else {
- /*
- * Boot Swap Off: boot from mask ROM
- * 0x40000000-0x41ffffff: mask ROM
- * 0x42000000-0x43efffff: memory bank (31MB)
- * 0x43f00000-0x43ffffff: peripherals (1MB)
- */
- writel(0x0000be01, SBBASE0); /* dummy */
- writel(0x0200be01, SBBASE1);
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-#include "sbc-regs.h"
-
-int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
-{
- /*
- * Only CS1 is connected to support card.
- * BKSZ[1:0] should be set to "01".
- */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
-
- if (boot_is_swapped()) {
- /*
- * Boot Swap On: boot from external NOR/SRAM
- * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
- *
- * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
- * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
- */
- writel(0x0000bc01, SBBASE0);
- } else {
- /*
- * Boot Swap Off: boot from mask ROM
- * 0x40000000-0x41ffffff: mask ROM
- * 0x42000000-0x43efffff: memory bank (31MB)
- * 0x43f00000-0x43ffffff: peripherals (1MB)
- */
- writel(0x0000be01, SBBASE0); /* dummy */
- writel(0x0200be01, SBBASE1);
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-#include "sbc-regs.h"
-
-int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
-{
- /* only address/data multiplex mode is supported */
-
- /*
- * Only CS1 is connected to support card.
- * BKSZ[1:0] should be set to "01".
- */
- writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
- writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
- writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
-
- if (boot_is_swapped()) {
- /*
- * Boot Swap On: boot from external NOR/SRAM
- * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
- *
- * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
- * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
- */
- writel(0x0000bc01, SBBASE0);
- } else {
- /*
- * Boot Swap Off: boot from mask ROM
- * 0x40000000-0x41ffffff: mask ROM
- * 0x42000000-0x43efffff: memory bank (31MB)
- * 0x43f00000-0x43ffffff: peripherals (1MB)
- */
- writel(0x0000be01, SBBASE0); /* dummy */
- writel(0x0200be01, SBBASE1);
- }
-
- sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-#include "sbc-regs.h"
-
-int proxstream2_sbc_init(const struct uniphier_board_data *bd)
-{
- /* necessary for ROM boot ?? */
- /* system bus output enable */
- writel(0x17, PC0CTRL);
-
- /*
- * Only CS1 is connected to support card.
- * BKSZ[1:0] should be set to "01".
- */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
-
- if (boot_is_swapped()) {
- /*
- * Boot Swap On: boot from external NOR/SRAM
- * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
- *
- * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
- * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
- */
- writel(0x0000bc01, SBBASE0);
- } else {
- /*
- * Boot Swap Off: boot from mask ROM
- * 0x40000000-0x41ffffff: mask ROM
- * 0x42000000-0x43efffff: memory bank (31MB)
- * 0x43f00000-0x43ffffff: peripherals (1MB)
- */
- writel(0x0000be01, SBBASE0); /* dummy */
- writel(0x0200be01, SBBASE1);
- }
-
- return 0;
-}
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "sbc-regs.h"
+
+int uniphier_pxs2_sbc_init(const struct uniphier_board_data *bd)
+{
+ /* necessary for ROM boot ?? */
+ /* system bus output enable */
+ writel(0x17, PC0CTRL);
+
+ return 0;
+}
#define SBCTRL73 SBCTRL(7, 3)
#define SBCTRL74 (SBCTRL_BASE + 0x170)
-/* slower but LED works */
-#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
-#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
-#define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
-#define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
-
-/* faster but LED does not work */
-#define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
-#define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
-/* NOR flash needs more wait counts than SRAM */
-#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
-#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
-
-#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
-#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
-#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
-
-#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
-#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
-#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
-
#define PC0CTRL 0x598000c0
#define ROM_BOOT_ROMRSV2 0x59801208
--- /dev/null
+/*
+ * Copyright (C) 2011-2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "sbc-regs.h"
+
+/* slower but LED works */
+#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
+#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
+#define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
+#define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
+
+/* faster but LED does not work */
+#define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
+#define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
+/* NOR flash needs more wait counts than SRAM */
+#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
+#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
+
+int uniphier_sbc_init_savepin(const struct uniphier_board_data *bd)
+{
+ /*
+ * Only CS1 is connected to support card.
+ * BKSZ[1:0] should be set to "01".
+ */
+ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
+ writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
+ writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
+ writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
+
+ if (boot_is_swapped()) {
+ /*
+ * Boot Swap On: boot from external NOR/SRAM
+ * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
+ *
+ * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
+ * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
+ */
+ writel(0x0000bc01, SBBASE0);
+ } else {
+ /*
+ * Boot Swap Off: boot from mask ROM
+ * 0x40000000-0x41ffffff: mask ROM
+ * 0x42000000-0x43efffff: memory bank (31MB)
+ * 0x43f00000-0x43ffffff: peripherals (1MB)
+ */
+ writel(0x0000be01, SBBASE0); /* dummy */
+ writel(0x0200be01, SBBASE1);
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+int uniphier_sld3_sbc_init(const struct uniphier_board_data *bd)
+{
+ sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */
+
+ return 0;
+}
#ifndef ARCH_SC_REGS_H
#define ARCH_SC_REGS_H
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
#define SC_BASE_ADDR 0xf1840000
#else
#define SC_BASE_ADDR 0x61840000
--- /dev/null
+/*
+ * UniPhier SC (System Control) block registers for ARMv8 SoCs
+ *
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef SC64_REGS_H
+#define SC64_REGS_H
+
+#define SC_BASE_ADDR 0x61840000
+
+#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
+#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
+#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
+#define SC_RSTCTRL4_ETHER (1 << 6)
+#define SC_RSTCTRL4_NAND (1 << 0)
+#define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010)
+#define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014)
+#define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018)
+#define SC_RSTCTRL7_UMCSB (1 << 16)
+#define SC_RSTCTRL7_UMCA2 (1 << 10)
+#define SC_RSTCTRL7_UMCA1 (1 << 9)
+#define SC_RSTCTRL7_UMCA0 (1 << 8)
+#define SC_RSTCTRL7_UMC32 (1 << 2)
+#define SC_RSTCTRL7_UMC31 (1 << 1)
+#define SC_RSTCTRL7_UMC30 (1 << 0)
+
+#define SC_CLKCTRL (SC_BASE_ADDR | 0x2100)
+#define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108)
+#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
+#define SC_CLKCTRL4_PERI (1 << 7)
+#define SC_CLKCTRL4_ETHER (1 << 6)
+#define SC_CLKCTRL4_NAND (1 << 0)
+#define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110)
+#define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114)
+#define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118)
+#define SC_CLKCTRL7_UMCSB (1 << 16)
+#define SC_CLKCTRL7_UMC32 (1 << 2)
+#define SC_CLKCTRL7_UMC31 (1 << 1)
+#define SC_CLKCTRL7_UMC30 (1 << 0)
+
+#endif /* SC64_REGS_H */
writel(tmp, reg);
}
+static inline void sg_set_iectrl(unsigned pin)
+{
+ unsigned bit = pin % 32;
+ unsigned long reg = SG_IECTRL + pin / 32 * 4;
+ u32 tmp;
+
+ tmp = readl(reg);
+ tmp |= 1 << bit;
+ writel(tmp, reg);
+}
+
#endif /* __ASSEMBLY__ */
#endif /* ARCH_SG_REGS_H */
#define __MACH_SOC_INFO_H__
enum uniphier_soc_id {
- SOC_UNIPHIER_PH1_SLD3,
- SOC_UNIPHIER_PH1_LD4,
- SOC_UNIPHIER_PH1_PRO4,
- SOC_UNIPHIER_PH1_SLD8,
- SOC_UNIPHIER_PH1_PRO5,
- SOC_UNIPHIER_PROXSTREAM2,
- SOC_UNIPHIER_PH1_LD6B,
- SOC_UNIPHIER_PH1_LD11,
- SOC_UNIPHIER_PH1_LD20,
+ SOC_UNIPHIER_SLD3,
+ SOC_UNIPHIER_LD4,
+ SOC_UNIPHIER_PRO4,
+ SOC_UNIPHIER_SLD8,
+ SOC_UNIPHIER_PRO5,
+ SOC_UNIPHIER_PXS2,
+ SOC_UNIPHIER_LD6B,
+ SOC_UNIPHIER_LD11,
+ SOC_UNIPHIER_LD20,
SOC_UNIPHIER_UNKNOWN,
};
#define UNIPHIER_NR_ENABLED_SOCS \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD4) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO5) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD11) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD20)
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_SLD3) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_LD4) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PRO4) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_SLD8) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PRO5) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PXS2) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_LD6B) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_LD11) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_LD20)
#define UNIPHIER_MULTI_SOC ((UNIPHIER_NR_ENABLED_SOCS) > 1)
#else
static inline enum uniphier_soc_id uniphier_get_soc_type(void)
{
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
- return SOC_UNIPHIER_PH1_SLD3;
+#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
+ return SOC_UNIPHIER_SLD3;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
- return SOC_UNIPHIER_PH1_LD4;
+#if defined(CONFIG_ARCH_UNIPHIER_LD4)
+ return SOC_UNIPHIER_LD4;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
- return SOC_UNIPHIER_PH1_PRO4;
+#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
+ return SOC_UNIPHIER_PRO4;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
- return SOC_UNIPHIER_PH1_SLD8;
+#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
+ return SOC_UNIPHIER_SLD8;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
- return SOC_UNIPHIER_PH1_PRO5;
+#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
+ return SOC_UNIPHIER_PRO5;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
- return SOC_UNIPHIER_PROXSTREAM2;
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
+ return SOC_UNIPHIER_PXS2;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
- return SOC_UNIPHIER_PH1_LD6B;
+#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
+ return SOC_UNIPHIER_LD6B;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD11)
- return SOC_UNIPHIER_PH1_LD11;
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+ return SOC_UNIPHIER_LD11;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD20)
- return SOC_UNIPHIER_PH1_LD20;
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+ return SOC_UNIPHIER_LD20;
#endif
return SOC_UNIPHIER_UNKNOWN;
enum uniphier_soc_id ret;
switch ((revision & SG_REVISION_TYPE_MASK) >> SG_REVISION_TYPE_SHIFT) {
-#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3
+#ifdef CONFIG_ARCH_UNIPHIER_SLD3
case 0x25:
- ret = SOC_UNIPHIER_PH1_SLD3;
+ ret = SOC_UNIPHIER_SLD3;
break;
#endif
-#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD4
+#ifdef CONFIG_ARCH_UNIPHIER_LD4
case 0x26:
- ret = SOC_UNIPHIER_PH1_LD4;
+ ret = SOC_UNIPHIER_LD4;
break;
#endif
-#ifdef CONFIG_ARCH_UNIPHIER_PH1_PRO4
+#ifdef CONFIG_ARCH_UNIPHIER_PRO4
case 0x28:
- ret = SOC_UNIPHIER_PH1_PRO4;
+ ret = SOC_UNIPHIER_PRO4;
break;
#endif
-#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD8
+#ifdef CONFIG_ARCH_UNIPHIER_SLD8
case 0x29:
- ret = SOC_UNIPHIER_PH1_SLD8;
+ ret = SOC_UNIPHIER_SLD8;
break;
#endif
-#ifdef CONFIG_ARCH_UNIPHIER_PH1_PRO5
+#ifdef CONFIG_ARCH_UNIPHIER_PRO5
case 0x2A:
- ret = SOC_UNIPHIER_PH1_PRO5;
+ ret = SOC_UNIPHIER_PRO5;
break;
#endif
-#ifdef CONFIG_ARCH_UNIPHIER_PROXSTREAM2
+#ifdef CONFIG_ARCH_UNIPHIER_PXS2
case 0x2E:
- ret = SOC_UNIPHIER_PROXSTREAM2;
+ ret = SOC_UNIPHIER_PXS2;
break;
#endif
-#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD6B
+#ifdef CONFIG_ARCH_UNIPHIER_LD6B
case 0x2F:
- ret = SOC_UNIPHIER_PH1_LD6B;
+ ret = SOC_UNIPHIER_LD6B;
break;
#endif
-#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD11
+#ifdef CONFIG_ARCH_UNIPHIER_LD11
case 0x31:
- ret = SOC_UNIPHIER_PH1_LD11;
+ ret = SOC_UNIPHIER_LD11;
break;
#endif
-#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD20
+#ifdef CONFIG_ARCH_UNIPHIER_LD20
case 0x32:
- ret = SOC_UNIPHIER_PH1_LD20;
+ ret = SOC_UNIPHIER_LD20;
break;
#endif
default:
extern void zynq_ddrc_init(void);
extern unsigned int zynq_get_silicon_version(void);
+int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
+
/* Driver extern functions */
extern void ps7_init(void);
#include <common.h>
#include <command.h>
+#include <fdtdec.h>
#include <malloc.h>
#include <asm/microblaze_intc.h>
#include <asm/asm.h>
+DECLARE_GLOBAL_DATA_PTR;
+
void enable_interrupts(void)
{
debug("Enable interrupts for the whole CPU\n");
int interrupt_init(void)
{
int i;
+ const void *blob = gd->fdt_blob;
+ int node = 0;
+
+ debug("INTC: Initialization\n");
+
+ node = fdt_node_offset_by_compatible(blob, node,
+ "xlnx,xps-intc-1.00.a");
+ if (node != -1) {
+ fdt_addr_t base = fdtdec_get_addr(blob, node, "reg");
+ if (base == FDT_ADDR_T_NONE)
+ return -1;
+
+ debug("INTC: Base addr %lx\n", base);
+ intc = (microblaze_intc_t *)base;
+ irq_no = fdtdec_get_int(blob, node, "xlnx,num-intr-inputs", 0);
+ debug("INTC: IRQ NO %x\n", irq_no);
+ } else {
+ return node;
+ }
-#if defined(CONFIG_SYS_INTC_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM)
- intc = (microblaze_intc_t *)CONFIG_SYS_INTC_0_ADDR;
- irq_no = CONFIG_SYS_INTC_0_NUM;
-#endif
if (irq_no) {
vecs = calloc(1, sizeof(struct irq_action) * irq_no);
if (vecs == NULL) {
*/
#include <common.h>
+#include <fdtdec.h>
#include <asm/microblaze_timer.h>
#include <asm/microblaze_intc.h>
+DECLARE_GLOBAL_DATA_PTR;
+
volatile int timestamp = 0;
microblaze_timer_t *tmr;
i = get_timer(0);
while ((get_timer(0) - i) < (usec / 1000))
;
- } else {
- for (i = 0; i < (usec * XILINX_CLOCK_FREQ / 10000000); i++)
- ;
}
}
int irq = -1;
u32 preload = 0;
u32 ret = 0;
+ const void *blob = gd->fdt_blob;
+ int node = 0;
+ u32 cell[2];
-#if defined(CONFIG_SYS_TIMER_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM)
- preload = XILINX_CLOCK_FREQ / CONFIG_SYS_HZ;
- irq = CONFIG_SYS_TIMER_0_IRQ;
- tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR);
-#endif
+ debug("TIMER: Initialization\n");
+
+ node = fdt_node_offset_by_compatible(blob, node,
+ "xlnx,xps-timer-1.00.a");
+ if (node != -1) {
+ fdt_addr_t base = fdtdec_get_addr(blob, node, "reg");
+ if (base == FDT_ADDR_T_NONE)
+ return -1;
+
+ debug("TIMER: Base addr %lx\n", base);
+ tmr = (microblaze_timer_t *)base;
+
+ ret = fdtdec_get_int_array(blob, node, "interrupts",
+ cell, ARRAY_SIZE(cell));
+ if (ret)
+ return ret;
+
+ irq = cell[0];
+ debug("TIMER: IRQ %x\n", irq);
+
+ preload = fdtdec_get_int(blob, node, "clock-frequency", 0);
+ preload /= CONFIG_SYS_HZ;
+ } else {
+ return node;
+ }
if (tmr && preload && irq >= 0) {
tmr->loadreg = preload;
#address-cells = <1>;
#size-cells = <0>;
};
+
+ usb: musb@1f8e3000 {
+ compatible = "microchip,pic32mzda-usb";
+ reg = <0x1f8e3000 0x1000>,
+ <0x1f884000 0x1000>;
+ reg-names = "mc", "control";
+ interrupts = <132 IRQ_TYPE_EDGE_RISING>,
+ <133 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock PB5CLK>;
+ clock-names = "usb_clk";
+ status = "disabled";
+ };
};
ethernet_phy: lan8740_phy@0 {
reg = <0>;
};
+};
+
+&usb {
+ status = "okay";
};
\ No newline at end of file
#include <ioports.h>
#include <asm/io.h>
#ifdef CONFIG_USB_EHCI_FSL
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
void cpu_init_early_f(void *fdt)
{
u32 mas0, mas1, mas2, mas3, mas7;
- int i;
#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
u32 *dst, *src;
void (*setup_ifc_sram)(void);
+ int i;
#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
- /*
- * Clear initial global data
- * we don't use memset so we can share this code with NAND_SPL
- */
- for (i = 0; i < sizeof(gd_t); i++)
- ((char *)gd)[i] = 0;
+ /* gd area was zeroed during startup */
#ifdef CONFIG_QEMU_E500
/*
/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+
+#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#endif
+
+ /* Leave 16+ byte for back chain termination and NULL return address */
+ subi r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+#endif
+
+ /* End of RAM */
+ lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+ ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+
+ li r0,0
+
+1: subi r4,r4,4
+ stw r0,0(r4)
+ cmplw r4,r3
+ bne 1b
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+ lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+ ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
+
+ addi r3,r3,16 /* Pre-relocation malloc area */
+ stw r3,GD_MALLOC_BASE(r4)
+ subi r3,r3,16
+#endif
li r0,0
stw r0,0(r3) /* Terminate Back Chain */
stw r0,+4(r3) /* NULL return address. */
*
* The Serial Peripheral Interface (SPI) is tested in the local loopback mode.
* The interface is configured accordingly and several packets
- * are transfered. The configurable test parameters are:
+ * are transferred. The configurable test parameters are:
* TEST_MIN_LENGTH - minimum size of packet to transfer
* TEST_MAX_LENGTH - maximum size of packet to transfer
* TEST_NUM - number of tests
cli_init();
+#ifdef CONFIG_CMDLINE
if (state->cmd)
retval = run_command_list(state->cmd, -1, 0);
if (state->run_distro_boot)
retval = cli_simple_run_command("run distro_bootcmd",
0);
-
+#endif
if (!state->interactive)
os_exit(retval);
}
}
SANDBOX_CMDLINE_OPT_SHORT(verbose, 'v', 0, "Show test output");
+int board_run_command(const char *cmdline)
+{
+ printf("## Commands are disabled. Please enable CONFIG_CMDLINE.\n");
+
+ return 1;
+}
+
int main(int argc, char *argv[])
{
struct sandbox_state *state;
status = "disabled";
};
+ spmi: spmi@0 {
+ compatible = "sandbox,spmi";
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ pm8916@0 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x0 0x1>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+
+ spmi_gpios: gpios@c000 {
+ compatible = "qcom,pm8916-gpio";
+ reg = <0xc000 0x400>;
+ gpio-controller;
+ gpio-count = <4>;
+ #gpio-cells = <2>;
+ gpio-bank-name="spmi";
+ };
+ };
+ };
};
#include "cros-ec-keyboard.dtsi"
status = "disabled";
};
+ spmi: spmi@0 {
+ compatible = "sandbox,spmi";
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ pm8916@0 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x0 0x1>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+
+ spmi_gpios: gpios@c000 {
+ compatible = "qcom,pm8916-gpio";
+ reg = <0xc000 0x400>;
+ gpio-controller;
+ gpio-count = <4>;
+ #gpio-cells = <2>;
+ gpio-bank-name="spmi";
+ };
+ };
+ };
};
#include "sandbox_pmic.dtsi"
* For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
* will be inserted after the appropriate (depending the interval setting) skeleton TD.
* If an interrupt has been detected the dev->irqhandler is called. The status and number
- * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
+ * of transferred bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
* dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned,
* the interrupt TD will be reactivated.
*
return result;
}
-/* get the status and the transfered len of a td chain.
+/* get the status and the transferred len of a td chain.
* called from the completion handler
*/
int usb_get_td_status(uhci_td_t * td, struct usb_device *dev)
stat = usb_uhci_td_stat(temp);
info = swap_32((unsigned long)READ32(&mytd->info));
if (((info & 0xff) != USB_PID_SETUP) && (((info >> 21) & 0x7ff) != 0x7ff) && (temp & 0x7FF) != 0x7ff) { /* if not setup and not null data pack */
- dev->act_len += (temp & 0x7FF) + 1; /* the transfered len is act_len + 1 */
+ dev->act_len += (temp & 0x7FF) + 1; /* the transferred len is act_len + 1 */
}
if (stat) { /* status no ok */
dev->status = stat;
if ((td->dev_ptr != 0L) && !(status & TD_CTRL_ACTIVE)) {
/* td is not active and a device is assigned -> call irqhandler */
dev = (struct usb_device *)td->dev_ptr;
- dev->irq_act_len = ((status & 0x7FF) == 0x7FF) ? 0 : (status & 0x7FF) + 1; /* transfered length */
+ dev->irq_act_len = ((status & 0x7FF) == 0x7FF) ? 0 : (status & 0x7FF) + 1; /* transferred length */
dev->irq_status = usb_uhci_td_stat(status); /* get status */
res = dev->irq_handle(dev); /* call irqhandler */
if (res == 1) {
SECTIONS
{
+#ifndef CONFIG_CMDLINE
+ /DISCARD/ : { *(.u_boot_list_2_cmd_*) }
+#endif
+
. = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */
__text_start = .;
.text : { *(.text*); }
--- /dev/null
+DB_88F6720 BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/Marvell/db-88f6720/
+F: include/configs/db-88f6720.h
+F: configs/db-88f6720_defconfig
--- /dev/null
+#
+# Copyright (C) 2016 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := db-88f6720.o
--- /dev/null
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2014_T2.0" for the board Armada 375 DB-88F6720
+ */
+#define DB_88F6720_MPP0_7 0x00020020 /* SPI */
+#define DB_88F6720_MPP8_15 0x22000022 /* SPI , I2C */
+#define DB_88F6720_MPP16_23 0x22222222 /* UART, TDM*/
+#define DB_88F6720_MPP24_31 0x33333333 /* SDIO, SPI1*/
+#define DB_88F6720_MPP32_39 0x04403330 /* SPI1, External SMI */
+#define DB_88F6720_MPP40_47 0x22002044 /* UART1, GE0, SATA0 LED */
+#define DB_88F6720_MPP48_55 0x22222222 /* GE0 */
+#define DB_88F6720_MPP56_63 0x04444422 /* GE0 , LED_MATRIX, GPIO */
+#define DB_88F6720_MPP64_67 0x014 /* LED_MATRIX, SATA1 LED*/
+
+#define DB_88F6720_GPP_OUT_ENA_LOW 0xFFFFFFFF
+#define DB_88F6720_GPP_OUT_ENA_MID 0x7FFFFFFF
+#define DB_88F6720_GPP_OUT_ENA_HIGH 0xFFFFFFFF
+#define DB_88F6720_GPP_OUT_VAL_LOW 0x0
+#define DB_88F6720_GPP_OUT_VAL_MID BIT(31) /* SATA Power output enable */
+#define DB_88F6720_GPP_OUT_VAL_HIGH 0x0
+#define DB_88F6720_GPP_POL_LOW 0x0
+#define DB_88F6720_GPP_POL_MID 0x0
+#define DB_88F6720_GPP_POL_HIGH 0x0
+
+int board_early_init_f(void)
+{
+ /* Configure MPP */
+ writel(DB_88F6720_MPP0_7, MVEBU_MPP_BASE + 0x00);
+ writel(DB_88F6720_MPP8_15, MVEBU_MPP_BASE + 0x04);
+ writel(DB_88F6720_MPP16_23, MVEBU_MPP_BASE + 0x08);
+ writel(DB_88F6720_MPP24_31, MVEBU_MPP_BASE + 0x0c);
+ writel(DB_88F6720_MPP32_39, MVEBU_MPP_BASE + 0x10);
+ writel(DB_88F6720_MPP40_47, MVEBU_MPP_BASE + 0x14);
+ writel(DB_88F6720_MPP48_55, MVEBU_MPP_BASE + 0x18);
+ writel(DB_88F6720_MPP56_63, MVEBU_MPP_BASE + 0x1c);
+ writel(DB_88F6720_MPP64_67, MVEBU_MPP_BASE + 0x20);
+
+ /* Configure GPIO */
+ /* Set GPP Out value */
+ writel(DB_88F6720_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+ writel(DB_88F6720_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+ writel(DB_88F6720_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
+
+ /* Set GPP Polarity */
+ writel(DB_88F6720_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+ writel(DB_88F6720_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+ writel(DB_88F6720_GPP_POL_HIGH, MVEBU_GPIO2_BASE + 0x0c);
+
+ /* Set GPP Out Enable */
+ writel(DB_88F6720_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+ writel(DB_88F6720_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+ writel(DB_88F6720_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Marvell DB-88F6720\n");
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in controller(s) come first */
+ return pci_eth_init(bis);
+}
--- /dev/null
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION 1
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
+++ /dev/null
---------
-WARNING:
---------
-This file should contain the bin_hdr generated by the original Marvell
-U-Boot implementation. As this is currently not included in this
-U-Boot version, we have added this placeholder, so that the U-Boot
-image can be generated without errors.
-
-If you have a known to be working bin_hdr for your board, then you
-just need to replace this text file here with the binary header
-and recompile U-Boot.
-
-In a few weeks, mainline U-Boot will get support to generate the
-bin_hdr with the DDR training code itself. By implementing this code
-as SPL U-Boot. Then this file will not be needed any more and will
-get removed.
char reboot_mode[2] = { 0 };
u32 data = 0;
u32 value;
+ int rc;
/* Reboot mode */
- omap_reboot_mode(reboot_mode, sizeof(reboot_mode));
+ rc = omap_reboot_mode(reboot_mode, sizeof(reboot_mode));
/* USB ID pin pull-up indicates factory (fastboot) cable detection. */
gpio_request(KC1_GPIO_USB_ID, "USB_ID");
if (value)
reboot_mode[0] = 'b';
- if (reboot_mode[0] > 0 && isascii(reboot_mode[0])) {
- if (reboot_mode[0] == 'o')
- twl6030_power_off();
-
- if (!getenv("reboot-mode"))
- setenv("reboot-mode", (char *)reboot_mode);
-
- omap_reboot_mode_clear();
- } else {
- /* Reboot mode garbage may still be valid, so clear it. */
- omap_reboot_mode_clear();
-
+ if (rc < 0 || reboot_mode[0] == 'o') {
/*
* When not rebooting, valid power on reasons are either the
* power button, charger plug or USB plug.
twl6030_power_off();
}
+ if (reboot_mode[0] > 0 && isascii(reboot_mode[0])) {
+ if (!getenv("reboot-mode"))
+ setenv("reboot-mode", (char *)reboot_mode);
+ }
+
+ omap_reboot_mode_clear();
+
/* Serial number */
omap_die_id_serial();
#include <i2c.h>
#include <input.h>
#include <netdev.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
DECLARE_GLOBAL_DATA_PTR;
#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
#include <spl.h>
#include <fsl_esdhc.h>
#include <asm/gpio.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
#include <command.h>
#include <fsl_validate.h>
-static int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
+int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
if (fsl_check_boot_mode_secure() == 0) {
char *hash_str = NULL;
uintptr_t haddr;
int ret;
+ uintptr_t img_addr = 0;
+ char buf[20];
if (argc < 2)
return cmd_usage(cmdtp);
* part of header. So, the function is called
* by passing this argument as 0.
*/
- ret = fsl_secboot_validate(haddr, hash_str, 0);
+ ret = fsl_secboot_validate(haddr, hash_str, &img_addr);
+
+ /* Need to set "img_addr" even if validation failure.
+ * Required when SB_EN in RCW set and non-fatal error
+ * to continue U-Boot
+ */
+ sprintf(buf, "%lx", img_addr);
+ setenv("img_addr", buf);
+
if (ret)
return 1;
};
static u8 hash_val[SHA256_BYTES];
+
+#ifdef CONFIG_ESBC_HDR_LS
+/* New Barker Code for LS ESBC Header */
+static const u8 barker_code[ESBC_BARKER_LEN] = { 0x12, 0x19, 0x20, 0x01 };
+#else
static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 };
+#endif
void branch_to_self(void) __attribute__ ((noreturn));
/* This function checks srk_table_flag in header and set/reset srk_flag.*/
static u32 check_srk(struct fsl_secboot_img_priv *img)
{
+#ifdef CONFIG_ESBC_HDR_LS
+ /* In LS, No SRK Flag as SRK is always present*/
+ return 1;
+#else
if (img->hdr.len_kr.srk_table_flag & SRK_FLAG)
return 1;
return 0;
+#endif
}
/* This function returns ospr's key_revoc values.*/
}
#endif
+#ifndef CONFIG_ESBC_HDR_LS
static u32 read_validate_single_key(struct fsl_secboot_img_priv *img)
{
struct fsl_secboot_img_hdr *hdr = &img->hdr;
return 0;
}
+#endif /* CONFIG_ESBC_HDR_LS */
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img)
printf("Generating reset request\n");
do_reset(NULL, 0, 0, NULL);
+ /* If reset doesn't coocur, halt execution */
+ do_esbc_halt(NULL, 0, 0, NULL);
}
/*
printf("Generating reset request\n");
do_reset(NULL, 0, 0, NULL);
+ /* If reset doesn't coocur, halt execution */
+ do_esbc_halt(NULL, 0, 0, NULL);
+
} else {
change_sec_mon_state(HPSR_SSM_ST_TRUST,
HPSR_SSM_ST_NON_SECURE);
case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD:
case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP:
case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD:
+ case ERROR_KEY_TABLE_NOT_FOUND:
#ifdef CONFIG_KEY_REVOCATION
case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED:
case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY:
if (!key_hash && check_ie(img))
key_hash = 1;
#endif
- if (!key_hash)
+#ifndef CONFIG_ESBC_HDR_LS
+/* No single key support in LS ESBC header */
+ if (!key_hash) {
ret = algo->hash_update(algo, ctx,
img->img_key, img->hdr.key_len, 0);
+ key_hash = 1;
+ }
+#endif
if (ret)
return ret;
+ if (!key_hash)
+ return ERROR_KEY_TABLE_NOT_FOUND;
/* Update hash for actual Image */
ret = algo->hash_update(algo, ctx,
- (u8 *)img->img_addr, img->img_size, 1);
+ (u8 *)(*(img->img_addr_ptr)), img->img_size, 1);
if (ret)
return ret;
*/
static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
{
- char buf[20];
struct fsl_secboot_img_hdr *hdr = &img->hdr;
void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
u8 *k, *s;
u32 ret = 0;
-#ifdef CONFIG_KEY_REVOCATION
-#endif
int key_found = 0;
/* check barker code */
/* If Image Address is not passed as argument to function,
* then Address and Size must be read from the Header.
*/
- if (img->img_addr == 0) {
+ if (*(img->img_addr_ptr) == 0) {
#ifdef CONFIG_ESBC_ADDR_64BIT
- img->img_addr = hdr->pimg64;
+ *(img->img_addr_ptr) = hdr->pimg64;
#else
- img->img_addr = hdr->pimg;
+ *(img->img_addr_ptr) = hdr->pimg;
#endif
}
- sprintf(buf, "%lx", img->img_addr);
- setenv("img_addr", buf);
-
if (!hdr->img_size)
return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE;
key_found = 1;
}
#endif
-
+#ifndef CONFIG_ESBC_HDR_LS
+/* Single Key Feature not available in LS ESBC Header */
if (key_found == 0) {
ret = read_validate_single_key(img);
if (ret != 0)
return ret;
key_found = 1;
}
+#endif
+ if (!key_found)
+ return ERROR_KEY_TABLE_NOT_FOUND;
/* check signaure */
if (get_key_len(img) == 2 * hdr->sign_len) {
}
memcpy(&img->img_sign, esbc + hdr->psign, hdr->sign_len);
-
+/* No SG support in LS-CH3 */
+#ifndef CONFIG_ESBC_HDR_LS
/* No SG support */
if (hdr->sg_flag)
return ERROR_ESBC_CLIENT_HEADER_SG;
+#endif
/* modulus most significant bit should be set */
k = (u8 *)&img->img_key;
return 0;
}
-
+/* haddr - Address of the header of image to be validated.
+ * arg_hash_str - Option hash string. If provided, this
+ * overides the key hash in the SFP fuses.
+ * img_addr_ptr - Optional pointer to address of image to be validated.
+ * If non zero addr, this overides the addr of image in header,
+ * otherwise updated to image addr in header.
+ * Acts as both input and output of function.
+ * This pointer shouldn't be NULL.
+ */
int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
- uintptr_t img_addr)
+ uintptr_t *img_addr_ptr)
{
struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
ulong hash[SHA256_BYTES/sizeof(ulong)];
/* Update the information in Private Struct */
hdr = &img->hdr;
img->ehdrloc = haddr;
- img->img_addr = img_addr;
+ img->img_addr_ptr = img_addr_ptr;
esbc = (u8 *)img->ehdrloc;
memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr));
#include <asm/io.h>
#ifdef CONFIG_LS1043A
#include <asm/arch/immap_lsch2.h>
+#elif defined(CONFIG_FSL_LSCH3)
+#include <asm/arch/immap_lsch3.h>
#else
#include <asm/immap_85xx.h>
#endif
int adjust_vdd(ulong vdd_override)
{
int re_enable = disable_interrupts();
-#ifdef CONFIG_LS1043A
+#if defined(CONFIG_LS1043A) || defined(CONFIG_FSL_LSCH3)
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
#else
ccsr_gur_t __iomem *gur =
}
/* get the voltage ID from fuse status register */
+#ifdef CONFIG_FSL_LSCH3
+ fusesr = in_le32(&gur->dcfg_fusesr);
+#else
fusesr = in_be32(&gur->dcfg_fusesr);
+#endif
/*
* VID is used according to the table below
* ---------------------------------------
vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
}
+#elif defined(CONFIG_FSL_LSCH3)
+ vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
+ if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
+ vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
+ }
#else
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
exit:
if (re_enable)
enable_interrupts();
+
+ i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
+
return ret;
}
ret = find_ir_chip_on_i2c();
if (ret < 0) {
printf("VID: Could not find voltage regulator on I2C.\n");
- return -1;
+ goto exit;
} else {
i2caddress = ret;
debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
vdd_last = read_voltage(i2caddress);
if (vdd_last < 0) {
printf("VID: Couldn't read sensor abort VID adjustment\n");
- return -1;
+ goto exit;
}
printf("VID: Core voltage is at %d mV\n", vdd_last);
+exit:
+ i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
+
+ return ret < 0 ? -1 : 0;
- return 0;
}
static int do_vdd_override(cmd_tbl_t *cmdtp,
} else if (fm_info_get_enet_if(port) ==
PHY_INTERFACE_MODE_SGMII_2500) {
/* 2.5G SGMII interface */
- f_link.phy_id = port;
- f_link.duplex = 1;
- f_link.link_speed = 1000;
+ f_link.phy_id = cpu_to_fdt32(port);
+ f_link.duplex = cpu_to_fdt32(1);
+ f_link.link_speed = cpu_to_fdt32(1000);
f_link.pause = 0;
f_link.asym_pause = 0;
/* no PHY for 2.5G SGMII */
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
port == FM1_10GEC1) {
/* XFI interface */
- f_link.phy_id = port;
- f_link.duplex = 1;
- f_link.link_speed = 10000;
+ f_link.phy_id = cpu_to_fdt32(port);
+ f_link.duplex = cpu_to_fdt32(1);
+ f_link.link_speed = cpu_to_fdt32(10000);
f_link.pause = 0;
f_link.asym_pause = 0;
/* no PHY for XFI */
u8 reg;
/* Retimer is connected to I2C1_CH7_CH5 */
- reg = I2C_MUX_CH7;
- i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1);
+ select_i2c_ch_pca9547(I2C_MUX_CH7);
reg = I2C_MUX_CH5;
i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
reg = 0xcd;
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
+
+ /* Return the default channel */
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
}
int board_early_init_f(void)
F: configs/ls2080a_emu_defconfig
F: include/configs/ls2080a_simu.h
F: configs/ls2080a_simu_defconfig
-F: configs/ls2085a_emu_defconfig
-F: configs/ls2085a_simu_defconfig
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
+#include <asm/arch/soc.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
}
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- /* initialize DP-DDR here */
- puts("DP-DDR: ");
- /*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
- dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+ if (soc_has_dp_ddr()) {
+ /* initialize DP-DDR here */
+ puts("DP-DDR: ");
+ /*
+ * DDR controller use 0 as the base address for binding.
+ * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+ */
+ dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
CONFIG_DP_DDR_CTRL,
CONFIG_DP_DDR_NUM_CTRLS,
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
NULL, NULL, NULL);
- if (dp_ddr_size) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
- gd->bd->bi_dram[2].size = dp_ddr_size;
- } else {
- puts("Not detected");
+ if (dp_ddr_size) {
+ gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+ gd->bd->bi_dram[2].size = dp_ddr_size;
+ } else {
+ puts("Not detected");
+ }
}
#endif
}
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- if (gd->bd->bi_dram[2].size) {
+ if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
puts("\nDP-DDR ");
print_size(gd->bd->bi_dram[2].size, "");
print_ddr_info(CONFIG_DP_DDR_CTRL);
{
int offset;
- offset = fdt_path_offset(fdt, "/fsl-mc");
+ offset = fdt_path_offset(fdt, "/soc/fsl-mc");
/*
* TODO: Remove this when backward compatibility
- * with old DT node (fsl,dprc@0) is no longer needed.
+ * with old DT node (/fsl-mc) is no longer needed.
*/
if (offset < 0)
- offset = fdt_path_offset(fdt, "/fsl,dprc@0");
+ offset = fdt_path_offset(fdt, "/fsl-mc");
if (offset < 0) {
printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
F: include/configs/ls2080aqds.h
F: configs/ls2080aqds_defconfig
F: configs/ls2080aqds_nand_defconfig
-F: configs/ls2085aqds_defconfig
-F: configs/ls2085aqds_nand_defconfig
+
+LS2080A_SECURE_BOOT BOARD
+M: Saksham Jain <saksham.jain@nxp.freescale.com>
+S: Maintained
+F: configs/ls2080aqds_SECURE_BOOT_defconfig
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
+#include <asm/arch/soc.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
}
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- /* initialize DP-DDR here */
- puts("DP-DDR: ");
- /*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
- dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+ if (soc_has_dp_ddr()) {
+ /* initialize DP-DDR here */
+ puts("DP-DDR: ");
+ /*
+ * DDR controller use 0 as the base address for binding.
+ * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+ */
+ dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
CONFIG_DP_DDR_CTRL,
CONFIG_DP_DDR_NUM_CTRLS,
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
NULL, NULL, NULL);
- if (dp_ddr_size) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
- gd->bd->bi_dram[2].size = dp_ddr_size;
- } else {
- puts("Not detected");
+ if (dp_ddr_size) {
+ gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+ gd->bd->bi_dram[2].size = dp_ddr_size;
+ } else {
+ puts("Not detected");
+ }
}
#endif
}
dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
bus = mii_dev_for_muxval(EMI1_SLOT1);
wriop_set_mdio(dpmac_id, bus);
- dpmac_info[dpmac_id].phydev = phy_connect(
- dpmac_info[dpmac_id].bus,
- dpmac_info[dpmac_id].phy_addr,
- NULL,
- dpmac_info[dpmac_id].enet_if);
- phy_config(dpmac_info[dpmac_id].phydev);
break;
case 2:
/* Slot housing a SGMII riser card? */
dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
bus = mii_dev_for_muxval(EMI1_SLOT2);
wriop_set_mdio(dpmac_id, bus);
- dpmac_info[dpmac_id].phydev = phy_connect(
- dpmac_info[dpmac_id].bus,
- dpmac_info[dpmac_id].phy_addr,
- NULL,
- dpmac_info[dpmac_id].enet_if);
- phy_config(dpmac_info[dpmac_id].phydev);
break;
case 3:
break;
dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
bus = mii_dev_for_muxval(EMI1_SLOT4);
wriop_set_mdio(dpmac_id, bus);
- dpmac_info[dpmac_id].phydev = phy_connect(
- dpmac_info[dpmac_id].bus,
- dpmac_info[dpmac_id].phy_addr,
- NULL,
- dpmac_info[dpmac_id].enet_if);
- phy_config(dpmac_info[dpmac_id].phydev);
break;
case 5:
break;
dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
bus = mii_dev_for_muxval(EMI1_SLOT1);
wriop_set_mdio(dpmac_id, bus);
- dpmac_info[dpmac_id].phydev = phy_connect(
- dpmac_info[dpmac_id].bus,
- dpmac_info[dpmac_id].phy_addr,
- NULL,
- dpmac_info[dpmac_id].enet_if);
-
- phy_config(dpmac_info[dpmac_id].phydev);
break;
case 3:
break;
#include <rtc.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
+#include <fsl_sec.h>
#include "../common/qixis.h"
#include "ls2080aqds_qixis.h"
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- if (gd->bd->bi_dram[2].size) {
+ if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
puts("\nDP-DDR ");
print_size(gd->bd->bi_dram[2].size, "");
print_ddr_info(CONFIG_DP_DDR_CTRL);
#ifdef CONFIG_FSL_DEBUG_SERVER
debug_server_init();
#endif
-
+#ifdef CONFIG_FSL_CAAM
+ sec_init();
+#endif
return 0;
}
#endif
{
int offset;
- offset = fdt_path_offset(fdt, "/fsl-mc");
+ offset = fdt_path_offset(fdt, "/soc/fsl-mc");
if (offset < 0)
- offset = fdt_path_offset(fdt, "/fsl,dprc@0");
+ offset = fdt_path_offset(fdt, "/fsl-mc");
if (offset < 0) {
printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
F: include/configs/ls2080ardb.h
F: configs/ls2080ardb_defconfig
F: configs/ls2080ardb_nand_defconfig
-F: configs/ls2085ardb_defconfig
-F: configs/ls2085ardb_nand_defconfig
+
+LS2080A_SECURE_BOOT BOARD
+M: Saksham Jain <saksham.jain@nxp.freescale.com>
+S: Maintained
+F: configs/ls2080ardb_SECURE_BOOT_defconfig
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
+#include <asm/arch/soc.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
}
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- /* initialize DP-DDR here */
- puts("DP-DDR: ");
- /*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
- dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+ if (soc_has_dp_ddr()) {
+ /* initialize DP-DDR here */
+ puts("DP-DDR: ");
+ /*
+ * DDR controller use 0 as the base address for binding.
+ * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+ */
+ dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
CONFIG_DP_DDR_CTRL,
CONFIG_DP_DDR_NUM_CTRLS,
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
NULL, NULL, NULL);
- if (dp_ddr_size) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
- gd->bd->bi_dram[2].size = dp_ddr_size;
- } else {
- puts("Not detected");
+ if (dp_ddr_size) {
+ gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+ gd->bd->bi_dram[2].size = dp_ddr_size;
+ } else {
+ puts("Not detected");
+ }
}
#endif
}
DECLARE_GLOBAL_DATA_PTR;
-int load_firmware_cortina(struct phy_device *phy_dev)
-{
- if (phy_dev->drv->config)
- return phy_dev->drv->config(phy_dev);
-
- return 0;
-}
-
-void load_phy_firmware(void)
-{
- int i;
- u8 phy_addr;
- struct phy_device *phy_dev;
- struct mii_dev *dev;
- phy_interface_t interface;
-
- /*Initialize and upload firmware for all the PHYs*/
- for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) {
- interface = wriop_get_enet_if(i);
- if (interface == PHY_INTERFACE_MODE_XGMII) {
- dev = wriop_get_mdio(i);
- phy_addr = wriop_get_phy_address(i);
- phy_dev = phy_find_by_mask(dev, 1 << phy_addr,
- interface);
- if (!phy_dev) {
- printf("No phydev for phyaddr %d\n", phy_addr);
- continue;
- }
-
- /*Flash firmware for All CS4340 PHYS */
- if (phy_dev->phy_id == PHY_UID_CS4340)
- load_firmware_cortina(phy_dev);
- }
- }
-}
-
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
}
}
- /* Load CORTINA CS4340 PHY firmware */
- load_phy_firmware();
-
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
#include <environment.h>
#include <i2c.h>
#include <asm/arch/soc.h>
+#include <fsl_sec.h>
#include "../common/qixis.h"
#include "ls2080ardb_qixis.h"
+#include "../common/vid.h"
#define PIN_MUX_SEL_SDHC 0x00
#define PIN_MUX_SEL_DSPI 0x0a
return 0;
}
+int i2c_multiplexer_select_vid_channel(u8 channel)
+{
+ return select_i2c_ch_pca9547(channel);
+}
+
int config_board_mux(int ctrl_type)
{
u8 reg5;
{
char *env_hwconfig;
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+ u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
u32 val;
init_final_memctl_regs();
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
+ /* invert AQR405 IRQ pins polarity */
+ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
+
return 0;
}
if (hwconfig("sdhc"))
config_board_mux(MUX_TYPE_SDHC);
+ if (adjust_vdd(0))
+ printf("Warning: Adjusting core voltage failed.\n");
+
return 0;
}
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- if (gd->bd->bi_dram[2].size) {
+ if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
puts("\nDP-DDR ");
print_size(gd->bd->bi_dram[2].size, "");
print_ddr_info(CONFIG_DP_DDR_CTRL);
#ifdef CONFIG_FSL_DEBUG_SERVER
debug_server_init();
#endif
-
+#ifdef CONFIG_FSL_CAAM
+ sec_init();
+#endif
return 0;
}
#endif
{
int offset;
- offset = fdt_path_offset(fdt, "/fsl-mc");
+ offset = fdt_path_offset(fdt, "/soc/fsl-mc");
if (offset < 0)
- offset = fdt_path_offset(fdt, "/fsl,dprc@0");
+ offset = fdt_path_offset(fdt, "/fsl-mc");
if (offset < 0) {
printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
#include <power/pmic.h>
#include <fsl_pmic.h>
#include <mc13892.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
DECLARE_GLOBAL_DATA_PTR;
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
#include <usb.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
DECLARE_GLOBAL_DATA_PTR;
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
#include <usb.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
#include <pca953x.h>
DECLARE_GLOBAL_DATA_PTR;
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
#include <usb.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
DECLARE_GLOBAL_DATA_PTR;
#include <power/pfuze3000_pmic.h>
#include "../common/pfuze.h"
#include <usb.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/imx-common/mxc_i2c.h>
#include <asm/arch/crm_regs.h>
#include <usb.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
DECLARE_GLOBAL_DATA_PTR;
#include <errno.h>
#include <i2c.h>
+#define DP501_I2C_ADDR 0x08
+
+#ifdef CONFIG_SYS_DP501_I2C
+int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
+#endif
+
+#ifdef CONFIG_SYS_DP501_BASE
+int dp501_base[] = CONFIG_SYS_DP501_BASE;
+#endif
+
static void dp501_setbits(u8 addr, u8 reg, u8 mask)
{
u8 val;
{
dp501_setbits(addr, 0x0a, 0x30); /* power down encoder, standby mode */
}
+
+
+int dp501_probe(unsigned screen, bool power)
+{
+#ifdef CONFIG_SYS_DP501_BASE
+ uint8_t dp501_addr = dp501_base[screen];
+#else
+ uint8_t dp501_addr = DP501_I2C_ADDR;
+#endif
+
+#ifdef CONFIG_SYS_DP501_I2C
+ i2c_set_bus_num(dp501_i2c[screen]);
+#endif
+
+ if (i2c_probe(dp501_addr))
+ return -1;
+
+ dp501_powerup(dp501_addr);
+
+ return 0;
+}
void dp501_powerup(u8 addr);
void dp501_powerdown(u8 addr);
+int dp501_probe(unsigned screen, bool power);
#endif
#define SIL1178_MASTER_I2C_ADDRESS 0x38
#define SIL1178_SLAVE_I2C_ADDRESS 0x39
-#define DP501_I2C_ADDR 0x08
-
#define PIXCLK_640_480_60 25180000
#define MAX_X_CHARS 53
#define MAX_Y_CHARS 26
int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
#endif
-#ifdef CONFIG_SYS_DP501_I2C
-int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
-#endif
-
-#ifdef CONFIG_SYS_DP501_BASE
-int dp501_base[] = CONFIG_SYS_DP501_BASE;
-#endif
-
#ifdef CONFIG_SYS_MPC92469AC
static void mpc92469ac_calc_parameters(unsigned int fout,
unsigned int *post_div, unsigned int *feedback_div)
int old_bus = i2c_get_bus_num();
bool pixclock_present = false;
bool output_driver_present = false;
-#ifdef CONFIG_SYS_DP501_I2C
-#ifdef CONFIG_SYS_DP501_BASE
- uint8_t dp501_addr = dp501_base[screen];
-#else
- uint8_t dp501_addr = DP501_I2C_ADDR;
-#endif
-#endif
OSD_GET_REG(0, version, &version);
OSD_GET_REG(0, features, &features);
#endif
#ifdef CONFIG_SYS_DP501_I2C
- i2c_set_bus_num(dp501_i2c[screen]);
- if (!i2c_probe(dp501_addr)) {
- dp501_powerup(dp501_addr);
+ if (!dp501_probe(screen, true))
output_driver_present = true;
- }
#endif
if (!output_driver_present)
#include "../common/adv7611.h"
#include "../common/ch7301.h"
+#include "../common/dp501.h"
#include "../common/ioep-fpga.h"
#include "../common/mclink.h"
#include "../common/osd.h"
int slaves;
unsigned int k;
unsigned int mux_ch;
- unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
+ unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
+#ifdef CONFIG_STRIDER_CPU
+ unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
+#endif
bool hw_type_cat = pca9698_get_value(0x20, 18);
bool ch0_sgmii2_present = false;
pca9698_direction_output(0x20, 8, 0);
/* Turn on Parade DP501 */
- pca9698_direction_output(0x20, 9, 1);
+ pca9698_direction_output(0x20, 10, 1);
ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
/* wait for FPGA done, then reset FPGA */
- for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
+ for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
unsigned int ctr = 0;
+ unsigned char *mclink_controllers = mclink_controllers_dvi;
+#ifdef CONFIG_STRIDER_CPU
+ if (i2c_probe(mclink_controllers[k])) {
+ mclink_controllers = mclink_controllers_dp;
+ if (i2c_probe(mclink_controllers[k]))
+ continue;
+ }
+#else
if (i2c_probe(mclink_controllers[k]))
continue;
-
+#endif
while (!(pca953x_get_val(mclink_controllers[k])
& MCFPGA_DONE)) {
udelay(100000);
#ifdef CONFIG_STRIDER_CPU
ch7301_probe(0, false);
+ dp501_probe(0, false);
#endif
if (slaves <= 0)
mclink_fpgacount = slaves;
+#ifdef CONFIG_STRIDER_CPU
+ /* get ADV7611 out of reset, power up DP501, give some time to wakeup */
+ for (k = 1; k <= slaves; ++k)
+ FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
+
+ udelay(500000);
+#endif
+
for (k = 1; k <= slaves; ++k) {
ioep_fpga_print_info(k);
#ifdef CONFIG_STRIDER_CON
osd_probe(k);
#endif
#ifdef CONFIG_STRIDER_CPU
- FPGA_SET_REG(k, extended_control, 0); /* enable video in*/
if (!adv7611_probe(k))
printf(" Advantiv ADV7611 HDMI Receiver\n");
ch7301_probe(k, false);
+ dp501_probe(k, false);
#endif
if (hw_type_cat) {
miiphy_register(bb_miiphy_buses[k].name,
#elif CONFIG_CONS_INDEX == 4
.base = HI6220_UART3_BASE,
#else
-#error "Unsuported console index value."
+#error "Unsupported console index value."
#endif
.type = TYPE_PL011,
.clock = 19200000
--- /dev/null
+if TARGET_SNIPER
+
+config SYS_BOARD
+ default "sniper"
+
+config SYS_VENDOR
+ default "lg"
+
+config SYS_CONFIG_NAME
+ default "sniper"
+
+endif
--- /dev/null
+SNIPER BOARD
+M: Paul Kocialkowski <contact@paulk.fr>
+S: Maintained
+F: board/lg/sniper/
+F: include/configs/sniper.h
+F: configs/sniper_defconfig
--- /dev/null
+#
+# LG Optimus Black codename sniper board
+#
+# Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := sniper.o
--- /dev/null
+/*
+ * LG Optimus Black codename sniper board
+ *
+ * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <dm.h>
+#include <linux/ctype.h>
+#include <linux/usb/musb.h>
+#include <asm/omap_musb.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <twl4030.h>
+#include "sniper.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const omap3_sysinfo sysinfo = {
+ .mtype = DDR_STACKED,
+ .board_string = "sniper",
+ .nand_string = "MMC"
+};
+
+static const struct ns16550_platdata serial_omap_platdata = {
+ .base = OMAP34XX_UART3,
+ .reg_shift = 2,
+ .clock = V_NS16550_CLK
+};
+
+U_BOOT_DEVICE(sniper_serial) = {
+ .name = "ns16550_serial",
+ .platdata = &serial_omap_platdata
+};
+
+static struct musb_hdrc_config musb_config = {
+ .multipoint = 1,
+ .dyn_fifo = 1,
+ .num_eps = 16,
+ .ram_bits = 12
+};
+
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+};
+
+static struct musb_hdrc_platform_data musb_platform_data = {
+ .mode = MUSB_PERIPHERAL,
+ .config = &musb_config,
+ .power = 100,
+ .platform_ops = &omap2430_ops,
+ .board_data = &musb_board_data,
+};
+
+void set_muxconf_regs(void)
+{
+ MUX_SNIPER();
+}
+
+#ifdef CONFIG_SPL_BUILD
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+ timings->ctrla = HYNIX_V_ACTIMA_200;
+ timings->ctrlb = HYNIX_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ timings->mr = MICRON_V_MR_165;
+}
+#endif
+
+int board_init(void)
+{
+ /* GPMC init */
+ gpmc_init();
+
+ /* MACH number */
+ gd->bd->bi_arch_number = 3000;
+
+ /* ATAGs location */
+ gd->bd->bi_boot_params = OMAP34XX_SDRC_CS0 + 0x100;
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ unsigned char keypad_matrix[64] = { 0 };
+ char reboot_mode[2] = { 0 };
+ unsigned char keys[3];
+ unsigned char data = 0;
+ int rc;
+
+ /* Power button reset init */
+
+ twl4030_power_reset_init();
+
+ /* Keypad */
+
+ twl4030_keypad_scan((unsigned char *)&keypad_matrix);
+
+ keys[0] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 0);
+ keys[1] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 1);
+ keys[2] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 2);
+
+ /* Reboot mode */
+
+ rc = omap_reboot_mode(reboot_mode, sizeof(reboot_mode));
+
+ if (keys[0])
+ reboot_mode[0] = 'r';
+ else if (keys[1])
+ reboot_mode[0] = 'b';
+
+ if (rc < 0 || reboot_mode[0] == 'o') {
+ /*
+ * When not rebooting, valid power on reasons are either the
+ * power button, charger plug or USB plug.
+ */
+
+ data |= twl4030_input_power_button();
+ data |= twl4030_input_charger();
+ data |= twl4030_input_usb();
+
+ if (!data)
+ twl4030_power_off();
+ }
+
+ if (reboot_mode[0] > 0 && isascii(reboot_mode[0])) {
+ if (!getenv("reboot-mode"))
+ setenv("reboot-mode", (char *)reboot_mode);
+ }
+
+ omap_reboot_mode_clear();
+
+ /* Serial number */
+
+ omap_die_id_serial();
+
+ /* MUSB */
+
+ musb_register(&musb_platform_data, &musb_board_data, (void *)MUSB_BASE);
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ /* Sold devices are expected to be at least revision F. */
+ return 6;
+}
+
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ omap_die_id_get_board_serial(serialnr);
+}
+
+void reset_misc(void)
+{
+ char reboot_mode[2] = { 0 };
+
+ /*
+ * Valid resets must contain the reboot mode magic, but we must not
+ * override it when set previously (e.g. reboot to bootloader).
+ */
+
+ omap_reboot_mode(reboot_mode, sizeof(reboot_mode));
+ omap_reboot_mode_store(reboot_mode);
+}
+
+int fb_set_reboot_flag(void)
+{
+ return omap_reboot_mode_store("b");
+}
+
+#ifndef CONFIG_SPL_BUILD
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(1, 0, 0, -1, -1);
+}
+#endif
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(1);
+}
--- /dev/null
+/*
+ * LG Optimus Black codename sniper board
+ *
+ * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SNIPER_H_
+#define _SNIPER_H_
+
+#include <asm/arch/mux.h>
+
+#define MUX_SNIPER() \
+ /* SDRC */ \
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* sdrc_d0 */\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* sdrc_d1 */\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* sdrc_d2 */\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* sdrc_d3 */\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* sdrc_d4 */\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* sdrc_d5 */\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* sdrc_d6 */\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* sdrc_d7 */\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* sdrc_d8 */\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* sdrc_d9 */\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* sdrc_d10 */\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* sdrc_d11 */\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* sdrc_d12 */\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* sdrc_d13 */\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* sdrc_d14 */\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* sdrc_d15 */\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* sdrc_d16 */\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* sdrc_d17 */\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* sdrc_d18 */\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* sdrc_d19 */\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* sdrc_d20 */\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* sdrc_d21 */\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* sdrc_d22 */\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* sdrc_d23 */\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* sdrc_d24 */\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* sdrc_d25 */\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* sdrc_d26 */\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* sdrc_d27 */\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* sdrc_d28 */\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* sdrc_d29 */\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* sdrc_d30 */\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* sdrc_d31 */\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* sdrc_clk */\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* sdrc_dqs0 */\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* sdrc_dqs1 */\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* sdrc_dqs2 */\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* sdrc_dqs3 */ \
+ /* GPMC */ \
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M4)) /* gpio_34 */ \
+ MUX_VAL(CP(GPMC_A2), (IEN | PTD | DIS | M4)) /* gpio_35 */ \
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M4)) /* gpio_36 */ \
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M4)) /* gpio_37 */\
+ MUX_VAL(CP(GPMC_A5), (IEN | PTD | DIS | M4)) /* gpio_38 */\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M4)) /* gpio_39 */\
+ MUX_VAL(CP(GPMC_A7), (IEN | PTD | DIS | M4)) /* gpio_40 */\
+ MUX_VAL(CP(GPMC_A8), (IEN | PTD | DIS | M4)) /* gpio_41 */\
+ MUX_VAL(CP(GPMC_A9), (IEN | PTD | EN | M4)) /* gpio_42 */\
+ MUX_VAL(CP(GPMC_A10), (IEN | PTD | DIS | M4)) /* gpio_43 */\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* gpmc_d0 */ \
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* gpmc_d1 */ \
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* gpmc_d2 */ \
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* gpmc_d3 */ \
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* gpmc_d4 */ \
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* gpmc_d5 */ \
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* gpmc_d6 */ \
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* gpmc_d7 */ \
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* gpmc_d8 */ \
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* gpmc_d9 */ \
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* gpmc_d10 */ \
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* gpmc_d11 */ \
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* gpmc_d12 */ \
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* gpmc_d13 */ \
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* gpmc_d14 */ \
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTD | DIS | M7)) \
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTD | DIS | M4)) /* gpio_52 */ \
+ MUX_VAL(CP(GPMC_NCS2), (IEN | PTD | DIS | M4)) /* gpio_53 */ \
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* gpio_54 */ \
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTD | DIS | M4)) /* gpio_55 */ \
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M3)) /* gpio_56 */ \
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | DIS | M4)) /* gpio_57 */ \
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTD | DIS | M4)) /* gpio_58 */ \
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M7)) /* safe_mode */ \
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M7)) \
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M7)) \
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M7)) \
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M4)) /* gpio_60 */ \
+ MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)) /* gpio_61 */ \
+ MUX_VAL(CP(GPMC_NWP), (IDIS | PTD | DIS | M4)) /* gpio_62 */ \
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTD | DIS | M4)) /* gpio_63 */ \
+ MUX_VAL(CP(GPMC_WAIT2), (IDIS | PTD | DIS | M2)) /* gpio_64 */ \
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTD | DIS | M2)) /* gpio_65 */ \
+ /* DSS */ \
+ MUX_VAL(CP(DSS_PCLK), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_HSYNC), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_VSYNC), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_ACBIAS), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M1)) /* dsi_dx0 */ \
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M1)) /* dsi_dy0 */ \
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M1)) /* dsi_dx1 */ \
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M1)) /* dsi_dy1 */ \
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M1)) /* dsi_dx2 */ \
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M1)) /* dsi_dy2 */ \
+ MUX_VAL(CP(DSS_DATA6), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_DATA7), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_DATA10), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_DATA11), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_DATA12), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_DATA13), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_DATA14), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_DATA15), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M4)) /* gpio_87 */ \
+ MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_DATA20), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_DATA21), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_DATA22), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(DSS_DATA23), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ /* CAM */ \
+ MUX_VAL(CP(CAM_HS), (IEN | PTD | EN | M0)) /* cam_hs */ \
+ MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M0)) /* cam_vs */ \
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /* cam_xclka */ \
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M0)) /* cam_pclk */ \
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /* gpio_98 */ \
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M2)) /* csi2_dx2 */ \
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M2)) /* csi2_dy2 */ \
+ MUX_VAL(CP(CAM_D2), (IDIS | PTD | EN | M4)) /* gpio_101 */ \
+ MUX_VAL(CP(CAM_D3), (IDIS | PTD | DIS | M7)) /* safe_mode */ \
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /* cam_d4 */ \
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /* cam_d5 */ \
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /* cam_d6 */ \
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /* cam_d7 */ \
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /* cam_d8 */ \
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /* cam_d9 */ \
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /* cam_d10 */ \
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /* cam_d11 */ \
+ MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M0)) /* cam_xclkb */ \
+ MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)) /* gpio_167 */ \
+ MUX_VAL(CP(CAM_STROBE), (IEN | PTD | DIS | M7)) /* safe_mode */ \
+ /* CSI2 */ \
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /* csi2_dx0 */ \
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /* csi2_dy0 */ \
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /* csi2_dx1 */ \
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /* csi2_dy1 */ \
+ /* MCBSP2 */ \
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /* mcbsp2_fsx */ \
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /* mcbsp2_clkx */ \
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /* mcbsp2_dr */ \
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /* mcbsp2_dx */ \
+ /* MMC1 */ \
+ MUX_VAL(CP(MMC1_CLK), (IEN | PTD | DIS | M0)) /* mmc1_clk */ \
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTD | DIS | M0)) /* mmc1_cmd */ \
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTD | DIS | M0)) /* mmc1_dat0 */ \
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTD | DIS | M0)) /* mmc1_dat1 */ \
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTD | DIS | M0)) /* mmc1_dat2 */ \
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTD | DIS | M0)) /* mmc1_dat3 */ \
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | DIS | M7)) /* safe_mode */ \
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | DIS | M7)) /* safe_mode */ \
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | DIS | M7)) /* safe_mode */ \
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | DIS | M7)) /* safe_mode */ \
+ /* MMC2 */ \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) /* mmc2_clk */ \
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) /* mmc2_cmd */ \
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) /* mmc2_dat0 */ \
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) /* mmc2_dat1 */ \
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) /* mmc2_dat2 */ \
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) /* mmc2_dat3 */ \
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | DIS | M0)) /* mmc2_dat4 */ \
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | DIS | M0)) /* mmc2_dat5 */ \
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | DIS | M0)) /* mmc2_dat6 */ \
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | DIS | M0)) /* mmc2_dat7 */ \
+ /* MCBSP3 */ \
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /* mcbsp3_dx */ \
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /* mcbsp3_dr */ \
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /* mcbsp3_clkx */ \
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /* mcbsp3_fsx */ \
+ /* UART2 */ \
+ MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M0)) /* uart2_cts */ \
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /* uart2_rts */ \
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /* uart2_tx */ \
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /* uart2_rx */ \
+ /* UART1 */ \
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* uart1_tx */ \
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /* uart1_rts */ \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTD | DIS | M0)) /* uart1_cts */ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* uart1_rx */ \
+ /* MCBSP4 */ \
+ MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /* gpio_152 */ \
+ MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /* gpio_153 */ \
+ MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /* gpio_154 */ \
+ MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /* gpio_155 */ \
+ /* MCBSP1 */ \
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /* mcbsp1_clkr */ \
+ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0)) /* mcbsp1_fsr */ \
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) /* mcbsp1_dx */ \
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /* mcbsp1_dr */ \
+ MUX_VAL(CP(MCBSP_CLKS), (IDIS | PTD | DIS | M7)) /* safe_mode */ \
+ MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /* gpio_161 */ \
+ MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /* gpio_162 */ \
+ /* UART3 */ \
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M4)) /* gpio_163 */ \
+ MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* uart3_rx_irrx */ \
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* uart3_tx_irtx */ \
+ /* HSUSB0 */ \
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | EN | M0)) /* hsusb0_clk */\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTD | DIS | M0)) /* hsusb0_stp */\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | EN | M0)) /* hsusb0_dir */\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | EN | M0)) /* hsusb0_nxt */\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | EN | M0)) /* hsusb0_data0 */\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | EN | M0)) /* hsusb0_data1 */\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | EN | M0)) /* hsusb0_data2 */\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | EN | M0)) /* hsusb0_data3 */\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | EN | M0)) /* hsusb0_data4 */\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | EN | M0)) /* hsusb0_data5 */\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | EN | M0)) /* hsusb0_data6 */\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | EN | M0)) /* hsusb0_data7 */ \
+ /* I2C1 */ \
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* i2c1_scl */ \
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* i2c1_sda */ \
+ /* I2C2 */ \
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTD | DIS | M0)) /* i2c2_scl */ \
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTD | DIS | M0)) /* i2c2_sda */ \
+ /* I2C3 */ \
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTD | DIS | M0)) /* i2c3_scl */ \
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTD | DIS | M0)) /* i2c3_sda */ \
+ /* I2C4 */ \
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* i2c4_scl */ \
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* i2c4_sda */ \
+ /* HDQ */ \
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) /* gpio_170 */ \
+ /* MCSPI1 */ \
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | DIS | M4)) /* gpio_175 */ \
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /* gpio_176 */ \
+ MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTD | DIS | M4)) /* gpio_177 */ \
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M0)) /* mcspi2_clk */ \
+ MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | DIS | M0)) /* mcspi2_simo */ \
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /* mcspi2_somi */ \
+ MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTD | DIS | M4)) /* gpio_181 */ \
+ MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | DIS | M4)) /* gpio_182 */ \
+ /* SYS */ \
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* sys_32k */ \
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /* sys_clkreq */ \
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /* sys_nirq */ \
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTU | EN | M7)) /* safe_mode */ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IDIS | PTD | DIS | M0)) /* sys_off_mode */ \
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4)) /* gpio_10 */ \
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | EN | M7)) /* safe_mode */ \
+ /* JTAG */ \
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /* jtag_ntrst */ \
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /* jtag_tck */ \
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M0)) /* jtag_tms */ \
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M0)) /* jtag_tdi */ \
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /* jtag_emu0 */ \
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /* jtag_emu1 */ \
+ /* ETK */ \
+ MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_clk */ \
+ MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /* sdmmc3_cmd */ \
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M4)) /* gpio_14 */ \
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M4)) /* gpio_15 */ \
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | DIS | M4)) /* gpio_16 */ \
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat3 */ \
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat0 */ \
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat1 */ \
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat2 */ \
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M4)) /* gpio_21 */ \
+ MUX_VAL(CP(ETK_D8_ES2), (IDIS | PTD | DIS | M4)) /* gpio_22 */ \
+ MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M4)) /* gpio_23 */ \
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | EN | M4)) /* gpio_24 */ \
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) /* gpio_25 */ \
+ MUX_VAL(CP(ETK_D12_ES2), (IDIS | PTD | DIS | M4)) /* gpio_26 */ \
+ MUX_VAL(CP(ETK_D13_ES2), (IDIS | PTD | DIS | M4)) /* gpio_27 */ \
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* gpio_28 */ \
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | EN | M4)) /* gpio_29 */ \
+ /* D2D */ \
+ MUX_VAL(CP(D2D_MCAD0), (IEN | PTD | EN | M0)) /* d2d_mcad0 */ \
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /* d2d_mcad1 */ \
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /* d2d_mcad2 */ \
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /* d2d_mcad3 */ \
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /* d2d_mcad4 */ \
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /* d2d_mcad5 */ \
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /* d2d_mcad6 */ \
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /* d2d_mcad7 */ \
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /* d2d_mcad8 */ \
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /* d2d_mcad9 */ \
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /* d2d_mcad10 */ \
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /* d2d_mcad11 */ \
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /* d2d_mcad12 */ \
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /* d2d_mcad13 */ \
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /* d2d_mcad14 */ \
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /* d2d_mcad15 */ \
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /* d2d_mcad16 */ \
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /* d2d_mcad17 */ \
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /* d2d_mcad18 */ \
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /* d2d_mcad19 */ \
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /* d2d_mcad20 */ \
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /* d2d_mcad21 */ \
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /* d2d_mcad22 */ \
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /* d2d_mcad23 */ \
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /* d2d_mcad24 */ \
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /* d2d_mcad25 */ \
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /* d2d_mcad26 */ \
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /* d2d_mcad27 */ \
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /* d2d_mcad28 */ \
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /* d2d_mcad29 */ \
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /* d2d_mcad30 */ \
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /* d2d_mcad31 */ \
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /* d2d_mcad32 */ \
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /* d2d_mcad33 */ \
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /* d2d_mcad34 */ \
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /* d2d_mcad35 */ \
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /* d2d_mcad36 */ \
+ MUX_VAL(CP(D2D_CLK26MI), (IDIS | PTD | DIS | M0)) /* d2d_clk26mi */ \
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTU | EN | M0)) /* d2d_nrespwron */ \
+ MUX_VAL(CP(D2D_NRESWARM), (IDIS | PTD | DIS | M0)) /* d2d_nreswarm */ \
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IDIS | PTD | DIS | M0)) /* d2d_arm9nirq */ \
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IDIS | PTD | DIS | M0)) /* d2d_uma2p6fiq */ \
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | DIS | M0)) /* d2d_spint */ \
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | DIS | M0)) /* d2d_frint */ \
+ MUX_VAL(CP(D2D_DMAREQ0), (IDIS | PTD | DIS | M0)) /* d2d_dmareq0 */ \
+ MUX_VAL(CP(D2D_DMAREQ1), (IDIS | PTD | DIS | M0)) /* d2d_dmareq1 */ \
+ MUX_VAL(CP(D2D_DMAREQ2), (IDIS | PTD | DIS | M0)) /* d2d_dmareq2 */ \
+ MUX_VAL(CP(D2D_DMAREQ3), (IDIS | PTD | DIS | M0)) /* d2d_dmareq3 */ \
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /* d2d_n3gtrst */ \
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTU | EN | M0)) /* d2d_n3gtdi */ \
+ MUX_VAL(CP(D2D_N3GTDO), (IDIS | PTD | DIS | M0)) /* d2d_n3gtdo */ \
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTU | EN | M0)) /* d2d_n3gtms */ \
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /* d2d_n3gtck */ \
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /* d2d_n3grtck */ \
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /* d2d_mstdby */ \
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /* d2d_swakeup */ \
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /* d2d_idlereq */ \
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /* d2d_idleack */ \
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /* d2d_mwrite */ \
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /* d2d_swrite */ \
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /* d2d_mread */ \
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /* d2d_sread */ \
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /* d2d_mbusflag */ \
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /* d2d_sbusflag */ \
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTD | DIS | M0)) /* sdrc_cke0 */ \
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M0)) /* sdrc_cke1 */ \
+ MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M7)) /* safe_mode */ \
+ MUX_VAL(CP(GPIO126), (IDIS | PTD | DIS | M4)) /* gpio_126 */ \
+ MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /* gpio_128 */ \
+ MUX_VAL(CP(GPIO129), (IEN | PTD | DIS | M4)) /* gpio_129 */
+
+#endif
+++ /dev/null
-if TARGET_SNIPER
-
-config SYS_BOARD
- default "sniper"
-
-config SYS_VENDOR
- default "lge"
-
-config SYS_CONFIG_NAME
- default "sniper"
-
-endif
+++ /dev/null
-SNIPER BOARD
-M: Paul Kocialkowski <contact@paulk.fr>
-S: Maintained
-F: board/lge/sniper/
-F: include/configs/sniper.h
-F: configs/sniper_defconfig
+++ /dev/null
-#
-# LG Optimus Black codename sniper board
-#
-# Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := sniper.o
+++ /dev/null
-/*
- * LG Optimus Black codename sniper board
- *
- * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <dm.h>
-#include <linux/ctype.h>
-#include <linux/usb/musb.h>
-#include <asm/omap_musb.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <twl4030.h>
-#include "sniper.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const omap3_sysinfo sysinfo = {
- .mtype = DDR_STACKED,
- .board_string = "sniper",
- .nand_string = "MMC"
-};
-
-static const struct ns16550_platdata serial_omap_platdata = {
- .base = OMAP34XX_UART3,
- .reg_shift = 2,
- .clock = V_NS16550_CLK
-};
-
-U_BOOT_DEVICE(sniper_serial) = {
- .name = "ns16550_serial",
- .platdata = &serial_omap_platdata
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 1,
- .dyn_fifo = 1,
- .num_eps = 16,
- .ram_bits = 12
-};
-
-static struct omap_musb_board_data musb_board_data = {
- .interface_type = MUSB_INTERFACE_ULPI,
-};
-
-static struct musb_hdrc_platform_data musb_platform_data = {
- .mode = MUSB_PERIPHERAL,
- .config = &musb_config,
- .power = 100,
- .platform_ops = &omap2430_ops,
- .board_data = &musb_board_data,
-};
-
-void set_muxconf_regs(void)
-{
- MUX_SNIPER();
-}
-
-#ifdef CONFIG_SPL_BUILD
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
- timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
- timings->ctrla = HYNIX_V_ACTIMA_200;
- timings->ctrlb = HYNIX_V_ACTIMB_200;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
- timings->mr = MICRON_V_MR_165;
-}
-#endif
-
-int board_init(void)
-{
- /* GPMC init */
- gpmc_init();
-
- /* MACH number */
- gd->bd->bi_arch_number = 3000;
-
- /* ATAGs location */
- gd->bd->bi_boot_params = OMAP34XX_SDRC_CS0 + 0x100;
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- unsigned char keypad_matrix[64] = { 0 };
- char reboot_mode[2] = { 0 };
- unsigned char keys[3];
- unsigned char data = 0;
-
- /* Power button reset init */
-
- twl4030_power_reset_init();
-
- /* Keypad */
-
- twl4030_keypad_scan((unsigned char *)&keypad_matrix);
-
- keys[0] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 0);
- keys[1] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 1);
- keys[2] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 2);
-
- /* Reboot mode */
-
- omap_reboot_mode(reboot_mode, sizeof(reboot_mode));
-
- if (keys[0])
- reboot_mode[0] = 'r';
- else if (keys[1])
- reboot_mode[0] = 'b';
-
- if (reboot_mode[0] > 0 && isascii(reboot_mode[0])) {
- if (!getenv("reboot-mode"))
- setenv("reboot-mode", (char *)reboot_mode);
-
- omap_reboot_mode_clear();
- } else {
- /* Reboot mode garbage may still be valid, so clear it. */
- omap_reboot_mode_clear();
-
- /*
- * When not rebooting, valid power on reasons are either the
- * power button, charger plug or USB plug.
- */
-
- data |= twl4030_input_power_button();
- data |= twl4030_input_charger();
- data |= twl4030_input_usb();
-
- if (!data)
- twl4030_power_off();
- }
-
- /* Serial number */
-
- omap_die_id_serial();
-
- /* MUSB */
-
- musb_register(&musb_platform_data, &musb_board_data, (void *)MUSB_BASE);
-
- return 0;
-}
-
-u32 get_board_rev(void)
-{
- /* Sold devices are expected to be at least revision F. */
- return 6;
-}
-
-void get_board_serial(struct tag_serialnr *serialnr)
-{
- omap_die_id_get_board_serial(serialnr);
-}
-
-int fb_set_reboot_flag(void)
-{
- return omap_reboot_mode_store("b");
-}
-
-#ifndef CONFIG_SPL_BUILD
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(1, 0, 0, -1, -1);
-}
-#endif
-
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(1);
-}
+++ /dev/null
-/*
- * LG Optimus Black codename sniper board
- *
- * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SNIPER_H_
-#define _SNIPER_H_
-
-#include <asm/arch/mux.h>
-
-#define MUX_SNIPER() \
- /* SDRC */ \
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* sdrc_d0 */\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* sdrc_d1 */\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* sdrc_d2 */\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* sdrc_d3 */\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* sdrc_d4 */\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* sdrc_d5 */\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* sdrc_d6 */\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* sdrc_d7 */\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* sdrc_d8 */\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* sdrc_d9 */\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* sdrc_d10 */\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* sdrc_d11 */\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* sdrc_d12 */\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* sdrc_d13 */\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* sdrc_d14 */\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* sdrc_d15 */\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* sdrc_d16 */\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* sdrc_d17 */\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* sdrc_d18 */\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* sdrc_d19 */\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* sdrc_d20 */\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* sdrc_d21 */\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* sdrc_d22 */\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* sdrc_d23 */\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* sdrc_d24 */\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* sdrc_d25 */\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* sdrc_d26 */\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* sdrc_d27 */\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* sdrc_d28 */\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* sdrc_d29 */\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* sdrc_d30 */\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* sdrc_d31 */\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* sdrc_clk */\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* sdrc_dqs0 */\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* sdrc_dqs1 */\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* sdrc_dqs2 */\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* sdrc_dqs3 */ \
- /* GPMC */ \
- MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M4)) /* gpio_34 */ \
- MUX_VAL(CP(GPMC_A2), (IEN | PTD | DIS | M4)) /* gpio_35 */ \
- MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M4)) /* gpio_36 */ \
- MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M4)) /* gpio_37 */\
- MUX_VAL(CP(GPMC_A5), (IEN | PTD | DIS | M4)) /* gpio_38 */\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M4)) /* gpio_39 */\
- MUX_VAL(CP(GPMC_A7), (IEN | PTD | DIS | M4)) /* gpio_40 */\
- MUX_VAL(CP(GPMC_A8), (IEN | PTD | DIS | M4)) /* gpio_41 */\
- MUX_VAL(CP(GPMC_A9), (IEN | PTD | EN | M4)) /* gpio_42 */\
- MUX_VAL(CP(GPMC_A10), (IEN | PTD | DIS | M4)) /* gpio_43 */\
- MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* gpmc_d0 */ \
- MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* gpmc_d1 */ \
- MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* gpmc_d2 */ \
- MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* gpmc_d3 */ \
- MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* gpmc_d4 */ \
- MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* gpmc_d5 */ \
- MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* gpmc_d6 */ \
- MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* gpmc_d7 */ \
- MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* gpmc_d8 */ \
- MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* gpmc_d9 */ \
- MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* gpmc_d10 */ \
- MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* gpmc_d11 */ \
- MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* gpmc_d12 */ \
- MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* gpmc_d13 */ \
- MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* gpmc_d14 */ \
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTD | DIS | M7)) \
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTD | DIS | M4)) /* gpio_52 */ \
- MUX_VAL(CP(GPMC_NCS2), (IEN | PTD | DIS | M4)) /* gpio_53 */ \
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* gpio_54 */ \
- MUX_VAL(CP(GPMC_NCS4), (IDIS | PTD | DIS | M4)) /* gpio_55 */ \
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M3)) /* gpio_56 */ \
- MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | DIS | M4)) /* gpio_57 */ \
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTD | DIS | M4)) /* gpio_58 */ \
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M7)) /* safe_mode */ \
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M7)) \
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M7)) \
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M7)) \
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M4)) /* gpio_60 */ \
- MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)) /* gpio_61 */ \
- MUX_VAL(CP(GPMC_NWP), (IDIS | PTD | DIS | M4)) /* gpio_62 */ \
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTD | DIS | M4)) /* gpio_63 */ \
- MUX_VAL(CP(GPMC_WAIT2), (IDIS | PTD | DIS | M2)) /* gpio_64 */ \
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTD | DIS | M2)) /* gpio_65 */ \
- /* DSS */ \
- MUX_VAL(CP(DSS_PCLK), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_HSYNC), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_VSYNC), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_ACBIAS), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M1)) /* dsi_dx0 */ \
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M1)) /* dsi_dy0 */ \
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M1)) /* dsi_dx1 */ \
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M1)) /* dsi_dy1 */ \
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M1)) /* dsi_dx2 */ \
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M1)) /* dsi_dy2 */ \
- MUX_VAL(CP(DSS_DATA6), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA7), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA10), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA11), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA12), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA13), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA14), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA15), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M4)) /* gpio_87 */ \
- MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA20), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA21), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA22), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA23), (IEN | PTD | EN | M7)) /* safe_mode */ \
- /* CAM */ \
- MUX_VAL(CP(CAM_HS), (IEN | PTD | EN | M0)) /* cam_hs */ \
- MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M0)) /* cam_vs */ \
- MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /* cam_xclka */ \
- MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M0)) /* cam_pclk */ \
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /* gpio_98 */ \
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M2)) /* csi2_dx2 */ \
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M2)) /* csi2_dy2 */ \
- MUX_VAL(CP(CAM_D2), (IDIS | PTD | EN | M4)) /* gpio_101 */ \
- MUX_VAL(CP(CAM_D3), (IDIS | PTD | DIS | M7)) /* safe_mode */ \
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /* cam_d4 */ \
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /* cam_d5 */ \
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /* cam_d6 */ \
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /* cam_d7 */ \
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /* cam_d8 */ \
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /* cam_d9 */ \
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /* cam_d10 */ \
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /* cam_d11 */ \
- MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M0)) /* cam_xclkb */ \
- MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)) /* gpio_167 */ \
- MUX_VAL(CP(CAM_STROBE), (IEN | PTD | DIS | M7)) /* safe_mode */ \
- /* CSI2 */ \
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /* csi2_dx0 */ \
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /* csi2_dy0 */ \
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /* csi2_dx1 */ \
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /* csi2_dy1 */ \
- /* MCBSP2 */ \
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /* mcbsp2_fsx */ \
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /* mcbsp2_clkx */ \
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /* mcbsp2_dr */ \
- MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /* mcbsp2_dx */ \
- /* MMC1 */ \
- MUX_VAL(CP(MMC1_CLK), (IEN | PTD | DIS | M0)) /* mmc1_clk */ \
- MUX_VAL(CP(MMC1_CMD), (IEN | PTD | DIS | M0)) /* mmc1_cmd */ \
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTD | DIS | M0)) /* mmc1_dat0 */ \
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTD | DIS | M0)) /* mmc1_dat1 */ \
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTD | DIS | M0)) /* mmc1_dat2 */ \
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTD | DIS | M0)) /* mmc1_dat3 */ \
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | DIS | M7)) /* safe_mode */ \
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | DIS | M7)) /* safe_mode */ \
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | DIS | M7)) /* safe_mode */ \
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | DIS | M7)) /* safe_mode */ \
- /* MMC2 */ \
- MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) /* mmc2_clk */ \
- MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) /* mmc2_cmd */ \
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) /* mmc2_dat0 */ \
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) /* mmc2_dat1 */ \
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) /* mmc2_dat2 */ \
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) /* mmc2_dat3 */ \
- MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | DIS | M0)) /* mmc2_dat4 */ \
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | DIS | M0)) /* mmc2_dat5 */ \
- MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | DIS | M0)) /* mmc2_dat6 */ \
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | DIS | M0)) /* mmc2_dat7 */ \
- /* MCBSP3 */ \
- MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /* mcbsp3_dx */ \
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /* mcbsp3_dr */ \
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /* mcbsp3_clkx */ \
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /* mcbsp3_fsx */ \
- /* UART2 */ \
- MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M0)) /* uart2_cts */ \
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /* uart2_rts */ \
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /* uart2_tx */ \
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /* uart2_rx */ \
- /* UART1 */ \
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* uart1_tx */ \
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /* uart1_rts */ \
- MUX_VAL(CP(UART1_CTS), (IEN | PTD | DIS | M0)) /* uart1_cts */ \
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* uart1_rx */ \
- /* MCBSP4 */ \
- MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /* gpio_152 */ \
- MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /* gpio_153 */ \
- MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /* gpio_154 */ \
- MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /* gpio_155 */ \
- /* MCBSP1 */ \
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /* mcbsp1_clkr */ \
- MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0)) /* mcbsp1_fsr */ \
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) /* mcbsp1_dx */ \
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /* mcbsp1_dr */ \
- MUX_VAL(CP(MCBSP_CLKS), (IDIS | PTD | DIS | M7)) /* safe_mode */ \
- MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /* gpio_161 */ \
- MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /* gpio_162 */ \
- /* UART3 */ \
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M4)) /* gpio_163 */ \
- MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* uart3_rx_irrx */ \
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* uart3_tx_irtx */ \
- /* HSUSB0 */ \
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | EN | M0)) /* hsusb0_clk */\
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTD | DIS | M0)) /* hsusb0_stp */\
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | EN | M0)) /* hsusb0_dir */\
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | EN | M0)) /* hsusb0_nxt */\
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | EN | M0)) /* hsusb0_data0 */\
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | EN | M0)) /* hsusb0_data1 */\
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | EN | M0)) /* hsusb0_data2 */\
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | EN | M0)) /* hsusb0_data3 */\
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | EN | M0)) /* hsusb0_data4 */\
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | EN | M0)) /* hsusb0_data5 */\
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | EN | M0)) /* hsusb0_data6 */\
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | EN | M0)) /* hsusb0_data7 */ \
- /* I2C1 */ \
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* i2c1_scl */ \
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* i2c1_sda */ \
- /* I2C2 */ \
- MUX_VAL(CP(I2C2_SCL), (IEN | PTD | DIS | M0)) /* i2c2_scl */ \
- MUX_VAL(CP(I2C2_SDA), (IEN | PTD | DIS | M0)) /* i2c2_sda */ \
- /* I2C3 */ \
- MUX_VAL(CP(I2C3_SCL), (IEN | PTD | DIS | M0)) /* i2c3_scl */ \
- MUX_VAL(CP(I2C3_SDA), (IEN | PTD | DIS | M0)) /* i2c3_sda */ \
- /* I2C4 */ \
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* i2c4_scl */ \
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* i2c4_sda */ \
- /* HDQ */ \
- MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) /* gpio_170 */ \
- /* MCSPI1 */ \
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | DIS | M4)) /* gpio_175 */ \
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /* gpio_176 */ \
- MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTD | DIS | M4)) /* gpio_177 */ \
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M0)) /* mcspi2_clk */ \
- MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | DIS | M0)) /* mcspi2_simo */ \
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /* mcspi2_somi */ \
- MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTD | DIS | M4)) /* gpio_181 */ \
- MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | DIS | M4)) /* gpio_182 */ \
- /* SYS */ \
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* sys_32k */ \
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /* sys_clkreq */ \
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /* sys_nirq */ \
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(SYS_BOOT6), (IEN | PTU | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(SYS_OFF_MODE), (IDIS | PTD | DIS | M0)) /* sys_off_mode */ \
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4)) /* gpio_10 */ \
- MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | EN | M7)) /* safe_mode */ \
- /* JTAG */ \
- MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /* jtag_ntrst */ \
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /* jtag_tck */ \
- MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M0)) /* jtag_tms */ \
- MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M0)) /* jtag_tdi */ \
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /* jtag_emu0 */ \
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /* jtag_emu1 */ \
- /* ETK */ \
- MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_clk */ \
- MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /* sdmmc3_cmd */ \
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M4)) /* gpio_14 */ \
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M4)) /* gpio_15 */ \
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | DIS | M4)) /* gpio_16 */ \
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat3 */ \
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat0 */ \
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat1 */ \
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat2 */ \
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M4)) /* gpio_21 */ \
- MUX_VAL(CP(ETK_D8_ES2), (IDIS | PTD | DIS | M4)) /* gpio_22 */ \
- MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M4)) /* gpio_23 */ \
- MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | EN | M4)) /* gpio_24 */ \
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) /* gpio_25 */ \
- MUX_VAL(CP(ETK_D12_ES2), (IDIS | PTD | DIS | M4)) /* gpio_26 */ \
- MUX_VAL(CP(ETK_D13_ES2), (IDIS | PTD | DIS | M4)) /* gpio_27 */ \
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* gpio_28 */ \
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | EN | M4)) /* gpio_29 */ \
- /* D2D */ \
- MUX_VAL(CP(D2D_MCAD0), (IEN | PTD | EN | M0)) /* d2d_mcad0 */ \
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /* d2d_mcad1 */ \
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /* d2d_mcad2 */ \
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /* d2d_mcad3 */ \
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /* d2d_mcad4 */ \
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /* d2d_mcad5 */ \
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /* d2d_mcad6 */ \
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /* d2d_mcad7 */ \
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /* d2d_mcad8 */ \
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /* d2d_mcad9 */ \
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /* d2d_mcad10 */ \
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /* d2d_mcad11 */ \
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /* d2d_mcad12 */ \
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /* d2d_mcad13 */ \
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /* d2d_mcad14 */ \
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /* d2d_mcad15 */ \
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /* d2d_mcad16 */ \
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /* d2d_mcad17 */ \
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /* d2d_mcad18 */ \
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /* d2d_mcad19 */ \
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /* d2d_mcad20 */ \
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /* d2d_mcad21 */ \
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /* d2d_mcad22 */ \
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /* d2d_mcad23 */ \
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /* d2d_mcad24 */ \
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /* d2d_mcad25 */ \
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /* d2d_mcad26 */ \
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /* d2d_mcad27 */ \
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /* d2d_mcad28 */ \
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /* d2d_mcad29 */ \
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /* d2d_mcad30 */ \
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /* d2d_mcad31 */ \
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /* d2d_mcad32 */ \
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /* d2d_mcad33 */ \
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /* d2d_mcad34 */ \
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /* d2d_mcad35 */ \
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /* d2d_mcad36 */ \
- MUX_VAL(CP(D2D_CLK26MI), (IDIS | PTD | DIS | M0)) /* d2d_clk26mi */ \
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTU | EN | M0)) /* d2d_nrespwron */ \
- MUX_VAL(CP(D2D_NRESWARM), (IDIS | PTD | DIS | M0)) /* d2d_nreswarm */ \
- MUX_VAL(CP(D2D_ARM9NIRQ), (IDIS | PTD | DIS | M0)) /* d2d_arm9nirq */ \
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IDIS | PTD | DIS | M0)) /* d2d_uma2p6fiq */ \
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | DIS | M0)) /* d2d_spint */ \
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | DIS | M0)) /* d2d_frint */ \
- MUX_VAL(CP(D2D_DMAREQ0), (IDIS | PTD | DIS | M0)) /* d2d_dmareq0 */ \
- MUX_VAL(CP(D2D_DMAREQ1), (IDIS | PTD | DIS | M0)) /* d2d_dmareq1 */ \
- MUX_VAL(CP(D2D_DMAREQ2), (IDIS | PTD | DIS | M0)) /* d2d_dmareq2 */ \
- MUX_VAL(CP(D2D_DMAREQ3), (IDIS | PTD | DIS | M0)) /* d2d_dmareq3 */ \
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /* d2d_n3gtrst */ \
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTU | EN | M0)) /* d2d_n3gtdi */ \
- MUX_VAL(CP(D2D_N3GTDO), (IDIS | PTD | DIS | M0)) /* d2d_n3gtdo */ \
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTU | EN | M0)) /* d2d_n3gtms */ \
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /* d2d_n3gtck */ \
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /* d2d_n3grtck */ \
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /* d2d_mstdby */ \
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /* d2d_swakeup */ \
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /* d2d_idlereq */ \
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /* d2d_idleack */ \
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /* d2d_mwrite */ \
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /* d2d_swrite */ \
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /* d2d_mread */ \
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /* d2d_sread */ \
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /* d2d_mbusflag */ \
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /* d2d_sbusflag */ \
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTD | DIS | M0)) /* sdrc_cke0 */ \
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M0)) /* sdrc_cke1 */ \
- MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M7)) /* safe_mode */ \
- MUX_VAL(CP(GPIO126), (IDIS | PTD | DIS | M4)) /* gpio_126 */ \
- MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /* gpio_128 */ \
- MUX_VAL(CP(GPIO129), (IEN | PTD | DIS | M4)) /* gpio_129 */
-
-#endif
* For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
* will be inserted after the appropriate (depending the interval setting) skeleton TD.
* If an interrupt has been detected the dev->irqhandler is called. The status and number
- * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
+ * of transferred bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
* dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned,
* the interrupt TD will be reactivated.
*
return result;
}
-/* get the status and the transfered len of a td chain.
+/* get the status and the transferred len of a td chain.
* called from the completion handler
*/
int usb_get_td_status(uhci_td_t *td,struct usb_device *dev)
(((info >> 21) & 0x7ff)!= 0x7ff) &&
(temp & 0x7FF)!=0x7ff)
{ /* if not setup and not null data pack */
- dev->act_len+=(temp & 0x7FF) + 1; /* the transfered len is act_len + 1 */
+ dev->act_len+=(temp & 0x7FF) + 1; /* the transferred len is act_len + 1 */
}
if(stat) { /* status no ok */
dev->status=stat;
if((td->dev_ptr!=0L) && !(status & TD_CTRL_ACTIVE)) {
/* td is not active and a device is assigned -> call irqhandler */
dev=(struct usb_device *)td->dev_ptr;
- dev->irq_act_len=((status & 0x7FF)==0x7FF) ? 0 : (status & 0x7FF) + 1; /* transfered length */
+ dev->irq_act_len=((status & 0x7FF)==0x7FF) ? 0 : (status & 0x7FF) + 1; /* transferred length */
dev->irq_status=usb_uhci_td_stat(status); /* get status */
res=dev->irq_handle(dev); /* call irqhandler */
if(res==1) {
--- /dev/null
+if TARGET_DRAGONBOARD410C
+
+config SYS_BOARD
+ default "dragonboard410c"
+
+config SYS_VENDOR
+ default "qualcomm"
+
+config SYS_SOC
+ default "apq8016"
+
+config SYS_CONFIG_NAME
+ default "dragonboard410c"
+
+endif
--- /dev/null
+DRAGONBOARD410C BOARD
+M: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+S: Maintained
+F: board/qualcomm/dragonboard410c/
+F: include/configs/dragonboard410c.h
+F: configs/dragonboard410c_defconfig
--- /dev/null
+#
+# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := dragonboard410c.o
+extra-y += head.o
--- /dev/null
+/*
+ * Board init file for Dragonboard 410C
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <usb.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+
+int board_prepare_usb(enum usb_init_type type)
+{
+ static struct udevice *pmic_gpio;
+ static struct gpio_desc hub_reset, usb_sel;
+ int ret = 0, node;
+
+ if (!pmic_gpio) {
+ ret = uclass_get_device_by_name(UCLASS_GPIO,
+ "pm8916_gpios@c000",
+ &pmic_gpio);
+ if (ret < 0) {
+ printf("Failed to find pm8916_gpios@c000 node.\n");
+ return ret;
+ }
+ }
+
+ /* Try to request gpios needed to start usb host on dragonboard */
+ if (!dm_gpio_is_valid(&hub_reset)) {
+ node = fdt_subnode_offset(gd->fdt_blob, pmic_gpio->of_offset,
+ "usb_hub_reset_pm");
+ if (node < 0) {
+ printf("Failed to find usb_hub_reset_pm dt node.\n");
+ return node;
+ }
+ ret = gpio_request_by_name_nodev(gd->fdt_blob, node, "gpios", 0,
+ &hub_reset, 0);
+ if (ret < 0) {
+ printf("Failed to request usb_hub_reset_pm gpio.\n");
+ return ret;
+ }
+ }
+
+ if (!dm_gpio_is_valid(&usb_sel)) {
+ node = fdt_subnode_offset(gd->fdt_blob, pmic_gpio->of_offset,
+ "usb_sw_sel_pm");
+ if (node < 0) {
+ printf("Failed to find usb_sw_sel_pm dt node.\n");
+ return 0;
+ }
+ ret = gpio_request_by_name_nodev(gd->fdt_blob, node, "gpios", 0,
+ &usb_sel, 0);
+ if (ret < 0) {
+ printf("Failed to request usb_sw_sel_pm gpio.\n");
+ return ret;
+ }
+ }
+
+ if (type == USB_INIT_HOST) {
+ /* Start USB Hub */
+ dm_gpio_set_dir_flags(&hub_reset,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ mdelay(100);
+ /* Switch usb to host connectors */
+ dm_gpio_set_dir_flags(&usb_sel,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ mdelay(100);
+ } else { /* Device */
+ /* Disable hub */
+ dm_gpio_set_dir_flags(&hub_reset, GPIOD_IS_OUT);
+ /* Switch back to device connector */
+ dm_gpio_set_dir_flags(&usb_sel, GPIOD_IS_OUT);
+ }
+
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+/* Check for vol- button - if pressed - stop autoboot */
+int misc_init_r(void)
+{
+ struct udevice *pon;
+ struct gpio_desc resin;
+ int node, ret;
+
+ ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8916_pon@800", &pon);
+ if (ret < 0) {
+ printf("Failed to find PMIC pon node. Check device tree\n");
+ return 0;
+ }
+
+ node = fdt_subnode_offset(gd->fdt_blob, pon->of_offset, "key_vol_down");
+ if (node < 0) {
+ printf("Failed to find key_vol_down node. Check device tree\n");
+ return 0;
+ }
+
+ if (gpio_request_by_name_nodev(gd->fdt_blob, node, "gpios", 0, &resin,
+ 0)) {
+ printf("Failed to request key_vol_down button.\n");
+ return 0;
+ }
+
+ if (dm_gpio_get_value(&resin)) {
+ setenv("bootdelay", "-1");
+ printf("Power button pressed - dropping to console.\n");
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * ARM64 header for proper chain-loading with Little Kernel.
+ *
+ * Little Kernel shipped with Dragonboard410C boots standard Linux images for
+ * ARM64. This file adds header that is required to boot U-Boot properly.
+ *
+ * For details see:
+ * https://www.kernel.org/doc/Documentation/arm64/booting.txt
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+.global _arm64_header
+_arm64_header:
+ b _start
+ .word 0
+ /* Image load offset from start of RAM, little-endian */
+ .quad CONFIG_SYS_TEXT_BASE-PHYS_SDRAM_1
+ /* Effective size of kernel image, little-endian */
+ .quad 0 /* 0x60000 - ignored */
+ /* Informative flags, little-endian */
+ .quad 0
+ .quad 0 /* reserved */
+ .quad 0 /* reserved */
+ .quad 0 /* reserved */
+ .byte 0x41 /* Magic number, "ARM\x64" */
+ .byte 0x52
+ .byte 0x4d
+ .byte 0x64
+ .word 0 /* reserved */
--- /dev/null
+#
+# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+Build & Run instructions:
+
+1) Install mkbootimg and dtbTool from
+ git://codeaurora.org/quic/kernel/skales (15ece94f09 worked for me)
+2) Setup CROSS_COMPILE to aarch64 compiler
+3) make dragonboard410c_config
+4) make
+5) generate fake, empty ramdisk (can have 0 bytes)
+$ touch rd
+
+6) Generate qualcomm device tree table with dtbTool [1]
+$ dtbTool -o dt.img arch/arm/dts
+
+7) Generate Android boot image with mkbootimg [2]:
+$ mkbootimg --kernel=u-boot-dtb.bin --output=u-boot.img --dt=dt.img \
+ --pagesize 2048 --base 0x80000000 --ramdisk=rd --cmdline=""
+
+8) Enter fastboot (reboot board with vol- button pressed)
+
+9) Boot it:
+$ fastboot boot u-boot.img
+or flash as kernel:
+$ fastboot flash boot u-boot.img
+$ fastboot reboot
+
+
+What is working:
+- UART
+- GPIO (SoC)
+- SD
+- eMMC
+- Reset
+- USB in EHCI mode (usb starts does switch device->host, usb stop does the opposite)
+- PMIC GPIOS (but not in generic subsystem)
+- PMIC "special" buttons (power, vol-)
+
+What is not working / known bugs:
+- SDHCI is slow (~2.5MiB/s for SD and eMMC)
+
+[1] To boot any kernel image, Little Kernel requires valid device tree for the
+platform it runs on. dtbTool creates device tree table that Little Kernel scans.
+Later on proper device tree is passed to next boot stage.
+Full device tree is not required to boot u-boot. Enough would be:
+/dts-v1/;
+
+/ {
+ model = "Qualcomm Technologies, Inc. Dragonboard 410c";
+ compatible = "qcom,dragonboard", "qcom,apq8016-sbc";
+ qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>;
+ qcom,board-id = <0x10018 0x0>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ chosen { };
+ aliases { };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0x3da00000>;
+ };
+};
+
+but for simplicity (and because size of image is not that critical) we use
+existing Qualcomm device trees.
+
+[2] Note that ramdisk is required, even if it is unused.
--- /dev/null
+/*
+ * Override linker script for fastboot-readable images
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * Based on arch/arm/cpu/armv8/u-boot.lds (Just add header)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_arm64_header)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(8);
+ .text :
+ {
+ *(.__image_copy_start)
+ board/qualcomm/dragonboard410c/head.o (.text*)
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(8);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(8);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(8);
+
+ . = .;
+
+ . = ALIGN(8);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(8);
+
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ . = ALIGN(8);
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rela.dyn : {
+ *(.rela*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ }
+
+ _end = .;
+
+ . = ALIGN(8);
+
+ .bss_start : {
+ KEEP(*(.__bss_start));
+ }
+
+ .bss : {
+ *(.bss*)
+ . = ALIGN(8);
+ }
+
+ .bss_end : {
+ KEEP(*(.__bss_end));
+ }
+
+ /DISCARD/ : { *(.dynsym) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
S: Maintained
F: board/raspberrypi/rpi/
F: include/configs/rpi.h
-F: configs/rpi_defconfig
+F: configs/rpi_*defconfig
/*
- * (C) Copyright 2012-2013,2015 Stephen Warren
+ * (C) Copyright 2012-2016 Stephen Warren
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <asm/arch/sdhci.h>
#include <asm/global_data.h>
#include <dm/platform_data/serial_pl01x.h>
+#include <dm/platform_data/serial_bcm283x_mu.h>
+#ifdef CONFIG_ARM64
+#include <asm/armv8/mmu.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
.platdata = &gpio_platdata,
};
+#ifdef CONFIG_PL01X_SERIAL
static const struct pl01x_serial_platdata serial_platdata = {
-#ifdef CONFIG_BCM2836
+#ifndef CONFIG_BCM2835
.base = 0x3f201000,
#else
.base = 0x20201000,
#endif
.type = TYPE_PL011,
- .clock = 3000000,
+ .skip_init = true,
};
U_BOOT_DEVICE(bcm2835_serials) = {
.name = "serial_pl01x",
.platdata = &serial_platdata,
};
+#else
+static const struct bcm283x_mu_serial_platdata serial_platdata = {
+ .base = 0x3f215040,
+ .clock = 250000000,
+ .skip_init = true,
+};
+
+U_BOOT_DEVICE(bcm2837_serials) = {
+ .name = "serial_bcm283x_mu",
+ .platdata = &serial_platdata,
+};
+#endif
struct msg_get_arm_mem {
struct bcm2835_mbox_hdr hdr;
static const struct rpi_model rpi_model_unknown = {
"Unknown model",
-#ifdef CONFIG_BCM2836
- "bcm2836-rpi-other.dtb",
-#else
- "bcm2835-rpi-other.dtb",
-#endif
+ "bcm283x-rpi-other.dtb",
false,
};
"bcm2836-rpi-2-b.dtb",
true,
},
+ [0x8] = {
+ "3 Model B",
+ "bcm2837-rpi-3-b.dtb",
+ true,
+ },
[0x9] = {
"Zero",
"bcm2835-rpi-zero.dtb",
static uint32_t rev_type;
static const struct rpi_model *model;
+#ifdef CONFIG_ARM64
+static struct mm_region bcm2837_mem_map[] = {
+ {
+ .base = 0x00000000UL,
+ .size = 0x3f000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .base = 0x3f000000UL,
+ .size = 0x01000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bcm2837_mem_map;
+#endif
+
int dram_init(void)
{
ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1);
+++ /dev/null
-RPI_2 BOARD
-M: Stephen Warren <swarren@wwwdotorg.org>
-S: Maintained
-F: board/raspberrypi/rpi_2/
-F: include/configs/rpi_2.h
-F: configs/rpi_2_defconfig
+++ /dev/null
-#
-# (C) Copyright 2012,2015 Stephen Warren
-#
-# SPDX-License-Identifier: GPL-2.0
-#
-
-obj-y := ../rpi/rpi.o
#include <asm/arch/sys_proto.h>
#include <spl.h>
#include <usb.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
DECLARE_GLOBAL_DATA_PTR;
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+config MACH_SUN50I
+ bool "sun50i (Allwinner A64)"
+ select ARM64
+ select SUNXI_GEN_SUN6I
+
config MACH_SUN8I_A83T
bool "sun8i (Allwinner A83T)"
select CPU_V7
endif
config SYS_CLK_FREQ
+ default 816000000 if MACH_SUN50I
default 912000000 if MACH_SUN7I
default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
default "sun7i" if MACH_SUN7I
default "sun8i" if MACH_SUN8I
default "sun9i" if MACH_SUN9I
+ default "sun50i" if MACH_SUN50I
config SYS_BOARD
default "sunxi"
slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
support for this.
+config INITIAL_USB_SCAN_DELAY
+ int "delay initial usb scan by x ms to allow builtin devices to init"
+ default 0
+ ---help---
+ Some boards have on board usb devices which need longer than the
+ USB spec's 1 second to connect from board powerup. Set this config
+ option to a non 0 value to add an extra delay before the first usb
+ bus scan.
+
config USB0_VBUS_PIN
string "Vbus enable pin for usb0 (otg)"
default ""
---help---
See USB1_VBUS_PIN help text.
+config USB3_VBUS_PIN
+ string "Vbus enable pin for usb3 (ehci2)"
+ default ""
+ ---help---
+ See USB1_VBUS_PIN help text.
+
config I2C0_ENABLE
bool "Enable I2C/TWI controller 0"
default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Set the GMAC Transmit Clock Delay Chain value.
config SPL_STACK_R_ADDR
- default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I
+ default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
default 0x2fe00000 if MACH_SUN9I
endif
F: configs/ba10_tv_box_defconfig
F: configs/Chuwi_V7_CW0825_defconfig
F: configs/Cubieboard_defconfig
+F: configs/dserve_dsrv9703c_defconfig
F: configs/Hyundai_A7HD_defconfig
F: configs/inet1_defconfig
F: configs/inet97fv2_defconfig
F: configs/Auxtek-T003_defconfig
F: configs/Auxtek-T004_defconfig
F: configs/CHIP_defconfig
+F: configs/difrnce_dit4350_defconfig
F: configs/Empire_electronix_d709_defconfig
F: configs/inet98v_rev2_defconfig
F: configs/mk802_a10s_defconfig
F: configs/UTOO_P66_defconfig
F: configs/Wobo_i5_defconfig
F: include/configs/sun6i.h
+F: configs/colorfly_e708_q1_defconfig
F: configs/CSQ_CS908_defconfig
F: configs/Mele_A1000G_quad_defconfig
F: configs/Mele_M9_defconfig
F: include/configs/sun8i.h
F: configs/ga10h_v1_1_defconfig
F: configs/gt90h_v4_defconfig
+F: configs/orangepi_2_defconfig
+F: configs/orangepi_one_defconfig
F: configs/orangepi_pc_defconfig
F: configs/orangepi_plus_defconfig
+F: configs/polaroid_mid2809pxe04_defconfig
F: configs/q8_a23_tablet_800x480_defconfig
F: configs/q8_a33_tablet_800x480_defconfig
F: configs/q8_a33_tablet_1024x600_defconfig
F: include/configs/sun9i.h
F: configs/Merrii_A80_Optimus_defconfig
+F: include/configs/sun50i.h
+F: configs/pine64_plus_defconfig
A20-OLIMEX-SOM-EVB BOARD
M: Marcus Cooper <codekipper@gmail.com>
F: configs/Cubieboard2_defconfig
F: configs/Cubietruck_defconfig
+CUBIETRUCK-PLUS BOARD
+M: Chen-Yu Tsai <wens@csie.org>
+S: Maintained
+F: configs/Cubietruck_plus_defconfig
+
GEMEI-G9 TABLET
M: Priit Laes <plaes@plaes.org>
S: Maintained
S: Maintained
F: configs/Hummingbird_A31_defconfig
+ICnova-A20-SWAC BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: configs/icnova-a20-swac_defconfig
+
+ITEAD IBOX BOARD
+M: Marcus Cooper <codekipper@gmail.com>
+S: Maintained
+F: configs/Itead_Ibox_A20_defconfig
+
INET 3F BOARD
M: Paul Kocialkowski <contact@paulk.fr>
S: Maintained
S: Maintained
F: configs/MSI_Primo81_defconfig
+SINLINX SINA31s BOARD
+M: Chen-Yu Tsai <wens@csie.org>
+S: Maintained
+F: configs/Sinlinx_SinA31s_defconfig
+W: http://linux-sunxi.org/Sinlinx_SinA31s
+
SINLINX SINA33 BOARD
M: Chen-Yu Tsai <wens@csie.org>
S: Maintained
M: Paul Kocialkowski <contact@paulk.fr>
S: Maintained
F: configs/Yones_Toptech_BD1078_defconfig
+
+YONES TOPTECH BS1078 V2 BOARD
+M: Peter Korsgaard <peter@korsgaard.com>
+S: Maintained
+F: configs/Yones_Toptech_BS1078_V2_defconfig
void scsi_init(void)
{
- printf("SUNXI SCSI INIT\n");
-#ifdef CONFIG_SATAPWR
- gpio_request(CONFIG_SATAPWR, "satapwr");
- gpio_direction_output(CONFIG_SATAPWR, 1);
- /* Give attached sata device time to power-up to avoid link timeouts */
- mdelay(500);
-#endif
-
if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0)
return;
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/usb_phy.h>
+#ifndef CONFIG_ARM64
+#include <asm/armv7.h>
+#endif
#include <asm/gpio.h>
#include <asm/io.h>
#include <nand.h>
/* add board specific code here */
int board_init(void)
{
- int id_pfr1, ret;
+ __maybe_unused int id_pfr1, ret;
gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
+#ifndef CONFIG_ARM64
asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
debug("id_pfr1: 0x%08x\n", id_pfr1);
/* Generic Timer Extension available? */
- if ((id_pfr1 >> 16) & 0xf) {
+ if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
+ uint32_t freq;
+
debug("Setting CNTFRQ\n");
- /* CNTFRQ == 24 MHz */
- asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
+
+ /*
+ * CNTFRQ is a secure register, so we will crash if we try to
+ * write this from the non-secure world (read is OK, though).
+ * In case some bootcode has already set the correct value,
+ * we avoid the risk of writing to it.
+ */
+ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
+ if (freq != CONFIG_TIMER_CLK_FREQ) {
+ debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
+ freq, CONFIG_TIMER_CLK_FREQ);
+#ifdef CONFIG_NON_SECURE
+ printf("arch timer frequency is wrong, but cannot adjust it\n");
+#else
+ asm volatile("mcr p15, 0, %0, c14, c0, 0"
+ : : "r"(CONFIG_TIMER_CLK_FREQ));
+#endif
+ }
}
+#endif /* !CONFIG_ARM64 */
ret = axp_gpio_init();
if (ret)
return ret;
+#ifdef CONFIG_SATAPWR
+ gpio_request(CONFIG_SATAPWR, "satapwr");
+ gpio_direction_output(CONFIG_SATAPWR, 1);
+#endif
+#ifdef CONFIG_MACPWR
+ gpio_request(CONFIG_MACPWR, "macpwr");
+ gpio_direction_output(CONFIG_MACPWR, 1);
+#endif
+
/* Uses dm gpio code so do this here and not in i2c_init_board() */
return soft_i2c_board_init();
}
return 0;
}
+#ifdef CONFIG_MACH_SUN50I
+void dram_init_banksize(void)
+{
+ /* We need to reserve the first 16MB of RAM for ATF */
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024);
+ gd->bd->bi_dram[0].size = get_effective_memsize() - (16 * 1024 * 1024);
+}
+#endif
+
#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
static void nand_pinmux_setup(void)
{
sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
}
-#elif defined(CONFIG_MACH_SUN8I)
+#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
/* SDC2: PC5-PC6, PC8-PC16 */
for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
#endif
+
+#ifdef CONFIG_AXP818_POWER
+ power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
+ power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
+ power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
+#endif
#endif
printf("DRAM:");
ramsize = sunxi_dram_init();
*/
static void parse_spl_header(const uint32_t spl_addr)
{
- struct boot_file_head *spl = (void *)spl_addr;
+ struct boot_file_head *spl = (void *)(ulong)spl_addr;
if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) == 0) {
uint8_t spl_header_version = spl->spl_signature[3];
if (spl_header_version == SPL_HEADER_VERSION) {
}
#endif
-#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
+ int __maybe_unused r;
+
#ifdef CONFIG_VIDEO_DT_SIMPLEFB
- return sunxi_simplefb_setup(blob);
+ r = sunxi_simplefb_setup(blob);
+ if (r)
+ return r;
#endif
+ return 0;
}
-#endif /* CONFIG_OF_BOARD_SETUP */
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
-int sunxi_gmac_initialize(bd_t *bis)
+void eth_init_board(void)
{
int pin;
struct sunxi_ccm_reg *const ccm =
for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
#endif
-
-#ifdef CONFIG_DM_ETH
- return 0;
-#else
-# ifdef CONFIG_RGMII
- return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
-# elif defined CONFIG_GMII
- return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
-# else
- return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
-# endif
-#endif
}
0x00001000,
0xA0000034,
0x0D000001,
- 0x40680208,
- 0x41034051,
- 0x12481A00,
- 0x802080D0,
- 0x34051406,
- 0x01A02490,
- 0x080D0000,
- 0x51406802,
- 0x02490340,
+ 0xE0680B2C,
+ 0x20834038,
+ 0x11441A00,
+ 0x80B2C0D0,
+ 0x34038E06,
+ 0x01A00208,
+ 0x2C0D0000,
+ 0x38E0680B,
+ 0x00208340,
0xD000001A,
- 0x0680A280,
+ 0x0680B2C0,
0x10040000,
0x00200000,
0x10040000,
0x00001000,
0xA0000034,
0x0D000001,
- 0x40680208,
- 0x49034051,
- 0x12481A02,
- 0x80A280D0,
- 0x34030C06,
+ 0xE0680B2C,
+ 0x20834038,
+ 0x11441A00,
+ 0x80B2C0D0,
+ 0x34038E06,
0x01A00040,
- 0x280D0002,
- 0x5140680A,
- 0x02490340,
- 0xD012481A,
- 0x0680A280,
+ 0x2C0D0002,
+ 0x38E0680B,
+ 0x00208340,
+ 0xD001041A,
+ 0x0680B2C0,
0x10040000,
0x00200000,
0x10040000,
0x14F3690D,
0x1A041414,
0x00D00000,
- 0x04864000,
- 0x59647A01,
- 0xD32CA3DE,
- 0xF551451E,
- 0x034CD348,
+ 0x18864000,
+ 0x49247A06,
+ 0xABCF23D7,
+ 0xF7DE791E,
+ 0x0356E388,
0x821A0000,
0x0000D000,
- 0x05140680,
- 0xD669A47A,
- 0x1ED32CA3,
- 0x48F55E79,
- 0x00034C92,
+ 0x05960680,
+ 0xD749247A,
+ 0x1EABCF23,
+ 0x88F7DE79,
+ 0x000356E3,
0x00080200,
0x00001000,
0x00080200,
0x14F3690D,
0x1A041414,
0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0x9228A3DE,
- 0xF65E791E,
- 0x034CD348,
- 0x821A0186,
+ 0x18864000,
+ 0x49247A06,
+ 0xABCF23D7,
+ 0xF7DE791E,
+ 0x0356E388,
+ 0x821A01C7,
0x0000D000,
0x00000680,
- 0xD669A47A,
- 0x1E9228A3,
- 0x48F65E79,
- 0x00034CD3,
+ 0xD749247A,
+ 0x1EABCF23,
+ 0x88F7DE79,
+ 0x000356E3,
0x00080200,
0x00001000,
0x00080200,
0x14F3690D,
0x1A041414,
0x00D00000,
- 0x0C864000,
- 0x79E47A03,
- 0xB2AAA3D1,
- 0xF551451E,
- 0x035CD348,
+ 0x18864000,
+ 0x49247A06,
+ 0xABCF23D7,
+ 0xF7DE791E,
+ 0x0356E388,
0x821A0000,
0x0000D000,
0x00000680,
- 0xD159647A,
- 0x1ED32CA3,
- 0x48F55145,
- 0x00035CD3,
+ 0xD749247A,
+ 0x1EABCF23,
+ 0x88F7DE79,
+ 0x000356E3,
0x00080200,
0x00001000,
0x00080200,
0x14F1690D,
0x1A041414,
0x00D00000,
- 0x04864000,
- 0x69A47A01,
- 0x9228A3D6,
- 0xF65E791E,
- 0x034C9248,
+ 0x18864000,
+ 0x49247A06,
+ 0xABCF23D7,
+ 0xF7DE791E,
+ 0x0356E388,
0x821A0000,
0x0000D000,
0x00000680,
- 0xDE59647A,
- 0x1ED32CA3,
- 0x48F55E79,
- 0x00034CD3,
+ 0xD749247A,
+ 0x1EABCF23,
+ 0x88F7DE79,
+ 0x000356E3,
0x00080200,
0x00001000,
0x00080200,
#define CONFIG_HPS_DBCTRL_STAYOSC1 1
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
#define CONFIG_HPS_CLK_OSC2_HZ 25000000
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
#define CONFIG_HPS_CLK_NAND_HZ 50000000
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 370000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
#define CONFIG_HPS_CLK_SPIM_HZ 200000000
#define CONFIG_HPS_CLK_CAN0_HZ 12500000
#define CONFIG_HPS_CLK_CAN1_HZ 12500000
#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 8
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
/* Sequencer defines configuration */
#define AFI_RATE_RATIO 1
-#define CALIB_LFIFO_OFFSET 8
-#define CALIB_VFIFO_OFFSET 6
+#define CALIB_LFIFO_OFFSET 12
+#define CALIB_VFIFO_OFFSET 10
#define ENABLE_SUPER_QUICK_CALIBRATION 0
#define IO_DELAY_PER_DCHAIN_TAP 25
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
#define MAX_LATENCY_COUNT_WIDTH 5
#define READ_VALID_FIFO_SIZE 16
-#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
#define RW_MGR_MEM_ADDRESS_MIRRORING 0
#define RW_MGR_MEM_DATA_MASK_WIDTH 4
#define RW_MGR_MEM_DATA_WIDTH 32
const u32 ac_rom_init[] = {
0x20700000,
0x20780000,
- 0x10080431,
- 0x10080530,
- 0x10090044,
- 0x100a0008,
+ 0x10080471,
+ 0x10080570,
+ 0x10090006,
+ 0x100a0218,
0x100b0000,
0x10380400,
- 0x10080449,
- 0x100804c8,
- 0x100a0024,
- 0x10090010,
+ 0x10080469,
+ 0x100804e8,
+ 0x100a0006,
+ 0x10090218,
0x100b0000,
0x30780000,
0x38780000,
#
obj-y := theadorable.o
+obj-y += fpga.o
--- /dev/null
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <altera.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-mvebu/spi.h>
+#include "theadorable.h"
+
+/*
+ * FPGA programming support
+ */
+static int fpga_pre_fn(int cookie)
+{
+ int gpio_config = COOKIE2CONFIG(cookie);
+ int gpio_done = COOKIE2DONE(cookie);
+ int ret;
+
+ debug("%s (%d): cookie=%08x gpio_config=%d gpio_done=%d\n",
+ __func__, __LINE__, cookie, gpio_config, gpio_done);
+
+ /* Configure config pin */
+ /* Set to output */
+ ret = gpio_request(gpio_config, "CONFIG");
+ if (ret < 0)
+ return ret;
+ gpio_direction_output(gpio_config, 1);
+
+ /* Configure done pin */
+ /* Set to input */
+ ret = gpio_request(gpio_done, "DONE");
+ if (ret < 0)
+ return ret;
+
+ gpio_direction_input(gpio_done);
+
+ return 0;
+}
+
+static int fpga_config_fn(int assert, int flush, int cookie)
+{
+ int gpio_config = COOKIE2CONFIG(cookie);
+
+ debug("%s (%d): cookie=%08x gpio_config=%d\n",
+ __func__, __LINE__, cookie, gpio_config);
+
+ if (assert)
+ gpio_set_value(gpio_config, 1);
+ else
+ gpio_set_value(gpio_config, 0);
+
+ return 0;
+}
+
+static int fpga_write_fn(const void *buf, size_t len, int flush, int cookie)
+{
+ int spi_bus = COOKIE2SPI_BUS(cookie);
+ int spi_dev = COOKIE2SPI_DEV(cookie);
+ struct kwspi_registers *reg;
+ u32 control_reg;
+ u32 config_reg;
+ void *dst;
+
+ /*
+ * Write data to FPGA attached to SPI bus via SPI direct write.
+ * This results in the fastest and easiest way to program the
+ * bitstream into the FPGA.
+ */
+ debug("%s (%d): cookie=%08x spi_bus=%d spi_dev=%d\n",
+ __func__, __LINE__, cookie, spi_bus, spi_dev);
+
+ if (spi_bus == 0) {
+ reg = (struct kwspi_registers *)MVEBU_REGISTER(0x10600);
+ dst = (void *)SPI_BUS0_DEV1_BASE;
+ } else {
+ reg = (struct kwspi_registers *)MVEBU_REGISTER(0x10680);
+ dst = (void *)SPI_BUS1_DEV2_BASE;
+ }
+
+ /* Configure SPI controller for direct access mode */
+ control_reg = readl(®->ctrl);
+ config_reg = readl(®->cfg);
+ writel(0x00000214, ®->cfg); /* 27MHz clock */
+ writel(0x00000000, ®->dw_cfg); /* don't de-asset CS */
+ writel(KWSPI_CSN_ACT, ®->ctrl); /* activate CS */
+
+ /* Copy data to the SPI direct mapped window */
+ memcpy(dst, buf, len);
+
+ /* Restore original register values */
+ writel(control_reg, ®->ctrl);
+ writel(config_reg, ®->cfg);
+
+ return 0;
+}
+
+/* Returns the state of CONF_DONE Pin */
+static int fpga_done_fn(int cookie)
+{
+ int gpio_done = COOKIE2DONE(cookie);
+ unsigned long ts;
+
+ debug("%s (%d): cookie=%08x gpio_done=%d\n",
+ __func__, __LINE__, cookie, gpio_done);
+
+ ts = get_timer(0);
+ do {
+ if (gpio_get_value(gpio_done))
+ return 0;
+ } while (get_timer(ts) < 1000);
+
+ /* timeout so return error */
+ return -ENODEV;
+}
+
+static altera_board_specific_func stratixv_fns = {
+ .pre = fpga_pre_fn,
+ .config = fpga_config_fn,
+ .write = fpga_write_fn,
+ .done = fpga_done_fn,
+};
+
+static Altera_desc altera_fpga[] = {
+ {
+ /* Family */
+ Altera_StratixV,
+ /* Interface type */
+ passive_serial,
+ /* No limitation as additional data will be ignored */
+ -1,
+ /* Device function table */
+ (void *)&stratixv_fns,
+ /* Base interface address specified in driver */
+ NULL,
+ /* Cookie implementation */
+ /*
+ * In this 32bit word the following information is coded:
+ * Bit 31 ... Bit 0
+ * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
+ */
+ FPGA_COOKIE(0, 1, 26, 7)
+ },
+ {
+ /* Family */
+ Altera_StratixV,
+ /* Interface type */
+ passive_serial,
+ /* No limitation as additional data will be ignored */
+ -1,
+ /* Device function table */
+ (void *)&stratixv_fns,
+ /* Base interface address specified in driver */
+ NULL,
+ /* Cookie implementation */
+ /*
+ * In this 32bit word the following information is coded:
+ * Bit 31 ... Bit 0
+ * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
+ */
+ FPGA_COOKIE(1, 2, 29, 9)
+ },
+};
+
+/* Add device descriptor to FPGA device table */
+void board_fpga_add(void)
+{
+ int i;
+
+ fpga_init();
+ for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
+ fpga_add(fpga_altera, &altera_fpga[i]);
+}
*/
#include <common.h>
+#include <i2c.h>
+#include <pci.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
+#include <linux/crc8.h>
+#include <linux/mbus.h>
#ifdef CONFIG_NET
#include <netdev.h>
#endif
+#include "theadorable.h"
#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
DECLARE_GLOBAL_DATA_PTR;
+#define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
+#define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \
+ (MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
+
#define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780
#define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0
#define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0))
#define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c
#define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000
+#define GPIO_USB0_PWR_ON 18
+#define GPIO_USB1_PWR_ON 19
+
+#define PEX_SWITCH_NOT_FOUNT_LIMIT 3
+
+#define STM_I2C_BUS 1
+#define STM_I2C_ADDR 0x27
+#define REBOOT_DELAY 1000 /* reboot-delay in ms */
+
/* DDR3 static configuration */
static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
{0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */
int board_init(void)
{
+ int ret;
+
/* adress of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+ /*
+ * Map SPI devices via MBUS so that they can be accessed via
+ * the SPI direct access mode
+ */
+ mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE,
+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1);
+ mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
+
+ /*
+ * Set RX Channel Control 0 Register:
+ * Tests have shown, that setting the LPF_COEF from 0 (1/8)
+ * to 3 (1/1) results in a more stable USB connection.
+ */
+ setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
+ setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
+ setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
+
+ /* Toggle USB power */
+ ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
+ if (ret < 0)
+ return ret;
+ gpio_direction_output(GPIO_USB0_PWR_ON, 0);
+ ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
+ if (ret < 0)
+ return ret;
+ gpio_direction_output(GPIO_USB1_PWR_ON, 0);
+ mdelay(1);
+ gpio_set_value(GPIO_USB0_PWR_ON, 1);
+ gpio_set_value(GPIO_USB1_PWR_ON, 1);
+
return 0;
}
int checkboard(void)
{
- puts("Board: theadorable\n");
+ board_fpga_add();
return 0;
}
return mvebu_lcd_register_init(&lcd_info);
}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ pci_dev_t bdf;
+ ulong bootcount;
+
+ /*
+ * Check if the PEX switch is detected (somtimes its not available
+ * on the PCIe bus). In this case, try to recover by issuing a
+ * soft-reset or even a power-cycle, depending on the bootcounter
+ * value.
+ */
+ bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0);
+ if (bdf == -1) {
+ u8 i2c_buf[8];
+ int ret;
+
+ /* PEX switch not found! */
+ bootcount = bootcount_load();
+ printf("Failed to find PLX PEX-switch (bootcount=%ld)\n",
+ bootcount);
+ if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) {
+ printf("Issuing power-switch via uC!\n");
+
+ printf("Issuing power-switch via uC!\n");
+ i2c_set_bus_num(STM_I2C_BUS);
+ i2c_buf[0] = STM_I2C_ADDR << 1;
+ i2c_buf[1] = 0xc5; /* cmd */
+ i2c_buf[2] = 0x01; /* enable */
+ /* Delay before reboot */
+ i2c_buf[3] = REBOOT_DELAY & 0x00ff;
+ i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8;
+ /* Delay before shutdown */
+ i2c_buf[5] = 0x00;
+ i2c_buf[6] = 0x00;
+ i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7);
+
+ ret = i2c_write(STM_I2C_ADDR, 0, 0, &i2c_buf[1], 7);
+ if (ret) {
+ printf("I2C write error (ret=%d)\n", ret);
+ printf("Issuing soft-reset...\n");
+ /* default handling: SOFT reset */
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ /* Wait for power-cycle to occur... */
+ printf("Waiting for power-cycle via uC...\n");
+ while (1)
+ ;
+ } else {
+ printf("Issuing soft-reset...\n");
+ /* default handling: SOFT reset */
+ do_reset(NULL, 0, 0, NULL);
+ }
+ }
+
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Base addresses for the SPI direct access mode */
+#define SPI_BUS0_DEV1_BASE 0xe0000000
+#define SPI_BUS0_DEV1_SIZE (1 << 20)
+#define SPI_BUS1_DEV2_BASE (SPI_BUS0_DEV1_BASE + SPI_BUS0_DEV1_SIZE)
+
+void board_fpga_add(void);
int board_late_init(void)
{
- init_sata(0);
setup_board_eeprom_env();
/*
.version = CPSW_CTRL_VERSION_2,
};
+static u64 mac_to_u64(u8 mac[6])
+{
+ int i;
+ u64 addr = 0;
+
+ for (i = 0; i < 6; i++) {
+ addr <<= 8;
+ addr |= mac[i];
+ }
+
+ return addr;
+}
+
+static void u64_to_mac(u64 addr, u8 mac[6])
+{
+ mac[5] = addr;
+ mac[4] = addr >> 8;
+ mac[3] = addr >> 16;
+ mac[2] = addr >> 24;
+ mac[1] = addr >> 32;
+ mac[0] = addr >> 40;
+}
+
int board_eth_init(bd_t *bis)
{
int ret;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
uint32_t ctrl_val;
+ int i;
+ u64 mac1, mac2;
+ u8 mac_addr1[6], mac_addr2[6];
+ int num_macs;
/* try reading mac address from efuse */
mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
if (ret < 0)
printf("Error %d registering CPSW switch\n", ret);
+ /*
+ * Export any Ethernet MAC addresses from EEPROM.
+ * On AM57xx the 2 MAC addresses define the address range
+ */
+ board_ti_get_eth_mac_addr(0, mac_addr1);
+ board_ti_get_eth_mac_addr(1, mac_addr2);
+
+ if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
+ mac1 = mac_to_u64(mac_addr1);
+ mac2 = mac_to_u64(mac_addr2);
+
+ /* must contain an address range */
+ num_macs = mac2 - mac1 + 1;
+ /* <= 50 to protect against user programming error */
+ if (num_macs > 0 && num_macs <= 50) {
+ for (i = 0; i < num_macs; i++) {
+ u64_to_mac(mac1 + i, mac_addr);
+ if (is_valid_ethaddr(mac_addr)) {
+ eth_setenv_enetaddr_by_index("eth",
+ i + 2,
+ mac_addr);
+ }
+ }
+ }
+ }
+
return ret;
}
#endif
#include <dwc3-uboot.h>
#include <dwc3-omap-uboot.h>
#include <ti-usb-phy-uboot.h>
+#include <miiphy.h>
#include "mux_data.h"
#include "../common/board_detect.h"
#define board_is_dra74x_evm() board_ti_is("5777xCPU")
+#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
#define board_is_dra74x_revh_or_later() board_is_dra74x_evm() && \
(strncmp("H", board_ti_get_rev(), 1) <= 0)
+#define board_is_dra72x_revc_or_later() board_is_dra72x_evm() && \
+ (strncmp("C", board_ti_get_rev(), 1) <= 0)
#define board_ti_get_emif_size() board_ti_get_emif1_size() + \
board_ti_get_emif2_size()
.emif_rd_wr_exec_thresh = 0x00000305
};
+const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
+ .sdram_config_init = 0x61862BB2,
+ .sdram_config = 0x61862BB2,
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x0000514D,
+ .ref_ctrl_final = 0x0000144A,
+ .sdram_tim1 = 0xD1137824,
+ .sdram_tim2 = 0x30B37FE3,
+ .sdram_tim3 = 0x409F8AD8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x5007190B,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0824400E,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400E,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
+ .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
+ .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
+ .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
.sdram_config_init = 0x61851ab2,
.sdram_config = 0x61851ab2,
}
break;
case DRA722_ES1_0:
- *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
+ case DRA722_ES2_0:
+ if (ram_size < CONFIG_MAX_MEM_MAPPED)
+ *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
+ else
+ *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
break;
default:
*regs = &emif1_ddr3_532_mhz_1cs;
.is_ma_present = 0x1
};
+/*
+ * DRA722 EVM EMIF1 2GB CONFIGURATION
+ * EMIF1 4 devices of 512Mb x 8 Micron
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
+ .dmm_lisa_map_0 = 0x0,
+ .dmm_lisa_map_1 = 0x0,
+ .dmm_lisa_map_2 = 0x80700100,
+ .dmm_lisa_map_3 = 0xFF020100,
+ .is_ma_present = 0x1
+};
+
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
u64 ram_size;
*dmm_lisa_regs = &lisa_map_dra7_1536MB;
break;
case DRA722_ES1_0:
+ case DRA722_ES2_0:
default:
- *dmm_lisa_regs = &lisa_map_2G_x_2;
+ if (ram_size < CONFIG_MAX_MEM_MAPPED)
+ *dmm_lisa_regs = &lisa_map_2G_x_2;
+ else
+ *dmm_lisa_regs = &lisa_map_2G_x_4;
+ break;
}
}
if (board_is_dra74x_evm()) {
bname = "DRA74x EVM";
- /* If EEPROM is not populated */
+ } else if (board_is_dra72x_evm()) {
+ bname = "DRA72x EVM";
} else {
+ /* If EEPROM is not populated */
if (is_dra72x())
bname = "DRA72x EVM";
else
#ifdef CONFIG_IODELAY_RECALIBRATION
void recalibrate_iodelay(void)
{
- struct pad_conf_entry const *pads;
+ struct pad_conf_entry const *pads, *delta_pads = NULL;
struct iodelay_cfg_entry const *iodelay;
- int npads, niodelays;
+ int npads, niodelays, delta_npads = 0;
+ int ret;
switch (omap_revision()) {
case DRA722_ES1_0:
- pads = dra72x_core_padconf_array;
- npads = ARRAY_SIZE(dra72x_core_padconf_array);
- iodelay = dra72_iodelay_cfg_array;
- niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array);
+ case DRA722_ES2_0:
+ pads = dra72x_core_padconf_array_common;
+ npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
+ if (board_is_dra72x_revc_or_later()) {
+ delta_pads = dra72x_rgmii_padconf_array_revc;
+ delta_npads =
+ ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
+ iodelay = dra72_iodelay_cfg_array_revc;
+ niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
+ } else {
+ delta_pads = dra72x_rgmii_padconf_array_revb;
+ delta_npads =
+ ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
+ iodelay = dra72_iodelay_cfg_array_revb;
+ niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
+ }
break;
case DRA752_ES1_0:
case DRA752_ES1_1:
RGMII1_ID_MODE_N_MASK);
break;
}
- __recalibrate_iodelay(pads, npads, iodelay, niodelays);
+ /* Setup I/O isolation */
+ ret = __recalibrate_iodelay_start();
+ if (ret)
+ goto err;
+
+ /* Do the muxing here */
+ do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
+
+ /* Now do the weird minor deltas that should be safe */
+ if (delta_npads)
+ do_set_mux32((*ctrl)->control_padconf_core_base,
+ delta_pads, delta_npads);
+
+ /* Setup IOdelay configuration */
+ ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
+err:
+ /* Closeup.. remove isolation */
+ __recalibrate_iodelay_end(ret);
}
#endif
if (*omap_si_rev == DRA722_ES1_0)
cpsw_data.active_slave = 1;
+ if (board_is_dra72x_revc_or_later()) {
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
+ cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
+ }
+
ret = cpsw_register(&cpsw_data);
if (ret < 0)
printf("Error %d registering CPSW switch\n", ret);
return;
/* Do not enable VTT for DRA722 */
- if (omap_revision() == DRA722_ES1_0)
+ if (is_dra72x())
return;
/*
#include <asm/arch/mux_dra7xx.h>
-const struct pad_conf_entry dra72x_core_padconf_array[] = {
+const struct pad_conf_entry dra72x_core_padconf_array_common[] = {
{GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
{GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
{GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
{VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
{MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
- {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
- {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
- {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
- {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
- {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
- {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
- {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d0.rgmii1_txc */
- {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d1.rgmii1_txctl */
- {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d2.rgmii1_txd3 */
- {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d3.rgmii1_txd2 */
- {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d4.rgmii1_txd1 */
- {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d5.rgmii1_txd0 */
- {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d6.rgmii1_rxc */
- {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d7.rgmii1_rxctl */
- {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d8.rgmii1_rxd3 */
- {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d9.rgmii1_rxd2 */
- {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d10.rgmii1_rxd1 */
- {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d11.rgmii1_rxd0 */
{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
{GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
{GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
{GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
- {XREF_CLK1, (M5 | PIN_OUTPUT)}, /* xref_clk1.atl_clk1 */
- {XREF_CLK2, (M5 | PIN_OUTPUT)}, /* xref_clk2.atl_clk2 */
{MCASP1_AXR0, (M10 | PIN_INPUT_SLEW)}, /* mcasp1_axr0.i2c5_sda */
{MCASP1_AXR1, (M10 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.i2c5_scl */
{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
{MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
- {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
{SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
{SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
{SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
{WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */
};
+const struct pad_conf_entry dra72x_rgmii_padconf_array_revb[] = {
+ {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
+ {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d0.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d1.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d2.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d3.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d4.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d5.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d6.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d7.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d8.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d9.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d10.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d11.rgmii1_rxd0 */
+ {XREF_CLK1, (M5 | PIN_OUTPUT)}, /* xref_clk1.atl_clk1 */
+ {XREF_CLK2, (M5 | PIN_OUTPUT)}, /* xref_clk2.atl_clk2 */
+};
+
+const struct pad_conf_entry dra72x_rgmii_padconf_array_revc[] = {
+ {VIN2A_FLD0, (M14 | PIN_INPUT)}, /* vin2a_fld0.gpio3_30 */
+ {RGMII0_TXC, (M0 | PIN_OUTPUT)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_OUTPUT)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_OUTPUT)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_OUTPUT)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_OUTPUT)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_OUTPUT)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {VIN2A_D12, (M3 | PIN_OUTPUT)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_OUTPUT)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_OUTPUT)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_OUTPUT)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_OUTPUT)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_OUTPUT)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d18.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d20.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d21.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d22.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d23.rgmii1_rxd0 */
+ {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
+};
+
const struct pad_conf_entry early_padconf[] = {
#if (CONFIG_CONS_INDEX == 1)
{UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */
};
#ifdef CONFIG_IODELAY_RECALIBRATION
-const struct iodelay_cfg_entry dra72_iodelay_cfg_array[] = {
+const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revb[] = {
{0x6F0, 359, 0}, /* RGMMI0_RXC_IN */
{0x6FC, 129, 1896}, /* RGMMI0_RXCTL_IN */
{0x708, 80, 1391}, /* RGMMI0_RXD0_IN */
{0x188, 0, 0}, /* CFG_GPMC_A18_OUT */
{0x374, 121, 0}, /* CFG_GPMC_CS2_OUT */
};
+
+const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revc[] = {
+ {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
+ {0x0150, 2247, 1186}, /* CFG_GPMC_A14_IN */
+ {0x015C, 2176, 1197}, /* CFG_GPMC_A15_IN */
+ {0x0168, 2229, 1268}, /* CFG_GPMC_A16_IN */
+ {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
+ {0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */
+ {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
+ {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
+};
+
#endif
const struct pad_conf_entry dra74x_core_padconf_array[] = {
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "board.h"
#include <common.h>
+#include "board.h"
#include <spl.h>
#include <exports.h>
#include <fdt_support.h>
#define XILINX_BOARD_NAME microblaze-generic
-/* System Clock Frequency */
-#define XILINX_CLOCK_FREQ 100000000
-
/* Microblaze is microblaze_0 */
#define XILINX_USE_MSR_INSTR 1
#define XILINX_FSL_NUMBER 3
-/* Interrupt controller is opb_intc_0 */
-#define XILINX_INTC_BASEADDR 0x41200000
-#define XILINX_INTC_NUM_INTR_INPUTS 6
-
-/* Timer pheriphery is opb_timer_1 */
-#define XILINX_TIMER_BASEADDR 0x41c00000
-#define XILINX_TIMER_IRQ 0
-
/* GPIO is LEDs_4Bit*/
#define XILINX_GPIO_BASEADDR 0x40000000
}
#endif
+int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
+{
+#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
+ defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
+ if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
+ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
+ ethaddr, 6))
+ printf("I2C EEPROM MAC address read failed\n");
+#endif
+
+ return 0;
+}
+
int dram_init(void)
{
int node;
/* .. SRCSEL = 0x0 */
/* .. ==> 0XF8000154[5:4] = 0x00000000U */
/* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. DIVISOR = 0x14 */
- /* .. ==> 0XF8000154[13:8] = 0x00000014U */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
+ /* .. DIVISOR = 0xa */
+ /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
/* .. */
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
/* .. .. START: TRACE CLOCK */
/* .. .. FINISH: TRACE CLOCK */
/* .. .. CLKACT = 0x1 */
/* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
/* .. .. */
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
- /* .. .. SRCSEL = 0x3 */
- /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */
- /* .. .. DIVISOR0 = 0x6 */
- /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x7 */
+ /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
/* .. .. DIVISOR1 = 0x1 */
/* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
/* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
/* .. .. */
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U),
- /* .. .. SRCSEL = 0x2 */
- /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */
- /* .. .. DIVISOR0 = 0x35 */
- /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */
- /* .. .. DIVISOR1 = 0x2 */
- /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x5 */
+ /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
/* .. .. SRCSEL = 0x0 */
/* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
/* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR0 = 0xa */
- /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
+ /* .. .. DIVISOR0 = 0x14 */
+ /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
/* .. .. DIVISOR1 = 0x1 */
/* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
/* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
/* .. .. */
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U),
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
/* .. .. CLK_621_TRUE = 0x1 */
/* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
/* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
/* .. .. reg_ddrc_burst_rdwr = 0x4 */
/* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
/* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
- /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */
- /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */
- /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */
+ /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
+ /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
+ /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
/* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
/* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
/* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
/* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
/* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
/* .. .. */
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
/* .. .. reg_ddrc_force_low_pri_n = 0x0 */
/* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
/* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. FINISH: DDRIOB SETTINGS */
/* .. START: MIO PROGRAMMING */
/* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000700[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000700[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000700[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000700[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000700[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000700[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000700[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000700[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000700[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
/* .. ==> 0XF8000704[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. L0_SEL = 1 */
/* .. */
EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
/* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800071C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800071C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800071C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800071C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800071C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800071C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800071C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800071C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800071C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000720[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000720[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000720[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000720[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000720[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000720[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000720[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000720[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000720[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000724[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000724[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000724[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000724[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000724[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000724[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000724[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000724[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000724[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000728[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000728[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000728[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000728[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000728[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000728[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000728[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000728[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000728[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800072C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800072C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800072C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800072C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800072C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800072C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800072C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF800072C[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800072C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000730[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000730[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000730[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000730[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000730[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000730[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000730[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000730[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000730[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000734[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000734[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000734[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000734[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000734[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000734[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000734[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000734[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000734[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000738[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000738[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000738[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000738[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000738[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000738[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000738[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000738[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000738[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800073C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800073C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800073C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800073C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800073C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800073C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800073C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF800073C[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800073C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
/* .. ==> 0XF8000740[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. L0_SEL = 1 */
/* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
/* .. */
EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
/* .. TRI_ENABLE = 1 */
/* .. ==> 0XF80007BC[0:0] = 0x00000001U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
/* .. */
EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
/* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
+ /* .. TRI_ENABLE = 0 */
/* .. ==> 0XF80007D0[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. L0_SEL = 0 */
/* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
/* .. */
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
- /* .. CD = 0x3e */
- /* .. ==> 0XE0001018[15:0] = 0x0000003EU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */
+ /* .. CD = 0x7c */
+ /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
/* .. */
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
/* .. STPBRK = 0x0 */
/* .. ==> 0XE0001000[8:8] = 0x00000000U */
/* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
/* .. */
EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
/* .. FINISH: UART REGISTERS */
- /* .. START: TPIU WIDTH IN CASE OF EMIO */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0XC5ACCE55 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. .. START: TRACE CURRENT PORT SIZE */
- /* .. .. a = 2 */
- /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U),
- /* .. .. FINISH: TRACE CURRENT PORT SIZE */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0X0 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */
/* .. START: QSPI REGISTERS */
/* .. Holdb_dr = 1 */
/* .. ==> 0XE000D000[19:19] = 0x00000001U */
/* .. .. .. .. START: DIR MODE BANK 0 */
/* .. .. .. .. FINISH: DIR MODE BANK 0 */
/* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. DIRECTION_1 = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
/* .. .. .. .. FINISH: DIR MODE BANK 1 */
/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x0 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. */
EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
/* .. FINISH: ENABLING LEVEL SHIFTER */
- /* .. START: TPIU WIDTH IN CASE OF EMIO */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0XC5ACCE55 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. .. START: TRACE CURRENT PORT SIZE */
- /* .. .. a = 2 */
- /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U),
- /* .. .. FINISH: TRACE CURRENT PORT SIZE */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0X0 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */
/* .. START: FPGA RESETS TO 0 */
/* .. reserved_3 = 0 */
/* .. ==> 0XF8000240[31:25] = 0x00000000U */
/* .. .. FINISH: AFI2 REGISTERS */
/* .. .. START: AFI3 REGISTERS */
/* .. .. FINISH: AFI3 REGISTERS */
+ /* .. .. START: AFI2 SECURE REGISTER */
+ /* .. .. FINISH: AFI2 SECURE REGISTER */
/* .. FINISH: AFI REGISTERS */
/* .. START: LOCK IT BACK */
/* .. LOCK_KEY = 0X767B */
/* .. SRCSEL = 0x0 */
/* .. ==> 0XF8000154[5:4] = 0x00000000U */
/* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. DIVISOR = 0x14 */
- /* .. ==> 0XF8000154[13:8] = 0x00000014U */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
+ /* .. DIVISOR = 0xa */
+ /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
/* .. */
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
/* .. .. START: TRACE CLOCK */
/* .. .. FINISH: TRACE CLOCK */
/* .. .. CLKACT = 0x1 */
/* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
/* .. .. */
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
- /* .. .. SRCSEL = 0x3 */
- /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */
- /* .. .. DIVISOR0 = 0x6 */
- /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x7 */
+ /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
/* .. .. DIVISOR1 = 0x1 */
/* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
/* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
/* .. .. */
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U),
- /* .. .. SRCSEL = 0x2 */
- /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */
- /* .. .. DIVISOR0 = 0x35 */
- /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */
- /* .. .. DIVISOR1 = 0x2 */
- /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x5 */
+ /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
/* .. .. SRCSEL = 0x0 */
/* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
/* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR0 = 0xa */
- /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
+ /* .. .. DIVISOR0 = 0x14 */
+ /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
/* .. .. DIVISOR1 = 0x1 */
/* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
/* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
/* .. .. */
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U),
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
/* .. .. CLK_621_TRUE = 0x1 */
/* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
/* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
/* .. .. reg_ddrc_burst_rdwr = 0x4 */
/* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
/* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
- /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */
- /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */
- /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */
+ /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
+ /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
+ /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
/* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
/* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
/* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
/* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
/* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
/* .. .. */
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
/* .. .. reg_ddrc_force_low_pri_n = 0x0 */
/* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
/* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. FINISH: DDRIOB SETTINGS */
/* .. START: MIO PROGRAMMING */
/* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000700[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000700[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000700[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000700[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000700[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000700[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000700[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000700[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000700[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
/* .. ==> 0XF8000704[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. L0_SEL = 1 */
/* .. */
EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
/* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800071C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800071C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800071C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800071C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800071C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800071C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800071C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800071C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800071C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000720[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000720[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000720[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000720[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000720[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000720[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000720[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000720[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000720[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000724[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000724[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000724[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000724[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000724[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000724[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000724[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000724[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000724[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000728[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000728[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000728[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000728[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000728[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000728[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000728[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000728[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000728[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800072C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800072C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800072C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800072C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800072C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800072C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800072C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF800072C[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800072C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000730[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000730[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000730[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000730[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000730[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000730[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000730[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000730[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000730[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000734[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000734[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000734[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000734[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000734[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000734[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000734[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000734[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000734[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000738[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000738[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000738[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000738[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000738[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000738[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000738[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000738[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000738[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800073C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800073C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800073C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800073C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800073C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800073C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800073C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF800073C[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800073C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
/* .. ==> 0XF8000740[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. L0_SEL = 1 */
/* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
/* .. */
EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
/* .. TRI_ENABLE = 1 */
/* .. ==> 0XF80007BC[0:0] = 0x00000001U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
/* .. */
EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
/* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
+ /* .. TRI_ENABLE = 0 */
/* .. ==> 0XF80007D0[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. L0_SEL = 0 */
/* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
/* .. */
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
- /* .. CD = 0x3e */
- /* .. ==> 0XE0001018[15:0] = 0x0000003EU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */
+ /* .. CD = 0x7c */
+ /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
/* .. */
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
/* .. STPBRK = 0x0 */
/* .. ==> 0XE0001000[8:8] = 0x00000000U */
/* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
/* .. */
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
/* .. FINISH: UART REGISTERS */
- /* .. START: TPIU WIDTH IN CASE OF EMIO */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0XC5ACCE55 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. .. START: TRACE CURRENT PORT SIZE */
- /* .. .. a = 2 */
- /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U),
- /* .. .. FINISH: TRACE CURRENT PORT SIZE */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0X0 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */
/* .. START: QSPI REGISTERS */
/* .. Holdb_dr = 1 */
/* .. ==> 0XE000D000[19:19] = 0x00000001U */
/* .. .. .. .. START: DIR MODE BANK 0 */
/* .. .. .. .. FINISH: DIR MODE BANK 0 */
/* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. DIRECTION_1 = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
/* .. .. .. .. FINISH: DIR MODE BANK 1 */
/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x0 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. ==> 0XF8000900[3:2] = 0x00000003U */
/* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */
/* .. */
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
- /* .. FINISH: ENABLING LEVEL SHIFTER */
- /* .. START: TPIU WIDTH IN CASE OF EMIO */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0XC5ACCE55 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. .. START: TRACE CURRENT PORT SIZE */
- /* .. .. a = 2 */
- /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U),
- /* .. .. FINISH: TRACE CURRENT PORT SIZE */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0X0 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ /* .. FINISH: ENABLING LEVEL SHIFTER */
/* .. START: FPGA RESETS TO 0 */
/* .. reserved_3 = 0 */
/* .. ==> 0XF8000240[31:25] = 0x00000000U */
/* .. SRCSEL = 0x0 */
/* .. ==> 0XF8000154[5:4] = 0x00000000U */
/* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. DIVISOR = 0x14 */
- /* .. ==> 0XF8000154[13:8] = 0x00000014U */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
+ /* .. DIVISOR = 0xa */
+ /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
/* .. */
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
/* .. .. START: TRACE CLOCK */
/* .. .. FINISH: TRACE CLOCK */
/* .. .. CLKACT = 0x1 */
/* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
/* .. .. */
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
- /* .. .. SRCSEL = 0x3 */
- /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */
- /* .. .. DIVISOR0 = 0x6 */
- /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x7 */
+ /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
/* .. .. DIVISOR1 = 0x1 */
/* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
/* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
/* .. .. */
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U),
- /* .. .. SRCSEL = 0x2 */
- /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */
- /* .. .. DIVISOR0 = 0x35 */
- /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */
- /* .. .. DIVISOR1 = 0x2 */
- /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x5 */
+ /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
/* .. .. SRCSEL = 0x0 */
/* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
/* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR0 = 0xa */
- /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
+ /* .. .. DIVISOR0 = 0x14 */
+ /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
/* .. .. DIVISOR1 = 0x1 */
/* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
/* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
/* .. .. */
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U),
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
/* .. .. CLK_621_TRUE = 0x1 */
/* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
/* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
/* .. .. reg_ddrc_burst_rdwr = 0x4 */
/* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
/* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
- /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */
- /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */
- /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */
+ /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
+ /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
+ /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
/* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
/* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
/* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
/* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
/* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
/* .. .. */
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
/* .. .. reg_ddrc_force_low_pri_n = 0x0 */
/* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
/* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. FINISH: DDRIOB SETTINGS */
/* .. START: MIO PROGRAMMING */
/* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000700[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000700[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000700[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000700[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000700[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000700[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000700[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000700[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000700[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
/* .. ==> 0XF8000704[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. L0_SEL = 1 */
/* .. */
EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
/* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800071C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800071C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800071C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800071C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800071C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800071C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800071C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800071C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800071C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000720[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000720[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000720[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000720[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000720[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000720[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000720[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000720[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000720[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000724[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000724[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000724[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000724[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000724[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000724[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000724[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000724[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000724[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000728[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000728[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000728[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000728[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000728[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000728[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000728[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000728[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000728[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800072C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800072C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800072C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800072C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800072C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800072C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800072C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF800072C[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800072C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000730[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000730[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000730[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000730[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000730[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000730[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000730[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000730[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000730[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000734[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000734[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000734[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000734[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000734[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000734[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000734[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000734[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000734[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000738[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000738[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000738[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000738[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000738[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000738[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000738[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000738[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000738[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800073C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800073C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800073C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800073C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800073C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800073C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800073C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF800073C[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800073C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
/* .. ==> 0XF8000740[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. L0_SEL = 1 */
/* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
/* .. */
EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
/* .. TRI_ENABLE = 1 */
/* .. ==> 0XF80007BC[0:0] = 0x00000001U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
/* .. */
EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
/* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
+ /* .. TRI_ENABLE = 0 */
/* .. ==> 0XF80007D0[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. L0_SEL = 0 */
/* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
/* .. */
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
- /* .. CD = 0x3e */
- /* .. ==> 0XE0001018[15:0] = 0x0000003EU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */
+ /* .. CD = 0x7c */
+ /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
/* .. */
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
/* .. STPBRK = 0x0 */
/* .. ==> 0XE0001000[8:8] = 0x00000000U */
/* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
/* .. */
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
/* .. FINISH: UART REGISTERS */
- /* .. START: TPIU WIDTH IN CASE OF EMIO */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0XC5ACCE55 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. .. START: TRACE CURRENT PORT SIZE */
- /* .. .. a = 2 */
- /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U),
- /* .. .. FINISH: TRACE CURRENT PORT SIZE */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0X0 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */
/* .. START: QSPI REGISTERS */
/* .. Holdb_dr = 1 */
/* .. ==> 0XE000D000[19:19] = 0x00000001U */
/* .. .. .. .. START: DIR MODE BANK 0 */
/* .. .. .. .. FINISH: DIR MODE BANK 0 */
/* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. DIRECTION_1 = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
/* .. .. .. .. FINISH: DIR MODE BANK 1 */
/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x0 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. */
EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
/* .. FINISH: ENABLING LEVEL SHIFTER */
- /* .. START: TPIU WIDTH IN CASE OF EMIO */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0XC5ACCE55 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. .. START: TRACE CURRENT PORT SIZE */
- /* .. .. a = 2 */
- /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U),
- /* .. .. FINISH: TRACE CURRENT PORT SIZE */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0X0 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */
/* .. START: FPGA RESETS TO 0 */
/* .. reserved_3 = 0 */
/* .. ==> 0XF8000240[31:25] = 0x00000000U */
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
+#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 108333336
#define WDT_FREQ 108333336
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 175000000
-#define FPGA2_FREQ 12264151
-#define FPGA3_FREQ 100000000
+#define FPGA1_FREQ 142857132
+#define FPGA2_FREQ 200000000
+#define FPGA3_FREQ 50000000
+
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-XILINX_ZYNQMP_EP BOARD
+XILINX_ZYNQMP BOARDS
M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
F: board/xilinx/zynqmp/
-F: include/configs/xilinx_zynqmp.h
-F: include/configs/xilinx_zynqmp_ep.h
-F: configs/xilinx_zynqmp_ep_defconfig
+F: include/configs/xilinx_zynqmp*
+F: configs/xilinx_zynqmp*
#include <common.h>
#include <netdev.h>
+#include <sata.h>
#include <ahci.h>
#include <scsi.h>
#include <asm/arch/clk.h>
return 0;
}
+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+/*
+ * fdt_get_reg - Fill buffer by information from DT
+ */
+static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
+ const u32 *cell, int n)
+{
+ int i = 0, b, banks;
+ int parent_offset = fdt_parent_offset(fdt, nodeoffset);
+ int address_cells = fdt_address_cells(fdt, parent_offset);
+ int size_cells = fdt_size_cells(fdt, parent_offset);
+ char *p = buf;
+ phys_addr_t val;
+ phys_size_t vals;
+
+ debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
+ __func__, address_cells, size_cells, buf, cell);
+
+ /* Check memory bank setup */
+ banks = n % (address_cells + size_cells);
+ if (banks)
+ panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
+ n, address_cells, size_cells);
+
+ banks = n / (address_cells + size_cells);
+
+ for (b = 0; b < banks; b++) {
+ debug("%s: Bank #%d:\n", __func__, b);
+ if (address_cells == 2) {
+ val = cell[i + 1];
+ val <<= 32;
+ val |= cell[i];
+ val = fdt64_to_cpu(val);
+ debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
+ __func__, val, p, &cell[i]);
+ *(phys_addr_t *)p = val;
+ } else {
+ debug("%s: addr32=%x, ptr=%p\n",
+ __func__, fdt32_to_cpu(cell[i]), p);
+ *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
+ }
+ p += sizeof(phys_addr_t);
+ i += address_cells;
+
+ debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
+ sizeof(phys_addr_t));
+
+ if (size_cells == 2) {
+ vals = cell[i + 1];
+ vals <<= 32;
+ vals |= cell[i];
+ vals = fdt64_to_cpu(vals);
+
+ debug("%s: size64=%llx, ptr=%p, cell=%p\n",
+ __func__, vals, p, &cell[i]);
+ *(phys_size_t *)p = vals;
+ } else {
+ debug("%s: size32=%x, ptr=%p\n",
+ __func__, fdt32_to_cpu(cell[i]), p);
+ *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
+ }
+ p += sizeof(phys_size_t);
+ i += size_cells;
+
+ debug("%s: ps=%p, i=%x, size=%zu\n",
+ __func__, p, i, sizeof(phys_size_t));
+ }
+
+ /* Return the first address size */
+ return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
+}
+
+#define FDT_REG_SIZE sizeof(u32)
+/* Temp location for sharing data for storing */
+/* Up to 64-bit address + 64-bit size */
+static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
+
+void dram_init_banksize(void)
+{
+ int bank;
+
+ memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ debug("Bank #%d: start %llx\n", bank,
+ (unsigned long long)gd->bd->bi_dram[bank].start);
+ debug("Bank #%d: size %llx\n", bank,
+ (unsigned long long)gd->bd->bi_dram[bank].size);
+ }
+}
+
+int dram_init(void)
+{
+ int node, len;
+ const void *blob = gd->fdt_blob;
+ const u32 *cell;
+
+ memset(&tmp, 0, sizeof(tmp));
+
+ /* find or create "/memory" node. */
+ node = fdt_subnode_offset(blob, 0, "memory");
+ if (node < 0) {
+ printf("%s: Can't get memory node\n", __func__);
+ return node;
+ }
+
+ /* Get pointer to cells and lenght of it */
+ cell = fdt_getprop(blob, node, "reg", &len);
+ if (!cell) {
+ printf("%s: Can't get reg property\n", __func__);
+ return -1;
+ }
+
+ gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
+
+ debug("%s: Initial DRAM size %llx\n", __func__, gd->ram_size);
+
+ return 0;
+}
+#else
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
+#endif
void reset_cpu(ulong addr)
{
#ifdef CONFIG_SCSI_AHCI_PLAT
void scsi_init(void)
{
+#if defined(CONFIG_SATA_CEVA)
+ init_sata(0);
+#endif
ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
scsi_scan(1);
}
--- /dev/null
+if TARGET_ZIPITZ2
+
+config SYS_BOARD
+ default "zipitz2"
+
+config SYS_CONFIG_NAME
+ default "zipitz2"
+
+endif
--- /dev/null
+ZIPITZ2 BOARD
+M: Vasily Khoruzhick <anarsoul@gmail.com>
+S: Maintained
+F: board/zipitz2/
+F: include/configs/zipitz2.h
+F: configs/zipitz2_defconfig
--- /dev/null
+#
+# Copyright (C) 2009
+# Marek Vasut <marek.vasut@gmail.com>
+#
+# Heavily based on pxa255_idp platform
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := zipitz2.o
--- /dev/null
+/*
+ * Copyright (C) 2009
+ * Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Heavily based on pxa255_idp platform
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <serial.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pxa.h>
+#include <asm/arch/regs-mmc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_SPI
+void lcd_start(void);
+#else
+inline void lcd_start(void) {};
+#endif
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ /* arch number of Z2 */
+ gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* Enable LCD */
+ lcd_start();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ pxa2xx_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_CMD_USB
+int board_usb_init(int index, enum usb_init_type init)
+{
+ /* enable port 2 */
+ writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+ UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
+
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return 0;
+}
+
+void usb_board_stop(void)
+{
+}
+#endif
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ pxa_mmc_register(0);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_SPI
+
+struct {
+ unsigned char reg;
+ unsigned short data;
+ unsigned char mdelay;
+} lcd_data[] = {
+ { 0x07, 0x0000, 0 },
+ { 0x13, 0x0000, 10 },
+ { 0x11, 0x3004, 0 },
+ { 0x14, 0x200F, 0 },
+ { 0x10, 0x1a20, 0 },
+ { 0x13, 0x0040, 50 },
+ { 0x13, 0x0060, 0 },
+ { 0x13, 0x0070, 200 },
+ { 0x01, 0x0127, 0 },
+ { 0x02, 0x0700, 0 },
+ { 0x03, 0x1030, 0 },
+ { 0x08, 0x0208, 0 },
+ { 0x0B, 0x0620, 0 },
+ { 0x0C, 0x0110, 0 },
+ { 0x30, 0x0120, 0 },
+ { 0x31, 0x0127, 0 },
+ { 0x32, 0x0000, 0 },
+ { 0x33, 0x0503, 0 },
+ { 0x34, 0x0727, 0 },
+ { 0x35, 0x0124, 0 },
+ { 0x36, 0x0706, 0 },
+ { 0x37, 0x0701, 0 },
+ { 0x38, 0x0F00, 0 },
+ { 0x39, 0x0F00, 0 },
+ { 0x40, 0x0000, 0 },
+ { 0x41, 0x0000, 0 },
+ { 0x42, 0x013f, 0 },
+ { 0x43, 0x0000, 0 },
+ { 0x44, 0x013f, 0 },
+ { 0x45, 0x0000, 0 },
+ { 0x46, 0xef00, 0 },
+ { 0x47, 0x013f, 0 },
+ { 0x48, 0x0000, 0 },
+ { 0x07, 0x0015, 30 },
+ { 0x07, 0x0017, 0 },
+ { 0x20, 0x0000, 0 },
+ { 0x21, 0x0000, 0 },
+ { 0x22, 0x0000, 0 },
+};
+
+void zipitz2_spi_sda(int set)
+{
+ /* GPIO 13 */
+ if (set)
+ writel((1 << 13), GPSR0);
+ else
+ writel((1 << 13), GPCR0);
+}
+
+void zipitz2_spi_scl(int set)
+{
+ /* GPIO 22 */
+ if (set)
+ writel((1 << 22), GPCR0);
+ else
+ writel((1 << 22), GPSR0);
+}
+
+unsigned char zipitz2_spi_read(void)
+{
+ /* GPIO 40 */
+ return !!(readl(GPLR1) & (1 << 8));
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ /* Always valid */
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* GPIO 88 low */
+ writel((1 << 24), GPCR2);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* GPIO 88 high */
+ writel((1 << 24), GPSR2);
+}
+
+void lcd_start(void)
+{
+ int i;
+ unsigned char reg[3] = { 0x74, 0x00, 0 };
+ unsigned char data[3] = { 0x76, 0, 0 };
+ unsigned char dummy[3] = { 0, 0, 0 };
+
+ /* PWM2 AF */
+ writel(readl(GAFR0_L) | 0x00800000, GAFR0_L);
+ /* Enable clock to all PWM */
+ writel(readl(CKEN) | 0x3, CKEN);
+ /* Configure PWM2 */
+ writel(0x4f, PWM_CTRL2);
+ writel(0x2ff, PWM_PWDUTY2);
+ writel(792, PWM_PERVAL2);
+
+ /* Toggle the reset pin to reset the LCD */
+ writel((1 << 19), GPSR0);
+ udelay(100000);
+ writel((1 << 19), GPCR0);
+ udelay(20000);
+ writel((1 << 19), GPSR0);
+ udelay(20000);
+
+ /* Program the LCD init sequence */
+ for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) {
+ reg[0] = 0x74;
+ reg[1] = 0x0;
+ reg[2] = lcd_data[i].reg;
+ spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
+
+ data[0] = 0x76;
+ data[1] = lcd_data[i].data >> 8;
+ data[2] = lcd_data[i].data & 0xff;
+ spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
+
+ if (lcd_data[i].mdelay)
+ udelay(lcd_data[i].mdelay * 1000);
+ }
+
+ writel((1 << 11), GPSR0);
+}
+#endif
menu "Command line interface"
+config CMDLINE
+ bool "Support U-Boot commands"
+ default y
+ help
+ Enable U-Boot's command-line functions. This provides a means
+ to enter commands into U-Boot for a wide variety of purposes. It
+ also allows scripts (containing commands) to be executed.
+ Various commands and command categorys can be indivdually enabled.
+ Depending on the number of commands enabled, this can add
+ substantially to the size of U-Boot.
+
config HUSH_PARSER
bool "Use hush shell"
select SYS_HUSH_PARSER
+ depends on CMDLINE
help
This option enables the "hush" shell (from Busybox) as command line
interpreter, thus enabling powerful command line syntax like
help
Show AMBA Plug-n-Play information on startup.
+config CMD_BLOCK_CACHE
+ bool "blkcache - control and stats for block cache"
+ depends on BLOCK_CACHE
+ default y if BLOCK_CACHE
+ help
+ Enable the blkcache command, which can be used to control the
+ operation of the cache functions.
+ This is most useful when fine-tuning the operation of the cache
+ during development, but also allows the cache to be disabled when
+ it might hurt performance (e.g. when using the ums command).
+
config CMD_TIME
bool "time"
help
obj-$(CONFIG_CMD_SOURCE) += source.o
obj-$(CONFIG_CMD_BDI) += bdinfo.o
obj-$(CONFIG_CMD_BEDBUG) += bedbug.o
+obj-$(CONFIG_CMD_BLOCK_CACHE) += blkcache.o
obj-$(CONFIG_CMD_BMP) += bmp.o
obj-$(CONFIG_CMD_BOOTEFI) += bootefi.o
obj-$(CONFIG_CMD_BOOTMENU) += bootmenu.o
--- /dev/null
+/*
+ * Copyright (C) Nelson Integration, LLC 2016
+ * Author: Eric Nelson<eric@nelint.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <part.h>
+
+static int blkc_show(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ struct block_cache_stats stats;
+ blkcache_stats(&stats);
+
+ printf("hits: %u\n"
+ "misses: %u\n"
+ "entries: %u\n"
+ "max blocks/entry: %u\n"
+ "max cache entries: %u\n",
+ stats.hits, stats.misses, stats.entries,
+ stats.max_blocks_per_entry, stats.max_entries);
+ return 0;
+}
+
+static int blkc_configure(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ unsigned blocks_per_entry, max_entries;
+ if (argc != 3)
+ return CMD_RET_USAGE;
+
+ blocks_per_entry = simple_strtoul(argv[1], 0, 0);
+ max_entries = simple_strtoul(argv[2], 0, 0);
+ blkcache_configure(blocks_per_entry, max_entries);
+ printf("changed to max of %u entries of %u blocks each\n",
+ max_entries, blocks_per_entry);
+ return 0;
+}
+
+static cmd_tbl_t cmd_blkc_sub[] = {
+ U_BOOT_CMD_MKENT(show, 0, 0, blkc_show, "", ""),
+ U_BOOT_CMD_MKENT(configure, 3, 0, blkc_configure, "", ""),
+};
+
+static __maybe_unused void blkc_reloc(void)
+{
+ static int relocated;
+
+ if (!relocated) {
+ fixup_cmdtable(cmd_blkc_sub, ARRAY_SIZE(cmd_blkc_sub));
+ relocated = 1;
+ };
+}
+
+static int do_blkcache(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ cmd_tbl_t *c;
+
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+ blkc_reloc();
+#endif
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ /* Strip off leading argument */
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], &cmd_blkc_sub[0], ARRAY_SIZE(cmd_blkc_sub));
+
+ if (!c)
+ return CMD_RET_USAGE;
+
+ return c->cmd(cmdtp, flag, argc, argv);
+}
+
+U_BOOT_CMD(
+ blkcache, 4, 0, do_blkcache,
+ "block cache diagnostics and control",
+ "show - show and reset statistics\n"
+ "blkcache configure blocks entries\n"
+);
#ifdef CONFIG_PARTITIONS
efi_disk_register();
#endif
+#ifdef CONFIG_LCD
+ efi_gop_register();
+#endif
/* Call our payload! */
#ifdef DEBUG_EFI
* correct location and then move the image there.
*/
dst = gd->bd->bi_dram[0].start + le32_to_cpu(ih->text_offset);
+
+ unmap_sysmem(ih);
+
if (images->ep != dst) {
void *src;
lmb_reserve(&images->lmb, images->ep, le32_to_cpu(ih->image_size));
+ unmap_sysmem(ih);
+
/*
* Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not
* have a header that provide this informaiton.
#include <command.h>
#include <cbfs.h>
-int do_cbfs_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+static int do_cbfs_init(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
{
uintptr_t end_of_rom = 0xffffffff;
char *ep;
" CBFS is in. It defaults to 0xFFFFFFFF\n"
);
-int do_cbfs_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+static int do_cbfs_fsload(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
{
const struct cbfs_cachenode *file;
unsigned long offset;
" - load binary file 'filename' from the cbfs to address 'addr'\n"
);
-int do_cbfs_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+static int do_cbfs_ls(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
{
const struct cbfs_cachenode *file = file_cbfs_get_first();
int files = 0;
" - list the files in the cbfs\n"
);
-int do_cbfs_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+static int do_cbfs_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
{
const struct cbfs_header *header = file_cbfs_get_header();
break;
}
if((c&0xC0)==0x80) { /* output */
- PRINTF("Transfer error transfered: at %ld, MSR=%02X\n",i,c);
+ PRINTF("Transfer error transferred: at %ld, MSR=%02X\n",i,c);
if(i>6) {
for(ii=0;ii<7;ii++) {
pCMD->result[ii]=bufferw[(i-7+ii)];
static int do_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
+#ifdef CONFIG_CMDLINE
cmd_tbl_t *start = ll_entry_start(cmd_tbl_t, cmd);
const int len = ll_entry_count(cmd_tbl_t, cmd);
return _do_help(start, len, cmdtp, flag, argc, argv);
+#else
+ return 0;
+#endif
}
U_BOOT_CMD(
#include <common.h>
-/* COPYING is currently 15951 bytes in size */
+/* Licenses/gpl-2.0.txt is currently 18092 bytes in size */
#define LICENSE_MAX 20480
#include <command.h>
int do_license(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- char *tok, *dst = malloc(LICENSE_MAX);
+ char *dst = malloc(LICENSE_MAX);
unsigned long len = LICENSE_MAX;
if (!dst)
return -1;
- if (gunzip(dst, LICENSE_MAX, license_gz, &len) != 0) {
+ if (gunzip(dst, LICENSE_MAX, license_gzip, &len) != 0) {
printf("Error uncompressing license text\n");
free(dst);
return -1;
printf("no mmc device at slot %x\n", dev);
return NULL;
}
+
if (force_init)
mmc->has_init = 0;
if (mmc_init(mmc))
printf("\nMMC read: dev # %d, block # %d, count %d ... ",
curr_device, blk, cnt);
- n = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, addr);
+ n = blk_dread(&mmc->block_dev, blk, cnt, addr);
/* flush cache after read */
flush_cache((ulong)addr, cnt * 512); /* FIXME */
printf("%d blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR");
printf("Error: card is write protected!\n");
return CMD_RET_FAILURE;
}
- n = mmc->block_dev.block_write(&mmc->block_dev, blk, cnt, addr);
+ n = blk_dwrite(&mmc->block_dev, blk, cnt, addr);
printf("%d blocks written: %s\n", n, (n == cnt) ? "OK" : "ERROR");
return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
printf("Error: card is write protected!\n");
return CMD_RET_FAILURE;
}
- n = mmc->block_dev.block_erase(&mmc->block_dev, blk, cnt);
+ n = blk_derase(&mmc->block_dev, blk, cnt);
printf("%d blocks erased: %s\n", n, (n == cnt) ? "OK" : "ERROR");
return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
printf("\nSATA read: device %d block # %ld, count %ld ... ",
sata_curr_device, blk, cnt);
- n = sata_read(sata_curr_device, blk, cnt, (u32 *)addr);
+ n = blk_dread(&sata_dev_desc[sata_curr_device],
+ blk, cnt, (u32 *)addr);
/* flush cache after read */
flush_cache(addr, cnt * sata_dev_desc[sata_curr_device].blksz);
printf("\nSATA write: device %d block # %ld, count %ld ... ",
sata_curr_device, blk, cnt);
- n = sata_write(sata_curr_device, blk, cnt, (u32 *)addr);
+ n = blk_dwrite(&sata_dev_desc[sata_curr_device],
+ blk, cnt, (u32 *)addr);
printf("%ld blocks written: %s\n",
n, (n == cnt) ? "OK" : "ERROR");
snprintf(name, sizeof(name), "generic_%d:%d", bus, cs);
str = strdup(name);
+ if (!str)
+ return -ENOMEM;
ret = spi_get_bus_and_cs(bus, cs, 1000000, mode, "spi_generic_drv",
str, &dev, &slave);
if (ret)
#include <command.h>
#include <console.h>
#include <dm.h>
+#include <dm/uclass-internal.h>
#include <memalign.h>
#include <asm/byteorder.h>
#include <asm/unaligned.h>
#ifdef CONFIG_DM_USB
struct udevice *bus;
- for (uclass_first_device(UCLASS_USB, &bus);
+ for (uclass_find_first_device(UCLASS_USB, &bus);
bus;
- uclass_next_device(&bus)) {
+ uclass_find_next_device(&bus)) {
struct usb_device *udev;
struct udevice *dev;
+ if (!device_active(bus))
+ continue;
+
device_find_first_child(bus, &dev);
if (dev && device_active(dev)) {
udev = dev_get_parent_priv(dev);
static int do_usb_stop_keyboard(int force)
{
-#ifdef CONFIG_USB_KEYBOARD
+#if !defined CONFIG_DM_USB && defined CONFIG_USB_KEYBOARD
if (usb_kbd_deregister(force) != 0) {
printf("USB not stopped: usbkbd still using USB\n");
return 1;
endif
# We always have this since drivers/ddr/fs/interactive.c needs it
-obj-y += cli_simple.o
+obj-$(CONFIG_CMDLINE) += cli_simple.o
obj-y += cli.o
-obj-y += cli_readline.o
+obj-$(CONFIG_CMDLINE) += cli_readline.o
obj-y += command.o
obj-y += s_record.o
obj-y += xyzModem.o
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_CMDLINE
/*
* Run a command using the selected parser.
*
return 0;
#endif
}
+#endif /* CONFIG_CMDLINE */
int run_command_list(const char *cmd, int len, int flag)
{
* doing a malloc() which is actually required only in a case that
* is pretty rare.
*/
+#ifdef CONFIG_CMDLINE
rcode = cli_simple_run_command_list(buff, flag);
+#else
+ rcode = board_run_command(buff);
+#endif
#endif
if (need_buff)
free(buff);
*/
void cli_secure_boot_cmd(const char *cmd)
{
+#ifdef CONFIG_CMDLINE
cmd_tbl_t *cmdtp;
+#endif
int rc;
if (!cmd) {
disable_ctrlc(1);
/* Find the command directly. */
+#ifdef CONFIG_CMDLINE
cmdtp = find_cmd(cmd);
if (!cmdtp) {
printf("## Error: \"%s\" not defined\n", cmd);
/* Run the command, forcing no flags and faking argc and argv. */
rc = (cmdtp->cmd)(cmdtp, 0, 1, (char **)&cmd);
+#else
+ rc = board_run_command(cmd);
+#endif
+
/* Shouldn't ever return from boot command. */
printf("## Error: \"%s\" returned (code %d)\n", cmd, rc);
parse_file_outer();
/* This point is never reached */
for (;;);
-#else
+#elif defined(CONFIG_CMDLINE)
cli_simple_loop();
+#else
+ printf("## U-Boot command line is disabled. Please enable CONFIG_CMDLINE\n");
#endif /*CONFIG_SYS_HUSH_PARSER*/
}
/* find command table entry for a command */
cmd_tbl_t *find_cmd_tbl(const char *cmd, cmd_tbl_t *table, int table_len)
{
+#ifdef CONFIG_CMDLINE
cmd_tbl_t *cmdtp;
cmd_tbl_t *cmdtp_temp = table; /* Init value */
const char *p;
if (n_found == 1) { /* exactly one match */
return cmdtp_temp;
}
+#endif /* CONFIG_CMDLINE */
return NULL; /* not found or ambiguous command */
}
static int complete_cmdv(int argc, char * const argv[], char last_char, int maxv, char *cmdv[])
{
+#ifdef CONFIG_CMDLINE
cmd_tbl_t *cmdtp = ll_entry_start(cmd_tbl_t, cmd);
const int count = ll_entry_count(cmd_tbl_t, cmd);
const cmd_tbl_t *cmdend = cmdtp + count;
cmdv[n_found] = NULL;
return n_found;
+#else
+ return 0;
+#endif
}
static int make_argv(char *s, int argvsz, char *argv[])
int ch = *s++;
printch(ch);
- if (ch == '\n')
- printch('\r');
}
return;
}
gd->env_valid = 1;
}
- if (gd->env_valid == 2)
- gd->env_addr = off_env[1] + offsetof(env_t, data);
- else if (gd->env_valid == 1)
- gd->env_addr = off_env[0] + offsetof(env_t, data);
-
#else /* CONFIG_ENV_OFFSET_REDUND */
ulong crc, len, new;
uchar rdbuf[64];
}
if (crc == new) {
- gd->env_addr = offsetof(env_t, data);
gd->env_valid = 1;
} else {
- gd->env_addr = 0;
gd->env_valid = 0;
}
#endif /* CONFIG_ENV_OFFSET_REDUND */
ret = env_import((char *)ep, 0);
if (!ret) {
error("Cannot import environment: errno = %d\n", errno);
- set_default_env("env_import failed");
+ set_default_env("!env_import failed");
}
err_read:
sparse_storage_t *storage,
sparse_header_t *sparse)
{
- return size * sparse->blk_sz / storage->block_sz;
+ return (unsigned int)lldiv((uint64_t)size * sparse->blk_sz,
+ storage->block_sz);
}
static bool sparse_chunk_has_buffer(chunk_header_t *chunk)
sparse_buffer_t *buffer;
uint32_t start;
uint32_t total_blocks = 0;
- uint32_t skipped = 0;
int i;
debug("=== Storage ===\n");
* and go on parsing the rest of the chunks
*/
if (chunk_header->chunk_type == CHUNK_TYPE_DONT_CARE) {
- skipped += sparse_block_size_to_storage(chunk_header->chunk_sz,
- storage,
- sparse_header);
+ blkcnt = sparse_block_size_to_storage(chunk_header->chunk_sz,
+ storage,
+ sparse_header);
+#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
+ total_blocks += blkcnt;
+#endif
continue;
}
sparse_put_data_buffer(buffer);
}
- debug("Wrote %d blocks, skipped %d, expected to write %d blocks\n",
- total_blocks, skipped,
+ debug("Wrote %d blocks, expected to write %d blocks\n",
+ total_blocks,
sparse_block_size_to_storage(sparse_header->total_blks,
storage, sparse_header));
printf("........ wrote %d blocks to '%s'\n", total_blocks,
storage->name);
- if ((total_blocks + skipped) !=
+ if (total_blocks !=
sparse_block_size_to_storage(sparse_header->total_blks,
storage, sparse_header)) {
printf("sparse image write failure\n");
int line_length;
if (lcd_flush_dcache)
- flush_dcache_range((u32)lcd_base,
- (u32)(lcd_base + lcd_get_size(&line_length)));
+ flush_dcache_range((ulong)lcd_base,
+ (ulong)(lcd_base + lcd_get_size(&line_length)));
#endif
}
autoboot_command(s);
cli_loop();
+ panic("No CLI available");
}
* make it obvious what the key for each entry is.
*
* item_choice - If not NULL, will be called when asking the user to choose an
- * item. Returns a key string corresponding to the choosen item or NULL if
+ * item. Returns a key string corresponding to the chosen item or NULL if
* no item has been selected.
*
* item_choice_data - Will be passed as the argument to the item_choice function
{ BOOT_DEVICE_RAM, "RAM" },
#endif
#ifdef CONFIG_SPL_MMC_SUPPORT
- { BOOT_DEVICE_MMC1, "MMC" },
- { BOOT_DEVICE_MMC2, "MMC" },
- { BOOT_DEVICE_MMC2_2, "MMC" },
+ { BOOT_DEVICE_MMC1, "MMC1" },
+ { BOOT_DEVICE_MMC2, "MMC2" },
+ { BOOT_DEVICE_MMC2_2, "MMC2_2" },
#endif
#ifdef CONFIG_SPL_NAND_SUPPORT
{ BOOT_DEVICE_NAND, "NAND" },
return 0;
}
-#ifdef CONFIG_SPL_LOAD_FIT
static ulong h_spl_load_read(struct spl_load_info *load, ulong sector,
ulong count, void *buf)
{
return mmc->block_dev.block_read(&mmc->block_dev, sector, count, buf);
}
-#endif
static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
{
goto end;
}
- switch (image_get_magic(header)) {
- case IH_MAGIC:
- ret = mmc_load_legacy(mmc, sector, header);
- break;
-#ifdef CONFIG_SPL_LOAD_FIT
- case FDT_MAGIC: {
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+ image_get_magic(header) == FDT_MAGIC) {
struct spl_load_info load;
debug("Found FIT\n");
load.bl_len = mmc->read_bl_len;
load.read = h_spl_load_read;
ret = spl_load_simple_fit(&load, sector, header);
- break;
- }
-#endif
- default:
- puts("bad magic\n");
- return -1;
+ } else {
+ ret = mmc_load_legacy(mmc, sector, header);
}
end:
static int mmc_load_image_raw_os(struct mmc *mmc)
{
unsigned long count;
+ int ret;
count = mmc->block_dev.block_read(&mmc->block_dev,
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
return -1;
}
- return mmc_load_image_raw_sector(mmc,
+ ret = mmc_load_image_raw_sector(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR);
+ if (ret)
+ return ret;
+
+ if (spl_image.os != IH_OS_LINUX) {
+ puts("Expected Linux image is not found. Trying to start U-boot\n");
+ return -ENOENT;
+ }
+
+ return 0;
}
#else
int spl_start_uboot(void)
int *src __attribute__((unused));
int *dst __attribute__((unused));
+#ifdef CONFIG_SPL_NAND_SOFTECC
+ debug("spl: nand - using sw ecc\n");
+#else
debug("spl: nand - using hw ecc\n");
+#endif
nand_init();
/*use CONFIG_SYS_TEXT_BASE as temporary storage area */
* clear keyboards LEDs). For data transfers, (storage transfers) we don't
* allow control messages with 0 timeout, by previousely resetting the flag
* asynch_allowed (usb_disable_asynch(1)).
- * returns the transfered length if OK or -1 if error. The transfered length
+ * returns the transferred length if OK or -1 if error. The transferred length
* and the current status are stored in the dev->act_len and dev->status.
*/
int usb_control_msg(struct usb_device *dev, unsigned int pipe,
static int usb_hub_port_reset(struct usb_device *dev, struct usb_device *hub)
{
- if (hub) {
- unsigned short portstatus;
- int err;
-
- /* reset the port for the second time */
- err = legacy_hub_port_reset(hub, dev->portnr - 1, &portstatus);
- if (err < 0) {
- printf("\n Couldn't reset port %i\n", dev->portnr);
- return err;
- }
- } else {
+ if (!hub)
usb_reset_root_port(dev);
- }
return 0;
}
#include <asm/processor.h>
#include <asm/unaligned.h>
#include <linux/ctype.h>
+#include <linux/list.h>
#include <asm/byteorder.h>
#ifdef CONFIG_SANDBOX
#include <asm/state.h>
#define USB_BUFSIZ 512
+#define HUB_SHORT_RESET_TIME 20
+#define HUB_LONG_RESET_TIME 200
+
+#define PORT_OVERCURRENT_MAX_SCAN_COUNT 3
+
+struct usb_device_scan {
+ struct usb_device *dev; /* USB hub device to scan */
+ struct usb_hub_device *hub; /* USB hub struct */
+ int port; /* USB port to scan */
+ struct list_head list;
+};
+
/* TODO(sjg@chromium.org): Remove this when CONFIG_DM_USB is defined */
static struct usb_hub_device hub_dev[USB_MAX_HUB];
static int usb_hub_index;
+static LIST_HEAD(usb_scan_list);
__weak void usb_hub_reset_devices(int port)
{
debug("port %d returns %lX\n", i + 1, dev->status);
}
+#ifdef CONFIG_SANDBOX
+ /*
+ * Don't set timeout / delay values here. This results
+ * in these values still being reset to 0.
+ */
+ if (state_get_skip_delays())
+ return;
+#endif
+
/*
* Wait for power to become stable,
* plus spec-defined max time for device to connect
pgood_delay = max(pgood_delay,
(unsigned)simple_strtol(env, NULL, 0));
debug("pgood_delay=%dms\n", pgood_delay);
- mdelay(pgood_delay + 1000);
+
+ /*
+ * Do a minimum delay of the larger value of 100ms or pgood_delay
+ * so that the power can stablize before the devices are queried
+ */
+ hub->query_delay = get_timer(0) + max(100, (int)pgood_delay);
+
+ /*
+ * Record the power-on timeout here. The max. delay (timeout)
+ * will be done based on this value in the USB port loop in
+ * usb_hub_configure() later.
+ */
+ hub->connect_timeout = hub->query_delay + 1000;
+ debug("devnum=%d poweron: query_delay=%d connect_timeout=%d\n",
+ dev->devnum, max(100, (int)pgood_delay),
+ max(100, (int)pgood_delay) + 1000);
}
void usb_hub_reset(void)
{
usb_hub_index = 0;
+
+ /* Zero out global hub_dev in case its re-used again */
+ memset(hub_dev, 0, sizeof(hub_dev));
}
static struct usb_hub_device *usb_hub_allocate(void)
int err, tries;
ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
unsigned short portstatus, portchange;
+ int delay = HUB_SHORT_RESET_TIME; /* start with short reset delay */
#ifdef CONFIG_DM_USB
debug("%s: resetting '%s' port %d...\n", __func__, dev->dev->name,
if (err < 0)
return err;
- mdelay(200);
+ mdelay(delay);
if (usb_get_port_status(dev, port + 1, portsts) < 0) {
debug("get_port_status failed status %lX\n",
if (portstatus & USB_PORT_STAT_ENABLE)
break;
- mdelay(200);
+ /* Switch to long reset delay for the next round */
+ delay = HUB_LONG_RESET_TIME;
}
if (tries == MAX_TRIES) {
if (!(portstatus & USB_PORT_STAT_CONNECTION))
return -ENOTCONN;
}
- mdelay(200);
/* Reset the port */
ret = legacy_hub_port_reset(dev, port, &portstatus);
return ret;
}
- mdelay(200);
-
switch (portstatus & USB_PORT_STAT_SPEED_MASK) {
case USB_PORT_STAT_SUPER_SPEED:
speed = USB_SPEED_SUPER;
return ret;
}
+static int usb_scan_port(struct usb_device_scan *usb_scan)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
+ unsigned short portstatus;
+ unsigned short portchange;
+ struct usb_device *dev;
+ struct usb_hub_device *hub;
+ int ret = 0;
+ int i;
+
+ dev = usb_scan->dev;
+ hub = usb_scan->hub;
+ i = usb_scan->port;
+
+ /*
+ * Don't talk to the device before the query delay is expired.
+ * This is needed for voltages to stabalize.
+ */
+ if (get_timer(0) < hub->query_delay)
+ return 0;
+
+ ret = usb_get_port_status(dev, i + 1, portsts);
+ if (ret < 0) {
+ debug("get_port_status failed\n");
+ if (get_timer(0) >= hub->connect_timeout) {
+ debug("devnum=%d port=%d: timeout\n",
+ dev->devnum, i + 1);
+ /* Remove this device from scanning list */
+ list_del(&usb_scan->list);
+ free(usb_scan);
+ return 0;
+ }
+ }
+
+ portstatus = le16_to_cpu(portsts->wPortStatus);
+ portchange = le16_to_cpu(portsts->wPortChange);
+ debug("Port %d Status %X Change %X\n", i + 1, portstatus, portchange);
+
+ /* No connection change happened, wait a bit more. */
+ if (!(portchange & USB_PORT_STAT_C_CONNECTION)) {
+ if (get_timer(0) >= hub->connect_timeout) {
+ debug("devnum=%d port=%d: timeout\n",
+ dev->devnum, i + 1);
+ /* Remove this device from scanning list */
+ list_del(&usb_scan->list);
+ free(usb_scan);
+ return 0;
+ }
+ return 0;
+ }
+
+ /* Test if the connection came up, and if not exit */
+ if (!(portstatus & USB_PORT_STAT_CONNECTION))
+ return 0;
+
+ /* A new USB device is ready at this point */
+ debug("devnum=%d port=%d: USB dev found\n", dev->devnum, i + 1);
+
+ usb_hub_port_connect_change(dev, i);
+
+ if (portchange & USB_PORT_STAT_C_ENABLE) {
+ debug("port %d enable change, status %x\n", i + 1, portstatus);
+ usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_C_ENABLE);
+ /*
+ * The following hack causes a ghost device problem
+ * to Faraday EHCI
+ */
+#ifndef CONFIG_USB_EHCI_FARADAY
+ /*
+ * EM interference sometimes causes bad shielded USB
+ * devices to be shutdown by the hub, this hack enables
+ * them again. Works at least with mouse driver
+ */
+ if (!(portstatus & USB_PORT_STAT_ENABLE) &&
+ (portstatus & USB_PORT_STAT_CONNECTION) &&
+ usb_device_has_child_on_port(dev, i)) {
+ debug("already running port %i disabled by hub (EMI?), re-enabling...\n",
+ i + 1);
+ usb_hub_port_connect_change(dev, i);
+ }
+#endif
+ }
+
+ if (portstatus & USB_PORT_STAT_SUSPEND) {
+ debug("port %d suspend change\n", i + 1);
+ usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_SUSPEND);
+ }
+
+ if (portchange & USB_PORT_STAT_C_OVERCURRENT) {
+ debug("port %d over-current change\n", i + 1);
+ usb_clear_port_feature(dev, i + 1,
+ USB_PORT_FEAT_C_OVER_CURRENT);
+ /* Only power-on this one port */
+ usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER);
+ hub->overcurrent_count[i]++;
+
+ /*
+ * If the max-scan-count is not reached, return without removing
+ * the device from scan-list. This will re-issue a new scan.
+ */
+ if (hub->overcurrent_count[i] <=
+ PORT_OVERCURRENT_MAX_SCAN_COUNT)
+ return 0;
+
+ /* Otherwise the device will get removed */
+ printf("Port %d over-current occured %d times\n", i + 1,
+ hub->overcurrent_count[i]);
+ }
+
+ if (portchange & USB_PORT_STAT_C_RESET) {
+ debug("port %d reset change\n", i + 1);
+ usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_C_RESET);
+ }
+
+ /*
+ * We're done with this device, so let's remove this device from
+ * scanning list
+ */
+ list_del(&usb_scan->list);
+ free(usb_scan);
+
+ return 0;
+}
+
+static int usb_device_list_scan(void)
+{
+ struct usb_device_scan *usb_scan;
+ struct usb_device_scan *tmp;
+ static int running;
+ int ret = 0;
+
+ /* Only run this loop once for each controller */
+ if (running)
+ return 0;
+
+ running = 1;
+
+ while (1) {
+ /* We're done, once the list is empty again */
+ if (list_empty(&usb_scan_list))
+ goto out;
+
+ list_for_each_entry_safe(usb_scan, tmp, &usb_scan_list, list) {
+ int ret;
+
+ /* Scan this port */
+ ret = usb_scan_port(usb_scan);
+ if (ret)
+ goto out;
+ }
+ }
+
+out:
+ /*
+ * This USB controller has finished scanning all its connected
+ * USB devices. Set "running" back to 0, so that other USB controllers
+ * will scan their devices too.
+ */
+ running = 0;
+
+ return ret;
+}
static int usb_hub_configure(struct usb_device *dev)
{
for (i = 0; i < dev->maxchild; i++)
usb_hub_reset_devices(i + 1);
+ /*
+ * Only add the connected USB devices, including potential hubs,
+ * to a scanning list. This list will get scanned and devices that
+ * are detected (either via port connected or via port timeout)
+ * will get removed from this list. Scanning of the devices on this
+ * list will continue until all devices are removed.
+ */
for (i = 0; i < dev->maxchild; i++) {
- ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
- unsigned short portstatus, portchange;
- int ret;
- ulong start = get_timer(0);
- uint delay = CONFIG_SYS_HZ;
-
-#ifdef CONFIG_SANDBOX
- if (state_get_skip_delays())
- delay = 0;
-#endif
-#ifdef CONFIG_DM_USB
- debug("\n\nScanning '%s' port %d\n", dev->dev->name, i + 1);
-#else
- debug("\n\nScanning port %d\n", i + 1);
-#endif
- /*
- * Wait for (whichever finishes first)
- * - A maximum of 10 seconds
- * This is a purely observational value driven by connecting
- * a few broken pen drives and taking the max * 1.5 approach
- * - connection_change and connection state to report same
- * state
- */
- do {
- ret = usb_get_port_status(dev, i + 1, portsts);
- if (ret < 0) {
- debug("get_port_status failed\n");
- break;
- }
-
- portstatus = le16_to_cpu(portsts->wPortStatus);
- portchange = le16_to_cpu(portsts->wPortChange);
-
- /* No connection change happened, wait a bit more. */
- if (!(portchange & USB_PORT_STAT_C_CONNECTION))
- continue;
-
- /* Test if the connection came up, and if so, exit. */
- if (portstatus & USB_PORT_STAT_CONNECTION)
- break;
-
- } while (get_timer(start) < delay);
-
- if (ret < 0)
- continue;
+ struct usb_device_scan *usb_scan;
- debug("Port %d Status %X Change %X\n",
- i + 1, portstatus, portchange);
-
- if (portchange & USB_PORT_STAT_C_CONNECTION) {
- debug("port %d connection change\n", i + 1);
- usb_hub_port_connect_change(dev, i);
- }
- if (portchange & USB_PORT_STAT_C_ENABLE) {
- debug("port %d enable change, status %x\n",
- i + 1, portstatus);
- usb_clear_port_feature(dev, i + 1,
- USB_PORT_FEAT_C_ENABLE);
- /*
- * The following hack causes a ghost device problem
- * to Faraday EHCI
- */
-#ifndef CONFIG_USB_EHCI_FARADAY
- /* EM interference sometimes causes bad shielded USB
- * devices to be shutdown by the hub, this hack enables
- * them again. Works at least with mouse driver */
- if (!(portstatus & USB_PORT_STAT_ENABLE) &&
- (portstatus & USB_PORT_STAT_CONNECTION) &&
- usb_device_has_child_on_port(dev, i)) {
- debug("already running port %i " \
- "disabled by hub (EMI?), " \
- "re-enabling...\n", i + 1);
- usb_hub_port_connect_change(dev, i);
- }
-#endif
- }
- if (portstatus & USB_PORT_STAT_SUSPEND) {
- debug("port %d suspend change\n", i + 1);
- usb_clear_port_feature(dev, i + 1,
- USB_PORT_FEAT_SUSPEND);
- }
-
- if (portchange & USB_PORT_STAT_C_OVERCURRENT) {
- debug("port %d over-current change\n", i + 1);
- usb_clear_port_feature(dev, i + 1,
- USB_PORT_FEAT_C_OVER_CURRENT);
- usb_hub_power_on(hub);
+ usb_scan = calloc(1, sizeof(*usb_scan));
+ if (!usb_scan) {
+ printf("Can't allocate memory for USB device!\n");
+ return -ENOMEM;
}
+ usb_scan->dev = dev;
+ usb_scan->hub = hub;
+ usb_scan->port = i;
+ list_add_tail(&usb_scan->list, &usb_scan_list);
+ }
- if (portchange & USB_PORT_STAT_C_RESET) {
- debug("port %d reset change\n", i + 1);
- usb_clear_port_feature(dev, i + 1,
- USB_PORT_FEAT_C_RESET);
- }
- } /* end for i all ports */
+ /*
+ * And now call the scanning code which loops over the generated list
+ */
+ ret = usb_device_list_scan();
- return 0;
+ return ret;
}
static int usb_hub_check(struct usb_device *dev, int ifnum)
/* No USB Keyboard found */
return -1;
}
-#endif
/* Deregister the keyboard. */
int usb_kbd_deregister(int force)
#endif
}
+#endif
+
#ifdef CONFIG_DM_USB
static int usb_kbd_probe(struct udevice *dev)
return 1;
}
- return 1;
+ return 0;
}
static unsigned int usb_get_max_lun(struct us_data *us)
us->ip_wanted = 0;
return USB_STOR_TRANSPORT_ERROR;
}
- debug("Got interrupt data 0x%x, transfered %d status 0x%lX\n",
+ debug("Got interrupt data 0x%x, transferred %d status 0x%lX\n",
us->ip_data, us->pusb_dev->irq_act_len,
us->pusb_dev->irq_status);
/* UFI gives us ASC and ASCQ, like a request sense */
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_AXP152_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_SUNXI_NO_PMIC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t003"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_AXP152_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_AXP152_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_NETCONSOLE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_NETCONSOLE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO4_VOLT=2500
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
# CONFIG_MMC is not set
CONFIG_USB0_VBUS_PIN="PB10"
+CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_GPIO=y
-CONFIG_AXP_DCDC2_VOLT=1300
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_AXP_ALDO4_VOLT=3300
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_SPI_CS="PA0"
CONFIG_VIDEO_LCD_SPI_SCLK="PA1"
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A83T=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=15355
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+CONFIG_I2C0_ENABLE=y
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_USB0_ID_DET="PH11"
+CONFIG_USB1_VBUS_PIN="PD29"
+CONFIG_USB2_VBUS_PIN="PL6"
+CONFIG_AXP_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_AXP_DLDO3_VOLT=2500
+CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_AXP_FLDO1_VOLT=1200
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-d709"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_MUSB_HOST=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=480
+CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-itead-ibox"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
+#CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,SATAPWR=SUNXI_GPB(3)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3-nano"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_EHCI_HCD=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_RTL8139=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PHYS_64BIT"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_RTL8139=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_RTL8139=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-primo81"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_SSD2828_TX_CLK=27
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_SUNXI_NO_PMIC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_DCDC1_VOLT=3300
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_DCDC1_VOLT=3300
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,STATUSLED=234"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_DCDC1_VOLT=3300
CONFIG_AXP_ALDO1_VOLT=3300
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=251
+CONFIG_MMC0_CD_PIN="PA4"
+CONFIG_MMC3_PINS="PC"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_USB1_VBUS_PIN=""
+CONFIG_USB2_VBUS_PIN=""
+CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sina31s"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_ALDO2_VOLT=1800
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=15355
CONFIG_DRAM_ODT_EN=y
+CONFIG_INITIAL_USB_SCAN_DELAY=500
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_USB0_ID_DET="PH11"
+CONFIG_USB1_VBUS_PIN="PD24"
CONFIG_AXP_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-sinovoip-bpi-m3"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_AXP_DCDC1_VOLT=3000
CONFIG_AXP_DCDC5_VOLT=1200
-CONFIG_AXP_ALDO2_VOLT=0
-CONFIG_AXP_ALDO3_VOLT=0
+CONFIG_AXP_DLDO3_VOLT=2500
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPD(25)"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wits-pro-a20-dkt"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-wobo-i5"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_MUSB_HOST=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CLK=420
+CONFIG_DRAM_ZQ=251
+CONFIG_MMC0_CD_PIN="PA8"
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_USB0_ID_DET="PA15"
+CONFIG_AXP_GPIO=y
+CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:70000,le:120,ri:180,up:17,lo:15,hs:20,vs:3,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_BL_EN="PA25"
+CONFIG_VIDEO_LCD_BL_PWM="PH13"
+CONFIG_VIDEO_LCD_PANEL_LVDS=y
+CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-yones-toptech-bs1078-v2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_USB_MUSB_HOST=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_NS16550=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_NS16550=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_RSA=y
CONFIG_TARGET_AM3517_EVM=y
CONFIG_SPL=y
CONFIG_FIT=y
-CONFIG_SYS_PROMPT="AM3517_EVM # "
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_SYS_PROMPT="AM3517_EVM # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_DMA=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
-CONFIG_DMA=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_RTL8169=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA20_SLINK=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_RTL8169=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA20_SLINK=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_NS16550=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_DM_VIDEO=y
-CONFIG_I2C_EDID=y
-CONFIG_VIDEO_ROTATION=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_VENDOR_GOOGLE=y
CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
CONFIG_TARGET_CHROMEBOOK_LINK=y
-CONFIG_HAVE_MRC=y
CONFIG_ENABLE_MRC_CACHE=y
+CONFIG_HAVE_MRC=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_FIT=y
CONFIG_HAVE_REFCODE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
CONFIG_VENDOR_GOOGLE=y
CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther"
CONFIG_TARGET_CHROMEBOX_PANTHER=y
-CONFIG_HAVE_MRC=y
CONFIG_ENABLE_MRC_CACHE=y
+CONFIG_HAVE_MRC=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
+CONFIG_RTL8169=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_TARGET_CM_T43=y
+CONFIG_DM_SERIAL=y
CONFIG_DM_GPIO=y
CONFIG_SPL=y
CONFIG_SYS_PROMPT="CM-T43 # "
CONFIG_CMD_GPIO=y
# CONFIG_CMD_NFS is not set
CONFIG_DM=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
-CONFIG_DM_SERIAL=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
# CONFIG_CMD_NFS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
CONFIG_FSL_LPUART=y
CONFIG_FSL_DSPI=y
-CONFIG_OF_LIBFDT=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=251
+CONFIG_MMC0_CD_PIN="PA8"
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_USB0_ID_DET="PA15"
+CONFIG_AXP_GPIO=y
+CONFIG_VIDEO_LCD_MODE="x:800,y:1280,depth:24,pclk_khz:64000,le:20,ri:34,up:1,lo:16,hs:10,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_BL_EN="PA25"
+CONFIG_VIDEO_LCD_BL_PWM="PH13"
+CONFIG_VIDEO_LCD_PANEL_LVDS=y
+CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-colorfly-e708-q1"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_AXP_DLDO2_VOLT=1800
+CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_USE_PRIVATE_LIBGCC=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_DB_88F6720=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-375-db"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_MISC=y
+CONFIG_NAND_PXA3XX=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_MVPP2=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xf1012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=408
+CONFIG_MMC0_CD_PIN="PG0"
+CONFIG_USB0_VBUS_PIN="PG12"
+CONFIG_USB0_VBUS_DET="PG1"
+CONFIG_USB0_ID_DET="PG2"
+CONFIG_AXP_GPIO=y
+# CONFIG_VIDEO_HDMI is not set
+CONFIG_VIDEO_LCD_MODE="x:480,y:272,depth:18,pclk_khz:12000,le:1,ri:43,up:1,lo:12,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_POWER="AXP0-0"
+CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-difrnce-dit4350"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_USB_MUSB_HOST=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SNAPDRAGON=y
+CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c"
+CONFIG_SYS_PROMPT="dragonboard410c => "
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_USB=y
+CONFIG_CLK=y
+CONFIG_MSM_GPIO=y
+CONFIG_PM8916_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_RESET=y
+CONFIG_DM_MMC=y
+CONFIG_MSM_SDHCI=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PM8916=y
+CONFIG_MSM_SERIAL=y
+CONFIG_SPMI_MSM=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MSM=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=360
+CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_USB0_VBUS_PIN="PB9"
+CONFIG_USB0_VBUS_DET="PH5"
+CONFIG_USB0_ID_DET="PH4"
+CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:80000,le:479,ri:544,up:5,lo:26,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_POWER="PH8"
+CONFIG_VIDEO_LCD_BL_EN="PH7"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_VIDEO_LCD_PANEL_LVDS=y
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-dserve-dsrv9703c"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_USB_MUSB_HOST=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_DM_VIDEO=y
-CONFIG_I2C_EDID=y
-CONFIG_VIDEO_ROTATION=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ga10h-v1.1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-gt90h-v4"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=15355
CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+CONFIG_USB0_VBUS_PIN="PL5"
+CONFIG_USB1_VBUS_PIN="PL6"
CONFIG_AXP_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-allwinner-h8homlet-v2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_AXP_DCDC1_VOLT=3000
-CONFIG_AXP_DCDC5_VOLT=1500
+CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_NFS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,MACPWR=SUNXI_GPH(21)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_MUSB_HOST=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_OLD_SUNXI_KERNEL_COMPAT=y
+CONFIG_MMC0_CD_PIN="PI5"
+CONFIG_USB0_VBUS_PIN="PG11"
+CONFIG_USB0_VBUS_DET="PH7"
+CONFIG_USB1_VBUS_PIN="PG10"
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_POWER="PH22"
+CONFIG_VIDEO_LCD_PANEL_LVDS=y
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-swac"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,CMD_BMP,CMD_UNZIP"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet97fv2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-98v-rev2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet9f-rev03"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(19)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_RTL8169=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SYS_NS16550=y
CONFIG_DM_ETH=y
+CONFIG_SYS_NS16550=y
CONFIG_DEFAULT_DEVICE_TREE="k2g-evm"
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_CMD_REMOTEPROC=y
-CONFIG_REMOTEPROC_TI_POWER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_REMOTEPROC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SYS_NS16550=y
CONFIG_DM_ETH=y
+CONFIG_REMOTEPROC_TI_POWER=y
+CONFIG_SYS_NS16550=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SYS_NS16550=y
CONFIG_DM_ETH=y
+CONFIG_SYS_NS16550=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SYS_NS16550=y
CONFIG_DM_ETH=y
+CONFIG_SYS_NS16550=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_OF_LIBFDT=y
CONFIG_CMD_TIME=y
CONFIG_NETCONSOLE=y
CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
-CONFIG_DM_SERIAL=y
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
-CONFIG_DM_SERIAL=y
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_FSL_LPUART=y
-CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DM_SERIAL=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DM_SERIAL=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_FSL_LPUART=y
-CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
+CONFIG_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
-CONFIG_SYS_NS16550=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI=y
-CONFIG_OF_LIBFDT=y
+CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
+CONFIG_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_NS16550=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI=y
-CONFIG_OF_LIBFDT=y
+CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT"
+CONFIG_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT"
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI=y
+CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
+CONFIG_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
-CONFIG_SYS_NS16550=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI=y
-CONFIG_OF_LIBFDT=y
+CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
+CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI=y
+CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT"
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
+CONFIG_RSA=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080ARDB=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT"
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
+CONFIG_RSA=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080A_EMU=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2085A"
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080A_SIMU=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2085A"
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080AQDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
-CONFIG_FSL_DSPI=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080AQDS=y
-CONFIG_SPL=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080ARDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
-CONFIG_FSL_DSPI=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080ARDB=y
-CONFIG_SPL=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_USB=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT_OMAP=y
# CONFIG_CMD_NFS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
+CONFIG_RTL8169=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_AXP152_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_SUNXI_NO_PMIC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_USB=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT_OMAP=y
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_PWM=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_TPM_TIS_INFINEON=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_DISPLAY=y
-CONFIG_I2C_EDID=y
+CONFIG_USB_GADGET=y
CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
CONFIG_VIDEO_TEGRA124=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_DM_REGULATOR=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_ERRNO_STR=y
CONFIG_DM_REGULATOR_MAX77686=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_ERRNO_STR=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_TARGET_OMAP3_LOGIC=y
CONFIG_SPL=y
CONFIG_FIT=y
-CONFIG_SYS_PROMPT="OMAP Logic # "
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_SYS_PROMPT="OMAP Logic # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+# CONFIG_VIDEO is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SY8106A_POWER=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB1_VBUS_PIN="PG13"
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+# CONFIG_VIDEO is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB1_VBUS_PIN=""
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB1_VBUS_PIN=""
+CONFIG_USB2_VBUS_PIN=""
+CONFIG_USB3_VBUS_PIN=""
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_VIDEO is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB1_VBUS_PIN="PG13"
+CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPG(11)"
CONFIG_OF_CONTROL=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_RTL8169=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
# CONFIG_CMD_NFS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_FSL_LPUART=y
-CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_RARP=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_FULL is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_PIC32=y
+CONFIG_USB_STORAGE=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881915
+# CONFIG_VIDEO is not set
+CONFIG_DEFAULT_DEVICE_TREE="pine64_plus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A23=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=63351
+CONFIG_MMC0_CD_PIN="PB4"
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_USB0_ID_DET="PH8"
+CONFIG_AXP_GPIO=y
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:36,ri:210,up:18,lo:22,hs:10,vs:5,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_POWER="PH7"
+CONFIG_VIDEO_LCD_BL_EN="PH6"
+CONFIG_VIDEO_LCD_BL_PWM="PH0"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2809pxe04"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pov-protab2-ips9"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_MUSB_HOST=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
CONFIG_SH=y
CONFIG_TARGET_R2DPLUS=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_RTL8139=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_AXP152_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_DM_VIDEO=y
-CONFIG_I2C_EDID=y
-CONFIG_VIDEO_ROTATION=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_USE_PRIVATE_LIBGCC=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_BCM283X=y
+CONFIG_TARGET_RPI_3_32B=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_PROMPT="U-Boot> "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_PHYS_TO_BUS=y
+CONFIG_OF_LIBFDT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_BCM283X=y
+CONFIG_TARGET_RPI_3=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_PROMPT="U-Boot> "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_PHYS_TO_BUS=y
+CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_CONTROL=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_CMD_SF=y
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_SF=y
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_BLK=y
CONFIG_CLK=y
CONFIG_SANDBOX_GPIO=y
+CONFIG_PM8916_GPIO=y
CONFIG_SYS_I2C_SANDBOX=y
CONFIG_CROS_EC_KEYB=y
CONFIG_LED=y
CONFIG_PINCTRL_SANDBOX=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_SANDBOX=y
+CONFIG_PMIC_PM8916=y
+CONFIG_SPMI=y
+CONFIG_SPMI_SANDBOX=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_SANDBOX=y
CONFIG_RAM=y
# CONFIG_CMD_NFS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_NFS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_THEADORABLE=y
+CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_THEADORABLE=y
+CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
-# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_OF_CONTROL=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_CONTROL=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_RTL8169=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA20_SFLASH=y
CONFIG_CMD_TIME=y
CONFIG_NETCONSOLE=y
CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
CONFIG_CMD_TIME=y
CONFIG_NETCONSOLE=y
CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_USB=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT_OMAP=y
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ARCH_UNIPHIER_PH1_PRO4=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
-CONFIG_ARCH_UNIPHIER_PH1_SLD3=y
+CONFIG_ARCH_UNIPHIER_SLD3=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref"
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_NFS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DM_SERIAL=y
-CONFIG_DEFAULT_DEVICE_TREE="vexpress64"
CONFIG_SYS_PROMPT="VExpress64# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
CONFIG_TARGET_VEXPRESS64_JUNO=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DM_SERIAL=y
-CONFIG_DEFAULT_DEVICE_TREE="vexpress64"
CONFIG_SYS_PROMPT="VExpress64# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
CONFIG_TARGET_VEXPRESS64_BASE_FVP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DM_SERIAL=y
-CONFIG_DEFAULT_DEVICE_TREE="vexpress64"
CONFIG_SYS_PROMPT="VExpress64# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPI_FLASH=y
CONFIG_FSL_LPUART=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPI_FLASH=y
CONFIG_FSL_LPUART=y
-CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_XILINX_PPC405_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc405-generic"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000"
CONFIG_SYS_PROMPT="xlx-ppc405:/# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_MALLOC_SIMPLE=y
-CONFIG_XILINX_UARTLITE=y
-CONFIG_SYS_NS16550=y
CONFIG_OF_EMBED=y
-CONFIG_OF_CONTROL=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc405-generic"
+CONFIG_SYS_NS16550=y
+CONFIG_XILINX_UARTLITE=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_XILINX_PPC440_GENERIC=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1"
-CONFIG_SYS_PROMPT="board:/# "
-CONFIG_SYS_MALLOC_SIMPLE=y
-CONFIG_XILINX_UARTLITE=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_EMBED=y
-CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1"
+CONFIG_SYS_PROMPT="board:/# "
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_OF_EMBED=y
CONFIG_NETCONSOLE=y
+CONFIG_SYS_NS16550=y
+CONFIG_XILINX_UARTLITE=y
CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
CONFIG_ARCH_ZYNQMP=y
CONFIG_ZYNQMP_USB=y
-CONFIG_NAND_ARASAN=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ZYNQ_SDHCI=y
+CONFIG_NAND_ARASAN=y
CONFIG_ZYNQ_GEM=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
# CONFIG_REGEX is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_ZIPITZ2=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="$ "
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_ZYNQ_GEM=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
const int n_ents = ll_entry_count(struct part_driver, part_driver);
struct part_driver *entry;
+ blkcache_invalidate(dev_desc->if_type, dev_desc->devnum);
+
dev_desc->part_type = PART_TYPE_UNKNOWN;
for (entry = drv; entry != drv + n_ents; entry++) {
int ret;
char uuid[37];
unsigned char *uuid_bin;
- if (!dev_desc) {
- printf("%s: Invalid Argument(s)\n", __func__);
- return;
- }
/* This function validates AND fills in the GPT header and PTE */
if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
gpt_head, &gpt_pte) != 1) {
gpt_entry *gpt_pte = NULL;
/* "part" argument must be at least 1 */
- if (!dev_desc || !info || part < 1) {
+ if (part < 1) {
printf("%s: Invalid Argument(s)\n", __func__);
return -1;
}
#include <common.h>
#include <command.h>
+#include <asm/unaligned.h>
#include "part_iso.h"
#ifdef HAVE_BLOCK_DEVICE
static unsigned char tmpbuf[CD_SECTSIZE];
-/* Convert char[4] in little endian format to the host format integer
- */
-static inline unsigned long le32_to_int(unsigned char *le32)
-{
- return ((le32[3] << 24) +
- (le32[2] << 16) +
- (le32[1] << 8) +
- le32[0]
- );
-}
-/* Convert char[2] in little endian format to the host format integer
- */
-static inline unsigned short le16_to_int(unsigned char *le16)
-{
- return ((le16[1] << 8) +
- le16[0]
- );
-}
-
-
/* only boot records will be listed as valid partitions */
int part_get_info_iso_verb(struct blk_desc *dev_desc, int part_num,
disk_partition_t *info, int verb)
pbr->ident_str, dev_desc->devnum, part_num);
return (-1);
}
- bootaddr=le32_to_int(pbr->pointer);
+ bootaddr = get_unaligned_le32(pbr->pointer);
PRINTF(" Boot Entry at: %08lX\n",bootaddr);
if (blk_dread(dev_desc, bootaddr, 1, (ulong *)tmpbuf) != 1) {
if(verb)
}
switch(pide->boot_media) {
case 0x00: /* no emulation */
- info->size=le16_to_int(pide->sec_cnt)>>2;
+ info->size = get_unaligned_le16(pide->sec_cnt)>>2;
break;
case 0x01: info->size=2400>>2; break; /* 1.2MByte Floppy */
case 0x02: info->size=2880>>2; break; /* 1.44MByte Floppy */
case 0x04: info->size=2880>>2; break; /* dummy (HD Emulation) */
default: info->size=0; break;
}
- newblkaddr=le32_to_int(pide->rel_block_addr);
+ newblkaddr = get_unaligned_le32(pide->rel_block_addr);
info->start=newblkaddr;
PRINTF(" part %d found @ %lx size %lx\n",part_num,newblkaddr,info->size);
return 0;
This group will contain: b, bl, bc.
The first 2 instructions (b, bl) will be verified by jumping to
- a fixed address and checking whether control was transfered to
+ a fixed address and checking whether control was transferred to
that very point. For the bl instruction the value of the link
register will be checked as well (using mfspr). To verify the bc
instruction various combinations of the BI/BO fields, the CTR
Binary packages can be installed as usual, e.g.:
sudo apt-get install clang
-To compile U-Boot with clang on linux without IAS use e.g.:
-export TRIPLET=arm-linux-gnueabi && export CROSS_COMPILE="$TRIPLET-"
-make HOSTCC=clang CC="clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrated-as" rpi_defconfig
-make HOSTCC=clang CC="clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrated-as" all V=1 -j8
+Note that we still use binutils for some tools so we must continue to set
+CROSS_COMPILE. To compile U-Boot with clang on linux without IAS use e.g.:
+make HOSTCC=clang rpi_2_defconfig
+make HOSTCC=clang CROSS_COMPILE=arm-linux-gnueabi- CC=clang -j8
+
+It can also be used to compile sandbox:
+make HOSTCC=clang sandbox_defconfig
+make HOSTCC=clang CC=clang -j8
FreeBSD 11 (Current):
--------------------
# The following commands compile U-Boot using the clang xdev toolchain.
# NOTE: CROSS_COMPILE and target differ on purpose!
export CROSS_COMPILE=arm-gnueabi-freebsd-
-gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" rpi_defconfig
-gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" -j8
+gmake rpi_2_defconfig
+gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd" -j8
Given that U-Boot will default to gcc, above commands can be
simplified with a simple wrapper script, listed below.
---
#!/bin/sh
-exec clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0 "$@"
-
+exec clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd "$@"
Syntax is
hwconfig=fsl_ddr:ecc=off
+
+Memory address parity on/off
+============================
+address parity can be turned on/off by hwconfig.
+Syntax is:
+hwconfig=fsl_ddr:parity=on
+
+
Memory testing options for mpc85xx
==================================
1. Memory test can be done once U-Boot prompt comes up using mtest, or
hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
+
Table for dynamic ODT for DDR3
==============================
For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may
Burn U-Boot images to NAND
--------------------------
-Write two files to the NAND device as follows:
+Write the following to the NAND device:
+
- spl/u-boot-spl.bin at the offset address 0x00000000
- - u-boot.img at the offset address 0x00010000
+ - u-boot.bin at the offset address 0x00010000
+
+or
+
+ - u-boot-with-spl.bin at the offset address 0x00000000
If a TFTP server is available, the images can be easily updated.
-Just copy the u-boot-spl-dtb.bin and u-boot-dtb.img to the TFTP public
-directory, and then run the following command at the U-Boot command line:
+Just copy the u-boot-spl.bin and u-boot.bin to the TFTP public directory,
+and then run the following command at the U-Boot command line:
=> run nandupdate
Burn U-Boot images to eMMC
--------------------------
-Write two files to the Boot partition 1 of the eMMC device as follows:
+Write the following to the Boot partition 1 of the eMMC device:
+
- spl/u-boot-spl.bin at the offset address 0x00000000
- - u-boot.img at the offset address 0x00010000
+ - u-boot.bin at the offset address 0x00010000
+
+or
+
+ - u-boot-with-spl.bin at the offset address 0x00000000
If a TFTP server is available, the images can be easily updated.
-Just copy the u-boot-spl-dtb.bin and u-boot-dtb.img to the TFTP public
-directory, and then run the following command at the U-Boot command line:
+Just copy the u-boot-spl.bin and u-boot.bin to the TFTP public directory,
+and then run the following command at the U-Boot command line:
=> run emmcupdate
--- /dev/null
+Qualcomm Snapdragon GPIO controller
+
+Required properties:
+- compatible : "qcom,msm8916-pinctrl" or "qcom,apq8016-pinctrl"
+- reg : Physical base address and length of the controller's registers.
+ This controller is called "Top Level Mode Multiplexing" in
+ Qualcomm documentation.
+- #gpio-cells : Should be one (pin number).
+- gpio-controller : Marks the device node as a GPIO controller.
+- gpio-count: Number of GPIO pins.
+- gpio-bank-name: (optional) name of gpio bank. As default "soc" is used.
+
+Example:
+
+soc_gpios: pinctrl@1000000 {
+ compatible = "qcom,msm8916-pinctrl";
+ reg = <0x1000000 0x300000>;
+ gpio-controller;
+ gpio-count = <122>;
+ gpio-bank-name="soc";
+ #gpio-cells = <1>;
+};
--- /dev/null
+Driver for part of pm8916 PMIC - gpio and power/reset keys
+
+This device should be child of SPMI pmic.
+
+1) GPIO driver
+
+Required properties:
+- compatible: "qcom,pm8916-gpio"
+- reg: peripheral ID, size of register block
+- gpio-controller
+- gpio-count: number of GPIOs
+- #gpio-cells: 2
+
+Optional properties:
+- gpio-bank-name: name of bank (as default "pm8916" is used)
+
+Example:
+
+pmic_gpios: gpios@c000 {
+ compatible = "qcom,pm8916-gpio";
+ reg = <0xc000 0x400>;
+ gpio-controller;
+ gpio-count = <4>;
+ #gpio-cells = <2>;
+ gpio-bank-name="pmic";
+};
+
+
+2) Power/Reset key driver
+
+Required properties:
+- compatible: "qcom,pm8916-pwrkey"
+- reg: peripheral ID, size of register block
+- gpio-controller
+- #gpio-cells: 2
+
+Optional properties:
+- gpio-bank-name: name of bank (as default "pm8916_key" is used)
+
+
+Example:
+
+pmic_pon: pon@800 {
+ compatible = "qcom,pm8916-pwrkey";
+ reg = <0x800 0x96>;
+ #gpio-cells = <2>;
+ gpio-controller;
+};
--- /dev/null
+Qualcomm Snapdragon SDHCI controller
+
+Required properties:
+- compatible : "qcom,sdhci-msm-v4"
+- reg: Base address and length of registers:
+ - Host controller registers (SDHCI)
+ - SD Core registers
+- clock: interface clock (must accept SD bus clock as a frequency)
+
+Optional properties:
+- index: If there is more than one controller - controller index (required
+ by generic SDHCI code).
+- bus_width: Width of SD/eMMC bus (default 4)
+- clock-frequency: Frequency of SD/eMMC bus (default 400 kHz)
+
+Example:
+
+sdhci@07864000 {
+ compatible = "qcom,sdhci-msm-v4";
+ reg = <0x7864900 0x11c 0x7864000 0x800>;
+ index = <0x1>;
+ bus-width = <0x4>;
+ clock = <&clkc 1>;
+ clock-frequency = <200000000>;
+};
--- /dev/null
+Qualcomm pm8916 PMIC
+
+This PMIC is connected using SPMI bus so should be child of SPMI bus controller.
+
+Required properties:
+- compatible: "qcom,spmi-pmic";
+- reg: SPMI Slave ID, size (ignored)
+- #address-cells: 0x1 (peripheral ID)
+- #size-cells: 0x1 (size of peripheral register space)
+
+Example:
+
+pm8916@0 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x0 0x1>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+};
Represents a single port that is compatible with the DUART found
on many Freescale chips (examples include mpc8349, mpc8548,
- mpc8641d, p4080 and ls2085a).
+ mpc8641d, p4080 and ls2080a).
Example:
--- /dev/null
+Qualcomm UART (Data Mover mode)
+
+Required properties:
+- compatible: must be "qcom,msm-uartdm-v1.4"
+- reg: start address and size of the registers
+- clock: interface clock (must accept baudrate as a frequency)
a header byte before reading data from the slave.
Some SPI controllers and devices support Dual and Quad SPI transfer mode.
-It allows data in SPI system transfered in 2 wires(DUAL) or 4 wires(QUAD).
+It allows data in SPI system transferred in 2 wires(DUAL) or 4 wires(QUAD).
Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is
only 1(SINGLE), 2(DUAL) and 4(QUAD).
Dual/Quad mode is not allowed when 3-wire mode is used.
--- /dev/null
+Qualcomm SPMI arbiter/bus driver
+
+This is bus driver for Qualcomm chips that use SPMI to communicate with PMICs.
+
+Required properties:
+- compatible: "qcom,spmi-pmic-arb"
+- reg: Register block adresses and sizes for various parts of device:
+ 1) PMIC arbiter channel mapping base (PMIC_ARB_REG_CHNLn)
+ 2) SPMI write command (master) registers (PMIC_ARB_CORE_SW_DEC_CHANNELS)
+ 3) SPMI read command (observer) registers (PMIC_ARB_CORE_REGISTERS_OBS)
+
+Optional properties (if not set by parent):
+- #address-cells: 0x1 - childs slave ID address
+- #size-cells: 0x1
+
+All PMICs should be placed as a child nodes of bus arbiter.
+Automatic detection of childs is currently not supported.
+
+Example:
+
+spmi@200f000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x200f800 0x200 0x2400000 0x400000 0x2c00000 0x400000>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+};
--- /dev/null
+Sandbox SPMI emulated arbiter.
+
+This is bus driver for Sandbox. It includes part of emulated pm8916 pmic.
+
+Required properties:
+- compatible: "sandbox,spmi"
+- #address-cells: 0x1 - childs slave ID address
+- #size-cells: 0x1
+
+Example:
+
+spmi: spmi@0 {
+ compatible = "sandbox,spmi";
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ pm8916@0 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x0 0x1>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+
+ spmi_gpios: gpios@c000 {
+ compatible = "qcom,pm8916-gpio";
+ reg = <0xc000 0x400>;
+ gpio-controller;
+ gpio-count = <4>;
+ #gpio-cells = <2>;
+ gpio-bank-name="spmi";
+ };
+ };
+};
--- /dev/null
+Chipidea EHCI controller (part of OTG controller) used on Qualcomm devices.
+
+Required properties:
+- compatible: must be "qcom,ehci-host"
+- reg: start address and size of the registers
+
+ehci@78d9000 {
+ compatible = "qcom,ehci-host";
+ reg = <0x78d9000 0x400>;
+};
alias macpaul Macpaul Lin <macpaul@andestech.com>
alias marex Marek Vasut <marex@denx.de>
alias masahiro Masahiro Yamada <yamada.masahiro@socionext.com>
+alias mateusz Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
alias monstr Michal Simek <monstr@monstr.eu>
alias panto Pantelis Antoniou <panto@antoniou-consulting.com>
alias prafulla Prafulla Wadaskar <prafulla@marvell.com>
alias s3c samsung
alias s5pc samsung
alias samsung uboot, prom
+alias snapdragon uboot, mateusz
alias socfpga uboot, marex, Dinh Nguyen <dinguyen@opensource.altera.com>
alias sunxi uboot, ijc, jwrdegoede
alias tegra uboot, sjg, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com>
alias net uboot, jhersh
alias phy uboot, jhersh
alias spi uboot, jagan
+alias spmi uboot, mateusz
alias ubi uboot, hs
alias usb uboot, marex
alias video uboot, ag
Following power-up or a system reset, system BootROM code polls the
UART for a brief period of time, sensing a handshake message which
initiates an image upload. This program sends this boot message until
-it receives a positive acknowledgement. The image is transfered using
+it receives a positive acknowledgement. The image is transferred using
Xmodem.
Additionally, this program implements a minimal terminal mode, which
also.
-Creating an RSA key and certificate
------------------------------------
-To create a new public key, size 2048 bits:
+Creating an RSA key pair and certificate
+----------------------------------------
+To create a new public/private key pair, size 2048 bits:
$ openssl genpkey -algorithm RSA -out keys/dev.key \
-pkeyopt rsa_keygen_bits:2048 -pkeyopt rsa_keygen_pubexp:65537
-To create a certificate for this:
+To create a certificate for this containing the public key:
$ openssl req -batch -new -x509 -key keys/dev.key -out keys/dev.crt
conforms to bindings defined in this document.
.its - image tree source
-.fit - flattened image tree blob
+.itb - flattened image tree blob
c) Image building procedure
source "drivers/spi/Kconfig"
+source "drivers/spmi/Kconfig"
+
source "drivers/thermal/Kconfig"
source "drivers/timer/Kconfig"
obj-$(CONFIG_X86) += pch/
obj-y += rtc/
obj-y += sound/
+obj-y += spmi/
obj-y += timer/
obj-y += tpm/
obj-y += twserial/
types can use this, such as AHCI/SATA. It does not provide any standard
operations at present. The block device interface has not been converted
to driver model.
+
+config BLOCK_CACHE
+ bool "Use block device cache"
+ default n
+ help
+ This option enables a disk-block cache for all block devices.
+ This is most useful when accessing filesystems under U-Boot since
+ it will prevent repeated reads from directory structures and other
+ filesystem data structures.
obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
obj-$(CONFIG_MX51_PATA) += mxc_ata.o
obj-$(CONFIG_PATA_BFIN) += pata_bfin.o
+obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
obj-$(CONFIG_SATA_DWC) += sata_dwc.o
obj-$(CONFIG_SATA_MV) += sata_mv.o
obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
obj-$(CONFIG_SANDBOX) += sandbox.o
obj-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
obj-$(CONFIG_SYSTEMACE) += systemace.o
+obj-$(CONFIG_BLOCK_CACHE) += blkcache.o
{
struct udevice *dev = block_dev->bdev;
const struct blk_ops *ops = blk_get_ops(dev);
+ ulong blks_read;
if (!ops->read)
return -ENOSYS;
- return ops->read(dev, start, blkcnt, buffer);
+ if (blkcache_read(block_dev->if_type, block_dev->devnum,
+ start, blkcnt, block_dev->blksz, buffer))
+ return blkcnt;
+ blks_read = ops->read(dev, start, blkcnt, buffer);
+ if (blks_read == blkcnt)
+ blkcache_fill(block_dev->if_type, block_dev->devnum,
+ start, blkcnt, block_dev->blksz, buffer);
+
+ return blks_read;
}
unsigned long blk_dwrite(struct blk_desc *block_dev, lbaint_t start,
if (!ops->write)
return -ENOSYS;
+ blkcache_invalidate(block_dev->if_type, block_dev->devnum);
return ops->write(dev, start, blkcnt, buffer);
}
if (!ops->erase)
return -ENOSYS;
+ blkcache_invalidate(block_dev->if_type, block_dev->devnum);
return ops->erase(dev, start, blkcnt);
}
--- /dev/null
+/*
+ * Copyright (C) Nelson Integration, LLC 2016
+ * Author: Eric Nelson<eric@nelint.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <part.h>
+#include <linux/ctype.h>
+#include <linux/list.h>
+
+struct block_cache_node {
+ struct list_head lh;
+ int iftype;
+ int devnum;
+ lbaint_t start;
+ lbaint_t blkcnt;
+ unsigned long blksz;
+ char *cache;
+};
+
+static LIST_HEAD(block_cache);
+
+static struct block_cache_stats _stats = {
+ .max_blocks_per_entry = 2,
+ .max_entries = 32
+};
+
+static struct block_cache_node *cache_find(int iftype, int devnum,
+ lbaint_t start, lbaint_t blkcnt,
+ unsigned long blksz)
+{
+ struct block_cache_node *node;
+
+ list_for_each_entry(node, &block_cache, lh)
+ if ((node->iftype == iftype) &&
+ (node->devnum == devnum) &&
+ (node->blksz == blksz) &&
+ (node->start <= start) &&
+ (node->start + node->blkcnt >= start + blkcnt)) {
+ if (block_cache.next != &node->lh) {
+ /* maintain MRU ordering */
+ list_del(&node->lh);
+ list_add(&node->lh, &block_cache);
+ }
+ return node;
+ }
+ return 0;
+}
+
+int blkcache_read(int iftype, int devnum,
+ lbaint_t start, lbaint_t blkcnt,
+ unsigned long blksz, void *buffer)
+{
+ struct block_cache_node *node = cache_find(iftype, devnum, start,
+ blkcnt, blksz);
+ if (node) {
+ const char *src = node->cache + (start - node->start) * blksz;
+ memcpy(buffer, src, blksz * blkcnt);
+ debug("hit: start " LBAF ", count " LBAFU "\n",
+ start, blkcnt);
+ ++_stats.hits;
+ return 1;
+ }
+
+ debug("miss: start " LBAF ", count " LBAFU "\n",
+ start, blkcnt);
+ ++_stats.misses;
+ return 0;
+}
+
+void blkcache_fill(int iftype, int devnum,
+ lbaint_t start, lbaint_t blkcnt,
+ unsigned long blksz, void const *buffer)
+{
+ lbaint_t bytes;
+ struct block_cache_node *node;
+
+ /* don't cache big stuff */
+ if (blkcnt > _stats.max_blocks_per_entry)
+ return;
+
+ if (_stats.max_entries == 0)
+ return;
+
+ bytes = blksz * blkcnt;
+ if (_stats.max_entries <= _stats.entries) {
+ /* pop LRU */
+ node = (struct block_cache_node *)block_cache.prev;
+ list_del(&node->lh);
+ _stats.entries--;
+ debug("drop: start " LBAF ", count " LBAFU "\n",
+ node->start, node->blkcnt);
+ if (node->blkcnt * node->blksz < bytes) {
+ free(node->cache);
+ node->cache = 0;
+ }
+ } else {
+ node = malloc(sizeof(*node));
+ if (!node)
+ return;
+ node->cache = 0;
+ }
+
+ if (!node->cache) {
+ node->cache = malloc(bytes);
+ if (!node->cache) {
+ free(node);
+ return;
+ }
+ }
+
+ debug("fill: start " LBAF ", count " LBAFU "\n",
+ start, blkcnt);
+
+ node->iftype = iftype;
+ node->devnum = devnum;
+ node->start = start;
+ node->blkcnt = blkcnt;
+ node->blksz = blksz;
+ memcpy(node->cache, buffer, bytes);
+ list_add(&node->lh, &block_cache);
+ _stats.entries++;
+}
+
+void blkcache_invalidate(int iftype, int devnum)
+{
+ struct list_head *entry, *n;
+ struct block_cache_node *node;
+
+ list_for_each_safe(entry, n, &block_cache) {
+ node = (struct block_cache_node *)entry;
+ if ((node->iftype == iftype) &&
+ (node->devnum == devnum)) {
+ list_del(entry);
+ free(node->cache);
+ free(node);
+ --_stats.entries;
+ }
+ }
+}
+
+void blkcache_configure(unsigned blocks, unsigned entries)
+{
+ struct block_cache_node *node;
+ if ((blocks != _stats.max_blocks_per_entry) ||
+ (entries != _stats.max_entries)) {
+ /* invalidate cache */
+ while (!list_empty(&block_cache)) {
+ node = (struct block_cache_node *)block_cache.next;
+ list_del(&node->lh);
+ free(node->cache);
+ free(node);
+ }
+ _stats.entries = 0;
+ }
+
+ _stats.max_blocks_per_entry = blocks;
+ _stats.max_entries = entries;
+
+ _stats.hits = 0;
+ _stats.misses = 0;
+}
+
+void blkcache_stats(struct block_cache_stats *stats)
+{
+ memcpy(stats, &_stats, sizeof(*stats));
+ _stats.hits = 0;
+ _stats.misses = 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2015 - 2016 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <netdev.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <asm/arch/hardware.h>
+
+#include <asm/io.h>
+
+/* Vendor Specific Register Offsets */
+#define AHCI_VEND_PCFG 0xA4
+#define AHCI_VEND_PPCFG 0xA8
+#define AHCI_VEND_PP2C 0xAC
+#define AHCI_VEND_PP3C 0xB0
+#define AHCI_VEND_PP4C 0xB4
+#define AHCI_VEND_PP5C 0xB8
+#define AHCI_VEND_PAXIC 0xC0
+#define AHCI_VEND_PTC 0xC8
+
+/* Vendor Specific Register bit definitions */
+#define PAXIC_ADBW_BW64 0x1
+#define PAXIC_MAWIDD (1 << 8)
+#define PAXIC_MARIDD (1 << 16)
+#define PAXIC_OTL (0x4 << 20)
+
+#define PCFG_TPSS_VAL (0x32 << 16)
+#define PCFG_TPRS_VAL (0x2 << 12)
+#define PCFG_PAD_VAL 0x2
+
+#define PPCFG_TTA 0x1FFFE
+#define PPCFG_PSSO_EN (1 << 28)
+#define PPCFG_PSS_EN (1 << 29)
+#define PPCFG_ESDF_EN (1 << 31)
+
+#define PP2C_CIBGMN 0x0F
+#define PP2C_CIBGMX (0x25 << 8)
+#define PP2C_CIBGN (0x18 << 16)
+#define PP2C_CINMP (0x29 << 24)
+
+#define PP3C_CWBGMN 0x04
+#define PP3C_CWBGMX (0x0B << 8)
+#define PP3C_CWBGN (0x08 << 16)
+#define PP3C_CWNMP (0x0F << 24)
+
+#define PP4C_BMX 0x0a
+#define PP4C_BNM (0x08 << 8)
+#define PP4C_SFD (0x4a << 16)
+#define PP4C_PTST (0x06 << 24)
+
+#define PP5C_RIT 0x60216
+#define PP5C_RCT (0x7f0 << 20)
+
+#define PTC_RX_WM_VAL 0x40
+#define PTC_RSVD (1 << 27)
+
+#define PORT0_BASE 0x100
+#define PORT1_BASE 0x180
+
+/* Port Control Register Bit Definitions */
+#define PORT_SCTL_SPD_GEN3 (0x3 << 4)
+#define PORT_SCTL_SPD_GEN2 (0x2 << 4)
+#define PORT_SCTL_SPD_GEN1 (0x1 << 4)
+#define PORT_SCTL_IPM (0x3 << 8)
+
+#define PORT_BASE 0x100
+#define PORT_OFFSET 0x80
+#define NR_PORTS 2
+#define DRV_NAME "ahci-ceva"
+#define CEVA_FLAG_BROKEN_GEN2 1
+
+int init_sata(int dev)
+{
+ ulong tmp;
+ ulong mmio = ZYNQMP_SATA_BASEADDR;
+ int i;
+
+ /*
+ * AXI Data bus width to 64
+ * Set Mem Addr Read, Write ID for data transfers
+ * Transfer limit to 72 DWord
+ */
+ tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
+ writel(tmp, mmio + AHCI_VEND_PAXIC);
+
+ /* Set AHCI Enable */
+ tmp = readl(mmio + HOST_CTL);
+ tmp |= HOST_AHCI_EN;
+ writel(tmp, mmio + HOST_CTL);
+
+ for (i = 0; i < NR_PORTS; i++) {
+ /* TPSS TPRS scalars, CISE and Port Addr */
+ tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
+ writel(tmp, mmio + AHCI_VEND_PCFG);
+
+ /* Port Phy Cfg register enables */
+ tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
+ writel(tmp, mmio + AHCI_VEND_PPCFG);
+
+ /* Rx Watermark setting */
+ tmp = PTC_RX_WM_VAL | PTC_RSVD;
+ writel(tmp, mmio + AHCI_VEND_PTC);
+
+ /* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
+ tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
+ writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
+ }
+ return 0;
+}
/* struct pccb must be set-up correctly */
retrycnt=0;
PRINTF("ID %d issue cmd %02X\n",pccb->target,pccb->cmd[0]);
- pccb->trans_bytes=0; /* no bytes transfered yet */
+ pccb->trans_bytes=0; /* no bytes transferred yet */
scsi_set_script(pccb); /* fill in SCRIPT */
scsi_int_mask=STO | UDC | MA; /* | CMP; / * Interrupts which are enabled */
script_int_mask=0xff; /* enable all Ints */
for(i=0;i<3;i++)
int_stat[i]=0; /* delete all int status */
retrycnt++;
- PRINTF("ID: %X Phase Missmatch Retry %d Phase %02X transfered %lx\n",
+ PRINTF("ID: %X Phase Missmatch Retry %d Phase %02X transferred %lx\n",
pccb->target,retrycnt,scsi_read_byte(SBCL),pccb->trans_bytes);
scsi_write_dsp(phys_to_bus(&script_cmd[4])); /* start retry script */
goto retry;
writel(patterns[i % NBR_OF_PATTERNS],
&save_addr[i + OFFS_PATTERN]);
+ /* Make sure the data is written to RAM */
+ flush_dcache_range((ulong)&save_addr[0],
+ (ulong)&save_addr[REPEAT_PATTERN + OFFS_PATTERN]);
}
ulong bootcount_load(void)
#include <mapmem.h>
#include <linux/bitops.h>
#include <linux/io.h>
+#include <linux/sizes.h>
#include <clk.h>
#include <dm/device.h>
#include "clk-uniphier.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static int uniphier_clk_enable(struct udevice *dev, int index)
{
struct uniphier_clk_priv *priv = dev_get_priv(dev);
{
struct uniphier_clk_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
- fdt_size_t size;
- addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg",
- &size);
+ addr = dev_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
- priv->base = map_sysmem(addr, size);
+ priv->base = map_sysmem(addr, SZ_4K);
if (!priv->base)
return -ENOMEM;
#define OP_PCLID_BLOB (0x0d << OP_PCLID_SHIFT)
#define OP_PCLID_SECRETKEY (0x11 << OP_PCLID_SHIFT)
#define OP_PCLID_PUBLICKEYPAIR (0x14 << OP_PCLID_SHIFT)
+#define OP_PCLID_DSA_SIGN (0x15 << OP_PCLID_SHIFT)
+#define OP_PCLID_DSA_VERIFY (0x16 << OP_PCLID_SHIFT)
+
+/* Assuming OP_TYPE = OP_TYPE_DECAP_PROTOCOL */
+#define OP_PCLID_MP_PUB_KEY (0x14 << OP_PCLID_SHIFT)
+#define OP_PCLID_MP_SIGN (0x15 << OP_PCLID_SHIFT)
+
+/* Assuming OP_TYPE = OP_TYPE_ENCAP_PROTOCOL */
+#define OP_PCLID_MP_PRIV_KEY (0x14 << OP_PCLID_SHIFT)
+
+/* PROTINFO fields for discrete log public key protocols */
+#define OP_PROTINFO_F2M_FP 0x00000001
+#define OP_PROTINFO_ECC_DL 0x00000002
+#define OP_PROTINFO_ENC_PRI 0x00000004
+#define OP_PROTINFO_TEST 0x00000008
+#define OP_PROTINFO_EXT_PRI 0x00000010
+#define OP_PROTINFO_ENC_Z 0x00000020
+#define OP_PROTINFO_EKT_Z 0x00000040
+#define OP_PROTINFO_MES_REP 0x00000400
+#define OP_PROTINFO_HASH_MD5 0x00000000
+#define OP_PROTINFO_HASH_SHA1 0x00000080
+#define OP_PROTINFO_HASH_SHA224 0x00000100
+#define OP_PROTINFO_HASH_SHA256 0x00000180
+#define OP_PROTINFO_HASH_SHA384 0x00000200
+#define OP_PROTINFO_HASH_SHA512 0x00000280
/* For non-protocol/alg-only op commands */
#define OP_ALG_TYPE_SHIFT 24
#define OP_ALG_RNG4_MAS (0x1f3 << OP_ALG_RNG4_SHIFT)
#define OP_ALG_RNG4_SK (0x100 << OP_ALG_RNG4_SHIFT)
+
+/* Structures for Protocol Data Blocks */
+struct __packed pdb_ecdsa_verify {
+ uint32_t pdb_hdr;
+ dma_addr_t dma_q; /* Pointer to q (elliptic curve) */
+ dma_addr_t dma_r; /* Pointer to r (elliptic curve) */
+ dma_addr_t dma_g_xy; /* Pointer to Gx,y (elliptic curve) */
+ dma_addr_t dma_pkey; /* Pointer to Wx,y (public key) */
+ dma_addr_t dma_hash; /* Pointer to hash input */
+ dma_addr_t dma_c; /* Pointer to C_signature */
+ dma_addr_t dma_d; /* Pointer to D_signature */
+ dma_addr_t dma_buf; /* Pointer to 64-byte temp buffer */
+ dma_addr_t dma_ab; /* Pointer to a,b (elliptic curve ) */
+ uint32_t img_size; /* Length of Message */
+};
+
+struct __packed pdb_ecdsa_sign {
+ uint32_t pdb_hdr;
+ dma_addr_t dma_q; /* Pointer to q (elliptic curve) */
+ dma_addr_t dma_r; /* Pointer to r (elliptic curve) */
+ dma_addr_t dma_g_xy; /* Pointer to Gx,y (elliptic curve) */
+ dma_addr_t dma_pri_key; /* Pointer to S (Private key) */
+ dma_addr_t dma_hash; /* Pointer to hash input */
+ dma_addr_t dma_c; /* Pointer to C_signature */
+ dma_addr_t dma_d; /* Pointer to D_signature */
+ dma_addr_t dma_ab; /* Pointer to a,b (elliptic curve ) */
+ dma_addr_t dma_u; /* Pointer to Per Message Random */
+ uint32_t img_size; /* Length of Message */
+};
+
+#define PDB_ECDSA_SGF_SHIFT 23
+#define PDB_ECDSA_L_SHIFT 7
+#define PDB_ECDSA_N_SHIFT 0
+
+struct __packed pdb_mp_pub_k {
+ uint32_t pdb_hdr;
+ #define PDB_MP_PUB_K_SGF_SHIFT 31
+ dma_addr_t dma_pkey; /* Pointer to Wx,y (public key) */
+};
+
+struct __packed pdb_mp_sign {
+ uint32_t pdb_hdr;
+ #define PDB_MP_SIGN_SGF_SHIFT 28
+ dma_addr_t dma_addr_msg; /* Pointer to Message */
+ dma_addr_t dma_addr_hash; /* Pointer to hash output */
+ dma_addr_t dma_addr_c_sig; /* Pointer to C_signature */
+ dma_addr_t dma_addr_d_sig; /* Pointer to D_signature */
+ uint32_t img_size; /* Length of Message */
+};
+
+#define PDB_MP_CSEL_SHIFT 17
+#define PDB_MP_CSEL_P256 0x3 << PDB_MP_CSEL_SHIFT /* P-256 */
+#define PDB_MP_CSEL_P384 0x4 << PDB_MP_CSEL_SHIFT /* P-384 */
+#define PDB_MP_CSEL_P521 0x5 << PDB_MP_CSEL_SHIFT /* P-521 */
+
#endif /* DESC_H */
};
#endif
+static inline void pdb_add_ptr(dma_addr_t *offset, dma_addr_t ptr)
+{
+#ifdef CONFIG_PHYS_64BIT
+ /* The Position of low and high part of 64 bit address
+ * will depend on the endianness of CAAM Block */
+ union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset;
+ ptr_addr->m_halfs.high = (u32)(ptr >> 32);
+ ptr_addr->m_halfs.low = (u32)ptr;
+#else
+ *offset = ptr;
+#endif
+}
+
static inline int desc_len(u32 *desc)
{
return *desc & HDR_DESCLEN_MASK;
return desc + desc_len(desc);
}
+static inline void *desc_pdb(u32 *desc)
+{
+ return desc + 1;
+}
+
static inline void init_desc(u32 *desc, u32 options)
{
*desc = (options | HDR_ONE) + 1;
init_desc(desc, CMD_DESC_HDR | options);
}
+static inline void init_job_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes)
+{
+ u32 pdb_len = (pdb_bytes + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ;
+
+ init_job_desc(desc,
+ (((pdb_len + 1) << HDR_START_IDX_SHIFT) + pdb_len) |
+ options);
+}
+
static inline void append_ptr(u32 *desc, dma_addr_t ptr)
{
dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
#ifdef CONFIG_PHYS_64BIT
/* The Position of low and high part of 64 bit address
* will depend on the endianness of CAAM Block */
- union ptr_addr_t ptr_addr;
- ptr_addr.m_halfs.high = (u32)(ptr >> 32);
- ptr_addr.m_halfs.low = (u32)ptr;
- *offset = ptr_addr.m_whole;
+ union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset;
+ ptr_addr->m_halfs.high = (u32)(ptr >> 32);
+ ptr_addr->m_halfs.low = (u32)ptr;
#else
*offset = ptr;
#endif
}
}
- if (!op.status) {
+ if (op.status) {
debug("Error %x\n", op.status);
ret = op.status;
}
uint32_t liodn_s;
#endif
+ /*
+ * Modifying CAAM Read/Write Attributes
+ * For LS2080A
+ * For AXI Write - Cacheable, Write Back, Write allocate
+ * For AXI Read - Cacheable, Read allocate
+ * Only For LS2080a, to solve CAAM coherency issues
+ */
+#ifdef CONFIG_LS2080A
+ mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
+ mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
+#else
mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
+#endif
+
#ifdef CONFIG_PHYS_64BIT
mcr |= (1 << MCFGR_PS_SHIFT);
#endif
#define MCFGR_PS_SHIFT 16
#define MCFGR_AWCACHE_SHIFT 8
#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)
+#define MCFGR_ARCACHE_SHIFT 12
+#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT)
+
#define JR_INTMASK 0x00000001
#define JRCR_RESET 0x01
#define JRINT_ERR_HALT_INPROGRESS 0x4
slow = get_ddr_freq(ctrl_num) < 1249000000;
#endif
- if (popts->registered_dimm_en) {
+ if (popts->registered_dimm_en)
rcw_en = 1;
- ap_en = popts->ap_en;
- } else {
+
+ /* DDR4 can have address parity for UDIMM and discrete */
+ if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) &&
+ (!popts->registered_dimm_en)) {
ap_en = 0;
+ } else {
+ ap_en = popts->ap_en;
}
x4_en = popts->x4_en ? 1 : 0;
unsigned short esdmode5; /* Extended SDRAM mode 5 */
int rtt_park = 0;
bool four_cs = false;
+ const unsigned int mclk_ps = get_memory_clk_period_ps(0);
#if CONFIG_CHIP_SELECTS_PER_CTRL == 4
if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) &&
esdmode5 = 0x00000400; /* Data mask enabled */
}
+ /* set command/address parity latency */
+ if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+ if (mclk_ps >= 935) {
+ /* for DDR4-1600/1866/2133 */
+ esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
+ } else if (mclk_ps >= 833) {
+ /* for DDR4-2400 */
+ esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
+ } else {
+ printf("parity: mclk_ps = %d not supported\n", mclk_ps);
+ }
+ }
+
ddr->ddr_sdram_mode_9 = (0
| ((esdmode4 & 0xffff) << 16)
| ((esdmode5 & 0xffff) << 0)
} else {
esdmode5 = 0x00000400;
}
+
+ if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+ if (mclk_ps >= 935) {
+ /* for DDR4-1600/1866/2133 */
+ esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
+ } else if (mclk_ps >= 833) {
+ /* for DDR4-2400 */
+ esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
+ } else {
+ printf("parity: mclk_ps = %d not supported\n",
+ mclk_ps);
+ }
+ }
+
switch (i) {
case 1:
ddr->ddr_sdram_mode_11 = (0
const common_timing_params_t *common_dimm)
{
unsigned int txpr, tcksre, tcksrx;
- unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
+ unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd;
+ const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
- par_lat = 0;
+
+ if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+ if (mclk_ps >= 935) {
+ /* parity latency 4 clocks in case of 1600/1866/2133 */
+ par_lat = 4;
+ } else if (mclk_ps >= 833) {
+ /* parity latency 5 clocks for DDR4-2400 */
+ par_lat = 5;
+ } else {
+ printf("parity: mclk_ps = %d not supported\n", mclk_ps);
+ }
+ }
+
cs_to_cmd = 0;
if (txpr <= 200)
#include <fsl_ddr.h>
#include <fsl_errata.h>
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \
+ defined(CONFIG_SYS_FSL_ERRATUM_A009803)
static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
{
int timeout = 1000;
timeout--;
}
if (timeout <= 0)
- puts("Error: A007865 wait for clear timeout.\n");
+ puts("Error: wait for clear timeout.\n");
}
-#endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
+#endif
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
}
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009803
+ /* part 1 of 2 */
+ if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
+ ddr_out32(&ddr->ddr_sdram_rcw_2,
+ regs->ddr_sdram_rcw_2 & ~0x0f000000);
+ }
+
+ ddr_out32(&ddr->err_disable, regs->err_disable | DDR_ERR_DISABLE_APED);
+#else
ddr_out32(&ddr->err_disable, regs->err_disable);
+#endif
ddr_out32(&ddr->err_int_en, regs->err_int_en);
for (i = 0; i < 32; i++) {
if (regs->debug[i]) {
mb();
isb();
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
+ defined(CONFIG_SYS_FSL_ERRATUM_A009803)
/* Part 2 of 2 */
/* This erraum only applies to verion 5.2.0 */
if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
ctrl_num, ddr_in32(&ddr->debug[1]));
}
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
/* The vref setting sequence is different for range 2 */
if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
vref_seq = vref_seq2;
}
/* Restore D_INIT */
ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
- }
#endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009803
+ /* if it's RDIMM */
+ if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
+ continue;
+ set_wait_for_bits_clear(&ddr->sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL(i) |
+ 0x070000ed,
+ MD_CNTL_MD_EN);
+ udelay(1);
+ }
+ }
+
+ ddr_out32(&ddr->err_disable,
+ regs->err_disable & ~DDR_ERR_DISABLE_APED);
+#endif
+ }
+#endif
+
total_gb_size_per_controller = 0;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (!(regs->cs[i].config & 0x80000000))
* 18ns for all DDR4 speed grades.
*/
if (caslat_actual * mclk_ps > taamax) {
- printf("The choosen cas latency %d is too large\n",
- caslat_actual);
+ printf("The chosen cas latency %d is too large\n",
+ caslat_actual);
}
outpdimm->lowest_common_spd_caslat = caslat_actual;
debug("lowest_common_spd_caslat is 0x%x\n", caslat_actual);
popts->twot_en = 0;
popts->threet_en = 0;
- /* for RDIMM, address parity enable */
- popts->ap_en = 1;
+ /* for RDIMM and DDR4 UDIMM/discrete memory, address parity enable */
+ if (popts->registered_dimm_en)
+ popts->ap_en = 1; /* 0 = disable, 1 = enable */
+ else
+ popts->ap_en = 0; /* disabled for DDR4 UDIMM/discrete default */
+
+ if (hwconfig_sub_f("fsl_ddr", "parity", buf)) {
+ if (hwconfig_subarg_cmp_f("fsl_ddr", "parity", "on", buf)) {
+ if (popts->registered_dimm_en ||
+ (CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4))
+ popts->ap_en = 1;
+ }
+ }
/*
* BSTTOPRE precharge interval
SAR1_CPU_CORE_OFFSET;
switch (soc_num) {
case 0x3:
- reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET);
- reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET);
case 0x1:
reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET);
case 0x0:
obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
+obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
endif
{ Altera_StratixII, "StratixII", StratixII_load,
StratixII_dump, StratixII_info },
#endif
+#if defined(CONFIG_FPGA_STRATIX_V)
+ { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
+#endif
#if defined(CONFIG_FPGA_SOCFPGA)
{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
#endif
/* 3.1 check stratix has not signaled us an error */
if (fns->status (cookie) != 1) {
printf
- ("\n%s(%d) Stratix failed (byte transfered till failure 0x%x)\n",
+ ("\n%s(%d) Stratix failed (byte transferred till failure 0x%x)\n",
__FUNCTION__, __LINE__, bytecount);
fns->abort (cookie);
return FPGA_FAIL;
--- /dev/null
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <altera.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+
+/* Write the RBF data to FPGA via SPI */
+static int program_write(int spi_bus, int spi_dev, const void *rbf_data,
+ unsigned long rbf_size)
+{
+ struct spi_slave *slave;
+ int ret;
+
+ debug("%s (%d): data=%p size=%ld\n",
+ __func__, __LINE__, rbf_data, rbf_size);
+
+ /* FIXME: How to get the max. SPI clock and SPI mode? */
+ slave = spi_setup_slave(spi_bus, spi_dev, 27777777, SPI_MODE_3);
+ if (!slave)
+ return -1;
+
+ if (spi_claim_bus(slave))
+ return -1;
+
+ ret = spi_xfer(slave, rbf_size * 8, rbf_data, (void *)rbf_data,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+
+ spi_release_bus(slave);
+
+ return ret;
+}
+
+/*
+ * This is the interface used by FPGA driver.
+ * Return 0 for sucess, non-zero for error.
+ */
+int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ altera_board_specific_func *pfns = desc->iface_fns;
+ int cookie = desc->cookie;
+ int spi_bus;
+ int spi_dev;
+ int ret = 0;
+
+ if ((u32)rbf_data & 0x3) {
+ puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
+ return -EINVAL;
+ }
+
+ /* Run the pre configuration function if there is one */
+ if (pfns->pre)
+ (pfns->pre)(cookie);
+
+ /* Establish the initial state */
+ if (pfns->config) {
+ /* De-assert nCONFIG */
+ (pfns->config)(false, true, cookie);
+
+ /* nConfig minimum low pulse width is 2us */
+ udelay(200);
+
+ /* Assert nCONFIG */
+ (pfns->config)(true, true, cookie);
+
+ /* nCONFIG high to first rising clock on DCLK min 1506 us */
+ udelay(1600);
+ }
+
+ /* Write the RBF data to FPGA */
+ if (pfns->write) {
+ /*
+ * Use board specific data function to write bitstream
+ * into the FPGA
+ */
+ ret = (pfns->write)(rbf_data, rbf_size, true, cookie);
+ } else {
+ /*
+ * Use common SPI functions to write bitstream into the
+ * FPGA
+ */
+ spi_bus = COOKIE2SPI_BUS(cookie);
+ spi_dev = COOKIE2SPI_DEV(cookie);
+ ret = program_write(spi_bus, spi_dev, rbf_data, rbf_size);
+ }
+ if (ret)
+ return ret;
+
+ /* Check done pin */
+ if (pfns->done) {
+ ret = (pfns->done)(cookie);
+
+ if (ret)
+ printf("Error: DONE not set (ret=%d)!\n", ret);
+ }
+
+ return ret;
+}
help
Support for the LPC32XX GPIO driver.
+config MSM_GPIO
+ bool "Qualcomm GPIO driver"
+ depends on DM_GPIO
+ default n
+ help
+ Support GPIO controllers on Qualcomm Snapdragon family of SoCs.
+ This controller have single bank (default name "soc"), every
+ gpio has it's own set of registers.
+ Only simple GPIO operations are supported (get/set, change of
+ direction and checking pin function).
+ Supported devices:
+ - APQ8016
+ - MSM8916
+
+config PM8916_GPIO
+ bool "Qualcomm PM8916 PMIC GPIO/keypad driver"
+ depends on DM_GPIO && PMIC_PM8916
+ help
+ Support for GPIO pins and power/reset buttons found on
+ Qualcomm PM8916 PMIC.
+ Default name for GPIO bank is "pm8916".
+ Power and reset buttons are placed in "pm8916_key" bank and
+ have gpio numbers 0 and 1 respectively.
+
config ROCKCHIP_GPIO
bool "Rockchip GPIO driver"
depends on DM_GPIO
help
Say yes here to support Microchip PIC32 GPIOs.
+config MVEBU_GPIO
+ bool "Marvell MVEBU GPIO driver"
+ depends on DM_GPIO && ARCH_MVEBU
+ default y
+ help
+ Say yes here to support Marvell MVEBU (Armada XP/38x) GPIOs.
+
endmenu
obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o
obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o
obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o
+obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o
+obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
+obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
u8 reg;
switch (pin) {
-#ifdef CONFIG_AXP221_POWER /* Only available on axp221/axp223 */
+#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
+ /* Only available on later PMICs */
case SUNXI_GPIO_AXP0_VBUS_ENABLE:
- ret = pmic_bus_clrbits(AXP221_MISC_CTRL,
- AXP221_MISC_CTRL_N_VBUSEN_FUNC);
+ ret = pmic_bus_clrbits(AXP_MISC_CTRL,
+ AXP_MISC_CTRL_N_VBUSEN_FUNC);
if (ret)
return ret;
mask = AXP_POWER_STATUS_VBUS_PRESENT;
break;
#endif
-#ifdef CONFIG_AXP221_POWER /* Only available on axp221/axp223 */
+#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
+ /* Only available on later PMICs */
case SUNXI_GPIO_AXP0_VBUS_ENABLE:
- ret = pmic_bus_read(AXP221_VBUS_IPSOUT, &val);
- mask = AXP221_VBUS_IPSOUT_DRIVEBUS;
+ ret = pmic_bus_read(AXP_VBUS_IPSOUT, &val);
+ mask = AXP_VBUS_IPSOUT_DRIVEBUS;
break;
#endif
default:
u8 reg;
switch (pin) {
-#ifdef CONFIG_AXP221_POWER /* Only available on axp221/axp223 */
+#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
+ /* Only available on later PMICs */
case SUNXI_GPIO_AXP0_VBUS_ENABLE:
if (val)
- return pmic_bus_setbits(AXP221_VBUS_IPSOUT,
- AXP221_VBUS_IPSOUT_DRIVEBUS);
+ return pmic_bus_setbits(AXP_VBUS_IPSOUT,
+ AXP_VBUS_IPSOUT_DRIVEBUS);
else
- return pmic_bus_clrbits(AXP221_VBUS_IPSOUT,
- AXP221_VBUS_IPSOUT_DRIVEBUS);
+ return pmic_bus_clrbits(AXP_VBUS_IPSOUT,
+ AXP_VBUS_IPSOUT_DRIVEBUS);
#endif
default:
reg = axp_get_gpio_ctrl_reg(pin);
#include <mapmem.h>
#include <linux/bitops.h>
#include <linux/io.h>
+#include <linux/sizes.h>
#include <asm/errno.h>
#include <asm/gpio.h>
{
struct uniphier_gpio_priv *priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- DECLARE_GLOBAL_DATA_PTR;
fdt_addr_t addr;
- fdt_size_t size;
unsigned int tmp;
- addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg",
- &size);
+ addr = dev_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
- priv->base = map_sysmem(addr, size);
+ priv->base = map_sysmem(addr, SZ_8);
if (!priv->base)
return -ENOMEM;
--- /dev/null
+/*
+ * Qualcomm GPIO driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Register offsets */
+#define GPIO_CONFIG_OFF(no) ((no) * 0x1000)
+#define GPIO_IN_OUT_OFF(no) ((no) * 0x1000 + 0x4)
+
+/* OE */
+#define GPIO_OE_DISABLE (0x0 << 9)
+#define GPIO_OE_ENABLE (0x1 << 9)
+#define GPIO_OE_MASK (0x1 << 9)
+
+/* GPIO_IN_OUT register shifts. */
+#define GPIO_IN 0
+#define GPIO_OUT 1
+
+struct msm_gpio_bank {
+ phys_addr_t base;
+};
+
+static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
+{
+ struct msm_gpio_bank *priv = dev_get_priv(dev);
+ phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
+
+ /* Disable OE bit */
+ clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_DISABLE);
+
+ return 0;
+}
+
+static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
+{
+ struct msm_gpio_bank *priv = dev_get_priv(dev);
+
+ value = !!value;
+ /* set value */
+ writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
+
+ return 0;
+}
+
+static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio,
+ int value)
+{
+ struct msm_gpio_bank *priv = dev_get_priv(dev);
+ phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
+
+ value = !!value;
+ /* set value */
+ writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
+ /* switch direction */
+ clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_ENABLE);
+
+ return 0;
+}
+
+static int msm_gpio_get_value(struct udevice *dev, unsigned gpio)
+{
+ struct msm_gpio_bank *priv = dev_get_priv(dev);
+
+ return !!(readl(priv->base + GPIO_IN_OUT_OFF(gpio)) >> GPIO_IN);
+}
+
+static int msm_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ struct msm_gpio_bank *priv = dev_get_priv(dev);
+
+ if (readl(priv->base + GPIO_CONFIG_OFF(offset)) & GPIO_OE_ENABLE)
+ return GPIOF_OUTPUT;
+
+ return GPIOF_INPUT;
+}
+
+static const struct dm_gpio_ops gpio_msm_ops = {
+ .direction_input = msm_gpio_direction_input,
+ .direction_output = msm_gpio_direction_output,
+ .get_value = msm_gpio_get_value,
+ .set_value = msm_gpio_set_value,
+ .get_function = msm_gpio_get_function,
+};
+
+static int msm_gpio_probe(struct udevice *dev)
+{
+ struct msm_gpio_bank *priv = dev_get_priv(dev);
+
+ priv->base = dev_get_addr(dev);
+
+ return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
+}
+
+static int msm_gpio_ofdata_to_platdata(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "gpio-count", 0);
+ uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ "gpio-bank-name", NULL);
+ if (uc_priv->bank_name == NULL)
+ uc_priv->bank_name = "soc";
+
+ return 0;
+}
+
+static const struct udevice_id msm_gpio_ids[] = {
+ { .compatible = "qcom,msm8916-pinctrl" },
+ { .compatible = "qcom,apq8016-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(gpio_msm) = {
+ .name = "gpio_msm",
+ .id = UCLASS_GPIO,
+ .of_match = msm_gpio_ids,
+ .ofdata_to_platdata = msm_gpio_ofdata_to_platdata,
+ .probe = msm_gpio_probe,
+ .ops = &gpio_msm_ops,
+ .priv_auto_alloc_size = sizeof(struct msm_gpio_bank),
+};
--- /dev/null
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MVEBU_GPIOS_PER_BANK 32
+
+struct mvebu_gpio_regs {
+ u32 data_out;
+ u32 io_conf;
+ u32 blink_en;
+ u32 in_pol;
+ u32 data_in;
+};
+
+struct mvebu_gpio_priv {
+ struct mvebu_gpio_regs *regs;
+ char name[2];
+};
+
+static int mvebu_gpio_direction_input(struct udevice *dev, unsigned int gpio)
+{
+ struct mvebu_gpio_priv *priv = dev_get_priv(dev);
+ struct mvebu_gpio_regs *regs = priv->regs;
+
+ setbits_le32(®s->io_conf, BIT(gpio));
+
+ return 0;
+}
+
+static int mvebu_gpio_direction_output(struct udevice *dev, unsigned gpio,
+ int value)
+{
+ struct mvebu_gpio_priv *priv = dev_get_priv(dev);
+ struct mvebu_gpio_regs *regs = priv->regs;
+
+ if (value)
+ setbits_le32(®s->data_out, BIT(gpio));
+ else
+ clrbits_le32(®s->data_out, BIT(gpio));
+ clrbits_le32(®s->io_conf, BIT(gpio));
+
+ return 0;
+}
+
+static int mvebu_gpio_get_function(struct udevice *dev, unsigned gpio)
+{
+ struct mvebu_gpio_priv *priv = dev_get_priv(dev);
+ struct mvebu_gpio_regs *regs = priv->regs;
+ u32 val;
+
+ val = readl(®s->io_conf) & BIT(gpio);
+ if (val)
+ return GPIOF_INPUT;
+ else
+ return GPIOF_OUTPUT;
+}
+
+static int mvebu_gpio_set_value(struct udevice *dev, unsigned gpio,
+ int value)
+{
+ struct mvebu_gpio_priv *priv = dev_get_priv(dev);
+ struct mvebu_gpio_regs *regs = priv->regs;
+
+ if (value)
+ setbits_le32(®s->data_out, BIT(gpio));
+ else
+ clrbits_le32(®s->data_out, BIT(gpio));
+
+ return 0;
+}
+
+static int mvebu_gpio_get_value(struct udevice *dev, unsigned gpio)
+{
+ struct mvebu_gpio_priv *priv = dev_get_priv(dev);
+ struct mvebu_gpio_regs *regs = priv->regs;
+
+ return !!(readl(®s->data_in) & BIT(gpio));
+}
+
+static int mvebu_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct mvebu_gpio_priv *priv = dev_get_priv(dev);
+
+ priv->regs = (struct mvebu_gpio_regs *)dev_get_addr(dev);
+ uc_priv->gpio_count = MVEBU_GPIOS_PER_BANK;
+ priv->name[0] = 'A' + dev->req_seq;
+ uc_priv->bank_name = priv->name;
+
+ return 0;
+}
+
+static const struct dm_gpio_ops mvebu_gpio_ops = {
+ .direction_input = mvebu_gpio_direction_input,
+ .direction_output = mvebu_gpio_direction_output,
+ .get_function = mvebu_gpio_get_function,
+ .get_value = mvebu_gpio_get_value,
+ .set_value = mvebu_gpio_set_value,
+};
+
+static const struct udevice_id mvebu_gpio_ids[] = {
+ { .compatible = "marvell,orion-gpio" },
+ { }
+};
+
+U_BOOT_DRIVER(gpio_mvebu) = {
+ .name = "gpio_mvebu",
+ .id = UCLASS_GPIO,
+ .of_match = mvebu_gpio_ids,
+ .ops = &mvebu_gpio_ops,
+ .probe = mvebu_gpio_probe,
+ .priv_auto_alloc_size = sizeof(struct mvebu_gpio_priv),
+};
--- /dev/null
+/*
+ * Qualcomm pm8916 pmic gpio driver - part of Qualcomm PM8916 PMIC
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <power/pmic.h>
+#include <spmi/spmi.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/bitops.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Register offset for each gpio */
+#define REG_OFFSET(x) ((x) * 0x100)
+
+/* Register maps */
+
+/* Type and subtype are shared for all pm8916 peripherals */
+#define REG_TYPE 0x4
+#define REG_SUBTYPE 0x5
+
+#define REG_STATUS 0x08
+#define REG_STATUS_VAL_MASK 0x1
+
+/* MODE_CTL */
+#define REG_CTL 0x40
+#define REG_CTL_MODE_MASK 0x70
+#define REG_CTL_MODE_INPUT 0x00
+#define REG_CTL_MODE_INOUT 0x20
+#define REG_CTL_MODE_OUTPUT 0x10
+#define REG_CTL_OUTPUT_MASK 0x0F
+
+#define REG_DIG_VIN_CTL 0x41
+#define REG_DIG_VIN_VIN0 0
+
+#define REG_DIG_PULL_CTL 0x42
+#define REG_DIG_PULL_NO_PU 0x5
+
+#define REG_DIG_OUT_CTL 0x45
+#define REG_DIG_OUT_CTL_CMOS (0x0 << 4)
+#define REG_DIG_OUT_CTL_DRIVE_L 0x1
+
+#define REG_EN_CTL 0x46
+#define REG_EN_CTL_ENABLE (1 << 7)
+
+struct pm8916_gpio_bank {
+ uint16_t pid; /* Peripheral ID on SPMI bus */
+};
+
+static int pm8916_gpio_set_direction(struct udevice *dev, unsigned offset,
+ bool input, int value)
+{
+ struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+ uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
+ int ret;
+
+ /* Disable the GPIO */
+ ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
+ REG_EN_CTL_ENABLE, 0);
+ if (ret < 0)
+ return ret;
+
+ /* Select the mode */
+ if (input)
+ ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL,
+ REG_CTL_MODE_INPUT);
+ else
+ ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL,
+ REG_CTL_MODE_INOUT | (value ? 1 : 0));
+ if (ret < 0)
+ return ret;
+
+ /* Set the right pull (no pull) */
+ ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_PULL_CTL,
+ REG_DIG_PULL_NO_PU);
+ if (ret < 0)
+ return ret;
+
+ /* Configure output pin drivers if needed */
+ if (!input) {
+ /* Select the VIN - VIN0, pin is input so it doesn't matter */
+ ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_VIN_CTL,
+ REG_DIG_VIN_VIN0);
+ if (ret < 0)
+ return ret;
+
+ /* Set the right dig out control */
+ ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_OUT_CTL,
+ REG_DIG_OUT_CTL_CMOS |
+ REG_DIG_OUT_CTL_DRIVE_L);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Enable the GPIO */
+ return pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, 0,
+ REG_EN_CTL_ENABLE);
+}
+
+static int pm8916_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+ return pm8916_gpio_set_direction(dev, offset, true, 0);
+}
+
+static int pm8916_gpio_direction_output(struct udevice *dev, unsigned offset,
+ int value)
+{
+ return pm8916_gpio_set_direction(dev, offset, false, value);
+}
+
+static int pm8916_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+ uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
+ int reg;
+
+ /* Set the output value of the gpio */
+ reg = pmic_reg_read(dev->parent, gpio_base + REG_CTL);
+ if (reg < 0)
+ return reg;
+
+ switch (reg & REG_CTL_MODE_MASK) {
+ case REG_CTL_MODE_INPUT:
+ return GPIOF_INPUT;
+ case REG_CTL_MODE_INOUT: /* Fallthrough */
+ case REG_CTL_MODE_OUTPUT:
+ return GPIOF_OUTPUT;
+ default:
+ return GPIOF_UNKNOWN;
+ }
+}
+
+static int pm8916_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+ struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+ uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
+ int reg;
+
+ reg = pmic_reg_read(dev->parent, gpio_base + REG_STATUS);
+ if (reg < 0)
+ return reg;
+
+ return !!(reg & REG_STATUS_VAL_MASK);
+}
+
+static int pm8916_gpio_set_value(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+ uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
+
+ /* Set the output value of the gpio */
+ return pmic_clrsetbits(dev->parent, gpio_base + REG_CTL,
+ REG_CTL_OUTPUT_MASK, !!value);
+}
+
+static const struct dm_gpio_ops pm8916_gpio_ops = {
+ .direction_input = pm8916_gpio_direction_input,
+ .direction_output = pm8916_gpio_direction_output,
+ .get_value = pm8916_gpio_get_value,
+ .set_value = pm8916_gpio_set_value,
+ .get_function = pm8916_gpio_get_function,
+};
+
+static int pm8916_gpio_probe(struct udevice *dev)
+{
+ struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+ int reg;
+
+ priv->pid = dev_get_addr(dev);
+ if (priv->pid == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ /* Do a sanity check */
+ reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
+ if (reg != 0x10)
+ return -ENODEV;
+
+ reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
+ if (reg != 0x5)
+ return -ENODEV;
+
+ return 0;
+}
+
+static int pm8916_gpio_ofdata_to_platdata(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "gpio-count", 0);
+ uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ "gpio-bank-name", NULL);
+ if (uc_priv->bank_name == NULL)
+ uc_priv->bank_name = "pm8916";
+
+ return 0;
+}
+
+static const struct udevice_id pm8916_gpio_ids[] = {
+ { .compatible = "qcom,pm8916-gpio" },
+ { }
+};
+
+U_BOOT_DRIVER(gpio_pm8916) = {
+ .name = "gpio_pm8916",
+ .id = UCLASS_GPIO,
+ .of_match = pm8916_gpio_ids,
+ .ofdata_to_platdata = pm8916_gpio_ofdata_to_platdata,
+ .probe = pm8916_gpio_probe,
+ .ops = &pm8916_gpio_ops,
+ .priv_auto_alloc_size = sizeof(struct pm8916_gpio_bank),
+};
+
+
+/* Add pmic buttons as GPIO as well - there is no generic way for now */
+#define PON_INT_RT_STS 0x10
+#define KPDPWR_ON_INT_BIT 0
+#define RESIN_ON_INT_BIT 1
+
+static int pm8941_pwrkey_get_function(struct udevice *dev, unsigned offset)
+{
+ return GPIOF_INPUT;
+}
+
+static int pm8941_pwrkey_get_value(struct udevice *dev, unsigned offset)
+{
+ struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+
+ int reg = pmic_reg_read(dev->parent, priv->pid + PON_INT_RT_STS);
+
+ if (reg < 0)
+ return 0;
+
+ switch (offset) {
+ case 0: /* Power button */
+ return (reg & BIT(KPDPWR_ON_INT_BIT)) != 0;
+ break;
+ case 1: /* Reset button */
+ default:
+ return (reg & BIT(RESIN_ON_INT_BIT)) != 0;
+ break;
+ }
+}
+
+static const struct dm_gpio_ops pm8941_pwrkey_ops = {
+ .get_value = pm8941_pwrkey_get_value,
+ .get_function = pm8941_pwrkey_get_function,
+};
+
+static int pm8941_pwrkey_probe(struct udevice *dev)
+{
+ struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+ int reg;
+
+ priv->pid = dev_get_addr(dev);
+ if (priv->pid == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ /* Do a sanity check */
+ reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
+ if (reg != 0x1)
+ return -ENODEV;
+
+ reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
+ if (reg != 0x1)
+ return -ENODEV;
+
+ return 0;
+}
+
+static int pm8941_pwrkey_ofdata_to_platdata(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ uc_priv->gpio_count = 2;
+ if (uc_priv->bank_name == NULL)
+ uc_priv->bank_name = "pm8916_key";
+
+ return 0;
+}
+
+static const struct udevice_id pm8941_pwrkey_ids[] = {
+ { .compatible = "qcom,pm8916-pwrkey" },
+ { }
+};
+
+U_BOOT_DRIVER(pwrkey_pm8941) = {
+ .name = "pwrkey_pm8916",
+ .id = UCLASS_GPIO,
+ .of_match = pm8941_pwrkey_ids,
+ .ofdata_to_platdata = pm8941_pwrkey_ofdata_to_platdata,
+ .probe = pm8941_pwrkey_probe,
+ .ops = &pm8941_pwrkey_ops,
+ .priv_auto_alloc_size = sizeof(struct pm8916_gpio_bank),
+};
start = 'L' - 'A';
no_banks = 2; /* L & M */
} else if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
- "allwinner,sun8i-a23-r-pinctrl") == 0) {
+ "allwinner,sun8i-a23-r-pinctrl") == 0 ||
+ fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
+ "allwinner,sun8i-a83t-r-pinctrl") == 0 ||
+ fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
+ "allwinner,sun8i-h3-r-pinctrl") == 0) {
start = 'L' - 'A';
no_banks = 1; /* L only */
+ } else if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
+ "allwinner,sun9i-a80-r-pinctrl") == 0) {
+ start = 'L' - 'A';
+ no_banks = 3; /* L, M & N */
} else {
start = 0;
no_banks = SUNXI_GPIO_BANKS;
{ .compatible = "allwinner,sun7i-a20-pinctrl" },
{ .compatible = "allwinner,sun8i-a23-pinctrl" },
{ .compatible = "allwinner,sun8i-a33-pinctrl" },
+ { .compatible = "allwinner,sun8i-a83t-pinctrl", },
+ { .compatible = "allwinner,sun8i-h3-pinctrl" },
{ .compatible = "allwinner,sun9i-a80-pinctrl" },
{ .compatible = "allwinner,sun6i-a31-r-pinctrl" },
{ .compatible = "allwinner,sun8i-a23-r-pinctrl" },
+ { .compatible = "allwinner,sun8i-a83t-r-pinctrl" },
+ { .compatible = "allwinner,sun8i-h3-r-pinctrl", },
+ { .compatible = "allwinner,sun9i-a80-r-pinctrl", },
{ }
};
#include <common.h>
#include <linux/types.h>
#include <linux/io.h>
+#include <linux/sizes.h>
#include <asm/errno.h>
#include <dm/device.h>
#include <dm/root.h>
#include <fdtdec.h>
#include <mapmem.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct uniphier_fi2c_regs {
u32 cr; /* control register */
#define I2C_CR_MST (1 << 3) /* master mode */
static int uniphier_fi2c_probe(struct udevice *dev)
{
fdt_addr_t addr;
- fdt_size_t size;
struct uniphier_fi2c_dev *priv = dev_get_priv(dev);
int ret;
- addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg",
- &size);
-
- priv->regs = map_sysmem(addr, size);
+ addr = dev_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ priv->regs = map_sysmem(addr, SZ_128);
if (!priv->regs)
return -ENOMEM;
#include <common.h>
#include <linux/types.h>
#include <linux/io.h>
+#include <linux/sizes.h>
#include <asm/errno.h>
#include <dm/device.h>
#include <dm/root.h>
#include <fdtdec.h>
#include <mapmem.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct uniphier_i2c_regs {
u32 dtrm; /* data transmission */
#define I2C_DTRM_STA (1 << 10)
static int uniphier_i2c_probe(struct udevice *dev)
{
fdt_addr_t addr;
- fdt_size_t size;
struct uniphier_i2c_dev *priv = dev_get_priv(dev);
- addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
-
- priv->regs = map_sysmem(addr, size);
+ addr = dev_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ priv->regs = map_sysmem(addr, SZ_64);
if (!priv->regs)
return -ENOMEM;
#include <i2c.h>
#include <watchdog.h>
#include <dm.h>
+#include <dm/pinctrl.h>
#include <fdtdec.h>
DECLARE_GLOBAL_DATA_PTR;
}
#else
/*
- * Since pinmux is not supported, implement a weak function here.
- * You can implement your i2c_bus_idle in board file. When pinctrl
- * is supported, this can be removed.
+ * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
+ * "
+ * scl-gpios: specify the gpio related to SCL pin
+ * sda-gpios: specify the gpio related to SDA pin
+ * add pinctrl to configure i2c pins to gpio function for i2c
+ * bus recovery, call it "gpio" state
+ * "
+ *
+ * The i2c_idle_bus is an implementation following Linux Kernel.
*/
-int __i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
+int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
{
- return 0;
-}
+ struct udevice *bus = i2c_bus->bus;
+ struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
+ struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
+ int sda, scl;
+ int i, ret = 0;
+ ulong elapsed, start_time;
-int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
- __attribute__((weak, alias("__i2c_idle_bus")));
+ if (pinctrl_select_state(bus, "gpio")) {
+ dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
+ /*
+ * GPIO pinctrl for i2c force idle is not a must,
+ * but it is strongly recommended to be used.
+ * Because it can help you to recover from bad
+ * i2c bus state. Do not return failure, because
+ * it is not a must.
+ */
+ return 0;
+ }
+
+ dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
+ dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
+ scl = dm_gpio_get_value(scl_gpio);
+ sda = dm_gpio_get_value(sda_gpio);
+
+ if ((sda & scl) == 1)
+ goto exit; /* Bus is idle already */
+
+ /* Send high and low on the SCL line */
+ for (i = 0; i < 9; i++) {
+ dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
+ dm_gpio_set_value(scl_gpio, 0);
+ udelay(50);
+ dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
+ udelay(50);
+ }
+ start_time = get_timer(0);
+ for (;;) {
+ dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
+ dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
+ scl = dm_gpio_get_value(scl_gpio);
+ sda = dm_gpio_get_value(sda_gpio);
+ if ((sda & scl) == 1)
+ break;
+ WATCHDOG_RESET();
+ elapsed = get_timer(start_time);
+ if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
+ ret = -EBUSY;
+ printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
+ break;
+ }
+ }
+
+exit:
+ pinctrl_select_state(bus, "default");
+ return ret;
+}
#endif
static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
static int mxc_i2c_probe(struct udevice *bus)
{
struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
+ const void *fdt = gd->fdt_blob;
+ int node = bus->of_offset;
fdt_addr_t addr;
- int ret;
+ int ret, ret2;
i2c_bus->driver_data = dev_get_driver_data(bus);
i2c_bus->base = addr;
i2c_bus->index = bus->seq;
+ i2c_bus->bus = bus;
/* Enable clk */
ret = enable_i2c_clk(1, bus->seq);
if (ret < 0)
return ret;
+ /*
+ * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
+ * Use gpio to force bus idle when necessary.
+ */
+ ret = fdt_find_string(fdt, node, "pinctrl-names", "gpio");
+ if (ret < 0) {
+ dev_info(dev, "i2c bus %d at %lu, no gpio pinctrl state.\n", bus->seq, i2c_bus->base);
+ } else {
+ ret = gpio_request_by_name_nodev(fdt, node, "scl-gpios",
+ 0, &i2c_bus->scl_gpio,
+ GPIOD_IS_OUT);
+ ret2 = gpio_request_by_name_nodev(fdt, node, "sda-gpios",
+ 0, &i2c_bus->sda_gpio,
+ GPIOD_IS_OUT);
+ if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) |
+ !dm_gpio_is_valid(&i2c_bus->scl_gpio) |
+ ret | ret2) {
+ dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base);
+ return -ENODEV;
+ }
+ }
+
ret = i2c_idle_bus(i2c_bus);
if (ret < 0) {
/* Disable clk */
return 1;
}
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
+ /*
+ * EEPROM chips that implement "address overflow" are ones
+ * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+ * address and the extra bits end up in the "chip address"
+ * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+ * four 256 byte chips.
+ *
+ * Note that we consider the length of the address field to
+ * still be one byte because the extra address bits are
+ * hidden in the chip address.
+ */
+ if (alen > 0)
+ chip |= ((addr >> (alen * 8)) &
+ CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+#endif
+
/* Wait until bus not busy */
if (wait_for_bb(adap))
return 1;
return 1;
}
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
+ /*
+ * EEPROM chips that implement "address overflow" are ones
+ * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+ * address and the extra bits end up in the "chip address"
+ * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+ * four 256 byte chips.
+ *
+ * Note that we consider the length of the address field to
+ * still be one byte because the extra address bits are
+ * hidden in the chip address.
+ */
+ if (alen > 0)
+ chip |= ((addr >> (alen * 8)) &
+ CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+#endif
+
/* Wait until bus not busy */
if (wait_for_bb(adap))
return 1;
appear as block devices in U-Boot and can support filesystems such
as EXT4 and FAT.
+config MSM_SDHCI
+ bool "Qualcomm SDHCI controller"
+ depends on DM_MMC
+ help
+ Enables support for SDHCI 2.0 controller present on some Qualcomm
+ Snapdragon devices. This device is compatible with eMMC v4.5 and
+ SD 3.0 specifications. Both SD and eMMC devices are supported.
+ Card-detect gpios are not supported.
+
config ROCKCHIP_DWMMC
bool "Rockchip SD/MMC controller support"
depends on DM_MMC && OF_CONTROL
obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
endif
obj-$(CONFIG_PIC32_SDHCI) += pic32_sdhci.o
+obj-$(CONFIG_MSM_SDHCI) += msm_sdhci.o
host = &bcm_host->host;
host->name = "bcm2835_sdhci";
- host->ioaddr = (void *)regbase;
+ host->ioaddr = (void *)(unsigned long)regbase;
host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B |
SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT;
host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
#include <fsl_esdhc.h>
#include <fdt_support.h>
#include <asm/io.h>
+#include <dm.h>
+#include <asm-generic/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
uint scr; /* eSDHC control register */
};
+/**
+ * struct fsl_esdhc_priv
+ *
+ * @esdhc_regs: registers of the sdhc controller
+ * @sdhc_clk: Current clk of the sdhc controller
+ * @bus_width: bus width, 1bit, 4bit or 8bit
+ * @cfg: mmc config
+ * @mmc: mmc
+ * Following is used when Driver Model is enabled for MMC
+ * @dev: pointer for the device
+ * @non_removable: 0: removable; 1: non-removable
+ * @cd_gpio: gpio for card detection
+ */
+struct fsl_esdhc_priv {
+ struct fsl_esdhc *esdhc_regs;
+ unsigned int sdhc_clk;
+ unsigned int bus_width;
+ struct mmc_config cfg;
+ struct mmc *mmc;
+ struct udevice *dev;
+ int non_removable;
+ struct gpio_desc cd_gpio;
+};
+
/* Return the XFERTYP flags for a given command and data packet */
static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
{
static void
esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
{
- struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_priv *priv = mmc->priv;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
uint blocks;
char *buffer;
uint databuf;
static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
{
int timeout;
- struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_priv *priv = mmc->priv;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
#ifdef CONFIG_FSL_LAYERSCAPE
dma_addr_t addr;
#endif
int err = 0;
uint xfertyp;
uint irqstat;
- struct fsl_esdhc_cfg *cfg = mmc->priv;
- volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_priv *priv = mmc->priv;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
static void set_sysctl(struct mmc *mmc, uint clock)
{
int div, pre_div;
- struct fsl_esdhc_cfg *cfg = mmc->priv;
- volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
- int sdhc_clk = cfg->sdhc_clk;
+ struct fsl_esdhc_priv *priv = mmc->priv;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ int sdhc_clk = priv->sdhc_clk;
uint clk;
if (clock < mmc->cfg->f_min)
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
static void esdhc_clock_control(struct mmc *mmc, bool enable)
{
- struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_priv *priv = mmc->priv;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
u32 value;
u32 time_out;
static void esdhc_set_ios(struct mmc *mmc)
{
- struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_priv *priv = mmc->priv;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
/* Select to use peripheral clock */
static int esdhc_init(struct mmc *mmc)
{
- struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_priv *priv = mmc->priv;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
int timeout = 1000;
/* Reset the entire host controller */
static int esdhc_getcd(struct mmc *mmc)
{
- struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_priv *priv = mmc->priv;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
int timeout = 1000;
#ifdef CONFIG_ESDHC_DETECT_QUIRK
if (CONFIG_ESDHC_DETECT_QUIRK)
return 1;
#endif
+
+#ifdef CONFIG_DM_MMC
+ if (priv->non_removable)
+ return 1;
+
+ if (dm_gpio_is_valid(&priv->cd_gpio))
+ return dm_gpio_get_value(&priv->cd_gpio);
+#endif
+
while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
udelay(1000);
.getcd = esdhc_getcd,
};
-int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
+static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
+ struct fsl_esdhc_priv *priv)
+{
+ if (!cfg || !priv)
+ return -EINVAL;
+
+ priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
+ priv->bus_width = cfg->max_bus_width;
+ priv->sdhc_clk = cfg->sdhc_clk;
+
+ return 0;
+};
+
+static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
{
struct fsl_esdhc *regs;
struct mmc *mmc;
u32 caps, voltage_caps;
- if (!cfg)
- return -1;
+ if (!priv)
+ return -EINVAL;
- regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ regs = priv->esdhc_regs;
/* First reset the eSDHC controller */
esdhc_reset(regs);
#endif
writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
- memset(&cfg->cfg, 0, sizeof(cfg->cfg));
+ memset(&priv->cfg, 0, sizeof(priv->cfg));
voltage_caps = 0;
caps = esdhc_read32(®s->hostcapblt);
if (caps & ESDHC_HOSTCAPBLT_VS33)
voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
- cfg->cfg.name = "FSL_SDHC";
- cfg->cfg.ops = &esdhc_ops;
+ priv->cfg.name = "FSL_SDHC";
+ priv->cfg.ops = &esdhc_ops;
#ifdef CONFIG_SYS_SD_VOLTAGE
- cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
+ priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
#else
- cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+ priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
#endif
- if ((cfg->cfg.voltages & voltage_caps) == 0) {
+ if ((priv->cfg.voltages & voltage_caps) == 0) {
printf("voltage not supported by controller\n");
return -1;
}
- cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+ if (priv->bus_width == 8)
+ priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+ else if (priv->bus_width == 4)
+ priv->cfg.host_caps = MMC_MODE_4BIT;
+
+ priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
- cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
+ priv->cfg.host_caps |= MMC_MODE_DDR_52MHz;
#endif
- if (cfg->max_bus_width > 0) {
- if (cfg->max_bus_width < 8)
- cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
- if (cfg->max_bus_width < 4)
- cfg->cfg.host_caps &= ~MMC_MODE_4BIT;
+ if (priv->bus_width > 0) {
+ if (priv->bus_width < 8)
+ priv->cfg.host_caps &= ~MMC_MODE_8BIT;
+ if (priv->bus_width < 4)
+ priv->cfg.host_caps &= ~MMC_MODE_4BIT;
}
if (caps & ESDHC_HOSTCAPBLT_HSS)
- cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+ priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
- cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
+ priv->cfg.host_caps &= ~MMC_MODE_8BIT;
#endif
- cfg->cfg.f_min = 400000;
- cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000);
+ priv->cfg.f_min = 400000;
+ priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000);
- cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+ priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
- mmc = mmc_create(&cfg->cfg, cfg);
+ mmc = mmc_create(&priv->cfg, priv);
if (mmc == NULL)
return -1;
+ priv->mmc = mmc;
+
+ return 0;
+}
+
+int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
+{
+ struct fsl_esdhc_priv *priv;
+ int ret;
+
+ if (!cfg)
+ return -EINVAL;
+
+ priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
+ if (!priv)
+ return -ENOMEM;
+
+ ret = fsl_esdhc_cfg_to_priv(cfg, priv);
+ if (ret) {
+ debug("%s xlate failure\n", __func__);
+ free(priv);
+ return ret;
+ }
+
+ ret = fsl_esdhc_init(priv);
+ if (ret) {
+ debug("%s init failure\n", __func__);
+ free(priv);
+ return ret;
+ }
+
return 0;
}
4 + 1, 1);
}
#endif
+
+#ifdef CONFIG_DM_MMC
+#include <asm/arch/clock.h>
+static int fsl_esdhc_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ const void *fdt = gd->fdt_blob;
+ int node = dev->of_offset;
+ fdt_addr_t addr;
+ unsigned int val;
+ int ret;
+
+ addr = dev_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->esdhc_regs = (struct fsl_esdhc *)addr;
+ priv->dev = dev;
+
+ val = fdtdec_get_int(fdt, node, "bus-width", -1);
+ if (val == 8)
+ priv->bus_width = 8;
+ else if (val == 4)
+ priv->bus_width = 4;
+ else
+ priv->bus_width = 1;
+
+ if (fdt_get_property(fdt, node, "non-removable", NULL)) {
+ priv->non_removable = 1;
+ } else {
+ priv->non_removable = 0;
+ gpio_request_by_name_nodev(fdt, node, "cd-gpios", 0,
+ &priv->cd_gpio, GPIOD_IS_IN);
+ }
+
+ /*
+ * TODO:
+ * Because lack of clk driver, if SDHC clk is not enabled,
+ * need to enable it first before this driver is invoked.
+ *
+ * we use MXC_ESDHC_CLK to get clk freq.
+ * If one would like to make this function work,
+ * the aliases should be provided in dts as this:
+ *
+ * aliases {
+ * mmc0 = &usdhc1;
+ * mmc1 = &usdhc2;
+ * mmc2 = &usdhc3;
+ * mmc3 = &usdhc4;
+ * };
+ * Then if your board only supports mmc2 and mmc3, but we can
+ * correctly get the seq as 2 and 3, then let mxc_get_clock
+ * work as expected.
+ */
+ priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
+ if (priv->sdhc_clk <= 0) {
+ dev_err(dev, "Unable to get clk for %s\n", dev->name);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_init(priv);
+ if (ret) {
+ dev_err(dev, "fsl_esdhc_init failure\n");
+ return ret;
+ }
+
+ upriv->mmc = priv->mmc;
+
+ return 0;
+}
+
+static const struct udevice_id fsl_esdhc_ids[] = {
+ { .compatible = "fsl,imx6ul-usdhc", },
+ { .compatible = "fsl,imx6sx-usdhc", },
+ { .compatible = "fsl,imx6sl-usdhc", },
+ { .compatible = "fsl,imx6q-usdhc", },
+ { .compatible = "fsl,imx7d-usdhc", },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(fsl_esdhc) = {
+ .name = "fsl-esdhc-mmc",
+ .id = UCLASS_MMC,
+ .of_match = fsl_esdhc_ids,
+ .probe = fsl_esdhc_probe,
+ .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
+};
+#endif
printf("CMD_SEND:%d\n", cmd->cmdidx);
printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
- switch (cmd->resp_type) {
+ if (ret) {
+ printf("\t\tRET\t\t\t %d\n", ret);
+ } else {
+ switch (cmd->resp_type) {
case MMC_RSP_NONE:
printf("\t\tMMC_RSP_NONE\n");
break;
default:
printf("\t\tERROR MMC rsp not supported\n");
break;
+ }
}
#else
ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
mmc->scr[1] = __be32_to_cpu(scr[1]);
switch ((mmc->scr[0] >> 24) & 0xf) {
- case 0:
- mmc->version = SD_VERSION_1_0;
- break;
- case 1:
- mmc->version = SD_VERSION_1_10;
- break;
- case 2:
- mmc->version = SD_VERSION_2;
- if ((mmc->scr[0] >> 15) & 0x1)
- mmc->version = SD_VERSION_3;
- break;
- default:
- mmc->version = SD_VERSION_1_0;
- break;
+ case 0:
+ mmc->version = SD_VERSION_1_0;
+ break;
+ case 1:
+ mmc->version = SD_VERSION_1_10;
+ break;
+ case 2:
+ mmc->version = SD_VERSION_2;
+ if ((mmc->scr[0] >> 15) & 0x1)
+ mmc->version = SD_VERSION_3;
+ break;
+ default:
+ mmc->version = SD_VERSION_1_0;
+ break;
}
if (mmc->scr[0] & SD_DATA_4BIT)
int version = (cmd.response[0] >> 26) & 0xf;
switch (version) {
- case 0:
- mmc->version = MMC_VERSION_1_2;
- break;
- case 1:
- mmc->version = MMC_VERSION_1_4;
- break;
- case 2:
- mmc->version = MMC_VERSION_2_2;
- break;
- case 3:
- mmc->version = MMC_VERSION_3;
- break;
- case 4:
- mmc->version = MMC_VERSION_4;
- break;
- default:
- mmc->version = MMC_VERSION_1_2;
- break;
+ case 0:
+ mmc->version = MMC_VERSION_1_2;
+ break;
+ case 1:
+ mmc->version = MMC_VERSION_1_4;
+ break;
+ case 2:
+ mmc->version = MMC_VERSION_2_2;
+ break;
+ case 3:
+ mmc->version = MMC_VERSION_3;
+ break;
+ case 4:
+ mmc->version = MMC_VERSION_4;
+ break;
+ default:
+ mmc->version = MMC_VERSION_1_2;
+ break;
}
}
--- /dev/null
+/*
+ * Qualcomm SDHCI driver - SD/eMMC controller
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * Based on Linux driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <sdhci.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+
+/* Non-standard registers needed for SDHCI startup */
+#define SDCC_MCI_POWER 0x0
+#define SDCC_MCI_POWER_SW_RST BIT(7)
+
+/* This is undocumented register */
+#define SDCC_MCI_VERSION 0x50
+#define SDCC_MCI_VERSION_MAJOR_SHIFT 28
+#define SDCC_MCI_VERSION_MAJOR_MASK (0xf << SDCC_MCI_VERSION_MAJOR_SHIFT)
+#define SDCC_MCI_VERSION_MINOR_MASK 0xff
+
+#define SDCC_MCI_STATUS2 0x6C
+#define SDCC_MCI_STATUS2_MCI_ACT 0x1
+#define SDCC_MCI_HC_MODE 0x78
+
+/* Offset to SDHCI registers */
+#define SDCC_SDHCI_OFFSET 0x900
+
+/* Non standard (?) SDHCI register */
+#define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c
+
+struct msm_sdhc {
+ struct sdhci_host host;
+ void *base;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int msm_sdc_clk_init(struct udevice *dev)
+{
+ uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ "clock-frequency", 400000);
+ uint clkd[2]; /* clk_id and clk_no */
+ int clk_offset;
+ struct udevice *clk;
+ int ret;
+
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd,
+ 2);
+ if (ret)
+ return ret;
+
+ clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
+ if (clk_offset < 0)
+ return clk_offset;
+
+ ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk);
+ if (ret)
+ return ret;
+
+ ret = clk_set_periph_rate(clk, clkd[1], clk_rate);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int msm_sdc_probe(struct udevice *dev)
+{
+ struct msm_sdhc *prv = dev_get_priv(dev);
+ struct sdhci_host *host = &prv->host;
+ u32 core_version, core_minor, core_major;
+ int ret;
+
+ host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
+
+ /* Init clocks */
+ ret = msm_sdc_clk_init(dev);
+ if (ret)
+ return ret;
+
+ /* Reset the core and Enable SDHC mode */
+ writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST,
+ prv->base + SDCC_MCI_POWER);
+
+
+ /* Wait for reset to be written to register */
+ if (wait_for_bit(__func__, prv->base + SDCC_MCI_STATUS2,
+ SDCC_MCI_STATUS2_MCI_ACT, false, 10, false)) {
+ printf("msm_sdhci: reset request failed\n");
+ return -EIO;
+ }
+
+ /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
+ if (wait_for_bit(__func__, prv->base + SDCC_MCI_POWER,
+ SDCC_MCI_POWER_SW_RST, false, 2, false)) {
+ printf("msm_sdhci: stuck in reset\n");
+ return -ETIMEDOUT;
+ }
+
+ /* Enable host-controller mode */
+ writel(1, prv->base + SDCC_MCI_HC_MODE);
+
+ core_version = readl(prv->base + SDCC_MCI_VERSION);
+
+ core_major = (core_version & SDCC_MCI_VERSION_MAJOR_MASK);
+ core_major >>= SDCC_MCI_VERSION_MAJOR_SHIFT;
+
+ core_minor = core_version & SDCC_MCI_VERSION_MINOR_MASK;
+
+ /*
+ * Support for some capabilities is not advertised by newer
+ * controller versions and must be explicitly enabled.
+ */
+ if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
+ u32 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
+ caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
+ writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0);
+ }
+
+ /* Set host controller version */
+ host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+
+ /* automatically detect max and min speed */
+ return add_sdhci(host, 0, 0);
+}
+
+static int msm_sdc_remove(struct udevice *dev)
+{
+ struct msm_sdhc *priv = dev_get_priv(dev);
+
+ /* Disable host-controller mode */
+ writel(0, priv->base + SDCC_MCI_HC_MODE);
+
+ return 0;
+}
+
+static int msm_ofdata_to_platdata(struct udevice *dev)
+{
+ struct udevice *parent = dev->parent;
+ struct msm_sdhc *priv = dev_get_priv(dev);
+ struct sdhci_host *host = &priv->host;
+
+ host->name = strdup(dev->name);
+ host->ioaddr = (void *)dev_get_addr(dev);
+ host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "bus-width", 4);
+ host->index = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, "index", 0);
+ priv->base = (void *)fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
+ parent->of_offset,
+ dev->of_offset,
+ "reg", 1, NULL);
+ if (priv->base == (void *)FDT_ADDR_T_NONE ||
+ host->ioaddr == (void *)FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct udevice_id msm_mmc_ids[] = {
+ { .compatible = "qcom,sdhci-msm-v4" },
+ { }
+};
+
+U_BOOT_DRIVER(msm_sdc_drv) = {
+ .name = "msm_sdc",
+ .id = UCLASS_MMC,
+ .of_match = msm_mmc_ids,
+ .ofdata_to_platdata = msm_ofdata_to_platdata,
+ .probe = msm_sdc_probe,
+ .remove = msm_sdc_remove,
+ .priv_auto_alloc_size = sizeof(struct msm_sdhc),
+};
#include <common.h>
#include <asm/arch/clock_manager.h>
-#include <asm/arch/dwmmc.h>
#include <asm/arch/system_manager.h>
#include <dm.h>
#include <dwmmc.h>
cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
if (data) {
- if ((u32) data->dest & 0x3) {
+ if ((u32)(long)data->dest & 0x3) {
error = -1;
goto out;
}
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->host_caps = MMC_MODE_4BIT;
+#ifdef CONFIG_MACH_SUN50I
+ if (sdc_no == 2)
+ cfg->host_caps = MMC_MODE_8BIT;
+#endif
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
#include <dm/device.h>
#include <linux/compat.h>
#include <linux/io.h>
+#include <linux/sizes.h>
#include <asm/unaligned.h>
#include <asm/dma-mapping.h>
struct uniphier_sd_priv *priv = dev_get_priv(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
fdt_addr_t base;
- fdt_size_t size;
struct udevice *clk_dev;
int clk_id;
int ret;
priv->dev = dev;
- base = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
- priv->regbase = map_sysmem(base, size);
+ base = dev_get_addr(dev);
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regbase = map_sysmem(base, SZ_2K);
if (!priv->regbase)
return -ENOMEM;
obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
obj-$(CONFIG_ST_SMI) += st_smi.o
+obj-$(CONFIG_STM32_FLASH) += stm32_flash.o
flash_isset (info, sect_cnt,
FLASH_OFFSET_PROTECT,
FLASH_STATUS_PROTECT);
+ flash_write_cmd(info, sect_cnt, 0,
+ FLASH_CMD_RESET);
break;
case CFI_CMDSET_AMD_EXTENDED:
case CFI_CMDSET_AMD_STANDARD:
static void detect_max_banks(struct denali_nand_info *denali)
{
uint32_t features = readl(denali->flash_reg + FEATURES);
- denali->max_banks = 2 << (features & FEATURES__N_BANKS);
+ /*
+ * Read the revision register, so we can calculate the max_banks
+ * properly: the encoding changed from rev 5.0 to 5.1
+ */
+ u32 revision = MAKE_COMPARABLE_REVISION(
+ readl(denali->flash_reg + REVISION));
+ if (revision < REVISION_5_1)
+ denali->max_banks = 2 << (features & FEATURES__N_BANKS);
+ else
+ denali->max_banks = 1 << (features & FEATURES__N_BANKS);
}
static void detect_partition_feature(struct denali_nand_info *denali)
{
uint32_t mode;
const int page_count = 1;
- uint32_t addr = (uint32_t)denali->buf.dma_buf;
+ uint64_t addr = (unsigned long)denali->buf.dma_buf;
flush_dcache_range(addr, addr + sizeof(denali->buf.dma_buf));
index_addr(denali, mode, addr);
/* 3. set memory high address bits 64:32 */
- index_addr(denali, mode, 0);
+ index_addr(denali, mode, addr >> 32);
#else
mode = MODE_10 | BANK(denali->flash_bank);
index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
/* 2. set memory high address bits 23:8 */
- index_addr(denali, mode | ((addr >> 16) << 8), 0x2200);
+ index_addr(denali, mode | (((addr >> 16) & 0xffff) << 8), 0x2200);
/* 3. set memory low address bits 23:8 */
index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300);
#define REVISION 0x370
#define REVISION__VALUE 0xffff
+#define MAKE_COMPARABLE_REVISION(x) swab16((x) & REVISION__VALUE)
+#define REVISION_5_1 0x00000501
#define ONFI_DEVICE_FEATURES 0x380
#define ONFI_DEVICE_FEATURES__VALUE 0x003f
#include <common.h>
#include <asm/io.h>
#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
#include <nand.h>
/* NAND Flash Soc registers */
static struct kwnandf_registers *nf_reg =
(struct kwnandf_registers *)KW_NANDF_BASE;
+static u32 nand_mpp_backup[9] = { 0 };
+
/*
* hardware specific access to control-lines/bits
*/
void kw_nand_select_chip(struct mtd_info *mtd, int chip)
{
u32 data;
+ static const u32 nand_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ 0
+ };
+
+ if (chip >= 0)
+ kirkwood_mpp_conf(nand_config, nand_mpp_backup);
+ else
+ kirkwood_mpp_conf(nand_mpp_backup, NULL);
data = readl(&nf_reg->ctrl);
data |= NAND_ACTCEBOOT_BIT;
#include "pxa3xx_nand.h"
-/* Some U-Boot compatibility macros */
-#define writesl(a, d, s) __raw_writesl((unsigned long)a, d, s)
-#define readsl(a, d, s) __raw_readsl((unsigned long)a, d, s)
-#define writesw(a, d, s) __raw_writesw((unsigned long)a, d, s)
-#define readsw(a, d, s) __raw_readsw((unsigned long)a, d, s)
-#define writesb(a, d, s) __raw_writesb((unsigned long)a, d, s)
-#define readsb(a, d, s) __raw_readsb((unsigned long)a, d, s)
-
#define TIMEOUT_DRAIN_FIFO 5 /* in ms */
#define CHIP_DELAY_TIMEOUT 200
#define NAND_STOP_DELAY 40
--- /dev/null
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <kamil.lulko@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+#include "stm32_flash.h"
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+#define STM32_FLASH ((struct stm32_flash_regs *)FLASH_CNTL_BASE)
+
+void stm32_flash_latency_cfg(int latency)
+{
+ /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
+ writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
+ | FLASH_ACR_DCEN, &STM32_FLASH->acr);
+}
+
+static void stm32_flash_lock(u8 lock)
+{
+ if (lock) {
+ setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_LOCK);
+ } else {
+ writel(STM32_FLASH_KEY1, &STM32_FLASH->key);
+ writel(STM32_FLASH_KEY2, &STM32_FLASH->key);
+ }
+}
+
+unsigned long flash_init(void)
+{
+ unsigned long total_size = 0;
+ u8 i, j;
+
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+ flash_info[i].flash_id = FLASH_STM32;
+ flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 20);
+ flash_info[i].size = sect_sz_kb[0];
+ for (j = 1; j < CONFIG_SYS_MAX_FLASH_SECT; j++) {
+ flash_info[i].start[j] = flash_info[i].start[j - 1]
+ + (sect_sz_kb[j - 1]);
+ flash_info[i].size += sect_sz_kb[j];
+ }
+ total_size += flash_info[i].size;
+ }
+
+ return total_size;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ } else if (info->flash_id == FLASH_STM32) {
+ printf("stm32 Embedded Flash\n");
+ }
+
+ printf(" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf("\n");
+ return;
+}
+
+int flash_erase(flash_info_t *info, int first, int last)
+{
+ u8 bank = 0xFF;
+ int i;
+
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+ if (info == &flash_info[i]) {
+ bank = i;
+ break;
+ }
+ }
+ if (bank == 0xFF)
+ return -1;
+
+ stm32_flash_lock(0);
+
+ for (i = first; i <= last; i++) {
+ while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
+ ;
+
+ /* clear old sector number before writing a new one */
+ clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SNB_MASK);
+
+ if (bank == 0) {
+ setbits_le32(&STM32_FLASH->cr,
+ (i << STM32_FLASH_CR_SNB_OFFSET));
+ } else if (bank == 1) {
+ setbits_le32(&STM32_FLASH->cr,
+ ((0x10 | i) << STM32_FLASH_CR_SNB_OFFSET));
+ } else {
+ stm32_flash_lock(1);
+ return -1;
+ }
+ setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
+ setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_STRT);
+
+ while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
+ ;
+
+ clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
+ }
+
+ stm32_flash_lock(1);
+ return 0;
+}
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong i;
+
+ while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
+ ;
+
+ stm32_flash_lock(0);
+
+ setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG);
+ /* To make things simple use byte writes only */
+ for (i = 0; i < cnt; i++) {
+ *(uchar *)(addr + i) = src[i];
+ /* avoid re-ordering flash data write and busy status
+ * check as flash memory space attributes are generally Normal
+ */
+ mb();
+ while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
+ ;
+ }
+ clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG);
+ stm32_flash_lock(1);
+
+ return 0;
+}
--- /dev/null
+struct stm32_flash_regs {
+ u32 acr;
+ u32 key;
+ u32 optkeyr;
+ u32 sr;
+ u32 cr;
+ u32 optcr;
+ u32 optcr1;
+};
+
+#define STM32_FLASH_KEY1 0x45670123
+#define STM32_FLASH_KEY2 0xCDEF89AB
+
+#define STM32_FLASH_SR_BSY (1 << 16)
+
+#define STM32_FLASH_CR_PG (1 << 0)
+#define STM32_FLASH_CR_SER (1 << 1)
+#define STM32_FLASH_CR_STRT (1 << 16)
+#define STM32_FLASH_CR_LOCK (1 << 31)
+#define STM32_FLASH_CR_SNB_OFFSET 3
+#define STM32_FLASH_CR_SNB_MASK (15 << STM32_FLASH_CR_SNB_OFFSET)
+
+/* Flash ACR: Access control register */
+#define FLASH_ACR_WS(n) n
+#define FLASH_ACR_PRFTEN (1 << 8)
+#define FLASH_ACR_ICEN (1 << 9)
+#define FLASH_ACR_DCEN (1 << 10)
help
Enable Ethernet PHY (physical media interface) support.
+config RTL8211X_PHY_FORCE_MASTER
+ bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode"
+ depends on PHYLIB
+ help
+ Force master mode for 1000BASE-T on RTl8211x PHYs (except for RTL8211F).
+ This can work around link stability and data corruption issues on gigabit
+ links which can occur in slave mode on certain PHYs, e.g. on the
+ RTL8211C(L).
+
+ Please note that two directly connected devices (i.e. via crossover cable)
+ will not be able to establish a link between each other if they both force
+ master mode. Multiple devices forcing master mode when connected by a
+ network switch do not pose a problem as the switch configures its affected
+ ports into slave mode.
+
+ This option only affects gigabit links. If you must establish a direct
+ connection between two devices which both force master mode, try forcing
+ the link speed to 100MBit/s.
+
+ If unsure, say N.
+
menuconfig NETDEVICES
bool "Network device support"
depends on NET
100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to
provide the PHY (physical media interface).
+config MVPP2
+ bool "Marvell Armada 375 network interface support"
+ depends on ARMADA_375
+ select PHYLIB
+ help
+ This driver supports the network interface units in the
+ Marvell ARMADA 375 SoC.
+
config PCH_GBE
bool "Intel Platform Controller Hub EG20T GMAC driver"
depends on DM_ETH && DM_PCI
This MAC is present in Intel Platform Controller Hub EG20T. It
supports 10/100/1000 Mbps operation.
+config RTL8139
+ bool "Realtek 8139 series Ethernet controller driver"
+ help
+ This driver supports Realtek 8139 series fast ethernet family of
+ PCI chipsets/adapters.
+
+config RTL8169
+ bool "Realtek 8169 series Ethernet controller driver"
+ help
+ This driver supports Realtek 8169 series gigabit ethernet family of
+ PCI/PCIe chipsets/adapters.
+
config XILINX_AXIEMAC
depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
select PHYLIB
obj-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
obj-$(CONFIG_MVGBE) += mvgbe.o
obj-$(CONFIG_MVNETA) += mvneta.o
+obj-$(CONFIG_MVPP2) += mvpp2.o
obj-$(CONFIG_NATSEMI) += natsemi.o
obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
s->addr_cena = d->cena_bar;
s->addr_cinh = d->cinh_bar;
s->cena = (void *)valloc(CONFIG_SYS_PAGE_SIZE);
- memset((void *)s->cena, 0x00, CONFIG_SYS_PAGE_SIZE);
if (!s->cena) {
printf("Could not allocate page for cena shadow\n");
return -1;
}
+ memset((void *)s->cena, 0x00, CONFIG_SYS_PAGE_SIZE);
#ifdef QBMAN_CHECKING
/* We should never be asked to initialise for a portal that isn't in
}
#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+
+__weak bool soc_has_aiop(void)
+{
+ return false;
+}
+
static int load_mc_aiop_img(u64 aiop_fw_addr)
{
u64 mc_ram_addr = mc_get_dram_addr();
void *aiop_img;
#endif
+ /* Check if AIOP is available */
+ if (!soc_has_aiop())
+ return -ENODEV;
/*
* Load the MC AIOP image in the MC private DRAM block:
*/
err_get_swp_init:
dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
err_get_enable:
- free(dflt_dpio);
err_get_attr:
dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
err_create:
+ free(dflt_dpio);
err_malloc:
return err;
}
{
int err = 0;
- if (bd && get_mc_boot_status() == -1)
+ /* MC is not loaded intentionally, So return success. */
+ if (bd && get_mc_boot_status() != 0)
return 0;
if (bd && !get_mc_boot_status() && get_dpl_apply_status() == -1) {
aiop_fw_addr = simple_strtoull(argv[3], NULL,
16);
+ /* if SoC doesn't have AIOP, err = -ENODEV */
err = load_mc_aiop_img(aiop_fw_addr);
if (!err)
printf("fsl-mc: AIOP FW applied\n");
obj-y += ldpaa_wriop.o
obj-y += ldpaa_eth.o
obj-$(CONFIG_LS2080A) += ls2080a.o
-obj-$(CONFIG_LS2085A) += ls2080a.o
#include <linux/compat.h>
#include <fsl-mc/fsl_dpmac.h>
+#include <fsl-mc/ldpaa_wriop.h>
#include "ldpaa_eth.h"
-#undef CONFIG_PHYLIB
+#ifdef CONFIG_PHYLIB
static int init_phy(struct eth_device *dev)
{
- /*TODO for external PHY */
+ struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv;
+ struct phy_device *phydev = NULL;
+ struct mii_dev *bus;
- return 0;
+ bus = wriop_get_mdio(priv->dpmac_id);
+ if (bus == NULL)
+ return 0;
+
+ phydev = phy_connect(bus, wriop_get_phy_address(priv->dpmac_id),
+ dev, wriop_get_enet_if(priv->dpmac_id));
+ if (!phydev) {
+ printf("Failed to connect\n");
+ return -1;
+ }
+
+ priv->phydev = phydev;
+
+ return phy_config(phydev);
}
+#endif
#ifdef DEBUG
static void ldpaa_eth_get_dpni_counter(void)
#ifdef DEBUG
struct dpni_link_state link_state;
#endif
- int err;
+ int err = 0;
+ struct mii_dev *bus;
+ phy_interface_t enet_if;
if (net_dev->state == ETH_STATE_ACTIVE)
return 0;
printf("ERROR (DPL is deployed. No device available)\n");
return -ENODEV;
}
+
/* DPMAC initialization */
err = ldpaa_dpmac_setup(priv);
if (err < 0)
goto err_dpmac_setup;
+#ifdef CONFIG_PHYLIB
+ if (priv->phydev)
+ err = phy_startup(priv->phydev);
+ if (err) {
+ printf("%s: Could not initialize\n",
+ priv->phydev->dev->name);
+ goto err_dpamc_bind;
+ }
+#else
+ priv->phydev = (struct phy_device *)malloc(sizeof(struct phy_device));
+ memset(priv->phydev, 0, sizeof(struct phy_device));
+
+ priv->phydev->speed = SPEED_1000;
+ priv->phydev->link = 1;
+ priv->phydev->duplex = DUPLEX_FULL;
+#endif
+
+ bus = wriop_get_mdio(priv->dpmac_id);
+ enet_if = wriop_get_enet_if(priv->dpmac_id);
+ if ((bus == NULL) &&
+ (enet_if == PHY_INTERFACE_MODE_XGMII)) {
+ priv->phydev = (struct phy_device *)
+ malloc(sizeof(struct phy_device));
+ memset(priv->phydev, 0, sizeof(struct phy_device));
+
+ priv->phydev->speed = SPEED_10000;
+ priv->phydev->link = 1;
+ priv->phydev->duplex = DUPLEX_FULL;
+ }
+
+ if (!priv->phydev->link) {
+ printf("%s: No link.\n", priv->phydev->dev->name);
+ err = -1;
+ goto err_dpamc_bind;
+ }
+
/* DPMAC binding DPNI */
err = ldpaa_dpmac_bind(priv);
if (err)
return err;
}
-#ifdef CONFIG_PHYLIB
- /* TODO Check this path */
- err = phy_startup(priv->phydev);
- if (err) {
- printf("%s: Could not initialize\n", priv->phydev->dev->name);
- return err;
- }
-#else
- priv->phydev->speed = SPEED_1000;
- priv->phydev->link = 1;
- priv->phydev->duplex = DUPLEX_FULL;
-#endif
-
err = dpni_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
if (err < 0) {
printf("dpni_enable() failed\n");
return err;
}
- dpmac_link_state.rate = SPEED_1000;
- dpmac_link_state.options = DPMAC_LINK_OPT_AUTONEG;
- dpmac_link_state.up = 1;
+ dpmac_link_state.rate = priv->phydev->speed;
+
+ if (priv->phydev->autoneg == AUTONEG_DISABLE)
+ dpmac_link_state.options &= ~DPMAC_LINK_OPT_AUTONEG;
+ else
+ dpmac_link_state.options |= DPMAC_LINK_OPT_AUTONEG;
+
+ if (priv->phydev->duplex == DUPLEX_HALF)
+ dpmac_link_state.options |= DPMAC_LINK_OPT_HALF_DUPLEX;
+
+ dpmac_link_state.up = priv->phydev->link;
+
err = dpmac_set_link_state(dflt_mc_io, MC_CMD_NO_FLAGS,
priv->dpmac_handle, &dpmac_link_state);
if (err < 0) {
goto err_qdid;
}
- if (!priv->phydev->link)
- printf("%s: No link.\n", priv->phydev->dev->name);
-
- return priv->phydev->link ? 0 : -1;
+ return priv->phydev->link;
err_qdid:
err_rx_flow:
err_dpni_bind:
ldpaa_dpbp_free();
err_dpbp_setup:
-err_dpamc_bind:
dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
err_dpni_setup:
+err_dpamc_bind:
+ dpmac_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpmac_handle);
err_dpmac_setup:
return err;
}
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
int err = 0;
+#ifdef CONFIG_PHYLIB
+ struct mii_dev *bus = wriop_get_mdio(priv->dpmac_id);
+#endif
if ((net_dev->state == ETH_STATE_PASSIVE) ||
(net_dev->state == ETH_STATE_INIT))
printf("dpni_disable() failed\n");
#ifdef CONFIG_PHYLIB
- phy_shutdown(priv->phydev);
+ if (priv->phydev && bus != NULL)
+ phy_shutdown(priv->phydev);
+ else
+ free(priv->phydev);
#endif
ldpaa_dpbp_free();
net_dev->halt = ldpaa_eth_stop;
net_dev->send = ldpaa_eth_tx;
net_dev->recv = ldpaa_eth_pull_dequeue_rx;
-/*
- TODO: PHY MDIO information
- priv->bus = info->bus;
- priv->phyaddr = info->phy_addr;
- priv->enet_if = info->enet_if;
-*/
- if (init_phy(net_dev))
- return 0;
+#ifdef CONFIG_PHYLIB
+ err = init_phy(net_dev);
+ if (err < 0)
+ return err;
+#endif
err = eth_register(net_dev);
if (err < 0) {
--- /dev/null
+/*
+ * Driver for Marvell PPv2 network controller for Armada 375 SoC.
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Marcin Wojtas <mw@semihalf.com>
+ *
+ * U-Boot version:
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <net.h>
+#include <netdev.h>
+#include <config.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <phy.h>
+#include <miiphy.h>
+#include <watchdog.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/compat.h>
+#include <linux/mbus.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Some linux -> U-Boot compatibility stuff */
+#define netdev_err(dev, fmt, args...) \
+ printf(fmt, ##args)
+#define netdev_warn(dev, fmt, args...) \
+ printf(fmt, ##args)
+#define netdev_info(dev, fmt, args...) \
+ printf(fmt, ##args)
+#define netdev_dbg(dev, fmt, args...) \
+ printf(fmt, ##args)
+
+#define ETH_ALEN 6 /* Octets in one ethernet addr */
+
+#define __verify_pcpu_ptr(ptr) \
+do { \
+ const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
+ (void)__vpp_verify; \
+} while (0)
+
+#define VERIFY_PERCPU_PTR(__p) \
+({ \
+ __verify_pcpu_ptr(__p); \
+ (typeof(*(__p)) __kernel __force *)(__p); \
+})
+
+#define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
+#define smp_processor_id() 0
+#define num_present_cpus() 1
+#define for_each_present_cpu(cpu) \
+ for ((cpu) = 0; (cpu) < 1; (cpu)++)
+
+#define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
+
+#define CONFIG_NR_CPUS 1
+#define ETH_HLEN ETHER_HDR_SIZE /* Total octets in header */
+
+/* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
+#define WRAP (2 + ETH_HLEN + 4 + 32)
+#define MTU 1500
+#define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
+
+#define MVPP2_SMI_TIMEOUT 10000
+
+/* RX Fifo Registers */
+#define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
+#define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
+#define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
+#define MVPP2_RX_FIFO_INIT_REG 0x64
+
+/* RX DMA Top Registers */
+#define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
+#define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
+#define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
+#define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
+#define MVPP2_POOL_BUF_SIZE_OFFSET 5
+#define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
+#define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
+#define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
+#define MVPP2_RXQ_POOL_SHORT_OFFS 20
+#define MVPP2_RXQ_POOL_SHORT_MASK 0x700000
+#define MVPP2_RXQ_POOL_LONG_OFFS 24
+#define MVPP2_RXQ_POOL_LONG_MASK 0x7000000
+#define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
+#define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
+#define MVPP2_RXQ_DISABLE_MASK BIT(31)
+
+/* Parser Registers */
+#define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
+#define MVPP2_PRS_PORT_LU_MAX 0xf
+#define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
+#define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
+#define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
+#define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
+#define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
+#define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
+#define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
+#define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
+#define MVPP2_PRS_TCAM_IDX_REG 0x1100
+#define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
+#define MVPP2_PRS_TCAM_INV_MASK BIT(31)
+#define MVPP2_PRS_SRAM_IDX_REG 0x1200
+#define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
+#define MVPP2_PRS_TCAM_CTRL_REG 0x1230
+#define MVPP2_PRS_TCAM_EN_MASK BIT(0)
+
+/* Classifier Registers */
+#define MVPP2_CLS_MODE_REG 0x1800
+#define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
+#define MVPP2_CLS_PORT_WAY_REG 0x1810
+#define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
+#define MVPP2_CLS_LKP_INDEX_REG 0x1814
+#define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
+#define MVPP2_CLS_LKP_TBL_REG 0x1818
+#define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
+#define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
+#define MVPP2_CLS_FLOW_INDEX_REG 0x1820
+#define MVPP2_CLS_FLOW_TBL0_REG 0x1824
+#define MVPP2_CLS_FLOW_TBL1_REG 0x1828
+#define MVPP2_CLS_FLOW_TBL2_REG 0x182c
+#define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
+#define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
+#define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
+#define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
+#define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
+#define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
+
+/* Descriptor Manager Top Registers */
+#define MVPP2_RXQ_NUM_REG 0x2040
+#define MVPP2_RXQ_DESC_ADDR_REG 0x2044
+#define MVPP2_RXQ_DESC_SIZE_REG 0x2048
+#define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
+#define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
+#define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
+#define MVPP2_RXQ_NUM_NEW_OFFSET 16
+#define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
+#define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
+#define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
+#define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
+#define MVPP2_RXQ_THRESH_REG 0x204c
+#define MVPP2_OCCUPIED_THRESH_OFFSET 0
+#define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
+#define MVPP2_RXQ_INDEX_REG 0x2050
+#define MVPP2_TXQ_NUM_REG 0x2080
+#define MVPP2_TXQ_DESC_ADDR_REG 0x2084
+#define MVPP2_TXQ_DESC_SIZE_REG 0x2088
+#define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
+#define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
+#define MVPP2_TXQ_THRESH_REG 0x2094
+#define MVPP2_TRANSMITTED_THRESH_OFFSET 16
+#define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
+#define MVPP2_TXQ_INDEX_REG 0x2098
+#define MVPP2_TXQ_PREF_BUF_REG 0x209c
+#define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
+#define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
+#define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
+#define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
+#define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
+#define MVPP2_TXQ_PENDING_REG 0x20a0
+#define MVPP2_TXQ_PENDING_MASK 0x3fff
+#define MVPP2_TXQ_INT_STATUS_REG 0x20a4
+#define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
+#define MVPP2_TRANSMITTED_COUNT_OFFSET 16
+#define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
+#define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
+#define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
+#define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
+#define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
+#define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
+#define MVPP2_TXQ_RSVD_CLR_OFFSET 16
+#define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
+#define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
+#define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
+#define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
+#define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
+#define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
+
+/* MBUS bridge registers */
+#define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
+#define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
+#define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
+#define MVPP2_BASE_ADDR_ENABLE 0x4060
+
+/* Interrupt Cause and Mask registers */
+#define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
+#define MVPP2_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
+#define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
+#define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
+#define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
+#define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
+#define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
+#define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
+#define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
+#define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
+#define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
+#define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
+#define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
+#define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
+#define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
+#define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
+#define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
+#define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
+#define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
+#define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
+
+/* Buffer Manager registers */
+#define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
+#define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
+#define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
+#define MVPP2_BM_POOL_SIZE_MASK 0xfff0
+#define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
+#define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
+#define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
+#define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
+#define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
+#define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
+#define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
+#define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
+#define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
+#define MVPP2_BM_START_MASK BIT(0)
+#define MVPP2_BM_STOP_MASK BIT(1)
+#define MVPP2_BM_STATE_MASK BIT(4)
+#define MVPP2_BM_LOW_THRESH_OFFS 8
+#define MVPP2_BM_LOW_THRESH_MASK 0x7f00
+#define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
+ MVPP2_BM_LOW_THRESH_OFFS)
+#define MVPP2_BM_HIGH_THRESH_OFFS 16
+#define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
+#define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
+ MVPP2_BM_HIGH_THRESH_OFFS)
+#define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
+#define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
+#define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
+#define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
+#define MVPP2_BM_BPPE_FULL_MASK BIT(3)
+#define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
+#define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
+#define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
+#define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
+#define MVPP2_BM_VIRT_ALLOC_REG 0x6440
+#define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
+#define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
+#define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
+#define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
+#define MVPP2_BM_VIRT_RLS_REG 0x64c0
+#define MVPP2_BM_MC_RLS_REG 0x64c4
+#define MVPP2_BM_MC_ID_MASK 0xfff
+#define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
+
+/* TX Scheduler registers */
+#define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
+#define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
+#define MVPP2_TXP_SCHED_ENQ_MASK 0xff
+#define MVPP2_TXP_SCHED_DISQ_OFFSET 8
+#define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
+#define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
+#define MVPP2_TXP_SCHED_MTU_REG 0x801c
+#define MVPP2_TXP_MTU_MAX 0x7FFFF
+#define MVPP2_TXP_SCHED_REFILL_REG 0x8020
+#define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
+#define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
+#define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
+#define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
+#define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
+#define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
+#define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
+#define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
+#define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
+#define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
+#define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
+#define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
+#define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
+
+/* TX general registers */
+#define MVPP2_TX_SNOOP_REG 0x8800
+#define MVPP2_TX_PORT_FLUSH_REG 0x8810
+#define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
+
+/* LMS registers */
+#define MVPP2_SRC_ADDR_MIDDLE 0x24
+#define MVPP2_SRC_ADDR_HIGH 0x28
+#define MVPP2_PHY_AN_CFG0_REG 0x34
+#define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
+#define MVPP2_MIB_COUNTERS_BASE(port) (0x1000 + ((port) >> 1) * \
+ 0x400 + (port) * 0x400)
+#define MVPP2_MIB_LATE_COLLISION 0x7c
+#define MVPP2_ISR_SUM_MASK_REG 0x220c
+#define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
+#define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
+
+/* Per-port registers */
+#define MVPP2_GMAC_CTRL_0_REG 0x0
+#define MVPP2_GMAC_PORT_EN_MASK BIT(0)
+#define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
+#define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
+#define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
+#define MVPP2_GMAC_CTRL_1_REG 0x4
+#define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
+#define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
+#define MVPP2_GMAC_PCS_LB_EN_BIT 6
+#define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
+#define MVPP2_GMAC_SA_LOW_OFFS 7
+#define MVPP2_GMAC_CTRL_2_REG 0x8
+#define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
+#define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
+#define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
+#define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
+#define MVPP2_GMAC_AUTONEG_CONFIG 0xc
+#define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
+#define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
+#define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
+#define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
+#define MVPP2_GMAC_AN_SPEED_EN BIT(7)
+#define MVPP2_GMAC_FC_ADV_EN BIT(9)
+#define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
+#define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
+#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
+#define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
+#define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
+#define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
+ MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
+
+#define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
+
+/* Descriptor ring Macros */
+#define MVPP2_QUEUE_NEXT_DESC(q, index) \
+ (((index) < (q)->last_desc) ? ((index) + 1) : 0)
+
+/* SMI: 0xc0054 -> offset 0x54 to lms_base */
+#define MVPP2_SMI 0x0054
+#define MVPP2_PHY_REG_MASK 0x1f
+/* SMI register fields */
+#define MVPP2_SMI_DATA_OFFS 0 /* Data */
+#define MVPP2_SMI_DATA_MASK (0xffff << MVPP2_SMI_DATA_OFFS)
+#define MVPP2_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
+#define MVPP2_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
+#define MVPP2_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
+#define MVPP2_SMI_OPCODE_READ (1 << MVPP2_SMI_OPCODE_OFFS)
+#define MVPP2_SMI_READ_VALID (1 << 27) /* Read Valid */
+#define MVPP2_SMI_BUSY (1 << 28) /* Busy */
+
+#define MVPP2_PHY_ADDR_MASK 0x1f
+#define MVPP2_PHY_REG_MASK 0x1f
+
+/* Various constants */
+
+/* Coalescing */
+#define MVPP2_TXDONE_COAL_PKTS_THRESH 15
+#define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
+#define MVPP2_RX_COAL_PKTS 32
+#define MVPP2_RX_COAL_USEC 100
+
+/* The two bytes Marvell header. Either contains a special value used
+ * by Marvell switches when a specific hardware mode is enabled (not
+ * supported by this driver) or is filled automatically by zeroes on
+ * the RX side. Those two bytes being at the front of the Ethernet
+ * header, they allow to have the IP header aligned on a 4 bytes
+ * boundary automatically: the hardware skips those two bytes on its
+ * own.
+ */
+#define MVPP2_MH_SIZE 2
+#define MVPP2_ETH_TYPE_LEN 2
+#define MVPP2_PPPOE_HDR_SIZE 8
+#define MVPP2_VLAN_TAG_LEN 4
+
+/* Lbtd 802.3 type */
+#define MVPP2_IP_LBDT_TYPE 0xfffa
+
+#define MVPP2_CPU_D_CACHE_LINE_SIZE 32
+#define MVPP2_TX_CSUM_MAX_SIZE 9800
+
+/* Timeout constants */
+#define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
+#define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
+
+#define MVPP2_TX_MTU_MAX 0x7ffff
+
+/* Maximum number of T-CONTs of PON port */
+#define MVPP2_MAX_TCONT 16
+
+/* Maximum number of supported ports */
+#define MVPP2_MAX_PORTS 4
+
+/* Maximum number of TXQs used by single port */
+#define MVPP2_MAX_TXQ 8
+
+/* Maximum number of RXQs used by single port */
+#define MVPP2_MAX_RXQ 8
+
+/* Default number of TXQs in use */
+#define MVPP2_DEFAULT_TXQ 1
+
+/* Dfault number of RXQs in use */
+#define MVPP2_DEFAULT_RXQ 1
+#define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
+
+/* Total number of RXQs available to all ports */
+#define MVPP2_RXQ_TOTAL_NUM (MVPP2_MAX_PORTS * MVPP2_MAX_RXQ)
+
+/* Max number of Rx descriptors */
+#define MVPP2_MAX_RXD 16
+
+/* Max number of Tx descriptors */
+#define MVPP2_MAX_TXD 16
+
+/* Amount of Tx descriptors that can be reserved at once by CPU */
+#define MVPP2_CPU_DESC_CHUNK 64
+
+/* Max number of Tx descriptors in each aggregated queue */
+#define MVPP2_AGGR_TXQ_SIZE 256
+
+/* Descriptor aligned size */
+#define MVPP2_DESC_ALIGNED_SIZE 32
+
+/* Descriptor alignment mask */
+#define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
+
+/* RX FIFO constants */
+#define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000
+#define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80
+#define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
+
+/* RX buffer constants */
+#define MVPP2_SKB_SHINFO_SIZE \
+ 0
+
+#define MVPP2_RX_PKT_SIZE(mtu) \
+ ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
+ ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
+
+#define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
+#define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
+#define MVPP2_RX_MAX_PKT_SIZE(total_size) \
+ ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
+
+#define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
+
+/* IPv6 max L3 address size */
+#define MVPP2_MAX_L3_ADDR_SIZE 16
+
+/* Port flags */
+#define MVPP2_F_LOOPBACK BIT(0)
+
+/* Marvell tag types */
+enum mvpp2_tag_type {
+ MVPP2_TAG_TYPE_NONE = 0,
+ MVPP2_TAG_TYPE_MH = 1,
+ MVPP2_TAG_TYPE_DSA = 2,
+ MVPP2_TAG_TYPE_EDSA = 3,
+ MVPP2_TAG_TYPE_VLAN = 4,
+ MVPP2_TAG_TYPE_LAST = 5
+};
+
+/* Parser constants */
+#define MVPP2_PRS_TCAM_SRAM_SIZE 256
+#define MVPP2_PRS_TCAM_WORDS 6
+#define MVPP2_PRS_SRAM_WORDS 4
+#define MVPP2_PRS_FLOW_ID_SIZE 64
+#define MVPP2_PRS_FLOW_ID_MASK 0x3f
+#define MVPP2_PRS_TCAM_ENTRY_INVALID 1
+#define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
+#define MVPP2_PRS_IPV4_HEAD 0x40
+#define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
+#define MVPP2_PRS_IPV4_MC 0xe0
+#define MVPP2_PRS_IPV4_MC_MASK 0xf0
+#define MVPP2_PRS_IPV4_BC_MASK 0xff
+#define MVPP2_PRS_IPV4_IHL 0x5
+#define MVPP2_PRS_IPV4_IHL_MASK 0xf
+#define MVPP2_PRS_IPV6_MC 0xff
+#define MVPP2_PRS_IPV6_MC_MASK 0xff
+#define MVPP2_PRS_IPV6_HOP_MASK 0xff
+#define MVPP2_PRS_TCAM_PROTO_MASK 0xff
+#define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
+#define MVPP2_PRS_DBL_VLANS_MAX 100
+
+/* Tcam structure:
+ * - lookup ID - 4 bits
+ * - port ID - 1 byte
+ * - additional information - 1 byte
+ * - header data - 8 bytes
+ * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
+ */
+#define MVPP2_PRS_AI_BITS 8
+#define MVPP2_PRS_PORT_MASK 0xff
+#define MVPP2_PRS_LU_MASK 0xf
+#define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
+ (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
+#define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
+ (((offs) * 2) - ((offs) % 2) + 2)
+#define MVPP2_PRS_TCAM_AI_BYTE 16
+#define MVPP2_PRS_TCAM_PORT_BYTE 17
+#define MVPP2_PRS_TCAM_LU_BYTE 20
+#define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
+#define MVPP2_PRS_TCAM_INV_WORD 5
+/* Tcam entries ID */
+#define MVPP2_PE_DROP_ALL 0
+#define MVPP2_PE_FIRST_FREE_TID 1
+#define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
+#define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
+#define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
+#define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
+#define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
+#define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
+#define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
+#define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
+#define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
+#define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
+#define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
+#define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
+#define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
+#define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
+#define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
+#define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
+#define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
+#define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
+#define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
+#define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
+#define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
+#define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
+#define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
+#define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
+#define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
+
+/* Sram structure
+ * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
+ */
+#define MVPP2_PRS_SRAM_RI_OFFS 0
+#define MVPP2_PRS_SRAM_RI_WORD 0
+#define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
+#define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
+#define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
+#define MVPP2_PRS_SRAM_SHIFT_OFFS 64
+#define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
+#define MVPP2_PRS_SRAM_UDF_OFFS 73
+#define MVPP2_PRS_SRAM_UDF_BITS 8
+#define MVPP2_PRS_SRAM_UDF_MASK 0xff
+#define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
+#define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
+#define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
+#define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
+#define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
+#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
+#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
+#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
+#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
+#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
+#define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
+#define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
+#define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
+#define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
+#define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
+#define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
+#define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
+#define MVPP2_PRS_SRAM_AI_OFFS 90
+#define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
+#define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
+#define MVPP2_PRS_SRAM_AI_MASK 0xff
+#define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
+#define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
+#define MVPP2_PRS_SRAM_LU_DONE_BIT 110
+#define MVPP2_PRS_SRAM_LU_GEN_BIT 111
+
+/* Sram result info bits assignment */
+#define MVPP2_PRS_RI_MAC_ME_MASK 0x1
+#define MVPP2_PRS_RI_DSA_MASK 0x2
+#define MVPP2_PRS_RI_VLAN_MASK 0xc
+#define MVPP2_PRS_RI_VLAN_NONE ~(BIT(2) | BIT(3))
+#define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
+#define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
+#define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
+#define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
+#define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
+#define MVPP2_PRS_RI_L2_CAST_MASK 0x600
+#define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10))
+#define MVPP2_PRS_RI_L2_MCAST BIT(9)
+#define MVPP2_PRS_RI_L2_BCAST BIT(10)
+#define MVPP2_PRS_RI_PPPOE_MASK 0x800
+#define MVPP2_PRS_RI_L3_PROTO_MASK 0x7000
+#define MVPP2_PRS_RI_L3_UN ~(BIT(12) | BIT(13) | BIT(14))
+#define MVPP2_PRS_RI_L3_IP4 BIT(12)
+#define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
+#define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
+#define MVPP2_PRS_RI_L3_IP6 BIT(14)
+#define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
+#define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
+#define MVPP2_PRS_RI_L3_ADDR_MASK 0x18000
+#define MVPP2_PRS_RI_L3_UCAST ~(BIT(15) | BIT(16))
+#define MVPP2_PRS_RI_L3_MCAST BIT(15)
+#define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
+#define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
+#define MVPP2_PRS_RI_UDF3_MASK 0x300000
+#define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
+#define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
+#define MVPP2_PRS_RI_L4_TCP BIT(22)
+#define MVPP2_PRS_RI_L4_UDP BIT(23)
+#define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
+#define MVPP2_PRS_RI_UDF7_MASK 0x60000000
+#define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
+#define MVPP2_PRS_RI_DROP_MASK 0x80000000
+
+/* Sram additional info bits assignment */
+#define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
+#define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
+#define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
+#define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
+#define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
+#define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
+#define MVPP2_PRS_SINGLE_VLAN_AI 0
+#define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
+
+/* DSA/EDSA type */
+#define MVPP2_PRS_TAGGED true
+#define MVPP2_PRS_UNTAGGED false
+#define MVPP2_PRS_EDSA true
+#define MVPP2_PRS_DSA false
+
+/* MAC entries, shadow udf */
+enum mvpp2_prs_udf {
+ MVPP2_PRS_UDF_MAC_DEF,
+ MVPP2_PRS_UDF_MAC_RANGE,
+ MVPP2_PRS_UDF_L2_DEF,
+ MVPP2_PRS_UDF_L2_DEF_COPY,
+ MVPP2_PRS_UDF_L2_USER,
+};
+
+/* Lookup ID */
+enum mvpp2_prs_lookup {
+ MVPP2_PRS_LU_MH,
+ MVPP2_PRS_LU_MAC,
+ MVPP2_PRS_LU_DSA,
+ MVPP2_PRS_LU_VLAN,
+ MVPP2_PRS_LU_L2,
+ MVPP2_PRS_LU_PPPOE,
+ MVPP2_PRS_LU_IP4,
+ MVPP2_PRS_LU_IP6,
+ MVPP2_PRS_LU_FLOWS,
+ MVPP2_PRS_LU_LAST,
+};
+
+/* L3 cast enum */
+enum mvpp2_prs_l3_cast {
+ MVPP2_PRS_L3_UNI_CAST,
+ MVPP2_PRS_L3_MULTI_CAST,
+ MVPP2_PRS_L3_BROAD_CAST
+};
+
+/* Classifier constants */
+#define MVPP2_CLS_FLOWS_TBL_SIZE 512
+#define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
+#define MVPP2_CLS_LKP_TBL_SIZE 64
+
+/* BM constants */
+#define MVPP2_BM_POOLS_NUM 1
+#define MVPP2_BM_LONG_BUF_NUM 16
+#define MVPP2_BM_SHORT_BUF_NUM 16
+#define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
+#define MVPP2_BM_POOL_PTR_ALIGN 128
+#define MVPP2_BM_SWF_LONG_POOL(port) 0
+
+/* BM cookie (32 bits) definition */
+#define MVPP2_BM_COOKIE_POOL_OFFS 8
+#define MVPP2_BM_COOKIE_CPU_OFFS 24
+
+/* BM short pool packet size
+ * These value assure that for SWF the total number
+ * of bytes allocated for each buffer will be 512
+ */
+#define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
+
+enum mvpp2_bm_type {
+ MVPP2_BM_FREE,
+ MVPP2_BM_SWF_LONG,
+ MVPP2_BM_SWF_SHORT
+};
+
+/* Definitions */
+
+/* Shared Packet Processor resources */
+struct mvpp2 {
+ /* Shared registers' base addresses */
+ void __iomem *base;
+ void __iomem *lms_base;
+
+ /* List of pointers to port structures */
+ struct mvpp2_port **port_list;
+
+ /* Aggregated TXQs */
+ struct mvpp2_tx_queue *aggr_txqs;
+
+ /* BM pools */
+ struct mvpp2_bm_pool *bm_pools;
+
+ /* PRS shadow table */
+ struct mvpp2_prs_shadow *prs_shadow;
+ /* PRS auxiliary table for double vlan entries control */
+ bool *prs_double_vlans;
+
+ /* Tclk value */
+ u32 tclk;
+
+ struct mii_dev *bus;
+};
+
+struct mvpp2_pcpu_stats {
+ u64 rx_packets;
+ u64 rx_bytes;
+ u64 tx_packets;
+ u64 tx_bytes;
+};
+
+struct mvpp2_port {
+ u8 id;
+
+ int irq;
+
+ struct mvpp2 *priv;
+
+ /* Per-port registers' base address */
+ void __iomem *base;
+
+ struct mvpp2_rx_queue **rxqs;
+ struct mvpp2_tx_queue **txqs;
+
+ int pkt_size;
+
+ u32 pending_cause_rx;
+
+ /* Per-CPU port control */
+ struct mvpp2_port_pcpu __percpu *pcpu;
+
+ /* Flags */
+ unsigned long flags;
+
+ u16 tx_ring_size;
+ u16 rx_ring_size;
+ struct mvpp2_pcpu_stats __percpu *stats;
+
+ struct phy_device *phy_dev;
+ phy_interface_t phy_interface;
+ int phy_node;
+ int phyaddr;
+ int init;
+ unsigned int link;
+ unsigned int duplex;
+ unsigned int speed;
+
+ struct mvpp2_bm_pool *pool_long;
+ struct mvpp2_bm_pool *pool_short;
+
+ /* Index of first port's physical RXQ */
+ u8 first_rxq;
+
+ u8 dev_addr[ETH_ALEN];
+};
+
+/* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
+ * layout of the transmit and reception DMA descriptors, and their
+ * layout is therefore defined by the hardware design
+ */
+
+#define MVPP2_TXD_L3_OFF_SHIFT 0
+#define MVPP2_TXD_IP_HLEN_SHIFT 8
+#define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
+#define MVPP2_TXD_L4_CSUM_NOT BIT(14)
+#define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
+#define MVPP2_TXD_PADDING_DISABLE BIT(23)
+#define MVPP2_TXD_L4_UDP BIT(24)
+#define MVPP2_TXD_L3_IP6 BIT(26)
+#define MVPP2_TXD_L_DESC BIT(28)
+#define MVPP2_TXD_F_DESC BIT(29)
+
+#define MVPP2_RXD_ERR_SUMMARY BIT(15)
+#define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
+#define MVPP2_RXD_ERR_CRC 0x0
+#define MVPP2_RXD_ERR_OVERRUN BIT(13)
+#define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
+#define MVPP2_RXD_BM_POOL_ID_OFFS 16
+#define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
+#define MVPP2_RXD_HWF_SYNC BIT(21)
+#define MVPP2_RXD_L4_CSUM_OK BIT(22)
+#define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
+#define MVPP2_RXD_L4_TCP BIT(25)
+#define MVPP2_RXD_L4_UDP BIT(26)
+#define MVPP2_RXD_L3_IP4 BIT(28)
+#define MVPP2_RXD_L3_IP6 BIT(30)
+#define MVPP2_RXD_BUF_HDR BIT(31)
+
+struct mvpp2_tx_desc {
+ u32 command; /* Options used by HW for packet transmitting.*/
+ u8 packet_offset; /* the offset from the buffer beginning */
+ u8 phys_txq; /* destination queue ID */
+ u16 data_size; /* data size of transmitted packet in bytes */
+ u32 buf_phys_addr; /* physical addr of transmitted buffer */
+ u32 buf_cookie; /* cookie for access to TX buffer in tx path */
+ u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
+ u32 reserved2; /* reserved (for future use) */
+};
+
+struct mvpp2_rx_desc {
+ u32 status; /* info about received packet */
+ u16 reserved1; /* parser_info (for future use, PnC) */
+ u16 data_size; /* size of received packet in bytes */
+ u32 buf_phys_addr; /* physical address of the buffer */
+ u32 buf_cookie; /* cookie for access to RX buffer in rx path */
+ u16 reserved2; /* gem_port_id (for future use, PON) */
+ u16 reserved3; /* csum_l4 (for future use, PnC) */
+ u8 reserved4; /* bm_qset (for future use, BM) */
+ u8 reserved5;
+ u16 reserved6; /* classify_info (for future use, PnC) */
+ u32 reserved7; /* flow_id (for future use, PnC) */
+ u32 reserved8;
+};
+
+/* Per-CPU Tx queue control */
+struct mvpp2_txq_pcpu {
+ int cpu;
+
+ /* Number of Tx DMA descriptors in the descriptor ring */
+ int size;
+
+ /* Number of currently used Tx DMA descriptor in the
+ * descriptor ring
+ */
+ int count;
+
+ /* Number of Tx DMA descriptors reserved for each CPU */
+ int reserved_num;
+
+ /* Index of last TX DMA descriptor that was inserted */
+ int txq_put_index;
+
+ /* Index of the TX DMA descriptor to be cleaned up */
+ int txq_get_index;
+};
+
+struct mvpp2_tx_queue {
+ /* Physical number of this Tx queue */
+ u8 id;
+
+ /* Logical number of this Tx queue */
+ u8 log_id;
+
+ /* Number of Tx DMA descriptors in the descriptor ring */
+ int size;
+
+ /* Number of currently used Tx DMA descriptor in the descriptor ring */
+ int count;
+
+ /* Per-CPU control of physical Tx queues */
+ struct mvpp2_txq_pcpu __percpu *pcpu;
+
+ u32 done_pkts_coal;
+
+ /* Virtual address of thex Tx DMA descriptors array */
+ struct mvpp2_tx_desc *descs;
+
+ /* DMA address of the Tx DMA descriptors array */
+ dma_addr_t descs_phys;
+
+ /* Index of the last Tx DMA descriptor */
+ int last_desc;
+
+ /* Index of the next Tx DMA descriptor to process */
+ int next_desc_to_proc;
+};
+
+struct mvpp2_rx_queue {
+ /* RX queue number, in the range 0-31 for physical RXQs */
+ u8 id;
+
+ /* Num of rx descriptors in the rx descriptor ring */
+ int size;
+
+ u32 pkts_coal;
+ u32 time_coal;
+
+ /* Virtual address of the RX DMA descriptors array */
+ struct mvpp2_rx_desc *descs;
+
+ /* DMA address of the RX DMA descriptors array */
+ dma_addr_t descs_phys;
+
+ /* Index of the last RX DMA descriptor */
+ int last_desc;
+
+ /* Index of the next RX DMA descriptor to process */
+ int next_desc_to_proc;
+
+ /* ID of port to which physical RXQ is mapped */
+ int port;
+
+ /* Port's logic RXQ number to which physical RXQ is mapped */
+ int logic_rxq;
+};
+
+union mvpp2_prs_tcam_entry {
+ u32 word[MVPP2_PRS_TCAM_WORDS];
+ u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
+};
+
+union mvpp2_prs_sram_entry {
+ u32 word[MVPP2_PRS_SRAM_WORDS];
+ u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
+};
+
+struct mvpp2_prs_entry {
+ u32 index;
+ union mvpp2_prs_tcam_entry tcam;
+ union mvpp2_prs_sram_entry sram;
+};
+
+struct mvpp2_prs_shadow {
+ bool valid;
+ bool finish;
+
+ /* Lookup ID */
+ int lu;
+
+ /* User defined offset */
+ int udf;
+
+ /* Result info */
+ u32 ri;
+ u32 ri_mask;
+};
+
+struct mvpp2_cls_flow_entry {
+ u32 index;
+ u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
+};
+
+struct mvpp2_cls_lookup_entry {
+ u32 lkpid;
+ u32 way;
+ u32 data;
+};
+
+struct mvpp2_bm_pool {
+ /* Pool number in the range 0-7 */
+ int id;
+ enum mvpp2_bm_type type;
+
+ /* Buffer Pointers Pool External (BPPE) size */
+ int size;
+ /* Number of buffers for this pool */
+ int buf_num;
+ /* Pool buffer size */
+ int buf_size;
+ /* Packet size */
+ int pkt_size;
+
+ /* BPPE virtual base address */
+ u32 *virt_addr;
+ /* BPPE physical base address */
+ dma_addr_t phys_addr;
+
+ /* Ports using BM pool */
+ u32 port_map;
+
+ /* Occupied buffers indicator */
+ int in_use_thresh;
+};
+
+struct mvpp2_buff_hdr {
+ u32 next_buff_phys_addr;
+ u32 next_buff_virt_addr;
+ u16 byte_count;
+ u16 info;
+ u8 reserved1; /* bm_qset (for future use, BM) */
+};
+
+/* Buffer header info bits */
+#define MVPP2_B_HDR_INFO_MC_ID_MASK 0xfff
+#define MVPP2_B_HDR_INFO_MC_ID(info) ((info) & MVPP2_B_HDR_INFO_MC_ID_MASK)
+#define MVPP2_B_HDR_INFO_LAST_OFFS 12
+#define MVPP2_B_HDR_INFO_LAST_MASK BIT(12)
+#define MVPP2_B_HDR_INFO_IS_LAST(info) \
+ ((info & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS)
+
+/* Static declaractions */
+
+/* Number of RXQs used by single port */
+static int rxq_number = MVPP2_DEFAULT_RXQ;
+/* Number of TXQs used by single port */
+static int txq_number = MVPP2_DEFAULT_TXQ;
+
+#define MVPP2_DRIVER_NAME "mvpp2"
+#define MVPP2_DRIVER_VERSION "1.0"
+
+/*
+ * U-Boot internal data, mostly uncached buffers for descriptors and data
+ */
+struct buffer_location {
+ struct mvpp2_tx_desc *aggr_tx_descs;
+ struct mvpp2_tx_desc *tx_descs;
+ struct mvpp2_rx_desc *rx_descs;
+ u32 *bm_pool[MVPP2_BM_POOLS_NUM];
+ u32 *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
+ int first_rxq;
+};
+
+/*
+ * All 4 interfaces use the same global buffer, since only one interface
+ * can be enabled at once
+ */
+static struct buffer_location buffer_loc;
+
+/*
+ * Page table entries are set to 1MB, or multiples of 1MB
+ * (not < 1MB). driver uses less bd's so use 1MB bdspace.
+ */
+#define BD_SPACE (1 << 20)
+
+/* Utility/helper methods */
+
+static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
+{
+ writel(data, priv->base + offset);
+}
+
+static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
+{
+ return readl(priv->base + offset);
+}
+
+static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
+{
+ txq_pcpu->txq_get_index++;
+ if (txq_pcpu->txq_get_index == txq_pcpu->size)
+ txq_pcpu->txq_get_index = 0;
+}
+
+/* Get number of physical egress port */
+static inline int mvpp2_egress_port(struct mvpp2_port *port)
+{
+ return MVPP2_MAX_TCONT + port->id;
+}
+
+/* Get number of physical TXQ */
+static inline int mvpp2_txq_phys(int port, int txq)
+{
+ return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
+}
+
+/* Parser configuration routines */
+
+/* Update parser tcam and sram hw entries */
+static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
+{
+ int i;
+
+ if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
+ return -EINVAL;
+
+ /* Clear entry invalidation bit */
+ pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
+
+ /* Write tcam index - indirect access */
+ mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
+ for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
+ mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
+
+ /* Write sram index - indirect access */
+ mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
+ for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
+ mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
+
+ return 0;
+}
+
+/* Read tcam entry from hw */
+static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
+{
+ int i;
+
+ if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
+ return -EINVAL;
+
+ /* Write tcam index - indirect access */
+ mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
+
+ pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
+ MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
+ if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
+ return MVPP2_PRS_TCAM_ENTRY_INVALID;
+
+ for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
+ pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
+
+ /* Write sram index - indirect access */
+ mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
+ for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
+ pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
+
+ return 0;
+}
+
+/* Invalidate tcam hw entry */
+static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
+{
+ /* Write index - indirect access */
+ mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
+ mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
+ MVPP2_PRS_TCAM_INV_MASK);
+}
+
+/* Enable shadow table entry and set its lookup ID */
+static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
+{
+ priv->prs_shadow[index].valid = true;
+ priv->prs_shadow[index].lu = lu;
+}
+
+/* Update ri fields in shadow table entry */
+static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
+ unsigned int ri, unsigned int ri_mask)
+{
+ priv->prs_shadow[index].ri_mask = ri_mask;
+ priv->prs_shadow[index].ri = ri;
+}
+
+/* Update lookup field in tcam sw entry */
+static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
+{
+ int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
+
+ pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
+ pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
+}
+
+/* Update mask for single port in tcam sw entry */
+static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
+ unsigned int port, bool add)
+{
+ int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
+
+ if (add)
+ pe->tcam.byte[enable_off] &= ~(1 << port);
+ else
+ pe->tcam.byte[enable_off] |= 1 << port;
+}
+
+/* Update port map in tcam sw entry */
+static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
+ unsigned int ports)
+{
+ unsigned char port_mask = MVPP2_PRS_PORT_MASK;
+ int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
+
+ pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
+ pe->tcam.byte[enable_off] &= ~port_mask;
+ pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
+}
+
+/* Obtain port map from tcam sw entry */
+static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
+{
+ int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
+
+ return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
+}
+
+/* Set byte of data and its enable bits in tcam sw entry */
+static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
+ unsigned int offs, unsigned char byte,
+ unsigned char enable)
+{
+ pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
+ pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
+}
+
+/* Get byte of data and its enable bits from tcam sw entry */
+static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
+ unsigned int offs, unsigned char *byte,
+ unsigned char *enable)
+{
+ *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
+ *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
+}
+
+/* Set ethertype in tcam sw entry */
+static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
+ unsigned short ethertype)
+{
+ mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
+ mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
+}
+
+/* Set bits in sram sw entry */
+static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
+ int val)
+{
+ pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
+}
+
+/* Clear bits in sram sw entry */
+static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
+ int val)
+{
+ pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
+}
+
+/* Update ri bits in sram sw entry */
+static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
+ unsigned int bits, unsigned int mask)
+{
+ unsigned int i;
+
+ for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
+ int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
+
+ if (!(mask & BIT(i)))
+ continue;
+
+ if (bits & BIT(i))
+ mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
+ else
+ mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
+
+ mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
+ }
+}
+
+/* Update ai bits in sram sw entry */
+static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
+ unsigned int bits, unsigned int mask)
+{
+ unsigned int i;
+ int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
+
+ for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
+
+ if (!(mask & BIT(i)))
+ continue;
+
+ if (bits & BIT(i))
+ mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
+ else
+ mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
+
+ mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
+ }
+}
+
+/* Read ai bits from sram sw entry */
+static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
+{
+ u8 bits;
+ int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
+ int ai_en_off = ai_off + 1;
+ int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
+
+ bits = (pe->sram.byte[ai_off] >> ai_shift) |
+ (pe->sram.byte[ai_en_off] << (8 - ai_shift));
+
+ return bits;
+}
+
+/* In sram sw entry set lookup ID field of the tcam key to be used in the next
+ * lookup interation
+ */
+static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
+ unsigned int lu)
+{
+ int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
+
+ mvpp2_prs_sram_bits_clear(pe, sram_next_off,
+ MVPP2_PRS_SRAM_NEXT_LU_MASK);
+ mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
+}
+
+/* In the sram sw entry set sign and value of the next lookup offset
+ * and the offset value generated to the classifier
+ */
+static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
+ unsigned int op)
+{
+ /* Set sign */
+ if (shift < 0) {
+ mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
+ shift = 0 - shift;
+ } else {
+ mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
+ }
+
+ /* Set value */
+ pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
+ (unsigned char)shift;
+
+ /* Reset and set operation */
+ mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
+ MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
+ mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
+
+ /* Set base offset as current */
+ mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
+}
+
+/* In the sram sw entry set sign and value of the user defined offset
+ * generated to the classifier
+ */
+static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
+ unsigned int type, int offset,
+ unsigned int op)
+{
+ /* Set sign */
+ if (offset < 0) {
+ mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
+ offset = 0 - offset;
+ } else {
+ mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
+ }
+
+ /* Set value */
+ mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
+ MVPP2_PRS_SRAM_UDF_MASK);
+ mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
+ pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
+ MVPP2_PRS_SRAM_UDF_BITS)] &=
+ ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
+ pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
+ MVPP2_PRS_SRAM_UDF_BITS)] |=
+ (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
+
+ /* Set offset type */
+ mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
+ MVPP2_PRS_SRAM_UDF_TYPE_MASK);
+ mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
+
+ /* Set offset operation */
+ mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
+ MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
+ mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
+
+ pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
+ MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
+ ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
+ (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
+
+ pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
+ MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
+ (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
+
+ /* Set base offset as current */
+ mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
+}
+
+/* Find parser flow entry */
+static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
+{
+ struct mvpp2_prs_entry *pe;
+ int tid;
+
+ pe = kzalloc(sizeof(*pe), GFP_KERNEL);
+ if (!pe)
+ return NULL;
+ mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
+
+ /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
+ for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
+ u8 bits;
+
+ if (!priv->prs_shadow[tid].valid ||
+ priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
+ continue;
+
+ pe->index = tid;
+ mvpp2_prs_hw_read(priv, pe);
+ bits = mvpp2_prs_sram_ai_get(pe);
+
+ /* Sram store classification lookup ID in AI bits [5:0] */
+ if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
+ return pe;
+ }
+ kfree(pe);
+
+ return NULL;
+}
+
+/* Return first free tcam index, seeking from start to end */
+static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
+ unsigned char end)
+{
+ int tid;
+
+ if (start > end)
+ swap(start, end);
+
+ if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
+ end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
+
+ for (tid = start; tid <= end; tid++) {
+ if (!priv->prs_shadow[tid].valid)
+ return tid;
+ }
+
+ return -EINVAL;
+}
+
+/* Enable/disable dropping all mac da's */
+static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
+{
+ struct mvpp2_prs_entry pe;
+
+ if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
+ /* Entry exist - update port only */
+ pe.index = MVPP2_PE_DROP_ALL;
+ mvpp2_prs_hw_read(priv, &pe);
+ } else {
+ /* Entry doesn't exist - create new */
+ memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
+ mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
+ pe.index = MVPP2_PE_DROP_ALL;
+
+ /* Non-promiscuous mode for all ports - DROP unknown packets */
+ mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
+ MVPP2_PRS_RI_DROP_MASK);
+
+ mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
+ mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
+
+ /* Update shadow table */
+ mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
+
+ /* Mask all ports */
+ mvpp2_prs_tcam_port_map_set(&pe, 0);
+ }
+
+ /* Update port mask */
+ mvpp2_prs_tcam_port_set(&pe, port, add);
+
+ mvpp2_prs_hw_write(priv, &pe);
+}
+
+/* Set port to promiscuous mode */
+static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
+{
+ struct mvpp2_prs_entry pe;
+
+ /* Promiscuous mode - Accept unknown packets */
+
+ if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
+ /* Entry exist - update port only */
+ pe.index = MVPP2_PE_MAC_PROMISCUOUS;
+ mvpp2_prs_hw_read(priv, &pe);
+ } else {
+ /* Entry doesn't exist - create new */
+ memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
+ mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
+ pe.index = MVPP2_PE_MAC_PROMISCUOUS;
+
+ /* Continue - set next lookup */
+ mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
+
+ /* Set result info bits */
+ mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
+ MVPP2_PRS_RI_L2_CAST_MASK);
+
+ /* Shift to ethertype */
+ mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
+ MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+
+ /* Mask all ports */
+ mvpp2_prs_tcam_port_map_set(&pe, 0);
+
+ /* Update shadow table */
+ mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
+ }
+
+ /* Update port mask */
+ mvpp2_prs_tcam_port_set(&pe, port, add);
+
+ mvpp2_prs_hw_write(priv, &pe);
+}
+
+/* Accept multicast */
+static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
+ bool add)
+{
+ struct mvpp2_prs_entry pe;
+ unsigned char da_mc;
+
+ /* Ethernet multicast address first byte is
+ * 0x01 for IPv4 and 0x33 for IPv6
+ */
+ da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
+
+ if (priv->prs_shadow[index].valid) {
+ /* Entry exist - update port only */
+ pe.index = index;
+ mvpp2_prs_hw_read(priv, &pe);
+ } else {
+ /* Entry doesn't exist - create new */
+ memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
+ mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
+ pe.index = index;
+
+ /* Continue - set next lookup */
+ mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
+
+ /* Set result info bits */
+ mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
+ MVPP2_PRS_RI_L2_CAST_MASK);
+
+ /* Update tcam entry data first byte */
+ mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
+
+ /* Shift to ethertype */
+ mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
+ MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+
+ /* Mask all ports */
+ mvpp2_prs_tcam_port_map_set(&pe, 0);
+
+ /* Update shadow table */
+ mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
+ }
+
+ /* Update port mask */
+ mvpp2_prs_tcam_port_set(&pe, port, add);
+
+ mvpp2_prs_hw_write(priv, &pe);
+}
+
+/* Parser per-port initialization */
+static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
+ int lu_max, int offset)
+{
+ u32 val;
+
+ /* Set lookup ID */
+ val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
+ val &= ~MVPP2_PRS_PORT_LU_MASK(port);
+ val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
+ mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
+
+ /* Set maximum number of loops for packet received from port */
+ val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
+ val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
+ val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
+ mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
+
+ /* Set initial offset for packet header extraction for the first
+ * searching loop
+ */
+ val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
+ val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
+ val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
+ mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
+}
+
+/* Default flow entries initialization for all ports */
+static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
+{
+ struct mvpp2_prs_entry pe;
+ int port;
+
+ for (port = 0; port < MVPP2_MAX_PORTS; port++) {
+ memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
+ mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
+ pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
+
+ /* Mask all ports */
+ mvpp2_prs_tcam_port_map_set(&pe, 0);
+
+ /* Set flow ID*/
+ mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
+ mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
+
+ /* Update shadow table and hw entry */
+ mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
+ mvpp2_prs_hw_write(priv, &pe);
+ }
+}
+
+/* Set default entry for Marvell Header field */
+static void mvpp2_prs_mh_init(struct mvpp2 *priv)
+{
+ struct mvpp2_prs_entry pe;
+
+ memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
+
+ pe.index = MVPP2_PE_MH_DEFAULT;
+ mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
+ mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
+ MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+ mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
+
+ /* Unmask all ports */
+ mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
+
+ /* Update shadow table and hw entry */
+ mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
+ mvpp2_prs_hw_write(priv, &pe);
+}
+
+/* Set default entires (place holder) for promiscuous, non-promiscuous and
+ * multicast MAC addresses
+ */
+static void mvpp2_prs_mac_init(struct mvpp2 *priv)
+{
+ struct mvpp2_prs_entry pe;
+
+ memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
+
+ /* Non-promiscuous mode for all ports - DROP unknown packets */
+ pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
+ mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
+
+ mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
+ MVPP2_PRS_RI_DROP_MASK);
+ mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
+ mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
+
+ /* Unmask all ports */
+ mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
+
+ /* Update shadow table and hw entry */
+ mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
+ mvpp2_prs_hw_write(priv, &pe);
+
+ /* place holders only - no ports */
+ mvpp2_prs_mac_drop_all_set(priv, 0, false);
+ mvpp2_prs_mac_promisc_set(priv, 0, false);
+ mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
+ mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
+}
+
+/* Match basic ethertypes */
+static int mvpp2_prs_etype_init(struct mvpp2 *priv)
+{
+ struct mvpp2_prs_entry pe;
+ int tid;
+
+ /* Ethertype: PPPoE */
+ tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
+ MVPP2_PE_LAST_FREE_TID);
+ if (tid < 0)
+ return tid;
+
+ memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
+ mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
+ pe.index = tid;
+
+ mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
+
+ mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
+ MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+ mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
+ mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
+ MVPP2_PRS_RI_PPPOE_MASK);
+
+ /* Update shadow table and hw entry */
+ mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
+ priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
+ priv->prs_shadow[pe.index].finish = false;
+ mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
+ MVPP2_PRS_RI_PPPOE_MASK);
+ mvpp2_prs_hw_write(priv, &pe);
+
+ /* Ethertype: ARP */
+ tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
+ MVPP2_PE_LAST_FREE_TID);
+ if (tid < 0)
+ return tid;
+
+ memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
+ mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
+ pe.index = tid;
+
+ mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
+
+ /* Generate flow in the next iteration*/
+ mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
+ mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
+ mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
+ MVPP2_PRS_RI_L3_PROTO_MASK);
+ /* Set L3 offset */
+ mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
+ MVPP2_ETH_TYPE_LEN,
+ MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
+
+ /* Update shadow table and hw entry */
+ mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
+ priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
+ priv->prs_shadow[pe.index].finish = true;
+ mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
+ MVPP2_PRS_RI_L3_PROTO_MASK);
+ mvpp2_prs_hw_write(priv, &pe);
+
+ /* Ethertype: LBTD */
+ tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
+ MVPP2_PE_LAST_FREE_TID);
+ if (tid < 0)
+ return tid;
+
+ memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
+ mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
+ pe.index = tid;
+
+ mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
+
+ /* Generate flow in the next iteration*/
+ mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
+ mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
+ mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
+ MVPP2_PRS_RI_UDF3_RX_SPECIAL,
+ MVPP2_PRS_RI_CPU_CODE_MASK |
+ MVPP2_PRS_RI_UDF3_MASK);
+ /* Set L3 offset */
+ mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
+ MVPP2_ETH_TYPE_LEN,
+ MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
+
+ /* Update shadow table and hw entry */
+ mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
+ priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
+ priv->prs_shadow[pe.index].finish = true;
+ mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
+ MVPP2_PRS_RI_UDF3_RX_SPECIAL,
+ MVPP2_PRS_RI_CPU_CODE_MASK |
+ MVPP2_PRS_RI_UDF3_MASK);
+ mvpp2_prs_hw_write(priv, &pe);
+
+ /* Ethertype: IPv4 without options */
+ tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
+ MVPP2_PE_LAST_FREE_TID);
+ if (tid < 0)
+ return tid;
+
+ memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
+ mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
+ pe.index = tid;
+
+ mvpp2_prs_match_etype(&pe, 0, PROT_IP);
+ mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
+ MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
+ MVPP2_PRS_IPV4_HEAD_MASK |
+ MVPP2_PRS_IPV4_IHL_MASK);
+
+ mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
+ mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
+ MVPP2_PRS_RI_L3_PROTO_MASK);
+ /* Skip eth_type + 4 bytes of IP header */
+ mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
+ MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+ /* Set L3 offset */
+ mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
+ MVPP2_ETH_TYPE_LEN,
+ MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
+
+ /* Update shadow table and hw entry */
+ mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
+ priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
+ priv->prs_shadow[pe.index].finish = false;
+ mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
+ MVPP2_PRS_RI_L3_PROTO_MASK);
+ mvpp2_prs_hw_write(priv, &pe);
+
+ /* Ethertype: IPv4 with options */
+ tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
+ MVPP2_PE_LAST_FREE_TID);
+ if (tid < 0)
+ return tid;
+
+ pe.index = tid;
+
+ /* Clear tcam data before updating */
+ pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
+ pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
+
+ mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
+ MVPP2_PRS_IPV4_HEAD,
+ MVPP2_PRS_IPV4_HEAD_MASK);
+
+ /* Clear ri before updating */
+ pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
+ pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
+ mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
+ MVPP2_PRS_RI_L3_PROTO_MASK);
+
+ /* Update shadow table and hw entry */
+ mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
+ priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
+ priv->prs_shadow[pe.index].finish = false;
+ mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
+ MVPP2_PRS_RI_L3_PROTO_MASK);
+ mvpp2_prs_hw_write(priv, &pe);
+
+ /* Ethertype: IPv6 without options */
+ tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
+ MVPP2_PE_LAST_FREE_TID);
+ if (tid < 0)
+ return tid;
+
+ memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
+ mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
+ pe.index = tid;
+
+ mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
+
+ /* Skip DIP of IPV6 header */
+ mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
+ MVPP2_MAX_L3_ADDR_SIZE,
+ MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+ mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
+ mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
+ MVPP2_PRS_RI_L3_PROTO_MASK);
+ /* Set L3 offset */
+ mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
+ MVPP2_ETH_TYPE_LEN,
+ MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
+
+ mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
+ priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
+ priv->prs_shadow[pe.index].finish = false;
+ mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
+ MVPP2_PRS_RI_L3_PROTO_MASK);
+ mvpp2_prs_hw_write(priv, &pe);
+
+ /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
+ memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
+ mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
+ pe.index = MVPP2_PE_ETH_TYPE_UN;
+
+ /* Unmask all ports */
+ mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
+
+ /* Generate flow in the next iteration*/
+ mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
+ mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
+ mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
+ MVPP2_PRS_RI_L3_PROTO_MASK);
+ /* Set L3 offset even it's unknown L3 */
+ mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
+ MVPP2_ETH_TYPE_LEN,
+ MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
+
+ /* Update shadow table and hw entry */
+ mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
+ priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
+ priv->prs_shadow[pe.index].finish = true;
+ mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
+ MVPP2_PRS_RI_L3_PROTO_MASK);
+ mvpp2_prs_hw_write(priv, &pe);
+
+ return 0;
+}
+
+/* Parser default initialization */
+static int mvpp2_prs_default_init(struct udevice *dev,
+ struct mvpp2 *priv)
+{
+ int err, index, i;
+
+ /* Enable tcam table */
+ mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
+
+ /* Clear all tcam and sram entries */
+ for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
+ mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
+ for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
+ mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
+
+ mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
+ for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
+ mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
+ }
+
+ /* Invalidate all tcam entries */
+ for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
+ mvpp2_prs_hw_inv(priv, index);
+
+ priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
+ sizeof(struct mvpp2_prs_shadow),
+ GFP_KERNEL);
+ if (!priv->prs_shadow)
+ return -ENOMEM;
+
+ /* Always start from lookup = 0 */
+ for (index = 0; index < MVPP2_MAX_PORTS; index++)
+ mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
+ MVPP2_PRS_PORT_LU_MAX, 0);
+
+ mvpp2_prs_def_flow_init(priv);
+
+ mvpp2_prs_mh_init(priv);
+
+ mvpp2_prs_mac_init(priv);
+
+ err = mvpp2_prs_etype_init(priv);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+/* Compare MAC DA with tcam entry data */
+static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
+ const u8 *da, unsigned char *mask)
+{
+ unsigned char tcam_byte, tcam_mask;
+ int index;
+
+ for (index = 0; index < ETH_ALEN; index++) {
+ mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
+ if (tcam_mask != mask[index])
+ return false;
+
+ if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
+ return false;
+ }
+
+ return true;
+}
+
+/* Find tcam entry with matched pair <MAC DA, port> */
+static struct mvpp2_prs_entry *
+mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
+ unsigned char *mask, int udf_type)
+{
+ struct mvpp2_prs_entry *pe;
+ int tid;
+
+ pe = kzalloc(sizeof(*pe), GFP_KERNEL);
+ if (!pe)
+ return NULL;
+ mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
+
+ /* Go through the all entires with MVPP2_PRS_LU_MAC */
+ for (tid = MVPP2_PE_FIRST_FREE_TID;
+ tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
+ unsigned int entry_pmap;
+
+ if (!priv->prs_shadow[tid].valid ||
+ (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
+ (priv->prs_shadow[tid].udf != udf_type))
+ continue;
+
+ pe->index = tid;
+ mvpp2_prs_hw_read(priv, pe);
+ entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
+
+ if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
+ entry_pmap == pmap)
+ return pe;
+ }
+ kfree(pe);
+
+ return NULL;
+}
+
+/* Update parser's mac da entry */
+static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
+ const u8 *da, bool add)
+{
+ struct mvpp2_prs_entry *pe;
+ unsigned int pmap, len, ri;
+ unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+ int tid;
+
+ /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
+ pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
+ MVPP2_PRS_UDF_MAC_DEF);
+
+ /* No such entry */
+ if (!pe) {
+ if (!add)
+ return 0;
+
+ /* Create new TCAM entry */
+ /* Find first range mac entry*/
+ for (tid = MVPP2_PE_FIRST_FREE_TID;
+ tid <= MVPP2_PE_LAST_FREE_TID; tid++)
+ if (priv->prs_shadow[tid].valid &&
+ (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
+ (priv->prs_shadow[tid].udf ==
+ MVPP2_PRS_UDF_MAC_RANGE))
+ break;
+
+ /* Go through the all entries from first to last */
+ tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
+ tid - 1);
+ if (tid < 0)
+ return tid;
+
+ pe = kzalloc(sizeof(*pe), GFP_KERNEL);
+ if (!pe)
+ return -1;
+ mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
+ pe->index = tid;
+
+ /* Mask all ports */
+ mvpp2_prs_tcam_port_map_set(pe, 0);
+ }
+
+ /* Update port mask */
+ mvpp2_prs_tcam_port_set(pe, port, add);
+
+ /* Invalidate the entry if no ports are left enabled */
+ pmap = mvpp2_prs_tcam_port_map_get(pe);
+ if (pmap == 0) {
+ if (add) {
+ kfree(pe);
+ return -1;
+ }
+ mvpp2_prs_hw_inv(priv, pe->index);
+ priv->prs_shadow[pe->index].valid = false;
+ kfree(pe);
+ return 0;
+ }
+
+ /* Continue - set next lookup */
+ mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
+
+ /* Set match on DA */
+ len = ETH_ALEN;
+ while (len--)
+ mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
+
+ /* Set result info bits */
+ ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
+
+ mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
+ MVPP2_PRS_RI_MAC_ME_MASK);
+ mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
+ MVPP2_PRS_RI_MAC_ME_MASK);
+
+ /* Shift to ethertype */
+ mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
+ MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+
+ /* Update shadow table and hw entry */
+ priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
+ mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
+ mvpp2_prs_hw_write(priv, pe);
+
+ kfree(pe);
+
+ return 0;
+}
+
+static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
+{
+ int err;
+
+ /* Remove old parser entry */
+ err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
+ false);
+ if (err)
+ return err;
+
+ /* Add new parser entry */
+ err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
+ if (err)
+ return err;
+
+ /* Set addr in the device */
+ memcpy(port->dev_addr, da, ETH_ALEN);
+
+ return 0;
+}
+
+/* Set prs flow for the port */
+static int mvpp2_prs_def_flow(struct mvpp2_port *port)
+{
+ struct mvpp2_prs_entry *pe;
+ int tid;
+
+ pe = mvpp2_prs_flow_find(port->priv, port->id);
+
+ /* Such entry not exist */
+ if (!pe) {
+ /* Go through the all entires from last to first */
+ tid = mvpp2_prs_tcam_first_free(port->priv,
+ MVPP2_PE_LAST_FREE_TID,
+ MVPP2_PE_FIRST_FREE_TID);
+ if (tid < 0)
+ return tid;
+
+ pe = kzalloc(sizeof(*pe), GFP_KERNEL);
+ if (!pe)
+ return -ENOMEM;
+
+ mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
+ pe->index = tid;
+
+ /* Set flow ID*/
+ mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
+ mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
+
+ /* Update shadow table */
+ mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
+ }
+
+ mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
+ mvpp2_prs_hw_write(port->priv, pe);
+ kfree(pe);
+
+ return 0;
+}
+
+/* Classifier configuration routines */
+
+/* Update classification flow table registers */
+static void mvpp2_cls_flow_write(struct mvpp2 *priv,
+ struct mvpp2_cls_flow_entry *fe)
+{
+ mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
+ mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
+ mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
+ mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
+}
+
+/* Update classification lookup table register */
+static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
+ struct mvpp2_cls_lookup_entry *le)
+{
+ u32 val;
+
+ val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
+ mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
+ mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
+}
+
+/* Classifier default initialization */
+static void mvpp2_cls_init(struct mvpp2 *priv)
+{
+ struct mvpp2_cls_lookup_entry le;
+ struct mvpp2_cls_flow_entry fe;
+ int index;
+
+ /* Enable classifier */
+ mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
+
+ /* Clear classifier flow table */
+ memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
+ for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
+ fe.index = index;
+ mvpp2_cls_flow_write(priv, &fe);
+ }
+
+ /* Clear classifier lookup table */
+ le.data = 0;
+ for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
+ le.lkpid = index;
+ le.way = 0;
+ mvpp2_cls_lookup_write(priv, &le);
+
+ le.way = 1;
+ mvpp2_cls_lookup_write(priv, &le);
+ }
+}
+
+static void mvpp2_cls_port_config(struct mvpp2_port *port)
+{
+ struct mvpp2_cls_lookup_entry le;
+ u32 val;
+
+ /* Set way for the port */
+ val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
+ val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
+ mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
+
+ /* Pick the entry to be accessed in lookup ID decoding table
+ * according to the way and lkpid.
+ */
+ le.lkpid = port->id;
+ le.way = 0;
+ le.data = 0;
+
+ /* Set initial CPU queue for receiving packets */
+ le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
+ le.data |= port->first_rxq;
+
+ /* Disable classification engines */
+ le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
+
+ /* Update lookup ID table entry */
+ mvpp2_cls_lookup_write(port->priv, &le);
+}
+
+/* Set CPU queue number for oversize packets */
+static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
+{
+ u32 val;
+
+ mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
+ port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
+
+ mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
+ (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
+
+ val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
+ val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
+ mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
+}
+
+/* Buffer Manager configuration routines */
+
+/* Create pool */
+static int mvpp2_bm_pool_create(struct udevice *dev,
+ struct mvpp2 *priv,
+ struct mvpp2_bm_pool *bm_pool, int size)
+{
+ u32 val;
+
+ bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
+ bm_pool->phys_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
+ if (!bm_pool->virt_addr)
+ return -ENOMEM;
+
+ if (!IS_ALIGNED((u32)bm_pool->virt_addr, MVPP2_BM_POOL_PTR_ALIGN)) {
+ dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
+ bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
+ return -ENOMEM;
+ }
+
+ mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
+ bm_pool->phys_addr);
+ mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
+
+ val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
+ val |= MVPP2_BM_START_MASK;
+ mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
+
+ bm_pool->type = MVPP2_BM_FREE;
+ bm_pool->size = size;
+ bm_pool->pkt_size = 0;
+ bm_pool->buf_num = 0;
+
+ return 0;
+}
+
+/* Set pool buffer size */
+static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
+ struct mvpp2_bm_pool *bm_pool,
+ int buf_size)
+{
+ u32 val;
+
+ bm_pool->buf_size = buf_size;
+
+ val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
+ mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
+}
+
+/* Free all buffers from the pool */
+static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
+ struct mvpp2_bm_pool *bm_pool)
+{
+ bm_pool->buf_num = 0;
+}
+
+/* Cleanup pool */
+static int mvpp2_bm_pool_destroy(struct udevice *dev,
+ struct mvpp2 *priv,
+ struct mvpp2_bm_pool *bm_pool)
+{
+ u32 val;
+
+ mvpp2_bm_bufs_free(dev, priv, bm_pool);
+ if (bm_pool->buf_num) {
+ dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
+ return 0;
+ }
+
+ val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
+ val |= MVPP2_BM_STOP_MASK;
+ mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
+
+ return 0;
+}
+
+static int mvpp2_bm_pools_init(struct udevice *dev,
+ struct mvpp2 *priv)
+{
+ int i, err, size;
+ struct mvpp2_bm_pool *bm_pool;
+
+ /* Create all pools with maximum size */
+ size = MVPP2_BM_POOL_SIZE_MAX;
+ for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
+ bm_pool = &priv->bm_pools[i];
+ bm_pool->id = i;
+ err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
+ if (err)
+ goto err_unroll_pools;
+ mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
+ }
+ return 0;
+
+err_unroll_pools:
+ dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
+ for (i = i - 1; i >= 0; i--)
+ mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
+ return err;
+}
+
+static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
+{
+ int i, err;
+
+ for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
+ /* Mask BM all interrupts */
+ mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
+ /* Clear BM cause register */
+ mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
+ }
+
+ /* Allocate and initialize BM pools */
+ priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
+ sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
+ if (!priv->bm_pools)
+ return -ENOMEM;
+
+ err = mvpp2_bm_pools_init(dev, priv);
+ if (err < 0)
+ return err;
+ return 0;
+}
+
+/* Attach long pool to rxq */
+static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
+ int lrxq, int long_pool)
+{
+ u32 val;
+ int prxq;
+
+ /* Get queue physical ID */
+ prxq = port->rxqs[lrxq]->id;
+
+ val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
+ val &= ~MVPP2_RXQ_POOL_LONG_MASK;
+ val |= ((long_pool << MVPP2_RXQ_POOL_LONG_OFFS) &
+ MVPP2_RXQ_POOL_LONG_MASK);
+
+ mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
+}
+
+/* Set pool number in a BM cookie */
+static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
+{
+ u32 bm;
+
+ bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
+ bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
+
+ return bm;
+}
+
+/* Get pool number from a BM cookie */
+static inline int mvpp2_bm_cookie_pool_get(u32 cookie)
+{
+ return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
+}
+
+/* Release buffer to BM */
+static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
+ u32 buf_phys_addr, u32 buf_virt_addr)
+{
+ mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr);
+ mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_phys_addr);
+}
+
+/* Refill BM pool */
+static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
+ u32 phys_addr, u32 cookie)
+{
+ int pool = mvpp2_bm_cookie_pool_get(bm);
+
+ mvpp2_bm_pool_put(port, pool, phys_addr, cookie);
+}
+
+/* Allocate buffers for the pool */
+static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
+ struct mvpp2_bm_pool *bm_pool, int buf_num)
+{
+ int i;
+ u32 bm;
+
+ if (buf_num < 0 ||
+ (buf_num + bm_pool->buf_num > bm_pool->size)) {
+ netdev_err(port->dev,
+ "cannot allocate %d buffers for pool %d\n",
+ buf_num, bm_pool->id);
+ return 0;
+ }
+
+ bm = mvpp2_bm_cookie_pool_set(0, bm_pool->id);
+ for (i = 0; i < buf_num; i++) {
+ mvpp2_pool_refill(port, bm, (u32)buffer_loc.rx_buffer[i],
+ (u32)buffer_loc.rx_buffer[i]);
+ }
+
+ /* Update BM driver with number of buffers added to pool */
+ bm_pool->buf_num += i;
+ bm_pool->in_use_thresh = bm_pool->buf_num / 4;
+
+ return i;
+}
+
+/* Notify the driver that BM pool is being used as specific type and return the
+ * pool pointer on success
+ */
+static struct mvpp2_bm_pool *
+mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
+ int pkt_size)
+{
+ struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
+ int num;
+
+ if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
+ netdev_err(port->dev, "mixing pool types is forbidden\n");
+ return NULL;
+ }
+
+ if (new_pool->type == MVPP2_BM_FREE)
+ new_pool->type = type;
+
+ /* Allocate buffers in case BM pool is used as long pool, but packet
+ * size doesn't match MTU or BM pool hasn't being used yet
+ */
+ if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
+ (new_pool->pkt_size == 0)) {
+ int pkts_num;
+
+ /* Set default buffer number or free all the buffers in case
+ * the pool is not empty
+ */
+ pkts_num = new_pool->buf_num;
+ if (pkts_num == 0)
+ pkts_num = type == MVPP2_BM_SWF_LONG ?
+ MVPP2_BM_LONG_BUF_NUM :
+ MVPP2_BM_SHORT_BUF_NUM;
+ else
+ mvpp2_bm_bufs_free(NULL,
+ port->priv, new_pool);
+
+ new_pool->pkt_size = pkt_size;
+
+ /* Allocate buffers for this pool */
+ num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
+ if (num != pkts_num) {
+ dev_err(dev, "pool %d: %d of %d allocated\n",
+ new_pool->id, num, pkts_num);
+ return NULL;
+ }
+ }
+
+ mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
+ MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
+
+ return new_pool;
+}
+
+/* Initialize pools for swf */
+static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
+{
+ int rxq;
+
+ if (!port->pool_long) {
+ port->pool_long =
+ mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
+ MVPP2_BM_SWF_LONG,
+ port->pkt_size);
+ if (!port->pool_long)
+ return -ENOMEM;
+
+ port->pool_long->port_map |= (1 << port->id);
+
+ for (rxq = 0; rxq < rxq_number; rxq++)
+ mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
+ }
+
+ return 0;
+}
+
+/* Port configuration routines */
+
+static void mvpp2_port_mii_set(struct mvpp2_port *port)
+{
+ u32 val;
+
+ val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+
+ switch (port->phy_interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ val |= MVPP2_GMAC_INBAND_AN_MASK;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ val |= MVPP2_GMAC_PORT_RGMII_MASK;
+ default:
+ val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
+ }
+
+ writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+}
+
+static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
+{
+ u32 val;
+
+ val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+ val |= MVPP2_GMAC_FC_ADV_EN;
+ writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+}
+
+static void mvpp2_port_enable(struct mvpp2_port *port)
+{
+ u32 val;
+
+ val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
+ val |= MVPP2_GMAC_PORT_EN_MASK;
+ val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
+ writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
+}
+
+static void mvpp2_port_disable(struct mvpp2_port *port)
+{
+ u32 val;
+
+ val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
+ val &= ~(MVPP2_GMAC_PORT_EN_MASK);
+ writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
+}
+
+/* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
+static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
+{
+ u32 val;
+
+ val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
+ ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
+ writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
+}
+
+/* Configure loopback port */
+static void mvpp2_port_loopback_set(struct mvpp2_port *port)
+{
+ u32 val;
+
+ val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
+
+ if (port->speed == 1000)
+ val |= MVPP2_GMAC_GMII_LB_EN_MASK;
+ else
+ val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
+
+ if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
+ val |= MVPP2_GMAC_PCS_LB_EN_MASK;
+ else
+ val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
+
+ writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
+}
+
+static void mvpp2_port_reset(struct mvpp2_port *port)
+{
+ u32 val;
+
+ val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
+ ~MVPP2_GMAC_PORT_RESET_MASK;
+ writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+ while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
+ MVPP2_GMAC_PORT_RESET_MASK)
+ continue;
+}
+
+/* Change maximum receive size of the port */
+static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
+{
+ u32 val;
+
+ val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
+ val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
+ val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
+ MVPP2_GMAC_MAX_RX_SIZE_OFFS);
+ writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
+}
+
+/* Set defaults to the MVPP2 port */
+static void mvpp2_defaults_set(struct mvpp2_port *port)
+{
+ int tx_port_num, val, queue, ptxq, lrxq;
+
+ /* Configure port to loopback if needed */
+ if (port->flags & MVPP2_F_LOOPBACK)
+ mvpp2_port_loopback_set(port);
+
+ /* Update TX FIFO MIN Threshold */
+ val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+ val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
+ /* Min. TX threshold must be less than minimal packet length */
+ val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
+ writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+
+ /* Disable Legacy WRR, Disable EJP, Release from reset */
+ tx_port_num = mvpp2_egress_port(port);
+ mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
+ tx_port_num);
+ mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
+
+ /* Close bandwidth for all queues */
+ for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
+ ptxq = mvpp2_txq_phys(port->id, queue);
+ mvpp2_write(port->priv,
+ MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
+ }
+
+ /* Set refill period to 1 usec, refill tokens
+ * and bucket size to maximum
+ */
+ mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
+ val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
+ val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
+ val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
+ val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
+ mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
+ val = MVPP2_TXP_TOKEN_SIZE_MAX;
+ mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
+
+ /* Set MaximumLowLatencyPacketSize value to 256 */
+ mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
+ MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
+ MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
+
+ /* Enable Rx cache snoop */
+ for (lrxq = 0; lrxq < rxq_number; lrxq++) {
+ queue = port->rxqs[lrxq]->id;
+ val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
+ val |= MVPP2_SNOOP_PKT_SIZE_MASK |
+ MVPP2_SNOOP_BUF_HDR_MASK;
+ mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
+ }
+}
+
+/* Enable/disable receiving packets */
+static void mvpp2_ingress_enable(struct mvpp2_port *port)
+{
+ u32 val;
+ int lrxq, queue;
+
+ for (lrxq = 0; lrxq < rxq_number; lrxq++) {
+ queue = port->rxqs[lrxq]->id;
+ val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
+ val &= ~MVPP2_RXQ_DISABLE_MASK;
+ mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
+ }
+}
+
+static void mvpp2_ingress_disable(struct mvpp2_port *port)
+{
+ u32 val;
+ int lrxq, queue;
+
+ for (lrxq = 0; lrxq < rxq_number; lrxq++) {
+ queue = port->rxqs[lrxq]->id;
+ val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
+ val |= MVPP2_RXQ_DISABLE_MASK;
+ mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
+ }
+}
+
+/* Enable transmit via physical egress queue
+ * - HW starts take descriptors from DRAM
+ */
+static void mvpp2_egress_enable(struct mvpp2_port *port)
+{
+ u32 qmap;
+ int queue;
+ int tx_port_num = mvpp2_egress_port(port);
+
+ /* Enable all initialized TXs. */
+ qmap = 0;
+ for (queue = 0; queue < txq_number; queue++) {
+ struct mvpp2_tx_queue *txq = port->txqs[queue];
+
+ if (txq->descs != NULL)
+ qmap |= (1 << queue);
+ }
+
+ mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
+ mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
+}
+
+/* Disable transmit via physical egress queue
+ * - HW doesn't take descriptors from DRAM
+ */
+static void mvpp2_egress_disable(struct mvpp2_port *port)
+{
+ u32 reg_data;
+ int delay;
+ int tx_port_num = mvpp2_egress_port(port);
+
+ /* Issue stop command for active channels only */
+ mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
+ reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
+ MVPP2_TXP_SCHED_ENQ_MASK;
+ if (reg_data != 0)
+ mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
+ (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
+
+ /* Wait for all Tx activity to terminate. */
+ delay = 0;
+ do {
+ if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
+ netdev_warn(port->dev,
+ "Tx stop timed out, status=0x%08x\n",
+ reg_data);
+ break;
+ }
+ mdelay(1);
+ delay++;
+
+ /* Check port TX Command register that all
+ * Tx queues are stopped
+ */
+ reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
+ } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
+}
+
+/* Rx descriptors helper methods */
+
+/* Get number of Rx descriptors occupied by received packets */
+static inline int
+mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
+{
+ u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
+
+ return val & MVPP2_RXQ_OCCUPIED_MASK;
+}
+
+/* Update Rx queue status with the number of occupied and available
+ * Rx descriptor slots.
+ */
+static inline void
+mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
+ int used_count, int free_count)
+{
+ /* Decrement the number of used descriptors and increment count
+ * increment the number of free descriptors.
+ */
+ u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
+
+ mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
+}
+
+/* Get pointer to next RX descriptor to be processed by SW */
+static inline struct mvpp2_rx_desc *
+mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
+{
+ int rx_desc = rxq->next_desc_to_proc;
+
+ rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
+ prefetch(rxq->descs + rxq->next_desc_to_proc);
+ return rxq->descs + rx_desc;
+}
+
+/* Set rx queue offset */
+static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
+ int prxq, int offset)
+{
+ u32 val;
+
+ /* Convert offset from bytes to units of 32 bytes */
+ offset = offset >> 5;
+
+ val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
+ val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
+
+ /* Offset is in */
+ val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
+ MVPP2_RXQ_PACKET_OFFSET_MASK);
+
+ mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
+}
+
+/* Obtain BM cookie information from descriptor */
+static u32 mvpp2_bm_cookie_build(struct mvpp2_rx_desc *rx_desc)
+{
+ int pool = (rx_desc->status & MVPP2_RXD_BM_POOL_ID_MASK) >>
+ MVPP2_RXD_BM_POOL_ID_OFFS;
+ int cpu = smp_processor_id();
+
+ return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
+ ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
+}
+
+/* Tx descriptors helper methods */
+
+/* Get number of Tx descriptors waiting to be transmitted by HW */
+static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
+ struct mvpp2_tx_queue *txq)
+{
+ u32 val;
+
+ mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
+ val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
+
+ return val & MVPP2_TXQ_PENDING_MASK;
+}
+
+/* Get pointer to next Tx descriptor to be processed (send) by HW */
+static struct mvpp2_tx_desc *
+mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
+{
+ int tx_desc = txq->next_desc_to_proc;
+
+ txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
+ return txq->descs + tx_desc;
+}
+
+/* Update HW with number of aggregated Tx descriptors to be sent */
+static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
+{
+ /* aggregated access - relevant TXQ number is written in TX desc */
+ mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
+}
+
+/* Get number of sent descriptors and decrement counter.
+ * The number of sent descriptors is returned.
+ * Per-CPU access
+ */
+static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
+ struct mvpp2_tx_queue *txq)
+{
+ u32 val;
+
+ /* Reading status reg resets transmitted descriptor counter */
+ val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
+
+ return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
+ MVPP2_TRANSMITTED_COUNT_OFFSET;
+}
+
+static void mvpp2_txq_sent_counter_clear(void *arg)
+{
+ struct mvpp2_port *port = arg;
+ int queue;
+
+ for (queue = 0; queue < txq_number; queue++) {
+ int id = port->txqs[queue]->id;
+
+ mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
+ }
+}
+
+/* Set max sizes for Tx queues */
+static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
+{
+ u32 val, size, mtu;
+ int txq, tx_port_num;
+
+ mtu = port->pkt_size * 8;
+ if (mtu > MVPP2_TXP_MTU_MAX)
+ mtu = MVPP2_TXP_MTU_MAX;
+
+ /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
+ mtu = 3 * mtu;
+
+ /* Indirect access to registers */
+ tx_port_num = mvpp2_egress_port(port);
+ mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
+
+ /* Set MTU */
+ val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
+ val &= ~MVPP2_TXP_MTU_MAX;
+ val |= mtu;
+ mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
+
+ /* TXP token size and all TXQs token size must be larger that MTU */
+ val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
+ size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
+ if (size < mtu) {
+ size = mtu;
+ val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
+ val |= size;
+ mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
+ }
+
+ for (txq = 0; txq < txq_number; txq++) {
+ val = mvpp2_read(port->priv,
+ MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
+ size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
+
+ if (size < mtu) {
+ size = mtu;
+ val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
+ val |= size;
+ mvpp2_write(port->priv,
+ MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
+ val);
+ }
+ }
+}
+
+/* Free Tx queue skbuffs */
+static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
+ struct mvpp2_tx_queue *txq,
+ struct mvpp2_txq_pcpu *txq_pcpu, int num)
+{
+ int i;
+
+ for (i = 0; i < num; i++)
+ mvpp2_txq_inc_get(txq_pcpu);
+}
+
+static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
+ u32 cause)
+{
+ int queue = fls(cause) - 1;
+
+ return port->rxqs[queue];
+}
+
+static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
+ u32 cause)
+{
+ int queue = fls(cause) - 1;
+
+ return port->txqs[queue];
+}
+
+/* Rx/Tx queue initialization/cleanup methods */
+
+/* Allocate and initialize descriptors for aggr TXQ */
+static int mvpp2_aggr_txq_init(struct udevice *dev,
+ struct mvpp2_tx_queue *aggr_txq,
+ int desc_num, int cpu,
+ struct mvpp2 *priv)
+{
+ /* Allocate memory for TX descriptors */
+ aggr_txq->descs = buffer_loc.aggr_tx_descs;
+ aggr_txq->descs_phys = (dma_addr_t)buffer_loc.aggr_tx_descs;
+ if (!aggr_txq->descs)
+ return -ENOMEM;
+
+ /* Make sure descriptor address is cache line size aligned */
+ BUG_ON(aggr_txq->descs !=
+ PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
+
+ aggr_txq->last_desc = aggr_txq->size - 1;
+
+ /* Aggr TXQ no reset WA */
+ aggr_txq->next_desc_to_proc = mvpp2_read(priv,
+ MVPP2_AGGR_TXQ_INDEX_REG(cpu));
+
+ /* Set Tx descriptors queue starting address */
+ /* indirect access */
+ mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu),
+ aggr_txq->descs_phys);
+ mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
+
+ return 0;
+}
+
+/* Create a specified Rx queue */
+static int mvpp2_rxq_init(struct mvpp2_port *port,
+ struct mvpp2_rx_queue *rxq)
+
+{
+ rxq->size = port->rx_ring_size;
+
+ /* Allocate memory for RX descriptors */
+ rxq->descs = buffer_loc.rx_descs;
+ rxq->descs_phys = (dma_addr_t)buffer_loc.rx_descs;
+ if (!rxq->descs)
+ return -ENOMEM;
+
+ BUG_ON(rxq->descs !=
+ PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
+
+ rxq->last_desc = rxq->size - 1;
+
+ /* Zero occupied and non-occupied counters - direct access */
+ mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
+
+ /* Set Rx descriptors queue starting address - indirect access */
+ mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
+ mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_phys);
+ mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
+ mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
+
+ /* Set Offset */
+ mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
+
+ /* Add number of descriptors ready for receiving packets */
+ mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
+
+ return 0;
+}
+
+/* Push packets received by the RXQ to BM pool */
+static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
+ struct mvpp2_rx_queue *rxq)
+{
+ int rx_received, i;
+
+ rx_received = mvpp2_rxq_received(port, rxq->id);
+ if (!rx_received)
+ return;
+
+ for (i = 0; i < rx_received; i++) {
+ struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
+ u32 bm = mvpp2_bm_cookie_build(rx_desc);
+
+ mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr,
+ rx_desc->buf_cookie);
+ }
+ mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
+}
+
+/* Cleanup Rx queue */
+static void mvpp2_rxq_deinit(struct mvpp2_port *port,
+ struct mvpp2_rx_queue *rxq)
+{
+ mvpp2_rxq_drop_pkts(port, rxq);
+
+ rxq->descs = NULL;
+ rxq->last_desc = 0;
+ rxq->next_desc_to_proc = 0;
+ rxq->descs_phys = 0;
+
+ /* Clear Rx descriptors queue starting address and size;
+ * free descriptor number
+ */
+ mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
+ mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
+ mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
+ mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
+}
+
+/* Create and initialize a Tx queue */
+static int mvpp2_txq_init(struct mvpp2_port *port,
+ struct mvpp2_tx_queue *txq)
+{
+ u32 val;
+ int cpu, desc, desc_per_txq, tx_port_num;
+ struct mvpp2_txq_pcpu *txq_pcpu;
+
+ txq->size = port->tx_ring_size;
+
+ /* Allocate memory for Tx descriptors */
+ txq->descs = buffer_loc.tx_descs;
+ txq->descs_phys = (dma_addr_t)buffer_loc.tx_descs;
+ if (!txq->descs)
+ return -ENOMEM;
+
+ /* Make sure descriptor address is cache line size aligned */
+ BUG_ON(txq->descs !=
+ PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
+
+ txq->last_desc = txq->size - 1;
+
+ /* Set Tx descriptors queue starting address - indirect access */
+ mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
+ mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_phys);
+ mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
+ MVPP2_TXQ_DESC_SIZE_MASK);
+ mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
+ mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
+ txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
+ val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
+ val &= ~MVPP2_TXQ_PENDING_MASK;
+ mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
+
+ /* Calculate base address in prefetch buffer. We reserve 16 descriptors
+ * for each existing TXQ.
+ * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
+ * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
+ */
+ desc_per_txq = 16;
+ desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
+ (txq->log_id * desc_per_txq);
+
+ mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
+ MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
+ MVPP2_PREF_BUF_THRESH(desc_per_txq/2));
+
+ /* WRR / EJP configuration - indirect access */
+ tx_port_num = mvpp2_egress_port(port);
+ mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
+
+ val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
+ val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
+ val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
+ val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
+ mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
+
+ val = MVPP2_TXQ_TOKEN_SIZE_MAX;
+ mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
+ val);
+
+ for_each_present_cpu(cpu) {
+ txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
+ txq_pcpu->size = txq->size;
+ }
+
+ return 0;
+}
+
+/* Free allocated TXQ resources */
+static void mvpp2_txq_deinit(struct mvpp2_port *port,
+ struct mvpp2_tx_queue *txq)
+{
+ txq->descs = NULL;
+ txq->last_desc = 0;
+ txq->next_desc_to_proc = 0;
+ txq->descs_phys = 0;
+
+ /* Set minimum bandwidth for disabled TXQs */
+ mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
+
+ /* Set Tx descriptors queue starting address and size */
+ mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
+ mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
+ mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
+}
+
+/* Cleanup Tx ports */
+static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
+{
+ struct mvpp2_txq_pcpu *txq_pcpu;
+ int delay, pending, cpu;
+ u32 val;
+
+ mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
+ val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
+ val |= MVPP2_TXQ_DRAIN_EN_MASK;
+ mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
+
+ /* The napi queue has been stopped so wait for all packets
+ * to be transmitted.
+ */
+ delay = 0;
+ do {
+ if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
+ netdev_warn(port->dev,
+ "port %d: cleaning queue %d timed out\n",
+ port->id, txq->log_id);
+ break;
+ }
+ mdelay(1);
+ delay++;
+
+ pending = mvpp2_txq_pend_desc_num_get(port, txq);
+ } while (pending);
+
+ val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
+ mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
+
+ for_each_present_cpu(cpu) {
+ txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
+
+ /* Release all packets */
+ mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
+
+ /* Reset queue */
+ txq_pcpu->count = 0;
+ txq_pcpu->txq_put_index = 0;
+ txq_pcpu->txq_get_index = 0;
+ }
+}
+
+/* Cleanup all Tx queues */
+static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
+{
+ struct mvpp2_tx_queue *txq;
+ int queue;
+ u32 val;
+
+ val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
+
+ /* Reset Tx ports and delete Tx queues */
+ val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
+ mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
+
+ for (queue = 0; queue < txq_number; queue++) {
+ txq = port->txqs[queue];
+ mvpp2_txq_clean(port, txq);
+ mvpp2_txq_deinit(port, txq);
+ }
+
+ mvpp2_txq_sent_counter_clear(port);
+
+ val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
+ mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
+}
+
+/* Cleanup all Rx queues */
+static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
+{
+ int queue;
+
+ for (queue = 0; queue < rxq_number; queue++)
+ mvpp2_rxq_deinit(port, port->rxqs[queue]);
+}
+
+/* Init all Rx queues for port */
+static int mvpp2_setup_rxqs(struct mvpp2_port *port)
+{
+ int queue, err;
+
+ for (queue = 0; queue < rxq_number; queue++) {
+ err = mvpp2_rxq_init(port, port->rxqs[queue]);
+ if (err)
+ goto err_cleanup;
+ }
+ return 0;
+
+err_cleanup:
+ mvpp2_cleanup_rxqs(port);
+ return err;
+}
+
+/* Init all tx queues for port */
+static int mvpp2_setup_txqs(struct mvpp2_port *port)
+{
+ struct mvpp2_tx_queue *txq;
+ int queue, err;
+
+ for (queue = 0; queue < txq_number; queue++) {
+ txq = port->txqs[queue];
+ err = mvpp2_txq_init(port, txq);
+ if (err)
+ goto err_cleanup;
+ }
+
+ mvpp2_txq_sent_counter_clear(port);
+ return 0;
+
+err_cleanup:
+ mvpp2_cleanup_txqs(port);
+ return err;
+}
+
+/* Adjust link */
+static void mvpp2_link_event(struct mvpp2_port *port)
+{
+ struct phy_device *phydev = port->phy_dev;
+ int status_change = 0;
+ u32 val;
+
+ if (phydev->link) {
+ if ((port->speed != phydev->speed) ||
+ (port->duplex != phydev->duplex)) {
+ u32 val;
+
+ val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+ val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
+ MVPP2_GMAC_CONFIG_GMII_SPEED |
+ MVPP2_GMAC_CONFIG_FULL_DUPLEX |
+ MVPP2_GMAC_AN_SPEED_EN |
+ MVPP2_GMAC_AN_DUPLEX_EN);
+
+ if (phydev->duplex)
+ val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
+
+ if (phydev->speed == SPEED_1000)
+ val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
+ else if (phydev->speed == SPEED_100)
+ val |= MVPP2_GMAC_CONFIG_MII_SPEED;
+
+ writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+
+ port->duplex = phydev->duplex;
+ port->speed = phydev->speed;
+ }
+ }
+
+ if (phydev->link != port->link) {
+ if (!phydev->link) {
+ port->duplex = -1;
+ port->speed = 0;
+ }
+
+ port->link = phydev->link;
+ status_change = 1;
+ }
+
+ if (status_change) {
+ if (phydev->link) {
+ val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+ val |= (MVPP2_GMAC_FORCE_LINK_PASS |
+ MVPP2_GMAC_FORCE_LINK_DOWN);
+ writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+ mvpp2_egress_enable(port);
+ mvpp2_ingress_enable(port);
+ } else {
+ mvpp2_ingress_disable(port);
+ mvpp2_egress_disable(port);
+ }
+ }
+}
+
+/* Main RX/TX processing routines */
+
+/* Display more error info */
+static void mvpp2_rx_error(struct mvpp2_port *port,
+ struct mvpp2_rx_desc *rx_desc)
+{
+ u32 status = rx_desc->status;
+
+ switch (status & MVPP2_RXD_ERR_CODE_MASK) {
+ case MVPP2_RXD_ERR_CRC:
+ netdev_err(port->dev, "bad rx status %08x (crc error), size=%d\n",
+ status, rx_desc->data_size);
+ break;
+ case MVPP2_RXD_ERR_OVERRUN:
+ netdev_err(port->dev, "bad rx status %08x (overrun error), size=%d\n",
+ status, rx_desc->data_size);
+ break;
+ case MVPP2_RXD_ERR_RESOURCE:
+ netdev_err(port->dev, "bad rx status %08x (resource error), size=%d\n",
+ status, rx_desc->data_size);
+ break;
+ }
+}
+
+/* Reuse skb if possible, or allocate a new skb and add it to BM pool */
+static int mvpp2_rx_refill(struct mvpp2_port *port,
+ struct mvpp2_bm_pool *bm_pool,
+ u32 bm, u32 phys_addr)
+{
+ mvpp2_pool_refill(port, bm, phys_addr, phys_addr);
+ return 0;
+}
+
+/* Set hw internals when starting port */
+static void mvpp2_start_dev(struct mvpp2_port *port)
+{
+ mvpp2_gmac_max_rx_size_set(port);
+ mvpp2_txp_max_tx_size_set(port);
+
+ mvpp2_port_enable(port);
+}
+
+/* Set hw internals when stopping port */
+static void mvpp2_stop_dev(struct mvpp2_port *port)
+{
+ /* Stop new packets from arriving to RXQs */
+ mvpp2_ingress_disable(port);
+
+ mvpp2_egress_disable(port);
+ mvpp2_port_disable(port);
+}
+
+static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
+{
+ struct phy_device *phy_dev;
+
+ if (!port->init || port->link == 0) {
+ phy_dev = phy_connect(port->priv->bus, port->phyaddr, dev,
+ port->phy_interface);
+ port->phy_dev = phy_dev;
+ if (!phy_dev) {
+ netdev_err(port->dev, "cannot connect to phy\n");
+ return -ENODEV;
+ }
+ phy_dev->supported &= PHY_GBIT_FEATURES;
+ phy_dev->advertising = phy_dev->supported;
+
+ port->phy_dev = phy_dev;
+ port->link = 0;
+ port->duplex = 0;
+ port->speed = 0;
+
+ phy_config(phy_dev);
+ phy_startup(phy_dev);
+ if (!phy_dev->link) {
+ printf("%s: No link\n", phy_dev->dev->name);
+ return -1;
+ }
+
+ port->init = 1;
+ } else {
+ mvpp2_egress_enable(port);
+ mvpp2_ingress_enable(port);
+ }
+
+ return 0;
+}
+
+static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
+{
+ unsigned char mac_bcast[ETH_ALEN] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+ int err;
+
+ err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
+ if (err) {
+ netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
+ return err;
+ }
+ err = mvpp2_prs_mac_da_accept(port->priv, port->id,
+ port->dev_addr, true);
+ if (err) {
+ netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
+ return err;
+ }
+ err = mvpp2_prs_def_flow(port);
+ if (err) {
+ netdev_err(dev, "mvpp2_prs_def_flow failed\n");
+ return err;
+ }
+
+ /* Allocate the Rx/Tx queues */
+ err = mvpp2_setup_rxqs(port);
+ if (err) {
+ netdev_err(port->dev, "cannot allocate Rx queues\n");
+ return err;
+ }
+
+ err = mvpp2_setup_txqs(port);
+ if (err) {
+ netdev_err(port->dev, "cannot allocate Tx queues\n");
+ return err;
+ }
+
+ err = mvpp2_phy_connect(dev, port);
+ if (err < 0)
+ return err;
+
+ mvpp2_link_event(port);
+
+ mvpp2_start_dev(port);
+
+ return 0;
+}
+
+/* No Device ops here in U-Boot */
+
+/* Driver initialization */
+
+static void mvpp2_port_power_up(struct mvpp2_port *port)
+{
+ mvpp2_port_mii_set(port);
+ mvpp2_port_periodic_xon_disable(port);
+ mvpp2_port_fc_adv_enable(port);
+ mvpp2_port_reset(port);
+}
+
+/* Initialize port HW */
+static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
+{
+ struct mvpp2 *priv = port->priv;
+ struct mvpp2_txq_pcpu *txq_pcpu;
+ int queue, cpu, err;
+
+ if (port->first_rxq + rxq_number > MVPP2_RXQ_TOTAL_NUM)
+ return -EINVAL;
+
+ /* Disable port */
+ mvpp2_egress_disable(port);
+ mvpp2_port_disable(port);
+
+ port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
+ GFP_KERNEL);
+ if (!port->txqs)
+ return -ENOMEM;
+
+ /* Associate physical Tx queues to this port and initialize.
+ * The mapping is predefined.
+ */
+ for (queue = 0; queue < txq_number; queue++) {
+ int queue_phy_id = mvpp2_txq_phys(port->id, queue);
+ struct mvpp2_tx_queue *txq;
+
+ txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
+ if (!txq)
+ return -ENOMEM;
+
+ txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
+ GFP_KERNEL);
+ if (!txq->pcpu)
+ return -ENOMEM;
+
+ txq->id = queue_phy_id;
+ txq->log_id = queue;
+ txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
+ for_each_present_cpu(cpu) {
+ txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
+ txq_pcpu->cpu = cpu;
+ }
+
+ port->txqs[queue] = txq;
+ }
+
+ port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
+ GFP_KERNEL);
+ if (!port->rxqs)
+ return -ENOMEM;
+
+ /* Allocate and initialize Rx queue for this port */
+ for (queue = 0; queue < rxq_number; queue++) {
+ struct mvpp2_rx_queue *rxq;
+
+ /* Map physical Rx queue to port's logical Rx queue */
+ rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
+ if (!rxq)
+ return -ENOMEM;
+ /* Map this Rx queue to a physical queue */
+ rxq->id = port->first_rxq + queue;
+ rxq->port = port->id;
+ rxq->logic_rxq = queue;
+
+ port->rxqs[queue] = rxq;
+ }
+
+ /* Configure Rx queue group interrupt for this port */
+ mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(port->id), CONFIG_MV_ETH_RXQ);
+
+ /* Create Rx descriptor rings */
+ for (queue = 0; queue < rxq_number; queue++) {
+ struct mvpp2_rx_queue *rxq = port->rxqs[queue];
+
+ rxq->size = port->rx_ring_size;
+ rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
+ rxq->time_coal = MVPP2_RX_COAL_USEC;
+ }
+
+ mvpp2_ingress_disable(port);
+
+ /* Port default configuration */
+ mvpp2_defaults_set(port);
+
+ /* Port's classifier configuration */
+ mvpp2_cls_oversize_rxq_set(port);
+ mvpp2_cls_port_config(port);
+
+ /* Provide an initial Rx packet size */
+ port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
+
+ /* Initialize pools for swf */
+ err = mvpp2_swf_bm_pool_init(port);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+/* Ports initialization */
+static int mvpp2_port_probe(struct udevice *dev,
+ struct mvpp2_port *port,
+ int port_node,
+ struct mvpp2 *priv,
+ int *next_first_rxq)
+{
+ int phy_node;
+ u32 id;
+ u32 phyaddr;
+ const char *phy_mode_str;
+ int phy_mode = -1;
+ int priv_common_regs_num = 2;
+ int err;
+
+ phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
+ if (phy_node < 0) {
+ dev_err(&pdev->dev, "missing phy\n");
+ return -ENODEV;
+ }
+
+ phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
+ if (phy_mode_str)
+ phy_mode = phy_get_interface_by_name(phy_mode_str);
+ if (phy_mode == -1) {
+ dev_err(&pdev->dev, "incorrect phy mode\n");
+ return -EINVAL;
+ }
+
+ id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
+ if (id == -1) {
+ dev_err(&pdev->dev, "missing port-id value\n");
+ return -EINVAL;
+ }
+
+ phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
+
+ port->priv = priv;
+ port->id = id;
+ port->first_rxq = *next_first_rxq;
+ port->phy_node = phy_node;
+ port->phy_interface = phy_mode;
+ port->phyaddr = phyaddr;
+
+ port->base = (void __iomem *)dev_get_addr_index(dev->parent,
+ priv_common_regs_num
+ + id);
+ if (IS_ERR(port->base))
+ return PTR_ERR(port->base);
+
+ port->tx_ring_size = MVPP2_MAX_TXD;
+ port->rx_ring_size = MVPP2_MAX_RXD;
+
+ err = mvpp2_port_init(dev, port);
+ if (err < 0) {
+ dev_err(&pdev->dev, "failed to init port %d\n", id);
+ return err;
+ }
+ mvpp2_port_power_up(port);
+
+ /* Increment the first Rx queue number to be used by the next port */
+ *next_first_rxq += CONFIG_MV_ETH_RXQ;
+ priv->port_list[id] = port;
+ return 0;
+}
+
+/* Initialize decoding windows */
+static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
+ struct mvpp2 *priv)
+{
+ u32 win_enable;
+ int i;
+
+ for (i = 0; i < 6; i++) {
+ mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
+ mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
+
+ if (i < 4)
+ mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
+ }
+
+ win_enable = 0;
+
+ for (i = 0; i < dram->num_cs; i++) {
+ const struct mbus_dram_window *cs = dram->cs + i;
+
+ mvpp2_write(priv, MVPP2_WIN_BASE(i),
+ (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
+ dram->mbus_dram_target_id);
+
+ mvpp2_write(priv, MVPP2_WIN_SIZE(i),
+ (cs->size - 1) & 0xffff0000);
+
+ win_enable |= (1 << i);
+ }
+
+ mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
+}
+
+/* Initialize Rx FIFO's */
+static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
+{
+ int port;
+
+ for (port = 0; port < MVPP2_MAX_PORTS; port++) {
+ mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
+ MVPP2_RX_FIFO_PORT_DATA_SIZE);
+ mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
+ MVPP2_RX_FIFO_PORT_ATTR_SIZE);
+ }
+
+ mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
+ MVPP2_RX_FIFO_PORT_MIN_PKT);
+ mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
+}
+
+/* Initialize network controller common part HW */
+static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
+{
+ const struct mbus_dram_target_info *dram_target_info;
+ int err, i;
+ u32 val;
+
+ /* Checks for hardware constraints (U-Boot uses only one rxq) */
+ if ((rxq_number > MVPP2_MAX_RXQ) || (txq_number > MVPP2_MAX_TXQ)) {
+ dev_err(&pdev->dev, "invalid queue size parameter\n");
+ return -EINVAL;
+ }
+
+ /* MBUS windows configuration */
+ dram_target_info = mvebu_mbus_dram_info();
+ if (dram_target_info)
+ mvpp2_conf_mbus_windows(dram_target_info, priv);
+
+ /* Disable HW PHY polling */
+ val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
+ val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
+ writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
+
+ /* Allocate and initialize aggregated TXQs */
+ priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
+ sizeof(struct mvpp2_tx_queue),
+ GFP_KERNEL);
+ if (!priv->aggr_txqs)
+ return -ENOMEM;
+
+ for_each_present_cpu(i) {
+ priv->aggr_txqs[i].id = i;
+ priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
+ err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
+ MVPP2_AGGR_TXQ_SIZE, i, priv);
+ if (err < 0)
+ return err;
+ }
+
+ /* Rx Fifo Init */
+ mvpp2_rx_fifo_init(priv);
+
+ /* Reset Rx queue group interrupt configuration */
+ for (i = 0; i < MVPP2_MAX_PORTS; i++)
+ mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i),
+ CONFIG_MV_ETH_RXQ);
+
+ writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
+ priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
+
+ /* Allow cache snoop when transmiting packets */
+ mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
+
+ /* Buffer Manager initialization */
+ err = mvpp2_bm_init(dev, priv);
+ if (err < 0)
+ return err;
+
+ /* Parser default initialization */
+ err = mvpp2_prs_default_init(dev, priv);
+ if (err < 0)
+ return err;
+
+ /* Classifier default initialization */
+ mvpp2_cls_init(priv);
+
+ return 0;
+}
+
+/* SMI / MDIO functions */
+
+static int smi_wait_ready(struct mvpp2 *priv)
+{
+ u32 timeout = MVPP2_SMI_TIMEOUT;
+ u32 smi_reg;
+
+ /* wait till the SMI is not busy */
+ do {
+ /* read smi register */
+ smi_reg = readl(priv->lms_base + MVPP2_SMI);
+ if (timeout-- == 0) {
+ printf("Error: SMI busy timeout\n");
+ return -EFAULT;
+ }
+ } while (smi_reg & MVPP2_SMI_BUSY);
+
+ return 0;
+}
+
+/*
+ * mpp2_mdio_read - miiphy_read callback function.
+ *
+ * Returns 16bit phy register value, or 0xffff on error
+ */
+static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ struct mvpp2 *priv = bus->priv;
+ u32 smi_reg;
+ u32 timeout;
+
+ /* check parameters */
+ if (addr > MVPP2_PHY_ADDR_MASK) {
+ printf("Error: Invalid PHY address %d\n", addr);
+ return -EFAULT;
+ }
+
+ if (reg > MVPP2_PHY_REG_MASK) {
+ printf("Err: Invalid register offset %d\n", reg);
+ return -EFAULT;
+ }
+
+ /* wait till the SMI is not busy */
+ if (smi_wait_ready(priv) < 0)
+ return -EFAULT;
+
+ /* fill the phy address and regiser offset and read opcode */
+ smi_reg = (addr << MVPP2_SMI_DEV_ADDR_OFFS)
+ | (reg << MVPP2_SMI_REG_ADDR_OFFS)
+ | MVPP2_SMI_OPCODE_READ;
+
+ /* write the smi register */
+ writel(smi_reg, priv->lms_base + MVPP2_SMI);
+
+ /* wait till read value is ready */
+ timeout = MVPP2_SMI_TIMEOUT;
+
+ do {
+ /* read smi register */
+ smi_reg = readl(priv->lms_base + MVPP2_SMI);
+ if (timeout-- == 0) {
+ printf("Err: SMI read ready timeout\n");
+ return -EFAULT;
+ }
+ } while (!(smi_reg & MVPP2_SMI_READ_VALID));
+
+ /* Wait for the data to update in the SMI register */
+ for (timeout = 0; timeout < MVPP2_SMI_TIMEOUT; timeout++)
+ ;
+
+ return readl(priv->lms_base + MVPP2_SMI) & MVPP2_SMI_DATA_MASK;
+}
+
+/*
+ * mpp2_mdio_write - miiphy_write callback function.
+ *
+ * Returns 0 if write succeed, -EINVAL on bad parameters
+ * -ETIME on timeout
+ */
+static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 value)
+{
+ struct mvpp2 *priv = bus->priv;
+ u32 smi_reg;
+
+ /* check parameters */
+ if (addr > MVPP2_PHY_ADDR_MASK) {
+ printf("Error: Invalid PHY address %d\n", addr);
+ return -EFAULT;
+ }
+
+ if (reg > MVPP2_PHY_REG_MASK) {
+ printf("Err: Invalid register offset %d\n", reg);
+ return -EFAULT;
+ }
+
+ /* wait till the SMI is not busy */
+ if (smi_wait_ready(priv) < 0)
+ return -EFAULT;
+
+ /* fill the phy addr and reg offset and write opcode and data */
+ smi_reg = value << MVPP2_SMI_DATA_OFFS;
+ smi_reg |= (addr << MVPP2_SMI_DEV_ADDR_OFFS)
+ | (reg << MVPP2_SMI_REG_ADDR_OFFS);
+ smi_reg &= ~MVPP2_SMI_OPCODE_READ;
+
+ /* write the smi register */
+ writel(smi_reg, priv->lms_base + MVPP2_SMI);
+
+ return 0;
+}
+
+static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct mvpp2_port *port = dev_get_priv(dev);
+ struct mvpp2_rx_desc *rx_desc;
+ struct mvpp2_bm_pool *bm_pool;
+ dma_addr_t phys_addr;
+ u32 bm, rx_status;
+ int pool, rx_bytes, err;
+ int rx_received;
+ struct mvpp2_rx_queue *rxq;
+ u32 cause_rx_tx, cause_rx, cause_misc;
+ u8 *data;
+
+ cause_rx_tx = mvpp2_read(port->priv,
+ MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
+ cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
+ cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
+ if (!cause_rx_tx && !cause_misc)
+ return 0;
+
+ cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
+
+ /* Process RX packets */
+ cause_rx |= port->pending_cause_rx;
+ rxq = mvpp2_get_rx_queue(port, cause_rx);
+
+ /* Get number of received packets and clamp the to-do */
+ rx_received = mvpp2_rxq_received(port, rxq->id);
+
+ /* Return if no packets are received */
+ if (!rx_received)
+ return 0;
+
+ rx_desc = mvpp2_rxq_next_desc_get(rxq);
+ rx_status = rx_desc->status;
+ rx_bytes = rx_desc->data_size - MVPP2_MH_SIZE;
+ phys_addr = rx_desc->buf_phys_addr;
+
+ bm = mvpp2_bm_cookie_build(rx_desc);
+ pool = mvpp2_bm_cookie_pool_get(bm);
+ bm_pool = &port->priv->bm_pools[pool];
+
+ /* Check if buffer header is used */
+ if (rx_status & MVPP2_RXD_BUF_HDR)
+ return 0;
+
+ /* In case of an error, release the requested buffer pointer
+ * to the Buffer Manager. This request process is controlled
+ * by the hardware, and the information about the buffer is
+ * comprised by the RX descriptor.
+ */
+ if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
+ mvpp2_rx_error(port, rx_desc);
+ /* Return the buffer to the pool */
+ mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr,
+ rx_desc->buf_cookie);
+ return 0;
+ }
+
+ err = mvpp2_rx_refill(port, bm_pool, bm, phys_addr);
+ if (err) {
+ netdev_err(port->dev, "failed to refill BM pools\n");
+ return 0;
+ }
+
+ /* Update Rx queue management counters */
+ mb();
+ mvpp2_rxq_status_update(port, rxq->id, 1, 1);
+
+ /* give packet to stack - skip on first n bytes */
+ data = (u8 *)phys_addr + 2 + 32;
+
+ if (rx_bytes <= 0)
+ return 0;
+
+ /*
+ * No cache invalidation needed here, since the rx_buffer's are
+ * located in a uncached memory region
+ */
+ *packetp = data;
+
+ return rx_bytes;
+}
+
+/* Drain Txq */
+static void mvpp2_txq_drain(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
+ int enable)
+{
+ u32 val;
+
+ mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
+ val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
+ if (enable)
+ val |= MVPP2_TXQ_DRAIN_EN_MASK;
+ else
+ val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
+ mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
+}
+
+static int mvpp2_send(struct udevice *dev, void *packet, int length)
+{
+ struct mvpp2_port *port = dev_get_priv(dev);
+ struct mvpp2_tx_queue *txq, *aggr_txq;
+ struct mvpp2_tx_desc *tx_desc;
+ int tx_done;
+ int timeout;
+
+ txq = port->txqs[0];
+ aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
+
+ /* Get a descriptor for the first part of the packet */
+ tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
+ tx_desc->phys_txq = txq->id;
+ tx_desc->data_size = length;
+ tx_desc->packet_offset = (u32)packet & MVPP2_TX_DESC_ALIGN;
+ tx_desc->buf_phys_addr = (u32)packet & ~MVPP2_TX_DESC_ALIGN;
+ /* First and Last descriptor */
+ tx_desc->command = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
+ | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
+
+ /* Flush tx data */
+ flush_dcache_range((u32)packet, (u32)packet + length);
+
+ /* Enable transmit */
+ mb();
+ mvpp2_aggr_txq_pend_desc_add(port, 1);
+
+ mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
+
+ timeout = 0;
+ do {
+ if (timeout++ > 10000) {
+ printf("timeout: packet not sent from aggregated to phys TXQ\n");
+ return 0;
+ }
+ tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
+ } while (tx_done);
+
+ /* Enable TXQ drain */
+ mvpp2_txq_drain(port, txq, 1);
+
+ timeout = 0;
+ do {
+ if (timeout++ > 10000) {
+ printf("timeout: packet not sent\n");
+ return 0;
+ }
+ tx_done = mvpp2_txq_sent_desc_proc(port, txq);
+ } while (!tx_done);
+
+ /* Disable TXQ drain */
+ mvpp2_txq_drain(port, txq, 0);
+
+ return 0;
+}
+
+static int mvpp2_start(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct mvpp2_port *port = dev_get_priv(dev);
+
+ /* Load current MAC address */
+ memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
+
+ /* Reconfigure parser accept the original MAC address */
+ mvpp2_prs_update_mac_da(port, port->dev_addr);
+
+ mvpp2_port_power_up(port);
+
+ mvpp2_open(dev, port);
+
+ return 0;
+}
+
+static void mvpp2_stop(struct udevice *dev)
+{
+ struct mvpp2_port *port = dev_get_priv(dev);
+
+ mvpp2_stop_dev(port);
+ mvpp2_cleanup_rxqs(port);
+ mvpp2_cleanup_txqs(port);
+}
+
+static int mvpp2_probe(struct udevice *dev)
+{
+ struct mvpp2_port *port = dev_get_priv(dev);
+ struct mvpp2 *priv = dev_get_priv(dev->parent);
+ int err;
+
+ /* Initialize network controller */
+ err = mvpp2_init(dev, priv);
+ if (err < 0) {
+ dev_err(&pdev->dev, "failed to initialize controller\n");
+ return err;
+ }
+
+ return mvpp2_port_probe(dev, port, dev->of_offset, priv,
+ &buffer_loc.first_rxq);
+}
+
+static const struct eth_ops mvpp2_ops = {
+ .start = mvpp2_start,
+ .send = mvpp2_send,
+ .recv = mvpp2_recv,
+ .stop = mvpp2_stop,
+};
+
+static struct driver mvpp2_driver = {
+ .name = "mvpp2",
+ .id = UCLASS_ETH,
+ .probe = mvpp2_probe,
+ .ops = &mvpp2_ops,
+ .priv_auto_alloc_size = sizeof(struct mvpp2_port),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+
+/*
+ * Use a MISC device to bind the n instances (child nodes) of the
+ * network base controller in UCLASS_ETH.
+ */
+static int mvpp2_base_probe(struct udevice *dev)
+{
+ struct mvpp2 *priv = dev_get_priv(dev);
+ struct mii_dev *bus;
+ void *bd_space;
+ u32 size = 0;
+ int i;
+
+ /*
+ * U-Boot special buffer handling:
+ *
+ * Allocate buffer area for descs and rx_buffers. This is only
+ * done once for all interfaces. As only one interface can
+ * be active. Make this area DMA-safe by disabling the D-cache
+ */
+
+ /* Align buffer area for descs and rx_buffers to 1MiB */
+ bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
+ mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);
+
+ buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
+ size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
+
+ buffer_loc.tx_descs = (struct mvpp2_tx_desc *)((u32)bd_space + size);
+ size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
+
+ buffer_loc.rx_descs = (struct mvpp2_rx_desc *)((u32)bd_space + size);
+ size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
+
+ for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
+ buffer_loc.bm_pool[i] = (u32 *)((u32)bd_space + size);
+ size += MVPP2_BM_POOL_SIZE_MAX * sizeof(u32);
+ }
+
+ for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
+ buffer_loc.rx_buffer[i] = (u32 *)((u32)bd_space + size);
+ size += RX_BUFFER_SIZE;
+ }
+
+ /* Save base addresses for later use */
+ priv->base = (void *)dev_get_addr_index(dev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->lms_base = (void *)dev_get_addr_index(dev, 1);
+ if (IS_ERR(priv->lms_base))
+ return PTR_ERR(priv->lms_base);
+
+ /* Finally create and register the MDIO bus driver */
+ bus = mdio_alloc();
+ if (!bus) {
+ printf("Failed to allocate MDIO bus\n");
+ return -ENOMEM;
+ }
+
+ bus->read = mpp2_mdio_read;
+ bus->write = mpp2_mdio_write;
+ snprintf(bus->name, sizeof(bus->name), dev->name);
+ bus->priv = (void *)priv;
+ priv->bus = bus;
+
+ return mdio_register(bus);
+}
+
+static int mvpp2_base_bind(struct udevice *parent)
+{
+ const void *blob = gd->fdt_blob;
+ int node = parent->of_offset;
+ struct uclass_driver *drv;
+ struct udevice *dev;
+ struct eth_pdata *plat;
+ char *name;
+ int subnode;
+ u32 id;
+
+ /* Lookup eth driver */
+ drv = lists_uclass_lookup(UCLASS_ETH);
+ if (!drv) {
+ puts("Cannot find eth driver\n");
+ return -ENOENT;
+ }
+
+ fdt_for_each_subnode(blob, subnode, node) {
+ /* Skip disabled ports */
+ if (!fdtdec_get_is_enabled(blob, subnode))
+ continue;
+
+ plat = calloc(1, sizeof(*plat));
+ if (!plat)
+ return -ENOMEM;
+
+ id = fdtdec_get_int(blob, subnode, "port-id", -1);
+
+ name = calloc(1, 16);
+ sprintf(name, "mvpp2-%d", id);
+
+ /* Create child device UCLASS_ETH and bind it */
+ device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
+ dev->of_offset = subnode;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id mvpp2_ids[] = {
+ { .compatible = "marvell,armada-375-pp2" },
+ { }
+};
+
+U_BOOT_DRIVER(mvpp2_base) = {
+ .name = "mvpp2_base",
+ .id = UCLASS_MISC,
+ .of_match = mvpp2_ids,
+ .bind = mvpp2_base_bind,
+ .probe = mvpp2_base_probe,
+ .priv_auto_alloc_size = sizeof(struct mvpp2),
+};
obj-$(CONFIG_PHY_SMSC) += smsc.o
obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
obj-$(CONFIG_PHY_TI) += ti.o
+obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o
obj-$(CONFIG_PHY_VITESSE) += vitesse.o
#ifdef CONFIG_PHY_VITESSE
phy_vitesse_init();
#endif
+#ifdef CONFIG_PHY_XILINX
+ phy_xilinx_init();
+#endif
return 0;
}
*
* Copyright 2010-2011, 2015 Freescale Semiconductor, Inc.
* author Andy Fleming
+ * Copyright 2016 Karsten Merker <merker@debian.org>
*/
#include <config.h>
#include <common.h>
#define PHY_AUTONEGOTIATE_TIMEOUT 5000
+/* RTL8211x 1000BASE-T Control Register */
+#define MIIM_RTL8211x_CTRL1000T_MSCE (1 << 12);
+#define MIIM_RTL8211X_CTRL1000T_MASTER (1 << 11);
+
/* RTL8211x PHY Status Register */
#define MIIM_RTL8211x_PHY_STATUS 0x11
#define MIIM_RTL8211x_PHYSTAT_SPEED 0xc000
*/
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER,
MIIM_RTL8211x_PHY_INTR_DIS);
-
+#ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER
+ unsigned int reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
+ /* force manual master/slave configuration */
+ reg |= MIIM_RTL8211x_CTRL1000T_MSCE;
+ /* force master mode */
+ reg |= MIIM_RTL8211X_CTRL1000T_MASTER;
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
+#endif
/* read interrupt status just to clear it */
phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
/* Support for RTL8211B PHY */
static struct phy_driver RTL8211B_driver = {
.name = "RealTek RTL8211B",
- .uid = 0x1cc910,
+ .uid = 0x1cc912,
.mask = 0xffffff,
.features = PHY_GBIT_FEATURES,
.config = &rtl8211x_config,
#define MII_DP83867_PHYCTRL 0x10
#define MII_DP83867_MICR 0x12
+#define MII_DP83867_CFG2 0x14
+#define MII_DP83867_BISCR 0x16
#define DP83867_CTRL 0x1f
/* Extended Registers */
#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
#define DP83867_MDI_CROSSOVER 5
#define DP83867_MDI_CROSSOVER_AUTO 2
+#define DP83867_MDI_CROSSOVER_MDIX 2
+#define DP83867_PHYCTRL_SGMIIEN 0x0800
+#define DP83867_PHYCTRL_RXFIFO_SHIFT 12
+#define DP83867_PHYCTRL_TXFIFO_SHIFT 14
/* RGMIIDCTL bits */
#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
+/* CFG2 bits */
+#define MII_DP83867_CFG2_SPEEDOPT_10EN 0x0040
+#define MII_DP83867_CFG2_SGMII_AUTONEGEN 0x0080
+#define MII_DP83867_CFG2_SPEEDOPT_ENH 0x0100
+#define MII_DP83867_CFG2_SPEEDOPT_CNT 0x0800
+#define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000
+#define MII_DP83867_CFG2_MASK 0x003F
+
#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
#define MII_MMD_DATA 0x0e /* MMD Access Data Register */
static int dp83867_config(struct phy_device *phydev)
{
- unsigned int val, delay;
+ unsigned int val, delay, cfg2;
int ret;
/* Restart the PHY. */
(FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
if (ret)
return ret;
+ } else {
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
+ (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
+
+ cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
+ cfg2 &= MII_DP83867_CFG2_MASK;
+ cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
+ MII_DP83867_CFG2_SGMII_AUTONEGEN |
+ MII_DP83867_CFG2_SPEEDOPT_ENH |
+ MII_DP83867_CFG2_SPEEDOPT_CNT |
+ MII_DP83867_CFG2_SPEEDOPT_INTLOW);
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
+
+ phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
+ DP83867_DEVADDR, phydev->addr, 0x0);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
+ DP83867_PHYCTRL_SGMIIEN |
+ (DP83867_MDI_CROSSOVER_MDIX <<
+ DP83867_MDI_CROSSOVER) |
+ (FIFO_DEPTH << DP83867_PHYCTRL_RXFIFO_SHIFT) |
+ (FIFO_DEPTH << DP83867_PHYCTRL_TXFIFO_SHIFT));
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
}
if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
--- /dev/null
+/*
+ * Xilinx PCS/PMA Core phy driver
+ *
+ * Copyright (C) 2015 - 2016 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <phy.h>
+#include <dm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MII_PHY_STATUS_SPD_MASK 0x0C00
+#define MII_PHY_STATUS_FULLDUPLEX 0x1000
+#define MII_PHY_STATUS_1000 0x0800
+#define MII_PHY_STATUS_100 0x0400
+#define XPCSPMA_PHY_CTRL_ISOLATE_DISABLE 0xFBFF
+
+/* Mask used for ID comparisons */
+#define XILINX_PHY_ID_MASK 0xfffffff0
+
+/* Known PHY IDs */
+#define XILINX_PHY_ID 0x01740c00
+
+/* struct phy_device dev_flags definitions */
+#define XAE_PHY_TYPE_MII 0
+#define XAE_PHY_TYPE_GMII 1
+#define XAE_PHY_TYPE_RGMII_1_3 2
+#define XAE_PHY_TYPE_RGMII_2_0 3
+#define XAE_PHY_TYPE_SGMII 4
+#define XAE_PHY_TYPE_1000BASE_X 5
+
+static int xilinxphy_startup(struct phy_device *phydev)
+{
+ int err;
+ int status = 0;
+
+ debug("%s\n", __func__);
+ /* Update the link, but return if there
+ * was an error
+ */
+ err = genphy_update_link(phydev);
+ if (err)
+ return err;
+
+ if (AUTONEG_ENABLE == phydev->autoneg) {
+ status = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);
+ status = status & MII_PHY_STATUS_SPD_MASK;
+
+ if (status & MII_PHY_STATUS_FULLDUPLEX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+
+ switch (status) {
+ case MII_PHY_STATUS_1000:
+ phydev->speed = SPEED_1000;
+ break;
+
+ case MII_PHY_STATUS_100:
+ phydev->speed = SPEED_100;
+ break;
+
+ default:
+ phydev->speed = SPEED_10;
+ break;
+ }
+ } else {
+ int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
+
+ if (bmcr < 0)
+ return bmcr;
+
+ if (bmcr & BMCR_FULLDPLX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+
+ if (bmcr & BMCR_SPEED1000)
+ phydev->speed = SPEED_1000;
+ else if (bmcr & BMCR_SPEED100)
+ phydev->speed = SPEED_100;
+ else
+ phydev->speed = SPEED_10;
+ }
+
+ /*
+ * For 1000BASE-X Phy Mode the speed/duplex will always be
+ * 1000Mbps/fullduplex
+ */
+ if (phydev->flags == XAE_PHY_TYPE_1000BASE_X) {
+ phydev->duplex = DUPLEX_FULL;
+ phydev->speed = SPEED_1000;
+ }
+
+ return 0;
+}
+
+static int xilinxphy_of_init(struct phy_device *phydev)
+{
+ struct udevice *dev = (struct udevice *)&phydev->dev;
+ u32 phytype;
+
+ debug("%s\n", __func__);
+ phytype = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "phy-type", -1);
+ if (phytype == XAE_PHY_TYPE_1000BASE_X)
+ phydev->flags |= XAE_PHY_TYPE_1000BASE_X;
+
+ return 0;
+}
+
+static int xilinxphy_config(struct phy_device *phydev)
+{
+ int temp;
+
+ debug("%s\n", __func__);
+ xilinxphy_of_init(phydev);
+ temp = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
+ temp &= XPCSPMA_PHY_CTRL_ISOLATE_DISABLE;
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, temp);
+
+ return 0;
+}
+
+static struct phy_driver xilinxphy_driver = {
+ .uid = XILINX_PHY_ID,
+ .mask = XILINX_PHY_ID_MASK,
+ .name = "Xilinx PCS/PMA PHY",
+ .features = PHY_GBIT_FEATURES,
+ .config = &xilinxphy_config,
+ .startup = &xilinxphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+int phy_xilinx_init(void)
+{
+ debug("%s\n", __func__);
+ phy_register(&xilinxphy_driver);
+
+ return 0;
+}
/* Force RTL8169 in 10/100/1000 Full/Half mode. */
if (option > 0) {
#ifdef DEBUG_RTL8169
- printf("%s: Force-mode Enabled.\n", dev->name);
+ printf("%s: Force-mode Enabled.\n", name);
#endif
Cap10_100 = 0, Cap1000 = 0;
switch (option) {
} else {
#ifdef DEBUG_RTL8169
printf("%s: Auto-negotiation Enabled.\n",
- dev->name);
+ name);
#endif
/* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
mdio_write(PHY_AUTO_NEGO_REG,
if (option & _1000bpsF) {
#ifdef DEBUG_RTL8169
printf("%s: 1000Mbps Full-duplex operation.\n",
- dev->name);
+ name);
#endif
} else {
#ifdef DEBUG_RTL8169
printf("%s: %sMbps %s-duplex operation.\n",
- dev->name,
+ name,
(option & _100bps) ? "100" :
"10",
(option & FullDup) ? "Full" :
#ifdef DEBUG_RTL8169
printf
("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
- dev->name,
+ name,
(RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
#endif
}
struct vsc9953_analyzer *l2ana_reg;
/* Administrative down */
- if (vsc9953_l2sw.port[port_nr].enabled) {
+ if (!vsc9953_l2sw.port[port_nr].enabled) {
printf("Port %d is administrative down\n", port_nr);
return -1;
}
if (vsc9953_port_init(i))
printf("Failed to initialize l2switch port %d\n", i);
+ if (!vsc9953_l2sw.port[i].enabled)
+ continue;
+
/* Enable VSC9953 GMII Ports Port ID 0 - 7 */
if (VSC9953_INTERNAL_PORT_CHECK(i)) {
out_le32(&l2ana_reg->pfc[i].pfc_cfg,
out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i],
VSC9953_MAC_FC_CFG);
}
+
+ l2dev_gmii_reg = (struct vsc9953_dev_gmii *)
+ (VSC9953_OFFSET + VSC9953_DEV_GMII_OFFSET +
+ T1040_SWITCH_GMII_DEV_OFFSET * i);
+
out_le32(&l2dev_gmii_reg->port_mode.clock_cfg,
VSC9953_CLOCK_CFG);
out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ena_cfg,
/* WAIT FOR 2 us*/
udelay(2);
- l2dev_gmii_reg = (struct vsc9953_dev_gmii *)(
- (char *)l2dev_gmii_reg
- + T1040_SWITCH_GMII_DEV_OFFSET);
-
/* Initialize Lynx PHY Wrappers */
phy_addr = 0;
if (vsc9953_l2sw.port[i].enet_if ==
}
/* Interface - look at tsec */
- phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
+ phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
phydev->supported &= supported;
phydev->advertising = phydev->supported;
/* Setting axi emac and phy to proper setting */
static int setup_phy(struct udevice *dev)
{
- u32 speed, emmc_reg;
+ u16 temp;
+ u32 speed, emmc_reg, ret;
struct axidma_priv *priv = dev_get_priv(dev);
struct axi_regs *regs = priv->iobase;
struct phy_device *phydev = priv->phydev;
+ if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
+ /*
+ * In SGMII cases the isolate bit might set
+ * after DMA and ethernet resets and hence
+ * check and clear if set.
+ */
+ ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp);
+ if (ret)
+ return 0;
+ if (temp & BMCR_ISOLATE) {
+ temp &= ~BMCR_ISOLATE;
+ ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
+ if (ret)
+ return 0;
+ }
+ }
+
if (phy_startup(phydev)) {
printf("axiemac: could not initialize PHY %s\n",
phydev->dev->name);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
- debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
return -EINVAL;
}
priv->interface = pdata->phy_interface;
#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
+#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x080000000 /* SGMII Enable */
+#define ZYNQ_GEM_NWCFG_PCS_SEL 0x000000800 /* PCS select */
#ifdef CONFIG_ARM64
#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000100000 /* Div pclk by 64, max 160MHz */
#else
#define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
+#define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
+
/* Use MII register 1 (MII status register) to detect PHY */
#define PHY_DETECT_REG 1
u32 reserved6[18];
#define STAT_SIZE 44
u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
- u32 reserved7[164];
+ u32 reserved9[20];
+ u32 pcscntrl;
+ u32 reserved7[143];
u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
u32 reserved8[15];
u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
/* Enable only MDIO bus */
writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl);
- ret = phy_detection(dev);
- if (ret) {
- printf("GEM PHY init failed\n");
- return ret;
+ if (priv->interface != PHY_INTERFACE_MODE_SGMII) {
+ ret = phy_detection(dev);
+ if (ret) {
+ printf("GEM PHY init failed\n");
+ return ret;
+ }
}
priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
static int zynq_gem_init(struct udevice *dev)
{
- u32 i;
+ u32 i, nwconfig;
unsigned long clk_rate = 0;
struct zynq_gem_priv *priv = dev_get_priv(dev);
struct zynq_gem_regs *regs = priv->iobase;
return -1;
}
+ nwconfig = ZYNQ_GEM_NWCFG_INIT;
+
+ if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
+ nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
+ ZYNQ_GEM_NWCFG_PCS_SEL;
+#ifdef CONFIG_ARM64
+ writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
+ ®s->pcscntrl);
+#endif
+ }
+
switch (priv->phydev->speed) {
case SPEED_1000:
- writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
+ writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
®s->nwcfg);
clk_rate = ZYNQ_GEM_FREQUENCY_1000;
break;
case SPEED_100:
- writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100,
+ writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
®s->nwcfg);
clk_rate = ZYNQ_GEM_FREQUENCY_100;
break;
ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
}
+__weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
+{
+ return -ENOSYS;
+}
+
+static int zynq_gem_read_rom_mac(struct udevice *dev)
+{
+ int retval;
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ retval = zynq_board_read_rom_ethaddr(pdata->enetaddr);
+ if (retval == -ENOSYS)
+ retval = 0;
+
+ return retval;
+}
+
static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
int devad, int reg)
{
if (ret)
return ret;
- zynq_phy_init(dev);
-
- return 0;
+ return zynq_phy_init(dev);
}
static int zynq_gem_remove(struct udevice *dev)
.free_pkt = zynq_gem_free_pkt,
.stop = zynq_gem_halt,
.write_hwaddr = zynq_gem_setup_mac,
+ .read_rom_hwaddr = zynq_gem_read_rom_mac,
};
static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
}
priv->interface = pdata->phy_interface;
+ priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio");
+
printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
void __iomem *dbi;
void __iomem *va_cfg0;
void __iomem *va_cfg1;
+ int next_lut_index;
struct pci_controller hose;
};
}
}
+#ifdef CONFIG_FSL_LSCH3
+/*
+ * Return next available LUT index.
+ */
+static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
+{
+ if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
+ return pcie->next_lut_index++;
+ else
+ return -1; /* LUT is full */
+}
+
+/*
+ * Program a single LUT entry
+ */
+static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
+ u32 streamid)
+{
+ void __iomem *lut;
+
+ lut = pcie->dbi + PCIE_LUT_BASE;
+
+ /* leave mask as all zeroes, want to match all bits */
+ writel((devid << 16), lut + PCIE_LUT_UDR(index));
+ writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index));
+}
+
+/* returns the next available streamid */
+static u32 ls_pcie_next_streamid(void)
+{
+ static int next_stream_id = FSL_PEX_STREAM_ID_START;
+
+ if (next_stream_id > FSL_PEX_STREAM_ID_END)
+ return 0xffffffff;
+
+ return next_stream_id++;
+}
+
+/*
+ * An msi-map is a property to be added to the pci controller
+ * node. It is a table, where each entry consists of 4 fields
+ * e.g.:
+ *
+ * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
+ * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
+ */
+static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
+ u32 devid, u32 streamid)
+{
+ char pcie_path[19];
+ u32 *prop;
+ u32 phandle;
+ int nodeoffset;
+
+ /* find pci controller node */
+ snprintf(pcie_path, sizeof(pcie_path), "/soc/pcie@%llx",
+ (u64)pcie->dbi);
+ nodeoffset = fdt_path_offset(blob, pcie_path);
+ if (nodeoffset < 0) {
+ printf("\n%s: ERROR: unable to update PCIe node: %s\n",
+ __func__, pcie_path);
+ return;
+ }
+
+ /* get phandle to MSI controller */
+ prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
+ if (prop == NULL) {
+ printf("\n%s: ERROR: missing msi-parent: %s\n", __func__,
+ pcie_path);
+ return;
+ }
+ phandle = be32_to_cpu(*prop);
+
+ /* set one msi-map row */
+ fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
+ fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
+ fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
+ fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
+}
+
+static void fdt_fixup_pcie(void *blob)
+{
+ unsigned int found_multi = 0;
+ unsigned char header_type;
+ int index;
+ u32 streamid;
+ pci_dev_t dev;
+ int bus;
+ unsigned short id;
+ struct pci_controller *hose;
+ struct ls_pcie *pcie;
+ int i;
+
+ for (i = 0, hose = pci_get_hose_head(); hose; hose = hose->next, i++) {
+ pcie = hose->priv_data;
+ for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
+
+ for (dev = PCI_BDF(bus, 0, 0);
+ dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
+ PCI_MAX_PCI_FUNCTIONS - 1);
+ dev += PCI_BDF(0, 0, 1)) {
+
+ if (PCI_FUNC(dev) && !found_multi)
+ continue;
+
+ pci_read_config_word(dev, PCI_VENDOR_ID, &id);
+
+ pci_read_config_byte(dev, PCI_HEADER_TYPE,
+ &header_type);
+
+ if ((id == 0xFFFF) || (id == 0x0000))
+ continue;
+
+ if (!PCI_FUNC(dev))
+ found_multi = header_type & 0x80;
+
+ streamid = ls_pcie_next_streamid();
+ if (streamid == 0xffffffff) {
+ printf("ERROR: no stream ids free\n");
+ continue;
+ }
+
+ index = ls_pcie_next_lut_index(pcie);
+ if (index < 0) {
+ printf("ERROR: no LUT indexes free\n");
+ continue;
+ }
+
+ /* map PCI b.d.f to streamID in LUT */
+ ls_pcie_lut_set_mapping(pcie, index, dev >> 8,
+ streamid);
+
+ /* update msi-map in device tree */
+ fdt_pcie_set_msi_map_entry(blob, pcie, dev >> 8,
+ streamid);
+ }
+ }
+ }
+}
+#endif
+
int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
{
struct ls_pcie *pcie;
pcie->va_cfg1 = map_physmem(info->cfg1_phys,
info->cfg1_size,
MAP_NOCACHE);
+ pcie->next_lut_index = 0;
/* outbound memory */
pci_set_region(&hose->regions[0],
#ifdef CONFIG_PCIE4
ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4);
#endif
+
+ #ifdef CONFIG_FSL_LSCH3
+ fdt_fixup_pcie(blob);
+ #endif
}
#else
{
}
#endif
-
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
-
-void pcie_set_available_streamids(void *blob, const char *pcie_path,
- u32 *stream_ids, int count)
-{
- int nodeoffset;
- int i;
-
- nodeoffset = fdt_path_offset(blob, pcie_path);
- if (nodeoffset < 0) {
- printf("\n%s: ERROR: unable to update PCIe node\n", __func__);
- return;
- }
-
- /* for each stream ID, append to mmu-masters */
- for (i = 0; i < count; i++) {
- fdt_appendprop_u32(blob, nodeoffset, "available-stream-ids",
- stream_ids[i]);
- }
-}
-
-#define MAX_STREAM_IDS 4
-void fdt_fixup_smmu_pcie(void *blob)
-{
- int count;
- u32 stream_ids[MAX_STREAM_IDS];
- u32 ctlr_streamid = 0x300;
-
- #ifdef CONFIG_PCIE1
- /* PEX1 stream ID fixup */
- count = FSL_PEX1_STREAM_ID_END - FSL_PEX1_STREAM_ID_START + 1;
- alloc_stream_ids(FSL_PEX1_STREAM_ID_START, count, stream_ids,
- MAX_STREAM_IDS);
- pcie_set_available_streamids(blob, "/pcie@3400000", stream_ids, count);
- append_mmu_masters(blob, "/iommu@5000000", "/pcie@3400000",
- &ctlr_streamid, 1);
- #endif
-
- #ifdef CONFIG_PCIE2
- /* PEX2 stream ID fixup */
- count = FSL_PEX2_STREAM_ID_END - FSL_PEX2_STREAM_ID_START + 1;
- alloc_stream_ids(FSL_PEX2_STREAM_ID_START, count, stream_ids,
- MAX_STREAM_IDS);
- pcie_set_available_streamids(blob, "/pcie@3500000", stream_ids, count);
- append_mmu_masters(blob, "/iommu@5000000", "/pcie@3500000",
- &ctlr_streamid, 1);
- #endif
-
- #ifdef CONFIG_PCIE3
- /* PEX3 stream ID fixup */
- count = FSL_PEX3_STREAM_ID_END - FSL_PEX3_STREAM_ID_START + 1;
- alloc_stream_ids(FSL_PEX3_STREAM_ID_START, count, stream_ids,
- MAX_STREAM_IDS);
- pcie_set_available_streamids(blob, "/pcie@3600000", stream_ids, count);
- append_mmu_masters(blob, "/iommu@5000000", "/pcie@3600000",
- &ctlr_streamid, 1);
- #endif
-
- #ifdef CONFIG_PCIE4
- /* PEX4 stream ID fixup */
- count = FSL_PEX4_STREAM_ID_END - FSL_PEX4_STREAM_ID_START + 1;
- alloc_stream_ids(FSL_PEX4_STREAM_ID_START, count, stream_ids,
- MAX_STREAM_IDS);
- pcie_set_available_streamids(blob, "/pcie@3700000", stream_ids, count);
- append_mmu_masters(blob, "/iommu@5000000", "/pcie@3700000",
- &ctlr_streamid, 1);
- #endif
-}
-#endif
config PINCTRL_UNIPHIER
bool
-config PINCTRL_UNIPHIER_PH1_LD4
+config PINCTRL_UNIPHIER_LD4
bool "UniPhier PH1-LD4 SoC pinctrl driver"
- depends on ARCH_UNIPHIER_PH1_LD4
+ depends on ARCH_UNIPHIER_LD4
default y
select PINCTRL_UNIPHIER
-config PINCTRL_UNIPHIER_PH1_PRO4
+config PINCTRL_UNIPHIER_PRO4
bool "UniPhier PH1-Pro4 SoC pinctrl driver"
- depends on ARCH_UNIPHIER_PH1_PRO4
+ depends on ARCH_UNIPHIER_PRO4
default y
select PINCTRL_UNIPHIER
-config PINCTRL_UNIPHIER_PH1_SLD8
+config PINCTRL_UNIPHIER_SLD8
bool "UniPhier PH1-sLD8 SoC pinctrl driver"
- depends on ARCH_UNIPHIER_PH1_SLD8
+ depends on ARCH_UNIPHIER_SLD8
default y
select PINCTRL_UNIPHIER
-config PINCTRL_UNIPHIER_PH1_PRO5
+config PINCTRL_UNIPHIER_PRO5
bool "UniPhier PH1-Pro5 SoC pinctrl driver"
- depends on ARCH_UNIPHIER_PH1_PRO5
+ depends on ARCH_UNIPHIER_PRO5
default y
select PINCTRL_UNIPHIER
-config PINCTRL_UNIPHIER_PROXSTREAM2
+config PINCTRL_UNIPHIER_PXS2
bool "UniPhier ProXstream2 SoC pinctrl driver"
- depends on ARCH_UNIPHIER_PROXSTREAM2
+ depends on ARCH_UNIPHIER_PXS2
default y
select PINCTRL_UNIPHIER
-config PINCTRL_UNIPHIER_PH1_LD6B
+config PINCTRL_UNIPHIER_LD6B
bool "UniPhier PH1-LD6b SoC pinctrl driver"
- depends on ARCH_UNIPHIER_PH1_LD6B
+ depends on ARCH_UNIPHIER_LD6B
+ default y
+ select PINCTRL_UNIPHIER
+
+config PINCTRL_UNIPHIER_LD20
+ bool "UniPhier PH1-LD11/PH1-LD20 SoC pinctrl driver"
+ depends on ARCH_UNIPHIER_LD11 || ARCH_UNIPHIER_LD20
default y
select PINCTRL_UNIPHIER
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += pinctrl-uniphier-core.o
+obj-y += pinctrl-uniphier-core.o
-obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o
-obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o
-obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o
-obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO5) += pinctrl-ph1-pro5.o
-obj-$(CONFIG_PINCTRL_UNIPHIER_PROXSTREAM2) += pinctrl-proxstream2.o
-obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD6B) += pinctrl-ph1-ld6b.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_LD4) += pinctrl-uniphier-ld4.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PRO4) += pinctrl-uniphier-pro4.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8) += pinctrl-uniphier-sld8.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PRO5) += pinctrl-uniphier-pro5.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PXS2) += pinctrl-uniphier-pxs2.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_LD6B) += pinctrl-uniphier-ld6b.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_LD20) += pinctrl-uniphier-ld20.o
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <dm/device.h>
-#include <dm/pinctrl.h>
-
-#include "pinctrl-uniphier.h"
-
-static const struct uniphier_pinctrl_pin ph1_ld4_pins[] = {
- UNIPHIER_PINCTRL_PIN(53, 0),
- UNIPHIER_PINCTRL_PIN(54, 0),
- UNIPHIER_PINCTRL_PIN(55, 0),
- UNIPHIER_PINCTRL_PIN(56, 0),
- UNIPHIER_PINCTRL_PIN(67, 0),
- UNIPHIER_PINCTRL_PIN(68, 0),
- UNIPHIER_PINCTRL_PIN(69, 0),
- UNIPHIER_PINCTRL_PIN(70, 0),
- UNIPHIER_PINCTRL_PIN(85, 0),
- UNIPHIER_PINCTRL_PIN(88, 0),
- UNIPHIER_PINCTRL_PIN(156, 0),
-};
-
-static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
-static const unsigned emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1};
-static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
-static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
-static const unsigned i2c0_pins[] = {102, 103};
-static const unsigned i2c0_muxvals[] = {0, 0};
-static const unsigned i2c1_pins[] = {104, 105};
-static const unsigned i2c1_muxvals[] = {0, 0};
-static const unsigned i2c2_pins[] = {108, 109};
-static const unsigned i2c2_muxvals[] = {2, 2};
-static const unsigned i2c3_pins[] = {108, 109};
-static const unsigned i2c3_muxvals[] = {3, 3};
-static const unsigned nand_pins[] = {24, 25, 26, 27, 28, 29, 30, 31, 158, 159,
- 160, 161, 162, 163, 164};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0};
-static const unsigned nand_cs1_pins[] = {22, 23};
-static const unsigned nand_cs1_muxvals[] = {0, 0};
-static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
-static const unsigned uart0_pins[] = {85, 88};
-static const unsigned uart0_muxvals[] = {1, 1};
-static const unsigned uart1_pins[] = {155, 156};
-static const unsigned uart1_muxvals[] = {13, 13};
-static const unsigned uart1b_pins[] = {69, 70};
-static const unsigned uart1b_muxvals[] = {23, 23};
-static const unsigned uart2_pins[] = {128, 129};
-static const unsigned uart2_muxvals[] = {13, 13};
-static const unsigned uart3_pins[] = {110, 111};
-static const unsigned uart3_muxvals[] = {1, 1};
-static const unsigned usb0_pins[] = {53, 54};
-static const unsigned usb0_muxvals[] = {0, 0};
-static const unsigned usb1_pins[] = {55, 56};
-static const unsigned usb1_muxvals[] = {0, 0};
-static const unsigned usb2_pins[] = {155, 156};
-static const unsigned usb2_muxvals[] = {4, 4};
-static const unsigned usb2b_pins[] = {67, 68};
-static const unsigned usb2b_muxvals[] = {23, 23};
-
-static const struct uniphier_pinctrl_group ph1_ld4_groups[] = {
- UNIPHIER_PINCTRL_GROUP(emmc),
- UNIPHIER_PINCTRL_GROUP(emmc_dat8),
- UNIPHIER_PINCTRL_GROUP(i2c0),
- UNIPHIER_PINCTRL_GROUP(i2c1),
- UNIPHIER_PINCTRL_GROUP(i2c2),
- UNIPHIER_PINCTRL_GROUP(i2c3),
- UNIPHIER_PINCTRL_GROUP(nand),
- UNIPHIER_PINCTRL_GROUP(nand_cs1),
- UNIPHIER_PINCTRL_GROUP(sd),
- UNIPHIER_PINCTRL_GROUP(uart0),
- UNIPHIER_PINCTRL_GROUP(uart1),
- UNIPHIER_PINCTRL_GROUP(uart1b),
- UNIPHIER_PINCTRL_GROUP(uart2),
- UNIPHIER_PINCTRL_GROUP(uart3),
- UNIPHIER_PINCTRL_GROUP(usb0),
- UNIPHIER_PINCTRL_GROUP(usb1),
- UNIPHIER_PINCTRL_GROUP(usb2),
- UNIPHIER_PINCTRL_GROUP(usb2b),
-};
-
-static const char * const ph1_ld4_functions[] = {
- "emmc",
- "i2c0",
- "i2c1",
- "i2c2",
- "i2c3",
- "nand",
- "sd",
- "uart0",
- "uart1",
- "uart2",
- "uart3",
- "usb0",
- "usb1",
- "usb2",
-};
-
-static struct uniphier_pinctrl_socdata ph1_ld4_pinctrl_socdata = {
- .pins = ph1_ld4_pins,
- .pins_count = ARRAY_SIZE(ph1_ld4_pins),
- .groups = ph1_ld4_groups,
- .groups_count = ARRAY_SIZE(ph1_ld4_groups),
- .functions = ph1_ld4_functions,
- .functions_count = ARRAY_SIZE(ph1_ld4_functions),
- .mux_bits = 8,
- .reg_stride = 4,
- .load_pinctrl = false,
-};
-
-static int ph1_ld4_pinctrl_probe(struct udevice *dev)
-{
- return uniphier_pinctrl_probe(dev, &ph1_ld4_pinctrl_socdata);
-}
-
-static const struct udevice_id ph1_ld4_pinctrl_match[] = {
- { .compatible = "socionext,ph1-ld4-pinctrl" },
- { /* sentinel */ }
-};
-
-U_BOOT_DRIVER(ph1_ld4_pinctrl) = {
- .name = "ph1-ld4-pinctrl",
- .id = UCLASS_PINCTRL,
- .of_match = of_match_ptr(ph1_ld4_pinctrl_match),
- .probe = ph1_ld4_pinctrl_probe,
- .remove = uniphier_pinctrl_remove,
- .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
- .ops = &uniphier_pinctrl_ops,
-};
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <dm/device.h>
-#include <dm/pinctrl.h>
-
-#include "pinctrl-uniphier.h"
-
-static const struct uniphier_pinctrl_pin ph1_ld6b_pins[] = {
- UNIPHIER_PINCTRL_PIN(113, 0),
- UNIPHIER_PINCTRL_PIN(114, 0),
- UNIPHIER_PINCTRL_PIN(115, 0),
- UNIPHIER_PINCTRL_PIN(116, 0),
- UNIPHIER_PINCTRL_PIN(217, 0),
- UNIPHIER_PINCTRL_PIN(218, 0),
- UNIPHIER_PINCTRL_PIN(219, 0),
- UNIPHIER_PINCTRL_PIN(220, 0),
-};
-
-static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
-static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
-static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
-static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
-static const unsigned i2c0_pins[] = {109, 110};
-static const unsigned i2c0_muxvals[] = {0, 0};
-static const unsigned i2c1_pins[] = {111, 112};
-static const unsigned i2c1_muxvals[] = {0, 0};
-static const unsigned i2c2_pins[] = {115, 116};
-static const unsigned i2c2_muxvals[] = {1, 1};
-static const unsigned i2c3_pins[] = {118, 119};
-static const unsigned i2c3_muxvals[] = {1, 1};
-static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
- 42, 43, 44, 45, 46};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0};
-static const unsigned nand_cs1_pins[] = {37, 38};
-static const unsigned nand_cs1_muxvals[] = {0, 0};
-static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
-static const unsigned uart0_pins[] = {135, 136};
-static const unsigned uart0_muxvals[] = {3, 3};
-static const unsigned uart0b_pins[] = {11, 12};
-static const unsigned uart0b_muxvals[] = {2, 2};
-static const unsigned uart1_pins[] = {115, 116};
-static const unsigned uart1_muxvals[] = {0, 0};
-static const unsigned uart1b_pins[] = {113, 114};
-static const unsigned uart1b_muxvals[] = {1, 1};
-static const unsigned uart2_pins[] = {113, 114};
-static const unsigned uart2_muxvals[] = {2, 2};
-static const unsigned uart2b_pins[] = {86, 87};
-static const unsigned uart2b_muxvals[] = {1, 1};
-static const unsigned usb0_pins[] = {56, 57};
-static const unsigned usb0_muxvals[] = {0, 0};
-static const unsigned usb1_pins[] = {58, 59};
-static const unsigned usb1_muxvals[] = {0, 0};
-static const unsigned usb2_pins[] = {60, 61};
-static const unsigned usb2_muxvals[] = {0, 0};
-static const unsigned usb3_pins[] = {62, 63};
-static const unsigned usb3_muxvals[] = {0, 0};
-
-static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = {
- UNIPHIER_PINCTRL_GROUP(emmc),
- UNIPHIER_PINCTRL_GROUP(emmc_dat8),
- UNIPHIER_PINCTRL_GROUP(i2c0),
- UNIPHIER_PINCTRL_GROUP(i2c1),
- UNIPHIER_PINCTRL_GROUP(i2c2),
- UNIPHIER_PINCTRL_GROUP(i2c3),
- UNIPHIER_PINCTRL_GROUP(nand),
- UNIPHIER_PINCTRL_GROUP(nand_cs1),
- UNIPHIER_PINCTRL_GROUP(sd),
- UNIPHIER_PINCTRL_GROUP(uart0),
- UNIPHIER_PINCTRL_GROUP(uart0b),
- UNIPHIER_PINCTRL_GROUP(uart1),
- UNIPHIER_PINCTRL_GROUP(uart1b),
- UNIPHIER_PINCTRL_GROUP(uart2),
- UNIPHIER_PINCTRL_GROUP(uart2b),
- UNIPHIER_PINCTRL_GROUP(usb0),
- UNIPHIER_PINCTRL_GROUP(usb1),
- UNIPHIER_PINCTRL_GROUP(usb2),
- UNIPHIER_PINCTRL_GROUP(usb3),
-};
-
-static const char * const ph1_ld6b_functions[] = {
- "emmc",
- "i2c0",
- "i2c1",
- "i2c2",
- "i2c3",
- "nand",
- "sd",
- "uart0",
- "uart1",
- "uart2",
- "usb0",
- "usb1",
- "usb2",
- "usb3",
-};
-
-static struct uniphier_pinctrl_socdata ph1_ld6b_pinctrl_socdata = {
- .pins = ph1_ld6b_pins,
- .pins_count = ARRAY_SIZE(ph1_ld6b_pins),
- .groups = ph1_ld6b_groups,
- .groups_count = ARRAY_SIZE(ph1_ld6b_groups),
- .functions = ph1_ld6b_functions,
- .functions_count = ARRAY_SIZE(ph1_ld6b_functions),
- .mux_bits = 8,
- .reg_stride = 4,
- .load_pinctrl = false,
-};
-
-static int ph1_ld6b_pinctrl_probe(struct udevice *dev)
-{
- return uniphier_pinctrl_probe(dev, &ph1_ld6b_pinctrl_socdata);
-}
-
-static const struct udevice_id ph1_ld6b_pinctrl_match[] = {
- { .compatible = "socionext,ph1-ld6b-pinctrl" },
- { /* sentinel */ }
-};
-
-U_BOOT_DRIVER(ph1_ld6b_pinctrl) = {
- .name = "ph1-ld6b-pinctrl",
- .id = UCLASS_PINCTRL,
- .of_match = of_match_ptr(ph1_ld6b_pinctrl_match),
- .probe = ph1_ld6b_pinctrl_probe,
- .remove = uniphier_pinctrl_remove,
- .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
- .ops = &uniphier_pinctrl_ops,
-};
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <dm/device.h>
-#include <dm/pinctrl.h>
-
-#include "pinctrl-uniphier.h"
-
-static const struct uniphier_pinctrl_pin ph1_pro4_pins[] = {
-};
-
-static const unsigned emmc_pins[] = {40, 41, 42, 43, 51, 52, 53};
-static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
-static const unsigned emmc_dat8_pins[] = {44, 45, 46, 47};
-static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
-static const unsigned i2c0_pins[] = {142, 143};
-static const unsigned i2c0_muxvals[] = {0, 0};
-static const unsigned i2c1_pins[] = {144, 145};
-static const unsigned i2c1_muxvals[] = {0, 0};
-static const unsigned i2c2_pins[] = {146, 147};
-static const unsigned i2c2_muxvals[] = {0, 0};
-static const unsigned i2c3_pins[] = {148, 149};
-static const unsigned i2c3_muxvals[] = {0, 0};
-static const unsigned i2c6_pins[] = {308, 309};
-static const unsigned i2c6_muxvals[] = {6, 6};
-static const unsigned nand_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
- 50, 51, 52, 53, 54};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0};
-static const unsigned nand_cs1_pins[] = {131, 132};
-static const unsigned nand_cs1_muxvals[] = {1, 1};
-static const unsigned sd_pins[] = {150, 151, 152, 153, 154, 155, 156, 157, 158};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
-static const unsigned sd1_pins[] = {319, 320, 321, 322, 323, 324, 325, 326,
- 327};
-static const unsigned sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
-static const unsigned uart0_pins[] = {127, 128};
-static const unsigned uart0_muxvals[] = {0, 0};
-static const unsigned uart1_pins[] = {129, 130};
-static const unsigned uart1_muxvals[] = {0, 0};
-static const unsigned uart2_pins[] = {131, 132};
-static const unsigned uart2_muxvals[] = {0, 0};
-static const unsigned uart3_pins[] = {88, 89};
-static const unsigned uart3_muxvals[] = {2, 2};
-static const unsigned usb0_pins[] = {180, 181};
-static const unsigned usb0_muxvals[] = {0, 0};
-static const unsigned usb1_pins[] = {182, 183};
-static const unsigned usb1_muxvals[] = {0, 0};
-static const unsigned usb2_pins[] = {184, 185};
-static const unsigned usb2_muxvals[] = {0, 0};
-static const unsigned usb3_pins[] = {186, 187};
-static const unsigned usb3_muxvals[] = {0, 0};
-
-static const struct uniphier_pinctrl_group ph1_pro4_groups[] = {
- UNIPHIER_PINCTRL_GROUP(emmc),
- UNIPHIER_PINCTRL_GROUP(emmc_dat8),
- UNIPHIER_PINCTRL_GROUP(i2c0),
- UNIPHIER_PINCTRL_GROUP(i2c1),
- UNIPHIER_PINCTRL_GROUP(i2c2),
- UNIPHIER_PINCTRL_GROUP(i2c3),
- UNIPHIER_PINCTRL_GROUP(i2c6),
- UNIPHIER_PINCTRL_GROUP(nand),
- UNIPHIER_PINCTRL_GROUP(nand_cs1),
- UNIPHIER_PINCTRL_GROUP(sd),
- UNIPHIER_PINCTRL_GROUP(sd1),
- UNIPHIER_PINCTRL_GROUP(uart0),
- UNIPHIER_PINCTRL_GROUP(uart1),
- UNIPHIER_PINCTRL_GROUP(uart2),
- UNIPHIER_PINCTRL_GROUP(uart3),
- UNIPHIER_PINCTRL_GROUP(usb0),
- UNIPHIER_PINCTRL_GROUP(usb1),
- UNIPHIER_PINCTRL_GROUP(usb2),
- UNIPHIER_PINCTRL_GROUP(usb3),
-};
-
-static const char * const ph1_pro4_functions[] = {
- "emmc",
- "i2c0",
- "i2c1",
- "i2c2",
- "i2c3",
- "i2c6",
- "nand",
- "sd",
- "sd1",
- "uart0",
- "uart1",
- "uart2",
- "uart3",
- "usb0",
- "usb1",
- "usb2",
- "usb3",
-};
-
-static struct uniphier_pinctrl_socdata ph1_pro4_pinctrl_socdata = {
- .pins = ph1_pro4_pins,
- .pins_count = ARRAY_SIZE(ph1_pro4_pins),
- .groups = ph1_pro4_groups,
- .groups_count = ARRAY_SIZE(ph1_pro4_groups),
- .functions = ph1_pro4_functions,
- .functions_count = ARRAY_SIZE(ph1_pro4_functions),
- .mux_bits = 4,
- .reg_stride = 8,
- .load_pinctrl = true,
-};
-
-static int ph1_pro4_pinctrl_probe(struct udevice *dev)
-{
- return uniphier_pinctrl_probe(dev, &ph1_pro4_pinctrl_socdata);
-}
-
-static const struct udevice_id ph1_pro4_pinctrl_match[] = {
- { .compatible = "socionext,ph1-pro4-pinctrl" },
- { /* sentinel */ }
-};
-
-U_BOOT_DRIVER(ph1_pro4_pinctrl) = {
- .name = "ph1-pro4-pinctrl",
- .id = UCLASS_PINCTRL,
- .of_match = of_match_ptr(ph1_pro4_pinctrl_match),
- .probe = ph1_pro4_pinctrl_probe,
- .remove = uniphier_pinctrl_remove,
- .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
- .ops = &uniphier_pinctrl_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <dm/device.h>
-#include <dm/pinctrl.h>
-
-#include "pinctrl-uniphier.h"
-
-static const struct uniphier_pinctrl_pin ph1_pro5_pins[] = {
- UNIPHIER_PINCTRL_PIN(47, 0),
- UNIPHIER_PINCTRL_PIN(48, 0),
- UNIPHIER_PINCTRL_PIN(49, 0),
- UNIPHIER_PINCTRL_PIN(50, 0),
- UNIPHIER_PINCTRL_PIN(53, 0),
- UNIPHIER_PINCTRL_PIN(54, 0),
- UNIPHIER_PINCTRL_PIN(87, 0),
- UNIPHIER_PINCTRL_PIN(88, 0),
- UNIPHIER_PINCTRL_PIN(101, 0),
- UNIPHIER_PINCTRL_PIN(102, 0),
-};
-
-static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
-static const unsigned emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
-static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
-static const unsigned emmc_dat8_muxvals[] = {0, 0, 0, 0};
-static const unsigned i2c0_pins[] = {112, 113};
-static const unsigned i2c0_muxvals[] = {0, 0};
-static const unsigned i2c1_pins[] = {114, 115};
-static const unsigned i2c1_muxvals[] = {0, 0};
-static const unsigned i2c2_pins[] = {116, 117};
-static const unsigned i2c2_muxvals[] = {0, 0};
-static const unsigned i2c3_pins[] = {118, 119};
-static const unsigned i2c3_muxvals[] = {0, 0};
-static const unsigned i2c5_pins[] = {87, 88};
-static const unsigned i2c5_muxvals[] = {2, 2};
-static const unsigned i2c5b_pins[] = {196, 197};
-static const unsigned i2c5b_muxvals[] = {2, 2};
-static const unsigned i2c5c_pins[] = {215, 216};
-static const unsigned i2c5c_muxvals[] = {2, 2};
-static const unsigned i2c6_pins[] = {101, 102};
-static const unsigned i2c6_muxvals[] = {2, 2};
-static const unsigned nand_pins[] = {19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
- 31, 32, 33, 34, 35};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0};
-static const unsigned nand_cs1_pins[] = {26, 27};
-static const unsigned nand_cs1_muxvals[] = {0, 0};
-static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
-static const unsigned uart0_pins[] = {47, 48};
-static const unsigned uart0_muxvals[] = {0, 0};
-static const unsigned uart0b_pins[] = {227, 228};
-static const unsigned uart0b_muxvals[] = {3, 3};
-static const unsigned uart1_pins[] = {49, 50};
-static const unsigned uart1_muxvals[] = {0, 0};
-static const unsigned uart2_pins[] = {51, 52};
-static const unsigned uart2_muxvals[] = {0, 0};
-static const unsigned uart3_pins[] = {53, 54};
-static const unsigned uart3_muxvals[] = {0, 0};
-static const unsigned usb0_pins[] = {124, 125};
-static const unsigned usb0_muxvals[] = {0, 0};
-static const unsigned usb1_pins[] = {126, 127};
-static const unsigned usb1_muxvals[] = {0, 0};
-static const unsigned usb2_pins[] = {128, 129};
-static const unsigned usb2_muxvals[] = {0, 0};
-
-static const struct uniphier_pinctrl_group ph1_pro5_groups[] = {
- UNIPHIER_PINCTRL_GROUP(emmc),
- UNIPHIER_PINCTRL_GROUP(emmc_dat8),
- UNIPHIER_PINCTRL_GROUP(i2c0),
- UNIPHIER_PINCTRL_GROUP(i2c1),
- UNIPHIER_PINCTRL_GROUP(i2c2),
- UNIPHIER_PINCTRL_GROUP(i2c3),
- UNIPHIER_PINCTRL_GROUP(i2c5),
- UNIPHIER_PINCTRL_GROUP(i2c5b),
- UNIPHIER_PINCTRL_GROUP(i2c5c),
- UNIPHIER_PINCTRL_GROUP(i2c6),
- UNIPHIER_PINCTRL_GROUP(nand),
- UNIPHIER_PINCTRL_GROUP(nand_cs1),
- UNIPHIER_PINCTRL_GROUP(sd),
- UNIPHIER_PINCTRL_GROUP(uart0),
- UNIPHIER_PINCTRL_GROUP(uart0b),
- UNIPHIER_PINCTRL_GROUP(uart1),
- UNIPHIER_PINCTRL_GROUP(uart2),
- UNIPHIER_PINCTRL_GROUP(uart3),
- UNIPHIER_PINCTRL_GROUP(usb0),
- UNIPHIER_PINCTRL_GROUP(usb1),
- UNIPHIER_PINCTRL_GROUP(usb2),
-};
-
-static const char * const ph1_pro5_functions[] = {
- "emmc",
- "i2c0",
- "i2c1",
- "i2c2",
- "i2c3",
- "i2c5",
- "i2c6",
- "nand",
- "sd",
- "uart0",
- "uart1",
- "uart2",
- "uart3",
- "usb0",
- "usb1",
- "usb2",
-};
-
-static struct uniphier_pinctrl_socdata ph1_pro5_pinctrl_socdata = {
- .pins = ph1_pro5_pins,
- .pins_count = ARRAY_SIZE(ph1_pro5_pins),
- .groups = ph1_pro5_groups,
- .groups_count = ARRAY_SIZE(ph1_pro5_groups),
- .functions = ph1_pro5_functions,
- .functions_count = ARRAY_SIZE(ph1_pro5_functions),
- .mux_bits = 4,
- .reg_stride = 8,
- .load_pinctrl = true,
-};
-
-static int ph1_pro5_pinctrl_probe(struct udevice *dev)
-{
- return uniphier_pinctrl_probe(dev, &ph1_pro5_pinctrl_socdata);
-}
-
-static const struct udevice_id ph1_pro5_pinctrl_match[] = {
- { .compatible = "socionext,ph1-pro5-pinctrl" },
- { /* sentinel */ }
-};
-
-U_BOOT_DRIVER(ph1_pro5_pinctrl) = {
- .name = "ph1-pro5-pinctrl",
- .id = UCLASS_PINCTRL,
- .of_match = of_match_ptr(ph1_pro5_pinctrl_match),
- .probe = ph1_pro5_pinctrl_probe,
- .remove = uniphier_pinctrl_remove,
- .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
- .ops = &uniphier_pinctrl_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <dm/device.h>
-#include <dm/pinctrl.h>
-
-#include "pinctrl-uniphier.h"
-
-static const struct uniphier_pinctrl_pin ph1_sld8_pins[] = {
- UNIPHIER_PINCTRL_PIN(32, 8),
- UNIPHIER_PINCTRL_PIN(33, 8),
- UNIPHIER_PINCTRL_PIN(34, 8),
- UNIPHIER_PINCTRL_PIN(35, 8),
- UNIPHIER_PINCTRL_PIN(36, 8),
- UNIPHIER_PINCTRL_PIN(37, 8),
- UNIPHIER_PINCTRL_PIN(38, 8),
- UNIPHIER_PINCTRL_PIN(39, 8),
- UNIPHIER_PINCTRL_PIN(40, 9),
- UNIPHIER_PINCTRL_PIN(41, 0),
- UNIPHIER_PINCTRL_PIN(42, 0),
- UNIPHIER_PINCTRL_PIN(43, 0),
- UNIPHIER_PINCTRL_PIN(44, 0),
- UNIPHIER_PINCTRL_PIN(70, 0),
- UNIPHIER_PINCTRL_PIN(71, 0),
- UNIPHIER_PINCTRL_PIN(102, 10),
- UNIPHIER_PINCTRL_PIN(103, 10),
- UNIPHIER_PINCTRL_PIN(104, 11),
- UNIPHIER_PINCTRL_PIN(105, 11),
- UNIPHIER_PINCTRL_PIN(108, 13),
- UNIPHIER_PINCTRL_PIN(109, 13),
- UNIPHIER_PINCTRL_PIN(112, 0),
- UNIPHIER_PINCTRL_PIN(113, 0),
- UNIPHIER_PINCTRL_PIN(114, 0),
- UNIPHIER_PINCTRL_PIN(115, 0),
-};
-
-static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
-static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
-static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
-static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
-static const unsigned i2c0_pins[] = {102, 103};
-static const unsigned i2c0_muxvals[] = {0, 0};
-static const unsigned i2c1_pins[] = {104, 105};
-static const unsigned i2c1_muxvals[] = {0, 0};
-static const unsigned i2c2_pins[] = {108, 109};
-static const unsigned i2c2_muxvals[] = {2, 2};
-static const unsigned i2c3_pins[] = {108, 109};
-static const unsigned i2c3_muxvals[] = {3, 3};
-static const unsigned nand_pins[] = {15, 16, 17, 18, 19, 20, 21, 24, 25, 26,
- 27, 28, 29, 30, 31};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0};
-static const unsigned nand_cs1_pins[] = {22, 23};
-static const unsigned nand_cs1_muxvals[] = {0, 0};
-static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
-static const unsigned uart0_pins[] = {70, 71};
-static const unsigned uart0_muxvals[] = {3, 3};
-static const unsigned uart1_pins[] = {114, 115};
-static const unsigned uart1_muxvals[] = {0, 0};
-static const unsigned uart2_pins[] = {112, 113};
-static const unsigned uart2_muxvals[] = {1, 1};
-static const unsigned uart3_pins[] = {110, 111};
-static const unsigned uart3_muxvals[] = {1, 1};
-static const unsigned usb0_pins[] = {41, 42};
-static const unsigned usb0_muxvals[] = {0, 0};
-static const unsigned usb1_pins[] = {43, 44};
-static const unsigned usb1_muxvals[] = {0, 0};
-static const unsigned usb2_pins[] = {114, 115};
-static const unsigned usb2_muxvals[] = {1, 1};
-
-static const struct uniphier_pinctrl_group ph1_sld8_groups[] = {
- UNIPHIER_PINCTRL_GROUP(emmc),
- UNIPHIER_PINCTRL_GROUP(emmc_dat8),
- UNIPHIER_PINCTRL_GROUP(i2c0),
- UNIPHIER_PINCTRL_GROUP(i2c1),
- UNIPHIER_PINCTRL_GROUP(i2c2),
- UNIPHIER_PINCTRL_GROUP(i2c3),
- UNIPHIER_PINCTRL_GROUP(nand),
- UNIPHIER_PINCTRL_GROUP(nand_cs1),
- UNIPHIER_PINCTRL_GROUP(sd),
- UNIPHIER_PINCTRL_GROUP(uart0),
- UNIPHIER_PINCTRL_GROUP(uart1),
- UNIPHIER_PINCTRL_GROUP(uart2),
- UNIPHIER_PINCTRL_GROUP(uart3),
- UNIPHIER_PINCTRL_GROUP(usb0),
- UNIPHIER_PINCTRL_GROUP(usb1),
- UNIPHIER_PINCTRL_GROUP(usb2),
-};
-
-static const char * const ph1_sld8_functions[] = {
- "emmc",
- "i2c0",
- "i2c1",
- "i2c2",
- "i2c3",
- "nand",
- "sd",
- "uart0",
- "uart1",
- "uart2",
- "uart3",
- "usb0",
- "usb1",
- "usb2",
-};
-
-static struct uniphier_pinctrl_socdata ph1_sld8_pinctrl_socdata = {
- .pins = ph1_sld8_pins,
- .pins_count = ARRAY_SIZE(ph1_sld8_pins),
- .groups = ph1_sld8_groups,
- .groups_count = ARRAY_SIZE(ph1_sld8_groups),
- .functions = ph1_sld8_functions,
- .functions_count = ARRAY_SIZE(ph1_sld8_functions),
- .mux_bits = 8,
- .reg_stride = 4,
- .load_pinctrl = false,
-};
-
-static int ph1_sld8_pinctrl_probe(struct udevice *dev)
-{
- return uniphier_pinctrl_probe(dev, &ph1_sld8_pinctrl_socdata);
-}
-
-static const struct udevice_id ph1_sld8_pinctrl_match[] = {
- { .compatible = "socionext,ph1-sld8-pinctrl" },
- { /* sentinel */ }
-};
-
-U_BOOT_DRIVER(ph1_sld8_pinctrl) = {
- .name = "ph1-sld8-pinctrl",
- .id = UCLASS_PINCTRL,
- .of_match = of_match_ptr(ph1_sld8_pinctrl_match),
- .probe = ph1_sld8_pinctrl_probe,
- .remove = uniphier_pinctrl_remove,
- .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
- .ops = &uniphier_pinctrl_ops,
-};
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <dm/device.h>
-#include <dm/pinctrl.h>
-
-#include "pinctrl-uniphier.h"
-
-static const struct uniphier_pinctrl_pin proxstream2_pins[] = {
- UNIPHIER_PINCTRL_PIN(113, 0),
- UNIPHIER_PINCTRL_PIN(114, 0),
- UNIPHIER_PINCTRL_PIN(115, 0),
- UNIPHIER_PINCTRL_PIN(116, 0),
-};
-
-static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
-static const unsigned emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9};
-static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
-static const unsigned emmc_dat8_muxvals[] = {9, 9, 9, 9};
-static const unsigned i2c0_pins[] = {109, 110};
-static const unsigned i2c0_muxvals[] = {8, 8};
-static const unsigned i2c1_pins[] = {111, 112};
-static const unsigned i2c1_muxvals[] = {8, 8};
-static const unsigned i2c2_pins[] = {171, 172};
-static const unsigned i2c2_muxvals[] = {8, 8};
-static const unsigned i2c3_pins[] = {159, 160};
-static const unsigned i2c3_muxvals[] = {8, 8};
-static const unsigned i2c5_pins[] = {183, 184};
-static const unsigned i2c5_muxvals[] = {11, 11};
-static const unsigned i2c6_pins[] = {185, 186};
-static const unsigned i2c6_muxvals[] = {11, 11};
-static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
- 42, 43, 44, 45, 46};
-static const unsigned nand_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
- 8, 8};
-static const unsigned nand_cs1_pins[] = {37, 38};
-static const unsigned nand_cs1_muxvals[] = {8, 8};
-static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
-static const unsigned sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8};
-static const unsigned uart0_pins[] = {217, 218};
-static const unsigned uart0_muxvals[] = {8, 8};
-static const unsigned uart0b_pins[] = {179, 180};
-static const unsigned uart0b_muxvals[] = {10, 10};
-static const unsigned uart1_pins[] = {115, 116};
-static const unsigned uart1_muxvals[] = {8, 8};
-static const unsigned uart2_pins[] = {113, 114};
-static const unsigned uart2_muxvals[] = {8, 8};
-static const unsigned uart3_pins[] = {219, 220};
-static const unsigned uart3_muxvals[] = {8, 8};
-static const unsigned uart3b_pins[] = {181, 182};
-static const unsigned uart3b_muxvals[] = {10, 10};
-static const unsigned usb0_pins[] = {56, 57};
-static const unsigned usb0_muxvals[] = {8, 8};
-static const unsigned usb1_pins[] = {58, 59};
-static const unsigned usb1_muxvals[] = {8, 8};
-static const unsigned usb2_pins[] = {60, 61};
-static const unsigned usb2_muxvals[] = {8, 8};
-static const unsigned usb3_pins[] = {62, 63};
-static const unsigned usb3_muxvals[] = {8, 8};
-
-static const struct uniphier_pinctrl_group proxstream2_groups[] = {
- UNIPHIER_PINCTRL_GROUP(emmc),
- UNIPHIER_PINCTRL_GROUP(emmc_dat8),
- UNIPHIER_PINCTRL_GROUP(i2c0),
- UNIPHIER_PINCTRL_GROUP(i2c1),
- UNIPHIER_PINCTRL_GROUP(i2c2),
- UNIPHIER_PINCTRL_GROUP(i2c3),
- UNIPHIER_PINCTRL_GROUP(i2c5),
- UNIPHIER_PINCTRL_GROUP(i2c6),
- UNIPHIER_PINCTRL_GROUP(nand),
- UNIPHIER_PINCTRL_GROUP(nand_cs1),
- UNIPHIER_PINCTRL_GROUP(sd),
- UNIPHIER_PINCTRL_GROUP(uart0),
- UNIPHIER_PINCTRL_GROUP(uart0b),
- UNIPHIER_PINCTRL_GROUP(uart1),
- UNIPHIER_PINCTRL_GROUP(uart2),
- UNIPHIER_PINCTRL_GROUP(uart3),
- UNIPHIER_PINCTRL_GROUP(uart3b),
- UNIPHIER_PINCTRL_GROUP(usb0),
- UNIPHIER_PINCTRL_GROUP(usb1),
- UNIPHIER_PINCTRL_GROUP(usb2),
- UNIPHIER_PINCTRL_GROUP(usb3),
-};
-
-static const char * const proxstream2_functions[] = {
- "emmc",
- "i2c0",
- "i2c1",
- "i2c2",
- "i2c3",
- "i2c5",
- "i2c6",
- "nand",
- "sd",
- "uart0",
- "uart0b",
- "uart1",
- "uart2",
- "uart3",
- "uart3b",
- "usb0",
- "usb1",
- "usb2",
- "usb3",
-};
-
-static struct uniphier_pinctrl_socdata proxstream2_pinctrl_socdata = {
- .pins = proxstream2_pins,
- .pins_count = ARRAY_SIZE(proxstream2_pins),
- .groups = proxstream2_groups,
- .groups_count = ARRAY_SIZE(proxstream2_groups),
- .functions = proxstream2_functions,
- .functions_count = ARRAY_SIZE(proxstream2_functions),
- .mux_bits = 8,
- .reg_stride = 4,
- .load_pinctrl = false,
-};
-
-static int proxstream2_pinctrl_probe(struct udevice *dev)
-{
- return uniphier_pinctrl_probe(dev, &proxstream2_pinctrl_socdata);
-}
-
-static const struct udevice_id proxstream2_pinctrl_match[] = {
- { .compatible = "socionext,proxstream2-pinctrl" },
- { /* sentinel */ }
-};
-
-U_BOOT_DRIVER(proxstream2_pinctrl) = {
- .name = "proxstream2-pinctrl",
- .id = UCLASS_PINCTRL,
- .of_match = of_match_ptr(proxstream2_pinctrl_match),
- .probe = proxstream2_pinctrl_probe,
- .remove = uniphier_pinctrl_remove,
- .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
- .ops = &uniphier_pinctrl_ops,
-};
#include <mapmem.h>
#include <linux/io.h>
#include <linux/err.h>
+#include <linux/sizes.h>
#include <dm/device.h>
#include <dm/pinctrl.h>
#include "pinctrl-uniphier.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static int uniphier_pinctrl_get_groups_count(struct udevice *dev)
{
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
return priv->socdata->functions[selector];
}
-static void uniphier_pinconf_input_enable(struct udevice *dev, unsigned pin)
+static void uniphier_pinconf_input_enable_perpin(struct udevice *dev,
+ unsigned pin)
+{
+ struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+ unsigned reg;
+ u32 mask, tmp;
+
+ reg = UNIPHIER_PINCTRL_IECTRL + pin / 32 * 4;
+ mask = BIT(pin % 32);
+
+ tmp = readl(priv->base + reg);
+ tmp |= mask;
+ writel(tmp, priv->base + reg);
+}
+
+static void uniphier_pinconf_input_enable_legacy(struct udevice *dev,
+ unsigned pin)
{
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
int pins_count = priv->socdata->pins_count;
}
}
+static void uniphier_pinconf_input_enable(struct udevice *dev, unsigned pin)
+{
+ struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+
+ if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL)
+ uniphier_pinconf_input_enable_perpin(dev, pin);
+ else
+ uniphier_pinconf_input_enable_legacy(dev, pin);
+}
+
static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
unsigned muxval)
{
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
- unsigned mux_bits = priv->socdata->mux_bits;
- unsigned reg_stride = priv->socdata->reg_stride;
- unsigned reg, reg_end, shift, mask;
+ unsigned mux_bits, reg_stride, reg, reg_end, shift, mask;
+ bool load_pinctrl;
u32 tmp;
/* some pins need input-enabling */
uniphier_pinconf_input_enable(dev, pin);
+ if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
+ /*
+ * Mode offset bit
+ * Normal 4 * n shift+3:shift
+ * Debug 4 * n shift+7:shift+4
+ */
+ mux_bits = 4;
+ reg_stride = 8;
+ load_pinctrl = true;
+ } else {
+ /*
+ * Mode offset bit
+ * Normal 8 * n shift+3:shift
+ * Debug 8 * n + 4 shift+3:shift
+ */
+ mux_bits = 8;
+ reg_stride = 4;
+ load_pinctrl = false;
+ }
+
reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
reg_end = reg + reg_stride;
shift = pin * mux_bits % 32;
muxval >>= mux_bits;
}
- if (priv->socdata->load_pinctrl)
+ if (load_pinctrl)
writel(1, priv->base + UNIPHIER_PINCTRL_LOAD_PINMUX);
}
{
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
- fdt_size_t size;
- addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg",
- &size);
+ addr = dev_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
- priv->base = map_sysmem(addr, size);
+ priv->base = map_sysmem(addr, SZ_4K);
if (!priv->base)
return -ENOMEM;
--- /dev/null
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23, 24, 25};
+static const unsigned emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
+static const unsigned emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const unsigned i2c0_pins[] = {63, 64};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {65, 66};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c3_pins[] = {67, 68};
+static const unsigned i2c3_muxvals[] = {1, 1};
+static const unsigned i2c4_pins[] = {61, 62};
+static const unsigned i2c4_muxvals[] = {1, 1};
+static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
+ 15, 16};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0};
+static const unsigned nand_cs1_pins[] = {};
+static const unsigned nand_cs1_muxvals[] = {};
+static const unsigned sd_pins[] = {10, 11, 12, 13, 14, 15, 16, 17};
+static const unsigned sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8}; /* No SDVOLC */
+static const unsigned uart0_pins[] = {54, 55};
+static const unsigned uart0_muxvals[] = {0, 0};
+static const unsigned uart1_pins[] = {58, 59};
+static const unsigned uart1_muxvals[] = {1, 1};
+static const unsigned uart2_pins[] = {90, 91};
+static const unsigned uart2_muxvals[] = {1, 1};
+static const unsigned uart3_pins[] = {94, 95};
+static const unsigned uart3_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {46, 47};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {48, 49};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {50, 51};
+static const unsigned usb2_muxvals[] = {0, 0};
+static const unsigned usb3_pins[] = {52, 53};
+static const unsigned usb3_muxvals[] = {0, 0};
+
+static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(i2c4),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd), /* SD does not exist for LD11 */
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+ UNIPHIER_PINCTRL_GROUP(usb3), /* USB3 does not exist for LD11 */
+};
+
+static const char * const uniphier_ld20_functions[] = {
+ "emmc",
+ "i2c0",
+ "i2c1",
+ "i2c3",
+ "i2c4",
+ "nand",
+ "sd", /* SD does not exist for LD11 */
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
+ "usb0",
+ "usb1",
+ "usb2",
+ "usb3", /* USB3 does not exist for LD11 */
+};
+
+static struct uniphier_pinctrl_socdata uniphier_ld20_pinctrl_socdata = {
+ .groups = uniphier_ld20_groups,
+ .groups_count = ARRAY_SIZE(uniphier_ld20_groups),
+ .functions = uniphier_ld20_functions,
+ .functions_count = ARRAY_SIZE(uniphier_ld20_functions),
+ .caps = UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL,
+};
+
+static int uniphier_ld20_pinctrl_probe(struct udevice *dev)
+{
+ return uniphier_pinctrl_probe(dev, &uniphier_ld20_pinctrl_socdata);
+}
+
+static const struct udevice_id uniphier_ld20_pinctrl_match[] = {
+ { .compatible = "socionext,ph1-ld11-pinctrl" },
+ { .compatible = "socionext,ph1-ld20-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_ld20_pinctrl) = {
+ .name = "uniphier-ld20-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(uniphier_ld20_pinctrl_match),
+ .probe = uniphier_ld20_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .ops = &uniphier_pinctrl_ops,
+};
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin ph1_ld4_pins[] = {
+ UNIPHIER_PINCTRL_PIN(53, 0),
+ UNIPHIER_PINCTRL_PIN(54, 0),
+ UNIPHIER_PINCTRL_PIN(55, 0),
+ UNIPHIER_PINCTRL_PIN(56, 0),
+ UNIPHIER_PINCTRL_PIN(67, 0),
+ UNIPHIER_PINCTRL_PIN(68, 0),
+ UNIPHIER_PINCTRL_PIN(69, 0),
+ UNIPHIER_PINCTRL_PIN(70, 0),
+ UNIPHIER_PINCTRL_PIN(85, 0),
+ UNIPHIER_PINCTRL_PIN(88, 0),
+ UNIPHIER_PINCTRL_PIN(156, 0),
+};
+
+static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
+static const unsigned emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
+static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {102, 103};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {104, 105};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {108, 109};
+static const unsigned i2c2_muxvals[] = {2, 2};
+static const unsigned i2c3_pins[] = {108, 109};
+static const unsigned i2c3_muxvals[] = {3, 3};
+static const unsigned nand_pins[] = {24, 25, 26, 27, 28, 29, 30, 31, 158, 159,
+ 160, 161, 162, 163, 164};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0};
+static const unsigned nand_cs1_pins[] = {22, 23};
+static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned uart0_pins[] = {85, 88};
+static const unsigned uart0_muxvals[] = {1, 1};
+static const unsigned uart1_pins[] = {155, 156};
+static const unsigned uart1_muxvals[] = {13, 13};
+static const unsigned uart1b_pins[] = {69, 70};
+static const unsigned uart1b_muxvals[] = {23, 23};
+static const unsigned uart2_pins[] = {128, 129};
+static const unsigned uart2_muxvals[] = {13, 13};
+static const unsigned uart3_pins[] = {110, 111};
+static const unsigned uart3_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {53, 54};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {55, 56};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {155, 156};
+static const unsigned usb2_muxvals[] = {4, 4};
+static const unsigned usb2b_pins[] = {67, 68};
+static const unsigned usb2b_muxvals[] = {23, 23};
+
+static const struct uniphier_pinctrl_group ph1_ld4_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart1b),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+ UNIPHIER_PINCTRL_GROUP(usb2b),
+};
+
+static const char * const ph1_ld4_functions[] = {
+ "emmc",
+ "i2c0",
+ "i2c1",
+ "i2c2",
+ "i2c3",
+ "nand",
+ "sd",
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
+ "usb0",
+ "usb1",
+ "usb2",
+};
+
+static struct uniphier_pinctrl_socdata ph1_ld4_pinctrl_socdata = {
+ .pins = ph1_ld4_pins,
+ .pins_count = ARRAY_SIZE(ph1_ld4_pins),
+ .groups = ph1_ld4_groups,
+ .groups_count = ARRAY_SIZE(ph1_ld4_groups),
+ .functions = ph1_ld4_functions,
+ .functions_count = ARRAY_SIZE(ph1_ld4_functions),
+};
+
+static int ph1_ld4_pinctrl_probe(struct udevice *dev)
+{
+ return uniphier_pinctrl_probe(dev, &ph1_ld4_pinctrl_socdata);
+}
+
+static const struct udevice_id ph1_ld4_pinctrl_match[] = {
+ { .compatible = "socionext,ph1-ld4-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(ph1_ld4_pinctrl) = {
+ .name = "ph1-ld4-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(ph1_ld4_pinctrl_match),
+ .probe = ph1_ld4_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .ops = &uniphier_pinctrl_ops,
+};
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin ph1_ld6b_pins[] = {
+ UNIPHIER_PINCTRL_PIN(113, 0),
+ UNIPHIER_PINCTRL_PIN(114, 0),
+ UNIPHIER_PINCTRL_PIN(115, 0),
+ UNIPHIER_PINCTRL_PIN(116, 0),
+ UNIPHIER_PINCTRL_PIN(217, 0),
+ UNIPHIER_PINCTRL_PIN(218, 0),
+ UNIPHIER_PINCTRL_PIN(219, 0),
+ UNIPHIER_PINCTRL_PIN(220, 0),
+};
+
+static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
+static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
+static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {109, 110};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {111, 112};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {115, 116};
+static const unsigned i2c2_muxvals[] = {1, 1};
+static const unsigned i2c3_pins[] = {118, 119};
+static const unsigned i2c3_muxvals[] = {1, 1};
+static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
+ 42, 43, 44, 45, 46};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0};
+static const unsigned nand_cs1_pins[] = {37, 38};
+static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned uart0_pins[] = {135, 136};
+static const unsigned uart0_muxvals[] = {3, 3};
+static const unsigned uart0b_pins[] = {11, 12};
+static const unsigned uart0b_muxvals[] = {2, 2};
+static const unsigned uart1_pins[] = {115, 116};
+static const unsigned uart1_muxvals[] = {0, 0};
+static const unsigned uart1b_pins[] = {113, 114};
+static const unsigned uart1b_muxvals[] = {1, 1};
+static const unsigned uart2_pins[] = {113, 114};
+static const unsigned uart2_muxvals[] = {2, 2};
+static const unsigned uart2b_pins[] = {86, 87};
+static const unsigned uart2b_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {56, 57};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {58, 59};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {60, 61};
+static const unsigned usb2_muxvals[] = {0, 0};
+static const unsigned usb3_pins[] = {62, 63};
+static const unsigned usb3_muxvals[] = {0, 0};
+
+static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart0b),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart1b),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart2b),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+ UNIPHIER_PINCTRL_GROUP(usb3),
+};
+
+static const char * const ph1_ld6b_functions[] = {
+ "emmc",
+ "i2c0",
+ "i2c1",
+ "i2c2",
+ "i2c3",
+ "nand",
+ "sd",
+ "uart0",
+ "uart1",
+ "uart2",
+ "usb0",
+ "usb1",
+ "usb2",
+ "usb3",
+};
+
+static struct uniphier_pinctrl_socdata ph1_ld6b_pinctrl_socdata = {
+ .pins = ph1_ld6b_pins,
+ .pins_count = ARRAY_SIZE(ph1_ld6b_pins),
+ .groups = ph1_ld6b_groups,
+ .groups_count = ARRAY_SIZE(ph1_ld6b_groups),
+ .functions = ph1_ld6b_functions,
+ .functions_count = ARRAY_SIZE(ph1_ld6b_functions),
+};
+
+static int ph1_ld6b_pinctrl_probe(struct udevice *dev)
+{
+ return uniphier_pinctrl_probe(dev, &ph1_ld6b_pinctrl_socdata);
+}
+
+static const struct udevice_id ph1_ld6b_pinctrl_match[] = {
+ { .compatible = "socionext,ph1-ld6b-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(ph1_ld6b_pinctrl) = {
+ .name = "ph1-ld6b-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(ph1_ld6b_pinctrl_match),
+ .probe = ph1_ld6b_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .ops = &uniphier_pinctrl_ops,
+};
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin ph1_pro4_pins[] = {
+};
+
+static const unsigned emmc_pins[] = {40, 41, 42, 43, 51, 52, 53};
+static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {44, 45, 46, 47};
+static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {142, 143};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {144, 145};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {146, 147};
+static const unsigned i2c2_muxvals[] = {0, 0};
+static const unsigned i2c3_pins[] = {148, 149};
+static const unsigned i2c3_muxvals[] = {0, 0};
+static const unsigned i2c6_pins[] = {308, 309};
+static const unsigned i2c6_muxvals[] = {6, 6};
+static const unsigned nand_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
+ 50, 51, 52, 53, 54};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0};
+static const unsigned nand_cs1_pins[] = {131, 132};
+static const unsigned nand_cs1_muxvals[] = {1, 1};
+static const unsigned sd_pins[] = {150, 151, 152, 153, 154, 155, 156, 157, 158};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned sd1_pins[] = {319, 320, 321, 322, 323, 324, 325, 326,
+ 327};
+static const unsigned sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned uart0_pins[] = {127, 128};
+static const unsigned uart0_muxvals[] = {0, 0};
+static const unsigned uart1_pins[] = {129, 130};
+static const unsigned uart1_muxvals[] = {0, 0};
+static const unsigned uart2_pins[] = {131, 132};
+static const unsigned uart2_muxvals[] = {0, 0};
+static const unsigned uart3_pins[] = {88, 89};
+static const unsigned uart3_muxvals[] = {2, 2};
+static const unsigned usb0_pins[] = {180, 181};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {182, 183};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {184, 185};
+static const unsigned usb2_muxvals[] = {0, 0};
+static const unsigned usb3_pins[] = {186, 187};
+static const unsigned usb3_muxvals[] = {0, 0};
+
+static const struct uniphier_pinctrl_group ph1_pro4_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(i2c6),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(sd1),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+ UNIPHIER_PINCTRL_GROUP(usb3),
+};
+
+static const char * const ph1_pro4_functions[] = {
+ "emmc",
+ "i2c0",
+ "i2c1",
+ "i2c2",
+ "i2c3",
+ "i2c6",
+ "nand",
+ "sd",
+ "sd1",
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
+ "usb0",
+ "usb1",
+ "usb2",
+ "usb3",
+};
+
+static struct uniphier_pinctrl_socdata ph1_pro4_pinctrl_socdata = {
+ .pins = ph1_pro4_pins,
+ .pins_count = ARRAY_SIZE(ph1_pro4_pins),
+ .groups = ph1_pro4_groups,
+ .groups_count = ARRAY_SIZE(ph1_pro4_groups),
+ .functions = ph1_pro4_functions,
+ .functions_count = ARRAY_SIZE(ph1_pro4_functions),
+ .caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE,
+};
+
+static int ph1_pro4_pinctrl_probe(struct udevice *dev)
+{
+ return uniphier_pinctrl_probe(dev, &ph1_pro4_pinctrl_socdata);
+}
+
+static const struct udevice_id ph1_pro4_pinctrl_match[] = {
+ { .compatible = "socionext,ph1-pro4-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(ph1_pro4_pinctrl) = {
+ .name = "ph1-pro4-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(ph1_pro4_pinctrl_match),
+ .probe = ph1_pro4_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .ops = &uniphier_pinctrl_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin ph1_pro5_pins[] = {
+ UNIPHIER_PINCTRL_PIN(47, 0),
+ UNIPHIER_PINCTRL_PIN(48, 0),
+ UNIPHIER_PINCTRL_PIN(49, 0),
+ UNIPHIER_PINCTRL_PIN(50, 0),
+ UNIPHIER_PINCTRL_PIN(53, 0),
+ UNIPHIER_PINCTRL_PIN(54, 0),
+ UNIPHIER_PINCTRL_PIN(87, 0),
+ UNIPHIER_PINCTRL_PIN(88, 0),
+ UNIPHIER_PINCTRL_PIN(101, 0),
+ UNIPHIER_PINCTRL_PIN(102, 0),
+};
+
+static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
+static const unsigned emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
+static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
+static const unsigned emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const unsigned i2c0_pins[] = {112, 113};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {114, 115};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {116, 117};
+static const unsigned i2c2_muxvals[] = {0, 0};
+static const unsigned i2c3_pins[] = {118, 119};
+static const unsigned i2c3_muxvals[] = {0, 0};
+static const unsigned i2c5_pins[] = {87, 88};
+static const unsigned i2c5_muxvals[] = {2, 2};
+static const unsigned i2c5b_pins[] = {196, 197};
+static const unsigned i2c5b_muxvals[] = {2, 2};
+static const unsigned i2c5c_pins[] = {215, 216};
+static const unsigned i2c5c_muxvals[] = {2, 2};
+static const unsigned i2c6_pins[] = {101, 102};
+static const unsigned i2c6_muxvals[] = {2, 2};
+static const unsigned nand_pins[] = {19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
+ 31, 32, 33, 34, 35};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0};
+static const unsigned nand_cs1_pins[] = {26, 27};
+static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned uart0_pins[] = {47, 48};
+static const unsigned uart0_muxvals[] = {0, 0};
+static const unsigned uart0b_pins[] = {227, 228};
+static const unsigned uart0b_muxvals[] = {3, 3};
+static const unsigned uart1_pins[] = {49, 50};
+static const unsigned uart1_muxvals[] = {0, 0};
+static const unsigned uart2_pins[] = {51, 52};
+static const unsigned uart2_muxvals[] = {0, 0};
+static const unsigned uart3_pins[] = {53, 54};
+static const unsigned uart3_muxvals[] = {0, 0};
+static const unsigned usb0_pins[] = {124, 125};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {126, 127};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {128, 129};
+static const unsigned usb2_muxvals[] = {0, 0};
+
+static const struct uniphier_pinctrl_group ph1_pro5_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(i2c5),
+ UNIPHIER_PINCTRL_GROUP(i2c5b),
+ UNIPHIER_PINCTRL_GROUP(i2c5c),
+ UNIPHIER_PINCTRL_GROUP(i2c6),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart0b),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+};
+
+static const char * const ph1_pro5_functions[] = {
+ "emmc",
+ "i2c0",
+ "i2c1",
+ "i2c2",
+ "i2c3",
+ "i2c5",
+ "i2c6",
+ "nand",
+ "sd",
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
+ "usb0",
+ "usb1",
+ "usb2",
+};
+
+static struct uniphier_pinctrl_socdata ph1_pro5_pinctrl_socdata = {
+ .pins = ph1_pro5_pins,
+ .pins_count = ARRAY_SIZE(ph1_pro5_pins),
+ .groups = ph1_pro5_groups,
+ .groups_count = ARRAY_SIZE(ph1_pro5_groups),
+ .functions = ph1_pro5_functions,
+ .functions_count = ARRAY_SIZE(ph1_pro5_functions),
+ .caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE,
+};
+
+static int ph1_pro5_pinctrl_probe(struct udevice *dev)
+{
+ return uniphier_pinctrl_probe(dev, &ph1_pro5_pinctrl_socdata);
+}
+
+static const struct udevice_id ph1_pro5_pinctrl_match[] = {
+ { .compatible = "socionext,ph1-pro5-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(ph1_pro5_pinctrl) = {
+ .name = "ph1-pro5-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(ph1_pro5_pinctrl_match),
+ .probe = ph1_pro5_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .ops = &uniphier_pinctrl_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin proxstream2_pins[] = {
+ UNIPHIER_PINCTRL_PIN(113, 0),
+ UNIPHIER_PINCTRL_PIN(114, 0),
+ UNIPHIER_PINCTRL_PIN(115, 0),
+ UNIPHIER_PINCTRL_PIN(116, 0),
+};
+
+static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
+static const unsigned emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9};
+static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
+static const unsigned emmc_dat8_muxvals[] = {9, 9, 9, 9};
+static const unsigned i2c0_pins[] = {109, 110};
+static const unsigned i2c0_muxvals[] = {8, 8};
+static const unsigned i2c1_pins[] = {111, 112};
+static const unsigned i2c1_muxvals[] = {8, 8};
+static const unsigned i2c2_pins[] = {171, 172};
+static const unsigned i2c2_muxvals[] = {8, 8};
+static const unsigned i2c3_pins[] = {159, 160};
+static const unsigned i2c3_muxvals[] = {8, 8};
+static const unsigned i2c5_pins[] = {183, 184};
+static const unsigned i2c5_muxvals[] = {11, 11};
+static const unsigned i2c6_pins[] = {185, 186};
+static const unsigned i2c6_muxvals[] = {11, 11};
+static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
+ 42, 43, 44, 45, 46};
+static const unsigned nand_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8};
+static const unsigned nand_cs1_pins[] = {37, 38};
+static const unsigned nand_cs1_muxvals[] = {8, 8};
+static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
+static const unsigned sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8};
+static const unsigned uart0_pins[] = {217, 218};
+static const unsigned uart0_muxvals[] = {8, 8};
+static const unsigned uart0b_pins[] = {179, 180};
+static const unsigned uart0b_muxvals[] = {10, 10};
+static const unsigned uart1_pins[] = {115, 116};
+static const unsigned uart1_muxvals[] = {8, 8};
+static const unsigned uart2_pins[] = {113, 114};
+static const unsigned uart2_muxvals[] = {8, 8};
+static const unsigned uart3_pins[] = {219, 220};
+static const unsigned uart3_muxvals[] = {8, 8};
+static const unsigned uart3b_pins[] = {181, 182};
+static const unsigned uart3b_muxvals[] = {10, 10};
+static const unsigned usb0_pins[] = {56, 57};
+static const unsigned usb0_muxvals[] = {8, 8};
+static const unsigned usb1_pins[] = {58, 59};
+static const unsigned usb1_muxvals[] = {8, 8};
+static const unsigned usb2_pins[] = {60, 61};
+static const unsigned usb2_muxvals[] = {8, 8};
+static const unsigned usb3_pins[] = {62, 63};
+static const unsigned usb3_muxvals[] = {8, 8};
+
+static const struct uniphier_pinctrl_group proxstream2_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(i2c5),
+ UNIPHIER_PINCTRL_GROUP(i2c6),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart0b),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(uart3b),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+ UNIPHIER_PINCTRL_GROUP(usb3),
+};
+
+static const char * const proxstream2_functions[] = {
+ "emmc",
+ "i2c0",
+ "i2c1",
+ "i2c2",
+ "i2c3",
+ "i2c5",
+ "i2c6",
+ "nand",
+ "sd",
+ "uart0",
+ "uart0b",
+ "uart1",
+ "uart2",
+ "uart3",
+ "uart3b",
+ "usb0",
+ "usb1",
+ "usb2",
+ "usb3",
+};
+
+static struct uniphier_pinctrl_socdata proxstream2_pinctrl_socdata = {
+ .pins = proxstream2_pins,
+ .pins_count = ARRAY_SIZE(proxstream2_pins),
+ .groups = proxstream2_groups,
+ .groups_count = ARRAY_SIZE(proxstream2_groups),
+ .functions = proxstream2_functions,
+ .functions_count = ARRAY_SIZE(proxstream2_functions),
+};
+
+static int proxstream2_pinctrl_probe(struct udevice *dev)
+{
+ return uniphier_pinctrl_probe(dev, &proxstream2_pinctrl_socdata);
+}
+
+static const struct udevice_id proxstream2_pinctrl_match[] = {
+ { .compatible = "socionext,proxstream2-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(proxstream2_pinctrl) = {
+ .name = "proxstream2-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(proxstream2_pinctrl_match),
+ .probe = proxstream2_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .ops = &uniphier_pinctrl_ops,
+};
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin ph1_sld8_pins[] = {
+ UNIPHIER_PINCTRL_PIN(32, 8),
+ UNIPHIER_PINCTRL_PIN(33, 8),
+ UNIPHIER_PINCTRL_PIN(34, 8),
+ UNIPHIER_PINCTRL_PIN(35, 8),
+ UNIPHIER_PINCTRL_PIN(36, 8),
+ UNIPHIER_PINCTRL_PIN(37, 8),
+ UNIPHIER_PINCTRL_PIN(38, 8),
+ UNIPHIER_PINCTRL_PIN(39, 8),
+ UNIPHIER_PINCTRL_PIN(40, 9),
+ UNIPHIER_PINCTRL_PIN(41, 0),
+ UNIPHIER_PINCTRL_PIN(42, 0),
+ UNIPHIER_PINCTRL_PIN(43, 0),
+ UNIPHIER_PINCTRL_PIN(44, 0),
+ UNIPHIER_PINCTRL_PIN(70, 0),
+ UNIPHIER_PINCTRL_PIN(71, 0),
+ UNIPHIER_PINCTRL_PIN(102, 10),
+ UNIPHIER_PINCTRL_PIN(103, 10),
+ UNIPHIER_PINCTRL_PIN(104, 11),
+ UNIPHIER_PINCTRL_PIN(105, 11),
+ UNIPHIER_PINCTRL_PIN(108, 13),
+ UNIPHIER_PINCTRL_PIN(109, 13),
+ UNIPHIER_PINCTRL_PIN(112, 0),
+ UNIPHIER_PINCTRL_PIN(113, 0),
+ UNIPHIER_PINCTRL_PIN(114, 0),
+ UNIPHIER_PINCTRL_PIN(115, 0),
+};
+
+static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
+static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
+static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {102, 103};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {104, 105};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {108, 109};
+static const unsigned i2c2_muxvals[] = {2, 2};
+static const unsigned i2c3_pins[] = {108, 109};
+static const unsigned i2c3_muxvals[] = {3, 3};
+static const unsigned nand_pins[] = {15, 16, 17, 18, 19, 20, 21, 24, 25, 26,
+ 27, 28, 29, 30, 31};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0};
+static const unsigned nand_cs1_pins[] = {22, 23};
+static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned uart0_pins[] = {70, 71};
+static const unsigned uart0_muxvals[] = {3, 3};
+static const unsigned uart1_pins[] = {114, 115};
+static const unsigned uart1_muxvals[] = {0, 0};
+static const unsigned uart2_pins[] = {112, 113};
+static const unsigned uart2_muxvals[] = {1, 1};
+static const unsigned uart3_pins[] = {110, 111};
+static const unsigned uart3_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {41, 42};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {43, 44};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {114, 115};
+static const unsigned usb2_muxvals[] = {1, 1};
+
+static const struct uniphier_pinctrl_group ph1_sld8_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+};
+
+static const char * const ph1_sld8_functions[] = {
+ "emmc",
+ "i2c0",
+ "i2c1",
+ "i2c2",
+ "i2c3",
+ "nand",
+ "sd",
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
+ "usb0",
+ "usb1",
+ "usb2",
+};
+
+static struct uniphier_pinctrl_socdata ph1_sld8_pinctrl_socdata = {
+ .pins = ph1_sld8_pins,
+ .pins_count = ARRAY_SIZE(ph1_sld8_pins),
+ .groups = ph1_sld8_groups,
+ .groups_count = ARRAY_SIZE(ph1_sld8_groups),
+ .functions = ph1_sld8_functions,
+ .functions_count = ARRAY_SIZE(ph1_sld8_functions),
+};
+
+static int ph1_sld8_pinctrl_probe(struct udevice *dev)
+{
+ return uniphier_pinctrl_probe(dev, &ph1_sld8_pinctrl_socdata);
+}
+
+static const struct udevice_id ph1_sld8_pinctrl_match[] = {
+ { .compatible = "socionext,ph1-sld8-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(ph1_sld8_pinctrl) = {
+ .name = "ph1-sld8-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(ph1_sld8_pinctrl_match),
+ .probe = ph1_sld8_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .ops = &uniphier_pinctrl_ops,
+};
#ifndef __PINCTRL_UNIPHIER_H__
#define __PINCTRL_UNIPHIER_H__
+#include <linux/bitops.h>
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/types.h>
* @functions_count: number of pinmux functions
* @mux_bits: bit width of each pinmux register
* @reg_stride: stride of pinmux register address
- * @load_pinctrl: if true, LOAD_PINMUX register must be set to one for new
- * values in pinmux registers to become really effective
+ * @caps: SoC-specific capability flag
*/
struct uniphier_pinctrl_socdata {
const struct uniphier_pinctrl_pin *pins;
int groups_count;
const char * const *functions;
int functions_count;
- unsigned mux_bits;
- unsigned reg_stride;
- bool load_pinctrl;
+ unsigned caps;
+#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(1)
+#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0)
};
#define UNIPHIER_PINCTRL_PIN(a, b) \
default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
default AXP818_POWER if MACH_SUN8I_A83T
- default SUNXI_NO_PMIC if MACH_SUN8I_H3
+ default SUNXI_NO_PMIC if MACH_SUN8I_H3 || MACH_SUN50I
config SUNXI_NO_PMIC
boolean "board without a pmic"
config AXP_DCDC5_VOLT
int "axp pmic dcdc5 voltage"
depends on AXP221_POWER || AXP818_POWER
- default 1800 if AXP818_POWER
default 1500 if MACH_SUN6I || MACH_SUN8I
---help---
Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to
disable dcdc5.
On A23 / A31 / A33 / A83T boards dcdc5 is VCC-DRAM and should be 1.5V,
- 1.8V for A83T.
+ 1.35V if DDR3L is used.
config AXP_ALDO1_VOLT
int "axp pmic (a)ldo1 voltage"
1.2V for the SSD2828 chip (converter of parallel LCD interface
into MIPI DSI).
+config AXP_FLDO1_VOLT
+ int "axp pmic fldo1 voltage"
+ depends on AXP818_POWER
+ default 0 if MACH_SUN8I_A83T
+ ---help---
+ Set the voltage (mV) to program the axp pmic fldo1 at, set to 0 to
+ disable fldo1.
+ On A83T / H8 boards fldo1 is VCC-HSIC and should be 1.2V if HSIC is
+ used.
+
+config AXP_FLDO2_VOLT
+ int "axp pmic eldo2 voltage"
+ depends on AXP818_POWER
+ default 900 if MACH_SUN8I_A83T
+ ---help---
+ Set the voltage (mV) to program the axp pmic fldo2 at, set to 0 to
+ disable fldo2.
+ On A83T / H8 boards fldo2 is VCC-CPUS and should be 0.9V.
+
+config AXP_FLDO3_VOLT
+ int "axp pmic fldo3 voltage"
+ depends on AXP818_POWER
+ default 0
+ ---help---
+ Set the voltage (mV) to program the axp pmic fldo3 at, set to 0 to
+ disable fldo3.
+
config SY8106A_VOUT1_VOLT
int "SY8106A pmic VOUT1 voltage"
depends on SY8106A_POWER
AXP818_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
}
+int axp_set_fldo(int fldo_num, unsigned int mvolt)
+{
+ int ret;
+ u8 cfg;
+
+ if (fldo_num < 1 || fldo_num > 3)
+ return -EINVAL;
+
+ if (mvolt == 0)
+ return pmic_bus_clrbits(AXP818_OUTPUT_CTRL3,
+ AXP818_OUTPUT_CTRL3_FLDO1_EN << (fldo_num - 1));
+
+ if (fldo_num < 3) {
+ cfg = axp818_mvolt_to_cfg(mvolt, 700, 1450, 50);
+ ret = pmic_bus_write(AXP818_FLDO1_CTRL + (fldo_num - 1), cfg);
+ } else {
+ /*
+ * Special case for FLDO3, which is DCDC5 / 2 or FLDOIN / 2
+ * Since FLDOIN is unknown, test against DCDC5.
+ */
+ if (mvolt * 2 == CONFIG_AXP_DCDC5_VOLT)
+ ret = pmic_bus_clrbits(AXP818_FLDO2_3_CTRL,
+ AXP818_FLDO2_3_CTRL_FLDO3_VOL);
+ else
+ ret = pmic_bus_setbits(AXP818_FLDO2_3_CTRL,
+ AXP818_FLDO2_3_CTRL_FLDO3_VOL);
+ }
+ if (ret)
+ return ret;
+
+ return pmic_bus_setbits(AXP818_OUTPUT_CTRL3,
+ AXP818_OUTPUT_CTRL3_FLDO1_EN << (fldo_num - 1));
+}
+
int axp_init(void)
{
u8 axp_chip_id;
This config enables implementation of driver-model pmic uclass features
for PMIC MAX77686. The driver implements read/write operations.
+config PMIC_PM8916
+ bool "Enable Driver Model for Qualcomm PM8916 PMIC"
+ depends on DM_PMIC
+ ---help---
+ The PM8916 is a PMIC connected to one (or several) processors
+ with SPMI bus. It has 2 slaves with several peripherals:
+ - 18x LDO
+ - 4x GPIO
+ - Power and Reset buttons
+ - Watchdog
+ - RTC
+ - Vibrator drivers
+ - Others
+
+ Driver binding info: doc/device-tree-bindings/pmic/pm8916.txt
+
config PMIC_RK808
bool "Enable support for Rockchip PMIC RK808"
depends on DM_PMIC
obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
obj-$(CONFIG_PMIC_ACT8846) += act8846.o
+obj-$(CONFIG_PMIC_PM8916) += pm8916.o
obj-$(CONFIG_PMIC_RK808) += rk808.o
obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
--- /dev/null
+/*
+ * Qualcomm pm8916 pmic driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <dm/root.h>
+#include <power/pmic.h>
+#include <spmi/spmi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PID_SHIFT 8
+#define PID_MASK (0xFF << PID_SHIFT)
+#define REG_MASK 0xFF
+
+struct pm8916_priv {
+ uint16_t usid; /* Slave ID on SPMI bus */
+};
+
+static int pm8916_reg_count(struct udevice *dev)
+{
+ return 0xFFFF;
+}
+
+static int pm8916_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+ struct pm8916_priv *priv = dev_get_priv(dev);
+
+ if (len != 1)
+ return -EINVAL;
+
+ return spmi_reg_write(dev->parent, priv->usid,
+ (reg & PID_MASK) >> PID_SHIFT, reg & REG_MASK,
+ *buff);
+}
+
+static int pm8916_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ struct pm8916_priv *priv = dev_get_priv(dev);
+ int val;
+
+ if (len != 1)
+ return -EINVAL;
+
+ val = spmi_reg_read(dev->parent, priv->usid,
+ (reg & PID_MASK) >> PID_SHIFT, reg & REG_MASK);
+
+ if (val < 0)
+ return val;
+ *buff = val;
+ return 0;
+}
+
+static struct dm_pmic_ops pm8916_ops = {
+ .reg_count = pm8916_reg_count,
+ .read = pm8916_read,
+ .write = pm8916_write,
+};
+
+static const struct udevice_id pm8916_ids[] = {
+ { .compatible = "qcom,spmi-pmic" },
+ { }
+};
+
+static int pm8916_probe(struct udevice *dev)
+{
+ struct pm8916_priv *priv = dev_get_priv(dev);
+
+ priv->usid = dev_get_addr(dev);
+
+ if (priv->usid == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return 0;
+}
+
+
+static int pm8916_bind(struct udevice *dev)
+{
+ return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+}
+
+U_BOOT_DRIVER(pmic_pm8916) = {
+ .name = "pmic_pm8916",
+ .id = UCLASS_PMIC,
+ .of_match = pm8916_ids,
+ .bind = pm8916_bind,
+ .probe = pm8916_probe,
+ .ops = &pm8916_ops,
+ .priv_auto_alloc_size = sizeof(struct pm8916_priv),
+};
will need to provide parameters to make this work. The driver will
be available until the real driver model serial is running.
+config DEBUG_UART_UNIPHIER
+ bool "UniPhier on-chip UART"
+ depends on ARCH_UNIPHIER
+ help
+ Select this to enable a debug UART using the UniPhier on-chip UART.
+ You will need to provide DEBUG_UART_BASE to make this work. The
+ driver will be available until the real driver-model serial is
+ running.
+
endchoice
config DEBUG_UART_BASE
If you have a Xilinx based board and want to use the uartlite
serial ports, say Y to this option. If unsure, say N.
+config MSM_SERIAL
+ bool "Qualcomm on-chip UART"
+ depends on DM_SERIAL
+ help
+ Support Data Mover UART used on Qualcomm Snapdragon SoCs.
+ It should support all Qualcomm devices with UARTDM version 1.4,
+ for example APQ8016 and MSM8916.
+ Single baudrate is supported in current implementation (115200).
endmenu
obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o
+obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o
+obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
int arc_console_baud = gd->cpu_clk / (baudrate * 4) - 1;
writeb(arc_console_baud & 0xff, ®s->baudl);
-
-#ifdef CONFIG_ARC
- /*
- * UART ISS(Instruction Set simulator) emulation has a subtle bug:
- * A existing value of Baudh = 0 is used as a indication to startup
- * it's internal state machine.
- * Thus if baudh is set to 0, 2 times, it chokes.
- * This happens with BAUD=115200 and the formaula above
- * Until that is fixed, when running on ISS, we will set baudh to !0
- */
- if (gd->arch.running_on_hw)
- writeb((arc_console_baud & 0xff00) >> 8, ®s->baudh);
- else
- writeb(1, ®s->baudh);
-#else
writeb((arc_console_baud & 0xff00) >> 8, ®s->baudh);
-#endif
return 0;
}
--- /dev/null
+/*
+ * (C) Copyright 2016 Stephen Warren <swarren@wwwdotorg.org>
+ *
+ * Derived from pl01x code:
+ *
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Simple U-Boot driver for the BCM283x mini UART */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <serial.h>
+#include <dm/platform_data/serial_bcm283x_mu.h>
+#include <linux/compiler.h>
+#include <fdtdec.h>
+
+struct bcm283x_mu_regs {
+ u32 io;
+ u32 iir;
+ u32 ier;
+ u32 lcr;
+ u32 mcr;
+ u32 lsr;
+ u32 msr;
+ u32 scratch;
+ u32 cntl;
+ u32 stat;
+ u32 baud;
+};
+
+#define BCM283X_MU_LCR_DATA_SIZE_8 3
+
+#define BCM283X_MU_LSR_TX_IDLE BIT(6)
+/* This actually means not full, but is named not empty in the docs */
+#define BCM283X_MU_LSR_TX_EMPTY BIT(5)
+#define BCM283X_MU_LSR_RX_READY BIT(0)
+
+struct bcm283x_mu_priv {
+ struct bcm283x_mu_regs *regs;
+};
+
+static int bcm283x_mu_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
+ struct bcm283x_mu_priv *priv = dev_get_priv(dev);
+ struct bcm283x_mu_regs *regs = priv->regs;
+ u32 divider;
+
+ if (plat->skip_init)
+ return 0;
+
+ divider = plat->clock / (baudrate * 8);
+
+ writel(BCM283X_MU_LCR_DATA_SIZE_8, ®s->lcr);
+ writel(divider - 1, ®s->baud);
+
+ return 0;
+}
+
+static int bcm283x_mu_serial_probe(struct udevice *dev)
+{
+ struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
+ struct bcm283x_mu_priv *priv = dev_get_priv(dev);
+
+ priv->regs = (struct bcm283x_mu_regs *)plat->base;
+
+ return 0;
+}
+
+static int bcm283x_mu_serial_getc(struct udevice *dev)
+{
+ struct bcm283x_mu_priv *priv = dev_get_priv(dev);
+ struct bcm283x_mu_regs *regs = priv->regs;
+ u32 data;
+
+ /* Wait until there is data in the FIFO */
+ if (!(readl(®s->lsr) & BCM283X_MU_LSR_RX_READY))
+ return -EAGAIN;
+
+ data = readl(®s->io);
+
+ return (int)data;
+}
+
+static int bcm283x_mu_serial_putc(struct udevice *dev, const char data)
+{
+ struct bcm283x_mu_priv *priv = dev_get_priv(dev);
+ struct bcm283x_mu_regs *regs = priv->regs;
+
+ /* Wait until there is space in the FIFO */
+ if (!(readl(®s->lsr) & BCM283X_MU_LSR_TX_EMPTY))
+ return -EAGAIN;
+
+ /* Send the character */
+ writel(data, ®s->io);
+
+ return 0;
+}
+
+static int bcm283x_mu_serial_pending(struct udevice *dev, bool input)
+{
+ struct bcm283x_mu_priv *priv = dev_get_priv(dev);
+ struct bcm283x_mu_regs *regs = priv->regs;
+ unsigned int lsr = readl(®s->lsr);
+
+ if (input) {
+ WATCHDOG_RESET();
+ return lsr & BCM283X_MU_LSR_RX_READY;
+ } else {
+ return !(lsr & BCM283X_MU_LSR_TX_IDLE);
+ }
+}
+
+static const struct dm_serial_ops bcm283x_mu_serial_ops = {
+ .putc = bcm283x_mu_serial_putc,
+ .pending = bcm283x_mu_serial_pending,
+ .getc = bcm283x_mu_serial_getc,
+ .setbrg = bcm283x_mu_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_bcm283x_mu) = {
+ .name = "serial_bcm283x_mu",
+ .id = UCLASS_SERIAL,
+ .platdata_auto_alloc_size = sizeof(struct bcm283x_mu_serial_platdata),
+ .probe = bcm283x_mu_serial_probe,
+ .ops = &bcm283x_mu_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+ .priv_auto_alloc_size = sizeof(struct bcm283x_mu_priv),
+};
--- /dev/null
+/*
+ * Qualcomm UART driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * UART will work in Data Mover mode.
+ * Based on Linux driver.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <errno.h>
+#include <serial.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+
+/* Serial registers - this driver works in uartdm mode*/
+
+#define UARTDM_DMRX 0x34 /* Max RX transfer length */
+#define UARTDM_NCF_TX 0x40 /* Number of chars to TX */
+
+#define UARTDM_RXFS 0x50 /* RX channel status register */
+#define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer */
+#define UARTDM_RXFS_BUF_MASK 0x7
+
+#define UARTDM_SR 0xA4 /* Status register */
+#define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */
+#define UARTDM_SR_TX_EMPTY (1 << 3) /* Transmitter underrun */
+#define UARTDM_SR_UART_OVERRUN (1 << 4) /* Receive overrun */
+
+#define UARTDM_CR 0xA8 /* Command register */
+#define UARTDM_CR_CMD_RESET_ERR (3 << 4) /* Clear overrun error */
+#define UARTDM_CR_CMD_RESET_STALE_INT (8 << 4) /* Clears stale irq */
+#define UARTDM_CR_CMD_RESET_TX_READY (3 << 8) /* Clears TX Ready irq*/
+#define UARTDM_CR_CMD_FORCE_STALE (4 << 8) /* Causes stale event */
+#define UARTDM_CR_CMD_STALE_EVENT_DISABLE (6 << 8) /* Disable stale event */
+
+#define UARTDM_IMR 0xB0 /* Interrupt mask register */
+#define UARTDM_ISR 0xB4 /* Interrupt status register */
+#define UARTDM_ISR_TX_READY 0x80 /* TX FIFO empty */
+
+#define UARTDM_TF 0x100 /* UART Transmit FIFO register */
+#define UARTDM_RF 0x140 /* UART Receive FIFO register */
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct msm_serial_data {
+ phys_addr_t base;
+ unsigned chars_cnt; /* number of buffered chars */
+ uint32_t chars_buf; /* buffered chars */
+};
+
+static int msm_serial_fetch(struct udevice *dev)
+{
+ struct msm_serial_data *priv = dev_get_priv(dev);
+ unsigned sr;
+
+ if (priv->chars_cnt)
+ return priv->chars_cnt;
+
+ /* Clear error in case of buffer overrun */
+ if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
+ writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
+
+ /* We need to fetch new character */
+ sr = readl(priv->base + UARTDM_SR);
+
+ if (sr & UARTDM_SR_RX_READY) {
+ /* There are at least 4 bytes in fifo */
+ priv->chars_buf = readl(priv->base + UARTDM_RF);
+ priv->chars_cnt = 4;
+ } else {
+ /* Check if there is anything in fifo */
+ priv->chars_cnt = readl(priv->base + UARTDM_RXFS);
+ /* Extract number of characters in UART packing buffer*/
+ priv->chars_cnt = (priv->chars_cnt >>
+ UARTDM_RXFS_BUF_SHIFT) &
+ UARTDM_RXFS_BUF_MASK;
+ if (!priv->chars_cnt)
+ return 0;
+
+ /* There is at least one charcter, move it to fifo */
+ writel(UARTDM_CR_CMD_FORCE_STALE,
+ priv->base + UARTDM_CR);
+
+ priv->chars_buf = readl(priv->base + UARTDM_RF);
+ writel(UARTDM_CR_CMD_RESET_STALE_INT,
+ priv->base + UARTDM_CR);
+ writel(0x7, priv->base + UARTDM_DMRX);
+ }
+
+ return priv->chars_cnt;
+}
+
+static int msm_serial_getc(struct udevice *dev)
+{
+ struct msm_serial_data *priv = dev_get_priv(dev);
+ char c;
+
+ if (!msm_serial_fetch(dev))
+ return -EAGAIN;
+
+ c = priv->chars_buf & 0xFF;
+ priv->chars_buf >>= 8;
+ priv->chars_cnt--;
+
+ return c;
+}
+
+static int msm_serial_putc(struct udevice *dev, const char ch)
+{
+ struct msm_serial_data *priv = dev_get_priv(dev);
+
+ if (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
+ !(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
+ return -EAGAIN;
+
+ writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
+
+ writel(1, priv->base + UARTDM_NCF_TX);
+ writel(ch, priv->base + UARTDM_TF);
+
+ return 0;
+}
+
+static int msm_serial_pending(struct udevice *dev, bool input)
+{
+ if (input) {
+ if (msm_serial_fetch(dev))
+ return 1;
+ }
+
+ return 0;
+}
+
+static const struct dm_serial_ops msm_serial_ops = {
+ .putc = msm_serial_putc,
+ .pending = msm_serial_pending,
+ .getc = msm_serial_getc,
+};
+
+static int msm_uart_clk_init(struct udevice *dev)
+{
+ uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ "clock-frequency", 115200);
+ uint clkd[2]; /* clk_id and clk_no */
+ int clk_offset;
+ struct udevice *clk;
+ int ret;
+
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd,
+ 2);
+ if (ret)
+ return ret;
+
+ clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
+ if (clk_offset < 0)
+ return clk_offset;
+
+ ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk);
+ if (ret)
+ return ret;
+
+ ret = clk_set_periph_rate(clk, clkd[1], clk_rate);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int msm_serial_probe(struct udevice *dev)
+{
+ struct msm_serial_data *priv = dev_get_priv(dev);
+
+ msm_uart_clk_init(dev); /* Ignore return value and hope clock was
+ properly initialized by earlier loaders */
+
+ if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
+ writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
+
+ writel(0, priv->base + UARTDM_IMR);
+ writel(UARTDM_CR_CMD_STALE_EVENT_DISABLE, priv->base + UARTDM_CR);
+ msm_serial_fetch(dev);
+
+ return 0;
+}
+
+static int msm_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct msm_serial_data *priv = dev_get_priv(dev);
+
+ priv->base = dev_get_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct udevice_id msm_serial_ids[] = {
+ { .compatible = "qcom,msm-uartdm-v1.4" },
+ { }
+};
+
+U_BOOT_DRIVER(serial_msm) = {
+ .name = "serial_msm",
+ .id = UCLASS_SERIAL,
+ .of_match = msm_serial_ids,
+ .ofdata_to_platdata = msm_serial_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct msm_serial_data),
+ .probe = msm_serial_probe,
+ .ops = &msm_serial_ops,
+};
struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
struct pl01x_priv *priv = dev_get_priv(dev);
- pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, baudrate);
+ if (!plat->skip_init) {
+ pl01x_generic_setbrg(priv->regs, priv->type, plat->clock,
+ baudrate);
+ }
return 0;
}
priv->regs = (struct pl01x_regs *)plat->base;
priv->type = plat->type;
- return pl01x_generic_serial_init(priv->regs, priv->type);
+ if (!plat->skip_init)
+ return pl01x_generic_serial_init(priv->regs, priv->type);
+ else
+ return 0;
}
static int pl01x_serial_getc(struct udevice *dev)
#include <linux/io.h>
#include <linux/serial_reg.h>
+#include <linux/sizes.h>
#include <asm/errno.h>
#include <dm/device.h>
#include <mapmem.h>
struct uniphier_serial_private_data *priv = dev_get_priv(dev);
struct uniphier_serial __iomem *port;
fdt_addr_t base;
- fdt_size_t size;
u32 tmp;
- base = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
+ base = dev_get_addr(dev);
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
- port = map_sysmem(base, size);
+ port = map_sysmem(base, SZ_64);
if (!port)
return -ENOMEM;
return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
}
+static int mvebu_spi_claim_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+
+ /* Configure the chip-select in the CTRL register */
+ clrsetbits_le32(&plat->spireg->ctrl,
+ KWSPI_CS_MASK << KWSPI_CS_SHIFT,
+ spi_chip_select(dev) << KWSPI_CS_SHIFT);
+
+ return 0;
+}
+
static int mvebu_spi_probe(struct udevice *bus)
{
struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
}
static const struct dm_spi_ops mvebu_spi_ops = {
+ .claim_bus = mvebu_spi_claim_bus,
.xfer = mvebu_spi_xfer,
.set_speed = mvebu_spi_set_speed,
.set_mode = mvebu_spi_set_mode,
};
static const struct udevice_id mvebu_spi_ids[] = {
+ { .compatible = "marvell,armada-375-spi" },
{ .compatible = "marvell,armada-380-spi" },
{ .compatible = "marvell,armada-xp-spi" },
{ }
--- /dev/null
+menu "SPMI support"
+
+config SPMI
+ bool "Enable SPMI bus support"
+ depends on DM
+ ---help---
+ Select this to enable to support SPMI bus.
+ SPMI (System Power Management Interface) bus is used
+ to connect PMIC devices on various SoCs.
+
+config SPMI_MSM
+ boolean "Support Qualcomm SPMI bus"
+ depends on SPMI
+ ---help---
+ Support SPMI bus implementation found on Qualcomm Snapdragon SoCs.
+
+config SPMI_SANDBOX
+ boolean "Support for Sandbox SPMI bus"
+ depends on SPMI
+ ---help---
+ Demo SPMI bus implementation. Emulates part of PM8916 as single
+ slave (0) on bus. It has 4 GPIO peripherals, pid 0xC0-0xC3.
+endmenu
--- /dev/null
+#
+# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_SPMI) += spmi-uclass.o
+obj-$(CONFIG_SPMI_MSM) += spmi-msm.o
+obj-$(CONFIG_SPMI_SANDBOX) += spmi-sandbox.o
--- /dev/null
+/*
+ * Qualcomm SPMI bus driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * Loosely based on Little Kernel driver
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <spmi/spmi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
+#define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
+
+#define SPMI_REG_CMD0 0x0
+#define SPMI_REG_CONFIG 0x4
+#define SPMI_REG_STATUS 0x8
+#define SPMI_REG_WDATA 0x10
+#define SPMI_REG_RDATA 0x18
+
+#define SPMI_CMD_OPCODE_SHIFT 27
+#define SPMI_CMD_SLAVE_ID_SHIFT 20
+#define SPMI_CMD_ADDR_SHIFT 12
+#define SPMI_CMD_ADDR_OFFSET_SHIFT 4
+#define SPMI_CMD_BYTE_CNT_SHIFT 0
+
+#define SPMI_CMD_EXT_REG_WRITE_LONG 0x00
+#define SPMI_CMD_EXT_REG_READ_LONG 0x01
+
+#define SPMI_STATUS_DONE 0x1
+
+#define SPMI_MAX_CHANNELS 128
+#define SPMI_MAX_SLAVES 16
+#define SPMI_MAX_PERIPH 256
+
+struct msm_spmi_priv {
+ phys_addr_t arb_chnl; /* ARB channel mapping base */
+ phys_addr_t spmi_core; /* SPMI core */
+ phys_addr_t spmi_obs; /* SPMI observer */
+ /* SPMI channel map */
+ uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
+};
+
+static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
+ uint8_t val)
+{
+ struct msm_spmi_priv *priv = dev_get_priv(dev);
+ unsigned channel;
+ uint32_t reg = 0;
+
+ if (usid >= SPMI_MAX_SLAVES)
+ return -EIO;
+ if (pid >= SPMI_MAX_PERIPH)
+ return -EIO;
+
+ channel = priv->channel_map[usid][pid];
+
+ /* Disable IRQ mode for the current channel*/
+ writel(0x0, priv->spmi_core + SPMI_CH_OFFSET(channel) +
+ SPMI_REG_CONFIG);
+
+ /* Write single byte */
+ writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
+
+ /* Prepare write command */
+ reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
+ reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
+ reg |= (pid << SPMI_CMD_ADDR_SHIFT);
+ reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
+ reg |= 1; /* byte count */
+
+ /* Send write command */
+ writel(reg, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
+
+ /* Wait till CMD DONE status */
+ reg = 0;
+ while (!reg) {
+ reg = readl(priv->spmi_core + SPMI_CH_OFFSET(channel) +
+ SPMI_REG_STATUS);
+ }
+
+ if (reg ^ SPMI_STATUS_DONE) {
+ printf("SPMI write failure.\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int msm_spmi_read(struct udevice *dev, int usid, int pid, int off)
+{
+ struct msm_spmi_priv *priv = dev_get_priv(dev);
+ unsigned channel;
+ uint32_t reg = 0;
+
+ if (usid >= SPMI_MAX_SLAVES)
+ return -EIO;
+ if (pid >= SPMI_MAX_PERIPH)
+ return -EIO;
+
+ channel = priv->channel_map[usid][pid];
+
+ /* Disable IRQ mode for the current channel*/
+ writel(0x0, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
+
+ /* Prepare read command */
+ reg |= SPMI_CMD_EXT_REG_READ_LONG << SPMI_CMD_OPCODE_SHIFT;
+ reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
+ reg |= (pid << SPMI_CMD_ADDR_SHIFT);
+ reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
+ reg |= 1; /* byte count */
+
+ /* Request read */
+ writel(reg, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
+
+ /* Wait till CMD DONE status */
+ reg = 0;
+ while (!reg) {
+ reg = readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
+ SPMI_REG_STATUS);
+ }
+
+ if (reg ^ SPMI_STATUS_DONE) {
+ printf("SPMI read failure.\n");
+ return -EIO;
+ }
+
+ /* Read the data */
+ return readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
+ SPMI_REG_RDATA) & 0xFF;
+}
+
+static struct dm_spmi_ops msm_spmi_ops = {
+ .read = msm_spmi_read,
+ .write = msm_spmi_write,
+};
+
+static int msm_spmi_probe(struct udevice *dev)
+{
+ struct udevice *parent = dev->parent;
+ struct msm_spmi_priv *priv = dev_get_priv(dev);
+ int i;
+
+ priv->arb_chnl = dev_get_addr(dev);
+ priv->spmi_core = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
+ parent->of_offset,
+ dev->of_offset,
+ "reg", 1, NULL);
+ priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
+ parent->of_offset,
+ dev->of_offset, "reg",
+ 2, NULL);
+ if (priv->arb_chnl == FDT_ADDR_T_NONE ||
+ priv->spmi_core == FDT_ADDR_T_NONE ||
+ priv->spmi_obs == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ /* Scan peripherals connected to each SPMI channel */
+ for (i = 0; i < SPMI_MAX_CHANNELS ; i++) {
+ uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i));
+ uint8_t slave_id = (periph & 0xf0000) >> 16;
+ uint8_t pid = (periph & 0xff00) >> 8;
+
+ priv->channel_map[slave_id][pid] = i;
+ }
+ return 0;
+}
+
+static const struct udevice_id msm_spmi_ids[] = {
+ { .compatible = "qcom,spmi-pmic-arb" },
+ { }
+};
+
+U_BOOT_DRIVER(msm_spmi) = {
+ .name = "msm_spmi",
+ .id = UCLASS_SPMI,
+ .of_match = msm_spmi_ids,
+ .ops = &msm_spmi_ops,
+ .probe = msm_spmi_probe,
+ .priv_auto_alloc_size = sizeof(struct msm_spmi_priv),
+};
--- /dev/null
+/*
+ * Sample SPMI bus driver
+ *
+ * It emulates bus with single pm8916-like pmic that has only GPIO reigsters.
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <spmi/spmi.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define EMUL_GPIO_PID_START 0xC0
+#define EMUL_GPIO_PID_END 0xC3
+
+#define EMUL_GPIO_COUNT 4
+
+#define EMUL_GPIO_REG_END 0x46 /* Last valid register */
+
+#define EMUL_PERM_R 0x1
+#define EMUL_PERM_W 0x2
+#define EMUL_PERM_RW (EMUL_PERM_R | EMUL_PERM_W)
+
+struct sandbox_emul_fake_regs {
+ u8 value;
+ u8 access_mask;
+ u8 perms; /* Access permissions */
+};
+
+struct sandbox_emul_gpio {
+ /* Fake registers - need one more entry as REG_END is valid address. */
+ struct sandbox_emul_fake_regs r[EMUL_GPIO_REG_END + 1];
+};
+
+struct sandbox_spmi_priv {
+ struct sandbox_emul_gpio gpios[EMUL_GPIO_COUNT];
+};
+
+/* Check if valid register was requested */
+static bool check_address_valid(int usid, int pid, int off)
+{
+ if (usid != 0)
+ return false;
+ if (pid < EMUL_GPIO_PID_START || pid > EMUL_GPIO_PID_END)
+ return false;
+ if (off > EMUL_GPIO_REG_END)
+ return false;
+ return true;
+}
+
+static int sandbox_spmi_write(struct udevice *dev, int usid, int pid, int off,
+ uint8_t val)
+{
+ struct sandbox_spmi_priv *priv = dev_get_priv(dev);
+ struct sandbox_emul_fake_regs *regs;
+
+ if (!check_address_valid(usid, pid, off))
+ return -EIO;
+
+ regs = priv->gpios[pid & 0x3].r; /* Last 3 bits of pid are gpio # */
+
+ switch (off) {
+ case 0x40: /* Control */
+ val &= regs[off].access_mask;
+ if (((val & 0x30) == 0x10) || ((val & 0x30) == 0x20)) {
+ /* out/inout - set status register */
+ regs[0x8].value &= ~0x1;
+ regs[0x8].value |= val & 0x1;
+ }
+ break;
+ default:
+ if (regs[off].perms & EMUL_PERM_W)
+ regs[off].value = val & regs[off].access_mask;
+ }
+ return 0;
+}
+
+static int sandbox_spmi_read(struct udevice *dev, int usid, int pid, int off)
+{
+ struct sandbox_spmi_priv *priv = dev_get_priv(dev);
+ struct sandbox_emul_fake_regs *regs;
+
+ if (!check_address_valid(usid, pid, off))
+ return -EIO;
+
+ regs = priv->gpios[pid & 0x3].r; /* Last 3 bits of pid are gpio # */
+
+ if (regs[0x46].value == 0) /* Block disabled */
+ return 0;
+
+ switch (off) {
+ case 0x8: /* Status */
+ if (regs[0x46].value == 0) /* Block disabled */
+ return 0;
+ return regs[off].value;
+ default:
+ if (regs[off].perms & EMUL_PERM_R)
+ return regs[off].value;
+ else
+ return 0;
+ }
+}
+
+static struct dm_spmi_ops sandbox_spmi_ops = {
+ .read = sandbox_spmi_read,
+ .write = sandbox_spmi_write,
+};
+
+static int sandbox_spmi_probe(struct udevice *dev)
+{
+ struct sandbox_spmi_priv *priv = dev_get_priv(dev);
+ int i;
+
+ for (i = 0; i < EMUL_GPIO_COUNT; ++i) {
+ struct sandbox_emul_fake_regs *regs = priv->gpios[i].r;
+ regs[4].perms = EMUL_PERM_R;
+ regs[4].value = 0x10;
+ regs[5].perms = EMUL_PERM_R;
+ regs[5].value = 0x5;
+ regs[8].access_mask = 0x81;
+ regs[8].perms = EMUL_PERM_RW;
+ regs[0x40].access_mask = 0x7F;
+ regs[0x40].perms = EMUL_PERM_RW;
+ regs[0x41].access_mask = 7;
+ regs[0x41].perms = EMUL_PERM_RW;
+ regs[0x42].access_mask = 7;
+ regs[0x42].perms = EMUL_PERM_RW;
+ regs[0x42].value = 0x4;
+ regs[0x45].access_mask = 0x3F;
+ regs[0x45].perms = EMUL_PERM_RW;
+ regs[0x45].value = 0x1;
+ regs[0x46].access_mask = 0x80;
+ regs[0x46].perms = EMUL_PERM_RW;
+ regs[0x46].value = 0x80;
+ }
+ return 0;
+}
+
+static const struct udevice_id sandbox_spmi_ids[] = {
+ { .compatible = "sandbox,spmi" },
+ { }
+};
+
+U_BOOT_DRIVER(msm_spmi) = {
+ .name = "sandbox_spmi",
+ .id = UCLASS_SPMI,
+ .of_match = sandbox_spmi_ids,
+ .ops = &sandbox_spmi_ops,
+ .probe = sandbox_spmi_probe,
+ .priv_auto_alloc_size = sizeof(struct sandbox_spmi_priv),
+};
--- /dev/null
+/*
+ * SPMI bus uclass driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/root.h>
+#include <spmi/spmi.h>
+#include <linux/ctype.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spmi_reg_read(struct udevice *dev, int usid, int pid, int reg)
+{
+ const struct dm_spmi_ops *ops = dev_get_driver_ops(dev);
+
+ if (!ops || !ops->read)
+ return -ENOSYS;
+
+ return ops->read(dev, usid, pid, reg);
+}
+
+int spmi_reg_write(struct udevice *dev, int usid, int pid, int reg,
+ uint8_t value)
+{
+ const struct dm_spmi_ops *ops = dev_get_driver_ops(dev);
+
+ if (!ops || !ops->write)
+ return -ENOSYS;
+
+ return ops->write(dev, usid, pid, reg, value);
+}
+
+static int spmi_post_bind(struct udevice *dev)
+{
+ return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+}
+
+UCLASS_DRIVER(spmi) = {
+ .id = UCLASS_SPMI,
+ .name = "spmi",
+ .post_bind = spmi_post_bind,
+};
rsk.struct_version = 2;
rsk.uid = ROLLBACK_SPACE_KERNEL_UID;
rsk.kernel_versions = 0;
- rsk.crc8 = crc8((unsigned char *)&rsk,
+ rsk.crc8 = crc8(0, (unsigned char *)&rsk,
offsetof(struct rollback_space_kernel,
crc8));
memcpy(data, &rsk, sizeof(rsk));
source "drivers/usb/emul/Kconfig"
+source "drivers/usb/ulpi/Kconfig"
+
comment "USB peripherals"
config USB_STORAGE
endif
+source "drivers/usb/gadget/Kconfig"
+
endif
--- /dev/null
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_USB_EHCI_FSL) += fsl-dt-fixup.o
+obj-$(CONFIG_USB_XHCI_FSL) += fsl-dt-fixup.o
--- /dev/null
+/*
+ * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
+ *
+ * Author: Tor Krill tor@excito.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <hwconfig.h>
+#include <fsl_usb.h>
+#include <fdt_support.h>
+
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
+static const char * const compat_usb_fsl[] = {
+ "fsl-usb2-mph",
+ "fsl-usb2-dr",
+ "snps,dwc3",
+ NULL
+};
+
+static int fdt_usb_get_node_type(void *blob, int start_offset,
+ int *node_offset, const char **node_type)
+{
+ int i;
+ int ret = -ENOENT;
+
+ for (i = 0; compat_usb_fsl[i]; i++) {
+ *node_offset = fdt_node_offset_by_compatible
+ (blob, start_offset,
+ compat_usb_fsl[i]);
+ if (*node_offset >= 0) {
+ *node_type = compat_usb_fsl[i];
+ ret = 0;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
+ const char *phy_type, int start_offset)
+{
+ const char *prop_mode = "dr_mode";
+ const char *prop_type = "phy_type";
+ const char *node_type = NULL;
+ int node_offset;
+ int err;
+
+ err = fdt_usb_get_node_type(blob, start_offset,
+ &node_offset, &node_type);
+ if (err < 0)
+ return err;
+
+ if (mode) {
+ err = fdt_setprop(blob, node_offset, prop_mode, mode,
+ strlen(mode) + 1);
+ if (err < 0)
+ printf("WARNING: could not set %s for %s: %s.\n",
+ prop_mode, node_type, fdt_strerror(err));
+ }
+
+ if (phy_type) {
+ err = fdt_setprop(blob, node_offset, prop_type, phy_type,
+ strlen(phy_type) + 1);
+ if (err < 0)
+ printf("WARNING: could not set %s for %s: %s.\n",
+ prop_type, node_type, fdt_strerror(err));
+ }
+
+ return node_offset;
+}
+
+static int fdt_fixup_usb_erratum(void *blob, const char *prop_erratum,
+ int start_offset)
+{
+ int node_offset, err;
+ const char *node_type = NULL;
+
+ err = fdt_usb_get_node_type(blob, start_offset,
+ &node_offset, &node_type);
+ if (err < 0)
+ return err;
+
+ err = fdt_setprop(blob, node_offset, prop_erratum, NULL, 0);
+ if (err < 0) {
+ printf("ERROR: could not set %s for %s: %s.\n",
+ prop_erratum, node_type, fdt_strerror(err));
+ }
+
+ return node_offset;
+}
+
+void fdt_fixup_dr_usb(void *blob, bd_t *bd)
+{
+ static const char * const modes[] = { "host", "peripheral", "otg" };
+ static const char * const phys[] = { "ulpi", "utmi", "utmi_dual" };
+ int usb_erratum_a006261_off = -1;
+ int usb_erratum_a007075_off = -1;
+ int usb_erratum_a007792_off = -1;
+ int usb_erratum_a005697_off = -1;
+ int usb_mode_off = -1;
+ int usb_phy_off = -1;
+ char str[5];
+ int i, j;
+
+ for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
+ const char *dr_mode_type = NULL;
+ const char *dr_phy_type = NULL;
+ int mode_idx = -1, phy_idx = -1;
+
+ snprintf(str, 5, "%s%d", "usb", i);
+ if (hwconfig(str)) {
+ for (j = 0; j < ARRAY_SIZE(modes); j++) {
+ if (hwconfig_subarg_cmp(str, "dr_mode",
+ modes[j])) {
+ mode_idx = j;
+ break;
+ }
+ }
+
+ for (j = 0; j < ARRAY_SIZE(phys); j++) {
+ if (hwconfig_subarg_cmp(str, "phy_type",
+ phys[j])) {
+ phy_idx = j;
+ break;
+ }
+ }
+
+ if (mode_idx < 0 && phy_idx < 0) {
+ printf("WARNING: invalid phy or mode\n");
+ return;
+ }
+
+ if (mode_idx > -1)
+ dr_mode_type = modes[mode_idx];
+
+ if (phy_idx > -1)
+ dr_phy_type = phys[phy_idx];
+ }
+
+ if (has_dual_phy())
+ dr_phy_type = phys[2];
+
+ usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
+ dr_mode_type, NULL,
+ usb_mode_off);
+
+ if (usb_mode_off < 0)
+ return;
+
+ usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
+ NULL, dr_phy_type,
+ usb_phy_off);
+
+ if (usb_phy_off < 0)
+ return;
+
+ if (has_erratum_a006261()) {
+ usb_erratum_a006261_off = fdt_fixup_usb_erratum
+ (blob,
+ "fsl,usb-erratum-a006261",
+ usb_erratum_a006261_off);
+ if (usb_erratum_a006261_off < 0)
+ return;
+ }
+
+ if (has_erratum_a007075()) {
+ usb_erratum_a007075_off = fdt_fixup_usb_erratum
+ (blob,
+ "fsl,usb-erratum-a007075",
+ usb_erratum_a007075_off);
+ if (usb_erratum_a007075_off < 0)
+ return;
+ }
+
+ if (has_erratum_a007792()) {
+ usb_erratum_a007792_off = fdt_fixup_usb_erratum
+ (blob,
+ "fsl,usb-erratum-a007792",
+ usb_erratum_a007792_off);
+ if (usb_erratum_a007792_off < 0)
+ return;
+ }
+ if (has_erratum_a005697()) {
+ usb_erratum_a005697_off = fdt_fixup_usb_erratum
+ (blob,
+ "fsl,usb-erratum-a005697",
+ usb_erratum_a005697_off);
+ if (usb_erratum_a005697_off < 0)
+ return;
+ }
+ }
+}
length + sizeof(packet_len) + sizeof(tx_hdr2),
&actual_len,
USB_BULK_SEND_TIMEOUT);
- debug("Tx: len = %u, actual = %u, err = %d\n",
+ debug("Tx: len = %zu, actual = %u, err = %d\n",
length + sizeof(packet_len), actual_len, err);
return err;
len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
USB_VENDOR_REQUEST_READ_REGISTER,
USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
- 0, index, tmpbuf, sizeof(data),
+ 0, index, tmpbuf, sizeof(*data),
USB_CTRL_GET_TIMEOUT);
*data = tmpbuf[0];
- if (len != sizeof(data)) {
+ if (len != sizeof(*data)) {
debug("smsc95xx_read_reg failed: index=%d, len=%d",
index, len);
return -EIO;
--- /dev/null
+#
+# USB Gadget support on a system involves
+# (a) a peripheral controller, and
+# (b) the gadget driver using it.
+#
+# NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
+#
+# - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
+# - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
+# - Some systems have both kinds of controllers.
+#
+# With help from a special transceiver and a "Mini-AB" jack, systems with
+# both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
+#
+
+menuconfig USB_GADGET
+ bool "USB Gadget Support"
+ help
+ USB is a master/slave protocol, organized with one master
+ host (such as a PC) controlling up to 127 peripheral devices.
+ The USB hardware is asymmetric, which makes it easier to set up:
+ you can't connect a "to-the-host" connector to a peripheral.
+
+ U-Boot can run in the host, or in the peripheral. In both cases
+ you need a low level bus controller driver, and some software
+ talking to it. Peripheral controllers are often discrete silicon,
+ or are integrated with the CPU in a microcontroller. The more
+ familiar host side controllers have names like "EHCI", "OHCI",
+ or "UHCI", and are usually integrated into southbridges on PC
+ motherboards.
+
+ Enable this configuration option if you want to run U-Boot inside
+ a USB peripheral device. Configure one hardware driver for your
+ peripheral/device side bus controller, and a "gadget driver" for
+ your peripheral protocol.
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
#include "dwc2_udc_otg_priv.h"
#include "bcm_udc_otg.h"
void otg_phy_init(struct dwc2_udc *dev)
{
+ /* turn on the USB OTG clocks */
+ clk_usb_otg_enable((void *)HSOTG_BASE_ADDR);
+
/* set Phy to driving mode */
wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
else
strcpy(response, "FAILValue not set");
} else {
- printf("WARNING: unknown variable: %s\n", cmd);
- strcpy(response, "FAILVariable not implemented");
+ char envstr[32];
+
+ snprintf(envstr, sizeof(envstr) - 1, "fastboot.%s", cmd);
+ s = getenv(envstr);
+ if (s) {
+ strncat(response, s, chars_left);
+ } else {
+ printf("WARNING: unknown variable: %s\n", cmd);
+ strcpy(response, "FAILVariable not implemented");
+ }
}
fastboot_tx_write_str(response);
}
---help---
Enables support for the on-chip EHCI controller on i.MX6 SoCs.
+config USB_EHCI_MSM
+ bool "Support for Qualcomm on-chip EHCI USB controller"
+ depends on DM_USB
+ select USB_ULPI_VIEWPORT
+ default n
+ ---help---
+ Enables support for the on-chip EHCI controller on Qualcomm
+ Snapdragon SoCs.
+ This driver supports combination of Chipidea USB controller
+ and Synapsys USB PHY in host mode only.
+
config USB_EHCI_GENERIC
bool "Support for generic EHCI USB controller"
depends on OF_CONTROL
obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
+obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o
obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
#include <pci.h>
#include <usb.h>
#include <asm/io.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
#include <hwconfig.h>
#include <fsl_usb.h>
#include <fdt_support.h>
cmd |= TXFIFO_THRESH(txfifo_thresh);
ehci_writel(&ehci->txfilltuning, cmd);
}
-
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
- const char *phy_type, int start_offset)
-{
- const char *compat_dr = "fsl-usb2-dr";
- const char *compat_mph = "fsl-usb2-mph";
- const char *prop_mode = "dr_mode";
- const char *prop_type = "phy_type";
- const char *node_type = NULL;
- int node_offset;
- int err;
-
- node_offset = fdt_node_offset_by_compatible(blob,
- start_offset, compat_mph);
- if (node_offset < 0) {
- node_offset = fdt_node_offset_by_compatible(blob,
- start_offset,
- compat_dr);
- if (node_offset < 0) {
- printf("WARNING: could not find compatible node: %s",
- fdt_strerror(node_offset));
- return -1;
- }
- node_type = compat_dr;
- } else {
- node_type = compat_mph;
- }
-
- if (mode) {
- err = fdt_setprop(blob, node_offset, prop_mode, mode,
- strlen(mode) + 1);
- if (err < 0)
- printf("WARNING: could not set %s for %s: %s.\n",
- prop_mode, node_type, fdt_strerror(err));
- }
-
- if (phy_type) {
- err = fdt_setprop(blob, node_offset, prop_type, phy_type,
- strlen(phy_type) + 1);
- if (err < 0)
- printf("WARNING: could not set %s for %s: %s.\n",
- prop_type, node_type, fdt_strerror(err));
- }
-
- return node_offset;
-}
-
-static const char *fdt_usb_get_node_type(void *blob, int start_offset,
- int *node_offset)
-{
- const char *compat_dr = "fsl-usb2-dr";
- const char *compat_mph = "fsl-usb2-mph";
- const char *node_type = NULL;
-
- *node_offset = fdt_node_offset_by_compatible(blob, start_offset,
- compat_mph);
- if (*node_offset < 0) {
- *node_offset = fdt_node_offset_by_compatible(blob,
- start_offset,
- compat_dr);
- if (*node_offset < 0) {
- printf("ERROR: could not find compatible node: %s\n",
- fdt_strerror(*node_offset));
- } else {
- node_type = compat_dr;
- }
- } else {
- node_type = compat_mph;
- }
-
- return node_type;
-}
-
-static int fdt_fixup_usb_erratum(void *blob, const char *prop_erratum,
- int start_offset)
-{
- int node_offset, err;
- const char *node_type = NULL;
-
- node_type = fdt_usb_get_node_type(blob, start_offset, &node_offset);
- if (!node_type)
- return -1;
-
- err = fdt_setprop(blob, node_offset, prop_erratum, NULL, 0);
- if (err < 0) {
- printf("ERROR: could not set %s for %s: %s.\n",
- prop_erratum, node_type, fdt_strerror(err));
- }
-
- return node_offset;
-}
-
-void fdt_fixup_dr_usb(void *blob, bd_t *bd)
-{
- static const char * const modes[] = { "host", "peripheral", "otg" };
- static const char * const phys[] = { "ulpi", "utmi", "utmi_dual" };
- int usb_erratum_a006261_off = -1;
- int usb_erratum_a007075_off = -1;
- int usb_erratum_a007792_off = -1;
- int usb_erratum_a005697_off = -1;
- int usb_mode_off = -1;
- int usb_phy_off = -1;
- char str[5];
- int i, j;
-
- for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
- const char *dr_mode_type = NULL;
- const char *dr_phy_type = NULL;
- int mode_idx = -1, phy_idx = -1;
-
- snprintf(str, 5, "%s%d", "usb", i);
- if (hwconfig(str)) {
- for (j = 0; j < ARRAY_SIZE(modes); j++) {
- if (hwconfig_subarg_cmp(str, "dr_mode",
- modes[j])) {
- mode_idx = j;
- break;
- }
- }
-
- for (j = 0; j < ARRAY_SIZE(phys); j++) {
- if (hwconfig_subarg_cmp(str, "phy_type",
- phys[j])) {
- phy_idx = j;
- break;
- }
- }
-
- if (mode_idx < 0 && phy_idx < 0) {
- printf("WARNING: invalid phy or mode\n");
- return;
- }
-
- if (mode_idx > -1)
- dr_mode_type = modes[mode_idx];
-
- if (phy_idx > -1)
- dr_phy_type = phys[phy_idx];
- }
-
- if (has_dual_phy())
- dr_phy_type = phys[2];
-
- usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
- dr_mode_type, NULL,
- usb_mode_off);
-
- if (usb_mode_off < 0)
- return;
-
- usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
- NULL, dr_phy_type,
- usb_phy_off);
-
- if (usb_phy_off < 0)
- return;
-
- if (has_erratum_a006261()) {
- usb_erratum_a006261_off = fdt_fixup_usb_erratum
- (blob,
- "fsl,usb-erratum-a006261",
- usb_erratum_a006261_off);
- if (usb_erratum_a006261_off < 0)
- return;
- }
-
- if (has_erratum_a007075()) {
- usb_erratum_a007075_off = fdt_fixup_usb_erratum
- (blob,
- "fsl,usb-erratum-a007075",
- usb_erratum_a007075_off);
- if (usb_erratum_a007075_off < 0)
- return;
- }
-
- if (has_erratum_a007792()) {
- usb_erratum_a007792_off = fdt_fixup_usb_erratum
- (blob,
- "fsl,usb-erratum-a007792",
- usb_erratum_a007792_off);
- if (usb_erratum_a007792_off < 0)
- return;
- }
- if (has_erratum_a005697()) {
- usb_erratum_a005697_off = fdt_fixup_usb_erratum
- (blob,
- "fsl,usb-erratum-a005697",
- usb_erratum_a005697_off);
- if (usb_erratum_a005697_off < 0)
- return;
- }
- }
-}
-#endif
if (ret)
goto err;
+ if (ctrl->ops.init_after_reset) {
+ ret = ctrl->ops.init_after_reset(ctrl);
+ if (ret)
+ goto err;
+ }
+
ret = ehci_common_init(ctrl, tweaks);
if (ret)
goto err;
#include <pci.h>
#include <usb.h>
#include <asm/io.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
#include "ehci.h"
unsigned int i;
/* Command a reset of the USB Controller */
- out_be32(&(ehci->usbcmd), EHCI_FSL_USBCMD_RST);
+ out_be32(&(ehci->usbcmd), CMD_RESET);
/* Wait for the reset process to finish */
for (i = 65535 ; i > 0 ; i--) {
* The host will set this bit to zero once the
* reset process is complete
*/
- if ((in_be32(&(ehci->usbcmd)) & EHCI_FSL_USBCMD_RST) == 0)
+ if ((in_be32(&(ehci->usbcmd)) & CMD_RESET) == 0)
return 0;
}
--- /dev/null
+/*
+ * Qualcomm EHCI driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * Based on Linux driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include <usb/ulpi.h>
+#include <wait_bit.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/compat.h>
+#include "ehci.h"
+
+/* PHY viewport regs */
+#define ULPI_MISC_A_READ 0x96
+#define ULPI_MISC_A_SET 0x97
+#define ULPI_MISC_A_CLEAR 0x98
+#define ULPI_MISC_A_VBUSVLDEXTSEL (1 << 1)
+#define ULPI_MISC_A_VBUSVLDEXT (1 << 0)
+
+#define GEN2_SESS_VLD_CTRL_EN (1 << 7)
+
+#define SESS_VLD_CTRL (1 << 25)
+
+struct msm_ehci_priv {
+ struct ehci_ctrl ctrl; /* Needed by EHCI */
+ struct usb_ehci *ehci; /* Start of IP core*/
+ struct ulpi_viewport ulpi_vp; /* ULPI Viewport */
+};
+
+int __weak board_prepare_usb(enum usb_init_type type)
+{
+ return 0;
+}
+
+static void setup_usb_phy(struct msm_ehci_priv *priv)
+{
+ /* Select and enable external configuration with USB PHY */
+ ulpi_write(&priv->ulpi_vp, (u8 *)ULPI_MISC_A_SET,
+ ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT);
+}
+
+static void reset_usb_phy(struct msm_ehci_priv *priv)
+{
+ /* Disable VBUS mimicing in the controller. */
+ ulpi_write(&priv->ulpi_vp, (u8 *)ULPI_MISC_A_CLEAR,
+ ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT);
+}
+
+
+static int msm_init_after_reset(struct ehci_ctrl *dev)
+{
+ struct msm_ehci_priv *p = container_of(dev, struct msm_ehci_priv, ctrl);
+ struct usb_ehci *ehci = p->ehci;
+
+ /* select ULPI phy */
+ writel(PORT_PTS_ULPI, &ehci->portsc);
+ setup_usb_phy(p);
+
+ /* Enable sess_vld */
+ setbits_le32(&ehci->genconfig2, GEN2_SESS_VLD_CTRL_EN);
+
+ /* Enable external vbus configuration in the LINK */
+ setbits_le32(&ehci->usbcmd, SESS_VLD_CTRL);
+
+ /* USB_OTG_HS_AHB_BURST */
+ writel(0x0, &ehci->sbuscfg);
+
+ /* USB_OTG_HS_AHB_MODE: HPROT_MODE */
+ /* Bus access related config. */
+ writel(0x08, &ehci->sbusmode);
+
+ /* set mode to host controller */
+ writel(CM_HOST, &ehci->usbmode);
+
+ return 0;
+}
+
+static const struct ehci_ops msm_ehci_ops = {
+ .init_after_reset = msm_init_after_reset
+};
+
+static int ehci_usb_probe(struct udevice *dev)
+{
+ struct msm_ehci_priv *p = dev_get_priv(dev);
+ struct usb_ehci *ehci = p->ehci;
+ struct ehci_hccr *hccr;
+ struct ehci_hcor *hcor;
+ int ret;
+
+ hccr = (struct ehci_hccr *)((phys_addr_t)&ehci->caplength);
+ hcor = (struct ehci_hcor *)((phys_addr_t)hccr +
+ HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
+
+ ret = board_prepare_usb(USB_INIT_HOST);
+ if (ret < 0)
+ return ret;
+
+ return ehci_register(dev, hccr, hcor, &msm_ehci_ops, 0, USB_INIT_HOST);
+}
+
+static int ehci_usb_remove(struct udevice *dev)
+{
+ struct msm_ehci_priv *p = dev_get_priv(dev);
+ struct usb_ehci *ehci = p->ehci;
+ int ret;
+
+ ret = ehci_deregister(dev);
+ if (ret)
+ return ret;
+
+ /* Stop controller. */
+ clrbits_le32(&ehci->usbcmd, CMD_RUN);
+
+ reset_usb_phy(p);
+
+ ret = board_prepare_usb(USB_INIT_DEVICE); /* Board specific hook */
+ if (ret < 0)
+ return ret;
+
+ /* Reset controller */
+ setbits_le32(&ehci->usbcmd, CMD_RESET);
+
+ /* Wait for reset */
+ if (wait_for_bit(__func__, &ehci->usbcmd, CMD_RESET, false, 30,
+ false)) {
+ printf("Stuck on USB reset.\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct msm_ehci_priv *priv = dev_get_priv(dev);
+
+ priv->ulpi_vp.port_num = 0;
+ priv->ehci = (void *)dev_get_addr(dev);
+
+ if (priv->ehci == (void *)FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ /* Warning: this will not work if viewport address is > 64 bit due to
+ * ULPI design.
+ */
+ priv->ulpi_vp.viewport_addr = (phys_addr_t)&priv->ehci->ulpi_viewpoint;
+
+ return 0;
+}
+
+static const struct udevice_id ehci_usb_ids[] = {
+ { .compatible = "qcom,ehci-host", },
+ { }
+};
+
+U_BOOT_DRIVER(usb_ehci) = {
+ .name = "ehci_msm",
+ .id = UCLASS_USB,
+ .of_match = ehci_usb_ids,
+ .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
+ .probe = ehci_usb_probe,
+ .remove = ehci_usb_remove,
+ .ops = &ehci_usb_ops,
+ .priv_auto_alloc_size = sizeof(struct msm_ehci_priv),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
#include <usb.h>
#include <errno.h>
#include <linux/compiler.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <errno.h>
#include <wait_bit.h>
#include <linux/compiler.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <usb.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
#include <errno.h>
#include "ehci.h"
#include <dm.h>
#include "ehci.h"
+#ifdef CONFIG_SUNXI_GEN_SUN4I
+#define BASE_DIST 0x8000
+#define AHB_CLK_DIST 2
+#else
+#define BASE_DIST 0x1000
+#define AHB_CLK_DIST 1
+#endif
+
struct ehci_sunxi_priv {
struct ehci_ctrl ehci;
int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
struct ehci_sunxi_priv *priv = dev_get_priv(dev);
struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev);
struct ehci_hcor *hcor;
+ int extra_ahb_gate_mask = 0;
/*
* This should go away once we've moved to the driver model for
*/
priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
#ifdef CONFIG_MACH_SUN8I_H3
- priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_OHCI0;
+ extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
#endif
- priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / 0x1000 + 1;
- priv->ahb_gate_mask <<= priv->phy_index - 1;
+ priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / BASE_DIST;
+ priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
+ extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
+ priv->phy_index++; /* Non otg phys start at 1 */
- setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
+ setbits_le32(&ccm->ahb_gate0,
+ priv->ahb_gate_mask | extra_ahb_gate_mask);
#ifdef CONFIG_SUNXI_GEN_SUN6I
- setbits_le32(&ccm->ahb_reset0_cfg, priv->ahb_gate_mask);
+ setbits_le32(&ccm->ahb_reset0_cfg,
+ priv->ahb_gate_mask | extra_ahb_gate_mask);
#endif
sunxi_usb_phy_init(priv->phy_index);
{ .compatible = "allwinner,sun6i-a31-ehci", },
{ .compatible = "allwinner,sun7i-a20-ehci", },
{ .compatible = "allwinner,sun8i-a23-ehci", },
+ { .compatible = "allwinner,sun8i-a83t-ehci", },
{ .compatible = "allwinner,sun8i-h3-ehci", },
{ .compatible = "allwinner,sun9i-a80-ehci", },
{ }
#include <asm/arch/crm_regs.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/regs-usbphy.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
#include "ehci.h"
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <usb.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
#include <usb/ulpi.h>
#include "ehci.h"
void (*powerup_fixup)(struct ehci_ctrl *ctrl, uint32_t *status_reg,
uint32_t *reg);
uint32_t *(*get_portsc_register)(struct ehci_ctrl *ctrl, int port);
+ int (*init_after_reset)(struct ehci_ctrl *ctrl);
};
struct ehci_ctrl {
#include <usb.h>
#include "ohci.h"
+#ifdef CONFIG_SUNXI_GEN_SUN4I
+#define BASE_DIST 0x8000
+#define AHB_CLK_DIST 2
+#else
+#define BASE_DIST 0x1000
+#define AHB_CLK_DIST 1
+#endif
+
struct ohci_sunxi_priv {
ohci_t ohci;
int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
struct ohci_sunxi_priv *priv = dev_get_priv(dev);
struct ohci_regs *regs = (struct ohci_regs *)dev_get_addr(dev);
+ int extra_ahb_gate_mask = 0;
bus_priv->companion = true;
*/
priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
#ifdef CONFIG_MACH_SUN8I_H3
- priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_EHCI0;
+ extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
#endif
priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
- priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / 0x1000 + 1;
- priv->ahb_gate_mask <<= priv->phy_index - 1;
- priv->usb_gate_mask <<= priv->phy_index - 1;
+ priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST;
+ priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
+ extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
+ priv->usb_gate_mask <<= priv->phy_index;
+ priv->phy_index++; /* Non otg phys start at 1 */
- setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
+ setbits_le32(&ccm->ahb_gate0,
+ priv->ahb_gate_mask | extra_ahb_gate_mask);
setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask);
#ifdef CONFIG_SUNXI_GEN_SUN6I
- setbits_le32(&ccm->ahb_reset0_cfg, priv->ahb_gate_mask);
+ setbits_le32(&ccm->ahb_reset0_cfg,
+ priv->ahb_gate_mask | extra_ahb_gate_mask);
#endif
sunxi_usb_phy_init(priv->phy_index);
{ .compatible = "allwinner,sun6i-a31-ohci", },
{ .compatible = "allwinner,sun7i-a20-ohci", },
{ .compatible = "allwinner,sun8i-a23-ohci", },
+ { .compatible = "allwinner,sun8i-a83t-ohci", },
{ .compatible = "allwinner,sun8i-h3-ohci", },
{ .compatible = "allwinner,sun9i-a80-ohci", },
{ }
if (usb_pipedevice(pipe) == ctrl->rootdev)
return xhci_submit_root(udev, pipe, buffer, setup);
- if (setup->request == USB_REQ_SET_ADDRESS)
+ if (setup->request == USB_REQ_SET_ADDRESS &&
+ (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD)
return xhci_address_device(udev, root_portnr);
- if (setup->request == USB_REQ_SET_CONFIGURATION) {
+ if (setup->request == USB_REQ_SET_CONFIGURATION &&
+ (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
ret = xhci_set_configuration(udev);
if (ret) {
puts("Failed to configure xHCI endpoint\n");
if USB_MUSB_HOST || USB_MUSB_GADGET
+config USB_MUSB_PIC32
+ bool "Enable Microchip PIC32 DRC USB controller"
+ depends on DM_USB && MACH_PIC32
+ help
+ Say y to enable PIC32 USB DRC controller support
+ if it is available on your Microchip PIC32 platform.
+
config USB_MUSB_SUNXI
bool "Enable sunxi OTG / DRC USB controller"
depends on ARCH_SUNXI
obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o
obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o
obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
+obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
ccflags-y := $(call cc-option,-Wno-unused-variable) \
printf(fmt, ##args); \
ret_warn; })
-#define writesl(a, d, s) __raw_writesl((unsigned long)a, d, s)
-#define readsl(a, d, s) __raw_readsl((unsigned long)a, d, s)
-#define writesw(a, d, s) __raw_writesw((unsigned long)a, d, s)
-#define readsw(a, d, s) __raw_readsw((unsigned long)a, d, s)
-#define writesb(a, d, s) __raw_writesb((unsigned long)a, d, s)
-#define readsb(a, d, s) __raw_readsb((unsigned long)a, d, s)
-
#define device_init_wakeup(dev, a) do {} while (0)
#define platform_data device_data
}
}
-#if !defined(CONFIG_USB_MUSB_AM35X)
+#if !defined(CONFIG_USB_MUSB_AM35X) && !defined(CONFIG_USB_MUSB_PIC32)
/*
* Unload an endpoint's FIFO
*/
static inline u8 musb_read_configdata(void __iomem *mbase)
{
-#ifdef CONFIG_MACH_SUN8I_A33
+#if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T
/* <Sigh> allwinner saves a reg, and we need to hardcode this */
return 0xde;
#else
if (musb_readb(mbase, MUSB_DEVCTL) & MUSB_DEVCTL_HM)
break;
} while (get_timer(0) < timeout);
- if (get_timer(0) >= timeout)
+ if (get_timer(0) >= timeout) {
+ musb_stop(host->host);
return -ENODEV;
+ }
_musb_reset_root_port(host, NULL);
host->host->is_active = 1;
--- /dev/null
+/*
+ * Microchip PIC32 MUSB "glue layer"
+ *
+ * Copyright (C) 2015, Microchip Technology Inc.
+ * Cristian Birsan <cristian.birsan@microchip.com>
+ * Purna Chandra Mandal <purna.mandal@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Based on the dsps "glue layer" code.
+ */
+
+#include <common.h>
+#include <linux/usb/musb.h>
+#include "linux-compat.h"
+#include "musb_core.h"
+#include "musb_uboot.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PIC32_TX_EP_MASK 0x0f /* EP0 + 7 Tx EPs */
+#define PIC32_RX_EP_MASK 0x0e /* 7 Rx EPs */
+
+#define MUSB_SOFTRST 0x7f
+#define MUSB_SOFTRST_NRST BIT(0)
+#define MUSB_SOFTRST_NRSTX BIT(1)
+
+#define USBCRCON 0
+#define USBCRCON_USBWKUPEN BIT(0) /* Enable Wakeup Interrupt */
+#define USBCRCON_USBRIE BIT(1) /* Enable Remote resume Interrupt */
+#define USBCRCON_USBIE BIT(2) /* Enable USB General interrupt */
+#define USBCRCON_SENDMONEN BIT(3) /* Enable Session End VBUS monitoring */
+#define USBCRCON_BSVALMONEN BIT(4) /* Enable B-Device VBUS monitoring */
+#define USBCRCON_ASVALMONEN BIT(5) /* Enable A-Device VBUS monitoring */
+#define USBCRCON_VBUSMONEN BIT(6) /* Enable VBUS monitoring */
+#define USBCRCON_PHYIDEN BIT(7) /* PHY ID monitoring enable */
+#define USBCRCON_USBIDVAL BIT(8) /* USB ID value */
+#define USBCRCON_USBIDOVEN BIT(9) /* USB ID override enable */
+#define USBCRCON_USBWK BIT(24) /* USB Wakeup Status */
+#define USBCRCON_USBRF BIT(25) /* USB Resume Status */
+#define USBCRCON_USBIF BIT(26) /* USB General Interrupt Status */
+
+/* PIC32 controller data */
+struct pic32_musb_data {
+ struct musb_host_data mdata;
+ struct device dev;
+ void __iomem *musb_glue;
+};
+
+#define to_pic32_musb_data(d) \
+ container_of(d, struct pic32_musb_data, dev)
+
+static void pic32_musb_disable(struct musb *musb)
+{
+ /* no way to shut the controller */
+}
+
+static int pic32_musb_enable(struct musb *musb)
+{
+ /* soft reset by NRSTx */
+ musb_writeb(musb->mregs, MUSB_SOFTRST, MUSB_SOFTRST_NRSTX);
+ /* set mode */
+ musb_platform_set_mode(musb, musb->board_mode);
+
+ return 0;
+}
+
+static irqreturn_t pic32_interrupt(int irq, void *hci)
+{
+ struct musb *musb = hci;
+ irqreturn_t ret = IRQ_NONE;
+ u32 epintr, usbintr;
+
+ /* ack usb core interrupts */
+ musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
+ if (musb->int_usb)
+ musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
+
+ /* ack endpoint interrupts */
+ musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX) & PIC32_RX_EP_MASK;
+ if (musb->int_rx)
+ musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
+
+ musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX) & PIC32_TX_EP_MASK;
+ if (musb->int_tx)
+ musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
+
+ /* drop spurious RX and TX if device is disconnected */
+ if (musb->int_usb & MUSB_INTR_DISCONNECT) {
+ musb->int_tx = 0;
+ musb->int_rx = 0;
+ }
+
+ if (musb->int_tx || musb->int_rx || musb->int_usb)
+ ret = musb_interrupt(musb);
+
+ return ret;
+}
+
+static int pic32_musb_set_mode(struct musb *musb, u8 mode)
+{
+ struct device *dev = musb->controller;
+ struct pic32_musb_data *pdata = to_pic32_musb_data(dev);
+
+ switch (mode) {
+ case MUSB_HOST:
+ clrsetbits_le32(pdata->musb_glue + USBCRCON,
+ USBCRCON_USBIDVAL, USBCRCON_USBIDOVEN);
+ break;
+ case MUSB_PERIPHERAL:
+ setbits_le32(pdata->musb_glue + USBCRCON,
+ USBCRCON_USBIDVAL | USBCRCON_USBIDOVEN);
+ break;
+ case MUSB_OTG:
+ dev_err(dev, "support for OTG is unimplemented\n");
+ break;
+ default:
+ dev_err(dev, "unsupported mode %d\n", mode);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int pic32_musb_init(struct musb *musb)
+{
+ struct pic32_musb_data *pdata = to_pic32_musb_data(musb->controller);
+ u32 ctrl, hwvers;
+ u8 power;
+
+ /* Returns zero if not clocked */
+ hwvers = musb_read_hwvers(musb->mregs);
+ if (!hwvers)
+ return -ENODEV;
+
+ /* Reset the musb */
+ power = musb_readb(musb->mregs, MUSB_POWER);
+ power = power | MUSB_POWER_RESET;
+ musb_writeb(musb->mregs, MUSB_POWER, power);
+ mdelay(100);
+
+ /* Start the on-chip PHY and its PLL. */
+ power = power & ~MUSB_POWER_RESET;
+ musb_writeb(musb->mregs, MUSB_POWER, power);
+
+ musb->isr = pic32_interrupt;
+
+ ctrl = USBCRCON_USBIF | USBCRCON_USBRF |
+ USBCRCON_USBWK | USBCRCON_USBIDOVEN |
+ USBCRCON_PHYIDEN | USBCRCON_USBIE |
+ USBCRCON_USBRIE | USBCRCON_USBWKUPEN |
+ USBCRCON_VBUSMONEN;
+ writel(ctrl, pdata->musb_glue + USBCRCON);
+
+ return 0;
+}
+
+/* PIC32 supports only 32bit read operation */
+void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
+{
+ void __iomem *fifo = hw_ep->fifo;
+ u32 val, rem = len % 4;
+
+ /* USB stack ensures dst is always 32bit aligned. */
+ readsl(fifo, dst, len / 4);
+ if (rem) {
+ dst += len & ~0x03;
+ val = musb_readl(fifo, 0);
+ memcpy(dst, &val, rem);
+ }
+}
+
+const struct musb_platform_ops pic32_musb_ops = {
+ .init = pic32_musb_init,
+ .set_mode = pic32_musb_set_mode,
+ .disable = pic32_musb_disable,
+ .enable = pic32_musb_enable,
+};
+
+/* PIC32 default FIFO config - fits in 8KB */
+static struct musb_fifo_cfg pic32_musb_fifo_config[] = {
+ { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
+ { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
+ { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
+ { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
+ { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
+ { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
+ { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
+ { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
+ { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
+ { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
+ { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
+ { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
+ { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
+ { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
+};
+
+static struct musb_hdrc_config pic32_musb_config = {
+ .fifo_cfg = pic32_musb_fifo_config,
+ .fifo_cfg_size = ARRAY_SIZE(pic32_musb_fifo_config),
+ .multipoint = 1,
+ .dyn_fifo = 1,
+ .num_eps = 8,
+ .ram_bits = 11,
+};
+
+/* PIC32 has one MUSB controller which can be host or gadget */
+static struct musb_hdrc_platform_data pic32_musb_plat = {
+ .mode = MUSB_HOST,
+ .config = &pic32_musb_config,
+ .power = 250, /* 500mA */
+ .platform_ops = &pic32_musb_ops,
+};
+
+static int musb_usb_probe(struct udevice *dev)
+{
+ struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
+ struct pic32_musb_data *pdata = dev_get_priv(dev);
+ struct musb_host_data *mdata = &pdata->mdata;
+ struct fdt_resource mc, glue;
+ void *fdt = (void *)gd->fdt_blob;
+ int node = dev->of_offset;
+ void __iomem *mregs;
+ int ret;
+
+ priv->desc_before_addr = true;
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "mc", &mc);
+ if (ret < 0) {
+ printf("pic32-musb: resource \"mc\" not found\n");
+ return ret;
+ }
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "control", &glue);
+ if (ret < 0) {
+ printf("pic32-musb: resource \"control\" not found\n");
+ return ret;
+ }
+
+ mregs = ioremap(mc.start, fdt_resource_size(&mc));
+ pdata->musb_glue = ioremap(glue.start, fdt_resource_size(&glue));
+
+ /* init controller */
+#ifdef CONFIG_USB_MUSB_HOST
+ mdata->host = musb_init_controller(&pic32_musb_plat,
+ &pdata->dev, mregs);
+ if (!mdata->host)
+ return -EIO;
+
+ ret = musb_lowlevel_init(mdata);
+#else
+ pic32_musb_plat.mode = MUSB_PERIPHERAL;
+ ret = musb_register(&pic32_musb_plat, &pdata->dev, mregs);
+#endif
+ if (ret == 0)
+ printf("PIC32 MUSB OTG\n");
+
+ return ret;
+}
+
+static int musb_usb_remove(struct udevice *dev)
+{
+ struct pic32_musb_data *pdata = dev_get_priv(dev);
+
+ musb_stop(pdata->mdata.host);
+
+ return 0;
+}
+
+static const struct udevice_id pic32_musb_ids[] = {
+ { .compatible = "microchip,pic32mzda-usb" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_musb) = {
+ .name = "pic32-musb",
+ .id = UCLASS_USB,
+ .of_match = pic32_musb_ids,
+ .probe = musb_usb_probe,
+ .remove = musb_usb_remove,
+#ifdef CONFIG_USB_MUSB_HOST
+ .ops = &musb_usb_ops,
+#endif
+ .platdata_auto_alloc_size = sizeof(struct usb_platdata),
+ .priv_auto_alloc_size = sizeof(struct pic32_musb_data),
+};
/* musb_core does not call enable / disable in a balanced manner <sigh> */
static bool enabled = false;
+static struct musb *sunxi_musb;
static int sunxi_musb_enable(struct musb *musb)
{
priv->desc_before_addr = true;
- if (!host->host) {
- host->host = musb_init_controller(&musb_plat, NULL,
+ if (!sunxi_musb) {
+ sunxi_musb = musb_init_controller(&musb_plat, NULL,
(void *)SUNXI_USB0_BASE);
- if (!host->host)
- return -EIO;
}
+ host->host = sunxi_musb;
+ if (!host->host)
+ return -EIO;
+
ret = musb_lowlevel_init(host);
if (ret == 0)
printf("MUSB OTG\n");
--- /dev/null
+comment "ULPI drivers"
+
+choice
+ prompt "ULPI Viewport type"
+ optional
+ default n
+ help
+ Select ULPI viewport (SoC-side interface to ULPI) implementation
+ appropriate for the device if you want to communicate with
+ UTMI (USB PHY) via ULPI interface.
+
+config USB_ULPI_VIEWPORT
+ bool "Generic ULPI Viewport"
+ help
+ Support generic ULPI Viewport implementation that is used on
+ some Tegra and Snapdragon devices.
+
+config USB_ULPI_VIEWPORT_OMAP
+ bool "OMAP ULPI Viewport"
+ help
+ Support ULPI Viewport implementation that is used on OMAP devices.
+
+endchoice
+
+config USB_ULPI
+ bool "ULPI support"
+ depends on (USB_ULPI_VIEWPORT || USB_ULPI_VIEWPORT_OMAP)
+ help
+ Select to commnicate with USB PHY via ULPI interface.
+ ULPI is wrapper on UTMI+ core that is used as
+ PHY Transreceiver for USB controllers.
+
+ This driver uses ULPI viewports that are specific for each SoC.
int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 value)
{
- u32 val = ULPI_RWRUN | ULPI_RWCTRL | ((u32)reg << 16) | (value & 0xff);
+ u32 addr = (uintptr_t)reg & 0xFF;
+ u32 val = ULPI_RWRUN | ULPI_RWCTRL | addr << 16 | (value & 0xff);
val |= (ulpi_vp->port_num & 0x7) << 24;
return ulpi_request(ulpi_vp, val);
u32 ulpi_read(struct ulpi_viewport *ulpi_vp, u8 *reg)
{
int err;
- u32 val = ULPI_RWRUN | ((u32)reg << 16);
+ u32 val = ULPI_RWRUN | ((uintptr_t)reg & 0xFF) << 16;
val |= (ulpi_vp->port_num & 0x7) << 24;
err = ulpi_request(ulpi_vp, val);
ALLOC_CACHE_ALIGN_BUFFER(struct msg_setup, msg_setup, 1);
int ret;
u32 w, h;
+ u32 fb_start, fb_end;
debug("bcm2835: Query resolution...\n");
gd->fb_base = bus_to_phys(
msg_setup->allocate_buffer.body.resp.fb_address);
+
+ /* Enable dcache for the frame buffer */
+ fb_start = gd->fb_base & ~(MMU_SECTION_SIZE - 1);
+ fb_end = gd->fb_base + msg_setup->allocate_buffer.body.resp.fb_size;
+ fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
+ mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
+ DCACHE_WRITEBACK);
+ lcd_set_flush_dcache(1);
}
void lcd_enable(void)
vidinfo_t panel_info = {
.vl_col = 240,
.vl_row = 320,
+ .vl_rot = 3,
.vl_width = 240,
.vl_height = 320,
.vl_clkp = CONFIG_SYS_HIGH,
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
int bp, clk_delay, clk_div, clk_double, pin, total, val;
+#if defined CONFIG_MACH_SUN8I && defined CONFIG_VIDEO_LCD_IF_LVDS
+ for (pin = SUNXI_GPD(18); pin <= SUNXI_GPD(27); pin++) {
+#else
for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++) {
+#endif
#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
#endif
loff_t maxsize, loff_t *actwrite)
{
if (offset != 0) {
- printf("Error: non zero offset is currently not suported.\n");
+ printf("Error: non zero offset is currently not supported.\n");
return -1;
}
#include <config.h>
#include <malloc.h>
#include <div64.h>
+#include <linux/compiler.h>
#include <linux/stat.h>
#include <linux/time.h>
#include <watchdog.h>
struct b_lists *pL)
{
struct jffs2_unknown_node crcnode;
- int ret, ofs;
+ int ret, __maybe_unused ofs;
uint32_t crc;
ofs = part->sector_size - sumsize;
/bmp_logo.h
/bmp_logo_data.h
/config.h
+/license.h
#ifndef _ALTERA_H_
#define _ALTERA_H_
+/*
+ * For the StratixV FPGA programming via SPI, the following
+ * information is coded in the 32bit cookie:
+ * Bit 31 ... Bit 0
+ * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
+ */
+#define FPGA_COOKIE(bus, dev, config, done) \
+ (((bus) << 24) | ((dev) << 16) | ((config) << 8) | (done))
+#define COOKIE2SPI_BUS(c) (((c) >> 24) & 0xff)
+#define COOKIE2SPI_DEV(c) (((c) >> 16) & 0xff)
+#define COOKIE2CONFIG(c) (((c) >> 8) & 0xff)
+#define COOKIE2DONE(c) ((c) & 0xff)
+
enum altera_iface {
/* insert all new types after this */
min_altera_iface_type,
Altera_CYC2,
/* StratixII Family */
Altera_StratixII,
+ /* StratixV Family */
+ Altera_StratixV,
/* SoCFPGA Family */
Altera_SoCFPGA,
Altera_done_fn done;
Altera_clk_fn clk;
Altera_data_fn data;
+ Altera_write_fn write;
Altera_abort_fn abort;
Altera_post_fn post;
} altera_board_specific_func;
int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
#endif
+#ifdef CONFIG_FPGA_STRATIX_V
+int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
+#endif
+
#endif /* _ALTERA_H_ */
#define AXP221_ALDO1_CTRL 0x28
#define AXP221_ALDO2_CTRL 0x29
#define AXP221_ALDO3_CTRL 0x2a
-#define AXP221_VBUS_IPSOUT 0x30
-#define AXP221_VBUS_IPSOUT_DRIVEBUS (1 << 2)
#define AXP221_SHUTDOWN 0x32
#define AXP221_SHUTDOWN_POWEROFF (1 << 7)
-#define AXP221_MISC_CTRL 0x8f
-#define AXP221_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
#define AXP221_PAGE 0xff
/* Page 1 addresses */
/* For axp_gpio.c */
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5)
+#define AXP_VBUS_IPSOUT 0x30
+#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
+#define AXP_MISC_CTRL 0x8f
+#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
#define AXP_GPIO0_CTRL 0x90
#define AXP_GPIO1_CTRL 0x92
#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
#define AXP818_ELDO3_CTRL 0x1b
#define AXP818_FLDO1_CTRL 0x1c
#define AXP818_FLDO2_3_CTRL 0x1d
+#define AXP818_FLDO2_3_CTRL_FLDO3_VOL (1 << 4)
#define AXP818_DCDC1_CTRL 0x20
#define AXP818_DCDC2_CTRL 0x21
#define AXP818_DCDC3_CTRL 0x22
#define AXP818_ALDO2_CTRL 0x29
#define AXP818_ALDO3_CTRL 0x2a
-int axp818_init(void);
-
/* For axp_gpio.c */
#define AXP_POWER_STATUS 0x00
-#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5)
+#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5)
+#define AXP_VBUS_IPSOUT 0x30
+#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
+#define AXP_MISC_CTRL 0x8f
+#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
#define AXP_GPIO0_CTRL 0x90
#define AXP_GPIO1_CTRL 0x92
#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
int axp_set_aldo4(unsigned int mvolt);
int axp_set_dldo(int dldo_num, unsigned int mvolt);
int axp_set_eldo(int eldo_num, unsigned int mvolt);
+int axp_set_fldo(int fldo_num, unsigned int mvolt);
int axp_init(void);
int axp_get_sid(unsigned int *sid);
#define PAD_TO_BLOCKSIZE(size, blk_desc) \
(PAD_SIZE(size, blk_desc->blksz))
+#ifdef CONFIG_BLOCK_CACHE
+/**
+ * blkcache_read() - attempt to read a set of blocks from cache
+ *
+ * @param iftype - IF_TYPE_x for type of device
+ * @param dev - device index of particular type
+ * @param start - starting block number
+ * @param blkcnt - number of blocks to read
+ * @param blksz - size in bytes of each block
+ * @param buf - buffer to contain cached data
+ *
+ * @return - '1' if block returned from cache, '0' otherwise.
+ */
+int blkcache_read(int iftype, int dev,
+ lbaint_t start, lbaint_t blkcnt,
+ unsigned long blksz, void *buffer);
+
+/**
+ * blkcache_fill() - make data read from a block device available
+ * to the block cache
+ *
+ * @param iftype - IF_TYPE_x for type of device
+ * @param dev - device index of particular type
+ * @param start - starting block number
+ * @param blkcnt - number of blocks available
+ * @param blksz - size in bytes of each block
+ * @param buf - buffer containing data to cache
+ *
+ */
+void blkcache_fill(int iftype, int dev,
+ lbaint_t start, lbaint_t blkcnt,
+ unsigned long blksz, void const *buffer);
+
+/**
+ * blkcache_invalidate() - discard the cache for a set of blocks
+ * because of a write or device (re)initialization.
+ *
+ * @param iftype - IF_TYPE_x for type of device
+ * @param dev - device index of particular type
+ */
+void blkcache_invalidate(int iftype, int dev);
+
+/**
+ * blkcache_configure() - configure block cache
+ *
+ * @param blocks - maximum blocks per entry
+ * @param entries - maximum entries in cache
+ */
+void blkcache_configure(unsigned blocks, unsigned entries);
+
+/*
+ * statistics of the block cache
+ */
+struct block_cache_stats {
+ unsigned hits;
+ unsigned misses;
+ unsigned entries; /* current entry count */
+ unsigned max_blocks_per_entry;
+ unsigned max_entries;
+};
+
+/**
+ * get_blkcache_stats() - return statistics and reset
+ *
+ * @param stats - statistics are copied here
+ */
+void blkcache_stats(struct block_cache_stats *stats);
+
+#else
+
+static inline int blkcache_read(int iftype, int dev,
+ lbaint_t start, lbaint_t blkcnt,
+ unsigned long blksz, void *buffer)
+{
+ return 0;
+}
+
+static inline void blkcache_fill(int iftype, int dev,
+ lbaint_t start, lbaint_t blkcnt,
+ unsigned long blksz, void const *buffer) {}
+
+static inline void blkcache_invalidate(int iftype, int dev) {}
+
+#endif
+
#ifdef CONFIG_BLK
struct udevice;
static inline ulong blk_dread(struct blk_desc *block_dev, lbaint_t start,
lbaint_t blkcnt, void *buffer)
{
+ ulong blks_read;
+ if (blkcache_read(block_dev->if_type, block_dev->devnum,
+ start, blkcnt, block_dev->blksz, buffer))
+ return blkcnt;
+
/*
* We could check if block_read is NULL and return -ENOSYS. But this
* bloats the code slightly (cause some board to fail to build), and
* it would be an error to try an operation that does not exist.
*/
- return block_dev->block_read(block_dev, start, blkcnt, buffer);
+ blks_read = block_dev->block_read(block_dev, start, blkcnt, buffer);
+ if (blks_read == blkcnt)
+ blkcache_fill(block_dev->if_type, block_dev->devnum,
+ start, blkcnt, block_dev->blksz, buffer);
+
+ return blks_read;
}
static inline ulong blk_dwrite(struct blk_desc *block_dev, lbaint_t start,
lbaint_t blkcnt, const void *buffer)
{
+ blkcache_invalidate(block_dev->if_type, block_dev->devnum);
return block_dev->block_write(block_dev, start, blkcnt, buffer);
}
static inline ulong blk_derase(struct blk_desc *block_dev, lbaint_t start,
lbaint_t blkcnt)
{
+ blkcache_invalidate(block_dev->if_type, block_dev->devnum);
return block_dev->block_erase(block_dev, start, blkcnt);
}
#endif /* !CONFIG_BLK */
int *repeatable, unsigned long *ticks);
void fixup_cmdtable(cmd_tbl_t *cmdtp, int size);
+
+/**
+ * board_run_command() - Fallback function to execute a command
+ *
+ * When no command line features are enabled in U-Boot, this function is
+ * called to execute a command. Typically the function can look at the
+ * command and perform a few very specific tasks, such as booting the
+ * system in a particular way.
+ *
+ * This function is only used when CONFIG_CMDLINE is not enabled.
+ *
+ * In normal situations this function should not return, since U-Boot will
+ * simply hang.
+ *
+ * @cmdline: Command line string to execute
+ * @return 0 if OK, 1 for error
+ */
+int board_run_command(const char *cmdline);
#endif /* __ASSEMBLY__ */
/*
# define _CMD_HELP(x)
#endif
+#ifdef CONFIG_CMDLINE
#define U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \
_usage, _help, _comp) \
{ #_name, _maxargs, _rep, _cmd, _usage, \
_CMD_HELP(_help) _CMD_COMPLETE(_comp) }
-#define U_BOOT_CMD_MKENT(_name, _maxargs, _rep, _cmd, _usage, _help) \
- U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \
- _usage, _help, NULL)
-
#define U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, _comp) \
ll_entry_declare(cmd_tbl_t, _name, cmd) = \
U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \
_usage, _help, _comp);
+#else
+#define U_BOOT_SUBCMD_START(name) static cmd_tbl_t name[] = {};
+#define U_BOOT_SUBCMD_END
+
+#define _CMD_REMOVE(_name, _cmd) \
+ int __remove_ ## _name(void) \
+ { \
+ if (0) \
+ _cmd(NULL, 0, 0, NULL); \
+ return 0; \
+ }
+#define U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, \
+ _help, _comp) \
+ { #_name, _maxargs, _rep, 0 ? _cmd : NULL, _usage, \
+ _CMD_HELP(_help) _CMD_COMPLETE(_comp) }
+
+#define U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, \
+ _comp) \
+ _CMD_REMOVE(sub_ ## _name, _cmd)
+
+#endif /* CONFIG_CMDLINE */
+
#define U_BOOT_CMD(_name, _maxargs, _rep, _cmd, _usage, _help) \
U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, NULL)
+#define U_BOOT_CMD_MKENT(_name, _maxargs, _rep, _cmd, _usage, _help) \
+ U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \
+ _usage, _help, NULL)
+
#endif /* __COMMAND_H */
# endif
#endif
+#ifndef CONFIG_CMDLINE
+#undef CONFIG_CMDLINE_EDITING
+#undef CONFIG_SYS_LONGHELP
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_RUN
+#undef CONFIG_SYS_HUSH_PARSER
+#undef CONFIG_CMD_ASKENV
+#undef CONFIG_MENU
+#endif
+
#endif /* __CONFIG_FALLBACKS_H */
* "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
*/
+#ifdef CONFIG_BOOTARGS
+#define CONFIG_SET_BOOTARGS "setenv bootargs \'" CONFIG_BOOTARGS" \';"
+#else
+#define CONFIG_SET_BOOTARGS "setenv bootargs \'root=/dev/ram " \
+ "rw console=ttyS0,115200 ramdisk_size=600000\';"
+#endif
+
+
#ifdef CONFIG_BOOTSCRIPT_KEY_HASH
#define CONFIG_SECBOOT \
"setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \
- "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \
- "ramdisk_size=600000\';" \
+ CONFIG_SET_BOOTARGS \
CONFIG_EXTRA_ENV \
"esbc_validate $bs_hdraddr " \
__stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \
#else
#define CONFIG_SECBOOT \
"setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \
- "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \
- "ramdisk_size=600000\';" \
+ CONFIG_SET_BOOTARGS \
CONFIG_EXTRA_ENV \
"esbc_validate $bs_hdraddr;" \
"source $img_addr;" \
"esbc_halt\0"
#endif
-/* For secure boot flow, default environment used will be used */
-#if defined(CONFIG_SYS_RAMBOOT)
#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
#define CONFIG_BS_COPY_ENV \
"setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \
"setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \
"setenv bs_size " __stringify(CONFIG_BS_SIZE)";"
+/* For secure boot flow, default environment used will be used */
+#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_RAMBOOT_NAND)
#define CONFIG_BS_COPY_CMD \
"nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \
"nand read $bs_ram $bs_flash $bs_size ;"
#endif /* CONFIG_RAMBOOT_NAND */
-#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */
-
+#else
+#define CONFIG_BS_COPY_CMD \
+ "cp.b $bs_hdr_flash $bs_hdr_ram $bs_hdr_size ;" \
+ "cp.b $bs_flash $bs_ram $bs_size ;"
#endif
+#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */
#ifndef CONFIG_BS_COPY_ENV
#define CONFIG_BS_COPY_ENV
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-#define CONFIG_SYS_INIT_RAM_END 0x00004000/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
-#define CONFIG_SYS_INIT_RAM_END 0x00004000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
-#undef CONFIG_RTL8139
#ifndef CONFIG_PCI_PNP
#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
-#define CONFIG_RTL8139
#ifndef CONFIG_PCI_PNP
#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
-#undef CONFIG_RTL8139
#ifndef CONFIG_PCI_PNP
#define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_RTL8139
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* Enable VSC9953 L2 Switch driver */
#define CONFIG_VSC9953
-#define CONFIG_VSC9953_CMD
+#define CONFIG_CMD_ETHSW
#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* Use SRAM for initial stack */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_USB_MUSB_GADGET
#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_USB_DWC3
#define CONFIG_USB_DWC3_GADGET
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
#define CONFIG_USB_MUSB_GADGET
#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_USB_GADGET
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_USB_MUSB_GADGET
#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_FASTBOOT_BUF_SIZE (CONFIG_SYS_SDRAM_SIZE - SZ_1M)
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_SDRAM_BASE
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 0
#define CONFIG_USB_GADGET_DWC2_OTG
#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
-/* PCI networking support */
-#define CONFIG_RTL8169
-
/* General networking support */
#define CONFIG_CMD_DHCP
#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
-/* PCI networking support */
-#define CONFIG_RTL8169
-
/* General networking support */
#define CONFIG_CMD_DHCP
#define CONFIG_USBD_HS
#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_GADGET_DOWNLOAD
#include <configs/x86-common.h>
#include <configs/x86-chromebook.h>
-#define CONFIG_RTL8169
-
#endif /* __CONFIG_H */
/* USB host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
/* USB Client Support */
-#define CONFIG_USB_GADGET
#define CONFIG_CI_UDC
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_ATMEL_USBA
--- /dev/null
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_DB_88F6720_H
+#define _CONFIG_DB_88F6720_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x00800000
+#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TFTPPUT
+#define CONFIG_CMD_TIME
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED 1000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
+
+#define CONFIG_PHY_MARVELL /* there is a marvell phy */
+#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* Additional FS support/configuration */
+#define CONFIG_SUPPORT_VFAT
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Memory layout while starting into the bin_hdr via the
+ * BootROM:
+ *
+ * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
+ * 0x4000.4030 bin_hdr start address
+ * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
+ * 0x4007.fffc BootROM stack top
+ *
+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
+ * L2 cache thus cannot be used.
+ */
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x40004030
+#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
+
+#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
+#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
+
+#endif /* _CONFIG_DB_88F6720_H */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_MII /* Required in net/eth.c */
#define CONFIG_PHY_GIGE /* per-board part of CPSW */
#define CONFIG_PHYLIB
+#define CONFIG_PHY_TI
/* SPI */
#undef CONFIG_OMAP3_SPI
#define CONFIG_USB_DWC3
#define CONFIG_USB_DWC3_GADGET
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
--- /dev/null
+/*
+ * Board configuration file for Dragonboard 410C
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIGS_DRAGONBOARD410C_H
+#define __CONFIGS_DRAGONBOARD410C_H
+
+#include <linux/sizes.h>
+#include <asm/arch/sysmap-apq8016.h>
+
+#define CONFIG_IDENT_STRING "\nQualcomm-DragonBoard 410C"
+
+#define CONFIG_MISC_INIT_R /* To stop autoboot */
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x80000000
+/* 1008 MB (the last ~30Mb are secured for TrustZone by ATF*/
+#define PHYS_SDRAM_1_SIZE 0x3da00000
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_TEXT_BASE 0x80080000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
+#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16MB max kernel size */
+
+/* UART */
+#define CONFIG_BAUDRATE 115200
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY 19000000
+
+/* This are needed to have proper mmc support */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SDHCI
+
+#define CONFIG_SYS_LDSCRIPT "board/qualcomm/dragonboard410c/u-boot.lds"
+
+/* Fixup - in init code we switch from device to host mode,
+ * it has to be done after each HCD reset */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#define CONFIG_USB_HOST_ETHER /* Enable USB Networking */
+
+/* Support all possible USB ethernet dongles */
+#define CONFIG_USB_ETHER_DM9601
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_ASIX88179
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
+
+/* Libraries */
+#define CONFIG_MD5
+
+/* Extra Commands */
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_GPT
+#define CONFIG_CMD_MD5SUM
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MMC
+/* Enable that for switching of boot partitions */
+/* Disabled by default as some sub-commands can brick eMMC */
+/*#define CONFIG_SUPPORT_EMMC_BOOT */
+#define CONFIG_CMD_PART
+#define CONFIG_CMD_REGINFO /* Register dump */
+#define CONFIG_CMD_TFTP
+#define CONFIG_CMD_TIMER
+#define CONFIG_CMD_UNZIP
+
+/* Partition table support */
+#define HAVE_BLOCK_DEVICE /* Needed for partition commands */
+#define CONFIG_PARTITION_UUIDS
+
+#include <config_distro_defaults.h>
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* Environment - Boot*/
+#define CONFIG_BOOTARGS "console=ttyMSM0,115200n8"
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(USB, usb, 0) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 1) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+/* Does what recovery does */
+#define REFLASH(file, part) \
+"part start mmc 0 "#part" start && "\
+"part size mmc 0 "#part" size && "\
+"tftp $loadaddr "#file" && " \
+"mmc write $loadaddr $start $size && "
+
+
+#define CONFIG_ENV_REFLASH \
+"mmc dev 0 && "\
+"usb start && "\
+"dhcp && "\
+"tftp $loadaddr dragonboard/rescue/gpt_both0.bin && "\
+"mmc write $loadaddr 0 43 && " \
+"mmc rescan && "\
+REFLASH(dragonboard/rescue/NON-HLOS.bin, 1)\
+REFLASH(dragonboard/rescue/sbl1.mbn, 2)\
+REFLASH(dragonboard/rescue/rpm.mbn, 3)\
+REFLASH(dragonboard/rescue/tz.mbn, 4)\
+REFLASH(dragonboard/rescue/hyp.mbn, 5)\
+REFLASH(dragonboard/rescue/sec.dat, 6)\
+REFLASH(dragonboard/rescue/emmc_appsboot.mbn, 7)\
+REFLASH(dragonboard/u-boot.img, 8)\
+"usb stop &&"\
+"echo Reflash completed"
+
+/* Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "reflash="CONFIG_ENV_REFLASH"\0"\
+ "loadaddr=0x81000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "linux_image=Image\0" \
+ "linux_addr=0x81000000\0"\
+ "fdt_image=apq8016-sbc.dtb\0" \
+ "fdt_addr=0x83000000\0"\
+ "ramdisk_addr=0x84000000\0"\
+ BOOTENV
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_SYS_NO_FLASH
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M)
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_MAXARGS 64 /* max command args */
+
+#endif
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DWC2_OTG
#define CONFIG_USB_GADGET_DWC2_OTG_PHY
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
/* USB Mass Storage Gadget */
-#define CONFIG_USB_GADGET
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_GADGET_DOWNLOAD
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
-/* PCI networking support */
-#define CONFIG_RTL8169
-
/* General networking support */
#define CONFIG_CMD_DHCP
#define CONFIG_KSNET_CPSW_NUM_PORTS 2
#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
#define CONFIG_PHY_MICREL
+#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */
/* MMC/SD */
#define CONFIG_MMC
#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_OMAP2PLUS
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 0
"boot_mmc_dev=0\0" \
"kernel_mmc_part=7\0" \
"recovery_mmc_part=5\0" \
- "bootargs=mem=512M console=ttyO2\0"
+ "fdtfile=omap4-kc1.dtb\0" \
+ "bootfile=/boot/extlinux/extlinux.conf\0" \
+ "bootargs=console=ttyO2,115200 mem=512M\0"
/*
* ATAGs
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_FSL_DIU_CH7301
#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_FSL_DCU_SII9022A
#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#ifdef CONFIG_NAND_BOOT
+/* Store Fman ucode at offeset 0x160000(11 blocks). */
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SD_BOOT)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2040 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
+#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
#define CONFIG_ENV_SPI_BUS 0
"ramdisk_size=0x2000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
- "kernel_start=0x61200000\0" \
- "kernel_load=0x807f0000\0" \
- "kernel_size=0x1000000\0" \
+ "kernel_start=0x61100000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
"console=ttyAMA0,38400n8\0"
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
- "earlycon=uart8250,0x21c0500,115200"
+ "earlycon=uart8250,mmio,0x21c0500"
#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
"$kernel_size && bootm $kernel_load"
#define CONFIG_BOOTDELAY 10
#define CONFIG_DOS_PARTITION
#define CONFIG_BOARD_LATE_INIT
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3 0
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
-#ifdef CONFIG_LS2085A
+/* For LS2085A */
#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
-#endif
/*
* Carve out a DDR region which will not be used by u-boot/Linux
#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
#endif
-#ifdef CONFIG_LS2085A
-#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
-#endif
-
#define CONFIG_SYS_PCI_64BIT
#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
" 0x580800000 \0"
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
- "earlycon=uart8250,mmio,0x21c0500" \
+ "earlycon=uart8250,mmio,0x21c0500 " \
"ramdisk_size=0x2000000 default_hugepagesz=2m" \
" hugepagesz=2m hugepages=256"
#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \
#include "ls2080a_common.h"
-#ifdef CONFIG_LS2080A
#define CONFIG_IDENT_STRING " LS2080A-EMU"
#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-EMU"
-#endif
-
-#ifdef CONFIG_LS2085A
-#define CONFIG_IDENT_STRING " LS2085A-EMU"
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2085A-EMU"
-#endif
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 133333333
#include "ls2080a_common.h"
-#ifdef CONFIG_LS2080A
#define CONFIG_IDENT_STRING " LS2080A-SIMU"
#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-SIMU"
-#endif
-
-#ifdef CONFIG_LS2085A
-#define CONFIG_IDENT_STRING " LS2085A-SIMU"
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2085A-SIMU"
-#endif
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 133333333
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_EXT2
+#include <asm/fsl_secure_boot.h>
+
#endif /* __LS2_QDS_H */
#define CONFIG_DISPLAY_BOARDINFO
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+#define I2C_VOL_MONITOR_ADDR 0x38
+#define CONFIG_VOL_MONITOR_IR36021_READ
+#define CONFIG_VOL_MONITOR_IR36021_SET
+
+#define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_VID
+#endif
+/* step the IR regulator in 5mV increments */
+#define IR_VDD_STEP_DOWN 5
+#define IR_VDD_STEP_UP 5
+/* The lowest and highest voltage allowed for LS2080ARDB */
+#define VDD_MV_MIN 819
+#define VDD_MV_MAX 1212
+
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
#endif
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
- "earlycon=uart8250,mmio,0x21c0600" \
+ "earlycon=uart8250,mmio,0x21c0600 " \
"ramdisk_size=0x2000000 default_hugepagesz=2m" \
" hugepagesz=2m hugepages=256"
#define AQ_PHY_ADDR2 0x01
#define AQ_PHY_ADDR3 0x02
#define AQ_PHY_ADDR4 0x03
+#define AQR405_IRQ_MASK 0x36
#define CONFIG_MII
#define CONFIG_ETHPRIME "DPNI1"
#define CONFIG_PHY_AQUANTIA
#endif
+#include <asm/fsl_secure_boot.h>
+
#endif /* __LS2_RDB_H */
#define CONFIG_USB_STORAGE
/* USB device */
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_ATMEL_USBA
#define CONFIG_USB_ETHER
#define CONFIG_OMAP3_GPIO_5
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_OMAP
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_HOST_ETHER
#endif
#define CONFIG_BOARD_LATE_INIT
-/* interrupt controller */
-#ifdef XILINX_INTC_BASEADDR
-# define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
-# define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
-#endif
-
-/* timer */
-#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
-# define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
-# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
-#endif
-
/* watchdog */
#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
#define CONFIG_SMSC_LPC47M
#define CONFIG_PCI_PNP
-#define CONFIG_RTL8169
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
"stdout=vga,serial\0" \
"stderr=vga,serial\0"
#define CONFIG_USBD_HS
#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USBD_HS
#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_GADGET_DOWNLOAD
#endif
-#define CONFIG_USB_GADGET
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
#else
/* End of used area in DPRAM */
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
#endif
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_USB_DWC3_PHY_SAMSUNG
/* USB gadget */
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_TWL4030_USB 1
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETHER_RNDIS
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_VBUS_DRAW 0
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_G_DNL_VENDOR_NUM 0x0451
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETHER_RNDIS
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_VBUS_DRAW 0
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_G_DNL_VENDOR_NUM 0x0451
#define CONFIG_USB_DWC3
#define CONFIG_USB_DWC3_GADGET
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
-/* PCI networking support */
-#define CONFIG_RTL8169
-
/* General networking support */
#define CONFIG_CMD_DHCP
#define CONFIG_USB_MUSB_GADGET
#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_USB_MUSB_HOST
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_MMC
+/*--------------------------------------------------
+ * USB Configuration
+ */
+#define CONFIG_USB_MUSB_PIO_ONLY
+#define CONFIG_SYS_CACHELINE_SIZE 16
+
/*-----------------------------------------------------------------------
* File System Configuration
*/
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#define __CONFIG_PXA_COMMON_H__
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
/*
* KGDB
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_BOARD_INIT
+#ifdef CONFIG_CPU_PXA27X
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
+#else
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#endif
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4c000000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "pxa-ohci"
#define CONFIG_USB_STORAGE
#define CONFIG_PCI_SYS_PHYS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
-/*
- * Network device (RTL8139) support
- */
-#define CONFIG_RTL8139
-
#endif /* __CONFIG_H */
#endif /* CONFIG_CMD_PCI */
#if defined(CONFIG_CMD_NET)
-/*
-#define CONFIG_RTL8169
-*/
/* AX88796L Support(NE2000 base chip) */
#define CONFIG_DRIVER_AX88796L
#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
+++ /dev/null
-/*
- * (C) Copyright 2012,2015 Stephen Warren
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#ifndef _RPI_COMMON_H_
-#define _RPI_COMMON_H_
-
-#include <linux/sizes.h>
-#include <asm/arch/timer.h>
-
-/* Architecture, CPU, etc.*/
-#define CONFIG_BCM2835
-#define CONFIG_ARCH_CPU_INIT
-
-#define CONFIG_SYS_TIMER_RATE 1000000
-#define CONFIG_SYS_TIMER_COUNTER \
- (&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo)
-
-/*
- * 2835 is a SKU in a series for which the 2708 is the first or primary SoC,
- * so 2708 has historically been used rather than a dedicated 2835 ID.
- *
- * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation
- * chose to use someone else's previously registered machine ID (3139, MX51_GGC)
- * rather than obtaining a valid ID:-/
- */
-#ifndef CONFIG_BCM2836
-#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708
-#endif
-
-/* Memory layout */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_TEXT_BASE 0x00008000
-#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
-/*
- * The board really has 256M. However, the VC (VideoCore co-processor) shares
- * the RAM, and uses a configurable portion at the top. We tell U-Boot that a
- * smaller amount of RAM is present in order to avoid stomping on the area
- * the VC uses.
- */
-#define CONFIG_SYS_SDRAM_SIZE SZ_128M
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_SDRAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MALLOC_LEN SZ_4M
-#define CONFIG_SYS_MEMTEST_START 0x00100000
-#define CONFIG_SYS_MEMTEST_END 0x00200000
-#define CONFIG_LOADADDR 0x00200000
-
-/* Flash */
-#define CONFIG_SYS_NO_FLASH
-
-/* Devices */
-/* GPIO */
-#define CONFIG_BCM2835_GPIO
-/* LCD */
-#define CONFIG_LCD
-#define CONFIG_LCD_DT_SIMPLEFB
-#define LCD_BPP LCD_COLOR16
-/*
- * Prevent allocation of RAM for FB; the real FB address is queried
- * dynamically from the VideoCore co-processor, and comes from RAM
- * not owned by the ARM CPU.
- */
-#define CONFIG_FB_ADDR 0
-#define CONFIG_VIDEO_BCM2835
-#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES 10
-
-/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_MMC_SDHCI_IO_ACCESSORS
-#define CONFIG_BCM2835_SDHCI
-
-#define CONFIG_CMD_USB
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2
-#ifdef CONFIG_BCM2836
-#define CONFIG_USB_DWC2_REG_ADDR 0x3f980000
-#else
-#define CONFIG_USB_DWC2_REG_ADDR 0x20980000
-#endif
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_SMSC95XX
-#define CONFIG_MISC_INIT_R
-#define CONFIG_USB_KEYBOARD
-#define CONFIG_SYS_USB_EVENT_POLL
-#define CONFIG_SYS_STDIO_DEREGISTER
-#endif
-
-/* Console UART */
-#define CONFIG_PL01X_SERIAL
-#define CONFIG_CONS_INDEX 0
-#define CONFIG_BAUDRATE 115200
-
-/* Console configuration */
-#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/* Environment */
-#define CONFIG_ENV_SIZE SZ_16K
-#define CONFIG_ENV_IS_IN_FAT
-#define FAT_ENV_INTERFACE "mmc"
-#define FAT_ENV_DEVICE_AND_PART "0:1"
-#define FAT_ENV_FILE "uboot.env"
-#define CONFIG_FAT_WRITE
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_SYS_LOAD_ADDR 0x1000000
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_PREBOOT "usb start"
-
-/* Shell */
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_COMMAND_HISTORY
-
-/* Commands */
-#define CONFIG_CMD_MMC
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
-
-/* ATAGs support for bootm/bootz */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-
-#include <config_distro_defaults.h>
-
-/* Environment */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-#define ENV_DEVICE_SETTINGS \
- "stdin=serial,usbkbd\0" \
- "stdout=serial,lcd\0" \
- "stderr=serial,lcd\0"
-
-/*
- * Memory layout for where various images get loaded by boot scripts:
- *
- * I suspect address 0 is used as the SMP pen on the RPi2, so avoid this.
- *
- * fdt_addr_r simply shouldn't overlap anything else. However, the RPi's
- * binary firmware loads a DT to address 0x100, so we choose this address to
- * match it. This allows custom boot scripts to pass this DT on to Linux
- * simply by not over-writing the data at this address. When using U-Boot,
- * U-Boot (and scripts it executes) typicaly ignore the DT loaded by the FW
- * and loads its own DT from disk (triggered by boot.scr or extlinux.conf).
- *
- * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
- * something else. Put it low in memory to avoid conflicts.
- *
- * kernel_addr_r must be within the first 128M of RAM in order for the
- * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
- * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
- * should not overlap that area, or the kernel will have to copy itself
- * somewhere else before decompression. Similarly, the address of any other
- * data passed to the kernel shouldn't overlap the start of RAM. Pushing
- * this up to 16M allows for a sizable kernel to be decompressed below the
- * compressed load address.
- *
- * scriptaddr can be pretty much anywhere that doesn't conflict with something
- * else. Choosing 32M allows for the compressed kernel to be up to 16M.
- *
- * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
- * for any boot script to be up to 1M, which is hopefully plenty.
- */
-#define ENV_MEM_LAYOUT_SETTINGS \
- "fdt_high=ffffffff\0" \
- "initrd_high=ffffffff\0" \
- "fdt_addr_r=0x00000100\0" \
- "pxefile_addr_r=0x00100000\0" \
- "kernel_addr_r=0x01000000\0" \
- "scriptaddr=0x02000000\0" \
- "ramdisk_addr_r=0x02100000\0" \
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(USB, usb, 0) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
-#include <config_distro_bootcmd.h>
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- ENV_DEVICE_SETTINGS \
- ENV_MEM_LAYOUT_SETTINGS \
- BOOTENV
-
-#define CONFIG_BOOTDELAY 2
-
-#endif
/*
- * (C) Copyright 2012,2015 Stephen Warren
+ * (C) Copyright 2012-2016 Stephen Warren
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <linux/sizes.h>
+#include <asm/arch/timer.h>
+
+#if defined(CONFIG_TARGET_RPI_2) || defined(CONFIG_TARGET_RPI_3_32B)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#ifdef CONFIG_BCM2835
#define CONFIG_SYS_CACHELINE_SIZE 32
+#else
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#endif
+
+/* Architecture, CPU, etc.*/
+#define CONFIG_ARCH_CPU_INIT
+
+/* Use SoC timer for AArch32, but architected timer for AArch64 */
+#ifndef CONFIG_ARM64
+#define CONFIG_SYS_TIMER_RATE 1000000
+#define CONFIG_SYS_TIMER_COUNTER \
+ (&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo)
+#endif
+
+/*
+ * 2835 is a SKU in a series for which the 2708 is the first or primary SoC,
+ * so 2708 has historically been used rather than a dedicated 2835 ID.
+ *
+ * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation
+ * chose to use someone else's previously registered machine ID (3139, MX51_GGC)
+ * rather than obtaining a valid ID:-/
+ *
+ * For the bcm2837, hopefully a machine type is not needed, since everything
+ * is DT.
+ */
+#ifdef CONFIG_BCM2835
+#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708
+#endif
+
+/* Memory layout */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_TEXT_BASE 0x00008000
+#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
+/*
+ * The board really has 256M. However, the VC (VideoCore co-processor) shares
+ * the RAM, and uses a configurable portion at the top. We tell U-Boot that a
+ * smaller amount of RAM is present in order to avoid stomping on the area
+ * the VC uses.
+ */
+#define CONFIG_SYS_SDRAM_SIZE SZ_128M
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_SDRAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_MALLOC_LEN SZ_4M
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x00200000
+#define CONFIG_LOADADDR 0x00200000
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* Devices */
+/* GPIO */
+#define CONFIG_BCM2835_GPIO
+/* LCD */
+#define CONFIG_LCD
+#define CONFIG_LCD_DT_SIMPLEFB
+#define LCD_BPP LCD_COLOR16
+/*
+ * Prevent allocation of RAM for FB; the real FB address is queried
+ * dynamically from the VideoCore co-processor, and comes from RAM
+ * not owned by the ARM CPU.
+ */
+#define CONFIG_FB_ADDR 0
+#define CONFIG_VIDEO_BCM2835
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES 10
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_MMC_SDHCI_IO_ACCESSORS
+#define CONFIG_BCM2835_SDHCI
+
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2
+#ifndef CONFIG_BCM2835
+#define CONFIG_USB_DWC2_REG_ADDR 0x3f980000
+#else
+#define CONFIG_USB_DWC2_REG_ADDR 0x20980000
+#endif
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MISC_INIT_R
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_SYS_STDIO_DEREGISTER
+#endif
+
+/* Console UART */
+#ifdef CONFIG_BCM2837
+#define CONFIG_BCM283X_MU_SERIAL
+#else
+#define CONFIG_PL01X_SERIAL
+#endif
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200
+
+/* Console configuration */
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Environment */
+#define CONFIG_ENV_SIZE SZ_16K
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE "mmc"
+#define FAT_ENV_DEVICE_AND_PART "0:1"
+#define FAT_ENV_FILE "uboot.env"
+#define CONFIG_FAT_WRITE
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_SYS_LOAD_ADDR 0x1000000
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_PREBOOT "usb start"
+
+/* Shell */
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_COMMAND_HISTORY
+
+/* Commands */
+#define CONFIG_CMD_MMC
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
+/* ATAGs support for bootm/bootz */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+
+#include <config_distro_defaults.h>
+
+/* Environment */
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define ENV_DEVICE_SETTINGS \
+ "stdin=serial,usbkbd\0" \
+ "stdout=serial,lcd\0" \
+ "stderr=serial,lcd\0"
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * I suspect address 0 is used as the SMP pen on the RPi2, so avoid this.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. However, the RPi's
+ * binary firmware loads a DT to address 0x100, so we choose this address to
+ * match it. This allows custom boot scripts to pass this DT on to Linux
+ * simply by not over-writing the data at this address. When using U-Boot,
+ * U-Boot (and scripts it executes) typicaly ignore the DT loaded by the FW
+ * and loads its own DT from disk (triggered by boot.scr or extlinux.conf).
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ * something else. Put it low in memory to avoid conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ * should not overlap that area, or the kernel will have to copy itself
+ * somewhere else before decompression. Similarly, the address of any other
+ * data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ * this up to 16M allows for a sizable kernel to be decompressed below the
+ * compressed load address.
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ * else. Choosing 32M allows for the compressed kernel to be up to 16M.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * for any boot script to be up to 1M, which is hopefully plenty.
+ */
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "fdt_high=ffffffff\0" \
+ "initrd_high=ffffffff\0" \
+ "fdt_addr_r=0x00000100\0" \
+ "pxefile_addr_r=0x00100000\0" \
+ "kernel_addr_r=0x01000000\0" \
+ "scriptaddr=0x02000000\0" \
+ "ramdisk_addr_r=0x02100000\0" \
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "dhcpuboot=usb start; dhcp u-boot.uimg; bootm\0" \
+ ENV_DEVICE_SETTINGS \
+ ENV_MEM_LAYOUT_SETTINGS \
+ BOOTENV
-#include "rpi-common.h"
+#define CONFIG_BOOTDELAY 2
#endif
+++ /dev/null
-/*
- * (C) Copyright 2012,2015 Stephen Warren
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BCM2836
-#define CONFIG_SYS_CACHELINE_SIZE 64
-#define CONFIG_SYS_DCACHE_OFF
-
-#include "rpi-common.h"
-
-#endif
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_SYS_MAX_I2C_BUS 7
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DWC2_OTG
#define CONFIG_USB_GADGET_DWC2_OTG_PHY
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_POWER_I2C
#define CONFIG_POWER_MAX8998
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DWC2_OTG
#define CONFIG_USB_GADGET_DWC2_OTG_PHY
#define CONFIG_USB_GADGET_DUALSPEED
#endif
/* USB device */
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_ATMEL_USBA
#define CONFIG_USB_ETHER
#endif
/* USB device */
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_ATMEL_USBA
#define CONFIG_USB_ETHER
#endif
/* USB device */
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_ATMEL_USBA
#define CONFIG_USB_ETHER
#endif
/* USB device */
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_ATMEL_USBA
#define CONFIG_USB_ETHER
#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
-/* Network device (RTL8169) support */
-#define CONFIG_RTL8169
-
/* ENV setting */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_MTDPARTS \
"orion_nand:512K(uboot)," \
- "512K(env),1M(script),6M(kernel)," \
- "12M(ramdisk),4M(spare),-(rootfs)\0"
+ "512K(env),4M(kernel)," \
+ "-(rootfs)\0"
#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
- "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
+ "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \
"x_bootcmd_usb=usb start\0" \
"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
#endif /* CONFIG_USB_MUSB_GADGET */
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DOWNLOAD
/* USB DRACO ID as default */
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_AT91
/* DFU class support */
#include "exynos4-common.h"
#undef CONFIG_BOARD_COMMON
-#undef CONFIG_USB_GADGET
#undef CONFIG_USB_GADGET_DWC2_OTG
#undef CONFIG_USB_GADGET_DWC2_OTG_PHY
#undef CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_MUSB_OMAP2PLUS
#define CONFIG_TWL4030_USB
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 0
"recovery_mmc_part=4\0" \
"fdtfile=omap3-sniper.dtb\0" \
"bootfile=/boot/extlinux/extlinux.conf\0" \
- "bootargs=console=ttyO2 vram=5M,0x9FA00000 omapfb.vram=0:5M\0"
+ "bootargs=console=ttyO2,115200 vram=5M,0x9FA00000 omapfb.vram=0:5M\0"
/*
* ATAGs
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
- "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"bootimage=zImage\0" \
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_BAR
/*
* The base address is configurable in QSys, each board must specify the
* base address based on it's particular FPGA configuration. Please note
#endif
#define CONFIG_CQSPI_DECODER 0
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_BAR
/*
* Designware SPI support
* USB Gadget (DFU, UMS)
*/
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DWC2_OTG
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+#if !defined(CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE 4096
+#endif
/* Environment for SDMMC boot */
#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
#endif
+/* Environment for QSPI boot */
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_OFFSET 0x00100000
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#endif
+
/*
* mtd partitioning for serial NOR flash
*
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
- "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"bootimage=zImage\0" \
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"bootimage=zImage\0" \
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
- "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"bootimage=zImage\0" \
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
- "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"bootimage=zImage\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
- "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"bootimage=zImage\0" \
#define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8
#define CONFIG_SYS_BOOTCOUNT_BE
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
-
-/* U-Boot payload is stored at offset 0x60000 */
-#undef CONFIG_SYS_SPI_U_BOOT_OFFS
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x60000
-
/* Environment setting for SPI flash */
-#undef CONFIG_ENV_SIZE
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_SIZE (16 * 1024)
-#define CONFIG_ENV_OFFSET 0x00040000
+#define CONFIG_ENV_OFFSET 0x000e0000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MODE SPI_MODE_3
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */
+#define CONFIG_SF_DEFAULT_SPEED 100000000
+
+/*
+ * The QSPI NOR flash layout on SR1500:
+ *
+ * 0000.0000 - 0003.ffff: SPL (4 times)
+ * 0004.0000 - 000d.ffff: U-Boot
+ * 000e.0000 - 000e.ffff: env1
+ * 000f.0000 - 000f.ffff: env2
+ */
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
#endif /* __CONFIG_SOCFPGA_SR1500_H__ */
#define CONFIG_GREEN_LED 109
#define CONFIG_STM32_GPIO
+#define CONFIG_STM32_FLASH
#define CONFIG_STM32_SERIAL
#define CONFIG_STM32_HSE_HZ 8000000
#define __CONFIG_H
#define CONFIG_SYS_THUMB_BUILD
-#define CONFIG_SYS_NO_FLASH
+/*#define CONFIG_SYS_NO_FLASH*/
#define CONFIG_OF_LIBFDT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_LOAD_ADDR 0x20000000
#define CONFIG_LOADADDR 0x20000000
-#define CONFIG_SYS_MAX_FLASH_SECT 12
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#define CONFIG_SYS_MAX_FLASH_SECT 8
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_IN_FLASH
-#else
#define CONFIG_ENV_IS_NOWHERE
-#endif
#define CONFIG_ENV_SIZE (8 << 10)
#define CONFIG_STM32_GPIO
+#define CONFIG_STM32_FLASH
#define CONFIG_STM32X7_SERIAL
#define CONFIG_SYS_CLK_FREQ 16*1000*1000 /* 180 MHz */
| BR_PS_16 /* 16 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
+
+#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET)
+ | OR_GPCM_SCY_5 \
+ | OR_GPCM_TRLX_CLEAR \
+ | OR_GPCM_EHTR_CLEAR)
#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
#define CONFIG_SYS_FPGA_DONE(k) 0x0010
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_PCA953X /* NXP PCA9554 */
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
+ {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
+
#define CONFIG_PCA9698 /* NXP PCA9698 */
#define CONFIG_SYS_I2C_IHS
--- /dev/null
+/*
+ * Configuration settings for the Allwinner A64 (sun50i) CPU
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A64 specific configuration
+ */
+
+#define CONFIG_SUNXI_USB_PHYS 1
+
+#define COUNTER_FREQUENCY CONFIG_TIMER_CLK_FREQ
+#define GICD_BASE 0x1c81000
+#define GICC_BASE 0x1c82000
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
#define CONFIG_ARMV7_PSCI 1
#define CONFIG_ARMV7_PSCI_NR_CPUS 4
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
-#define CONFIG_TIMER_CLK_FREQ 24000000
/*
* Include common sunxi configuration where most the settings are
#define CONFIG_ARMV7_PSCI 1
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
-#define CONFIG_TIMER_CLK_FREQ 24000000
/*
* Include common sunxi configuration where most the settings are
#ifdef CONFIG_MACH_SUN8I_H3
#define CONFIG_SUNXI_USB_PHYS 4
+#elif defined CONFIG_MACH_SUN8I_A83T
+ #define CONFIG_SUNXI_USB_PHYS 3
#else
#define CONFIG_SUNXI_USB_PHYS 2
#endif
#endif
#endif
-#define CONFIG_TIMER_CLK_FREQ 24000000
-
/*
* Include common sunxi configuration where most the settings are
*/
/* CPU */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_TIMER_CLK_FREQ 24000000
/*
* The DRAM Base differs between some models. We cannot use macros for the
#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */
-#ifdef CONFIG_MACH_SUN9I
+#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
/*
* The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is
* slightly bigger. Note that it is possible to map the first 32 KiB of the
* the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x10000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x0a000 /* 40 KiB */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */
#else
#define CONFIG_SYS_INIT_RAM_ADDR 0x0
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
#define CONFIG_SPL_BOARD_LOAD_IMAGE
+#if defined(CONFIG_MACH_SUN9I)
+#define CONFIG_SPL_TEXT_BASE 0x10020 /* sram start+header */
+#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* ? KiB on sun9i */
+#elif defined(CONFIG_MACH_SUN50I)
+#define CONFIG_SPL_TEXT_BASE 0x10020 /* sram start+header */
+#define CONFIG_SPL_MAX_SIZE 0x7fe0 /* 32 KiB on sun50i */
+#else
#define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */
#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */
+#endif
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#endif
+#ifndef CONFIG_ARM64
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
+#endif
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */
#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
+#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
+/* FIXME: 40 KiB instead of 32 KiB ? */
+#define LOW_LEVEL_SRAM_STACK 0x00018000
+#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+#else
/* end of 32 KiB in sram */
#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+#endif
/* I2C */
#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
#define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */
#define CONFIG_PHY_ADDR 1
#define CONFIG_MII /* MII PHY management */
+#define CONFIG_PHY_REALTEK
#endif
#ifdef CONFIG_USB_EHCI_HCD
#endif
#ifdef CONFIG_USB_MUSB_GADGET
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 0
#define CONFIG_OMAP3_GPIO_5
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_OMAP
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_STORAGE
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_AT91
/* DFU class support */
#ifdef CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_CI_UDC
#define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 0
#ifndef CONFIG_SPL_BUILD
/* USB gadget mode support*/
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_CI_UDC
#define CONFIG_CI_UDC_HAS_HOSTPC
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
+#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
#define CONFIG_SYS_I2C_SLAVE 0x0
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_PCI
#define CONFIG_PCI_MVEBU
#define CONFIG_PCI_PNP
+#define CONFIG_BOARD_LATE_INIT /* for PEX switch test */
#endif
#endif
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_CMD_BMP
+/* FPGA programming support */
+#define CONFIG_FPGA
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_STRATIX_V
+
+/*
+ * Bootcounter
+ */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_RAM
+/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
+#define BOOTCOUNT_ADDR 0x1000
+
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
/* SoC Configuration */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_ARCH_TIMER
+#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x0c000000
+#endif
#define CONFIG_SPL_TARGET "u-boot-spi.gph"
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
-/* PCI networking support */
-#define CONFIG_RTL8169
-
/* General networking support */
#define CONFIG_CMD_DHCP
#define CONFIG_I2C_EEPROM
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-#ifdef CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
-#define CONFIG_SYS_NS16550_CLK 12288000
-#define CONFIG_SYS_NS16550_REG_SIZE -2
-#endif
-
-/* TODO: move to Kconfig and device tree */
-#if 0
-#define CONFIG_SYS_NS16550_SERIAL
-#endif
-
#define CONFIG_SMC911X
/* dummy: referenced by examples/standalone/smc911x_eeprom.c */
#define CONFIG_SYS_CACHELINE_SIZE 32
-/* Comment out the following to enable L2 cache */
+/* Comment out the following to disable L2 cache */
#define CONFIG_UNIPHIER_L2CACHE_ON
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_MONITOR_BASE 0
+#define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */
#define CONFIG_SYS_FLASH_BASE 0
/*
/* Time clock 1MHz */
#define CONFIG_SYS_TIMER_RATE 1000000
-/*
- * By default, ARP timeout is 5 sec.
- * The first ARP request does not seem to work.
- * So we need to retry ARP request anyway.
- * We want to shrink the interval until the second ARP request.
- */
-#define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */
-
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 2
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_DENALI_ECC_SIZE 1024
-#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3
+#ifdef CONFIG_ARCH_UNIPHIER_SLD3
#define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
#define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
#else
"netdev=eth0\0" \
"verify=n\0" \
"nor_base=0x42000000\0" \
+ "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \
+ "tftpboot $tmp_addr u-boot-spl.bin &&" \
+ "setexpr tmp_addr $nor_base + 0x60000 &&" \
+ "tftpboot $tmp_addr u-boot.bin\0" \
"emmcupdate=mmcsetn &&" \
"mmc partconf $mmc_first_dev 0 1 1 &&" \
"mmc erase 0 800 &&" \
"tftpboot u-boot-spl.bin &&" \
"mmc write $loadaddr 0 80 &&" \
- "tftpboot u-boot.img &&" \
+ "tftpboot u-boot.bin &&" \
"mmc write $loadaddr 80 780\0" \
"nandupdate=nand erase 0 0x00100000 &&" \
"tftpboot u-boot-spl.bin &&" \
"nand write $loadaddr 0 0x00010000 &&" \
- "tftpboot u-boot.img &&" \
+ "tftpboot u-boot.bin &&" \
"nand write $loadaddr 0x00010000 0x000f0000\0" \
LINUXBOOT_ENV_SETTINGS
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_NR_DRAM_BANKS 2
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) || \
- defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
- defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+#if defined(CONFIG_ARCH_UNIPHIER_SLD3) || defined(CONFIG_ARCH_UNIPHIER_LD4) || \
+ defined(CONFIG_ARCH_UNIPHIER_SLD8)
#define CONFIG_SPL_TEXT_BASE 0x00040000
#else
#define CONFIG_SPL_TEXT_BASE 0x00100000
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NOR_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
+
+/* subtract sizeof(struct image_header) */
+#define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
+#define CONFIG_SPL_MAX_SIZE 0x10000
#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
#endif
/* USB device */
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_ATMEL_USBA
#define CONFIG_USB_ETHER
#define CONFIG_USBD_HS
#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE
+#ifndef CONFIG_NR_DRAM_BANKS
+# define CONFIG_NR_DRAM_BANKS 2
+#endif
+#define CONFIG_SYS_MEMTEST_START 0
+#define CONFIG_SYS_MEMTEST_END 1000
/* Have release address at the end of 256MB for now */
#define CPU_RELEASE_ADDR 0xFFFFFF0
# define CONFIG_IDENT_STRING " Xilinx ZynqMP"
#endif
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
/* Flat Device Tree Definitions */
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
#define CONFIG_MP
#define CONFIG_CMD_MII
# ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000
# endif
+#endif
+
+#if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQMP_USB)
# define CONFIG_FAT_WRITE
# define CONFIG_CMD_EXT4_WRITE
#endif
#define CONFIG_USB_DWC3
#define CONFIG_USB_DWC3_GADGET
-#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_PREBOOT "run bootargs"
#define CONFIG_BOOTCOMMAND "run $modeboot"
-#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOTDELAY 3
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
ZYNQMP_USB1_XHCI_BASEADDR}
-/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0
-#define CONFIG_SYS_SDRAM_SIZE 0x40000000
-
#define COUNTER_FREQUENCY 4000000
#include <configs/xilinx_zynqmp.h>
--- /dev/null
+/*
+ * Aeronix Zipit Z2 configuration file
+ *
+ * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
+#define CONFIG_SYS_TEXT_BASE 0x0
+
+#undef CONFIG_BOARD_LATE_INIT
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_PREBOOT
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR 0x40000
+#define CONFIG_ENV_SIZE 0x10000
+
+#define CONFIG_SYS_MALLOC_LEN (128*1024)
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
+ "then " \
+ "source 0xa0000000; " \
+ "else " \
+ "bootm 0x50000; " \
+ "fi; "
+#define CONFIG_BOOTARGS \
+ "console=tty0 console=ttyS2,115200 fbcon=rotate:3"
+#define CONFIG_TIMESTAMP
+#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_TEXT_BASE 0x0
+#define CONFIG_LZMA /* LZMA compression support */
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Serial Console Configuration
+ * STUART - the lower serial port on Colibri board
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_STUART 1
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Bootloader Components Configuration
+ */
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_CACHE
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_PXA_MMC_GENERIC
+#define CONFIG_SYS_MMC_BASE 0xF0000000
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * SPI and LCD
+ */
+#ifdef CONFIG_CMD_SPI
+#define CONFIG_SOFT_SPI
+#define CONFIG_LCD
+#define CONFIG_LCD_ROTATION
+#define CONFIG_PXA_LCD
+#define CONFIG_LMS283GF05
+
+#define SPI_DELAY udelay(10)
+#define SPI_SDA(val) zipitz2_spi_sda(val)
+#define SPI_SCL(val) zipitz2_spi_scl(val)
+#define SPI_READ zipitz2_spi_read()
+#ifndef __ASSEMBLY__
+void zipitz2_spi_sda(int);
+void zipitz2_spi_scl(int);
+unsigned char zipitz2_spi_read(void);
+#endif
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define CONFIG_SYS_HUSH_PARSER 1
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+
+/*
+ * Clock Configuration
+ */
+#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
+
+/*
+ * SRAM Map
+ */
+#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */
+#define PHYS_SRAM_SIZE 0x00040000 /* 256k */
+
+/*
+ * DRAM Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
+
+#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
+#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
+
+/*
+ * NOR FLASH
+ */
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
+#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+
+#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
+#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
+#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
+#define CONFIG_SYS_FLASH_PROTECTION
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GAFR0_L_VAL 0x02000140
+#define CONFIG_SYS_GAFR0_U_VAL 0x59188000
+#define CONFIG_SYS_GAFR1_L_VAL 0x63900002
+#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950
+#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL 0x29000308
+#define CONFIG_SYS_GAFR3_L_VAL 0x54000000
+#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5
+#define CONFIG_SYS_GPCR0_VAL 0x00000000
+#define CONFIG_SYS_GPCR1_VAL 0x00000020
+#define CONFIG_SYS_GPCR2_VAL 0x00000000
+#define CONFIG_SYS_GPCR3_VAL 0x00000000
+#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
+#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
+#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff
+#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
+#define CONFIG_SYS_GPSR0_VAL 0x06080400
+#define CONFIG_SYS_GPSR1_VAL 0x007f0000
+#define CONFIG_SYS_GPSR2_VAL 0x032a0000
+#define CONFIG_SYS_GPSR3_VAL 0x00000180
+
+#define CONFIG_SYS_PSSR_VAL 0x30
+
+/*
+ * Clock settings
+ */
+#define CONFIG_SYS_CKEN 0x00511220
+#define CONFIG_SYS_CCCR 0x00000190
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8
+#define CONFIG_SYS_MSC1_VAL 0x0000ccd1
+#define CONFIG_SYS_MSC2_VAL 0x0000b884
+#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9
+#define CONFIG_SYS_MDREFR_VAL 0x2011a01e
+#define CONFIG_SYS_MDMRS_VAL 0x00000000
+#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
+#define CONFIG_SYS_SXCNFG_VAL 0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL 0x00000001
+#define CONFIG_SYS_MCMEM0_VAL 0x00014307
+#define CONFIG_SYS_MCMEM1_VAL 0x00014307
+#define CONFIG_SYS_MCATT0_VAL 0x0001c787
+#define CONFIG_SYS_MCATT1_VAL 0x0001c787
+#define CONFIG_SYS_MCIO0_VAL 0x0001430f
+#define CONFIG_SYS_MCIO1_VAL 0x0001430f
+
+#include "pxa-common.h"
+
+#endif /* __CONFIG_H */
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_PHY_MARVELL
# define CONFIG_PHY_REALTEK
+# define CONFIG_PHY_XILINX
# define CONFIG_BOOTP_SERVERIP
# define CONFIG_BOOTP_BOOTPATH
# define CONFIG_BOOTP_GATEWAY
# define CONFIG_CMD_USB
# define CONFIG_USB_STORAGE
# define CONFIG_USB_EHCI_ZYNQ
-# define CONFIG_USB_ULPI_VIEWPORT
-# define CONFIG_USB_ULPI
# define CONFIG_EHCI_IS_TDI
# define CONFIG_USB_MAX_CONTROLLER_COUNT 2
# define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */
-# define CONFIG_USB_GADGET
# define CONFIG_USB_GADGET_DUALSPEED
# define CONFIG_USB_GADGET_DOWNLOAD
# define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000
# define CONFIG_G_DNL_VENDOR_NUM 0x03FD
# define CONFIG_G_DNL_PRODUCT_NUM 0x0300
# define CONFIG_G_DNL_MANUFACTURER "Xilinx"
-# define CONFIG_USB_GADGET
# define CONFIG_USB_CABLE_CHECK
# define CONFIG_CMD_DFU
# define CONFIG_CMD_THOR_DOWNLOAD
# define CONFIG_ENV_OFFSET 0xE0000
#endif
+/* enable preboot to be loaded before CONFIG_BOOTDELAY */
+#define CONFIG_PREBOOT
+
/* Default environment */
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"fit_image=fit.itb\0" \
"load_addr=0x2000000\0" \
"nor_flash_off=0xE2100000\0" \
"fdt_high=0x20000000\0" \
"initrd_high=0x20000000\0" \
+ "loadbootenv_addr=0x2000000\0" \
+ "bootenv=uEnv.txt\0" \
+ "bootenv_dev=mmc\0" \
+ "loadbootenv=load ${bootenv_dev} 0 ${loadbootenv_addr} ${bootenv}\0" \
+ "importbootenv=echo Importing environment from ${bootenv_dev} ...; " \
+ "env import -t ${loadbootenv_addr} $filesize\0" \
+ "bootenv_existence_test=test -e ${bootenv_dev} 0 /${bootenv}\0" \
+ "setbootenv=if env run bootenv_existence_test; then " \
+ "if env run loadbootenv; then " \
+ "env run importbootenv; " \
+ "fi; " \
+ "fi; \0" \
+ "sd_loadbootenv=set bootenv_dev mmc && " \
+ "run setbootenv \0" \
+ "usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv \0" \
+ "preboot=if test $modeboot = sdboot; then " \
+ "run sd_loadbootenv; " \
+ "echo Checking if uenvcmd is set ...; " \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...; " \
+ "run uenvcmd; " \
+ "fi; " \
+ "fi; \0" \
"norboot=echo Copying FIT from NOR flash to RAM... && " \
"cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \
"bootm ${load_addr}\0" \
"load usb 0 ${load_addr} ${fit_image} && " \
"bootm ${load_addr}; fi\0" \
DFU_ALT_INFO
+#endif
#define CONFIG_BOOTCOMMAND "run $modeboot"
#define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */
#define CONFIG_ZYNQ_I2C0
#define CONFIG_ZYNQ_I2C1
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x50
+#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0xFA
#define CONFIG_DISPLAY
#define CONFIG_I2C_EDID
--- /dev/null
+/*
+ * (C) Copyright 2016 Stephen Warren <swarren@wwwdotorg.org>
+ *
+ * Derived from pl01x code:
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __serial_bcm283x_mu_h
+#define __serial_bcm283x_mu_h
+
+/*
+ *Information about a serial port
+ *
+ * @base: Register base address
+ */
+struct bcm283x_mu_serial_platdata {
+ unsigned long base;
+ unsigned int clock;
+ bool skip_init;
+};
+
+#endif
* @base: Register base address
* @type: Port type
* @clock: Input clock rate, used for calculating the baud rate divisor
+ * @skip_init: Don't attempt to change port configuration (also means @clock
+ * is ignored)
*/
struct pl01x_serial_platdata {
unsigned long base;
enum pl01x_type type;
unsigned int clock;
+ bool skip_init;
};
#endif
UCLASS_RTC, /* Real time clock device */
UCLASS_SERIAL, /* Serial UART */
UCLASS_SPI, /* SPI bus */
+ UCLASS_SPMI, /* System Power Management Interface bus */
UCLASS_SPI_FLASH, /* SPI flash */
UCLASS_SPI_GENERIC, /* Generic SPI flash target */
UCLASS_SYSCON, /* System configuration device */
--- /dev/null
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_
+#define __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_
+
+#define SUN4I_A10_PLL2_1X 0
+#define SUN4I_A10_PLL2_2X 1
+#define SUN4I_A10_PLL2_4X 2
+#define SUN4I_A10_PLL2_8X 3
+
+#endif /* __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ */
#ifndef _DT_BINDINGS_INPUT_INPUT_H
#define _DT_BINDINGS_INPUT_INPUT_H
-#define KEY_RESERVED 0
-#define KEY_ESC 1
-#define KEY_1 2
-#define KEY_2 3
-#define KEY_3 4
-#define KEY_4 5
-#define KEY_5 6
-#define KEY_6 7
-#define KEY_7 8
-#define KEY_8 9
-#define KEY_9 10
-#define KEY_0 11
-#define KEY_MINUS 12
-#define KEY_EQUAL 13
-#define KEY_BACKSPACE 14
-#define KEY_TAB 15
-#define KEY_Q 16
-#define KEY_W 17
-#define KEY_E 18
-#define KEY_R 19
-#define KEY_T 20
-#define KEY_Y 21
-#define KEY_U 22
-#define KEY_I 23
-#define KEY_O 24
-#define KEY_P 25
-#define KEY_LEFTBRACE 26
-#define KEY_RIGHTBRACE 27
-#define KEY_ENTER 28
-#define KEY_LEFTCTRL 29
-#define KEY_A 30
-#define KEY_S 31
-#define KEY_D 32
-#define KEY_F 33
-#define KEY_G 34
-#define KEY_H 35
-#define KEY_J 36
-#define KEY_K 37
-#define KEY_L 38
-#define KEY_SEMICOLON 39
-#define KEY_APOSTROPHE 40
-#define KEY_GRAVE 41
-#define KEY_LEFTSHIFT 42
-#define KEY_BACKSLASH 43
-#define KEY_Z 44
-#define KEY_X 45
-#define KEY_C 46
-#define KEY_V 47
-#define KEY_B 48
-#define KEY_N 49
-#define KEY_M 50
-#define KEY_COMMA 51
-#define KEY_DOT 52
-#define KEY_SLASH 53
-#define KEY_RIGHTSHIFT 54
-#define KEY_KPASTERISK 55
-#define KEY_LEFTALT 56
-#define KEY_SPACE 57
-#define KEY_CAPSLOCK 58
-#define KEY_F1 59
-#define KEY_F2 60
-#define KEY_F3 61
-#define KEY_F4 62
-#define KEY_F5 63
-#define KEY_F6 64
-#define KEY_F7 65
-#define KEY_F8 66
-#define KEY_F9 67
-#define KEY_F10 68
-#define KEY_NUMLOCK 69
-#define KEY_SCROLLLOCK 70
-#define KEY_KP7 71
-#define KEY_KP8 72
-#define KEY_KP9 73
-#define KEY_KPMINUS 74
-#define KEY_KP4 75
-#define KEY_KP5 76
-#define KEY_KP6 77
-#define KEY_KPPLUS 78
-#define KEY_KP1 79
-#define KEY_KP2 80
-#define KEY_KP3 81
-#define KEY_KP0 82
-#define KEY_KPDOT 83
-
-#define KEY_ZENKAKUHANKAKU 85
-#define KEY_102ND 86
-#define KEY_F11 87
-#define KEY_F12 88
-#define KEY_RO 89
-#define KEY_KATAKANA 90
-#define KEY_HIRAGANA 91
-#define KEY_HENKAN 92
-#define KEY_KATAKANAHIRAGANA 93
-#define KEY_MUHENKAN 94
-#define KEY_KPJPCOMMA 95
-#define KEY_KPENTER 96
-#define KEY_RIGHTCTRL 97
-#define KEY_KPSLASH 98
-#define KEY_SYSRQ 99
-#define KEY_RIGHTALT 100
-#define KEY_LINEFEED 101
-#define KEY_HOME 102
-#define KEY_UP 103
-#define KEY_PAGEUP 104
-#define KEY_LEFT 105
-#define KEY_RIGHT 106
-#define KEY_END 107
-#define KEY_DOWN 108
-#define KEY_PAGEDOWN 109
-#define KEY_INSERT 110
-#define KEY_DELETE 111
-#define KEY_MACRO 112
-#define KEY_MUTE 113
-#define KEY_VOLUMEDOWN 114
-#define KEY_VOLUMEUP 115
-#define KEY_POWER 116 /* SC System Power Down */
-#define KEY_KPEQUAL 117
-#define KEY_KPPLUSMINUS 118
-#define KEY_PAUSE 119
-#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */
-
-#define KEY_KPCOMMA 121
-#define KEY_HANGEUL 122
-#define KEY_HANGUEL KEY_HANGEUL
-#define KEY_HANJA 123
-#define KEY_YEN 124
-#define KEY_LEFTMETA 125
-#define KEY_RIGHTMETA 126
-#define KEY_COMPOSE 127
-
-#define KEY_STOP 128 /* AC Stop */
-#define KEY_AGAIN 129
-#define KEY_PROPS 130 /* AC Properties */
-#define KEY_UNDO 131 /* AC Undo */
-#define KEY_FRONT 132
-#define KEY_COPY 133 /* AC Copy */
-#define KEY_OPEN 134 /* AC Open */
-#define KEY_PASTE 135 /* AC Paste */
-#define KEY_FIND 136 /* AC Search */
-#define KEY_CUT 137 /* AC Cut */
-#define KEY_HELP 138 /* AL Integrated Help Center */
-#define KEY_MENU 139 /* Menu (show menu) */
-#define KEY_CALC 140 /* AL Calculator */
-#define KEY_SETUP 141
-#define KEY_SLEEP 142 /* SC System Sleep */
-#define KEY_WAKEUP 143 /* System Wake Up */
-#define KEY_FILE 144 /* AL Local Machine Browser */
-#define KEY_SENDFILE 145
-#define KEY_DELETEFILE 146
-#define KEY_XFER 147
-#define KEY_PROG1 148
-#define KEY_PROG2 149
-#define KEY_WWW 150 /* AL Internet Browser */
-#define KEY_MSDOS 151
-#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */
-#define KEY_SCREENLOCK KEY_COFFEE
-#define KEY_DIRECTION 153
-#define KEY_CYCLEWINDOWS 154
-#define KEY_MAIL 155
-#define KEY_BOOKMARKS 156 /* AC Bookmarks */
-#define KEY_COMPUTER 157
-#define KEY_BACK 158 /* AC Back */
-#define KEY_FORWARD 159 /* AC Forward */
-#define KEY_CLOSECD 160
-#define KEY_EJECTCD 161
-#define KEY_EJECTCLOSECD 162
-#define KEY_NEXTSONG 163
-#define KEY_PLAYPAUSE 164
-#define KEY_PREVIOUSSONG 165
-#define KEY_STOPCD 166
-#define KEY_RECORD 167
-#define KEY_REWIND 168
-#define KEY_PHONE 169 /* Media Select Telephone */
-#define KEY_ISO 170
-#define KEY_CONFIG 171 /* AL Consumer Control Configuration */
-#define KEY_HOMEPAGE 172 /* AC Home */
-#define KEY_REFRESH 173 /* AC Refresh */
-#define KEY_EXIT 174 /* AC Exit */
-#define KEY_MOVE 175
-#define KEY_EDIT 176
-#define KEY_SCROLLUP 177
-#define KEY_SCROLLDOWN 178
-#define KEY_KPLEFTPAREN 179
-#define KEY_KPRIGHTPAREN 180
-#define KEY_NEW 181 /* AC New */
-#define KEY_REDO 182 /* AC Redo/Repeat */
-
-#define KEY_F13 183
-#define KEY_F14 184
-#define KEY_F15 185
-#define KEY_F16 186
-#define KEY_F17 187
-#define KEY_F18 188
-#define KEY_F19 189
-#define KEY_F20 190
-#define KEY_F21 191
-#define KEY_F22 192
-#define KEY_F23 193
-#define KEY_F24 194
-
-#define KEY_PLAYCD 200
-#define KEY_PAUSECD 201
-#define KEY_PROG3 202
-#define KEY_PROG4 203
-#define KEY_DASHBOARD 204 /* AL Dashboard */
-#define KEY_SUSPEND 205
-#define KEY_CLOSE 206 /* AC Close */
-#define KEY_PLAY 207
-#define KEY_FASTFORWARD 208
-#define KEY_BASSBOOST 209
-#define KEY_PRINT 210 /* AC Print */
-#define KEY_HP 211
-#define KEY_CAMERA 212
-#define KEY_SOUND 213
-#define KEY_QUESTION 214
-#define KEY_EMAIL 215
-#define KEY_CHAT 216
-#define KEY_SEARCH 217
-#define KEY_CONNECT 218
-#define KEY_FINANCE 219 /* AL Checkbook/Finance */
-#define KEY_SPORT 220
-#define KEY_SHOP 221
-#define KEY_ALTERASE 222
-#define KEY_CANCEL 223 /* AC Cancel */
-#define KEY_BRIGHTNESSDOWN 224
-#define KEY_BRIGHTNESSUP 225
-#define KEY_MEDIA 226
-
-#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video
- outputs (Monitor/LCD/TV-out/etc) */
-#define KEY_KBDILLUMTOGGLE 228
-#define KEY_KBDILLUMDOWN 229
-#define KEY_KBDILLUMUP 230
-
-#define KEY_SEND 231 /* AC Send */
-#define KEY_REPLY 232 /* AC Reply */
-#define KEY_FORWARDMAIL 233 /* AC Forward Msg */
-#define KEY_SAVE 234 /* AC Save */
-#define KEY_DOCUMENTS 235
-
-#define KEY_BATTERY 236
-
-#define KEY_BLUETOOTH 237
-#define KEY_WLAN 238
-#define KEY_UWB 239
-
-#define KEY_UNKNOWN 240
-
-#define KEY_VIDEO_NEXT 241 /* drive next video source */
-#define KEY_VIDEO_PREV 242 /* drive previous video source */
-#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */
-#define KEY_BRIGHTNESS_ZERO 244 /* brightness off, use ambient */
-#define KEY_DISPLAY_OFF 245 /* display device to off state */
-
-#define KEY_WIMAX 246
-#define KEY_RFKILL 247 /* Key that controls all radios */
-
-#define KEY_MICMUTE 248 /* Mute / unmute the microphone */
-
-/* Code 255 is reserved for special needs of AT keyboard driver */
-
-#define BTN_MISC 0x100
-#define BTN_0 0x100
-#define BTN_1 0x101
-#define BTN_2 0x102
-#define BTN_3 0x103
-#define BTN_4 0x104
-#define BTN_5 0x105
-#define BTN_6 0x106
-#define BTN_7 0x107
-#define BTN_8 0x108
-#define BTN_9 0x109
-
-#define BTN_MOUSE 0x110
-#define BTN_LEFT 0x110
-#define BTN_RIGHT 0x111
-#define BTN_MIDDLE 0x112
-#define BTN_SIDE 0x113
-#define BTN_EXTRA 0x114
-#define BTN_FORWARD 0x115
-#define BTN_BACK 0x116
-#define BTN_TASK 0x117
-
-#define BTN_JOYSTICK 0x120
-#define BTN_TRIGGER 0x120
-#define BTN_THUMB 0x121
-#define BTN_THUMB2 0x122
-#define BTN_TOP 0x123
-#define BTN_TOP2 0x124
-#define BTN_PINKIE 0x125
-#define BTN_BASE 0x126
-#define BTN_BASE2 0x127
-#define BTN_BASE3 0x128
-#define BTN_BASE4 0x129
-#define BTN_BASE5 0x12a
-#define BTN_BASE6 0x12b
-#define BTN_DEAD 0x12f
-
-#define BTN_GAMEPAD 0x130
-#define BTN_SOUTH 0x130
-#define BTN_A BTN_SOUTH
-#define BTN_EAST 0x131
-#define BTN_B BTN_EAST
-#define BTN_C 0x132
-#define BTN_NORTH 0x133
-#define BTN_X BTN_NORTH
-#define BTN_WEST 0x134
-#define BTN_Y BTN_WEST
-#define BTN_Z 0x135
-#define BTN_TL 0x136
-#define BTN_TR 0x137
-#define BTN_TL2 0x138
-#define BTN_TR2 0x139
-#define BTN_SELECT 0x13a
-#define BTN_START 0x13b
-#define BTN_MODE 0x13c
-#define BTN_THUMBL 0x13d
-#define BTN_THUMBR 0x13e
-
-#define BTN_DIGI 0x140
-#define BTN_TOOL_PEN 0x140
-#define BTN_TOOL_RUBBER 0x141
-#define BTN_TOOL_BRUSH 0x142
-#define BTN_TOOL_PENCIL 0x143
-#define BTN_TOOL_AIRBRUSH 0x144
-#define BTN_TOOL_FINGER 0x145
-#define BTN_TOOL_MOUSE 0x146
-#define BTN_TOOL_LENS 0x147
-#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */
-#define BTN_TOUCH 0x14a
-#define BTN_STYLUS 0x14b
-#define BTN_STYLUS2 0x14c
-#define BTN_TOOL_DOUBLETAP 0x14d
-#define BTN_TOOL_TRIPLETAP 0x14e
-#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */
-
-#define BTN_WHEEL 0x150
-#define BTN_GEAR_DOWN 0x150
-#define BTN_GEAR_UP 0x151
-
-#define KEY_OK 0x160
-#define KEY_SELECT 0x161
-#define KEY_GOTO 0x162
-#define KEY_CLEAR 0x163
-#define KEY_POWER2 0x164
-#define KEY_OPTION 0x165
-#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */
-#define KEY_TIME 0x167
-#define KEY_VENDOR 0x168
-#define KEY_ARCHIVE 0x169
-#define KEY_PROGRAM 0x16a /* Media Select Program Guide */
-#define KEY_CHANNEL 0x16b
-#define KEY_FAVORITES 0x16c
-#define KEY_EPG 0x16d
-#define KEY_PVR 0x16e /* Media Select Home */
-#define KEY_MHP 0x16f
-#define KEY_LANGUAGE 0x170
-#define KEY_TITLE 0x171
-#define KEY_SUBTITLE 0x172
-#define KEY_ANGLE 0x173
-#define KEY_ZOOM 0x174
-#define KEY_MODE 0x175
-#define KEY_KEYBOARD 0x176
-#define KEY_SCREEN 0x177
-#define KEY_PC 0x178 /* Media Select Computer */
-#define KEY_TV 0x179 /* Media Select TV */
-#define KEY_TV2 0x17a /* Media Select Cable */
-#define KEY_VCR 0x17b /* Media Select VCR */
-#define KEY_VCR2 0x17c /* VCR Plus */
-#define KEY_SAT 0x17d /* Media Select Satellite */
-#define KEY_SAT2 0x17e
-#define KEY_CD 0x17f /* Media Select CD */
-#define KEY_TAPE 0x180 /* Media Select Tape */
-#define KEY_RADIO 0x181
-#define KEY_TUNER 0x182 /* Media Select Tuner */
-#define KEY_PLAYER 0x183
-#define KEY_TEXT 0x184
-#define KEY_DVD 0x185 /* Media Select DVD */
-#define KEY_AUX 0x186
-#define KEY_MP3 0x187
-#define KEY_AUDIO 0x188 /* AL Audio Browser */
-#define KEY_VIDEO 0x189 /* AL Movie Browser */
-#define KEY_DIRECTORY 0x18a
-#define KEY_LIST 0x18b
-#define KEY_MEMO 0x18c /* Media Select Messages */
-#define KEY_CALENDAR 0x18d
-#define KEY_RED 0x18e
-#define KEY_GREEN 0x18f
-#define KEY_YELLOW 0x190
-#define KEY_BLUE 0x191
-#define KEY_CHANNELUP 0x192 /* Channel Increment */
-#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */
-#define KEY_FIRST 0x194
-#define KEY_LAST 0x195 /* Recall Last */
-#define KEY_AB 0x196
-#define KEY_NEXT 0x197
-#define KEY_RESTART 0x198
-#define KEY_SLOW 0x199
-#define KEY_SHUFFLE 0x19a
-#define KEY_BREAK 0x19b
-#define KEY_PREVIOUS 0x19c
-#define KEY_DIGITS 0x19d
-#define KEY_TEEN 0x19e
-#define KEY_TWEN 0x19f
-#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */
-#define KEY_GAMES 0x1a1 /* Media Select Games */
-#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */
-#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */
-#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */
-#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */
-#define KEY_EDITOR 0x1a6 /* AL Text Editor */
-#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */
-#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */
-#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */
-#define KEY_DATABASE 0x1aa /* AL Database App */
-#define KEY_NEWS 0x1ab /* AL Newsreader */
-#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */
-#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */
-#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */
-#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */
-#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */
-#define KEY_LOGOFF 0x1b1 /* AL Logoff */
-
-#define KEY_DOLLAR 0x1b2
-#define KEY_EURO 0x1b3
-
-#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */
-#define KEY_FRAMEFORWARD 0x1b5
-#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */
-#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */
-#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */
-#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */
-#define KEY_IMAGES 0x1ba /* AL Image Browser */
-
-#define KEY_DEL_EOL 0x1c0
-#define KEY_DEL_EOS 0x1c1
-#define KEY_INS_LINE 0x1c2
-#define KEY_DEL_LINE 0x1c3
-
-#define KEY_FN 0x1d0
-#define KEY_FN_ESC 0x1d1
-#define KEY_FN_F1 0x1d2
-#define KEY_FN_F2 0x1d3
-#define KEY_FN_F3 0x1d4
-#define KEY_FN_F4 0x1d5
-#define KEY_FN_F5 0x1d6
-#define KEY_FN_F6 0x1d7
-#define KEY_FN_F7 0x1d8
-#define KEY_FN_F8 0x1d9
-#define KEY_FN_F9 0x1da
-#define KEY_FN_F10 0x1db
-#define KEY_FN_F11 0x1dc
-#define KEY_FN_F12 0x1dd
-#define KEY_FN_1 0x1de
-#define KEY_FN_2 0x1df
-#define KEY_FN_D 0x1e0
-#define KEY_FN_E 0x1e1
-#define KEY_FN_F 0x1e2
-#define KEY_FN_S 0x1e3
-#define KEY_FN_B 0x1e4
-
-#define KEY_BRL_DOT1 0x1f1
-#define KEY_BRL_DOT2 0x1f2
-#define KEY_BRL_DOT3 0x1f3
-#define KEY_BRL_DOT4 0x1f4
-#define KEY_BRL_DOT5 0x1f5
-#define KEY_BRL_DOT6 0x1f6
-#define KEY_BRL_DOT7 0x1f7
-#define KEY_BRL_DOT8 0x1f8
-#define KEY_BRL_DOT9 0x1f9
-#define KEY_BRL_DOT10 0x1fa
-
-#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */
-#define KEY_NUMERIC_1 0x201 /* and other keypads */
-#define KEY_NUMERIC_2 0x202
-#define KEY_NUMERIC_3 0x203
-#define KEY_NUMERIC_4 0x204
-#define KEY_NUMERIC_5 0x205
-#define KEY_NUMERIC_6 0x206
-#define KEY_NUMERIC_7 0x207
-#define KEY_NUMERIC_8 0x208
-#define KEY_NUMERIC_9 0x209
-#define KEY_NUMERIC_STAR 0x20a
-#define KEY_NUMERIC_POUND 0x20b
-
-#define KEY_CAMERA_FOCUS 0x210
-#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */
-
-#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */
-#define KEY_TOUCHPAD_ON 0x213
-#define KEY_TOUCHPAD_OFF 0x214
-
-#define KEY_CAMERA_ZOOMIN 0x215
-#define KEY_CAMERA_ZOOMOUT 0x216
-#define KEY_CAMERA_UP 0x217
-#define KEY_CAMERA_DOWN 0x218
-#define KEY_CAMERA_LEFT 0x219
-#define KEY_CAMERA_RIGHT 0x21a
-
-#define KEY_ATTENDANT_ON 0x21b
-#define KEY_ATTENDANT_OFF 0x21c
-#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */
-#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */
-
-#define BTN_DPAD_UP 0x220
-#define BTN_DPAD_DOWN 0x221
-#define BTN_DPAD_LEFT 0x222
-#define BTN_DPAD_RIGHT 0x223
+#include "linux-event-codes.h"
#define MATRIX_KEY(row, col, code) \
((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))
--- /dev/null
+/*
+ * Input event codes
+ *
+ * *** IMPORTANT ***
+ * This file is not only included from C-code but also from devicetree source
+ * files. As such this file MUST only contain comments and defines.
+ *
+ * Copyright (c) 1999-2002 Vojtech Pavlik
+ * Copyright (c) 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef _UAPI_INPUT_EVENT_CODES_H
+#define _UAPI_INPUT_EVENT_CODES_H
+
+/*
+ * Device properties and quirks
+ */
+
+#define INPUT_PROP_POINTER 0x00 /* needs a pointer */
+#define INPUT_PROP_DIRECT 0x01 /* direct input devices */
+#define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */
+#define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */
+#define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */
+#define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */
+#define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */
+
+#define INPUT_PROP_MAX 0x1f
+#define INPUT_PROP_CNT (INPUT_PROP_MAX + 1)
+
+/*
+ * Event types
+ */
+
+#define EV_SYN 0x00
+#define EV_KEY 0x01
+#define EV_REL 0x02
+#define EV_ABS 0x03
+#define EV_MSC 0x04
+#define EV_SW 0x05
+#define EV_LED 0x11
+#define EV_SND 0x12
+#define EV_REP 0x14
+#define EV_FF 0x15
+#define EV_PWR 0x16
+#define EV_FF_STATUS 0x17
+#define EV_MAX 0x1f
+#define EV_CNT (EV_MAX+1)
+
+/*
+ * Synchronization events.
+ */
+
+#define SYN_REPORT 0
+#define SYN_CONFIG 1
+#define SYN_MT_REPORT 2
+#define SYN_DROPPED 3
+#define SYN_MAX 0xf
+#define SYN_CNT (SYN_MAX+1)
+
+/*
+ * Keys and buttons
+ *
+ * Most of the keys/buttons are modeled after USB HUT 1.12
+ * (see http://www.usb.org/developers/hidpage).
+ * Abbreviations in the comments:
+ * AC - Application Control
+ * AL - Application Launch Button
+ * SC - System Control
+ */
+
+#define KEY_RESERVED 0
+#define KEY_ESC 1
+#define KEY_1 2
+#define KEY_2 3
+#define KEY_3 4
+#define KEY_4 5
+#define KEY_5 6
+#define KEY_6 7
+#define KEY_7 8
+#define KEY_8 9
+#define KEY_9 10
+#define KEY_0 11
+#define KEY_MINUS 12
+#define KEY_EQUAL 13
+#define KEY_BACKSPACE 14
+#define KEY_TAB 15
+#define KEY_Q 16
+#define KEY_W 17
+#define KEY_E 18
+#define KEY_R 19
+#define KEY_T 20
+#define KEY_Y 21
+#define KEY_U 22
+#define KEY_I 23
+#define KEY_O 24
+#define KEY_P 25
+#define KEY_LEFTBRACE 26
+#define KEY_RIGHTBRACE 27
+#define KEY_ENTER 28
+#define KEY_LEFTCTRL 29
+#define KEY_A 30
+#define KEY_S 31
+#define KEY_D 32
+#define KEY_F 33
+#define KEY_G 34
+#define KEY_H 35
+#define KEY_J 36
+#define KEY_K 37
+#define KEY_L 38
+#define KEY_SEMICOLON 39
+#define KEY_APOSTROPHE 40
+#define KEY_GRAVE 41
+#define KEY_LEFTSHIFT 42
+#define KEY_BACKSLASH 43
+#define KEY_Z 44
+#define KEY_X 45
+#define KEY_C 46
+#define KEY_V 47
+#define KEY_B 48
+#define KEY_N 49
+#define KEY_M 50
+#define KEY_COMMA 51
+#define KEY_DOT 52
+#define KEY_SLASH 53
+#define KEY_RIGHTSHIFT 54
+#define KEY_KPASTERISK 55
+#define KEY_LEFTALT 56
+#define KEY_SPACE 57
+#define KEY_CAPSLOCK 58
+#define KEY_F1 59
+#define KEY_F2 60
+#define KEY_F3 61
+#define KEY_F4 62
+#define KEY_F5 63
+#define KEY_F6 64
+#define KEY_F7 65
+#define KEY_F8 66
+#define KEY_F9 67
+#define KEY_F10 68
+#define KEY_NUMLOCK 69
+#define KEY_SCROLLLOCK 70
+#define KEY_KP7 71
+#define KEY_KP8 72
+#define KEY_KP9 73
+#define KEY_KPMINUS 74
+#define KEY_KP4 75
+#define KEY_KP5 76
+#define KEY_KP6 77
+#define KEY_KPPLUS 78
+#define KEY_KP1 79
+#define KEY_KP2 80
+#define KEY_KP3 81
+#define KEY_KP0 82
+#define KEY_KPDOT 83
+
+#define KEY_ZENKAKUHANKAKU 85
+#define KEY_102ND 86
+#define KEY_F11 87
+#define KEY_F12 88
+#define KEY_RO 89
+#define KEY_KATAKANA 90
+#define KEY_HIRAGANA 91
+#define KEY_HENKAN 92
+#define KEY_KATAKANAHIRAGANA 93
+#define KEY_MUHENKAN 94
+#define KEY_KPJPCOMMA 95
+#define KEY_KPENTER 96
+#define KEY_RIGHTCTRL 97
+#define KEY_KPSLASH 98
+#define KEY_SYSRQ 99
+#define KEY_RIGHTALT 100
+#define KEY_LINEFEED 101
+#define KEY_HOME 102
+#define KEY_UP 103
+#define KEY_PAGEUP 104
+#define KEY_LEFT 105
+#define KEY_RIGHT 106
+#define KEY_END 107
+#define KEY_DOWN 108
+#define KEY_PAGEDOWN 109
+#define KEY_INSERT 110
+#define KEY_DELETE 111
+#define KEY_MACRO 112
+#define KEY_MUTE 113
+#define KEY_VOLUMEDOWN 114
+#define KEY_VOLUMEUP 115
+#define KEY_POWER 116 /* SC System Power Down */
+#define KEY_KPEQUAL 117
+#define KEY_KPPLUSMINUS 118
+#define KEY_PAUSE 119
+#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */
+
+#define KEY_KPCOMMA 121
+#define KEY_HANGEUL 122
+#define KEY_HANGUEL KEY_HANGEUL
+#define KEY_HANJA 123
+#define KEY_YEN 124
+#define KEY_LEFTMETA 125
+#define KEY_RIGHTMETA 126
+#define KEY_COMPOSE 127
+
+#define KEY_STOP 128 /* AC Stop */
+#define KEY_AGAIN 129
+#define KEY_PROPS 130 /* AC Properties */
+#define KEY_UNDO 131 /* AC Undo */
+#define KEY_FRONT 132
+#define KEY_COPY 133 /* AC Copy */
+#define KEY_OPEN 134 /* AC Open */
+#define KEY_PASTE 135 /* AC Paste */
+#define KEY_FIND 136 /* AC Search */
+#define KEY_CUT 137 /* AC Cut */
+#define KEY_HELP 138 /* AL Integrated Help Center */
+#define KEY_MENU 139 /* Menu (show menu) */
+#define KEY_CALC 140 /* AL Calculator */
+#define KEY_SETUP 141
+#define KEY_SLEEP 142 /* SC System Sleep */
+#define KEY_WAKEUP 143 /* System Wake Up */
+#define KEY_FILE 144 /* AL Local Machine Browser */
+#define KEY_SENDFILE 145
+#define KEY_DELETEFILE 146
+#define KEY_XFER 147
+#define KEY_PROG1 148
+#define KEY_PROG2 149
+#define KEY_WWW 150 /* AL Internet Browser */
+#define KEY_MSDOS 151
+#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */
+#define KEY_SCREENLOCK KEY_COFFEE
+#define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */
+#define KEY_DIRECTION KEY_ROTATE_DISPLAY
+#define KEY_CYCLEWINDOWS 154
+#define KEY_MAIL 155
+#define KEY_BOOKMARKS 156 /* AC Bookmarks */
+#define KEY_COMPUTER 157
+#define KEY_BACK 158 /* AC Back */
+#define KEY_FORWARD 159 /* AC Forward */
+#define KEY_CLOSECD 160
+#define KEY_EJECTCD 161
+#define KEY_EJECTCLOSECD 162
+#define KEY_NEXTSONG 163
+#define KEY_PLAYPAUSE 164
+#define KEY_PREVIOUSSONG 165
+#define KEY_STOPCD 166
+#define KEY_RECORD 167
+#define KEY_REWIND 168
+#define KEY_PHONE 169 /* Media Select Telephone */
+#define KEY_ISO 170
+#define KEY_CONFIG 171 /* AL Consumer Control Configuration */
+#define KEY_HOMEPAGE 172 /* AC Home */
+#define KEY_REFRESH 173 /* AC Refresh */
+#define KEY_EXIT 174 /* AC Exit */
+#define KEY_MOVE 175
+#define KEY_EDIT 176
+#define KEY_SCROLLUP 177
+#define KEY_SCROLLDOWN 178
+#define KEY_KPLEFTPAREN 179
+#define KEY_KPRIGHTPAREN 180
+#define KEY_NEW 181 /* AC New */
+#define KEY_REDO 182 /* AC Redo/Repeat */
+
+#define KEY_F13 183
+#define KEY_F14 184
+#define KEY_F15 185
+#define KEY_F16 186
+#define KEY_F17 187
+#define KEY_F18 188
+#define KEY_F19 189
+#define KEY_F20 190
+#define KEY_F21 191
+#define KEY_F22 192
+#define KEY_F23 193
+#define KEY_F24 194
+
+#define KEY_PLAYCD 200
+#define KEY_PAUSECD 201
+#define KEY_PROG3 202
+#define KEY_PROG4 203
+#define KEY_DASHBOARD 204 /* AL Dashboard */
+#define KEY_SUSPEND 205
+#define KEY_CLOSE 206 /* AC Close */
+#define KEY_PLAY 207
+#define KEY_FASTFORWARD 208
+#define KEY_BASSBOOST 209
+#define KEY_PRINT 210 /* AC Print */
+#define KEY_HP 211
+#define KEY_CAMERA 212
+#define KEY_SOUND 213
+#define KEY_QUESTION 214
+#define KEY_EMAIL 215
+#define KEY_CHAT 216
+#define KEY_SEARCH 217
+#define KEY_CONNECT 218
+#define KEY_FINANCE 219 /* AL Checkbook/Finance */
+#define KEY_SPORT 220
+#define KEY_SHOP 221
+#define KEY_ALTERASE 222
+#define KEY_CANCEL 223 /* AC Cancel */
+#define KEY_BRIGHTNESSDOWN 224
+#define KEY_BRIGHTNESSUP 225
+#define KEY_MEDIA 226
+
+#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video
+ outputs (Monitor/LCD/TV-out/etc) */
+#define KEY_KBDILLUMTOGGLE 228
+#define KEY_KBDILLUMDOWN 229
+#define KEY_KBDILLUMUP 230
+
+#define KEY_SEND 231 /* AC Send */
+#define KEY_REPLY 232 /* AC Reply */
+#define KEY_FORWARDMAIL 233 /* AC Forward Msg */
+#define KEY_SAVE 234 /* AC Save */
+#define KEY_DOCUMENTS 235
+
+#define KEY_BATTERY 236
+
+#define KEY_BLUETOOTH 237
+#define KEY_WLAN 238
+#define KEY_UWB 239
+
+#define KEY_UNKNOWN 240
+
+#define KEY_VIDEO_NEXT 241 /* drive next video source */
+#define KEY_VIDEO_PREV 242 /* drive previous video source */
+#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */
+#define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual
+ brightness control is off,
+ rely on ambient */
+#define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO
+#define KEY_DISPLAY_OFF 245 /* display device to off state */
+
+#define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */
+#define KEY_WIMAX KEY_WWAN
+#define KEY_RFKILL 247 /* Key that controls all radios */
+
+#define KEY_MICMUTE 248 /* Mute / unmute the microphone */
+
+/* Code 255 is reserved for special needs of AT keyboard driver */
+
+#define BTN_MISC 0x100
+#define BTN_0 0x100
+#define BTN_1 0x101
+#define BTN_2 0x102
+#define BTN_3 0x103
+#define BTN_4 0x104
+#define BTN_5 0x105
+#define BTN_6 0x106
+#define BTN_7 0x107
+#define BTN_8 0x108
+#define BTN_9 0x109
+
+#define BTN_MOUSE 0x110
+#define BTN_LEFT 0x110
+#define BTN_RIGHT 0x111
+#define BTN_MIDDLE 0x112
+#define BTN_SIDE 0x113
+#define BTN_EXTRA 0x114
+#define BTN_FORWARD 0x115
+#define BTN_BACK 0x116
+#define BTN_TASK 0x117
+
+#define BTN_JOYSTICK 0x120
+#define BTN_TRIGGER 0x120
+#define BTN_THUMB 0x121
+#define BTN_THUMB2 0x122
+#define BTN_TOP 0x123
+#define BTN_TOP2 0x124
+#define BTN_PINKIE 0x125
+#define BTN_BASE 0x126
+#define BTN_BASE2 0x127
+#define BTN_BASE3 0x128
+#define BTN_BASE4 0x129
+#define BTN_BASE5 0x12a
+#define BTN_BASE6 0x12b
+#define BTN_DEAD 0x12f
+
+#define BTN_GAMEPAD 0x130
+#define BTN_SOUTH 0x130
+#define BTN_A BTN_SOUTH
+#define BTN_EAST 0x131
+#define BTN_B BTN_EAST
+#define BTN_C 0x132
+#define BTN_NORTH 0x133
+#define BTN_X BTN_NORTH
+#define BTN_WEST 0x134
+#define BTN_Y BTN_WEST
+#define BTN_Z 0x135
+#define BTN_TL 0x136
+#define BTN_TR 0x137
+#define BTN_TL2 0x138
+#define BTN_TR2 0x139
+#define BTN_SELECT 0x13a
+#define BTN_START 0x13b
+#define BTN_MODE 0x13c
+#define BTN_THUMBL 0x13d
+#define BTN_THUMBR 0x13e
+
+#define BTN_DIGI 0x140
+#define BTN_TOOL_PEN 0x140
+#define BTN_TOOL_RUBBER 0x141
+#define BTN_TOOL_BRUSH 0x142
+#define BTN_TOOL_PENCIL 0x143
+#define BTN_TOOL_AIRBRUSH 0x144
+#define BTN_TOOL_FINGER 0x145
+#define BTN_TOOL_MOUSE 0x146
+#define BTN_TOOL_LENS 0x147
+#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */
+#define BTN_TOUCH 0x14a
+#define BTN_STYLUS 0x14b
+#define BTN_STYLUS2 0x14c
+#define BTN_TOOL_DOUBLETAP 0x14d
+#define BTN_TOOL_TRIPLETAP 0x14e
+#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */
+
+#define BTN_WHEEL 0x150
+#define BTN_GEAR_DOWN 0x150
+#define BTN_GEAR_UP 0x151
+
+#define KEY_OK 0x160
+#define KEY_SELECT 0x161
+#define KEY_GOTO 0x162
+#define KEY_CLEAR 0x163
+#define KEY_POWER2 0x164
+#define KEY_OPTION 0x165
+#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */
+#define KEY_TIME 0x167
+#define KEY_VENDOR 0x168
+#define KEY_ARCHIVE 0x169
+#define KEY_PROGRAM 0x16a /* Media Select Program Guide */
+#define KEY_CHANNEL 0x16b
+#define KEY_FAVORITES 0x16c
+#define KEY_EPG 0x16d
+#define KEY_PVR 0x16e /* Media Select Home */
+#define KEY_MHP 0x16f
+#define KEY_LANGUAGE 0x170
+#define KEY_TITLE 0x171
+#define KEY_SUBTITLE 0x172
+#define KEY_ANGLE 0x173
+#define KEY_ZOOM 0x174
+#define KEY_MODE 0x175
+#define KEY_KEYBOARD 0x176
+#define KEY_SCREEN 0x177
+#define KEY_PC 0x178 /* Media Select Computer */
+#define KEY_TV 0x179 /* Media Select TV */
+#define KEY_TV2 0x17a /* Media Select Cable */
+#define KEY_VCR 0x17b /* Media Select VCR */
+#define KEY_VCR2 0x17c /* VCR Plus */
+#define KEY_SAT 0x17d /* Media Select Satellite */
+#define KEY_SAT2 0x17e
+#define KEY_CD 0x17f /* Media Select CD */
+#define KEY_TAPE 0x180 /* Media Select Tape */
+#define KEY_RADIO 0x181
+#define KEY_TUNER 0x182 /* Media Select Tuner */
+#define KEY_PLAYER 0x183
+#define KEY_TEXT 0x184
+#define KEY_DVD 0x185 /* Media Select DVD */
+#define KEY_AUX 0x186
+#define KEY_MP3 0x187
+#define KEY_AUDIO 0x188 /* AL Audio Browser */
+#define KEY_VIDEO 0x189 /* AL Movie Browser */
+#define KEY_DIRECTORY 0x18a
+#define KEY_LIST 0x18b
+#define KEY_MEMO 0x18c /* Media Select Messages */
+#define KEY_CALENDAR 0x18d
+#define KEY_RED 0x18e
+#define KEY_GREEN 0x18f
+#define KEY_YELLOW 0x190
+#define KEY_BLUE 0x191
+#define KEY_CHANNELUP 0x192 /* Channel Increment */
+#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */
+#define KEY_FIRST 0x194
+#define KEY_LAST 0x195 /* Recall Last */
+#define KEY_AB 0x196
+#define KEY_NEXT 0x197
+#define KEY_RESTART 0x198
+#define KEY_SLOW 0x199
+#define KEY_SHUFFLE 0x19a
+#define KEY_BREAK 0x19b
+#define KEY_PREVIOUS 0x19c
+#define KEY_DIGITS 0x19d
+#define KEY_TEEN 0x19e
+#define KEY_TWEN 0x19f
+#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */
+#define KEY_GAMES 0x1a1 /* Media Select Games */
+#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */
+#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */
+#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */
+#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */
+#define KEY_EDITOR 0x1a6 /* AL Text Editor */
+#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */
+#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */
+#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */
+#define KEY_DATABASE 0x1aa /* AL Database App */
+#define KEY_NEWS 0x1ab /* AL Newsreader */
+#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */
+#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */
+#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */
+#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */
+#define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE
+#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */
+#define KEY_LOGOFF 0x1b1 /* AL Logoff */
+
+#define KEY_DOLLAR 0x1b2
+#define KEY_EURO 0x1b3
+
+#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */
+#define KEY_FRAMEFORWARD 0x1b5
+#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */
+#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */
+#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */
+#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */
+#define KEY_IMAGES 0x1ba /* AL Image Browser */
+
+#define KEY_DEL_EOL 0x1c0
+#define KEY_DEL_EOS 0x1c1
+#define KEY_INS_LINE 0x1c2
+#define KEY_DEL_LINE 0x1c3
+
+#define KEY_FN 0x1d0
+#define KEY_FN_ESC 0x1d1
+#define KEY_FN_F1 0x1d2
+#define KEY_FN_F2 0x1d3
+#define KEY_FN_F3 0x1d4
+#define KEY_FN_F4 0x1d5
+#define KEY_FN_F5 0x1d6
+#define KEY_FN_F6 0x1d7
+#define KEY_FN_F7 0x1d8
+#define KEY_FN_F8 0x1d9
+#define KEY_FN_F9 0x1da
+#define KEY_FN_F10 0x1db
+#define KEY_FN_F11 0x1dc
+#define KEY_FN_F12 0x1dd
+#define KEY_FN_1 0x1de
+#define KEY_FN_2 0x1df
+#define KEY_FN_D 0x1e0
+#define KEY_FN_E 0x1e1
+#define KEY_FN_F 0x1e2
+#define KEY_FN_S 0x1e3
+#define KEY_FN_B 0x1e4
+
+#define KEY_BRL_DOT1 0x1f1
+#define KEY_BRL_DOT2 0x1f2
+#define KEY_BRL_DOT3 0x1f3
+#define KEY_BRL_DOT4 0x1f4
+#define KEY_BRL_DOT5 0x1f5
+#define KEY_BRL_DOT6 0x1f6
+#define KEY_BRL_DOT7 0x1f7
+#define KEY_BRL_DOT8 0x1f8
+#define KEY_BRL_DOT9 0x1f9
+#define KEY_BRL_DOT10 0x1fa
+
+#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */
+#define KEY_NUMERIC_1 0x201 /* and other keypads */
+#define KEY_NUMERIC_2 0x202
+#define KEY_NUMERIC_3 0x203
+#define KEY_NUMERIC_4 0x204
+#define KEY_NUMERIC_5 0x205
+#define KEY_NUMERIC_6 0x206
+#define KEY_NUMERIC_7 0x207
+#define KEY_NUMERIC_8 0x208
+#define KEY_NUMERIC_9 0x209
+#define KEY_NUMERIC_STAR 0x20a
+#define KEY_NUMERIC_POUND 0x20b
+#define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */
+#define KEY_NUMERIC_B 0x20d
+#define KEY_NUMERIC_C 0x20e
+#define KEY_NUMERIC_D 0x20f
+
+#define KEY_CAMERA_FOCUS 0x210
+#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */
+
+#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */
+#define KEY_TOUCHPAD_ON 0x213
+#define KEY_TOUCHPAD_OFF 0x214
+
+#define KEY_CAMERA_ZOOMIN 0x215
+#define KEY_CAMERA_ZOOMOUT 0x216
+#define KEY_CAMERA_UP 0x217
+#define KEY_CAMERA_DOWN 0x218
+#define KEY_CAMERA_LEFT 0x219
+#define KEY_CAMERA_RIGHT 0x21a
+
+#define KEY_ATTENDANT_ON 0x21b
+#define KEY_ATTENDANT_OFF 0x21c
+#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */
+#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */
+
+#define BTN_DPAD_UP 0x220
+#define BTN_DPAD_DOWN 0x221
+#define BTN_DPAD_LEFT 0x222
+#define BTN_DPAD_RIGHT 0x223
+
+#define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */
+
+#define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */
+#define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */
+#define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */
+#define KEY_CONTROLPANEL 0x243 /* AL Control Panel */
+#define KEY_APPSELECT 0x244 /* AL Select Task/Application */
+#define KEY_SCREENSAVER 0x245 /* AL Screen Saver */
+#define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */
+
+#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */
+#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */
+
+#define KEY_KBDINPUTASSIST_PREV 0x260
+#define KEY_KBDINPUTASSIST_NEXT 0x261
+#define KEY_KBDINPUTASSIST_PREVGROUP 0x262
+#define KEY_KBDINPUTASSIST_NEXTGROUP 0x263
+#define KEY_KBDINPUTASSIST_ACCEPT 0x264
+#define KEY_KBDINPUTASSIST_CANCEL 0x265
+
+#define BTN_TRIGGER_HAPPY 0x2c0
+#define BTN_TRIGGER_HAPPY1 0x2c0
+#define BTN_TRIGGER_HAPPY2 0x2c1
+#define BTN_TRIGGER_HAPPY3 0x2c2
+#define BTN_TRIGGER_HAPPY4 0x2c3
+#define BTN_TRIGGER_HAPPY5 0x2c4
+#define BTN_TRIGGER_HAPPY6 0x2c5
+#define BTN_TRIGGER_HAPPY7 0x2c6
+#define BTN_TRIGGER_HAPPY8 0x2c7
+#define BTN_TRIGGER_HAPPY9 0x2c8
+#define BTN_TRIGGER_HAPPY10 0x2c9
+#define BTN_TRIGGER_HAPPY11 0x2ca
+#define BTN_TRIGGER_HAPPY12 0x2cb
+#define BTN_TRIGGER_HAPPY13 0x2cc
+#define BTN_TRIGGER_HAPPY14 0x2cd
+#define BTN_TRIGGER_HAPPY15 0x2ce
+#define BTN_TRIGGER_HAPPY16 0x2cf
+#define BTN_TRIGGER_HAPPY17 0x2d0
+#define BTN_TRIGGER_HAPPY18 0x2d1
+#define BTN_TRIGGER_HAPPY19 0x2d2
+#define BTN_TRIGGER_HAPPY20 0x2d3
+#define BTN_TRIGGER_HAPPY21 0x2d4
+#define BTN_TRIGGER_HAPPY22 0x2d5
+#define BTN_TRIGGER_HAPPY23 0x2d6
+#define BTN_TRIGGER_HAPPY24 0x2d7
+#define BTN_TRIGGER_HAPPY25 0x2d8
+#define BTN_TRIGGER_HAPPY26 0x2d9
+#define BTN_TRIGGER_HAPPY27 0x2da
+#define BTN_TRIGGER_HAPPY28 0x2db
+#define BTN_TRIGGER_HAPPY29 0x2dc
+#define BTN_TRIGGER_HAPPY30 0x2dd
+#define BTN_TRIGGER_HAPPY31 0x2de
+#define BTN_TRIGGER_HAPPY32 0x2df
+#define BTN_TRIGGER_HAPPY33 0x2e0
+#define BTN_TRIGGER_HAPPY34 0x2e1
+#define BTN_TRIGGER_HAPPY35 0x2e2
+#define BTN_TRIGGER_HAPPY36 0x2e3
+#define BTN_TRIGGER_HAPPY37 0x2e4
+#define BTN_TRIGGER_HAPPY38 0x2e5
+#define BTN_TRIGGER_HAPPY39 0x2e6
+#define BTN_TRIGGER_HAPPY40 0x2e7
+
+/* We avoid low common keys in module aliases so they don't get huge. */
+#define KEY_MIN_INTERESTING KEY_MUTE
+#define KEY_MAX 0x2ff
+#define KEY_CNT (KEY_MAX+1)
+
+/*
+ * Relative axes
+ */
+
+#define REL_X 0x00
+#define REL_Y 0x01
+#define REL_Z 0x02
+#define REL_RX 0x03
+#define REL_RY 0x04
+#define REL_RZ 0x05
+#define REL_HWHEEL 0x06
+#define REL_DIAL 0x07
+#define REL_WHEEL 0x08
+#define REL_MISC 0x09
+#define REL_MAX 0x0f
+#define REL_CNT (REL_MAX+1)
+
+/*
+ * Absolute axes
+ */
+
+#define ABS_X 0x00
+#define ABS_Y 0x01
+#define ABS_Z 0x02
+#define ABS_RX 0x03
+#define ABS_RY 0x04
+#define ABS_RZ 0x05
+#define ABS_THROTTLE 0x06
+#define ABS_RUDDER 0x07
+#define ABS_WHEEL 0x08
+#define ABS_GAS 0x09
+#define ABS_BRAKE 0x0a
+#define ABS_HAT0X 0x10
+#define ABS_HAT0Y 0x11
+#define ABS_HAT1X 0x12
+#define ABS_HAT1Y 0x13
+#define ABS_HAT2X 0x14
+#define ABS_HAT2Y 0x15
+#define ABS_HAT3X 0x16
+#define ABS_HAT3Y 0x17
+#define ABS_PRESSURE 0x18
+#define ABS_DISTANCE 0x19
+#define ABS_TILT_X 0x1a
+#define ABS_TILT_Y 0x1b
+#define ABS_TOOL_WIDTH 0x1c
+
+#define ABS_VOLUME 0x20
+
+#define ABS_MISC 0x28
+
+#define ABS_MT_SLOT 0x2f /* MT slot being modified */
+#define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */
+#define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */
+#define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */
+#define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */
+#define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */
+#define ABS_MT_POSITION_X 0x35 /* Center X touch position */
+#define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */
+#define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */
+#define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */
+#define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */
+#define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */
+#define ABS_MT_DISTANCE 0x3b /* Contact hover distance */
+#define ABS_MT_TOOL_X 0x3c /* Center X tool position */
+#define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */
+
+
+#define ABS_MAX 0x3f
+#define ABS_CNT (ABS_MAX+1)
+
+/*
+ * Switch events
+ */
+
+#define SW_LID 0x00 /* set = lid shut */
+#define SW_TABLET_MODE 0x01 /* set = tablet mode */
+#define SW_HEADPHONE_INSERT 0x02 /* set = inserted */
+#define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any"
+ set = radio enabled */
+#define SW_RADIO SW_RFKILL_ALL /* deprecated */
+#define SW_MICROPHONE_INSERT 0x04 /* set = inserted */
+#define SW_DOCK 0x05 /* set = plugged into dock */
+#define SW_LINEOUT_INSERT 0x06 /* set = inserted */
+#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */
+#define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */
+#define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */
+#define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */
+#define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */
+#define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */
+#define SW_LINEIN_INSERT 0x0d /* set = inserted */
+#define SW_MUTE_DEVICE 0x0e /* set = device disabled */
+#define SW_MAX 0x0f
+#define SW_CNT (SW_MAX+1)
+
+/*
+ * Misc events
+ */
+
+#define MSC_SERIAL 0x00
+#define MSC_PULSELED 0x01
+#define MSC_GESTURE 0x02
+#define MSC_RAW 0x03
+#define MSC_SCAN 0x04
+#define MSC_TIMESTAMP 0x05
+#define MSC_MAX 0x07
+#define MSC_CNT (MSC_MAX+1)
+
+/*
+ * LEDs
+ */
+
+#define LED_NUML 0x00
+#define LED_CAPSL 0x01
+#define LED_SCROLLL 0x02
+#define LED_COMPOSE 0x03
+#define LED_KANA 0x04
+#define LED_SLEEP 0x05
+#define LED_SUSPEND 0x06
+#define LED_MUTE 0x07
+#define LED_MISC 0x08
+#define LED_MAIL 0x09
+#define LED_CHARGING 0x0a
+#define LED_MAX 0x0f
+#define LED_CNT (LED_MAX+1)
+
+/*
+ * Autorepeat values
+ */
+
+#define REP_DELAY 0x00
+#define REP_PERIOD 0x01
+#define REP_MAX 0x01
+#define REP_CNT (REP_MAX+1)
+
+/*
+ * Sounds
+ */
+
+#define SND_CLICK 0x00
+#define SND_BELL 0x01
+#define SND_TONE 0x02
+#define SND_MAX 0x07
+#define SND_CNT (SND_MAX+1)
+
+#endif
--- /dev/null
+/*
+ *
+ * This header provides constants for the phy framework
+ *
+ * Copyright (C) 2014 STMicroelectronics
+ * Author: Gabriel Fernandez <gabriel.fernandez@st.com>
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#ifndef _DT_BINDINGS_PHY
+#define _DT_BINDINGS_PHY
+
+#define PHY_NONE 0
+#define PHY_TYPE_SATA 1
+#define PHY_TYPE_PCIE 2
+#define PHY_TYPE_USB2 3
+#define PHY_TYPE_USB3 4
+
+#endif /* _DT_BINDINGS_PHY */
uint16_t *password);
};
+#define EFI_GOP_GUID \
+ EFI_GUID(0x9042a9de, 0x23dc, 0x4a38, \
+ 0x96, 0xfb, 0x7a, 0xde, 0xd0, 0x80, 0x51, 0x6a)
+
+#define EFI_GOT_RGBA8 0
+#define EFI_GOT_BGRA8 1
+#define EFI_GOT_BITMASK 2
+
+struct efi_gop_mode_info
+{
+ u32 version;
+ u32 width;
+ u32 height;
+ u32 pixel_format;
+ u32 pixel_bitmask[4];
+ u32 pixels_per_scanline;
+};
+
+struct efi_gop_mode
+{
+ u32 max_mode;
+ u32 mode;
+ struct efi_gop_mode_info *info;
+ unsigned long info_size;
+ efi_physical_addr_t fb_base;
+ unsigned long fb_size;
+};
+
+#define EFI_BLT_VIDEO_FILL 0
+#define EFI_BLT_VIDEO_TO_BLT_BUFFER 1
+#define EFI_BLT_BUFFER_TO_VIDEO 2
+#define EFI_BLT_VIDEO_TO_VIDEO 3
+
+struct efi_gop
+{
+ efi_status_t (EFIAPI *query_mode)(struct efi_gop *this, u32 mode_number,
+ unsigned long *size_of_info,
+ struct efi_gop_mode_info **info);
+ efi_status_t (EFIAPI *set_mode)(struct efi_gop *this, u32 mode_number);
+ efi_status_t (EFIAPI *blt)(struct efi_gop *this, void *buffer,
+ unsigned long operation, unsigned long sx,
+ unsigned long sy, unsigned long dx,
+ unsigned long dy, unsigned long width,
+ unsigned long height, unsigned long delta);
+ struct efi_gop_mode *mode;
+};
+
#endif
/* Called by bootefi to make all disk storage accessible as EFI objects */
int efi_disk_register(void);
+/* Called by bootefi to make GOP (graphical) interface available */
+int efi_gop_register(void);
/*
* Stub implementation for a protocol opener that just returns the handle as
* interface
*/
int fdt_fixup_display(void *blob, const char *path, const char *display);
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+#if defined(CONFIG_USB_EHCI_FSL) || defined(CONFIG_USB_XHCI_FSL)
void fdt_fixup_dr_usb(void *blob, bd_t *bd);
#else
static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {}
-#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
+#endif /* defined(CONFIG_USB_EHCI_FSL) || defined(CONFIG_USB_XHCI_FSL) */
#if defined(CONFIG_SYS_FSL_SEC_COMPAT)
void fdt_fixup_crypto_node(void *blob, int sec_rev);
#define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */
#define FLASH_S29GL128N 0x00F1 /* Spansion S29GL128N */
-#define FLASH_STM32F4 0x00F2 /* STM32F4 Embedded Flash */
+#define FLASH_STM32 0x00F2 /* STM32 Embedded Flash */
#define FLASH_STM32F1 0x00F3 /* STM32F1 Embedded Flash */
#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
#define SDRAM_CFG2_FRC_SR 0x80000000
#define SDRAM_CFG2_D_INIT 0x00000010
+#define SDRAM_CFG2_AP_EN 0x00000020
#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
#define SDRAM_CFG2_ODT_NEVER 0
#define SDRAM_CFG2_ODT_ONLY_WRITE 1
#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
#define DDR_CDR2_VREF_RANGE_2 0x00000040
+/* DDR ERR_DISABLE */
+#define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */
+
+/* Mode Registers */
+#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
+#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
+
+
#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
#ifdef CONFIG_SYS_FSL_DDR3L
/* mirrior DIMMs for DDR3 */
unsigned int mirrored_dimm;
unsigned int quad_rank_present;
- unsigned int ap_en; /* address parity enable for RDIMM */
+ unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */
unsigned int x4_en; /* enable x4 devices */
/* Global Timing Parameters */
#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
struct fsl_esdhc_cfg {
-#ifdef CONFIG_FSL_LAYERSCAPE
- u64 esdhc_base;
-#else
- u32 esdhc_base;
-#endif
+ phys_addr_t esdhc_base;
u32 sdhc_clk;
u8 max_bus_width;
struct mmc_config cfg;
#define ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN 0x18
#define ERROR_IE_TABLE_NOT_FOUND 0x19
#define ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN 0x20
+#define ERROR_KEY_TABLE_NOT_FOUND 0x21
#define ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1 0x40
#define ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2 0x80
#define ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD 0x100
"Wrong IE public key len in header" },
{ ERROR_IE_TABLE_NOT_FOUND,
"Information about IE Table missing" },
+ { ERROR_KEY_TABLE_NOT_FOUND,
+ "No Key/ Key Table Found in header"},
{ ERROR_ESBC_CLIENT_MAX, "NULL" }
};
/* Number of SRKH registers */
#define NUM_SRKH_REGS 8
-#ifdef CONFIG_SYS_FSL_SFP_VER_3_2
+#if defined(CONFIG_SYS_FSL_SFP_VER_3_2) || \
+ defined(CONFIG_SYS_FSL_SFP_VER_3_4)
struct ccsr_sfp_regs {
u32 ospr; /* 0x200 */
u32 ospr1; /* 0x204 */
extern struct jobring jr;
-#ifdef CONFIG_KEY_REVOCATION
-/* Srk table and key revocation check */
-#define SRK_FLAG 0x01
-#define UNREVOCABLE_KEY 4
-#define ALIGN_REVOC_KEY 3
-#define MAX_KEY_ENTRIES 4
-#endif
-
/* Barker code size in bytes */
#define ESBC_BARKER_LEN 4 /* barker code length in ESBC uboot client */
/* header */
/* Maximum number of SG entries allowed */
#define MAX_SG_ENTRIES 8
+/* Different Header Struct for LS-CH3 */
+#ifdef CONFIG_ESBC_HDR_LS
+struct fsl_secboot_img_hdr {
+ u8 barker[ESBC_BARKER_LEN]; /* barker code */
+ u32 srk_tbl_off;
+ struct {
+ u8 num_srk;
+ u8 srk_sel;
+ u8 reserve;
+ u8 ie_flag;
+ } len_kr;
+
+ u32 uid_flag;
+
+ u32 psign; /* signature offset */
+ u32 sign_len; /* length of the signature in bytes */
+
+ u64 pimg64; /* 64 bit pointer to ESBC Image */
+ u32 img_size; /* ESBC client image size in bytes */
+ u32 ie_key_sel;
+
+ u32 fsl_uid_0;
+ u32 fsl_uid_1;
+ u32 oem_uid_0;
+ u32 oem_uid_1;
+ u32 oem_uid_2;
+ u32 oem_uid_3;
+ u32 oem_uid_4;
+ u32 reserved1[3];
+};
+
+#ifdef CONFIG_KEY_REVOCATION
+/* Srk table and key revocation check */
+#define UNREVOCABLE_KEY 8
+#define ALIGN_REVOC_KEY 7
+#define MAX_KEY_ENTRIES 8
+#endif
+
+
+#else /* CONFIG_ESBC_HDR_LS */
+
/*
* ESBC uboot client header structure.
* The struct contain the following fields
u32 ie_key_sel;
};
+#ifdef CONFIG_KEY_REVOCATION
+/* Srk table and key revocation check */
+#define SRK_FLAG 0x01
+#define UNREVOCABLE_KEY 4
+#define ALIGN_REVOC_KEY 3
+#define MAX_KEY_ENTRIES 4
+#endif
+
+#endif /* CONFIG_ESBC_HDR_LS */
+
+
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
struct ie_key_table {
u32 key_len;
struct fsl_secboot_sg_table sgtbl[MAX_SG_ENTRIES]; /* SG table */
uintptr_t ehdrloc; /* ESBC Header location */
- uintptr_t img_addr; /* ESBC Image Location */
+ uintptr_t *img_addr_ptr; /* ESBC Image Location */
uint32_t img_size; /* ESBC Image Size */
};
+int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]);
+
int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
- uintptr_t img_loc);
+ uintptr_t *img_addr_ptr);
int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[]);
int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc,
* This uses an x^8 + x^2 + x + 1 polynomial. A table-based algorithm would
* be faster, but for only a few bytes it isn't worth the code size
*
+ * @crc_start: CRC8 start value
* @vptr: Buffer to checksum
* @len: Length of buffer in bytes
* @return CRC8 checksum
*/
-unsigned int crc8(const unsigned char *vptr, int len);
+unsigned int crc8(unsigned int crc_start, const unsigned char *vptr, int len);
#endif
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
-#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#elif defined(CONFIG_LS2080A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
int eth_getenv_enetaddr(const char *name, uchar *enetaddr);
int eth_setenv_enetaddr(const char *name, const uchar *enetaddr);
+/**
+ * eth_setenv_enetaddr_by_index() - set the MAC address envrionment variable
+ *
+ * This sets up an environment variable with the given MAC address (@enetaddr).
+ * The environment variable to be set is defined by <@base_name><@index>addr.
+ * If @index is 0 it is omitted. For common Ethernet this means ethaddr,
+ * eth1addr, etc.
+ *
+ * @base_name: Base name for variable, typically "eth"
+ * @index: Index of interface being updated (>=0)
+ * @enetaddr: Pointer to MAC address to put into the variable
+ * @return 0 if OK, other value on error
+ */
+int eth_setenv_enetaddr_by_index(const char *base_name, int index,
+ uchar *enetaddr);
+
+
/*
* Get the hardware address for an ethernet interface .
* Args:
#define PROT_ARP 0x0806 /* IP ARP protocol */
#define PROT_RARP 0x8035 /* IP ARP protocol */
#define PROT_VLAN 0x8100 /* IEEE 802.1q protocol */
+#define PROT_IPV6 0x86dd /* IPv6 over bluebook */
+#define PROT_PPP_SES 0x8864 /* PPPoE session messages */
#define IPPROTO_ICMP 1 /* Internet Control Message Protocol */
#define IPPROTO_UDP 17 /* User Datagram Protocol */
*/
#ifdef CONFIG_SPL_BUILD
# define part_print_ptr(x) NULL
-# if defined(CONFIG_SPL_EXT_SUPPORT) || \
+# if defined(CONFIG_SPL_EXT_SUPPORT) || defined(CONFIG_SPL_FAT_SUPPORT) || \
defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION)
# define part_get_info_ptr(x) x
# else
extern void pci_register_hose(struct pci_controller* hose);
extern struct pci_controller* pci_bus_to_hose(int bus);
extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
+extern struct pci_controller *pci_get_hose_head(void);
extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
extern int pci_hose_scan(struct pci_controller *hose);
int phy_teranetics_init(void);
int phy_ti_init(void);
int phy_vitesse_init(void);
+int phy_xilinx_init(void);
int board_phy_config(struct phy_device *phydev);
int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
b transfer_to_handler
#define STD_EXCEPTION(n, label, hdlr) \
+.align 4; \
label: \
EXCEPTION_PROLOG(SRR0, SRR1); \
addi r3,r1,STACK_FRAME_OVERHEAD; \
EXC_XFER_TEMPLATE(n, label, hdlr, MSR_KERNEL, NOCOPY) \
#define CRIT_EXCEPTION(n, label, hdlr) \
+.align 4; \
label: \
EXCEPTION_PROLOG(CSRR0, CSRR1); \
addi r3,r1,STACK_FRAME_OVERHEAD; \
MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \
#define MCK_EXCEPTION(n, label, hdlr) \
+.align 4; \
label: \
EXCEPTION_PROLOG(MCSRR0, MCSRR1); \
addi r3,r1,STACK_FRAME_OVERHEAD; \
--- /dev/null
+#ifndef _SPMI_SPMI_H
+#define _SPMI_SPMI_H
+
+/**
+ * struct dm_spmi_ops - SPMI device I/O interface
+ *
+ * Should be implemented by UCLASS_SPMI device drivers. The standard
+ * device operations provides the I/O interface for it's childs.
+ *
+ * @read: read register 'reg' of slave 'usid' and peripheral 'pid'
+ * @write: write register 'reg' of slave 'usid' and peripheral 'pid'
+ *
+ * Each register is 8-bit, both read and write can return negative values
+ * on error.
+ */
+struct dm_spmi_ops {
+ int (*read)(struct udevice *dev, int usid, int pid, int reg);
+ int (*write)(struct udevice *dev, int usid, int pid, int reg,
+ uint8_t value);
+};
+
+/**
+ * spmi_reg_read() - read a register from specific slave/peripheral
+ *
+ * @dev: SPMI bus to read
+ * @usid SlaveID
+ * @pid Peripheral ID
+ * @reg: Register to read
+ * @return value read on success or negative value of errno.
+ */
+int spmi_reg_read(struct udevice *dev, int usid, int pid, int reg);
+
+/**
+ * spmi_reg_write() - write a register of specific slave/peripheral
+ *
+ * @dev: SPMI bus to write
+ * @usid SlaveID
+ * @pid Peripheral ID
+ * @reg: Register to write
+ * @value: Value to write
+ * @return 0 on success or negative value of errno.
+ */
+int spmi_reg_write(struct udevice *dev, int usid, int pid, int reg,
+ uint8_t value);
+
+#endif
int string_langid; /* language ID for strings */
int (*irq_handle)(struct usb_device *dev);
unsigned long irq_status;
- int irq_act_len; /* transfered bytes */
+ int irq_act_len; /* transferred bytes */
void *privptr;
/*
* Child devices - if this is a hub device
*/
unsigned long status;
unsigned long int_pending; /* 1 bit per ep, used by int_queue */
- int act_len; /* transfered bytes */
+ int act_len; /* transferred bytes */
int maxchild; /* Number of ports if hub */
int portnr; /* Port number, 1=first */
#ifndef CONFIG_DM_USB
struct usb_hub_device {
struct usb_device *pusb_dev;
struct usb_hub_descriptor desc;
+
+ ulong connect_timeout; /* Device connection timeout in ms */
+ ulong query_delay; /* Device query delay in ms */
+ int overcurrent_count[USB_MAXCHILDREN]; /* Over-current counter */
};
#ifdef CONFIG_DM_USB
--- /dev/null
+/*
+ * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc
+ * Copyright (c) 2005 MontaVista Software
+ * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _EHCI_CI_H
+#define _EHCI_CI_H
+
+#include <asm/processor.h>
+
+#define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */
+
+/* Global offsets */
+#define FSL_SKIP_PCI 0x100
+
+/* offsets for the non-ehci registers in the FSL SOC USB controller */
+#define FSL_SOC_USB_ULPIVP 0x170
+#define FSL_SOC_USB_PORTSC1 0x184
+#define PORT_PTS_MSK (3 << 30)
+#define PORT_PTS_UTMI (0 << 30)
+#define PORT_PTS_ULPI (2 << 30)
+#define PORT_PTS_SERIAL (3 << 30)
+#define PORT_PTS_PTW (1 << 28)
+#define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */
+#define PORT_PTS_PHCD (1 << 23)
+#define PORT_PP (1 << 12)
+#define PORT_PR (1 << 8)
+
+/* USBMODE Register bits */
+#define CM_IDLE (0 << 0)
+#define CM_RESERVED (1 << 0)
+#define CM_DEVICE (2 << 0)
+#define CM_HOST (3 << 0)
+#define ES_BE (1 << 2) /* Big Endian Select, default is LE */
+#define USBMODE_RESERVED_2 (0 << 2)
+#define SLOM (1 << 3)
+#define SDIS (1 << 4)
+
+/* CONTROL Register bits */
+#define ULPI_INT_EN (1 << 0)
+#define WU_INT_EN (1 << 1)
+#define USB_EN (1 << 2)
+#define LSF_EN (1 << 3)
+#define KEEP_OTG_ON (1 << 4)
+#define OTG_PORT (1 << 5)
+#define REFSEL_12MHZ (0 << 6)
+#define REFSEL_16MHZ (1 << 6)
+#define REFSEL_48MHZ (2 << 6)
+#define PLL_RESET (1 << 8)
+#define UTMI_PHY_EN (1 << 9)
+#define PHY_CLK_SEL_UTMI (0 << 10)
+#define PHY_CLK_SEL_ULPI (1 << 10)
+#define CLKIN_SEL_USB_CLK (0 << 11)
+#define CLKIN_SEL_USB_CLK2 (1 << 11)
+#define CLKIN_SEL_SYS_CLK (2 << 11)
+#define CLKIN_SEL_SYS_CLK2 (3 << 11)
+#define RESERVED_18 (0 << 13)
+#define RESERVED_17 (0 << 14)
+#define RESERVED_16 (0 << 15)
+#define WU_INT (1 << 16)
+#define PHY_CLK_VALID (1 << 17)
+
+#define FSL_SOC_USB_PORTSC2 0x188
+
+/* OTG Status Control Register bits */
+#define FSL_SOC_USB_OTGSC 0x1a4
+#define CTRL_VBUS_DISCHARGE (0x1<<0)
+#define CTRL_VBUS_CHARGE (0x1<<1)
+#define CTRL_OTG_TERMINATION (0x1<<3)
+#define CTRL_DATA_PULSING (0x1<<4)
+#define CTRL_ID_PULL_EN (0x1<<5)
+#define HA_DATA_PULSE (0x1<<6)
+#define HA_BA (0x1<<7)
+#define STS_USB_ID (0x1<<8)
+#define STS_A_VBUS_VALID (0x1<<9)
+#define STS_A_SESSION_VALID (0x1<<10)
+#define STS_B_SESSION_VALID (0x1<<11)
+#define STS_B_SESSION_END (0x1<<12)
+#define STS_1MS_TOGGLE (0x1<<13)
+#define STS_DATA_PULSING (0x1<<14)
+#define INTSTS_USB_ID (0x1<<16)
+#define INTSTS_A_VBUS_VALID (0x1<<17)
+#define INTSTS_A_SESSION_VALID (0x1<<18)
+#define INTSTS_B_SESSION_VALID (0x1<<19)
+#define INTSTS_B_SESSION_END (0x1<<20)
+#define INTSTS_1MS (0x1<<21)
+#define INTSTS_DATA_PULSING (0x1<<22)
+#define INTR_USB_ID_EN (0x1<<24)
+#define INTR_A_VBUS_VALID_EN (0x1<<25)
+#define INTR_A_SESSION_VALID_EN (0x1<<26)
+#define INTR_B_SESSION_VALID_EN (0x1<<27)
+#define INTR_B_SESSION_END_EN (0x1<<28)
+#define INTR_1MS_TIMER_EN (0x1<<29)
+#define INTR_DATA_PULSING_EN (0x1<<30)
+#define INTSTS_MASK (0x00ff0000)
+
+#define INTERRUPT_ENABLE_BITS_MASK \
+ (INTR_USB_ID_EN | \
+ INTR_1MS_TIMER_EN | \
+ INTR_A_VBUS_VALID_EN | \
+ INTR_A_SESSION_VALID_EN | \
+ INTR_B_SESSION_VALID_EN | \
+ INTR_B_SESSION_END_EN | \
+ INTR_DATA_PULSING_EN)
+
+#define INTERRUPT_STATUS_BITS_MASK \
+ (INTSTS_USB_ID | \
+ INTR_1MS_TIMER_EN | \
+ INTSTS_A_VBUS_VALID | \
+ INTSTS_A_SESSION_VALID | \
+ INTSTS_B_SESSION_VALID | \
+ INTSTS_B_SESSION_END | \
+ INTSTS_DATA_PULSING)
+
+#define FSL_SOC_USB_USBMODE 0x1a8
+
+#define USBGENCTRL 0x200 /* NOTE: big endian */
+#define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */
+#define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/
+#define GC_PPP (1 << 3) /* Port Power Polarity */
+#define GC_PFP (1 << 2) /* Power Fault Polarity */
+#define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */
+#define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */
+
+#define ISIPHYCTRL 0x204 /* NOTE: big endian */
+#define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */
+#define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */
+#define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */
+#define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */
+#define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */
+
+#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
+#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
+#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
+#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
+#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
+#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
+#define SNOOP_SIZE_2GB 0x1e
+
+/* System Clock Control Register */
+#define MPC83XX_SCCR_USB_MASK 0x00f00000
+#define MPC83XX_SCCR_USB_DRCM_11 0x00300000
+#define MPC83XX_SCCR_USB_DRCM_01 0x00100000
+#define MPC83XX_SCCR_USB_DRCM_10 0x00200000
+
+#if defined(CONFIG_MPC83xx)
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR
+#if defined(CONFIG_MPC834x)
+#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR
+#else
+#define CONFIG_SYS_FSL_USB2_ADDR 0
+#endif
+#elif defined(CONFIG_MPC85xx)
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR
+#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR
+#elif defined(CONFIG_MPC512X)
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
+#define CONFIG_SYS_FSL_USB2_ADDR 0
+#elif defined(CONFIG_LS102XA)
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR
+#define CONFIG_SYS_FSL_USB2_ADDR 0
+#endif
+
+/*
+ * Increasing TX FIFO threshold value from 2 to 4 decreases
+ * data burst rate with which data packets are posted from the TX
+ * latency FIFO to compensate for latencies in DDR pipeline during DMA
+ */
+#define TXFIFOTHRESH 4
+
+/*
+ * USB Registers
+ */
+struct usb_ehci {
+ u32 id; /* 0x000 - Identification register */
+ u32 hwgeneral; /* 0x004 - General hardware parameters */
+ u32 hwhost; /* 0x008 - Host hardware parameters */
+ u32 hwdevice; /* 0x00C - Device hardware parameters */
+ u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */
+ u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */
+ u8 res1[0x68];
+ u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */
+ u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */
+ u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */
+ u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */
+ u32 sbuscfg; /* 0x090 - System Bus Interface Control */
+ u32 sbusstatus; /* 0x094 - System Bus Interface Status */
+ u32 sbusmode; /* 0x098 - System Bus Interface Mode */
+ u32 genconfig; /* 0x09C - USB Core Configuration */
+ u32 genconfig2; /* 0x0A0 - USB Core Configuration 2 */
+ u8 res2[0x5c];
+ u8 caplength; /* 0x100 - Capability Register Length */
+ u8 res3[0x1];
+ u16 hciversion; /* 0x102 - Host Interface Version */
+ u32 hcsparams; /* 0x104 - Host Structural Parameters */
+ u32 hccparams; /* 0x108 - Host Capability Parameters */
+ u8 res4[0x14];
+ u32 dciversion; /* 0x120 - Device Interface Version */
+ u32 dciparams; /* 0x124 - Device Controller Params */
+ u8 res5[0x18];
+ u32 usbcmd; /* 0x140 - USB Command */
+ u32 usbsts; /* 0x144 - USB Status */
+ u32 usbintr; /* 0x148 - USB Interrupt Enable */
+ u32 frindex; /* 0x14C - USB Frame Index */
+ u8 res6[0x4];
+ u32 perlistbase; /* 0x154 - Periodic List Base
+ - USB Device Address */
+ u32 ep_list_addr; /* 0x158 - Next Asynchronous List
+ - End Point Address */
+ u8 res7[0x4];
+ u32 burstsize; /* 0x160 - Programmable Burst Size */
+#define FSL_EHCI_TXPBURST(X) ((X) << 8)
+#define FSL_EHCI_RXPBURST(X) (X)
+ u32 txfilltuning; /* 0x164 - Host TT Transmit
+ pre-buffer packet tuning */
+ u8 res8[0x8];
+ u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */
+ u8 res9[0xc];
+ u32 config_flag; /* 0x180 - Configured Flag Register */
+ u32 portsc; /* 0x184 - Port status/control */
+ u8 res10[0x1C];
+ u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */
+ u32 usbmode; /* 0x1a8 - USB Device Mode */
+ u32 epsetupstat; /* 0x1ac - End Point Setup Status */
+ u32 epprime; /* 0x1b0 - End Point Init Status */
+ u32 epflush; /* 0x1b4 - End Point De-initlialize */
+ u32 epstatus; /* 0x1b8 - End Point Status */
+ u32 epcomplete; /* 0x1bc - End Point Complete */
+ u32 epctrl0; /* 0x1c0 - End Point Control 0 */
+ u32 epctrl1; /* 0x1c4 - End Point Control 1 */
+ u32 epctrl2; /* 0x1c8 - End Point Control 2 */
+ u32 epctrl3; /* 0x1cc - End Point Control 3 */
+ u32 epctrl4; /* 0x1d0 - End Point Control 4 */
+ u32 epctrl5; /* 0x1d4 - End Point Control 5 */
+ u8 res11[0x28];
+ u32 usbgenctrl; /* 0x200 - USB General Control */
+ u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */
+ u8 res12[0x1F8];
+ u32 snoop1; /* 0x400 - Snoop 1 */
+ u32 snoop2; /* 0x404 - Snoop 2 */
+ u32 age_cnt_limit; /* 0x408 - Age Count Threshold */
+ u32 prictrl; /* 0x40c - Priority Control */
+ u32 sictrl; /* 0x410 - System Interface Control */
+ u8 res13[0xEC];
+ u32 control; /* 0x500 - Control */
+ u8 res14[0xafc];
+};
+
+/*
+ * For MXC SOCs
+ */
+
+/* values for portsc field */
+#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
+#define MXC_EHCI_FORCE_FS (1 << 24)
+#define MXC_EHCI_UTMI_8BIT (0 << 28)
+#define MXC_EHCI_UTMI_16BIT (1 << 28)
+#define MXC_EHCI_SERIAL (1 << 29)
+#define MXC_EHCI_MODE_UTMI (0 << 30)
+#define MXC_EHCI_MODE_PHILIPS (1 << 30)
+#define MXC_EHCI_MODE_ULPI (2 << 30)
+#define MXC_EHCI_MODE_SERIAL (3 << 30)
+
+/* values for flags field */
+#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
+#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
+#define MXC_EHCI_INTERFACE_MASK (0xf)
+
+#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
+#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6)
+#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7)
+#define MXC_EHCI_TTL_ENABLED (1 << 8)
+
+#define MXC_EHCI_INTERNAL_PHY (1 << 9)
+#define MXC_EHCI_IPPUE_DOWN (1 << 10)
+#define MXC_EHCI_IPPUE_UP (1 << 11)
+
+int usb_phy_mode(int port);
+/* Board-specific initialization */
+int board_ehci_hcd_init(int port);
+int board_usb_phy_mode(int port);
+
+#endif /* _EHCI_CI_H */
+++ /dev/null
-/*
- * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc
- * Copyright (c) 2005 MontaVista Software
- * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _EHCI_FSL_H
-#define _EHCI_FSL_H
-
-#include <asm/processor.h>
-
-#define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */
-
-/* Global offsets */
-#define FSL_SKIP_PCI 0x100
-
-/* offsets for the non-ehci registers in the FSL SOC USB controller */
-#define FSL_SOC_USB_ULPIVP 0x170
-#define FSL_SOC_USB_PORTSC1 0x184
-#define PORT_PTS_MSK (3 << 30)
-#define PORT_PTS_UTMI (0 << 30)
-#define PORT_PTS_ULPI (2 << 30)
-#define PORT_PTS_SERIAL (3 << 30)
-#define PORT_PTS_PTW (1 << 28)
-#define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */
-#define PORT_PTS_PHCD (1 << 23)
-#define PORT_PP (1 << 12)
-#define PORT_PR (1 << 8)
-
-/* USBMODE Register bits */
-#define CM_IDLE (0 << 0)
-#define CM_RESERVED (1 << 0)
-#define CM_DEVICE (2 << 0)
-#define CM_HOST (3 << 0)
-#define ES_BE (1 << 2) /* Big Endian Select, default is LE */
-#define USBMODE_RESERVED_2 (0 << 2)
-#define SLOM (1 << 3)
-#define SDIS (1 << 4)
-
-/* CONTROL Register bits */
-#define ULPI_INT_EN (1 << 0)
-#define WU_INT_EN (1 << 1)
-#define USB_EN (1 << 2)
-#define LSF_EN (1 << 3)
-#define KEEP_OTG_ON (1 << 4)
-#define OTG_PORT (1 << 5)
-#define REFSEL_12MHZ (0 << 6)
-#define REFSEL_16MHZ (1 << 6)
-#define REFSEL_48MHZ (2 << 6)
-#define PLL_RESET (1 << 8)
-#define UTMI_PHY_EN (1 << 9)
-#define PHY_CLK_SEL_UTMI (0 << 10)
-#define PHY_CLK_SEL_ULPI (1 << 10)
-#define CLKIN_SEL_USB_CLK (0 << 11)
-#define CLKIN_SEL_USB_CLK2 (1 << 11)
-#define CLKIN_SEL_SYS_CLK (2 << 11)
-#define CLKIN_SEL_SYS_CLK2 (3 << 11)
-#define RESERVED_18 (0 << 13)
-#define RESERVED_17 (0 << 14)
-#define RESERVED_16 (0 << 15)
-#define WU_INT (1 << 16)
-#define PHY_CLK_VALID (1 << 17)
-
-#define FSL_SOC_USB_PORTSC2 0x188
-
-/* OTG Status Control Register bits */
-#define FSL_SOC_USB_OTGSC 0x1a4
-#define CTRL_VBUS_DISCHARGE (0x1<<0)
-#define CTRL_VBUS_CHARGE (0x1<<1)
-#define CTRL_OTG_TERMINATION (0x1<<3)
-#define CTRL_DATA_PULSING (0x1<<4)
-#define CTRL_ID_PULL_EN (0x1<<5)
-#define HA_DATA_PULSE (0x1<<6)
-#define HA_BA (0x1<<7)
-#define STS_USB_ID (0x1<<8)
-#define STS_A_VBUS_VALID (0x1<<9)
-#define STS_A_SESSION_VALID (0x1<<10)
-#define STS_B_SESSION_VALID (0x1<<11)
-#define STS_B_SESSION_END (0x1<<12)
-#define STS_1MS_TOGGLE (0x1<<13)
-#define STS_DATA_PULSING (0x1<<14)
-#define INTSTS_USB_ID (0x1<<16)
-#define INTSTS_A_VBUS_VALID (0x1<<17)
-#define INTSTS_A_SESSION_VALID (0x1<<18)
-#define INTSTS_B_SESSION_VALID (0x1<<19)
-#define INTSTS_B_SESSION_END (0x1<<20)
-#define INTSTS_1MS (0x1<<21)
-#define INTSTS_DATA_PULSING (0x1<<22)
-#define INTR_USB_ID_EN (0x1<<24)
-#define INTR_A_VBUS_VALID_EN (0x1<<25)
-#define INTR_A_SESSION_VALID_EN (0x1<<26)
-#define INTR_B_SESSION_VALID_EN (0x1<<27)
-#define INTR_B_SESSION_END_EN (0x1<<28)
-#define INTR_1MS_TIMER_EN (0x1<<29)
-#define INTR_DATA_PULSING_EN (0x1<<30)
-#define INTSTS_MASK (0x00ff0000)
-
-/* USBCMD Bits of interest */
-#define EHCI_FSL_USBCMD_RST (1 << 1)
-#define EHCI_FSL_USBCMD_RS (1 << 0)
-
-#define INTERRUPT_ENABLE_BITS_MASK \
- (INTR_USB_ID_EN | \
- INTR_1MS_TIMER_EN | \
- INTR_A_VBUS_VALID_EN | \
- INTR_A_SESSION_VALID_EN | \
- INTR_B_SESSION_VALID_EN | \
- INTR_B_SESSION_END_EN | \
- INTR_DATA_PULSING_EN)
-
-#define INTERRUPT_STATUS_BITS_MASK \
- (INTSTS_USB_ID | \
- INTR_1MS_TIMER_EN | \
- INTSTS_A_VBUS_VALID | \
- INTSTS_A_SESSION_VALID | \
- INTSTS_B_SESSION_VALID | \
- INTSTS_B_SESSION_END | \
- INTSTS_DATA_PULSING)
-
-#define FSL_SOC_USB_USBMODE 0x1a8
-
-#define USBGENCTRL 0x200 /* NOTE: big endian */
-#define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */
-#define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/
-#define GC_PPP (1 << 3) /* Port Power Polarity */
-#define GC_PFP (1 << 2) /* Power Fault Polarity */
-#define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */
-#define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */
-
-#define ISIPHYCTRL 0x204 /* NOTE: big endian */
-#define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */
-#define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */
-#define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */
-#define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */
-#define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */
-
-#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
-#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
-#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
-#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
-#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
-#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
-#define SNOOP_SIZE_2GB 0x1e
-
-/* System Clock Control Register */
-#define MPC83XX_SCCR_USB_MASK 0x00f00000
-#define MPC83XX_SCCR_USB_DRCM_11 0x00300000
-#define MPC83XX_SCCR_USB_DRCM_01 0x00100000
-#define MPC83XX_SCCR_USB_DRCM_10 0x00200000
-
-#if defined(CONFIG_MPC83xx)
-#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR
-#if defined(CONFIG_MPC834x)
-#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR
-#else
-#define CONFIG_SYS_FSL_USB2_ADDR 0
-#endif
-#elif defined(CONFIG_MPC85xx)
-#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR
-#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR
-#elif defined(CONFIG_MPC512X)
-#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
-#define CONFIG_SYS_FSL_USB2_ADDR 0
-#elif defined(CONFIG_LS102XA)
-#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR
-#define CONFIG_SYS_FSL_USB2_ADDR 0
-#endif
-
-/*
- * Increasing TX FIFO threshold value from 2 to 4 decreases
- * data burst rate with which data packets are posted from the TX
- * latency FIFO to compensate for latencies in DDR pipeline during DMA
- */
-#define TXFIFOTHRESH 4
-
-/*
- * USB Registers
- */
-struct usb_ehci {
- u32 id; /* 0x000 - Identification register */
- u32 hwgeneral; /* 0x004 - General hardware parameters */
- u32 hwhost; /* 0x008 - Host hardware parameters */
- u32 hwdevice; /* 0x00C - Device hardware parameters */
- u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */
- u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */
- u8 res1[0x68];
- u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */
- u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */
- u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */
- u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */
- u32 sbuscfg; /* 0x090 - System Bus Interface Control */
- u8 res2[0x6C];
- u8 caplength; /* 0x100 - Capability Register Length */
- u8 res3[0x1];
- u16 hciversion; /* 0x102 - Host Interface Version */
- u32 hcsparams; /* 0x104 - Host Structural Parameters */
- u32 hccparams; /* 0x108 - Host Capability Parameters */
- u8 res4[0x14];
- u32 dciversion; /* 0x120 - Device Interface Version */
- u32 dciparams; /* 0x124 - Device Controller Params */
- u8 res5[0x18];
- u32 usbcmd; /* 0x140 - USB Command */
- u32 usbsts; /* 0x144 - USB Status */
- u32 usbintr; /* 0x148 - USB Interrupt Enable */
- u32 frindex; /* 0x14C - USB Frame Index */
- u8 res6[0x4];
- u32 perlistbase; /* 0x154 - Periodic List Base
- - USB Device Address */
- u32 ep_list_addr; /* 0x158 - Next Asynchronous List
- - End Point Address */
- u8 res7[0x4];
- u32 burstsize; /* 0x160 - Programmable Burst Size */
-#define FSL_EHCI_TXPBURST(X) ((X) << 8)
-#define FSL_EHCI_RXPBURST(X) (X)
- u32 txfilltuning; /* 0x164 - Host TT Transmit
- pre-buffer packet tuning */
- u8 res8[0x8];
- u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */
- u8 res9[0xc];
- u32 config_flag; /* 0x180 - Configured Flag Register */
- u32 portsc; /* 0x184 - Port status/control */
- u8 res10[0x1C];
- u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */
- u32 usbmode; /* 0x1a8 - USB Device Mode */
- u32 epsetupstat; /* 0x1ac - End Point Setup Status */
- u32 epprime; /* 0x1b0 - End Point Init Status */
- u32 epflush; /* 0x1b4 - End Point De-initlialize */
- u32 epstatus; /* 0x1b8 - End Point Status */
- u32 epcomplete; /* 0x1bc - End Point Complete */
- u32 epctrl0; /* 0x1c0 - End Point Control 0 */
- u32 epctrl1; /* 0x1c4 - End Point Control 1 */
- u32 epctrl2; /* 0x1c8 - End Point Control 2 */
- u32 epctrl3; /* 0x1cc - End Point Control 3 */
- u32 epctrl4; /* 0x1d0 - End Point Control 4 */
- u32 epctrl5; /* 0x1d4 - End Point Control 5 */
- u8 res11[0x28];
- u32 usbgenctrl; /* 0x200 - USB General Control */
- u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */
- u8 res12[0x1F8];
- u32 snoop1; /* 0x400 - Snoop 1 */
- u32 snoop2; /* 0x404 - Snoop 2 */
- u32 age_cnt_limit; /* 0x408 - Age Count Threshold */
- u32 prictrl; /* 0x40c - Priority Control */
- u32 sictrl; /* 0x410 - System Interface Control */
- u8 res13[0xEC];
- u32 control; /* 0x500 - Control */
- u8 res14[0xafc];
-};
-
-/*
- * For MXC SOCs
- */
-
-/* values for portsc field */
-#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
-#define MXC_EHCI_FORCE_FS (1 << 24)
-#define MXC_EHCI_UTMI_8BIT (0 << 28)
-#define MXC_EHCI_UTMI_16BIT (1 << 28)
-#define MXC_EHCI_SERIAL (1 << 29)
-#define MXC_EHCI_MODE_UTMI (0 << 30)
-#define MXC_EHCI_MODE_PHILIPS (1 << 30)
-#define MXC_EHCI_MODE_ULPI (2 << 30)
-#define MXC_EHCI_MODE_SERIAL (3 << 30)
-
-/* values for flags field */
-#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
-#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
-#define MXC_EHCI_INTERFACE_MASK (0xf)
-
-#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
-#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6)
-#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7)
-#define MXC_EHCI_TTL_ENABLED (1 << 8)
-
-#define MXC_EHCI_INTERNAL_PHY (1 << 9)
-#define MXC_EHCI_IPPUE_DOWN (1 << 10)
-#define MXC_EHCI_IPPUE_UP (1 << 11)
-
-int usb_phy_mode(int port);
-/* Board-specific initialization */
-int board_ehci_hcd_init(int port);
-int board_usb_phy_mode(int port);
-
-#endif /* _EHCI_FSL_H */
* be extended from this structure
*/
struct ulpi_viewport {
- u32 viewport_addr;
+ uintptr_t viewport_addr;
u32 port_num;
};
/*
* Write to the ULPI PHY register via the viewport.
* @reg - the ULPI register (one of the fields in struct ulpi_regs).
+ * Due to ULPI design, only 8 lsb of address are used.
* @value - the value - only 8 lower bits are used, others ignored.
*
* returns 0 on success, ULPI_ERROR on failure.
/*
* Read the ULPI PHY register content via the viewport.
* @reg - the ULPI register (one of the fields in struct ulpi_regs).
+ * Due to ULPI design, only 8 lsb of address are used.
*
* returns register content on success, ULPI_ERROR on failure.
*/
depends on HAVE_PRIVATE_LIBGCC
help
This option allows you to use the built-in libgcc implementation
- of U-Boot instead of the one privided by the compiler.
+ of U-Boot instead of the one provided by the compiler.
If unsure, say N.
config SYS_HZ
#include "linux/crc8.h"
-unsigned int crc8(const unsigned char *vptr, int len)
+#define POLY (0x1070U << 3)
+
+static unsigned char _crc8(unsigned short data)
{
- const unsigned char *data = vptr;
- unsigned int crc = 0;
- int i, j;
-
- for (j = len; j; j--, data++) {
- crc ^= (*data << 8);
- for (i = 8; i; i--) {
- if (crc & 0x8000)
- crc ^= (0x1070 << 3);
- crc <<= 1;
- }
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ if (data & 0x8000)
+ data = data ^ POLY;
+ data = data << 1;
}
- return (crc >> 8) & 0xff;
+ return (unsigned char)(data >> 8);
+}
+
+unsigned int crc8(unsigned int crc, const unsigned char *vptr, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ crc = _crc8((crc ^ vptr[i]) << 8);
+
+ return crc;
}
void putc(const char ch)
{
+ if (ch == '\n')
+ putc('\r');
+
if (use_uart) {
NS16550_t com_port = (NS16550_t)0x3f8;
} else {
efi_putc(global_priv, ch);
}
- if (ch == '\n')
- putc('\r');
}
void puts(const char *str)
obj-y += efi_image_loader.o efi_boottime.o efi_runtime.o efi_console.o
obj-y += efi_memory.o
+obj-$(CONFIG_LCD) += efi_gop.o
obj-$(CONFIG_PARTITIONS) += efi_disk.o
static efi_status_t EFIAPI efi_allocate_pool(int pool_type, unsigned long size,
void **buffer)
{
- return efi_allocate_pages(0, pool_type, (size + 0xfff) >> 12, (void*)buffer);
+ efi_status_t r;
+
+ EFI_ENTRY("%d, %ld, %p", pool_type, size, buffer);
+ r = efi_allocate_pages(0, pool_type, (size + 0xfff) >> 12, (void*)buffer);
+ return EFI_EXIT(r);
}
static efi_status_t EFIAPI efi_free_pool(void *buffer)
{
- return efi_free_pages((ulong)buffer, 0);
+ efi_status_t r;
+
+ EFI_ENTRY("%p", buffer);
+ r = efi_free_pages((ulong)buffer, 0);
+ return EFI_EXIT(r);
}
/*
efi_guid_t *protocol,
void **protocol_interface)
{
- EFI_ENTRY("%p, %p, %p", handle, protocol, protocol_interface);
return efi_open_protocol(handle, protocol, protocol_interface,
NULL, NULL, 0);
}
--- /dev/null
+/*
+ * EFI application disk support
+ *
+ * Copyright (c) 2016 Alexander Graf
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <efi_loader.h>
+#include <inttypes.h>
+#include <lcd.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const efi_guid_t efi_gop_guid = EFI_GOP_GUID;
+
+struct efi_gop_obj {
+ /* Generic EFI object parent class data */
+ struct efi_object parent;
+ /* EFI Interface callback struct for gop */
+ struct efi_gop ops;
+ /* The only mode we support */
+ struct efi_gop_mode_info info;
+ struct efi_gop_mode mode;
+};
+
+static efi_status_t EFIAPI gop_query_mode(struct efi_gop *this, u32 mode_number,
+ unsigned long *size_of_info,
+ struct efi_gop_mode_info **info)
+{
+ struct efi_gop_obj *gopobj;
+
+ EFI_ENTRY("%p, %x, %p, %p", this, mode_number, size_of_info, info);
+
+ gopobj = container_of(this, struct efi_gop_obj, ops);
+ *size_of_info = sizeof(gopobj->info);
+ *info = &gopobj->info;
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI gop_set_mode(struct efi_gop *this, u32 mode_number)
+{
+ EFI_ENTRY("%p, %x", this, mode_number);
+
+ if (mode_number != 0)
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI gop_blt(struct efi_gop *this, void *buffer,
+ unsigned long operation, unsigned long sx,
+ unsigned long sy, unsigned long dx,
+ unsigned long dy, unsigned long width,
+ unsigned long height, unsigned long delta)
+{
+ int i, j, line_len16, line_len32;
+ void *fb;
+
+ EFI_ENTRY("%p, %p, %lx, %lx, %lx, %lx, %lx, %lx, %lx, %lx", this,
+ buffer, operation, sx, sy, dx, dy, width, height, delta);
+
+ if (operation != EFI_BLT_BUFFER_TO_VIDEO)
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+
+ fb = (void*)gd->fb_base;
+ line_len16 = panel_info.vl_col * sizeof(u16);
+ line_len32 = panel_info.vl_col * sizeof(u32);
+
+ /* Copy the contents line by line */
+
+ switch (panel_info.vl_bpix) {
+ case LCD_COLOR32:
+ for (i = 0; i < height; i++) {
+ u32 *dest = fb + ((i + dy) * line_len32) +
+ (dx * sizeof(u32));
+ u32 *src = buffer + ((i + sy) * line_len32) +
+ (sx * sizeof(u32));
+
+ /* Same color format, just memcpy */
+ memcpy(dest, src, width * sizeof(u32));
+ }
+ break;
+ case LCD_COLOR16:
+ for (i = 0; i < height; i++) {
+ u16 *dest = fb + ((i + dy) * line_len16) +
+ (dx * sizeof(u16));
+ u32 *src = buffer + ((i + sy) * line_len32) +
+ (sx * sizeof(u32));
+
+ /* Convert from rgb888 to rgb565 */
+ for (j = 0; j < width; j++) {
+ u32 rgb888 = src[j];
+ dest[j] = ((((rgb888 >> (16 + 3)) & 0x1f) << 11) |
+ (((rgb888 >> (8 + 2)) & 0x3f) << 5) |
+ (((rgb888 >> (0 + 3)) & 0x1f) << 0));
+ }
+ }
+ break;
+ }
+
+ lcd_sync();
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+/* This gets called from do_bootefi_exec(). */
+int efi_gop_register(void)
+{
+ struct efi_gop_obj *gopobj;
+ int line_len;
+
+ switch (panel_info.vl_bpix) {
+ case LCD_COLOR32:
+ case LCD_COLOR16:
+ break;
+ default:
+ /* So far, we only work in 16 or 32 bit mode */
+ return -1;
+ }
+
+ gopobj = calloc(1, sizeof(*gopobj));
+
+ /* Fill in object data */
+ gopobj->parent.protocols[0].guid = &efi_gop_guid;
+ gopobj->parent.protocols[0].open = efi_return_handle;
+ gopobj->parent.handle = &gopobj->ops;
+ gopobj->ops.query_mode = gop_query_mode;
+ gopobj->ops.set_mode = gop_set_mode;
+ gopobj->ops.blt = gop_blt;
+ gopobj->ops.mode = &gopobj->mode;
+
+ gopobj->mode.max_mode = 1;
+ gopobj->mode.info = &gopobj->info;
+ gopobj->mode.info_size = sizeof(gopobj->info);
+ gopobj->mode.fb_base = gd->fb_base;
+ gopobj->mode.fb_size = lcd_get_size(&line_len);
+
+ gopobj->info.version = 0;
+ gopobj->info.width = panel_info.vl_col;
+ gopobj->info.height = panel_info.vl_row;
+ gopobj->info.pixel_format = EFI_GOT_RGBA8;
+ gopobj->info.pixels_per_scanline = panel_info.vl_col;
+
+ /* Hook up to the device list */
+ list_add_tail(&gopobj->parent.link, &efi_obj_list);
+
+ return 0;
+}
void **protocol_interface, void *agent_handle,
void *controller_handle, uint32_t attributes)
{
- EFI_ENTRY("%p, %p, %p, %p, %p, 0x%x", handle, protocol,
- protocol_interface, agent_handle, controller_handle,
- attributes);
*protocol_interface = handle;
- return EFI_EXIT(EFI_SUCCESS);
+ return EFI_SUCCESS;
}
static void efi_loader_relocate(const IMAGE_BASE_RELOCATION *rel,
#include <malloc.h>
#include <asm/global_data.h>
#include <libfdt_env.h>
+#include <linux/list_sort.h>
#include <inttypes.h>
#include <watchdog.h>
/* This list contains all memory map items */
LIST_HEAD(efi_mem);
+/*
+ * Sorts the memory list from highest address to lowest address
+ *
+ * When allocating memory we should always start from the highest
+ * address chunk, so sort the memory list such that the first list
+ * iterator gets the highest address and goes lower from there.
+ */
+static int efi_mem_cmp(void *priv, struct list_head *a, struct list_head *b)
+{
+ struct efi_mem_list *mema = list_entry(a, struct efi_mem_list, link);
+ struct efi_mem_list *memb = list_entry(b, struct efi_mem_list, link);
+
+ if (mema->desc.physical_start == memb->desc.physical_start)
+ return 0;
+ else if (mema->desc.physical_start < memb->desc.physical_start)
+ return 1;
+ else
+ return -1;
+}
+
+static void efi_mem_sort(void)
+{
+ list_sort(NULL, &efi_mem, efi_mem_cmp);
+}
+
/*
* Unmaps all memory occupied by the carve_desc region from the
* list entry pointed to by map.
/* Add our new map */
list_add_tail(&newlist->link, &efi_mem);
+ /* And make sure memory is listed in descending order */
+ efi_mem_sort();
+
return start;
}
#include <common.h>
#include <physmem.h>
+#include <linux/compiler.h>
-static phys_addr_t __arch_phys_memset(phys_addr_t s, int c, phys_size_t n)
+phys_addr_t __weak arch_phys_memset(phys_addr_t s, int c, phys_size_t n)
{
void *s_ptr = (void *)(uintptr_t)s;
assert(((phys_addr_t)(uintptr_t)(s + n)) == s + n);
return (phys_addr_t)(uintptr_t)memset(s_ptr, c, n);
}
-
-phys_addr_t arch_phys_memset(phys_addr_t s, int c, phys_size_t n)
- __attribute__((weak, alias("__arch_phys_memset")));
retval = -5;
else if (!bootp_match_id(net_read_u32(&bp->bp_id)))
retval = -6;
+ else if (memcmp(bp->bp_chaddr, net_ethaddr, HWL_ETHER) != 0)
+ retval = -7;
debug("Filtering pkt = %d\n", retval);
obj-$(CONFIG_MPC83xx) += cpu/mpc83xx/
obj-$(CONFIG_8xx) += cpu/mpc8xx/
obj-$(CONFIG_4xx) += cpu/ppc4xx/
-ifneq ($(filter lwmon lwmon5 netta pdm360ng,$(BOARD)),)
+ifneq ($(filter lwmon5 pdm360ng,$(BOARD)),)
obj-y += board/$(BOARD)/
endif
+++ /dev/null
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += codec.o dsp.o
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Pantelis Antoniou, Intracom S.A. , panto@intracom.gr
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-/*
- * CODEC test
- *
- * This test verifies the connection and performs a memory test
- * on any connected codec(s). The meat of the work is done
- * in the board specific function.
- */
-
-#include <post.h>
-
-#if CONFIG_POST & CONFIG_SYS_POST_CODEC
-
-extern int board_post_codec(int flags);
-
-int codec_post_test (int flags)
-{
- return board_post_codec(flags);
-}
-
-#endif /* CONFIG_POST & CONFIG_SYS_POST_CODEC */
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Pantelis Antoniou, Intracom S.A. , panto@intracom.gr
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-/*
- * DSP test
- *
- * This test verifies the connection and performs a memory test
- * on any connected DSP(s). The meat of the work is done
- * in the board specific function.
- */
-
-#include <post.h>
-
-#if CONFIG_POST & CONFIG_SYS_POST_DSP
-
-extern int board_post_dsp(int flags);
-
-int dsp_post_test (int flags)
-{
- return board_post_dsp(flags);
-}
-
-#endif /* CONFIG_POST & CONFIG_SYS_POST_DSP */
* Branch instructions: b, bl, bc
*
* The first 2 instructions (b, bl) are verified by jumping
- * to a fixed address and checking whether control was transfered
+ * to a fixed address and checking whether control was transferred
* to that very point. For the bl instruction the value of the
* link register is checked as well (using mfspr).
* To verify the bc instruction various combinations of the BI/BO
"ETHERNET test",
"ethernet",
"This test verifies the ETHERNET operation.",
- POST_RAM | POST_ALWAYS | POST_MANUAL,
+ POST_RAM | POST_ALWAYS,
ðer_post_test,
NULL,
NULL,
"SPI test",
"spi",
"This test verifies the SPI operation.",
- POST_RAM | POST_ALWAYS | POST_MANUAL,
+ POST_RAM | POST_ALWAYS,
&spi_post_test,
NULL,
NULL,
"USB test",
"usb",
"This test verifies the USB operation.",
- POST_RAM | POST_ALWAYS | POST_MANUAL,
+ POST_RAM | POST_ALWAYS,
&usb_post_test,
NULL,
NULL,
"DSP test",
"dsp",
"This test checks any connected DSP(s).",
- POST_RAM | POST_ALWAYS | POST_MANUAL,
+ POST_RAM | POST_ALWAYS,
&dsp_post_test,
NULL,
NULL,
obj-$(CONFIG_TIMER) += timer.o
obj-$(CONFIG_DM_VIDEO) += video.o
obj-$(CONFIG_ADC) += adc.o
+obj-$(CONFIG_SPMI) += spmi.o
endif
--- /dev/null
+/*
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <dm.h>
+#include <dm/device.h>
+#include <dm/root.h>
+#include <dm/test.h>
+#include <dm/util.h>
+#include <power/pmic.h>
+#include <spmi/spmi.h>
+#include <asm/gpio.h>
+#include <test/ut.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Test if bus childs got probed propperly*/
+static int dm_test_spmi_probe(struct unit_test_state *uts)
+{
+ const char *name = "spmi@0";
+ struct udevice *bus, *dev;
+
+ ut_assertok(uclass_get_device(UCLASS_SPMI, 0, &bus));
+
+ /* Check bus name */
+ ut_asserteq_str(name, bus->name);
+
+ /* Check that it has some devices */
+ ut_asserteq(device_has_children(bus), true);
+
+ ut_assertok(device_find_first_child(bus, &dev));
+
+ /* There should be at least one child */
+ ut_assertnonnull(dev);
+
+ /* Check that only PMICs are connected to the bus */
+ while (dev) {
+ ut_asserteq(device_get_uclass_id(dev), UCLASS_PMIC);
+ device_find_next_child(&dev);
+ }
+
+ return 0;
+}
+DM_TEST(dm_test_spmi_probe, DM_TESTF_SCAN_FDT);
+
+/* Test if it's possible to read bus directly and indirectly */
+static int dm_test_spmi_access(struct unit_test_state *uts)
+{
+ const char *pmic_name = "pm8916@0";
+ struct udevice *bus, *pmic;
+
+ ut_assertok(uclass_get_device(UCLASS_SPMI, 0, &bus));
+
+ ut_assertok(device_get_child(bus, 0, &pmic));
+
+ /* Sanity check if it's proper PMIC */
+ ut_asserteq_str(pmic_name, pmic->name);
+
+ /* Read PMIC ID reg using SPMI bus - it assumes it has slaveID == 0*/
+ ut_asserteq(spmi_reg_read(bus, 0, 0xC0, 0x4), 0x10);
+ ut_asserteq(spmi_reg_read(bus, 0, 0xC0, 0x5), 0x5);
+
+ /* Read ID reg via pmic interface */
+ ut_asserteq(pmic_reg_read(pmic, 0xC004), 0x10);
+ ut_asserteq(pmic_reg_read(pmic, 0xC005), 0x5);
+
+ return 0;
+}
+DM_TEST(dm_test_spmi_access, DM_TESTF_SCAN_FDT);
+
+
+/* Test if it's possible to access GPIO that should be in pmic */
+static int dm_test_spmi_access_peripheral(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ unsigned int offset, gpio;
+ const char *name;
+ int offset_count;
+
+ /* Get second pin of PMIC GPIO */
+ ut_assertok(gpio_lookup_name("spmi1", &dev, &offset, &gpio));
+
+ /* Check if PMIC is parent */
+ ut_asserteq(device_get_uclass_id(dev->parent), UCLASS_PMIC);
+
+ /* This should be second gpio */
+ ut_asserteq(1, offset);
+
+ name = gpio_get_bank_info(dev, &offset_count);
+
+ /* Check bank name */
+ ut_asserteq_str("spmi", name);
+ /* Check pin count */
+ ut_asserteq(4, offset_count);
+
+ ut_assertok(gpio_request(gpio, "testing"));
+
+ /* Try to set/clear gpio */
+ ut_assertok(gpio_direction_output(gpio, 0));
+ ut_asserteq(gpio_get_value(gpio), 0);
+ ut_assertok(gpio_direction_output(gpio, 1));
+ ut_asserteq(gpio_get_value(gpio), 1);
+ ut_assertok(gpio_direction_input(gpio));
+ ut_asserteq(gpio_get_value(gpio), 1);
+
+ ut_assertok(gpio_free(gpio));
+
+ return 0;
+}
+DM_TEST(dm_test_spmi_access_peripheral, DM_TESTF_SCAN_FDT);
avoid the need for `u-boot-test-flash` to actually write U-Boot to flash, thus
saving wear on the flash chip(s).
+#### Examples
+
+https://github.com/swarren/uboot-test-hooks contains some working example hook
+scripts, and may be useful as a reference when implementing hook scripts for
+your platform. These scripts are not considered part of U-Boot itself.
+
### Board-type-specific configuration
Each board has a different configuration and behaviour. Many of these
# may be omitted or set to None if TFTP testing is not possible or desired.
env__net_tftp_readable_file = {
"fn": "ubtest-readable.bin",
+ "addr": 0x10000000,
"size": 5058624,
"crc32": "c2244b26",
}
if not f:
pytest.skip('No TFTP readable file to read')
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = f.get('addr', None)
+ if not addr:
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+
fn = f['fn']
output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
expected_text = 'Bytes transferred = '
cmd += ['gdbserver', self.config.gdbserver]
cmd += [
self.config.build_dir + '/u-boot',
+ '-v',
'-d',
self.config.build_dir + '/arch/sandbox/dts/test.dtb'
]
hostprogs-$(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER) += atmel_pmecc_params
-# TODO: CONFIG_CMD_LICENSE does not work
hostprogs-$(CONFIG_CMD_LICENSE) += bin2header
hostprogs-$(CONFIG_LCD_LOGO) += bmp_logo
hostprogs-$(CONFIG_VIDEO_LOGO) += bmp_logo
endif # !LOGO_BMP
+# Generated gziped GPL-2.0 license text
+LICENSE_H = $(objtree)/include/license.h
+LICENSE-$(CONFIG_CMD_LICENSE) += $(LICENSE_H)
+
#
# Use native tools and options
# Define __KERNEL_STRICT_NAMES to prevent typedef overlaps
-D__KERNEL_STRICT_NAMES \
-D_GNU_SOURCE
-__build: $(LOGO-y)
+__build: $(LOGO-y) $(LICENSE-y)
$(LOGO_H): $(obj)/bmp_logo $(LOGO_BMP)
$(obj)/bmp_logo --gen-info $(LOGO_BMP) > $@
$(LOGO_DATA_H): $(obj)/bmp_logo $(LOGO_BMP)
$(obj)/bmp_logo --gen-data $(LOGO_BMP) > $@
+$(LICENSE_H): $(obj)/bin2header $(srctree)/Licenses/gpl-2.0.txt
+ cat $(srctree)/Licenses/gpl-2.0.txt | gzip -9 -c | \
+ $(obj)/bin2header license_gzip > $(LICENSE_H)
+
# Let clean descend into subdirs
subdir- += env
#include <stdlib.h>
#include <stdio.h>
+#include <unistd.h>
int main(int argc, char **argv)
{
#include <env_flags.h>
#include <fcntl.h>
#include <linux/stringify.h>
+#include <ctype.h>
#include <stdio.h>
#include <stdlib.h>
#include <stddef.h>
#include "fw_env.h"
-#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
+struct common_args common_args;
+struct printenv_args printenv_args;
+struct setenv_args setenv_args;
-#define WHITESPACE(c) ((c == '\t') || (c == ' '))
+#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#define min(x, y) ({ \
typeof(x) _min1 = (x); \
return rc;
}
-static char *fw_string_blank(char *s, int noblank)
+static char *skip_chars(char *s)
{
- int i;
- int len = strlen(s);
-
- for (i = 0; i < len; i++, s++) {
- if ((noblank && !WHITESPACE(*s)) ||
- (!noblank && WHITESPACE(*s)))
- break;
+ for (; *s != '\0'; s++) {
+ if (isblank(*s))
+ return s;
}
- if (i == len)
- return NULL;
+ return NULL;
+}
- return s;
+static char *skip_blanks(char *s)
+{
+ for (; *s != '\0'; s++) {
+ if (!isblank(*s))
+ return s;
+ }
+ return NULL;
}
/*
}
/* Drop ending line feed / carriage return */
- while (len > 0 && (dump[len - 1] == '\n' ||
- dump[len - 1] == '\r')) {
- dump[len - 1] = '\0';
- len--;
- }
+ dump[--len] = '\0';
+ if (len && dump[len - 1] == '\r')
+ dump[--len] = '\0';
/* Skip comment or empty lines */
- if ((len == 0) || dump[0] == '#')
+ if (len == 0 || dump[0] == '#')
continue;
/*
* Search for variable's name,
* remove leading whitespaces
*/
- name = fw_string_blank(dump, 1);
+ name = skip_blanks(dump);
if (!name)
continue;
/* The first white space is the end of variable name */
- val = fw_string_blank(name, 0);
+ val = skip_chars(name);
len = strlen(name);
if (val) {
*val++ = '\0';
if ((val - name) < len)
- val = fw_string_blank(val, 1);
+ val = skip_blanks(val);
else
val = NULL;
}
{NULL, 0, NULL, 0}
};
-struct common_args common_args;
-struct printenv_args printenv_args;
-struct setenv_args setenv_args;
-
void usage_printenv(void)
{
"\n"
"Script Syntax:\n"
" key [space] value\n"
- " lines starting with '#' are treated as commment\n"
+ " lines starting with '#' are treated as comment\n"
"\n"
" A variable without value will be deleted. Any number of spaces are\n"
" allowed between key and value. Space inside of the value is treated\n"
ret = fdt_property_placeholder(fdt, "data", sbuf.st_size, &ptr);
if (ret)
- return ret;
+ goto err;
ret = read(fd, ptr, sbuf.st_size);
if (ret != sbuf.st_size) {
fprintf(stderr, "%s: Can't read %s: %s\n",
params->cmdname, fname, strerror(errno));
goto err;
}
+ close(fd);
return 0;
err:
if (ret < 0) {
fprintf(stderr, "%s: Failed to build FIT image\n",
params->cmdname);
- goto err;
+ goto err_buf;
}
size = ret;
fd = open(fname, O_RDWR | O_CREAT | O_TRUNC | O_BINARY, 0666);
goto err;
}
close(fd);
+ free(buf);
return 0;
err:
+ close(fd);
+err_buf:
free(buf);
return -1;
}
buf = malloc(fit_size);
if (!buf) {
ret = -ENOMEM;
- goto err;
+ goto err_munmap;
}
buf_ptr = 0;
if (images < 0) {
debug("%s: Cannot find /images node: %d\n", __func__, images);
ret = -EINVAL;
- goto err;
+ goto err_munmap;
}
for (node = fdt_first_subnode(fdt, images);
ret = fdt_delprop(fdt, node, "data");
if (ret) {
ret = -EPERM;
- goto err;
+ goto err_munmap;
}
fdt_setprop_u32(fdt, node, "data-offset", buf_ptr);
fdt_setprop_u32(fdt, node, "data-size", len);
goto err;
}
close(fd);
+ return 0;
- ret = 0;
-
+err_munmap:
+ munmap(fdt, sbuf.st_size);
err:
+ if (buf)
+ free(buf);
close(fd);
return ret;
}
}
}
- munmap(fdt, sbuf.st_size);
+ munmap(old_fdt, sbuf.st_size);
close(fd);
/* Pack the FDT and place the data after it */
if (fd < 0) {
fprintf(stderr, "%s: Can't open %s: %s\n",
params->cmdname, fname, strerror(errno));
- goto err;
+ free(fdt);
+ return -EIO;
}
if (write(fd, fdt, new_size) != new_size) {
debug("%s: Failed to write external data to file %s\n",
ret = -EIO;
goto err;
}
- close(fd);
ret = 0;
err:
+ free(fdt);
close(fd);
return ret;
}
if (fstat(fd, &sbuf) < 0) {
fprintf(stderr, "%s: Can't stat %s: %s\n",
params->cmdname, fname, strerror(errno));
+ close(fd);
return -1;
}
close(fd);
static int msg_req_delay = KWBOOT_MSG_REQ_DELAY;
static int msg_rsp_timeo = KWBOOT_MSG_RSP_TIMEO;
+static int blk_rsp_timeo = KWBOOT_BLK_RSP_TIMEO;
static void
kwboot_printv(const char *fmt, ...)
break;
do {
- rc = kwboot_tty_recv(fd, &c, 1, KWBOOT_BLK_RSP_TIMEO);
+ rc = kwboot_tty_recv(fd, &c, 1, blk_rsp_timeo);
if (rc)
break;
kwboot_usage(FILE *stream, char *progname)
{
fprintf(stream,
- "Usage: %s [-d | -a | -q <req-delay> | -s <resp-timeo> | -b <image> | -D <image> ] [ -t ] [-B <baud> ] <TTY>\n",
+ "Usage: %s [OPTIONS] [-b <image> | -D <image> ] [-B <baud> ] <TTY>\n",
progname);
fprintf(stream, "\n");
fprintf(stream,
fprintf(stream, " -a: use timings for Armada XP\n");
fprintf(stream, " -q <req-delay>: use specific request-delay\n");
fprintf(stream, " -s <resp-timeo>: use specific response-timeout\n");
+ fprintf(stream,
+ " -o <block-timeo>: use specific xmodem block timeout\n");
fprintf(stream, "\n");
fprintf(stream, " -t: mini terminal\n");
fprintf(stream, "\n");
kwboot_verbose = isatty(STDOUT_FILENO);
do {
- int c = getopt(argc, argv, "hb:ptaB:dD:q:s:");
+ int c = getopt(argc, argv, "hb:ptaB:dD:q:s:o:");
if (c < 0)
break;
msg_rsp_timeo = atoi(optarg);
break;
+ case 'o':
+ blk_rsp_timeo = atoi(optarg);
+ break;
+
case 'B':
speed = kwboot_tty_speed(atoi(optarg));
if (speed == -1)