#define FSL_CORENET_RCWSR5_DDR_SYNC            0x00000080
 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT               7
 #define FSL_CORENET_RCWSR5_SRDS_EN             0x00002000
+#define FSL_CORENET_RCWSR6_BOOT_LOC    0x0f800000
 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2         0x3c000000 /* bits 162..165 */
 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3         0x003c0000 /* bits 170..173 */
 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT     0x00400000
 
 #ifdef CONFIG_SYS_NAND_BASE_PHYS
        SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif
-#ifdef CONFIG_SRIOBOOT_SLAVE
-#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
-       SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
-                               LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
-       SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
-                               LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
-#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
-       SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
-                               LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
-       SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
-                               LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
-#endif
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
 
                                law_table[i].size, law_table[i].trgt_id);
        }
 
+#ifdef CONFIG_SRIOBOOT_SLAVE
+       /* check RCW to get which port is used for boot */
+       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       u32 bootloc = in_be32(&gur->rcwsr[6]);
+       /* in SRIO boot we need to set specail LAWs for SRIO interfaces */
+       switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) {
+       case 0x8: /* boot from SRIO1 */
+               set_next_law(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+                               LAW_SIZE_1M,
+                               LAW_TRGT_IF_RIO_1);
+               set_next_law(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+                               LAW_SIZE_1M,
+                               LAW_TRGT_IF_RIO_1);
+               break;
+       case 0x9: /* boot from SRIO2 */
+               set_next_law(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+                               LAW_SIZE_1M,
+                               LAW_TRGT_IF_RIO_2);
+               set_next_law(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+                               LAW_SIZE_1M,
+                               LAW_TRGT_IF_RIO_2);
+               break;
+       default:
+               break;
+       }
+#endif
+
        return ;
 }
 
  * SRIOBOOT - SLAVE
  */
 #ifdef CONFIG_SRIOBOOT_SLAVE
-/* slave port for srioboot */
-#define CONFIG_SRIOBOOT_SLAVE_PORT0
-/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */
 #define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000
 #define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \
                (0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR)
 
  * SRIOBOOT - SLAVE
  */
 #ifdef CONFIG_SRIOBOOT_SLAVE
-/* slave port for srioboot */
-#define CONFIG_SRIOBOOT_SLAVE_PORT0
-/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */
 #define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000
 #define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \
                (0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR)