revert commit
98c19aff9524e1d0dd6bf39bf7bde5644f121feb as the
disabling of cache need not be done explicitly. Subsequent
patches to new cache management framework has fixed it.
EMAC issue with cache coherency still exists when cahces are
enabled.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM365
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_L2CACHE_OFF
/* Memory Info */
#define CONFIG_NR_DRAM_BANKS 1