]> git.sur5r.net Git - u-boot/commitdiff
arm:am43xx: Add TPS65218 support to scale voltages up
authorTom Rini <trini@ti.com>
Thu, 5 Jun 2014 15:15:30 +0000 (11:15 -0400)
committerTom Rini <trini@ti.com>
Fri, 6 Jun 2014 21:46:16 +0000 (17:46 -0400)
This family is supported by the TPS65218 PMIC.  Implement a scale_vcores
to set the MPU and CORE voltage correctly to the max frequency that is
supported (and what we will be scaling them to in setup_dplls()).

Signed-off-by: Tom Rini <trini@ti.com>
board/ti/am43xx/board.c
include/configs/am43xx_evm.h

index b635d691bfb6e3965adb5067c2e3bbb57b5b0d60..71af1ae7c8998b781e32f58b4770f950c89bc3d1 100644 (file)
@@ -19,6 +19,7 @@
 #include <asm/arch/gpio.h>
 #include <asm/emif.h>
 #include "board.h"
+#include <power/tps65218.h>
 #include <miiphy.h>
 #include <cpsw.h>
 
@@ -254,13 +255,6 @@ void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 
 const struct dpll_params *get_dpll_ddr_params(void)
 {
-       struct am43xx_board_id header;
-
-       enable_i2c0_pin_mux();
-       i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-       if (read_eeprom(&header) < 0)
-               puts("Could not get board ID.\n");
-
        if (board_is_eposevm())
                return &epos_evm_dpll_ddr;
        else if (board_is_gpevm())
@@ -338,6 +332,46 @@ const struct dpll_params *get_dpll_per_params(void)
        return &dpll_per[ind];
 }
 
+void scale_vcores(void)
+{
+       const struct dpll_params *mpu_params;
+       int mpu_vdd;
+       struct am43xx_board_id header;
+
+       enable_i2c0_pin_mux();
+       i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+       if (read_eeprom(&header) < 0)
+               puts("Could not get board ID.\n");
+
+       /* Get the frequency */
+       mpu_params = get_dpll_mpu_params();
+
+       if (i2c_probe(TPS65218_CHIP_PM))
+               return;
+
+       if (mpu_params->m == 1000) {
+               mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
+       } else if (mpu_params->m == 600) {
+               mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
+       } else {
+               puts("Unknown MPU clock, not scaling\n");
+               return;
+       }
+
+       /* Set DCDC1 (CORE) voltage to 1.1V */
+       if (tps65218_voltage_update(TPS65218_DCDC1,
+                                   TPS65218_DCDC_VOLT_SEL_1100MV)) {
+               puts("tps65218_voltage_update failure\n");
+               return;
+       }
+
+       /* Set DCDC2 (MPU) voltage */
+       if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
+               puts("tps65218_voltage_update failure\n");
+               return;
+       }
+}
+
 void set_uart_mux_conf(void)
 {
        enable_uart0_pin_mux();
index 83596212474fc06e888fc767c6f38e078c8f5e24..823cba6ff43583f0536c026e451d6c30aaceecf5 100644 (file)
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 
+/* Power */
+#define CONFIG_POWER_TPS65218
+
 /* SPL defines. */
 #define CONFIG_SPL_TEXT_BASE           0x40300350
 #define CONFIG_SPL_MAX_SIZE            (220 << 10)     /* 220KB */
 #define CONFIG_SYS_SPL_ARGS_ADDR       (CONFIG_SYS_SDRAM_BASE + \
                                         (128 << 20))
+#define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_YMODEM_SUPPORT
 
 /* Enabling L2 Cache */