config TARGET_CPCI405DT
bool "Support CPCI405DT"
-config TARGET_HH405
- bool "Support HH405"
-
config TARGET_HUB405
bool "Support HUB405"
source "board/dave/PPChameleonEVB/Kconfig"
source "board/esd/cpci2dp/Kconfig"
source "board/esd/cpci405/Kconfig"
-source "board/esd/hh405/Kconfig"
source "board/esd/hub405/Kconfig"
source "board/esd/ocrtc/Kconfig"
source "board/esd/pci405/Kconfig"
+++ /dev/null
-if TARGET_HH405
-
-config SYS_BOARD
- default "hh405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "HH405"
-
-endif
+++ /dev/null
-HH405 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/hh405/
-F: include/configs/HH405.h
-F: configs/HH405_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = hh405.o flash.o \
- ../common/misc.o \
- ../common/esd405ep_nand.o \
- ../common/auto_update.o
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
- uint pbcr;
- unsigned long base_b0;
- int size_val = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b0 = -size_b0;
- switch (size_b0) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
+++ /dev/null
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-0x1f, 0xd8, 0xfc, 0xf7, 0xbf, 0xf6, 0x8e, 0xfd,
-0xd0, 0x8a, 0x93, 0xb1, 0xdb, 0x37, 0xbd, 0x23,
-0x99, 0xb5, 0x39, 0x96, 0x3f, 0x03, 0x8b, 0xff,
-0x68, 0xe7, 0xa9, 0x67, 0xed, 0xec, 0x57, 0x3f,
-0x59, 0xc1, 0x74, 0x8f, 0xf3, 0x2f, 0xc6, 0x1f,
-0xd8, 0xfc, 0xaf, 0xde, 0xf1, 0x05, 0x18, 0x6d,
-0x6f, 0x07, 0x97, 0x7f, 0x6a, 0x2c, 0x7f, 0x06,
-0x17, 0xff, 0x2b, 0x23, 0x69, 0xda, 0x7f, 0x32,
-0xf1, 0x7d, 0x30, 0xdd, 0xb3, 0x1f, 0x39, 0xe1,
-0xe3, 0x0f, 0x66, 0xfe, 0x4d, 0xf6, 0x7c, 0x1c,
-0xbc, 0xd8, 0x6a, 0x82, 0xcd, 0x9e, 0x5a, 0x09,
-0x9b, 0x40, 0xff, 0xf5, 0xff, 0x13, 0xdc, 0xf7,
-0x46, 0x4c, 0xa8, 0x12, 0xaf, 0xcf, 0x2b, 0x7b,
-0x6e, 0x6c, 0xf7, 0x37, 0xea, 0xe7, 0xba, 0x8f,
-0xf0, 0x33, 0x01, 0x00,
+++ /dev/null
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006-2007
- * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-#include <malloc.h>
-#include <pci.h>
-#include <sm501.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* FPGA internal regs */
-#define FPGA_CTRL ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x000))
-#define FPGA_STATUS ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x002))
-#define FPGA_CTR ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x004))
-#define FPGA_BL ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x006))
-
-/* FPGA Control Reg */
-#define FPGA_CTRL_REV0 0x0001
-#define FPGA_CTRL_REV1 0x0002
-#define FPGA_CTRL_VGA0_BL 0x0004
-#define FPGA_CTRL_VGA0_BL_MODE 0x0008
-#define FPGA_CTRL_CF_RESET 0x0040
-#define FPGA_CTRL_PS2_PWR 0x0080
-#define FPGA_CTRL_CF_PWRN 0x0100 /* low active */
-#define FPGA_CTRL_CF_BUS_EN 0x0200
-#define FPGA_CTRL_LCD_CLK 0x7000 /* mask for lcd clock */
-#define FPGA_CTRL_OW_ENABLE 0x8000
-
-#define FPGA_STATUS_CF_DETECT 0x8000
-
-#ifdef CONFIG_VIDEO_SM501
-
-#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
- (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) )
-
-#ifdef CONFIG_VIDEO_SM501_8BPP
-#error CONFIG_VIDEO_SM501_8BPP not supported.
-#endif /* CONFIG_VIDEO_SM501_8BPP */
-
-#ifdef CONFIG_VIDEO_SM501_16BPP
-#define BPP 16
-
-/*
- * 800x600 display B084SN03: PCLK = 40MHz
- * => 2*PCLK = 80MHz
- * 336/4 = 84MHz
- * => PCLK = 84MHz
- */
-static const SMI_REGS init_regs_800x600 [] =
-{
-#if 1 /* test-only */
- {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
-#else
- {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
-#endif
- {0x00004, SWAP32(0x00000000)},
- /* clocks for pm1... */
- {0x00048, SWAP32(0x00021807)},
- {0x0004C, SWAP32(0x221a0a01)},
- {0x00054, SWAP32(0x00000001)},
- /* clocks for pm0... */
- {0x00040, SWAP32(0x00021807)},
- {0x00044, SWAP32(0x221a0a01)},
- {0x00054, SWAP32(0x00000000)},
- /* GPIO */
- {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
- /* panel control regs... */
- {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
- {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
- {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
- {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
- {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
- {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
- {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
- {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
- {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
- {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
- {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
- {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
- {0x80200, SWAP32(0x00010000)}, /* crt display control */
- {0, 0}
-};
-
-/*
- * 1024x768 display G150XG02: PCLK = 65MHz
- * => 2*PCLK = 130MHz
- * 288/2 = 144MHz
- * => PCLK = 72MHz
- */
-static const SMI_REGS init_regs_1024x768 [] =
-{
- {0x00004, SWAP32(0x00000000)},
- /* clocks for pm1... */
- {0x00048, SWAP32(0x00021807)},
- {0x0004C, SWAP32(0x011a0a01)},
- {0x00054, SWAP32(0x00000001)},
- /* clocks for pm0... */
- {0x00040, SWAP32(0x00021807)},
- {0x00044, SWAP32(0x011a0a01)},
- {0x00054, SWAP32(0x00000000)},
- /* GPIO */
- {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
- /* panel control regs... */
- {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
- {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
- {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
- {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
- {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
- {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
- {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
- {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
- {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
- {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
- {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
- {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
- {0x80200, SWAP32(0x00010000)}, /* crt display control */
- {0, 0}
-};
-
-#endif /* CONFIG_VIDEO_SM501_16BPP */
-
-#ifdef CONFIG_VIDEO_SM501_32BPP
-#define BPP 32
-
-/*
- * 800x600 display B084SN03: PCLK = 40MHz
- * => 2*PCLK = 80MHz
- * 336/4 = 84MHz
- * => PCLK = 84MHz
- */
-static const SMI_REGS init_regs_800x600 [] =
-{
-#if 0 /* test-only */
- {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
-#else
- {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
-#endif
- {0x00004, SWAP32(0x00000000)},
- /* clocks for pm1... */
- {0x00048, SWAP32(0x00021807)},
- {0x0004C, SWAP32(0x221a0a01)},
- {0x00054, SWAP32(0x00000001)},
- /* clocks for pm0... */
- {0x00040, SWAP32(0x00021807)},
- {0x00044, SWAP32(0x221a0a01)},
- {0x00054, SWAP32(0x00000000)},
- /* GPIO */
- {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
- /* panel control regs... */
- {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
- {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
- {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
- {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
- {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
- {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
- {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
- {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
- {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
- {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
- {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
- {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
- {0x80200, SWAP32(0x00010000)}, /* crt display control */
- {0, 0}
-};
-
-/*
- * 1024x768 display G150XG02: PCLK = 65MHz
- * => 2*PCLK = 130MHz
- * 288/2 = 144MHz
- * => PCLK = 72MHz
- */
-static const SMI_REGS init_regs_1024x768 [] =
-{
- {0x00004, SWAP32(0x00000000)},
- /* clocks for pm1... */
- {0x00048, SWAP32(0x00021807)},
- {0x0004C, SWAP32(0x011a0a01)},
- {0x00054, SWAP32(0x00000001)},
- /* clocks for pm0... */
- {0x00040, SWAP32(0x00021807)},
- {0x00044, SWAP32(0x011a0a01)},
- {0x00054, SWAP32(0x00000000)},
- /* GPIO */
- {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
- /* panel control regs... */
- {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
- {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
- {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
- {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
- {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
- {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
- {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
- {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
- {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
- {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
- {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
- {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
- {0x80200, SWAP32(0x00010000)}, /* crt display control */
- {0, 0}
-};
-
-#endif /* CONFIG_VIDEO_SM501_32BPP */
-
-#endif /* CONFIG_VIDEO_SM501 */
-
-#if 0
-#define FPGA_DEBUG
-#endif
-
-extern void lxt971_no_sleep(void);
-
-/* fpga configuration data - gzip compressed and generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-
-/* logo bitmap data - gzip compressed and generated by bin2c */
-unsigned char logo_bmp_320[] =
-{
-#include "logo_320_240_4bpp.c"
-};
-
-unsigned char logo_bmp_320_8bpp[] =
-{
-#include "logo_320_240_8bpp.c"
-};
-
-unsigned char logo_bmp_640[] =
-{
-#include "logo_640_480_24bpp.c"
-};
-
-unsigned char logo_bmp_1024[] =
-{
-#include "logo_1024_768_8bpp.c"
-};
-
-
-/*
- * include common lcd code (for esd boards)
- */
-#include "../common/lcd.c"
-
-#include "../common/s1d13704_320_240_4bpp.h"
-#include "../common/s1d13705_320_240_8bpp.h"
-#include "../common/s1d13806_640_480_16bpp.h"
-#include "../common/s1d13806_1024_768_8bpp.h"
-
-
-/*
- * include common auto-update code (for esd boards)
- */
-#include "../common/auto_update.h"
-
-au_image_t au_image[] = {
- {"hh405/preinst.img", 0, -1, AU_SCRIPT},
- {"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE},
- {"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
- {"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
- {"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
- {"hh405/postinst.img", 0, 0, AU_SCRIPT},
-};
-
-int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
-
-
-/*
- * Get version of HH405 board from GPIO's
- */
-int board_revision(void)
-{
- unsigned long osrh_reg;
- unsigned long isr1h_reg;
- unsigned long tcr_reg;
- unsigned long value;
-
- /*
- * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
- */
- osrh_reg = in_be32((void *)GPIO0_OSRH);
- isr1h_reg = in_be32((void *)GPIO0_ISR1H);
- tcr_reg = in_be32((void *)GPIO0_TCR);
- out_be32((void *)GPIO0_OSRH, osrh_reg & ~0xC0003000); /* output select */
- out_be32((void *)GPIO0_ISR1H, isr1h_reg | 0xC0003000); /* input select */
- out_be32((void *)GPIO0_TCR, tcr_reg & ~0x80400000); /* select input */
-
- udelay(1000); /* wait some time before reading input */
- value = in_be32((void *)GPIO0_IR) & 0x80400000; /* get config bits */
-
- /*
- * Restore GPIO settings
- */
- out_be32((void *)GPIO0_OSRH, osrh_reg); /* output select */
- out_be32((void *)GPIO0_ISR1H, isr1h_reg); /* input select */
- out_be32((void *)GPIO0_TCR, tcr_reg); /* enable output driver for outputs */
-
- if (value & 0x80000000) {
- /* Revision 1.0 or 1.1 detected */
- return 1;
- } else {
- if (value & 0x00400000) {
- /* unused */
- return 3;
- } else {
- return 2;
- }
- }
-}
-
-
-int board_early_init_f (void)
-{
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
- */
- mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
-
- return 0;
-}
-
-int cf_enable(void)
-{
- int i;
-
- if (gd->board_type >= 2) {
- if (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT) {
- if (!(in_be16(FPGA_CTRL) & FPGA_CTRL_CF_BUS_EN)) {
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_PWRN);
-
- for (i=0; i<300; i++)
- udelay(1000);
-
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) | FPGA_CTRL_CF_BUS_EN);
-
- for (i=0; i<20; i++)
- udelay(1000);
- }
- } else {
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_BUS_EN);
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) | FPGA_CTRL_CF_PWRN);
- }
- }
-
- return 0;
-}
-
-int misc_init_r (void)
-{
- unsigned char *dst;
- ulong len = sizeof(fpgadata);
- int status;
- int index;
- int i;
- char *str;
- unsigned long contrast0 = 0xffffffff;
-
- dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
- if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
- printf ("GUNZIP ERROR - must RESET board to recover\n");
- do_reset (NULL, 0, 0, NULL);
- }
-
- status = fpga_boot(dst, len);
- if (status != 0) {
- printf("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after programming FPGA)\n ");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("FPGA: %s\n", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
- /* delayed reboot */
- for (i=20; i>0; i--) {
- printf("Rebooting in %2d seconds \r",i);
- for (index=0;index<1000;index++)
- udelay(1000);
- }
- putc ('\n');
- do_reset(NULL, 0, 0, NULL);
- }
-
- puts("FPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("%s ", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
-
- free(dst);
-
- /*
- * Reset FPGA via FPGA_INIT pin
- */
- /* setup FPGA_INIT as output */
- out_be32((void *)GPIO0_TCR,
- in_be32((void *)GPIO0_TCR) | FPGA_INIT);
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~FPGA_INIT); /* reset low */
- udelay(1000); /* wait 1ms */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | FPGA_INIT); /* reset high */
- udelay(1000); /* wait 1ms */
-
- /*
- * Write Board revision into FPGA
- */
- out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | (gd->board_type & 0x0003));
-
- /*
- * Setup and enable EEPROM write protection
- */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
-
- /*
- * Reset touch-screen controller
- */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST);
- udelay(1000);
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | CONFIG_SYS_TOUCH_RST);
-
- /*
- * Enable power on PS/2 interface (with reset)
- */
- out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) & ~FPGA_CTRL_PS2_PWR);
- for (i=0;i<500;i++)
- udelay(1000);
- out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_PS2_PWR);
-
- /*
- * Get contrast value from environment variable
- */
- str = getenv("contrast0");
- if (str) {
- contrast0 = simple_strtol(str, NULL, 16);
- if (contrast0 > 255) {
- printf("ERROR: contrast0 value too high (0x%lx)!\n",
- contrast0);
- contrast0 = 0xffffffff;
- }
- }
-
- /*
- * Init lcd interface and display logo
- */
-
- str = getenv("bd_type");
- if (strcmp(str, "ppc230") == 0) {
- /*
- * Switch backlight on
- */
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) | FPGA_CTRL_VGA0_BL);
- out_be16(FPGA_BL, 0x0000);
-
- lcd_setup(1, 0);
- lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
- regs_13806_1024_768_8bpp,
- sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]),
- logo_bmp_1024, sizeof(logo_bmp_1024));
- } else if (strcmp(str, "ppc220") == 0) {
- /*
- * Switch backlight on
- */
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) & ~FPGA_CTRL_VGA0_BL);
- out_be16(FPGA_BL, 0x0000);
-
- lcd_setup(1, 0);
- lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
- regs_13806_640_480_16bpp,
- sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
- logo_bmp_640, sizeof(logo_bmp_640));
- } else if (strcmp(str, "ppc215") == 0) {
- /*
- * Set default display contrast voltage
- */
- if (contrast0 == 0xffffffff) {
- out_be16(FPGA_CTR, 0x0082);
- } else {
- out_be16(FPGA_CTR, contrast0);
- }
- out_be16(FPGA_BL, 0xffff);
- /*
- * Switch backlight on
- */
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) |
- FPGA_CTRL_VGA0_BL |
- FPGA_CTRL_VGA0_BL_MODE);
- /*
- * Set lcd clock (small epson)
- */
- out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | LCD_CLK_06250);
- udelay(100); /* wait for 100 us */
-
- lcd_setup(0, 1);
- lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
- regs_13705_320_240_8bpp,
- sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]),
- logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp));
- } else if (strcmp(str, "ppc210") == 0) {
- /*
- * Set default display contrast voltage
- */
- if (contrast0 == 0xffffffff) {
- out_be16(FPGA_CTR, 0x0060);
- } else {
- out_be16(FPGA_CTR, contrast0);
- }
- out_be16(FPGA_BL, 0xffff);
- /*
- * Switch backlight on
- */
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) |
- FPGA_CTRL_VGA0_BL |
- FPGA_CTRL_VGA0_BL_MODE);
- /*
- * Set lcd clock (small epson), enable 1-wire interface
- */
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) |
- LCD_CLK_08330 |
- FPGA_CTRL_OW_ENABLE);
-
- lcd_setup(0, 1);
- lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
- regs_13704_320_240_4bpp,
- sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
- logo_bmp_320, sizeof(logo_bmp_320));
-#ifdef CONFIG_VIDEO_SM501
- } else {
- pci_dev_t devbusfn;
-
- /*
- * Is SM501 connected (ppc221/ppc231)?
- */
- devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
- if (devbusfn != -1) {
- puts("VGA: SM501 with 8 MB ");
- if (strcmp(str, "ppc221") == 0) {
- printf("(800*600, %dbpp)\n", BPP);
- out_be16(FPGA_BL, 0x002d); /* max. allowed brightness */
- } else if (strcmp(str, "ppc231") == 0) {
- printf("(1024*768, %dbpp)\n", BPP);
- out_be16(FPGA_BL, 0x0000);
- } else {
- printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
- return 0;
- }
- } else {
- printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
- return 0;
- }
-#endif /* CONFIG_VIDEO_SM501 */
- }
-
- cf_enable();
-
- return (0);
-}
-
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming HH405");
- } else {
- puts(str);
- }
-
- if (getenv_f("bd_type", str, sizeof(str)) != -1) {
- printf(" (%s", str);
- } else {
- puts(" (Missing bd_type!");
- }
-
- gd->board_type = board_revision();
- printf(", Rev %ld.x)\n", gd->board_type);
-
- return 0;
-}
-
-#ifdef CONFIG_IDE_RESET
-void ide_set_reset(int on)
-{
- if (((gd->board_type >= 2) &&
- (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT)) ||
- (gd->board_type < 2)) {
- /*
- * Assert or deassert CompactFlash Reset Pin
- */
- if (on) { /* assert RESET */
- cf_enable();
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) &
- ~FPGA_CTRL_CF_RESET);
- } else { /* release RESET */
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) |
- FPGA_CTRL_CF_RESET);
- }
- }
-}
-#endif /* CONFIG_IDE_RESET */
-
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-/* Input: <dev_addr> I2C address of EEPROM device to enable.
- * <state> -1: deliver current state
- * 0: disable write
- * 1: enable write
- * Returns: -1: wrong device address
- * 0: dis-/en- able done
- * 0/1: current state if <state> was -1.
- */
-int eeprom_write_enable (unsigned dev_addr, int state)
-{
- if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
- return -1;
- } else {
- switch (state) {
- case 1:
- /* Enable write access, clear bit GPIO_SINT2. */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
- state = 0;
- break;
- case 0:
- /* Disable write access, set bit GPIO_SINT2. */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
- state = 0;
- break;
- default:
- /* Read current status back. */
- state = (0 == (in_be32((void *)GPIO0_OR) &
- CONFIG_SYS_EEPROM_WP));
- break;
- }
- }
- return state;
-}
-
-int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int query = argc == 1;
- int state = 0;
-
- if (query) {
- /* Query write access state. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
- if (state < 0) {
- puts ("Query of write access state failed.\n");
- } else {
- printf ("Write access for device 0x%0x is %sabled.\n",
- CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
- state = 0;
- }
- } else {
- if ('0' == argv[1][0]) {
- /* Disable write access. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
- } else {
- /* Enable write access. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
- }
- if (state < 0) {
- puts ("Setup of write access state failed.\n");
- }
- }
-
- return state;
-}
-
-U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "Enable / disable / query EEPROM write access",
- ""
-);
-#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
-
-
-#ifdef CONFIG_VIDEO_SM501
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str (int line_number, char *info)
-{
- char str[64];
- char str2[64];
- int i = getenv_f("serial#", str2, sizeof(str));
-
- if (line_number == 1) {
- sprintf(str, " Board: ");
-
- if (i == -1) {
- strcat(str, "### No HW ID - assuming HH405");
- } else {
- strcat(str, str2);
- }
-
- if (getenv_f("bd_type", str2, sizeof(str2)) != -1) {
- strcat(str, " (");
- strcat(str, str2);
- } else {
- strcat(str, " (Missing bd_type!");
- }
-
- sprintf(str2, ", Rev %ld.x)", gd->board_type);
- strcat(str, str2);
- strcpy(info, str);
- } else {
- info [0] = '\0';
- }
-}
-#endif /* CONFIG_CONSOLE_EXTRA_INFO */
-
-/*
- * Returns SM501 register base address. First thing called in the driver.
- */
-unsigned int board_video_init (void)
-{
- pci_dev_t devbusfn;
- u32 addr;
-
- /*
- * Is SM501 connected (ppc221/ppc231)?
- */
- devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
- if (devbusfn != -1) {
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr);
- return (addr & 0xfffffffe);
- }
-
- return 0;
-}
-
-/*
- * Returns SM501 framebuffer address
- */
-unsigned int board_video_get_fb (void)
-{
- pci_dev_t devbusfn;
- u32 addr;
-
- /*
- * Is SM501 connected (ppc221/ppc231)?
- */
- devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
- if (devbusfn != -1) {
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
- addr &= 0xfffffffe;
-#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
- addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
-#endif
- return addr;
- }
-
- return 0;
-}
-
-/*
- * Called after initializing the SM501 and before clearing the screen.
- */
-void board_validate_screen (unsigned int base)
-{
-}
-
-/*
- * Return a pointer to the initialization sequence.
- */
-const SMI_REGS *board_get_regs (void)
-{
- char *str;
-
- str = getenv("bd_type");
- if (strcmp(str, "ppc221") == 0) {
- return init_regs_800x600;
- } else {
- return init_regs_1024x768;
- }
-}
-
-int board_get_width (void)
-{
- char *str;
-
- str = getenv("bd_type");
- if (strcmp(str, "ppc221") == 0) {
- return 800;
- } else {
- return 1024;
- }
-}
-
-int board_get_height (void)
-{
- char *str;
-
- str = getenv("bd_type");
- if (strcmp(str, "ppc221") == 0) {
- return 600;
- } else {
- return 768;
- }
-}
-
-#endif /* CONFIG_VIDEO_SM501 */
-
-
-void reset_phy(void)
-{
-#ifdef CONFIG_LXT971_NO_SLEEP
-
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-#endif
-}
+++ /dev/null
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+++ /dev/null
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-0x3a, 0xce, 0x00, 0x95, 0x62, 0x99, 0x2a, 0x9c,
-0xbd, 0x44, 0x84, 0xb5, 0xaf, 0x78, 0xde, 0x70,
-0x67, 0x4c, 0xe3, 0x19, 0x0e, 0x59, 0x04, 0xf4,
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-0x40, 0x63, 0x93, 0xa2, 0x36, 0x72, 0xcd, 0xa9,
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-0x37, 0xac, 0xb5, 0x5c, 0x57, 0xf3, 0x5a, 0x7e,
-0xd7, 0xcd, 0xc3, 0xcb, 0xd9, 0x95, 0x38, 0x07,
-0x63, 0x01, 0xa9, 0xe8, 0xe3, 0xe2, 0xe6, 0x79,
-0xdd, 0x3d, 0xc0, 0xc5, 0xeb, 0x96, 0x8b, 0x5f,
-0xe4, 0xb5, 0xa0, 0x44, 0xd7, 0x30, 0x91, 0x7b,
-0xac, 0xea, 0x6a, 0x5a, 0x9f, 0xa3, 0x60, 0xfc,
-0x9a, 0x58, 0xe7, 0x24, 0x99, 0x77, 0x2e, 0x30,
-0x38, 0x89, 0x11, 0x1c, 0xc5, 0x0c, 0x82, 0x78,
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-0x99, 0x37, 0x6d, 0xfc, 0xd0, 0x05, 0x5d, 0x5c,
-0xb7, 0x29, 0xcd, 0xf1, 0x2c, 0x8d, 0xcd, 0x26,
-0xc7, 0x65, 0x8e, 0xff, 0xcd, 0x34, 0x9f, 0xa8,
-0x48, 0x67, 0x4c, 0xc1, 0xa3, 0xf4, 0x60, 0xf2,
-0xc5, 0x6a, 0x7d, 0xd1, 0x7f, 0x96, 0x21, 0xad,
-0xdb, 0x62, 0xd5, 0x8d, 0xf9, 0xe1, 0xf9, 0x18,
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-0xdf, 0x7c, 0x6a, 0xaf, 0x3e, 0xdf, 0x7d, 0xfc,
-0x76, 0x7f, 0x7d, 0xb3, 0xfd, 0xf2, 0x7d, 0x7b,
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-0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x6b, 0xbf,
-0x00, 0xff, 0xcf, 0xfd, 0x4c, 0x36, 0x10, 0x0e,
-0x00,
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_HH405=y
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+HH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu>
DU440 ppc4xx 440epx - - Matthias Fuchs <matthias.fuchs@esd.eu>
DU405 ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs@esd.eu>
DP405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu>
+++ /dev/null
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_HH405 1 /* ...on a HH405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT "autoupd"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "pciconfighost=1\0" \
- ""
-
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#undef CONFIG_HAS_ETH1
-
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
-
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-/*
- * Video console
- */
-#define CONFIG_VIDEO /* for sm501 video support */
-
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_SM501
-#if 0
-#define CONFIG_VIDEO_SM501_32BPP
-#else
-#define CONFIG_VIDEO_SM501_16BPP
-#endif
-#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */
-
-#endif /* CONFIG_VIDEO */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_EEPROM
-
-#ifdef CONFIG_VIDEO
-#define CONFIG_CMD_BMP
-#endif
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_SUPPORT_VFAT
-
-#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
-#undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */
-
-#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* print console @ startup */
-
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * RTC stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_RTC_DS1338
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define NAND_BIG_DELAY_US 25
-
-#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-
-#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
-#define CONFIG_SYS_NAND_QUIET 1
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#define CONFIG_IDE_RESET 1 /* reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#if 0 /* test-only */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-#endif
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFF80000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc() */
-
-#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CONFIG_SYS_RAMBOOT 1
-#else
-# undef CONFIG_SYS_RAMBOOT
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF4080000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#if 0 /* test-only */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#else
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-#endif
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
-#define CONFIG_SYS_EEPROM_WREN 1
-
-#if 1 /* test-only */
-/* CAT24WC08/16... */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#else
-/* CAT24WC32/64... */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
- /* 32 byte page write mode using*/
- /* last 5 bits of the address */
-#endif
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-#define CAN_BA 0xF0000000 /* CAN Base Address */
-#define LCD_BA 0xF1000000 /* Epson LCD Base Address */
-#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
-#define CONFIG_SYS_NVRAM_BASE 0xF4080000 /* NVRAM Base Address */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 4 (Epson LCD) initialization */
-#define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
-#define CONFIG_SYS_EBC_PB4CR LCD_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
-
-/*-----------------------------------------------------------------------
- * LCD Setup
- */
-
-#define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */
-#define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */
-#define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */
-#define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */
-
-/*-----------------------------------------------------------------------
- * Universal Interrupt Controller (UIC) Setup
- */
-
-/*
- * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
- */
-#define CONFIG_SYS_UIC0_POLARITY (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6))
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-
-#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
-
-#define LCD_CLK_OFF 0x0000 /* Off */
-#define LCD_CLK_02083 0x1000 /* 2.083 MHz */
-#define LCD_CLK_03135 0x2000 /* 3.135 MHz */
-#define LCD_CLK_04165 0x3000 /* 4.165 MHz */
-#define LCD_CLK_06250 0x4000 /* 6.250 MHz */
-#define LCD_CLK_08330 0x5000 /* 8.330 MHz */
-#define LCD_CLK_12500 0x6000 /* 12.50 MHz */
-#define LCD_CLK_25000 0x7000 /* 25.00 MHz */
-
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CONFIG_SYS_GPIO0_OSRL 0x40000550
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1H 0x15555440
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
-#define CONFIG_SYS_GPIO0_TCR 0xF7FE0017
-
-#define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7)
-#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
-#define CONFIG_SYS_TOUCH_RST (0x80000000 >> 9) /* GPIO9 */
-#define CONFIG_SYS_LCD0_RST (0x80000000 >> 30)
-#define CONFIG_SYS_LCD1_RST (0x80000000 >> 31)
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
-#endif
-#if 1
-#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
-#endif
-
-#endif /* __CONFIG_H */
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