select SUPPORT_SPL
        select SUPPORT_TPL
 
+config TARGET_P2020RDB
+       bool "Support P2020RDB-PC"
+       select SUPPORT_SPL
+       select SUPPORT_TPL
+
 config TARGET_P1_P2_RDB_PC
        bool "Support p1_p2_rdb_pc"
        select SUPPORT_SPL
 
        TARGET_P1020UTM         || \
        TARGET_P1021RDB         || \
        TARGET_P1024RDB         || \
-       TARGET_P1025RDB
+       TARGET_P1025RDB         || \
+       TARGET_P2020RDB
 
 config SYS_BOARD
        default "p1_p2_rdb_pc"
 
        .refresh_rate_ps = 7800000,
        .tfaw_ps = 37500,
 };
-#elif defined(CONFIG_P2020RDB)
+#elif defined(CONFIG_TARGET_P2020RDB)
 /* Micron MT41J128M16_15E */
 dimm_params_t ddr_raw_timing = {
        .n_ranks = 1,
 
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P2020RDB=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_BOOTDELAY=10
 CONFIG_SPL=y
 CONFIG_TPL=y
 
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P2020RDB=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
 CONFIG_BOOTDELAY=10
 CONFIG_SPL=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P2020RDB=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
 CONFIG_BOOTDELAY=10
 CONFIG_SPL=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P2020RDB=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB"
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P2020RDB=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_BOOTDELAY=10
 CONFIG_SPL=y
 CONFIG_TPL=y
 
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P2020RDB=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
 CONFIG_BOOTDELAY=10
 CONFIG_SPL=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P2020RDB=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
 CONFIG_BOOTDELAY=10
 CONFIG_SPL=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P2020RDB=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB"
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 
 #define CONFIG_SYS_L2_SIZE     (256 << 10)
 #endif
 
-#if defined(CONFIG_P2020RDB)
-#define CONFIG_BOARDNAME "P2020RDB-PCA"
+#if defined(CONFIG_TARGET_P2020RDB)
+#define CONFIG_BOARDNAME "P2020RDB-PC"
 #define CONFIG_NAND_FSL_ELBC
 #define CONFIG_P2020
 #define CONFIG_VSC7385_ENET
 #define CONFIG_LIBATA
 #define CONFIG_LBA48
 
-#if defined(CONFIG_P2020RDB)
+#if defined(CONFIG_TARGET_P2020RDB)
 #define CONFIG_SYS_CLK_FREQ    100000000
 #else
 #define CONFIG_SYS_CLK_FREQ    66666666
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 
 /* Default settings for DDR3 */
-#ifndef CONFIG_P2020RDB
+#ifndef CONFIG_TARGET_P2020RDB
 #define CONFIG_SYS_DDR_CS0_BNDS                0x0000003f
 #define CONFIG_SYS_DDR_CS0_CONFIG      0x80014302
 #define CONFIG_SYS_DDR_CS0_CONFIG_2    0x00000000
 #define CONFIG_SPL_RELOC_STACK         (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
 #define CONFIG_SPL_RELOC_STACK_SIZE    (32 << 10)
 #define CONFIG_SPL_RELOC_MALLOC_ADDR   (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
-#if defined(CONFIG_P2020RDB)
+#if defined(CONFIG_TARGET_P2020RDB)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE   (364 << 10)
 #else
 #define CONFIG_SPL_RELOC_MALLOC_SIZE   (108 << 10)
 
 CONFIG_P1024
 CONFIG_P1025
 CONFIG_P2020
-CONFIG_P2020RDB
 CONFIG_P2041RDB
 CONFIG_P3041DS
 CONFIG_P4080DS