* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <watchdog.h>
#include <asm/immap.h>
+#include <asm/io.h>
#include <asm/rtc.h>
/*
*/
void cpu_init_f(void)
{
- volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+ scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+ pll_t *pll = (pll_t *)MMAP_PLL;
#if !defined(CONFIG_CF_SBF)
/* Workaround, must place before fbcs */
- pll->psr = 0x12;
-
- scm1->mpr = 0x77777777;
- scm1->pacra = 0;
- scm1->pacrb = 0;
- scm1->pacrc = 0;
- scm1->pacrd = 0;
- scm1->pacre = 0;
- scm1->pacrf = 0;
- scm1->pacrg = 0;
- scm1->pacri = 0;
+ out_be32(&pll->psr, 0x12);
+
+ out_be32(&scm1->mpr, 0x77777777);
+ out_be32(&scm1->pacra, 0);
+ out_be32(&scm1->pacrb, 0);
+ out_be32(&scm1->pacrc, 0);
+ out_be32(&scm1->pacrd, 0);
+ out_be32(&scm1->pacre, 0);
+ out_be32(&scm1->pacrf, 0);
+ out_be32(&scm1->pacrg, 0);
+ out_be32(&scm1->pacri, 0);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
&& defined(CONFIG_SYS_CS0_CTRL))
- fbcs->csar0 = CONFIG_SYS_CS0_BASE;
- fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
- fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+ out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif
#endif /* CONFIG_CF_SBF */
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
&& defined(CONFIG_SYS_CS1_CTRL))
- fbcs->csar1 = CONFIG_SYS_CS1_BASE;
- fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
- fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+ out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
&& defined(CONFIG_SYS_CS2_CTRL))
- fbcs->csar2 = CONFIG_SYS_CS2_BASE;
- fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
- fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+ out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
&& defined(CONFIG_SYS_CS3_CTRL))
- fbcs->csar3 = CONFIG_SYS_CS3_BASE;
- fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
- fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+ out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
- fbcs->csar4 = CONFIG_SYS_CS4_BASE;
- fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
- fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+ out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+ out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+ out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
&& defined(CONFIG_SYS_CS5_CTRL))
- fbcs->csar5 = CONFIG_SYS_CS5_BASE;
- fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
- fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+ out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+ out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+ out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#ifdef CONFIG_FSL_I2C
- gpio->par_i2c = GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA;
+ out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA);
#endif
icache_enable();
int cpu_init_r(void)
{
#ifdef CONFIG_MCFRTC
- volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
- volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
+ rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
+ rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
- rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
- rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
+ out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
+ out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
#endif
return (0);
void uart_port_conf(int port)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (port) {
case 0:
- gpio->par_uart &=
- (GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK);
- gpio->par_uart |=
- (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+ clrbits_be16(&gpio->par_uart,
+ ~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK));
+ setbits_be16(&gpio->par_uart,
+ GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
break;
case 1:
- gpio->par_uart &=
- (GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK);
- gpio->par_uart |=
- (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+ clrbits_be16(&gpio->par_uart,
+ ~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK));
+ setbits_be16(&gpio->par_uart,
+ GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
break;
case 2:
- gpio->par_dspi &=
- (GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK);
- gpio->par_dspi =
- (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
+ clrbits_8(&gpio->par_dspi,
+ ~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK));
+ out_8(&gpio->par_dspi,
+ GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
break;
}
}
#ifdef CONFIG_CF_DSPI
void cfspi_port_conf(void)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- gpio->par_dspi =
- GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
- GPIO_PAR_DSPI_SCK_SCK;
+ out_8(&gpio->par_dspi,
+ GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+ GPIO_PAR_DSPI_SCK_SCK);
}
int cfspi_claim_bus(uint bus, uint cs)
{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+ if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
return -1;
/* Clear FIFO and resume transfer */
- dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+ clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
switch (cs) {
case 0:
- gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_UNMASK;
- gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 2:
- gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK;
- gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
+ clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
+ setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
break;
}
void cfspi_release_bus(uint bus, uint cs)
{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */
+ /* Clear FIFO */
+ clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
switch (cs) {
case 0:
- gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 2:
- gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK;
+ clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
break;
}
}
/*
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <asm/processor.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
void clock_enter_limp(int lpdiv)
{
- volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
+ ccm_t *ccm = (ccm_t *)MMAP_CCM;
int i, j;
/* Check bounds of divider */
for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
/* Apply the divider to the system clock */
- ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i);
+ clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
/* Enable Limp Mode */
- ccm->misccr |= CCM_MISCCR_LIMP;
+ setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
}
/*
*/
void clock_exit_limp(void)
{
- volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
- volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+ ccm_t *ccm = (ccm_t *)MMAP_CCM;
+ pll_t *pll = (pll_t *)MMAP_PLL;
/* Exit Limp mode */
- ccm->misccr &= ~CCM_MISCCR_LIMP;
+ clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
/* Wait for the PLL to lock */
- while (!(pll->psr & PLL_PSR_LOCK)) ;
+ while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
+ ;
}
/*
int get_clocks(void)
{
- volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
- volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+ ccm_t *ccm = (ccm_t *)MMAP_CCM;
+ pll_t *pll = (pll_t *)MMAP_PLL;
int vco, temp, pcrvalue, pfdr;
u8 bootmode;
- pcrvalue = pll->pcr & 0xFF0F0FFF;
+ pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF;
pfdr = pcrvalue >> 24;
if (pfdr == 0x1E)
if (bootmode == 0) {
/* Normal mode */
- vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+ vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
/* Default value */
- pcrvalue = (pll->pcr & 0x00FFFFFF);
+ pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
pcrvalue |= 0x1E << 24;
- pll->pcr = pcrvalue;
+ out_be32(&pll->pcr, pcrvalue);
vco =
- ((pll->pcr & 0xFF000000) >> 24) *
+ ((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
CONFIG_SYS_INPUT_CLKSRC;
}
gd->vco_clk = vco; /* Vco clock */
} else if (bootmode == 3) {
/* serial mode */
- vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+ vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
gd->vco_clk = vco; /* Vco clock */
}
- if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
+ if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
/* Limp mode */
} else {
gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
- temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
+ temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
gd->cpu_clk = vco / temp; /* cpu clock */
- temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
+ temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
gd->flb_clk = vco / temp; /* flexbus clock */
gd->bus_clk = gd->flb_clk;
}
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
*/
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
#else
- volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
- volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+ sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
u32 i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
}
i--;
- gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+ out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
- sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
- sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
__asm__("nop");
/* Issue LEMR */
- sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
__asm__("nop");
- sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD);
__asm__("nop");
udelay(1000);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
__asm__("nop");
/* Perform two refresh cycles */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
__asm__("nop");
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
__asm__("nop");
- sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00;
+ out_be32(&sdram->sdcr,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
#endif
projects / u-boot / commitdiff