Update these macros to use all upper-case to avoid checkpatch
warnings:
ENET_25MHz,
ENET_50MHz,
ENET_125MHz,
Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
};
enum enet_freq {
- ENET_25MHz,
- ENET_50MHz,
- ENET_125MHz,
+ ENET_25MHZ,
+ ENET_50MHZ,
+ ENET_125MHZ,
};
u32 get_root_clk(enum clk_root_index clock_id);
clock_enable(CCGR_ENET2, 0);
switch (type) {
- case ENET_125MHz:
+ case ENET_125MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
break;
- case ENET_50MHz:
+ case ENET_50MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
break;
- case ENET_25MHz:
+ case ENET_25MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
break;
(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
- return set_clk_enet(ENET_125MHz);
+ return set_clk_enet(ENET_125MHZ);
}
(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
- return set_clk_enet(ENET_125MHz);
+ return set_clk_enet(ENET_125MHZ);
}
int board_phy_config(struct phy_device *phydev)
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
#endif
- return set_clk_enet(ENET_50MHz);
+ return set_clk_enet(ENET_50MHZ);
}
int board_phy_config(struct phy_device *phydev)