board/ti/am335x: add support for beaglebone NAND cape

Beaglebone Board can be connected to expansion boards to add devices to them.
These expansion boards are called 'capes'. This patch adds support for
following versions of Beaglebone(AM335x) NAND capes
(a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
(b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224
Further information and datasheets can be found at [1] and [2]

* How to boot from NAND using Memory Expander + NAND Cape ? *
 - Important: As BOOTSEL values are sampled only at POR, so after changing any
   setting on SW2 (DIP switch), disconnect and reconnect all board power supply
   (including mini-USB console port) to POR the beaglebone.

 - Selection of ECC scheme
  for NAND cape(a), ROM code expects BCH8_HW ecc-scheme
  for NAND cape(b), ROM code expects BCH16_HW ecc-scheme

 - Selction of boot modes can be controlled via  DIP switch(SW2) present on
   Memory Expander cape.
   SW2[SWITCH_BOOT] == OFF  follow default boot order  MMC-> SPI -> UART -> USB
   SW2[SWITCH_BOOT] == ON   boot mode selected via DIP switch(SW2)
   So to flash NAND, first boot via MMC or other sources and then switch to
   SW2[SWITCH_BOOT]=ON to boot from NAND Cape.

 - For NAND boot following switch settings need to be followed
   SW2[ 1] = OFF  (SYSBOOT[ 0]==1: NAND boot mode selected )
   SW2[ 2] = OFF  (SYSBOOT[ 1]==1:       -- do --          )
   SW2[ 3] = ON   (SYSBOOT[ 2]==0:       -- do --          )
   SW2[ 4] = ON   (SYSBOOT[ 3]==0:       -- do --          )
   SW2[ 5] = OFF  (SYSBOOT[ 4]==1:       -- do --          )
   SW2[ 6] = OFF  (SYSBOOT[ 8]==1: 0:x8 device, 1:x16 device )
   SW2[ 7] = ON   (SYSBOOT[ 9]==0: ECC done by ROM  )
   SW2[ 8] = ON   (SYSBOOT[10]==0: Non Muxed device )
   SW2[ 9] = ON   (SYSBOOT[11]==0:    -- do --      )

[1] http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
[2] http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module

*IMPORTANT NOTE*
As Beaglebone board shares the same config as AM335x EVM, so following
changes are required in addition to this patch for Beaglebone NAND cape.
(1) Enable NAND in am335x_beaglebone board profile
(2) Add CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config because:
 -  AM335x EVM has NAND device with datawidth=8, whereas
 -  Beaglebone NAND cape has NAND device with data-width=16

diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index b2bfda5ea9f60a8214ee93e88ae3a842d944cae0..439da4b969fbebabb7f19c2b076e3235d4d1f421 100644 (file)
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -171,25 +171,36 @@ static struct module_pin_mux mii1_pin_mux[] = {
        {-1},
 };
 
+#ifdef CONFIG_NAND
 static struct module_pin_mux nand_pin_mux[] = {
-       {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD0 */
-       {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD1 */
-       {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD2 */
-       {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD3 */
-       {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD4 */
-       {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD5 */
-       {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD6 */
-       {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD7 */
-       {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
-       {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},   /* NAND_WPN */
-       {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},      /* NAND_CS0 */
-       {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
-       {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},   /* NAND_OE */
-       {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},       /* NAND_WEN */
-       {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},  /* NAND_BE_CLE */
+       {OFFSET(gpmc_ad0),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0  */
+       {OFFSET(gpmc_ad1),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1  */
+       {OFFSET(gpmc_ad2),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2  */
+       {OFFSET(gpmc_ad3),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3  */
+       {OFFSET(gpmc_ad4),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4  */
+       {OFFSET(gpmc_ad5),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5  */
+       {OFFSET(gpmc_ad6),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6  */
+       {OFFSET(gpmc_ad7),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7  */
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+       {OFFSET(gpmc_ad8),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8  */
+       {OFFSET(gpmc_ad9),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9  */
+       {OFFSET(gpmc_ad10),     (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
+       {OFFSET(gpmc_ad11),     (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
+       {OFFSET(gpmc_ad12),     (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
+       {OFFSET(gpmc_ad13),     (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
+       {OFFSET(gpmc_ad14),     (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
+       {OFFSET(gpmc_ad15),     (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
+#endif
+       {OFFSET(gpmc_wait0),    (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
+       {OFFSET(gpmc_wpn),      (MODE(7) | PULLUP_EN)},            /* nWP */
+       {OFFSET(gpmc_csn0),     (MODE(0) | PULLUP_EN)},            /* nCS */
+       {OFFSET(gpmc_wen),      (MODE(0) | PULLDOWN_EN)},          /* WEN */
+       {OFFSET(gpmc_oen_ren),  (MODE(0) | PULLDOWN_EN)},          /* OE */
+       {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)},          /* ADV_ALE */
+       {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)},          /* BE_CLE */
        {-1},
 };
-
+#endif
 #if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
 static struct module_pin_mux bone_norcape_pin_mux[] = {
        {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A0 */
@@ -336,11 +347,12 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
                configure_module_pin_mux(i2c1_pin_mux);
                configure_module_pin_mux(mii1_pin_mux);
                configure_module_pin_mux(mmc0_pin_mux);
-#ifndef CONFIG_NOR
-               configure_module_pin_mux(mmc1_pin_mux);
-#endif
-#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
+#if defined(CONFIG_NAND)
+               configure_module_pin_mux(nand_pin_mux);
+#elif defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
                configure_module_pin_mux(bone_norcape_pin_mux);
+#else
+               configure_module_pin_mux(mmc1_pin_mux);
 #endif
        } else if (board_is_gp_evm(header)) {
                /* General Purpose EVM */
@@ -351,8 +363,10 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
                if (profile & ~PROFILE_2)
                        configure_module_pin_mux(i2c1_pin_mux);
                /* Profiles 2 & 3 don't have NAND */
+#ifdef CONFIG_NAND
                if (profile & ~(PROFILE_2 | PROFILE_3))
                        configure_module_pin_mux(nand_pin_mux);
+#endif
                else if (profile == PROFILE_2) {
                        configure_module_pin_mux(mmc1_pin_mux);
                        configure_module_pin_mux(spi0_pin_mux);
@@ -377,7 +391,11 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
                configure_module_pin_mux(i2c1_pin_mux);
                configure_module_pin_mux(mii1_pin_mux);
                configure_module_pin_mux(mmc0_pin_mux);
+#if defined(CONFIG_NAND)
+               configure_module_pin_mux(nand_pin_mux);
+#else
                configure_module_pin_mux(mmc1_pin_mux);
+#endif
        } else {
                puts("Unknown board, cannot configure pinmux.");
                hang();