Changes since U-Boot 0.2.2:
======================================================================
+* Patch by Arun Dharankar, 24 Mar 2003:
+ - add threads / scheduler example code
+
+* Add patches by Robert Schwebel, 31 Mar 2003:
+ - add ctrl-c support for kermit download
+ - align bdinfo output on ARM
+
+* Add CPU ID, version, and clock speed for INCA-IP
+
* Patches by Dave Ellis, 18 Mar 2003 for SXNI855T board:
- fix SRAM and SDRAM memory sizing
- add status LED support
E: eramdam@kieray1.p.y.ki.era.ericsson.se
D: 8xxrom
+N: Arun Dharankar
+E: ADharankar@ATTBI.Com
+D: threads / scheduler example code
+
N: Kári Davíðsson
E: kd@flaga.is
D: FLAGA DM Support
## StrongARM Systems
#########################################################################
-LIST_SA="at91rm9200dk dnp1110 lart shannon"
+LIST_SA="dnp1110 lart shannon"
#########################################################################
## ARM7 Systems
## ARM9 Systems
#########################################################################
-LIST_ARM9="smdk2400 smdk2410 trab VCMA9"
+LIST_ARM9="at91rm9200dk smdk2400 smdk2410 trab VCMA9"
#########################################################################
## Xscale Systems
\( -name 'core' -o -name '*.bak' -o -name '*~' \
-o -name '*.o' -o -name '*.a' \) -print \
| xargs rm -f
- rm -f examples/hello_world examples/timer examples/eepro100_eeprom
+ rm -f examples/hello_world examples/timer \
+ examples/eepro100_eeprom examples/sched
rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr
rm -f tools/easylogo/easylogo tools/bmp_logo
rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
Modem Support:
--------------
-[so far only for SMDK2400 board]
+[so far only for SMDK2400 and TRAB boards]
- Modem support endable:
CONFIG_MODEM_SUPPORT
created; also, when using EEPROM you will have to use getenv_r()
until then to read environment variables.
-The environment is now protected by a CRC32 checksum. Before the
-monitor is relocated into RAM, as a result of a bad CRC you will be
-working with the compiled-in default environment - *silently*!!!
-[This is necessary, because the first environment variable we need is
-the "baudrate" setting for the console - if we have a bad CRC, we
-don't have any device yet where we could complain.]
+The environment is protected by a CRC32 checksum. Before the monitor
+is relocated into RAM, as a result of a bad CRC you will be working
+with the compiled-in default environment - *silently*!!! [This is
+necessary, because the first environment variable we need is the
+"baudrate" setting for the console - if we have a bad CRC, we don't
+have any device yet where we could complain.]
Note: once the monitor has been relocated, then it will complain if
the default environment is used; a new CRC is computed as soon as you
-use the "setenv" command to modify / delete / add any environment
-variable [even when you try to delete a non-existing variable!].
-
-Note2: you must edit your u-boot.lds file to reflect this
-configuration.
+use the "saveenv" command to store a valid environment.
Low Level (hardware related) configuration options:
- MPC824X: data cache
- PPC4xx: data cache
-- CFG_INIT_DATA_OFFSET:
+- CFG_GBL_DATA_OFFSET:
Offset of the initial data structure in the memory
area defined by CFG_INIT_RAM_ADDR. Usually
- CFG_INIT_DATA_OFFSET is chosen such that the initial
+ CFG_GBL_DATA_OFFSET is chosen such that the initial
data is located at the end of the available space
(sometimes written as (CFG_INIT_RAM_END -
CFG_INIT_DATA_SIZE), and the initial stack is just
below that area (growing from (CFG_INIT_RAM_ADDR +
- CFG_INIT_DATA_OFFSET) downward.
+ CFG_GBL_DATA_OFFSET) downward.
Note:
On the MPC824X (or other systems that use the data
steps:
1. Add a new configuration option for your board to the toplevel
- "Makefile", using the existing entries as examples.
+ "Makefile" and to the "MAKEALL" script, using the existing
+ entries as examples. Note that here and at many other places
+ boards and other names are listed alphabetically sorted. Please
+ keep this order.
2. Create a new directory to hold your board specific code. Add any
- files you need.
+ files you need. In your board directory, you will need at least
+ the "Makefile", a "<board>.c", "flash.c" and "u-boot.lds".
+3. Create a new configuration file "include/configs/<board>.h" for
+ your board
3. If you're porting U-Boot to a new CPU, then also create a new
directory to hold your CPU specific code. Add any files you need.
-4. Run "make config_name" with your new name.
+4. Run "make <board>_config" with your new name.
5. Type "make", and you should get a working "u-boot.srec" file
to be installed on your target system.
+6. Debug and solve any problems that might arise.
[Of course, this last step is much harder than it sounds.]
[q, b, e, ?] ## Application terminated, rc = 0x0
+
+Minicom warning:
+================
+
+Over time, many people have reported problems when trying to used the
+"minicom" terminal emulation program for serial download. I (wd)
+consider minicom to be broken, and recommend not to use it. Under
+Unix, I recommend to use CKermit for general purpose use (and
+especially for kermit binary protocol download ("loadb" command), and
+use "cu" for S-Record download ("loads" command).
+
NetBSD Notes:
=============
*/
#include <common.h>
-#include <AT91RM9200.h>
+#include <asm/arch/AT91RM9200.h>
/* ------------------------------------------------------------------------- */
/*
#include <asm/inca-ip.h>
+extern uint incaip_get_cpuclk(void);
+
static ulong max_sdram_size(void)
{
/* The only supported SDRAM data width is 16bit.
return max_size;
}
+int checkboard (void)
+{
+
+ unsigned long chipid = *INCA_IP_WDT_CHIPID;
+ int part_num;
+
+ puts ("Board: INCA-IP ");
+ part_num = (chipid >> 12) & 0xffff;
+ switch (part_num) {
+ case 0xc0:
+ printf ("Standard Version, ");
+ break;
+ case 0xc1:
+ printf ("Basic Version, ");
+ break;
+ default:
+ printf ("Unknown Part Number 0x%x ", part_num);
+ break;
+ }
+
+ printf ("Chip V1.%ld, ", (chipid >> 28));
+
+ printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000);
+
+ return 0;
+}
sw t1, EBU_ADDSEL0(t0)
#if CPU_CLOCK_RATE==150000000 /* 150 MHz clock for the MIPS core */
- li t1, 0xE841417E
+ li t1, 0xA841417E
sw t1, EBU_BUSCON0(t0) /* value set up by magic flash word */
sw t1, EBU_BUSCON2(t0)
#else /* 100 MHz */
printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
}
printf ("\n"
- "ip_addr = ");
+ "ip_addr = ");
print_IPaddr (bd->bi_ip_addr);
printf ("\n"
- "baudrate = %d bps\n", bd->bi_baudrate);
+ "baudrate = %d bps\n", bd->bi_baudrate);
return 0;
}
#define XON_CHAR 17
#define XOFF_CHAR 19
#define START_CHAR 0x01
+#define ETX_CHAR 0x03
#define END_CHAR 0x0D
#define SPACE 0x20
#define K_ESCAPE 0x23
#endif
/* get a packet */
- /* wait for the starting character */
- while (serial_getc () != START_CHAR);
+ /* wait for the starting character or ^C */
+ for (;;) {
+ switch (serial_getc ()) {
+ case START_CHAR: /* start packet */
+ break;
+ case ETX_CHAR: /* ^C waiting for packet */
+ return (0);
+ default:
+ ;
+ }
+ }
+
/* get length of packet */
sum = 0;
new_char = serial_getc ();
{
unsigned long nandptr;
struct Nand *mychip;
+ int ret = 0;
if (ofs & (nand->erasesize-1) || len & (nand->erasesize-1)) {
printf ("Offset and size must be sector aligned, erasesize = %d\n",
nandptr = nand->IO_ADDR;
+ /* Select the NAND device */
+ NAND_ENABLE_CE(nand); /* set pin low */
+
+ /* Check the WP bit */
+ NanD_Command(nand, NAND_CMD_STATUS);
+ if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
+ printf ("nand_write_ecc: Device is write protected!!!\n");
+ ret = -1;
+ goto out;
+ }
+
/* FIXME: Do nand in the background. Use timers or schedule_task() */
while(len) {
mychip = &nand->chips[shr(ofs, nand->chipshift)];
if (READ_NAND(nandptr) & 1) {
printf("Error erasing at 0x%lx\n", (long)ofs);
/* There was an error */
- goto callback;
+ ret = -1;
+ goto out;
}
ofs += nand->erasesize;
len -= nand->erasesize;
}
- callback:
- return 0;
+out:
+ /* De-select the NAND device */
+ NAND_DISABLE_CE(nand); /* set pin high */
+
+ return ret;
}
static inline int nandcheck(unsigned long potential, unsigned long physadr)
{
-
-
return 0;
}
#include <common.h>
#include <command.h>
-#include <AT91RM9200.h>
+#include <asm/io.h>
/* read co-processor 15, register #1 (control register) */
static unsigned long read_p15_c1(void)
*/
#include <common.h>
-#include <AT91RM9200.h>
+#include <asm/io.h>
#include <asm/proc-armv/ptrace.h>
extern void reset_cpu(ulong addr);
*/
#include <common.h>
-#include <AT91RM9200.h>
+#include <asm/io.h>
/* ggi thunder */
AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
#include <common.h>
#include <command.h>
-#include <AT91RM9200.h>
+#include <asm/io.h>
#include <net.h>
/* ----- Ethernet Buffer definitions ----- */
SREC = hello_world.srec
BIN = hello_world.bin
+ifeq ($(ARCH),ppc)
+SREC += sched.srec
+BIN += sched.bin
+endif
+
ifeq ($(CPU),mips)
SREC =
BIN =
# The following example is pretty 8xx specific...
ifeq ($(CPU),mpc8xx)
SREC += timer.srec
+BIN += timer.bin
endif
# Utility for resetting i82559 EEPROM
OBJS = $(SREC:.srec=.o)
-LIB = libsyscall.a
+LIB = libsyscall.a
LIBAOBJS= syscall.o
+ifeq ($(ARCH),ppc)
+LIBAOBJS+= $(ARCH)_longjmp.o $(ARCH)_setjmp.o
+endif
LIBCOBJS=
LIBOBJS = $(LIBAOBJS) $(LIBCOBJS)
--- /dev/null
+/* longjmp for PowerPC.
+ Copyright (C) 1995, 1996, 1997, 1999, 2000 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, write to the Free
+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307 USA. */
+
+#include <ppc_asm.tmpl>
+
+# define JB_GPR1 0 /* Also known as the stack pointer */
+# define JB_GPR2 1
+# define JB_LR 2 /* The address we will return to */
+# define JB_GPRS 3 /* GPRs 14 through 31 are saved, 18 in total */
+# define JB_CR 21 /* Condition code registers. */
+# define JB_FPRS 22 /* FPRs 14 through 31 are saved, 18*2 words total */
+# define JB_SIZE (58*4)
+
+#define FP(x...) x
+#define FP(x...) x
+
+.globl longjmp;
+
+longjmp:
+ lwz r1,(JB_GPR1*4)(r3)
+ lwz r2,(JB_GPR2*4)(r3)
+ lwz r0,(JB_LR*4)(r3)
+ lwz r14,((JB_GPRS+0)*4)(r3)
+FP( lfd 14,((JB_FPRS+0*2)*4)(r3))
+ lwz r15,((JB_GPRS+1)*4)(r3)
+FP( lfd 15,((JB_FPRS+1*2)*4)(r3))
+ lwz r16,((JB_GPRS+2)*4)(r3)
+FP( lfd 16,((JB_FPRS+2*2)*4)(r3))
+ lwz r17,((JB_GPRS+3)*4)(r3)
+FP( lfd 17,((JB_FPRS+3*2)*4)(r3))
+ lwz r18,((JB_GPRS+4)*4)(r3)
+FP( lfd 18,((JB_FPRS+4*2)*4)(r3))
+ lwz r19,((JB_GPRS+5)*4)(r3)
+FP( lfd 19,((JB_FPRS+5*2)*4)(r3))
+ lwz r20,((JB_GPRS+6)*4)(r3)
+FP( lfd 20,((JB_FPRS+6*2)*4)(r3))
+ mtlr r0
+ lwz r21,((JB_GPRS+7)*4)(r3)
+FP( lfd 21,((JB_FPRS+7*2)*4)(r3))
+ lwz r22,((JB_GPRS+8)*4)(r3)
+FP( lfd 22,((JB_FPRS+8*2)*4)(r3))
+ lwz r0,(JB_CR*4)(r3)
+ lwz r23,((JB_GPRS+9)*4)(r3)
+FP( lfd 23,((JB_FPRS+9*2)*4)(r3))
+ lwz r24,((JB_GPRS+10)*4)(r3)
+FP( lfd 24,((JB_FPRS+10*2)*4)(r3))
+ lwz r25,((JB_GPRS+11)*4)(r3)
+FP( lfd 25,((JB_FPRS+11*2)*4)(r3))
+ mtcrf 0xFF,r0
+ lwz r26,((JB_GPRS+12)*4)(r3)
+FP( lfd 26,((JB_FPRS+12*2)*4)(r3))
+ lwz r27,((JB_GPRS+13)*4)(r3)
+FP( lfd 27,((JB_FPRS+13*2)*4)(r3))
+ lwz r28,((JB_GPRS+14)*4)(r3)
+FP( lfd 28,((JB_FPRS+14*2)*4)(r3))
+ lwz r29,((JB_GPRS+15)*4)(r3)
+FP( lfd 29,((JB_FPRS+15*2)*4)(r3))
+ lwz r30,((JB_GPRS+16)*4)(r3)
+FP( lfd 30,((JB_FPRS+16*2)*4)(r3))
+ lwz r31,((JB_GPRS+17)*4)(r3)
+FP( lfd 31,((JB_FPRS+17*2)*4)(r3))
+ mr r3,r4
+ blr
--- /dev/null
+/* setjmp for PowerPC.
+ Copyright (C) 1995, 1996, 1997, 1999, 2000 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, write to the Free
+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307 USA. */
+
+#include <ppc_asm.tmpl>
+
+# define JB_GPR1 0 /* Also known as the stack pointer */
+# define JB_GPR2 1
+# define JB_LR 2 /* The address we will return to */
+# define JB_GPRS 3 /* GPRs 14 through 31 are saved, 18 in total */
+# define JB_CR 21 /* Condition code registers. */
+# define JB_FPRS 22 /* FPRs 14 through 31 are saved, 18*2 words total */
+# define JB_SIZE (58*4)
+
+#define FP(x...) x
+
+.globl setctxsp;
+setctxsp:
+ mr r1, r3
+ blr
+
+.globl _setjmp;
+_setjmp:
+ stw r1,(JB_GPR1*4)(3)
+ mflr r0
+ stw r2,(JB_GPR2*4)(3)
+ stw r14,((JB_GPRS+0)*4)(3)
+FP( stfd 14,((JB_FPRS+0*2)*4)(3))
+ stw r0,(JB_LR*4)(3)
+ stw r15,((JB_GPRS+1)*4)(3)
+FP( stfd 15,((JB_FPRS+1*2)*4)(3))
+ mfcr r0
+ stw r16,((JB_GPRS+2)*4)(3)
+FP( stfd 16,((JB_FPRS+2*2)*4)(3))
+ stw r0,(JB_CR*4)(3)
+ stw r17,((JB_GPRS+3)*4)(3)
+FP( stfd 17,((JB_FPRS+3*2)*4)(3))
+ stw r18,((JB_GPRS+4)*4)(3)
+FP( stfd 18,((JB_FPRS+4*2)*4)(3))
+ stw r19,((JB_GPRS+5)*4)(3)
+FP( stfd 19,((JB_FPRS+5*2)*4)(3))
+ stw r20,((JB_GPRS+6)*4)(3)
+FP( stfd 20,((JB_FPRS+6*2)*4)(3))
+ stw r21,((JB_GPRS+7)*4)(3)
+FP( stfd 21,((JB_FPRS+7*2)*4)(3))
+ stw r22,((JB_GPRS+8)*4)(3)
+FP( stfd 22,((JB_FPRS+8*2)*4)(3))
+ stw r23,((JB_GPRS+9)*4)(3)
+FP( stfd 23,((JB_FPRS+9*2)*4)(3))
+ stw r24,((JB_GPRS+10)*4)(3)
+FP( stfd 24,((JB_FPRS+10*2)*4)(3))
+ stw r25,((JB_GPRS+11)*4)(3)
+FP( stfd 25,((JB_FPRS+11*2)*4)(3))
+ stw r26,((JB_GPRS+12)*4)(3)
+FP( stfd 26,((JB_FPRS+12*2)*4)(3))
+ stw r27,((JB_GPRS+13)*4)(3)
+FP( stfd 27,((JB_FPRS+13*2)*4)(3))
+ stw r28,((JB_GPRS+14)*4)(3)
+FP( stfd 28,((JB_FPRS+14*2)*4)(3))
+ stw r29,((JB_GPRS+15)*4)(3)
+FP( stfd 29,((JB_FPRS+15*2)*4)(3))
+ stw r30,((JB_GPRS+16)*4)(3)
+FP( stfd 30,((JB_FPRS+16*2)*4)(3))
+ stw r31,((JB_GPRS+17)*4)(3)
+FP( stfd 31,((JB_FPRS+17*2)*4)(3))
+
+ li 3, 0
+ blr
--- /dev/null
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <syscall.h>
+#include <setjmp.h>
+
+/*
+ * Author: Arun Dharankar <ADharankar@ATTBI.Com>
+ *
+ * A very simple thread/schedular model:
+ * - only one master thread, and no parent child relation maintained
+ * - parent thread cannot be stopped or deleted
+ * - no permissions or credentials
+ * - no elaborate safety checks
+ * - cooperative multi threading
+ * - Simple round-robin scheduleing with no priorities
+ * - no metering/statistics collection
+ *
+ * Basic idea of implementing this is to allow more than one tests to
+ * execute "simultaneously".
+ *
+ * This may be modified such thread_yield may be called in syscalls, and
+ * timer interrupts.
+ */
+
+
+#define MAX_THREADS 8
+
+#define CTX_SIZE 512
+#define STK_SIZE 8*1024
+
+#define STATE_EMPTY 0
+#define STATE_RUNNABLE 1
+#define STATE_STOPPED 2
+#define STATE_TERMINATED 2
+
+#define MASTER_THREAD 0
+
+#define RC_FAILURE (-1)
+#define RC_SUCCESS (0)
+
+struct lthread {
+ int state;
+ int retval;
+ char stack[STK_SIZE];
+ uchar context[CTX_SIZE];
+ int (*func) (void *);
+ void *arg;
+};
+static volatile struct lthread lthreads[MAX_THREADS];
+static volatile int current_tid = MASTER_THREAD;
+
+
+static uchar dbg = 0;
+
+#define DEBUG(fmt, args...) { \
+ if(dbg != 0) { \
+ mon_printf("[%s %d %s]: ", __FILE__, __LINE__, __FUNCTION__); \
+ mon_printf(fmt, ##args); \
+ mon_printf("\n"); \
+ } \
+ }
+
+static int testthread (void *);
+static void sched_init (void);
+static int thread_create (int (*func) (void *), void *arg);
+static int thread_start (int id);
+static void thread_yield (void);
+static int thread_delete (int id);
+static int thread_join (int *ret);
+#if 0 /* not used yet */
+static int thread_stop (int id);
+#endif /* not used yet */
+
+/* An example of schedular test */
+
+#define NUMTHREADS 7
+int sched (bd_t *bd, int ac, char *av[])
+{
+ int i, j;
+ int tid[NUMTHREADS];
+ int names[NUMTHREADS];
+
+ sched_init ();
+
+ for (i = 0; i < NUMTHREADS; i++) {
+ names[i] = i;
+ j = thread_create (testthread, (void *) &names[i]);
+ if (j == RC_FAILURE)
+ mon_printf ("schedtest: Failed to create thread %d\n",
+ i);
+ if (j > 0) {
+ mon_printf ("schedtest: Created thread with id %d, name %d\n",
+ j, i);
+ tid[i] = j;
+ }
+ }
+ mon_printf ("schedtest: Threads created\n");
+
+ mon_printf ("sched_test: function=0x%08x\n", testthread);
+ for (i = 0; i < NUMTHREADS; i++) {
+ mon_printf ("schedtest: Setting thread %d runnable\n", tid[i]);
+ thread_start (tid[i]);
+ thread_yield ();
+ }
+ mon_printf ("schedtest: Started %d threads\n", NUMTHREADS);
+
+ while (1) {
+ mon_printf ("schedtest: Waiting for threads to complete\n");
+ if (mon_tstc () && mon_getc () == 0x3) {
+ mon_printf ("schedtest: Aborting threads...\n");
+ for (i = 0; i < NUMTHREADS; i++) {
+ mon_printf ("schedtest: Deleting thread %d\n",
+ tid[i]);
+ thread_delete (tid[i]);
+ }
+ return RC_SUCCESS;
+ }
+ j = -1;
+ i = thread_join (&j);
+ if (i == RC_FAILURE) {
+ mon_printf ("schedtest: No threads pending, "
+ "exiting schedular test\n");
+ return RC_SUCCESS;
+ }
+ mon_printf ("schedtest: thread is %d returned %d\n", i,
+ j);
+ thread_yield ();
+ }
+
+ return RC_SUCCESS;
+}
+
+static int testthread (void *name)
+{
+ int i;
+
+ mon_printf ("testthread: Begin executing thread, myname %d, &i=0x%08x\n",
+ *(int *) name, &i);
+
+ mon_printf ("Thread %02d, i=%d\n", *(int *) name);
+
+ for (i = 0; i < 0xffff * (*(int *) name + 1); i++) {
+ if (mon_tstc () && mon_getc () == 0x3) {
+ mon_printf ("testthread: myname %d terminating.\n",
+ *(int *) name);
+ return *(int *) name + 1;
+ }
+
+ if (i % 100 == 0)
+ thread_yield ();
+ }
+
+ mon_printf ("testthread: returning %d, i=0x%x\n",
+ *(int *) name + 1, i);
+
+ return *(int *) name + 1;
+}
+
+
+static void sched_init (void)
+{
+ int i;
+
+ for (i = MASTER_THREAD + 1; i < MAX_THREADS; i++)
+ lthreads[i].state = STATE_EMPTY;
+
+ current_tid = MASTER_THREAD;
+ lthreads[current_tid].state = STATE_RUNNABLE;
+ DEBUG ("sched_init: master context = 0x%08x",
+ lthreads[current_tid].context);
+ return;
+}
+
+static void thread_yield (void)
+{
+ static int i;
+
+ DEBUG ("thread_yield: current tid=%d", current_tid);
+
+#define SWITCH(new) \
+ if(lthreads[new].state == STATE_RUNNABLE) { \
+ DEBUG("thread_yield: %d match, ctx=0x%08x", \
+ new, lthreads[current_tid].context); \
+ if(setjmp(lthreads[current_tid].context) == 0) { \
+ current_tid = new; \
+ DEBUG("thread_yield: tid %d returns 0", \
+ new); \
+ longjmp(lthreads[new].context, 1); \
+ } else { \
+ DEBUG("thread_yield: tid %d returns 1", \
+ new); \
+ return; \
+ } \
+ }
+
+ for (i = current_tid + 1; i < MAX_THREADS; i++) {
+ SWITCH (i);
+ }
+
+ if (current_tid != 0) {
+ for (i = 0; i <= current_tid; i++) {
+ SWITCH (i);
+ }
+ }
+
+ DEBUG ("thread_yield: returning from thread_yield");
+ return;
+}
+
+static int thread_create (int (*func) (void *), void *arg)
+{
+ int i;
+
+ for (i = MASTER_THREAD + 1; i < MAX_THREADS; i++) {
+ if (lthreads[i].state == STATE_EMPTY) {
+ lthreads[i].state = STATE_STOPPED;
+ lthreads[i].func = func;
+ lthreads[i].arg = arg;
+ DEBUG ("thread_create: returns new tid %d", i);
+ return i;
+ }
+ }
+
+ DEBUG ("thread_create: returns failure");
+ return RC_FAILURE;
+}
+
+static int thread_delete (int id)
+{
+ if (id <= MASTER_THREAD || id > MAX_THREADS)
+ return RC_FAILURE;
+
+ if (current_tid == id)
+ return RC_FAILURE;
+
+ lthreads[id].state = STATE_EMPTY;
+ return RC_SUCCESS;
+}
+
+static void thread_launcher (void)
+{
+ DEBUG ("thread_launcher: invoking func=0x%08x",
+ lthreads[current_tid].func);
+
+ lthreads[current_tid].retval =
+ lthreads[current_tid].func(lthreads[current_tid].arg);
+
+ DEBUG ("thread_launcher: tid %d terminated", current_tid);
+
+ lthreads[current_tid].state = STATE_TERMINATED;
+ thread_yield ();
+ mon_printf ("thread_launcher: should NEVER get here!\n");
+
+ return;
+}
+
+static int thread_start (int id)
+{
+ DEBUG ("thread_start: id=%d", id);
+ if (id <= MASTER_THREAD || id > MAX_THREADS) {
+ return RC_FAILURE;
+ }
+
+ if (lthreads[id].state != STATE_STOPPED)
+ return RC_FAILURE;
+
+ if (setjmp (lthreads[current_tid].context) == 0) {
+ lthreads[id].state = STATE_RUNNABLE;
+ current_tid = id;
+ DEBUG ("thread_start: to be stack=0%08x", lthreads[id].stack);
+ setctxsp (<hreads[id].stack[STK_SIZE]);
+ thread_launcher ();
+ }
+
+ DEBUG ("thread_start: Thread id=%d started, parent returns", id);
+
+ return RC_SUCCESS;
+}
+
+#if 0 /* not used so far */
+static int thread_stop (int id)
+{
+ if (id <= MASTER_THREAD || id >= MAX_THREADS)
+ return RC_FAILURE;
+
+ if (current_tid == id)
+ return RC_FAILURE;
+
+ lthreads[id].state = STATE_STOPPED;
+ return RC_SUCCESS;
+}
+#endif /* not used so far */
+
+static int thread_join (int *ret)
+{
+ int i, j = 0;
+
+ DEBUG ("thread_join: *ret = %d", *ret);
+
+ if (!(*ret == -1 || *ret > MASTER_THREAD || *ret < MAX_THREADS)) {
+ DEBUG ("thread_join: invalid tid %d", *ret);
+ return RC_FAILURE;
+ }
+
+ if (*ret == -1) {
+ DEBUG ("Checking for tid = -1");
+ while (1) {
+ /* DEBUG("thread_join: start while-loopn"); */
+ j = 0;
+ for (i = MASTER_THREAD + 1; i < MAX_THREADS; i++) {
+ if (lthreads[i].state == STATE_TERMINATED) {
+ *ret = lthreads[i].retval;
+ lthreads[i].state = STATE_EMPTY;
+ /* DEBUG("thread_join: returning retval %d of tid %d",
+ ret, i); */
+ return RC_SUCCESS;
+ }
+
+ if (lthreads[i].state != STATE_EMPTY) {
+ DEBUG ("thread_join: %d used slots tid %d state=%d",
+ j, i, lthreads[i].state);
+ j++;
+ }
+ }
+ if (j == 0) {
+ DEBUG ("thread_join: all slots empty!");
+ return RC_FAILURE;
+ }
+ /* DEBUG("thread_join: yielding"); */
+ thread_yield ();
+ /* DEBUG("thread_join: back from yield"); */
+ }
+ }
+
+ if (lthreads[*ret].state == STATE_TERMINATED) {
+ i = *ret;
+ *ret = lthreads[*ret].retval;
+ lthreads[*ret].state = STATE_EMPTY;
+ DEBUG ("thread_join: returing %d for tid %d", *ret, i);
+ return RC_SUCCESS;
+ }
+
+ DEBUG ("thread_join: thread %d is not terminated!", *ret);
+ return RC_FAILURE;
+}
+++ /dev/null
-/* ---------------------------------------------------------------------------- */
-/* ATMEL Microcontroller Software Support - ROUSSET - */
-/* ---------------------------------------------------------------------------- */
-/* The software is delivered "AS IS" without warranty or condition of any */
-/* kind, either express, implied or statutory. This includes without */
-/* limitation any warranty or condition with respect to merchantability or */
-/* fitness for any particular purpose, or against the infringements of */
-/* intellectual property rights of others. */
-/* ---------------------------------------------------------------------------- */
-/* File Name : AT91RM9200.h */
-/* Object : AT91RM9200 definitions */
-/* Generated : AT91 SW Application Group 10/29/2002 (16:10:51) */
-#ifndef AT91RM9200_H
-#define AT91RM9200_H
-
-typedef volatile unsigned int AT91_REG;/* Hardware register definition */
-
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_TC {
- AT91_REG TC_CCR; /* Channel Control Register */
- AT91_REG TC_CMR; /* Channel Mode Register */
- AT91_REG Reserved0[2]; /* */
- AT91_REG TC_CV; /* Counter Value */
- AT91_REG TC_RA; /* Register A */
- AT91_REG TC_RB; /* Register B */
- AT91_REG TC_RC; /* Register C */
- AT91_REG TC_SR; /* Status Register */
- AT91_REG TC_IER; /* Interrupt Enable Register */
- AT91_REG TC_IDR; /* Interrupt Disable Register */
- AT91_REG TC_IMR; /* Interrupt Mask Register */
-} AT91S_TC, *AT91PS_TC;
-
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Usart */
-/* ***************************************************************************** */
-typedef struct _AT91S_USART {
- AT91_REG US_CR; /* Control Register */
- AT91_REG US_MR; /* Mode Register */
- AT91_REG US_IER; /* Interrupt Enable Register */
- AT91_REG US_IDR; /* Interrupt Disable Register */
- AT91_REG US_IMR; /* Interrupt Mask Register */
- AT91_REG US_CSR; /* Channel Status Register */
- AT91_REG US_RHR; /* Receiver Holding Register */
- AT91_REG US_THR; /* Transmitter Holding Register */
- AT91_REG US_BRGR; /* Baud Rate Generator Register */
- AT91_REG US_RTOR; /* Receiver Time-out Register */
- AT91_REG US_TTGR; /* Transmitter Time-guard Register */
- AT91_REG Reserved0[5]; /* */
- AT91_REG US_FIDI; /* FI_DI_Ratio Register */
- AT91_REG US_NER; /* Nb Errors Register */
- AT91_REG US_XXR; /* XON_XOFF Register */
- AT91_REG US_IF; /* IRDA_FILTER Register */
- AT91_REG Reserved1[44]; /* */
- AT91_REG US_RPR; /* Receive Pointer Register */
- AT91_REG US_RCR; /* Receive Counter Register */
- AT91_REG US_TPR; /* Transmit Pointer Register */
- AT91_REG US_TCR; /* Transmit Counter Register */
- AT91_REG US_RNPR; /* Receive Next Pointer Register */
- AT91_REG US_RNCR; /* Receive Next Counter Register */
- AT91_REG US_TNPR; /* Transmit Next Pointer Register */
- AT91_REG US_TNCR; /* Transmit Next Counter Register */
- AT91_REG US_PTCR; /* PDC Transfer Control Register */
- AT91_REG US_PTSR; /* PDC Transfer Status Register */
-} AT91S_USART, *AT91PS_USART;
-
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
-/* ***************************************************************************** */
-typedef struct _AT91S_PIO {
- AT91_REG PIO_PER; /* PIO Enable Register */
- AT91_REG PIO_PDR; /* PIO Disable Register */
- AT91_REG PIO_PSR; /* PIO Status Register */
- AT91_REG Reserved0[1]; /* */
- AT91_REG PIO_OER; /* Output Enable Register */
- AT91_REG PIO_ODR; /* Output Disable Registerr */
- AT91_REG PIO_OSR; /* Output Status Register */
- AT91_REG Reserved1[1]; /* */
- AT91_REG PIO_IFER; /* Input Filter Enable Register */
- AT91_REG PIO_IFDR; /* Input Filter Disable Register */
- AT91_REG PIO_IFSR; /* Input Filter Status Register */
- AT91_REG Reserved2[1]; /* */
- AT91_REG PIO_SODR; /* Set Output Data Register */
- AT91_REG PIO_CODR; /* Clear Output Data Register */
- AT91_REG PIO_ODSR; /* Output Data Status Register */
- AT91_REG PIO_PDSR; /* Pin Data Status Register */
- AT91_REG PIO_IER; /* Interrupt Enable Register */
- AT91_REG PIO_IDR; /* Interrupt Disable Register */
- AT91_REG PIO_IMR; /* Interrupt Mask Register */
- AT91_REG PIO_ISR; /* Interrupt Status Register */
- AT91_REG PIO_MDER; /* Multi-driver Enable Register */
- AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
- AT91_REG PIO_MDSR; /* Multi-driver Status Register */
- AT91_REG Reserved3[1]; /* */
- AT91_REG PIO_PPUDR; /* Pull-up Disable Register */
- AT91_REG PIO_PPUER; /* Pull-up Enable Register */
- AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */
- AT91_REG Reserved4[1]; /* */
- AT91_REG PIO_ASR; /* Select A Register */
- AT91_REG PIO_BSR; /* Select B Register */
- AT91_REG PIO_ABSR; /* AB Select Status Register */
- AT91_REG Reserved5[9]; /* */
- AT91_REG PIO_OWER; /* Output Write Enable Register */
- AT91_REG PIO_OWDR; /* Output Write Disable Register */
- AT91_REG PIO_OWSR; /* Output Write Status Register */
-} AT91S_PIO, *AT91PS_PIO;
-
-
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Debug Unit */
-/* ***************************************************************************** */
-typedef struct _AT91S_DBGU {
- AT91_REG DBGU_CR; /* Control Register */
- AT91_REG DBGU_MR; /* Mode Register */
- AT91_REG DBGU_IER; /* Interrupt Enable Register */
- AT91_REG DBGU_IDR; /* Interrupt Disable Register */
- AT91_REG DBGU_IMR; /* Interrupt Mask Register */
- AT91_REG DBGU_CSR; /* Channel Status Register */
- AT91_REG DBGU_RHR; /* Receiver Holding Register */
- AT91_REG DBGU_THR; /* Transmitter Holding Register */
- AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
- AT91_REG Reserved0[7]; /* */
- AT91_REG DBGU_C1R; /* Chip ID1 Register */
- AT91_REG DBGU_C2R; /* Chip ID2 Register */
- AT91_REG DBGU_FNTR; /* Force NTRST Register */
- AT91_REG Reserved1[45]; /* */
- AT91_REG DBGU_RPR; /* Receive Pointer Register */
- AT91_REG DBGU_RCR; /* Receive Counter Register */
- AT91_REG DBGU_TPR; /* Transmit Pointer Register */
- AT91_REG DBGU_TCR; /* Transmit Counter Register */
- AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
- AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
- AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
- AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
- AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
- AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
-} AT91S_DBGU, *AT91PS_DBGU;
-
-
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_SMC2 {
- AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */
-} AT91S_SMC2, *AT91PS_SMC2;
-
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Ethernet MAC */
-/* ***************************************************************************** */
-typedef struct _AT91S_EMAC {
- AT91_REG EMAC_CTL; /* Network Control Register */
- AT91_REG EMAC_CFG; /* Network Configuration Register */
- AT91_REG EMAC_SR; /* Network Status Register */
- AT91_REG EMAC_TAR; /* Transmit Address Register */
- AT91_REG EMAC_TCR; /* Transmit Control Register */
- AT91_REG EMAC_TSR; /* Transmit Status Register */
- AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */
- AT91_REG Reserved0[1]; /* */
- AT91_REG EMAC_RSR; /* Receive Status Register */
- AT91_REG EMAC_ISR; /* Interrupt Status Register */
- AT91_REG EMAC_IER; /* Interrupt Enable Register */
- AT91_REG EMAC_IDR; /* Interrupt Disable Register */
- AT91_REG EMAC_IMR; /* Interrupt Mask Register */
- AT91_REG EMAC_MAN; /* PHY Maintenance Register */
- AT91_REG Reserved1[2]; /* */
- AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */
- AT91_REG EMAC_SCOL; /* Single Collision Frame Register */
- AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */
- AT91_REG EMAC_OK; /* Frames Received OK Register */
- AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */
- AT91_REG EMAC_ALE; /* Alignment Error Register */
- AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */
- AT91_REG EMAC_LCOL; /* Late Collision Register */
- AT91_REG EMAC_ECOL; /* Excessive Collision Register */
- AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
- AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */
- AT91_REG EMAC_CDE; /* Code Error Register */
- AT91_REG EMAC_ELR; /* Excessive Length Error Register */
- AT91_REG EMAC_RJB; /* Receive Jabber Register */
- AT91_REG EMAC_USF; /* Undersize Frame Register */
- AT91_REG EMAC_SQEE; /* SQE Test Error Register */
- AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */
- AT91_REG Reserved2[3]; /* */
- AT91_REG EMAC_HSH; /* Hash Address High[63:32] */
- AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */
- AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */
- AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */
- AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */
- AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */
- AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */
- AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */
- AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */
- AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */
-} AT91S_EMAC, *AT91PS_EMAC;
-
-/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */
-#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */
-#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */
-#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */
-#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */
-#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */
-#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */
-#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */
-#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */
-#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */
-#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */
-#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */
-
-/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */
-#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */
-#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */
-#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */
-#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */
-#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */
-
-#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */
-#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */
-#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */
-#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
-
-#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) /* (PIOA) PIO Disable Register */
-#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */
-#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) /* Pin Controlled by PC0 */
-#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) /* Burst Flash Clock */
-#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) /* DBGU Debug Receive Data */
-#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) /* Pin Controlled by PA31 */
-#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) /* DBGU Debug Transmit Data */
-
-#define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */
-#define AT91C_ID_TC0 ((unsigned int) 17) /* Timer Counter 0 */
-#define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC */
-
-#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) /* Pin Controlled by PC1 */
-#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /* Burst Flash Ready */
-#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) /* Pin Controlled by PC3 */
-#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) /* Burst Flash Address Advance / SmartMedia Write Enable */
-#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) /* Pin Controlled by PC2 */
-#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) /* Burst Flash Address Valid */
-#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB1 */
-
-#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
-#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
-#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */
-#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */
-#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */
-#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */
-#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */
-#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */
-#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */
-#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */
-#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */
-#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */
-#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */
-#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */
-
-#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */
-#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */
-#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */
-#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) /* (EMAC) Receive enable. */
-#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) /* (EMAC) Transmit enable. */
-#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) /* (EMAC) */
-#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */
-#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */
-#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */
-#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */
-#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */
-#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */
-#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) /* (EMAC) Clear statistics registers. */
-#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */
-#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */
-#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 0) /* (EMAC) */
-#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) /* (EMAC) Management port enable. */
-#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */
-#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */
-#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */
-#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock */
-#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) /* Pin Controlled by PA14 */
-#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error */
-#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) /* Pin Controlled by PA13 */
-#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1 */
-#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) /* Pin Controlled by PA12 */
-#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0 */
-#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) /* Pin Controlled by PA11 */
-#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
-#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */
-#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1 */
-#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9 */
-#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) /* Ethernet MAC Transmit Data 0 */
-#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) /* Pin Controlled by PA8 */
-#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable */
-#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */
-#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */
-#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */
-#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */
-#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */
-#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) /* Pin Controlled by PB19 */
-#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) /* USART 1 Data Terminal ready */
-#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) /* Ethernet MAC Receive Clock */
-#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) /* Pin Controlled by PB18 */
-#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) /* USART 1 Ring Indicator */
-#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) /* Ethernet MAC Collision Detected */
-#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) /* Pin Controlled by PB17 */
-#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) /* SSC Receive Frame Sync 2 */
-#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) /* Ethernet MAC Receive Data Valid */
-#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) /* Pin Controlled by PB16 */
-#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) /* SSC Receive Clock 2 */
-#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) /* Ethernet MAC Receive Data 3 */
-#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) /* Pin Controlled by PB15 */
-#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) /* SSC Receive Data 2 */
-#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) /* Ethernet MAC Receive Data 2 */
-#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) /* Pin Controlled by PB14 */
-#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) /* SSC Transmit Data 2 */
-#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) /* Ethernet MAC Transmikt Coding Error */
-#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) /* Pin Controlled by PB13 */
-#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) /* SSC Transmit Clock 2 */
-#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) /* Ethernet MAC Transmit Data 3 */
-#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) /* Pin Controlled by PB12 */
-#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */
-#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */
-
-#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */
-#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
-#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */
-
-#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */
-#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
-#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
-#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */
-#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */
-
-#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */
-#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */
-#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */
-#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
-#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */
-#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
-#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */
-#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */
-#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */
-#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */
-#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */
-#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */
-#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */
-#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */
-#endif
--- /dev/null
+/* ---------------------------------------------------------------------------- */
+/* ATMEL Microcontroller Software Support - ROUSSET - */
+/* ---------------------------------------------------------------------------- */
+/* The software is delivered "AS IS" without warranty or condition of any */
+/* kind, either express, implied or statutory. This includes without */
+/* limitation any warranty or condition with respect to merchantability or */
+/* fitness for any particular purpose, or against the infringements of */
+/* intellectual property rights of others. */
+/* ---------------------------------------------------------------------------- */
+/* File Name : AT91RM9200.h */
+/* Object : AT91RM9200 definitions */
+/* Generated : AT91 SW Application Group 10/29/2002 (16:10:51) */
+#ifndef AT91RM9200_H
+#define AT91RM9200_H
+
+typedef volatile unsigned int AT91_REG;/* Hardware register definition */
+
+/* ***************************************************************************** */
+/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_TC {
+ AT91_REG TC_CCR; /* Channel Control Register */
+ AT91_REG TC_CMR; /* Channel Mode Register */
+ AT91_REG Reserved0[2]; /* */
+ AT91_REG TC_CV; /* Counter Value */
+ AT91_REG TC_RA; /* Register A */
+ AT91_REG TC_RB; /* Register B */
+ AT91_REG TC_RC; /* Register C */
+ AT91_REG TC_SR; /* Status Register */
+ AT91_REG TC_IER; /* Interrupt Enable Register */
+ AT91_REG TC_IDR; /* Interrupt Disable Register */
+ AT91_REG TC_IMR; /* Interrupt Mask Register */
+} AT91S_TC, *AT91PS_TC;
+
+/* ***************************************************************************** */
+/* SOFTWARE API DEFINITION FOR Usart */
+/* ***************************************************************************** */
+typedef struct _AT91S_USART {
+ AT91_REG US_CR; /* Control Register */
+ AT91_REG US_MR; /* Mode Register */
+ AT91_REG US_IER; /* Interrupt Enable Register */
+ AT91_REG US_IDR; /* Interrupt Disable Register */
+ AT91_REG US_IMR; /* Interrupt Mask Register */
+ AT91_REG US_CSR; /* Channel Status Register */
+ AT91_REG US_RHR; /* Receiver Holding Register */
+ AT91_REG US_THR; /* Transmitter Holding Register */
+ AT91_REG US_BRGR; /* Baud Rate Generator Register */
+ AT91_REG US_RTOR; /* Receiver Time-out Register */
+ AT91_REG US_TTGR; /* Transmitter Time-guard Register */
+ AT91_REG Reserved0[5]; /* */
+ AT91_REG US_FIDI; /* FI_DI_Ratio Register */
+ AT91_REG US_NER; /* Nb Errors Register */
+ AT91_REG US_XXR; /* XON_XOFF Register */
+ AT91_REG US_IF; /* IRDA_FILTER Register */
+ AT91_REG Reserved1[44]; /* */
+ AT91_REG US_RPR; /* Receive Pointer Register */
+ AT91_REG US_RCR; /* Receive Counter Register */
+ AT91_REG US_TPR; /* Transmit Pointer Register */
+ AT91_REG US_TCR; /* Transmit Counter Register */
+ AT91_REG US_RNPR; /* Receive Next Pointer Register */
+ AT91_REG US_RNCR; /* Receive Next Counter Register */
+ AT91_REG US_TNPR; /* Transmit Next Pointer Register */
+ AT91_REG US_TNCR; /* Transmit Next Counter Register */
+ AT91_REG US_PTCR; /* PDC Transfer Control Register */
+ AT91_REG US_PTSR; /* PDC Transfer Status Register */
+} AT91S_USART, *AT91PS_USART;
+
+/* ***************************************************************************** */
+/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
+/* ***************************************************************************** */
+typedef struct _AT91S_PIO {
+ AT91_REG PIO_PER; /* PIO Enable Register */
+ AT91_REG PIO_PDR; /* PIO Disable Register */
+ AT91_REG PIO_PSR; /* PIO Status Register */
+ AT91_REG Reserved0[1]; /* */
+ AT91_REG PIO_OER; /* Output Enable Register */
+ AT91_REG PIO_ODR; /* Output Disable Registerr */
+ AT91_REG PIO_OSR; /* Output Status Register */
+ AT91_REG Reserved1[1]; /* */
+ AT91_REG PIO_IFER; /* Input Filter Enable Register */
+ AT91_REG PIO_IFDR; /* Input Filter Disable Register */
+ AT91_REG PIO_IFSR; /* Input Filter Status Register */
+ AT91_REG Reserved2[1]; /* */
+ AT91_REG PIO_SODR; /* Set Output Data Register */
+ AT91_REG PIO_CODR; /* Clear Output Data Register */
+ AT91_REG PIO_ODSR; /* Output Data Status Register */
+ AT91_REG PIO_PDSR; /* Pin Data Status Register */
+ AT91_REG PIO_IER; /* Interrupt Enable Register */
+ AT91_REG PIO_IDR; /* Interrupt Disable Register */
+ AT91_REG PIO_IMR; /* Interrupt Mask Register */
+ AT91_REG PIO_ISR; /* Interrupt Status Register */
+ AT91_REG PIO_MDER; /* Multi-driver Enable Register */
+ AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
+ AT91_REG PIO_MDSR; /* Multi-driver Status Register */
+ AT91_REG Reserved3[1]; /* */
+ AT91_REG PIO_PPUDR; /* Pull-up Disable Register */
+ AT91_REG PIO_PPUER; /* Pull-up Enable Register */
+ AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */
+ AT91_REG Reserved4[1]; /* */
+ AT91_REG PIO_ASR; /* Select A Register */
+ AT91_REG PIO_BSR; /* Select B Register */
+ AT91_REG PIO_ABSR; /* AB Select Status Register */
+ AT91_REG Reserved5[9]; /* */
+ AT91_REG PIO_OWER; /* Output Write Enable Register */
+ AT91_REG PIO_OWDR; /* Output Write Disable Register */
+ AT91_REG PIO_OWSR; /* Output Write Status Register */
+} AT91S_PIO, *AT91PS_PIO;
+
+
+/* ***************************************************************************** */
+/* SOFTWARE API DEFINITION FOR Debug Unit */
+/* ***************************************************************************** */
+typedef struct _AT91S_DBGU {
+ AT91_REG DBGU_CR; /* Control Register */
+ AT91_REG DBGU_MR; /* Mode Register */
+ AT91_REG DBGU_IER; /* Interrupt Enable Register */
+ AT91_REG DBGU_IDR; /* Interrupt Disable Register */
+ AT91_REG DBGU_IMR; /* Interrupt Mask Register */
+ AT91_REG DBGU_CSR; /* Channel Status Register */
+ AT91_REG DBGU_RHR; /* Receiver Holding Register */
+ AT91_REG DBGU_THR; /* Transmitter Holding Register */
+ AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
+ AT91_REG Reserved0[7]; /* */
+ AT91_REG DBGU_C1R; /* Chip ID1 Register */
+ AT91_REG DBGU_C2R; /* Chip ID2 Register */
+ AT91_REG DBGU_FNTR; /* Force NTRST Register */
+ AT91_REG Reserved1[45]; /* */
+ AT91_REG DBGU_RPR; /* Receive Pointer Register */
+ AT91_REG DBGU_RCR; /* Receive Counter Register */
+ AT91_REG DBGU_TPR; /* Transmit Pointer Register */
+ AT91_REG DBGU_TCR; /* Transmit Counter Register */
+ AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
+ AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
+ AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
+ AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
+ AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
+ AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
+} AT91S_DBGU, *AT91PS_DBGU;
+
+
+/* ***************************************************************************** */
+/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_SMC2 {
+ AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */
+} AT91S_SMC2, *AT91PS_SMC2;
+
+/* ***************************************************************************** */
+/* SOFTWARE API DEFINITION FOR Ethernet MAC */
+/* ***************************************************************************** */
+typedef struct _AT91S_EMAC {
+ AT91_REG EMAC_CTL; /* Network Control Register */
+ AT91_REG EMAC_CFG; /* Network Configuration Register */
+ AT91_REG EMAC_SR; /* Network Status Register */
+ AT91_REG EMAC_TAR; /* Transmit Address Register */
+ AT91_REG EMAC_TCR; /* Transmit Control Register */
+ AT91_REG EMAC_TSR; /* Transmit Status Register */
+ AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */
+ AT91_REG Reserved0[1]; /* */
+ AT91_REG EMAC_RSR; /* Receive Status Register */
+ AT91_REG EMAC_ISR; /* Interrupt Status Register */
+ AT91_REG EMAC_IER; /* Interrupt Enable Register */
+ AT91_REG EMAC_IDR; /* Interrupt Disable Register */
+ AT91_REG EMAC_IMR; /* Interrupt Mask Register */
+ AT91_REG EMAC_MAN; /* PHY Maintenance Register */
+ AT91_REG Reserved1[2]; /* */
+ AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */
+ AT91_REG EMAC_SCOL; /* Single Collision Frame Register */
+ AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */
+ AT91_REG EMAC_OK; /* Frames Received OK Register */
+ AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */
+ AT91_REG EMAC_ALE; /* Alignment Error Register */
+ AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */
+ AT91_REG EMAC_LCOL; /* Late Collision Register */
+ AT91_REG EMAC_ECOL; /* Excessive Collision Register */
+ AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
+ AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */
+ AT91_REG EMAC_CDE; /* Code Error Register */
+ AT91_REG EMAC_ELR; /* Excessive Length Error Register */
+ AT91_REG EMAC_RJB; /* Receive Jabber Register */
+ AT91_REG EMAC_USF; /* Undersize Frame Register */
+ AT91_REG EMAC_SQEE; /* SQE Test Error Register */
+ AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */
+ AT91_REG Reserved2[3]; /* */
+ AT91_REG EMAC_HSH; /* Hash Address High[63:32] */
+ AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */
+ AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */
+ AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */
+ AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */
+ AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */
+ AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */
+ AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */
+ AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */
+ AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */
+} AT91S_EMAC, *AT91PS_EMAC;
+
+/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */
+
+/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */
+
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
+
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) /* (PIOA) PIO Disable Register */
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */
+#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) /* Pin Controlled by PC0 */
+#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) /* Burst Flash Clock */
+#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) /* DBGU Debug Receive Data */
+#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) /* Pin Controlled by PA31 */
+#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) /* DBGU Debug Transmit Data */
+
+#define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */
+#define AT91C_ID_TC0 ((unsigned int) 17) /* Timer Counter 0 */
+#define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC */
+
+#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) /* Pin Controlled by PC1 */
+#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /* Burst Flash Ready */
+#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) /* Pin Controlled by PC3 */
+#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) /* Burst Flash Address Advance / SmartMedia Write Enable */
+#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) /* Pin Controlled by PC2 */
+#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) /* Burst Flash Address Valid */
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB1 */
+
+#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
+#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
+#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */
+#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */
+#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */
+#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */
+#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */
+#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */
+
+#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */
+#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */
+#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */
+#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) /* (EMAC) Receive enable. */
+#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) /* (EMAC) Transmit enable. */
+#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) /* (EMAC) */
+#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */
+#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */
+#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */
+#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */
+#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */
+#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */
+#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) /* (EMAC) Clear statistics registers. */
+#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */
+#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */
+#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 0) /* (EMAC) */
+#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) /* (EMAC) Management port enable. */
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */
+#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */
+#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock */
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) /* Pin Controlled by PA14 */
+#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error */
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) /* Pin Controlled by PA13 */
+#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1 */
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) /* Pin Controlled by PA12 */
+#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0 */
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) /* Pin Controlled by PA11 */
+#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */
+#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1 */
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9 */
+#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) /* Ethernet MAC Transmit Data 0 */
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) /* Pin Controlled by PA8 */
+#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable */
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */
+#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */
+#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */
+#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */
+#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */
+#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) /* Pin Controlled by PB19 */
+#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) /* USART 1 Data Terminal ready */
+#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) /* Ethernet MAC Receive Clock */
+#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) /* Pin Controlled by PB18 */
+#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) /* USART 1 Ring Indicator */
+#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) /* Ethernet MAC Collision Detected */
+#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) /* Pin Controlled by PB17 */
+#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) /* SSC Receive Frame Sync 2 */
+#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) /* Ethernet MAC Receive Data Valid */
+#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) /* Pin Controlled by PB16 */
+#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) /* SSC Receive Clock 2 */
+#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) /* Ethernet MAC Receive Data 3 */
+#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) /* Pin Controlled by PB15 */
+#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) /* SSC Receive Data 2 */
+#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) /* Ethernet MAC Receive Data 2 */
+#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) /* Pin Controlled by PB14 */
+#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) /* SSC Transmit Data 2 */
+#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) /* Ethernet MAC Transmikt Coding Error */
+#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) /* Pin Controlled by PB13 */
+#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) /* SSC Transmit Clock 2 */
+#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) /* Ethernet MAC Transmit Data 3 */
+#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) /* Pin Controlled by PB12 */
+#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */
+#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */
+
+#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
+#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */
+
+#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */
+#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
+#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
+#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */
+#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */
+#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) /* (PIOC) Set Output Data Register */
+#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */
+#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */
+
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */
+#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
+#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
+#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */
+#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */
+#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */
+#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */
+#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */
+#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */
+#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */
+#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-at91/hardware.h
+ *
+ * Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+
+#ifndef __ASSEMBLY__
+#include "AT91RM9200.h"
+#else
+#include "AT91RM9200_inc.h"
+#endif
+
+/* AT91RM92000 clocks */
+#define AT91_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
+#define AT91_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
+#define AT91_SLOW_CLOCK 32768 /* slow clock */
+
+/* Virtual and Physical base address for system peripherals */
+#define AT91_SYS_BASE 0xFFFFF000 /*4K */
+
+/* Virtual and Physical base addresses of user peripherals */
+#define AT91_SPI_BASE 0xFFFE0000 /*16K */
+#define AT91_SSC2_BASE 0xFFFD8000 /*16K */
+#define AT91_SSC1_BASE 0xFFFD4000 /*16K */
+#define AT91_SSC0_BASE 0xFFFD0000 /*16K */
+#define AT91_USART3_BASE 0xFFFCC000 /*16K */
+#define AT91_USART2_BASE 0xFFFC8000 /*16K */
+#define AT91_USART1_BASE 0xFFFC4000 /*16K */
+#define AT91_USART0_BASE 0xFFFC0000 /*16K */
+#define AT91_EMAC_BASE 0xFFFBC000 /*16K */
+#define AT91_TWI_BASE 0xFFFB8000 /*16K */
+#define AT91_MCI_BASE 0xFFFB4000 /*16K */
+#define AT91_UDP_BASE 0xFFFB0000 /*16K */
+#define AT91_TCB1_BASE 0xFFFA4000 /*16K */
+#define AT91_TCB0_BASE 0xFFFA0000 /*16K */
+
+/*
+ * Where in virtual memory the IO devices (timers, system controllers
+ * and so on)
+ */
+#define AT91_IO_BASE 0xF0000000 /* Virt/Phys Address of IO */
+
+/* FLASH */
+#define AT91_FLASH_BASE 0x10000000 /* NCS0 */
+
+/* SDRAM */
+#define AT91_SDRAM_BASE 0x20000000 /* NCS1 */
+
+/* SmartMedia */
+#define AT91_SMARTMEDIA_BASE 0x40000000 /* NCS3 */
+
+/* Definition of interrupt priority levels */
+#define AT91C_AIC_PRIOR_0 AT91C_AIC_PRIOR_LOWEST
+#define AT91C_AIC_PRIOR_1 ((unsigned int) 0x1)
+#define AT91C_AIC_PRIOR_2 ((unsigned int) 0x2)
+#define AT91C_AIC_PRIOR_3 ((unsigned int) 0x3)
+#define AT91C_AIC_PRIOR_4 ((unsigned int) 0x4)
+#define AT91C_AIC_PRIOR_5 ((unsigned int) 0x5)
+#define AT91C_AIC_PRIOR_6 ((unsigned int) 0x6)
+#define AT91C_AIC_PRIOR_7 AT91C_AIC_PRIOR_HIGEST
+
+#endif
serial_init, /* serial communications setup */
console_init_f,
display_banner, /* say that we are here */
+ checkboard,
init_func_ram,
NULL,
};
projects / u-boot / commitdiff