powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020

The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we
need to enable for them to function.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 6f256cf7a7b0493b1bc0ad64d24dbabc105f8b68..b3da970d4201bb34ed29d20f49080266cb56e20c 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -436,6 +436,23 @@ int cpu_init_r(void)
        isync();
 #endif
 
+#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
+       {
+               ccsr_usb_phy_t *usb_phy1 =
+                       (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+               out_be32(&usb_phy1->usb_enable_override,
+                               CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
+       }
+#endif
+#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
+       {
+               ccsr_usb_phy_t *usb_phy2 =
+                       (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
+               out_be32(&usb_phy2->usb_enable_override,
+                               CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
+       }
+#endif
+
        return 0;
 }
 

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 88bc0309c0570c8eef5a32368ed425e9ebb38073..d93586a7bdd2b904eb84d4bebe621576d1a766a5 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -264,6 +264,8 @@
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
 #define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 
 #elif defined(CONFIG_PPC_P3041)
 #define CONFIG_MAX_CPUS                        4
@@ -275,6 +277,8 @@
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 
 #elif defined(CONFIG_PPC_P4040)
 #define CONFIG_MAX_CPUS                        4
@@ -317,6 +321,8 @@
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 
 #elif defined(CONFIG_PPC_P5020)
 #define CONFIG_MAX_CPUS                        2
@@ -328,6 +334,8 @@
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_NUM_DDR_CONTROLLERS     2
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 
 #else
 #error Processor type not defined for this platform

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 4c7105722b8df03ebff8feb56a342f39b8078eb1..5395c7f93ecc60980dce941697417cdfcc2ad8ea 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2288,6 +2288,13 @@ typedef struct ccsr_pme {
        u8      res4[0x400];
 } ccsr_pme_t;
 
+typedef struct ccsr_usb_phy {
+       u8      res0[0x18];
+       u32     usb_enable_override;
+       u8      res[0xe4];
+} ccsr_usb_phy_t;
+#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
+
 #ifdef CONFIG_FSL_CORENET
 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET      0x0000
 #define CONFIG_SYS_MPC85xx_DDR_OFFSET          0x8000
@@ -2310,6 +2317,8 @@ typedef struct ccsr_pme {
 #define CONFIG_SYS_MPC85xx_USB1_OFFSET         0x210000
 #define CONFIG_SYS_MPC85xx_USB2_OFFSET         0x211000
 #define CONFIG_SYS_MPC85xx_USB_OFFSET          CONFIG_SYS_MPC85xx_USB1_OFFSET
+#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
+#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET                0x220000
 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET                0x221000
 #define CONFIG_SYS_FSL_SEC_OFFSET              0x300000
@@ -2432,6 +2441,10 @@ typedef struct ccsr_pme {
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
 #define CONFIG_SYS_FSL_SEC_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
 #define CONFIG_SYS_FSL_FM1_ADDR \