ppc4xx: Corrected EBC register bit definitions

Corrected the bit field positions of the external master priority low
and the external master priority high values in the EBC configuration
register. These bit field positions differ between PPC405 and PPC440
processors

Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/include/asm-ppc/ppc4xx-ebc.h b/include/asm-ppc/ppc4xx-ebc.h
index 9680f70d6b0fac3f6c1ada6d1409c572c441f96c..9c17e46252267c954612f327e1340989138d0e16 100644 (file)
--- a/include/asm-ppc/ppc4xx-ebc.h
+++ b/include/asm-ppc/ppc4xx-ebc.h
@@ -25,14 +25,24 @@
 #define _PPC4xx_EBC_H_
 
 /*
- * Currently there are two register layout versions for the
- * IBM EBC core used on 4xx PPC's:
+ * Currently there are two register layout versions for the IBM EBC core
+ * used on 4xx PPC's. The following grouping lists the first layout.
+ * Within this group there is a slight variation concerning the bit field
+ * position of the EMPL and EMPH fields:
  */
 #if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
     defined(CONFIG_405EP) || \
     defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define CONFIG_EBC_PPC4xx_IBM_VER1
+#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
+    defined(CONFIG_405EP)
+#define EBC_CFG_EMPH_POS       8
+#define EBC_CFG_EMPL_POS       6
+#else
+#define EBC_CFG_EMPH_POS       6
+#define EBC_CFG_EMPL_POS       8
+#endif
 #endif
 
 /*
@@ -143,10 +153,12 @@
 #define EBC_CFG_EBTC_MASK      PPC_REG_VAL(0, 0x1)
 #define EBC_CFG_EBTC_HI                PPC_REG_VAL(0, 0x0)
 #define EBC_CFG_EBTC_DRIVEN    PPC_REG_VAL(0, 0x1)
-#define EBC_CFG_EMPH_MASK      PPC_REG_VAL(6, 0x3)
-#define EBC_CFG_EMPH_ENCODE(n) PPC_REG_VAL(6, (static_cast(u32, n)) & 0x3)
-#define EBC_CFG_EMPL_MASK      PPC_REG_VAL(8, 0x3)
-#define EBC_CFG_EMPL_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0x3)
+#define EBC_CFG_EMPH_MASK      PPC_REG_VAL(EBC_CFG_EMPH_POS, 0x3)
+#define EBC_CFG_EMPH_ENCODE(n) PPC_REG_VAL(EBC_CFG_EMPH_POS, \
+                                               (static_cast(u32, n)) & 0x3)
+#define EBC_CFG_EMPL_MASK      PPC_REG_VAL(EBC_CFG_EMPL_POS, 0x3)
+#define EBC_CFG_EMPL_ENCODE(n) PPC_REG_VAL(EBC_CFG_EMPH_POS, \
+                                               (static_cast(u32, n)) & 0x3)
 #define EBC_CFG_CSTC_MASK      PPC_REG_VAL(9, 0x1)
 #define EBC_CFG_CSTC_HI                PPC_REG_VAL(9, 0x0)
 #define EBC_CFG_CSTC_DRIVEN    PPC_REG_VAL(9, 0x1)