x86: link: Add PCH driver to support SPI Flash

U-Boot on coreboot does not have a driver for the PCH so cannot see the
SPI peripheral now that it has moved inside the PCH. Add a simple driver so
that SPI flash works again.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index fa415dd42be6814be9a851c9c950b8baacbde6f7..67eb14ce99406dd90c6bb819715a9d94f8f2d4c5 100644 (file)
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -34,3 +34,14 @@ U_BOOT_DRIVER(pci_x86_drv) = {
        .of_match       = pci_x86_ids,
        .ops            = &pci_x86_ops,
 };
+
+static const struct udevice_id generic_pch_ids[] = {
+       { .compatible = "intel,pch" },
+       { }
+};
+
+U_BOOT_DRIVER(generic_pch_drv) = {
+       .name           = "pch",
+       .id             = UCLASS_PCH,
+       .of_match       = generic_pch_ids,
+};

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index b450c3c55f5664de00fb1fcb0a4396f02b6783cc..7c7034c7ebe25a8dce184ff8ad1de32a55091cb4 100644 (file)
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -181,7 +181,7 @@
 
                pch {
                        reg = <0x0000f800 0 0 0 0>;
-                       compatible = "intel,bd82x6x";
+                       compatible = "intel,bd82x6x", "intel,pch";
                        u-boot,dm-pre-reloc;
                        #address-cells = <1>;
                        #size-cells = <1>;