]> git.sur5r.net Git - u-boot/commitdiff
net, davinci_emac: make clock divider in MDIO control register configurable
authorHeiko Schocher <hs@denx.de>
Tue, 1 Nov 2011 20:00:27 +0000 (20:00 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Thu, 3 Nov 2011 21:56:24 +0000 (22:56 +0100)
Define CONFIG_SYS_EMAC_TI_CLKDIV for setting the clkdiv value
in the MDIO control register.

Signed-off-by: Heiko Schocher <hs@denx.de>
cc: Sandeep Paulraj <s-paulraj@ti.com>
cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
drivers/net/davinci_emac.c

index a9004805dc53a110386f4c55a78f8b4b95db1d89..fa31159a0efc9115ce378ab5e67b67c8fb8ac8be 100644 (file)
@@ -53,6 +53,11 @@ unsigned int emac_dbg = 0;
 #define emac_gigabit_enable(phy_addr)  /* no gigabit to enable */
 #endif
 
+#if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
+#define CONFIG_SYS_EMAC_TI_CLKDIV      ((EMAC_MDIO_BUS_FREQ / \
+               EMAC_MDIO_CLOCK_FREQ) - 1)
+#endif
+
 static void davinci_eth_mdio_enable(void);
 
 static int gen_init_phy(int phy_addr);
@@ -131,7 +136,7 @@ static void davinci_eth_mdio_enable(void)
 {
        u_int32_t       clkdiv;
 
-       clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
+       clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
 
        writel((clkdiv & 0xff) |
               MDIO_CONTROL_ENABLE |
@@ -473,7 +478,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
 #endif
 
        /* Init MDIO & get link state */
-       clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
+       clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
        writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
               &adap_mdio->CONTROL);