endif
ifdef CONFIG_CMD_SF
-COBJS-y += spi_flash.o
+COBJS-y += sf.o
endif
-COBJS-$(CONFIG_SPI_FLASH) += spi_flash_probe.o spi_flash_ops.o
+COBJS-$(CONFIG_SPI_FLASH) += sf_probe.o sf_ops.o
COBJS-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
COBJS-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
--- /dev/null
+/*
+ * SPI flash interface
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <spi.h>
+
+static int spi_flash_read_write(struct spi_slave *spi,
+ const u8 *cmd, size_t cmd_len,
+ const u8 *data_out, u8 *data_in,
+ size_t data_len)
+{
+ unsigned long flags = SPI_XFER_BEGIN;
+ int ret;
+
+ if (data_len == 0)
+ flags |= SPI_XFER_END;
+
+ ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
+ if (ret) {
+ debug("SF: Failed to send command (%zu bytes): %d\n",
+ cmd_len, ret);
+ } else if (data_len != 0) {
+ ret = spi_xfer(spi, data_len * 8, data_out, data_in,
+ SPI_XFER_END);
+ if (ret)
+ debug("SF: Failed to transfer %zu bytes of data: %d\n",
+ data_len, ret);
+ }
+
+ return ret;
+}
+
+int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
+ size_t cmd_len, void *data, size_t data_len)
+{
+ return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len);
+}
+
+int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len)
+{
+ return spi_flash_cmd_read(spi, &cmd, 1, response, len);
+}
+
+int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
+ const void *data, size_t data_len)
+{
+ return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
+}
--- /dev/null
+/*
+ * SPI flash internal definitions
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _SPI_FLASH_INTERNAL_H_
+#define _SPI_FLASH_INTERNAL_H_
+
+#define SPI_FLASH_16MB_BOUN 0x1000000
+
+/* SECT flags */
+#define SECT_4K (1 << 1)
+#define SECT_32K (1 << 2)
+#define E_FSR (1 << 3)
+
+/* Erase commands */
+#define CMD_ERASE_4K 0x20
+#define CMD_ERASE_32K 0x52
+#define CMD_ERASE_CHIP 0xc7
+#define CMD_ERASE_64K 0xd8
+
+/* Write commands */
+#define CMD_WRITE_STATUS 0x01
+#define CMD_PAGE_PROGRAM 0x02
+#define CMD_WRITE_DISABLE 0x04
+#define CMD_READ_STATUS 0x05
+#define CMD_WRITE_ENABLE 0x06
+#define CMD_READ_CONFIG 0x35
+#define CMD_FLAG_STATUS 0x70
+
+/* Read commands */
+#define CMD_READ_ARRAY_SLOW 0x03
+#define CMD_READ_ARRAY_FAST 0x0b
+#define CMD_READ_ID 0x9f
+
+/* Bank addr access commands */
+#ifdef CONFIG_SPI_FLASH_BAR
+# define CMD_BANKADDR_BRWR 0x17
+# define CMD_BANKADDR_BRRD 0x16
+# define CMD_EXTNADDR_WREAR 0xC5
+# define CMD_EXTNADDR_RDEAR 0xC8
+#endif
+
+/* Common status */
+#define STATUS_WIP 0x01
+#define STATUS_PEC 0x80
+
+/* Flash timeout values */
+#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
+#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
+#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
+
+/* SST specific */
+#ifdef CONFIG_SPI_FLASH_SST
+# define SST_WP 0x01 /* Supports AAI word program */
+# define CMD_SST_BP 0x02 /* Byte Program */
+# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
+
+int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
+ const void *buf);
+#endif
+
+/* Send a single-byte command to the device and read the response */
+int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
+
+/*
+ * Send a multi-byte command to the device and read the response. Used
+ * for flash array reads, etc.
+ */
+int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
+ size_t cmd_len, void *data, size_t data_len);
+
+/*
+ * Send a multi-byte command to the device followed by (optional)
+ * data. Used for programming the flash array, etc.
+ */
+int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
+ const void *data, size_t data_len);
+
+
+/* Flash erase(sectors) operation, support all possible erase commands */
+int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
+
+/* Program the status register */
+int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
+
+/* Set quad enbale bit */
+int spi_flash_set_qeb(struct spi_flash *flash);
+
+/* Enable writing on the SPI flash */
+static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
+{
+ return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
+}
+
+/* Disable writing on the SPI flash */
+static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
+{
+ return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
+}
+
+/*
+ * Send the read status command to the device and wait for the wip
+ * (write-in-progress) bit to clear itself.
+ */
+int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
+
+/*
+ * Used for spi_flash write operation
+ * - SPI claim
+ * - spi_flash_cmd_write_enable
+ * - spi_flash_cmd_write
+ * - spi_flash_cmd_wait_ready
+ * - SPI release
+ */
+int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
+ size_t cmd_len, const void *buf, size_t buf_len);
+
+/*
+ * Flash write operation, support all possible write commands.
+ * Write the requested data out breaking it up into multiple write
+ * commands as needed per the write size.
+ */
+int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ size_t len, const void *buf);
+
+/*
+ * Same as spi_flash_cmd_read() except it also claims/releases the SPI
+ * bus. Used as common part of the ->read() operation.
+ */
+int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
+ size_t cmd_len, void *data, size_t data_len);
+
+/* Flash read operation, support all possible read commands */
+int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ size_t len, void *data);
+
+#endif /* _SPI_FLASH_INTERNAL_H_ */
--- /dev/null
+/*
+ * SPI flash operations
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
+ * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <watchdog.h>
+
+#include "sf_internal.h"
+
+static void spi_flash_addr(u32 addr, u8 *cmd)
+{
+ /* cmd[0] is actual command */
+ cmd[1] = addr >> 16;
+ cmd[2] = addr >> 8;
+ cmd[3] = addr >> 0;
+}
+
+int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
+{
+ u8 cmd;
+ int ret;
+
+ cmd = CMD_WRITE_STATUS;
+ ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
+ if (ret < 0) {
+ debug("SF: fail to write status register\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_SPI_FLASH_BAR
+static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
+{
+ u8 cmd;
+ int ret;
+
+ if (flash->bank_curr == bank_sel) {
+ debug("SF: not require to enable bank%d\n", bank_sel);
+ return 0;
+ }
+
+ cmd = flash->bank_write_cmd;
+ ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
+ if (ret < 0) {
+ debug("SF: fail to write bank register\n");
+ return ret;
+ }
+ flash->bank_curr = bank_sel;
+
+ return 0;
+}
+#endif
+
+int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
+{
+ struct spi_slave *spi = flash->spi;
+ unsigned long timebase;
+ int ret;
+ u8 status;
+ u8 check_status = 0x0;
+ u8 poll_bit = STATUS_WIP;
+ u8 cmd = flash->poll_cmd;
+
+ if (cmd == CMD_FLAG_STATUS) {
+ poll_bit = STATUS_PEC;
+ check_status = poll_bit;
+ }
+
+ ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
+ if (ret) {
+ debug("SF: fail to read %s status register\n",
+ cmd == CMD_READ_STATUS ? "read" : "flag");
+ return ret;
+ }
+
+ timebase = get_timer(0);
+ do {
+ WATCHDOG_RESET();
+
+ ret = spi_xfer(spi, 8, NULL, &status, 0);
+ if (ret)
+ return -1;
+
+ if ((status & poll_bit) == check_status)
+ break;
+
+ } while (get_timer(timebase) < timeout);
+
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
+
+ if ((status & poll_bit) == check_status)
+ return 0;
+
+ /* Timed out */
+ debug("SF: time out!\n");
+ return -1;
+}
+
+int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
+ size_t cmd_len, const void *buf, size_t buf_len)
+{
+ struct spi_slave *spi = flash->spi;
+ unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
+ int ret;
+
+ if (buf == NULL)
+ timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: unable to claim SPI bus\n");
+ return ret;
+ }
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret < 0) {
+ debug("SF: enabling write failed\n");
+ return ret;
+ }
+
+ ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
+ if (ret < 0) {
+ debug("SF: write cmd failed\n");
+ return ret;
+ }
+
+ ret = spi_flash_cmd_wait_ready(flash, timeout);
+ if (ret < 0) {
+ debug("SF: write %s timed out\n",
+ timeout == SPI_FLASH_PROG_TIMEOUT ?
+ "program" : "page erase");
+ return ret;
+ }
+
+ spi_release_bus(spi);
+
+ return ret;
+}
+
+int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+{
+ u32 erase_size;
+ u8 cmd[4];
+ int ret = -1;
+
+ erase_size = flash->erase_size;
+ if (offset % erase_size || len % erase_size) {
+ debug("SF: Erase offset/length not multiple of erase size\n");
+ return -1;
+ }
+
+ cmd[0] = flash->erase_cmd;
+ while (len) {
+#ifdef CONFIG_SPI_FLASH_BAR
+ u8 bank_sel;
+
+ bank_sel = offset / SPI_FLASH_16MB_BOUN;
+
+ ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
+ if (ret) {
+ debug("SF: fail to set bank%d\n", bank_sel);
+ return ret;
+ }
+#endif
+ spi_flash_addr(offset, cmd);
+
+ debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
+ cmd[2], cmd[3], offset);
+
+ ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
+ if (ret < 0) {
+ debug("SF: erase failed\n");
+ break;
+ }
+
+ offset += erase_size;
+ len -= erase_size;
+ }
+
+ return ret;
+}
+
+int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ size_t len, const void *buf)
+{
+ unsigned long byte_addr, page_size;
+ size_t chunk_len, actual;
+ u8 cmd[4];
+ int ret = -1;
+
+ page_size = flash->page_size;
+
+ cmd[0] = CMD_PAGE_PROGRAM;
+ for (actual = 0; actual < len; actual += chunk_len) {
+#ifdef CONFIG_SPI_FLASH_BAR
+ u8 bank_sel;
+
+ bank_sel = offset / SPI_FLASH_16MB_BOUN;
+
+ ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
+ if (ret) {
+ debug("SF: fail to set bank%d\n", bank_sel);
+ return ret;
+ }
+#endif
+ byte_addr = offset % page_size;
+ chunk_len = min(len - actual, page_size - byte_addr);
+
+ if (flash->spi->max_write_size)
+ chunk_len = min(chunk_len, flash->spi->max_write_size);
+
+ spi_flash_addr(offset, cmd);
+
+ debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
+ buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+
+ ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
+ buf + actual, chunk_len);
+ if (ret < 0) {
+ debug("SF: write failed\n");
+ break;
+ }
+
+ offset += chunk_len;
+ }
+
+ return ret;
+}
+
+int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
+ size_t cmd_len, void *data, size_t data_len)
+{
+ struct spi_slave *spi = flash->spi;
+ int ret;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: unable to claim SPI bus\n");
+ return ret;
+ }
+
+ ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
+ if (ret < 0) {
+ debug("SF: read cmd failed\n");
+ return ret;
+ }
+
+ spi_release_bus(spi);
+
+ return ret;
+}
+
+int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ size_t len, void *data)
+{
+ u8 cmd[5], bank_sel = 0;
+ u32 remain_len, read_len;
+ int ret = -1;
+
+ /* Handle memory-mapped SPI */
+ if (flash->memory_map) {
+ memcpy(data, flash->memory_map + offset, len);
+ return 0;
+ }
+
+ cmd[0] = CMD_READ_ARRAY_FAST;
+ cmd[4] = 0x00;
+
+ while (len) {
+#ifdef CONFIG_SPI_FLASH_BAR
+ bank_sel = offset / SPI_FLASH_16MB_BOUN;
+
+ ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
+ if (ret) {
+ debug("SF: fail to set bank%d\n", bank_sel);
+ return ret;
+ }
+#endif
+ remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset);
+ if (len < remain_len)
+ read_len = len;
+ else
+ read_len = remain_len;
+
+ spi_flash_addr(offset, cmd);
+
+ ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
+ data, read_len);
+ if (ret < 0) {
+ debug("SF: read failed\n");
+ break;
+ }
+
+ offset += read_len;
+ len -= read_len;
+ data += read_len;
+ }
+
+ return ret;
+}
+
+#ifdef CONFIG_SPI_FLASH_SST
+static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
+{
+ int ret;
+ u8 cmd[4] = {
+ CMD_SST_BP,
+ offset >> 16,
+ offset >> 8,
+ offset,
+ };
+
+ debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
+ spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret)
+ return ret;
+
+ ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
+ if (ret)
+ return ret;
+
+ return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+}
+
+int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
+ const void *buf)
+{
+ size_t actual, cmd_len;
+ int ret;
+ u8 cmd[4];
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ /* If the data is not word aligned, write out leading single byte */
+ actual = offset % 2;
+ if (actual) {
+ ret = sst_byte_write(flash, offset, buf);
+ if (ret)
+ goto done;
+ }
+ offset += actual;
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret)
+ goto done;
+
+ cmd_len = 4;
+ cmd[0] = CMD_SST_AAI_WP;
+ cmd[1] = offset >> 16;
+ cmd[2] = offset >> 8;
+ cmd[3] = offset;
+
+ for (; actual < len - 1; actual += 2) {
+ debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
+ spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
+ cmd[0], offset);
+
+ ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
+ buf + actual, 2);
+ if (ret) {
+ debug("SF: sst word program failed\n");
+ break;
+ }
+
+ ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ if (ret)
+ break;
+
+ cmd_len = 1;
+ offset += 2;
+ }
+
+ if (!ret)
+ ret = spi_flash_cmd_write_disable(flash);
+
+ /* If there is a single trailing byte, write it out */
+ if (!ret && actual != len)
+ ret = sst_byte_write(flash, offset, buf + actual);
+
+ done:
+ debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
+ ret ? "failure" : "success", len, offset - actual);
+
+ spi_release_bus(flash->spi);
+ return ret;
+}
+#endif
--- /dev/null
+/*
+ * SPI flash probing
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
+ * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <spi.h>
+#include <spi_flash.h>
+
+#include "sf_internal.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * struct spi_flash_params - SPI/QSPI flash device params structure
+ *
+ * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
+ * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
+ * @ext_jedec: Device ext_jedec ID
+ * @sector_size: Sector size of this device
+ * @nr_sectors: No.of sectors on this device
+ * @flags: Importent param, for flash specific behaviour
+ */
+struct spi_flash_params {
+ const char *name;
+ u32 jedec;
+ u16 ext_jedec;
+ u32 sector_size;
+ u32 nr_sectors;
+ u16 flags;
+};
+
+static const struct spi_flash_params spi_flash_params_table[] = {
+#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
+ {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, SECT_4K},
+ {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, SECT_4K},
+ {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, SECT_4K},
+ {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, SECT_4K},
+ {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, SECT_4K},
+ {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, SECT_4K},
+ {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, SECT_4K},
+#endif
+#ifdef CONFIG_SPI_FLASH_EON /* EON */
+ {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0},
+ {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, SECT_4K},
+ {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0},
+#endif
+#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
+ {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, SECT_4K},
+ {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, SECT_4K},
+#endif
+#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
+ {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0},
+ {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0},
+ {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0},
+ {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0},
+ {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0},
+ {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, 0},
+ {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, 0},
+ {"MX25L51235F", 0xc2201A, 0x0, 64 * 1024, 1024, 0},
+ {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, 0},
+#endif
+#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
+ {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0},
+ {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0},
+ {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0},
+ {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0},
+ {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, 0},
+ {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, 0},
+ {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, 0},
+ {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, 0},
+ {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, 0},
+ {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, 0},
+ {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, 0},
+ {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, 0},
+ {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, 0},
+#endif
+#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
+ {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0},
+ {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0},
+ {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0},
+ {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0},
+ {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0},
+ {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0},
+ {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0},
+ {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0},
+ {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, SECT_4K},
+ {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, SECT_4K},
+ {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, SECT_4K},
+ {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, SECT_4K},
+ {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, SECT_4K},
+ {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, SECT_4K},
+ {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, SECT_4K},
+ {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, SECT_4K},
+ {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, E_FSR | SECT_4K},
+ {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, E_FSR | SECT_4K},
+ {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, E_FSR | SECT_4K},
+ {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, E_FSR | SECT_4K},
+#endif
+#ifdef CONFIG_SPI_FLASH_SST /* SST */
+ {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WP},
+ {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WP},
+ {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WP},
+ {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WP},
+ {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, SECT_4K},
+ {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WP},
+ {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WP},
+ {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WP},
+ {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WP},
+ {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WP},
+#endif
+#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
+ {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0},
+ {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0},
+ {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0},
+ {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, SECT_4K},
+ {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, SECT_4K},
+ {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, SECT_4K},
+ {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, SECT_4K},
+ {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, SECT_4K},
+ {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, SECT_4K},
+ {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, SECT_4K},
+ {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, SECT_4K},
+ {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, SECT_4K},
+ {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, SECT_4K},
+ {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, SECT_4K},
+ {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, SECT_4K},
+ {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, SECT_4K},
+ {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, SECT_4K},
+ {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, SECT_4K},
+#endif
+ /*
+ * Note:
+ * Below paired flash devices has similar spi_flash_params params.
+ * (S25FL129P_64K, S25FL128S_64K)
+ * (W25Q80BL, W25Q80BV)
+ * (W25Q16CL, W25Q16DV)
+ * (W25Q32BV, W25Q32FV_SPI)
+ * (W25Q64CV, W25Q64FV_SPI)
+ * (W25Q128BV, W25Q128FV_SPI)
+ * (W25Q32DW, W25Q32FV_QPI)
+ * (W25Q64DW, W25Q64FV_QPI)
+ * (W25Q128FW, W25Q128FV_QPI)
+ */
+};
+
+struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, u8 *idcode)
+{
+ const struct spi_flash_params *params;
+ struct spi_flash *flash;
+ int i;
+ u16 jedec = idcode[1] << 8 | idcode[2];
+ u16 ext_jedec = idcode[3] << 8 | idcode[4];
+
+ /* Get the flash id (jedec = manuf_id + dev_id, ext_jedec) */
+ for (i = 0; i < ARRAY_SIZE(spi_flash_params_table); i++) {
+ params = &spi_flash_params_table[i];
+ if ((params->jedec >> 16) == idcode[0]) {
+ if ((params->jedec & 0xFFFF) == jedec) {
+ if (params->ext_jedec == 0)
+ break;
+ else if (params->ext_jedec == ext_jedec)
+ break;
+ }
+ }
+ }
+
+ if (i == ARRAY_SIZE(spi_flash_params_table)) {
+ printf("SF: Unsupported flash IDs: ");
+ printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
+ idcode[0], jedec, ext_jedec);
+ return NULL;
+ }
+
+ flash = malloc(sizeof(*flash));
+ if (!flash) {
+ debug("SF: Failed to allocate spi_flash\n");
+ return NULL;
+ }
+ memset(flash, '\0', sizeof(*flash));
+
+ flash->spi = spi;
+ flash->name = params->name;
+
+ /* Assign spi_flash ops */
+ flash->write = spi_flash_cmd_write_ops;
+#ifdef CONFIG_SPI_FLASH_SST
+ if (params->flags & SST_WP)
+ flash->write = sst_write_wp;
+#endif
+ flash->erase = spi_flash_cmd_erase_ops;
+ flash->read = spi_flash_cmd_read_ops;
+
+ /* Compute the flash size */
+ flash->page_size = (ext_jedec == 0x4d00) ? 512 : 256;
+ flash->sector_size = params->sector_size;
+ flash->size = flash->sector_size * params->nr_sectors;
+
+ /* Compute erase sector and command */
+ if (params->flags & SECT_4K) {
+ flash->erase_cmd = CMD_ERASE_4K;
+ flash->erase_size = 4096;
+ } else if (params->flags & SECT_32K) {
+ flash->erase_cmd = CMD_ERASE_32K;
+ flash->erase_size = 32768;
+ } else {
+ flash->erase_cmd = CMD_ERASE_64K;
+ flash->erase_size = flash->sector_size;
+ }
+
+ /* Poll cmd seclection */
+ flash->poll_cmd = CMD_READ_STATUS;
+#ifdef CONFIG_SPI_FLASH_STMICRO
+ if (params->flags & E_FSR)
+ flash->poll_cmd = CMD_FLAG_STATUS;
+#endif
+
+#ifdef CONFIG_SPI_FLASH_BAR
+ /* Configure the BAR - discover bank cmds and read current bank */
+ u8 curr_bank = 0;
+ if (flash->size > SPI_FLASH_16MB_BOUN) {
+ flash->bank_read_cmd = (idcode[0] == 0x01) ?
+ CMD_BANKADDR_BRRD : CMD_EXTNADDR_RDEAR;
+ flash->bank_write_cmd = (idcode[0] == 0x01) ?
+ CMD_BANKADDR_BRWR : CMD_EXTNADDR_WREAR;
+
+ if (spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
+ &curr_bank, 1)) {
+ debug("SF: fail to read bank addr register\n");
+ return NULL;
+ }
+ flash->bank_curr = curr_bank;
+ } else {
+ flash->bank_curr = curr_bank;
+ }
+#endif
+
+ /* Flash powers up read-only, so clear BP# bits */
+#if defined(CONFIG_SPI_FLASH_ATMEL) || \
+ defined(CONFIG_SPI_FLASH_MACRONIX) || \
+ defined(CONFIG_SPI_FLASH_SST)
+ spi_flash_cmd_write_status(flash, 0);
+#endif
+
+ return flash;
+}
+
+#ifdef CONFIG_OF_CONTROL
+int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
+{
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int node;
+
+ /* If there is no node, do nothing */
+ node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
+ if (node < 0)
+ return 0;
+
+ addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
+ if (addr == FDT_ADDR_T_NONE) {
+ debug("%s: Cannot decode address\n", __func__);
+ return 0;
+ }
+
+ if (flash->size != size) {
+ debug("%s: Memory map must cover entire device\n", __func__);
+ return -1;
+ }
+ flash->memory_map = (void *)addr;
+
+ return 0;
+}
+#endif /* CONFIG_OF_CONTROL */
+
+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode)
+{
+ struct spi_slave *spi;
+ struct spi_flash *flash = NULL;
+ u8 idcode[5];
+ int ret;
+
+ /* Setup spi_slave */
+ spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+ if (!spi) {
+ printf("SF: Failed to set up slave\n");
+ return NULL;
+ }
+
+ /* Claim spi bus */
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ debug("SF: Failed to claim SPI bus: %d\n", ret);
+ goto err_claim_bus;
+ }
+
+ /* Read the ID codes */
+ ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
+ if (ret) {
+ printf("SF: Failed to get idcodes\n");
+ goto err_read_id;
+ }
+
+#ifdef DEBUG
+ printf("SF: Got idcodes\n");
+ print_buffer(0, idcode, 1, sizeof(idcode), 0);
+#endif
+
+ /* Validate params from spi_flash_params table */
+ flash = spi_flash_validate_params(spi, idcode);
+ if (!flash)
+ goto err_read_id;
+
+#ifdef CONFIG_OF_CONTROL
+ if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
+ debug("SF: FDT decode error\n");
+ goto err_read_id;
+ }
+#endif
+#ifndef CONFIG_SPL_BUILD
+ printf("SF: Detected %s with page size ", flash->name);
+ print_size(flash->page_size, ", erase size ");
+ print_size(flash->erase_size, ", total ");
+ print_size(flash->size, "");
+ if (flash->memory_map)
+ printf(", mapped at %p", flash->memory_map);
+ puts("\n");
+#endif
+#ifndef CONFIG_SPI_FLASH_BAR
+ if (flash->size > SPI_FLASH_16MB_BOUN) {
+ puts("SF: Warning - Only lower 16MiB accessible,");
+ puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
+ }
+#endif
+
+ /* Release spi bus */
+ spi_release_bus(spi);
+
+ return flash;
+
+err_read_id:
+ spi_release_bus(spi);
+err_claim_bus:
+ spi_free_slave(spi);
+ return NULL;
+}
+
+void spi_flash_free(struct spi_flash *flash)
+{
+ spi_free_slave(flash->spi);
+ free(flash);
+}
+++ /dev/null
-/*
- * SPI flash interface
- *
- * Copyright (C) 2008 Atmel Corporation
- * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <spi.h>
-
-static int spi_flash_read_write(struct spi_slave *spi,
- const u8 *cmd, size_t cmd_len,
- const u8 *data_out, u8 *data_in,
- size_t data_len)
-{
- unsigned long flags = SPI_XFER_BEGIN;
- int ret;
-
- if (data_len == 0)
- flags |= SPI_XFER_END;
-
- ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
- if (ret) {
- debug("SF: Failed to send command (%zu bytes): %d\n",
- cmd_len, ret);
- } else if (data_len != 0) {
- ret = spi_xfer(spi, data_len * 8, data_out, data_in,
- SPI_XFER_END);
- if (ret)
- debug("SF: Failed to transfer %zu bytes of data: %d\n",
- data_len, ret);
- }
-
- return ret;
-}
-
-int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
- size_t cmd_len, void *data, size_t data_len)
-{
- return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len);
-}
-
-int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len)
-{
- return spi_flash_cmd_read(spi, &cmd, 1, response, len);
-}
-
-int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
- const void *data, size_t data_len)
-{
- return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
-}
+++ /dev/null
-/*
- * SPI flash internal definitions
- *
- * Copyright (C) 2008 Atmel Corporation
- * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _SPI_FLASH_INTERNAL_H_
-#define _SPI_FLASH_INTERNAL_H_
-
-#define SPI_FLASH_16MB_BOUN 0x1000000
-
-/* SECT flags */
-#define SECT_4K (1 << 1)
-#define SECT_32K (1 << 2)
-#define E_FSR (1 << 3)
-
-/* Erase commands */
-#define CMD_ERASE_4K 0x20
-#define CMD_ERASE_32K 0x52
-#define CMD_ERASE_CHIP 0xc7
-#define CMD_ERASE_64K 0xd8
-
-/* Write commands */
-#define CMD_WRITE_STATUS 0x01
-#define CMD_PAGE_PROGRAM 0x02
-#define CMD_WRITE_DISABLE 0x04
-#define CMD_READ_STATUS 0x05
-#define CMD_WRITE_ENABLE 0x06
-#define CMD_READ_CONFIG 0x35
-#define CMD_FLAG_STATUS 0x70
-
-/* Read commands */
-#define CMD_READ_ARRAY_SLOW 0x03
-#define CMD_READ_ARRAY_FAST 0x0b
-#define CMD_READ_ID 0x9f
-
-/* Bank addr access commands */
-#ifdef CONFIG_SPI_FLASH_BAR
-# define CMD_BANKADDR_BRWR 0x17
-# define CMD_BANKADDR_BRRD 0x16
-# define CMD_EXTNADDR_WREAR 0xC5
-# define CMD_EXTNADDR_RDEAR 0xC8
-#endif
-
-/* Common status */
-#define STATUS_WIP 0x01
-#define STATUS_PEC 0x80
-
-/* Flash timeout values */
-#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
-#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
-#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
-
-/* SST specific */
-#ifdef CONFIG_SPI_FLASH_SST
-# define SST_WP 0x01 /* Supports AAI word program */
-# define CMD_SST_BP 0x02 /* Byte Program */
-# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
-
-int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
- const void *buf);
-#endif
-
-/* Send a single-byte command to the device and read the response */
-int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
-
-/*
- * Send a multi-byte command to the device and read the response. Used
- * for flash array reads, etc.
- */
-int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
- size_t cmd_len, void *data, size_t data_len);
-
-/*
- * Send a multi-byte command to the device followed by (optional)
- * data. Used for programming the flash array, etc.
- */
-int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
- const void *data, size_t data_len);
-
-
-/* Flash erase(sectors) operation, support all possible erase commands */
-int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
-
-/* Program the status register */
-int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
-
-/* Set quad enbale bit */
-int spi_flash_set_qeb(struct spi_flash *flash);
-
-/* Enable writing on the SPI flash */
-static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
-{
- return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
-}
-
-/* Disable writing on the SPI flash */
-static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
-{
- return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
-}
-
-/*
- * Send the read status command to the device and wait for the wip
- * (write-in-progress) bit to clear itself.
- */
-int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
-
-/*
- * Used for spi_flash write operation
- * - SPI claim
- * - spi_flash_cmd_write_enable
- * - spi_flash_cmd_write
- * - spi_flash_cmd_wait_ready
- * - SPI release
- */
-int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
- size_t cmd_len, const void *buf, size_t buf_len);
-
-/*
- * Flash write operation, support all possible write commands.
- * Write the requested data out breaking it up into multiple write
- * commands as needed per the write size.
- */
-int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
- size_t len, const void *buf);
-
-/*
- * Same as spi_flash_cmd_read() except it also claims/releases the SPI
- * bus. Used as common part of the ->read() operation.
- */
-int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
- size_t cmd_len, void *data, size_t data_len);
-
-/* Flash read operation, support all possible read commands */
-int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
- size_t len, void *data);
-
-#endif /* _SPI_FLASH_INTERNAL_H_ */
+++ /dev/null
-/*
- * SPI flash operations
- *
- * Copyright (C) 2008 Atmel Corporation
- * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
- * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <spi.h>
-#include <spi_flash.h>
-#include <watchdog.h>
-
-#include "spi_flash_internal.h"
-
-static void spi_flash_addr(u32 addr, u8 *cmd)
-{
- /* cmd[0] is actual command */
- cmd[1] = addr >> 16;
- cmd[2] = addr >> 8;
- cmd[3] = addr >> 0;
-}
-
-int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
-{
- u8 cmd;
- int ret;
-
- cmd = CMD_WRITE_STATUS;
- ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
- if (ret < 0) {
- debug("SF: fail to write status register\n");
- return ret;
- }
-
- return 0;
-}
-
-#ifdef CONFIG_SPI_FLASH_BAR
-static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
-{
- u8 cmd;
- int ret;
-
- if (flash->bank_curr == bank_sel) {
- debug("SF: not require to enable bank%d\n", bank_sel);
- return 0;
- }
-
- cmd = flash->bank_write_cmd;
- ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
- if (ret < 0) {
- debug("SF: fail to write bank register\n");
- return ret;
- }
- flash->bank_curr = bank_sel;
-
- return 0;
-}
-#endif
-
-int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
-{
- struct spi_slave *spi = flash->spi;
- unsigned long timebase;
- int ret;
- u8 status;
- u8 check_status = 0x0;
- u8 poll_bit = STATUS_WIP;
- u8 cmd = flash->poll_cmd;
-
- if (cmd == CMD_FLAG_STATUS) {
- poll_bit = STATUS_PEC;
- check_status = poll_bit;
- }
-
- ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
- if (ret) {
- debug("SF: fail to read %s status register\n",
- cmd == CMD_READ_STATUS ? "read" : "flag");
- return ret;
- }
-
- timebase = get_timer(0);
- do {
- WATCHDOG_RESET();
-
- ret = spi_xfer(spi, 8, NULL, &status, 0);
- if (ret)
- return -1;
-
- if ((status & poll_bit) == check_status)
- break;
-
- } while (get_timer(timebase) < timeout);
-
- spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
-
- if ((status & poll_bit) == check_status)
- return 0;
-
- /* Timed out */
- debug("SF: time out!\n");
- return -1;
-}
-
-int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
- size_t cmd_len, const void *buf, size_t buf_len)
-{
- struct spi_slave *spi = flash->spi;
- unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
- int ret;
-
- if (buf == NULL)
- timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
-
- ret = spi_claim_bus(flash->spi);
- if (ret) {
- debug("SF: unable to claim SPI bus\n");
- return ret;
- }
-
- ret = spi_flash_cmd_write_enable(flash);
- if (ret < 0) {
- debug("SF: enabling write failed\n");
- return ret;
- }
-
- ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
- if (ret < 0) {
- debug("SF: write cmd failed\n");
- return ret;
- }
-
- ret = spi_flash_cmd_wait_ready(flash, timeout);
- if (ret < 0) {
- debug("SF: write %s timed out\n",
- timeout == SPI_FLASH_PROG_TIMEOUT ?
- "program" : "page erase");
- return ret;
- }
-
- spi_release_bus(spi);
-
- return ret;
-}
-
-int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
-{
- u32 erase_size;
- u8 cmd[4];
- int ret = -1;
-
- erase_size = flash->erase_size;
- if (offset % erase_size || len % erase_size) {
- debug("SF: Erase offset/length not multiple of erase size\n");
- return -1;
- }
-
- cmd[0] = flash->erase_cmd;
- while (len) {
-#ifdef CONFIG_SPI_FLASH_BAR
- u8 bank_sel;
-
- bank_sel = offset / SPI_FLASH_16MB_BOUN;
-
- ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
- if (ret) {
- debug("SF: fail to set bank%d\n", bank_sel);
- return ret;
- }
-#endif
- spi_flash_addr(offset, cmd);
-
- debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
- cmd[2], cmd[3], offset);
-
- ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
- if (ret < 0) {
- debug("SF: erase failed\n");
- break;
- }
-
- offset += erase_size;
- len -= erase_size;
- }
-
- return ret;
-}
-
-int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
- size_t len, const void *buf)
-{
- unsigned long byte_addr, page_size;
- size_t chunk_len, actual;
- u8 cmd[4];
- int ret = -1;
-
- page_size = flash->page_size;
-
- cmd[0] = CMD_PAGE_PROGRAM;
- for (actual = 0; actual < len; actual += chunk_len) {
-#ifdef CONFIG_SPI_FLASH_BAR
- u8 bank_sel;
-
- bank_sel = offset / SPI_FLASH_16MB_BOUN;
-
- ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
- if (ret) {
- debug("SF: fail to set bank%d\n", bank_sel);
- return ret;
- }
-#endif
- byte_addr = offset % page_size;
- chunk_len = min(len - actual, page_size - byte_addr);
-
- if (flash->spi->max_write_size)
- chunk_len = min(chunk_len, flash->spi->max_write_size);
-
- spi_flash_addr(offset, cmd);
-
- debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
- buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
-
- ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
- buf + actual, chunk_len);
- if (ret < 0) {
- debug("SF: write failed\n");
- break;
- }
-
- offset += chunk_len;
- }
-
- return ret;
-}
-
-int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
- size_t cmd_len, void *data, size_t data_len)
-{
- struct spi_slave *spi = flash->spi;
- int ret;
-
- ret = spi_claim_bus(flash->spi);
- if (ret) {
- debug("SF: unable to claim SPI bus\n");
- return ret;
- }
-
- ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
- if (ret < 0) {
- debug("SF: read cmd failed\n");
- return ret;
- }
-
- spi_release_bus(spi);
-
- return ret;
-}
-
-int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
- size_t len, void *data)
-{
- u8 cmd[5], bank_sel = 0;
- u32 remain_len, read_len;
- int ret = -1;
-
- /* Handle memory-mapped SPI */
- if (flash->memory_map) {
- memcpy(data, flash->memory_map + offset, len);
- return 0;
- }
-
- cmd[0] = CMD_READ_ARRAY_FAST;
- cmd[4] = 0x00;
-
- while (len) {
-#ifdef CONFIG_SPI_FLASH_BAR
- bank_sel = offset / SPI_FLASH_16MB_BOUN;
-
- ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
- if (ret) {
- debug("SF: fail to set bank%d\n", bank_sel);
- return ret;
- }
-#endif
- remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset);
- if (len < remain_len)
- read_len = len;
- else
- read_len = remain_len;
-
- spi_flash_addr(offset, cmd);
-
- ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
- data, read_len);
- if (ret < 0) {
- debug("SF: read failed\n");
- break;
- }
-
- offset += read_len;
- len -= read_len;
- data += read_len;
- }
-
- return ret;
-}
-
-#ifdef CONFIG_SPI_FLASH_SST
-static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
-{
- int ret;
- u8 cmd[4] = {
- CMD_SST_BP,
- offset >> 16,
- offset >> 8,
- offset,
- };
-
- debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
- spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
-
- ret = spi_flash_cmd_write_enable(flash);
- if (ret)
- return ret;
-
- ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
- if (ret)
- return ret;
-
- return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
-}
-
-int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
- const void *buf)
-{
- size_t actual, cmd_len;
- int ret;
- u8 cmd[4];
-
- ret = spi_claim_bus(flash->spi);
- if (ret) {
- debug("SF: Unable to claim SPI bus\n");
- return ret;
- }
-
- /* If the data is not word aligned, write out leading single byte */
- actual = offset % 2;
- if (actual) {
- ret = sst_byte_write(flash, offset, buf);
- if (ret)
- goto done;
- }
- offset += actual;
-
- ret = spi_flash_cmd_write_enable(flash);
- if (ret)
- goto done;
-
- cmd_len = 4;
- cmd[0] = CMD_SST_AAI_WP;
- cmd[1] = offset >> 16;
- cmd[2] = offset >> 8;
- cmd[3] = offset;
-
- for (; actual < len - 1; actual += 2) {
- debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
- spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
- cmd[0], offset);
-
- ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
- buf + actual, 2);
- if (ret) {
- debug("SF: sst word program failed\n");
- break;
- }
-
- ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
- if (ret)
- break;
-
- cmd_len = 1;
- offset += 2;
- }
-
- if (!ret)
- ret = spi_flash_cmd_write_disable(flash);
-
- /* If there is a single trailing byte, write it out */
- if (!ret && actual != len)
- ret = sst_byte_write(flash, offset, buf + actual);
-
- done:
- debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
- ret ? "failure" : "success", len, offset - actual);
-
- spi_release_bus(flash->spi);
- return ret;
-}
-#endif
+++ /dev/null
-/*
- * SPI flash probing
- *
- * Copyright (C) 2008 Atmel Corporation
- * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
- * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <fdtdec.h>
-#include <malloc.h>
-#include <spi.h>
-#include <spi_flash.h>
-
-#include "spi_flash_internal.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/**
- * struct spi_flash_params - SPI/QSPI flash device params structure
- *
- * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
- * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
- * @ext_jedec: Device ext_jedec ID
- * @sector_size: Sector size of this device
- * @nr_sectors: No.of sectors on this device
- * @flags: Importent param, for flash specific behaviour
- */
-struct spi_flash_params {
- const char *name;
- u32 jedec;
- u16 ext_jedec;
- u32 sector_size;
- u32 nr_sectors;
- u16 flags;
-};
-
-static const struct spi_flash_params spi_flash_params_table[] = {
-#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
- {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, SECT_4K},
- {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, SECT_4K},
- {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, SECT_4K},
- {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, SECT_4K},
- {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, SECT_4K},
- {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, SECT_4K},
- {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, SECT_4K},
-#endif
-#ifdef CONFIG_SPI_FLASH_EON /* EON */
- {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0},
- {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, SECT_4K},
- {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0},
-#endif
-#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
- {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, SECT_4K},
- {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, SECT_4K},
-#endif
-#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
- {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0},
- {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0},
- {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0},
- {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0},
- {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0},
- {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, 0},
- {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, 0},
- {"MX25L51235F", 0xc2201A, 0x0, 64 * 1024, 1024, 0},
- {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, 0},
-#endif
-#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
- {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0},
- {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0},
- {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0},
- {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0},
- {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, 0},
- {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, 0},
- {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, 0},
- {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, 0},
- {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, 0},
- {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, 0},
- {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, 0},
- {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, 0},
- {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, 0},
-#endif
-#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
- {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0},
- {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0},
- {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0},
- {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0},
- {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0},
- {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0},
- {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0},
- {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0},
- {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, SECT_4K},
- {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, SECT_4K},
- {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, SECT_4K},
- {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, SECT_4K},
- {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, SECT_4K},
- {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, SECT_4K},
- {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, SECT_4K},
- {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, SECT_4K},
- {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, E_FSR | SECT_4K},
- {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, E_FSR | SECT_4K},
- {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, E_FSR | SECT_4K},
- {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, E_FSR | SECT_4K},
-#endif
-#ifdef CONFIG_SPI_FLASH_SST /* SST */
- {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WP},
- {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WP},
- {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WP},
- {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WP},
- {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, SECT_4K},
- {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WP},
- {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WP},
- {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WP},
- {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WP},
- {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WP},
-#endif
-#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
- {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0},
- {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0},
- {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0},
- {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, SECT_4K},
- {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, SECT_4K},
- {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, SECT_4K},
- {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, SECT_4K},
- {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, SECT_4K},
- {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, SECT_4K},
- {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, SECT_4K},
- {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, SECT_4K},
- {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, SECT_4K},
- {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, SECT_4K},
- {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, SECT_4K},
- {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, SECT_4K},
- {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, SECT_4K},
- {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, SECT_4K},
- {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, SECT_4K},
-#endif
- /*
- * Note:
- * Below paired flash devices has similar spi_flash_params params.
- * (S25FL129P_64K, S25FL128S_64K)
- * (W25Q80BL, W25Q80BV)
- * (W25Q16CL, W25Q16DV)
- * (W25Q32BV, W25Q32FV_SPI)
- * (W25Q64CV, W25Q64FV_SPI)
- * (W25Q128BV, W25Q128FV_SPI)
- * (W25Q32DW, W25Q32FV_QPI)
- * (W25Q64DW, W25Q64FV_QPI)
- * (W25Q128FW, W25Q128FV_QPI)
- */
-};
-
-struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, u8 *idcode)
-{
- const struct spi_flash_params *params;
- struct spi_flash *flash;
- int i;
- u16 jedec = idcode[1] << 8 | idcode[2];
- u16 ext_jedec = idcode[3] << 8 | idcode[4];
-
- /* Get the flash id (jedec = manuf_id + dev_id, ext_jedec) */
- for (i = 0; i < ARRAY_SIZE(spi_flash_params_table); i++) {
- params = &spi_flash_params_table[i];
- if ((params->jedec >> 16) == idcode[0]) {
- if ((params->jedec & 0xFFFF) == jedec) {
- if (params->ext_jedec == 0)
- break;
- else if (params->ext_jedec == ext_jedec)
- break;
- }
- }
- }
-
- if (i == ARRAY_SIZE(spi_flash_params_table)) {
- printf("SF: Unsupported flash IDs: ");
- printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
- idcode[0], jedec, ext_jedec);
- return NULL;
- }
-
- flash = malloc(sizeof(*flash));
- if (!flash) {
- debug("SF: Failed to allocate spi_flash\n");
- return NULL;
- }
- memset(flash, '\0', sizeof(*flash));
-
- flash->spi = spi;
- flash->name = params->name;
-
- /* Assign spi_flash ops */
- flash->write = spi_flash_cmd_write_ops;
-#ifdef CONFIG_SPI_FLASH_SST
- if (params->flags & SST_WP)
- flash->write = sst_write_wp;
-#endif
- flash->erase = spi_flash_cmd_erase_ops;
- flash->read = spi_flash_cmd_read_ops;
-
- /* Compute the flash size */
- flash->page_size = (ext_jedec == 0x4d00) ? 512 : 256;
- flash->sector_size = params->sector_size;
- flash->size = flash->sector_size * params->nr_sectors;
-
- /* Compute erase sector and command */
- if (params->flags & SECT_4K) {
- flash->erase_cmd = CMD_ERASE_4K;
- flash->erase_size = 4096;
- } else if (params->flags & SECT_32K) {
- flash->erase_cmd = CMD_ERASE_32K;
- flash->erase_size = 32768;
- } else {
- flash->erase_cmd = CMD_ERASE_64K;
- flash->erase_size = flash->sector_size;
- }
-
- /* Poll cmd seclection */
- flash->poll_cmd = CMD_READ_STATUS;
-#ifdef CONFIG_SPI_FLASH_STMICRO
- if (params->flags & E_FSR)
- flash->poll_cmd = CMD_FLAG_STATUS;
-#endif
-
-#ifdef CONFIG_SPI_FLASH_BAR
- /* Configure the BAR - discover bank cmds and read current bank */
- u8 curr_bank = 0;
- if (flash->size > SPI_FLASH_16MB_BOUN) {
- flash->bank_read_cmd = (idcode[0] == 0x01) ?
- CMD_BANKADDR_BRRD : CMD_EXTNADDR_RDEAR;
- flash->bank_write_cmd = (idcode[0] == 0x01) ?
- CMD_BANKADDR_BRWR : CMD_EXTNADDR_WREAR;
-
- if (spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
- &curr_bank, 1)) {
- debug("SF: fail to read bank addr register\n");
- return NULL;
- }
- flash->bank_curr = curr_bank;
- } else {
- flash->bank_curr = curr_bank;
- }
-#endif
-
- /* Flash powers up read-only, so clear BP# bits */
-#if defined(CONFIG_SPI_FLASH_ATMEL) || \
- defined(CONFIG_SPI_FLASH_MACRONIX) || \
- defined(CONFIG_SPI_FLASH_SST)
- spi_flash_cmd_write_status(flash, 0);
-#endif
-
- return flash;
-}
-
-#ifdef CONFIG_OF_CONTROL
-int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
-{
- fdt_addr_t addr;
- fdt_size_t size;
- int node;
-
- /* If there is no node, do nothing */
- node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
- if (node < 0)
- return 0;
-
- addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
- if (addr == FDT_ADDR_T_NONE) {
- debug("%s: Cannot decode address\n", __func__);
- return 0;
- }
-
- if (flash->size != size) {
- debug("%s: Memory map must cover entire device\n", __func__);
- return -1;
- }
- flash->memory_map = (void *)addr;
-
- return 0;
-}
-#endif /* CONFIG_OF_CONTROL */
-
-struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int spi_mode)
-{
- struct spi_slave *spi;
- struct spi_flash *flash = NULL;
- u8 idcode[5];
- int ret;
-
- /* Setup spi_slave */
- spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
- if (!spi) {
- printf("SF: Failed to set up slave\n");
- return NULL;
- }
-
- /* Claim spi bus */
- ret = spi_claim_bus(spi);
- if (ret) {
- debug("SF: Failed to claim SPI bus: %d\n", ret);
- goto err_claim_bus;
- }
-
- /* Read the ID codes */
- ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
- if (ret) {
- printf("SF: Failed to get idcodes\n");
- goto err_read_id;
- }
-
-#ifdef DEBUG
- printf("SF: Got idcodes\n");
- print_buffer(0, idcode, 1, sizeof(idcode), 0);
-#endif
-
- /* Validate params from spi_flash_params table */
- flash = spi_flash_validate_params(spi, idcode);
- if (!flash)
- goto err_read_id;
-
-#ifdef CONFIG_OF_CONTROL
- if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
- debug("SF: FDT decode error\n");
- goto err_read_id;
- }
-#endif
-#ifndef CONFIG_SPL_BUILD
- printf("SF: Detected %s with page size ", flash->name);
- print_size(flash->page_size, ", erase size ");
- print_size(flash->erase_size, ", total ");
- print_size(flash->size, "");
- if (flash->memory_map)
- printf(", mapped at %p", flash->memory_map);
- puts("\n");
-#endif
-#ifndef CONFIG_SPI_FLASH_BAR
- if (flash->size > SPI_FLASH_16MB_BOUN) {
- puts("SF: Warning - Only lower 16MiB accessible,");
- puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
- }
-#endif
-
- /* Release spi bus */
- spi_release_bus(spi);
-
- return flash;
-
-err_read_id:
- spi_release_bus(spi);
-err_claim_bus:
- spi_free_slave(spi);
- return NULL;
-}
-
-void spi_flash_free(struct spi_flash *flash)
-{
- spi_free_slave(flash->spi);
- free(flash);
-}
projects / u-boot / commitdiff