83xx: Add Vitesse VSC7385 firmware uploading

Update the MPC8349E-mITX, MPC8313E-RDB, and MPC837XE-RDB board files to upload
the Vitesse VSC7385 firmware.  Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET.
Cleaned up the board header files to make selecting the VSC7385 easier to
control.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
index 42019fb80cbdcec56fa5fdc32e3be764c688b97d..7cbdb7bf3154d4770866ae0b8f607088c1510957 100644 (file)
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -28,6 +28,7 @@
 #endif
 #include <pci.h>
 #include <mpc83xx.h>
+#include <vsc7385.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -98,6 +99,26 @@ void pci_init_board(void)
        mpc83xx_pci_init(1, reg, warmboot);
 }
 
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+*/
+int misc_init_r(void)
+{
+       int rc = 0;
+
+#ifdef CONFIG_VSC7385_IMAGE
+       if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+               CONFIG_VSC7385_IMAGE_SIZE)) {
+               puts("Failure uploading VSC7385 microcode.\n");
+               rc = 1;
+       }
+#endif
+
+       return rc;
+}
+
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {

diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 972361fd68c7ce4a20d9bdd13b57f4ac177d625c..704f9636bcab0972806bef10a63d65eeec0f1dfe 100644 (file)
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -25,6 +25,7 @@
 #include <mpc83xx.h>
 #include <i2c.h>
 #include <miiphy.h>
+#include <vsc7385.h>
 #ifdef CONFIG_PCI
 #include <asm/mpc8349_pci.h>
 #include <pci.h>
@@ -177,7 +178,7 @@ int checkboard(void)
  */
 int misc_init_f(void)
 {
-#ifdef CONFIG_VSC7385
+#ifdef CONFIG_VSC7385_ENET
        volatile u32 *vsc7385_cpuctrl;
 
        /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register.  The power up
@@ -239,6 +240,8 @@ int misc_init_f(void)
 }
 
 /*
+ * Miscellaneous late-boot configurations
+ *
  * Make sure the EEPROM has the HRCW correctly programmed.
  * Make sure the RTC is correctly programmed.
  *
@@ -250,6 +253,8 @@ int misc_init_f(void)
  *
  * This function makes sure that the I2C EEPROM is programmed
  * correctly.
+ *
+ * If a VSC7385 microcode image is present, then upload it.
  */
 int misc_init_r(void)
 {
@@ -375,6 +380,14 @@ int misc_init_r(void)
        i2c_set_bus_num(orig_bus);
 #endif
 
+#ifdef CONFIG_VSC7385_IMAGE
+       if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+               CONFIG_VSC7385_IMAGE_SIZE)) {
+               puts("Failure uploading VSC7385 microcode.\n");
+               rc = 1;
+       }
+#endif
+
        return rc;
 }
 

diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index bed0fc37ea34002509447ac8880d00f6b8c0a980..a3b20b8f9584ef0623dfd16e30c0d2901f441040 100644 (file)
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -16,6 +16,8 @@
 #include <i2c.h>
 #include <asm/io.h>
 #include <spd_sdram.h>
+#include <vsc7385.h>
+
 
 #if defined(CFG_DRAM_TEST)
 int
@@ -56,11 +58,6 @@ testdram(void)
 }
 #endif
 
-int board_early_init_f(void)
-{
-       return 0;
-}
-
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 void ddr_enable_ecc(unsigned int dram_size);
 #endif
@@ -135,6 +132,26 @@ int checkboard(void)
        return 0;
 }
 
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+*/
+int misc_init_r(void)
+{
+       int rc = 0;
+
+#ifdef CONFIG_VSC7385_IMAGE
+       if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+               CONFIG_VSC7385_IMAGE_SIZE)) {
+               puts("Failure uploading VSC7385 microcode.\n");
+               rc = 1;
+       }
+#endif
+
+       return rc;
+}
+
 #if defined(CONFIG_OF_BOARD_SETUP)
 
 void ft_board_setup(void *blob, bd_t *bd)

diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index f12a3e605e665295cc1cebd982ea7991d5771a1c..9576fa59e28270bbbbd07c511a51e069b8a1e8ae 100644 (file)
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -38,6 +38,14 @@
 #define CONFIG_PCI
 #define CONFIG_83XX_GENERIC_PCI
 
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ */
+#define CONFIG_VSC7385_ENET
+
+
 #ifdef CFG_66MHZ
 #define CONFIG_83XX_CLKIN      66666667        /* in Hz */
 #elif defined(CFG_33MHZ)
@@ -64,6 +72,22 @@
 #define CFG_ACR_PIPE_DEP       3       /* Arbiter pipeline depth (0-3) */
 #define CFG_ACR_RPTCNT         3       /* Arbiter repeat count (0-7) */
 
+/*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE           0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE      8192
+
+#endif
+
 /*
  * DDR Setup
  */
@@ -214,19 +238,24 @@
 #define CFG_LBLAWBAR1_PRELIM   CFG_NAND_BASE
 #define CFG_LBLAWAR1_PRELIM    0x8000000E      /* 32KB  */
 
+/* local bus read write buffer mapping */
+#define CFG_BR3_PRELIM         0xFA000801      /* map at 0xFA000000 */
+#define CFG_OR3_PRELIM         0xFFFF8FF7      /* 32kB */
+#define CFG_LBLAWBAR3_PRELIM   0xFA000000
+#define CFG_LBLAWAR3_PRELIM    0x8000000E      /* 32KB  */
+
+/* Vitesse 7385 */
+
 #define CFG_VSC7385_BASE       0xF0000000
 
-#define CONFIG_VSC7385_ENET                    /* VSC7385 ethernet support */
+#ifdef CONFIG_VSC7385_ENET
+
 #define CFG_BR2_PRELIM         0xf0000801      /* VSC7385 Base address */
 #define CFG_OR2_PRELIM         0xfffe09ff      /* VSC7385, 128K bytes*/
 #define CFG_LBLAWBAR2_PRELIM   CFG_VSC7385_BASE/* Access window base at VSC7385 base */
 #define CFG_LBLAWAR2_PRELIM    0x80000010      /* Access window size 128K */
 
-/* local bus read write buffer mapping */
-#define CFG_BR3_PRELIM         0xFA000801      /* map at 0xFA000000 */
-#define CFG_OR3_PRELIM         0xFFFF8FF7      /* 32kB */
-#define CFG_LBLAWBAR3_PRELIM   0xFA000000
-#define CFG_LBLAWAR3_PRELIM    0x8000000E      /* 32KB  */
+#endif
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT       1
@@ -263,13 +292,6 @@
 #define CFG_I2C_OFFSET         0x3000
 #define CFG_I2C2_OFFSET                0x3100
 
-/* TSEC */
-#define CFG_TSEC1_OFFSET       0x24000
-#define CFG_TSEC1              (CFG_IMMR+CFG_TSEC1_OFFSET)
-#define CFG_TSEC2_OFFSET       0x25000
-#define CFG_TSEC2              (CFG_IMMR+CFG_TSEC2_OFFSET)
-#define CONFIG_NET_MULTI
-
 /*
  * General PCI
  * Addresses are mapped 1-1.
@@ -288,26 +310,31 @@
 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
 
 /*
- * TSEC configuration
+ * TSEC
  */
 #define CONFIG_TSEC_ENET               /* TSEC ethernet support */
 
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI               1
-#endif
-
-#define CONFIG_GMII                    1       /* MII PHY management */
-#define CONFIG_TSEC1           1
+#define CONFIG_NET_MULTI
+#define CONFIG_GMII                    /* MII PHY management */
 
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME      "TSEC0"
-#define CONFIG_TSEC2           1
+#define CFG_TSEC1_OFFSET       0x24000
+#define TSEC1_PHY_ADDR         0x1c
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC1_PHYIDX           0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME      "TSEC1"
-#define TSEC1_PHY_ADDR                 0x1c
-#define TSEC2_PHY_ADDR                 4
-#define TSEC1_FLAGS                    TSEC_GIGABIT
-#define TSEC2_FLAGS                    TSEC_GIGABIT
-#define TSEC1_PHYIDX                   0
-#define TSEC2_PHYIDX                   0
+#define CFG_TSEC2_OFFSET       0x25000
+#define TSEC2_PHY_ADDR         4
+#define TSEC2_FLAGS            TSEC_GIGABIT
+#define TSEC2_PHYIDX           0
+#endif
+
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME                        "TSEC1"
@@ -496,10 +523,13 @@
  */
 #define CONFIG_ENV_OVERWRITE
 
+#ifdef CONFIG_HAS_ETH0
 #define CONFIG_ETHADDR         00:E0:0C:00:95:01
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH0
+#endif
+
+#ifdef CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR                00:E0:0C:00:95:02
+#endif
 
 #define CONFIG_IPADDR          10.0.0.2
 #define CONFIG_SERVERIP                10.0.0.1

diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 48c2736fcbe56b7d16672217a41c69a9e1d90e70..0e501867652ea3a7a7c4fdee0044f25865fea38e 100644 (file)
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -68,12 +68,16 @@
 
 #define CFG_IMMR               0xE0000000      /* The IMMR is relocated to here */
 
+#define CONFIG_MISC_INIT_F
+#define CONFIG_MISC_INIT_R
 
-/* On-board devices */
+/*
+ * On-board devices
+ */
 
 #ifdef CONFIG_MPC8349ITX
 #define CONFIG_COMPACT_FLASH   /* The CF card interface on the back of the board */
-#define CONFIG_VSC7385         /* The Vitesse 7385 5-port switch */
+#define CONFIG_VSC7385_ENET    /* VSC7385 ethernet support */
 #endif
 
 #define CONFIG_PCI
@@ -88,9 +92,6 @@
 /* I2C */
 #ifdef CONFIG_HARD_I2C
 
-#define CONFIG_MISC_INIT_F
-#define CONFIG_MISC_INIT_R
-
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
@@ -190,6 +191,18 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CFG_FLASH_SIZE         16              /* FLASH size in MB */
 #define CFG_FLASH_SIZE_SHIFT   4               /* log2 of the above value */
 
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE           0xFEFFE000
+#define CONFIG_VSC7385_IMAGE_SIZE      8192
+
+#endif
+
 /*
  * BRx, ORx, LBLAWBARx, and LBLAWARx
  */
@@ -205,10 +218,10 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 /* Vitesse 7385 */
 
-#ifdef CONFIG_VSC7385
-
 #define CFG_VSC7385_BASE       0xF8000000
 
+#ifdef CONFIG_VSC7385_ENET
+
 #define CFG_BR1_PRELIM         (CFG_VSC7385_BASE | BR_PS_8 | BR_V)
 #define CFG_OR1_PRELIM         (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
                                OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
@@ -384,7 +397,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME  "TSEC1"
 #define CFG_TSEC2_OFFSET       0x25000
-#define CONFIG_UNKNOWN_TSEC    /* TSEC2 is proprietary */
+
 #define TSEC2_PHY_ADDR         4
 #define TSEC2_PHYIDX           0
 #define TSEC2_FLAGS            TSEC_GIGABIT
@@ -619,11 +632,11 @@ boards, we say we have two, but don't display a message if we find only one. */
  */
 #define CONFIG_ENV_OVERWRITE
 
-#ifdef CONFIG_TSEC1
+#ifdef CONFIG_HAS_ETH0
 #define CONFIG_ETHADDR         00:E0:0C:00:8C:01
 #endif
 
-#ifdef CONFIG_TSEC2
+#ifdef CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR                00:E0:0C:00:8C:02
 #endif
 

diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 1964946ec8d2e8411b0aefe4b4bcf93084fa33ec..0d79aaeac8072537f56f4244193d922583bc0acf 100644 (file)
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -32,6 +32,14 @@
 
 #define CONFIG_PCI     1
 
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ */
+#define CONFIG_TSEC_ENET               /* TSEC Ethernet support */
+#define CONFIG_VSC7385_ENET
+
 /*
  * System Clock Setup
  */
@@ -117,6 +125,22 @@
  */
 #define CFG_IMMR               0xE0000000
 
+/*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE           0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE      8192
+
+#endif
+
 /*
  * DDR Setup
  */
@@ -251,15 +275,19 @@
 #define CFG_FLASH_ERASE_TOUT   60000   /* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT   500     /* Flash Write Timeout (ms) */
 
+/* Vitesse 7385 */
+
 #define CFG_VSC7385_BASE       0xF0000000
 
-/* VSC7385 Gigabit Switch support */
-#define CONFIG_VSC7385_ENET
+#ifdef CONFIG_VSC7385_ENET
+
 #define CFG_BR2_PRELIM         0xf0000801              /* Base address */
 #define CFG_OR2_PRELIM         0xfffe09ff              /* 128K bytes*/
 #define CFG_LBLAWBAR2_PRELIM   CFG_VSC7385_BASE        /* Access Base */
 #define CFG_LBLAWAR2_PRELIM    0x80000010              /* Access Size 128K */
 
+#endif
+
 /*
  * Serial Port
  */
@@ -324,43 +352,43 @@
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP         /* do pci plug-and-play */
 
-#undef CONFIG_EEPRO100
 #undef CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
 #endif /* CONFIG_PCI */
 
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI       1
-#endif
-
 /*
  * TSEC
  */
-#define CONFIG_TSEC_ENET       /* TSEC ethernet support */
-#define CFG_TSEC1_OFFSET       0x24000
-#define CFG_TSEC1              (CFG_IMMR+CFG_TSEC1_OFFSET)
-#define CFG_TSEC2_OFFSET       0x25000
-#define CFG_TSEC2              (CFG_IMMR+CFG_TSEC2_OFFSET)
+#ifdef CONFIG_TSEC_ENET
 
-/*
- * TSEC ethernet configuration
- */
-#define CONFIG_GMII                    1       /* MII PHY management */
-#define CONFIG_TSEC1                   1
+#define CONFIG_NET_MULTI
+#define CONFIG_GMII                    /* MII PHY management */
+
+#define CONFIG_TSEC1
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME              "TSEC0"
-#define CONFIG_TSEC2                   1
-#define CONFIG_TSEC2_NAME              "TSEC1"
+#define CFG_TSEC1_OFFSET               0x24000
 #define TSEC1_PHY_ADDR                 2
-#define TSEC2_PHY_ADDR                 0x1c
 #define TSEC1_FLAGS                    (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS                    (TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC1_PHYIDX                   0
-#define TSEC2_PHYIDX                   0
+#endif
 
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME              "TSEC1"
+#define CFG_TSEC2_OFFSET               0x25000
+#define TSEC2_PHY_ADDR                 0x1c
+#define TSEC2_FLAGS                    (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHYIDX                   0
+#endif
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME                        "TSEC0"
 
+#endif
+
 /*
  * Environment
  */
@@ -529,10 +557,13 @@
  */
 #define CONFIG_ENV_OVERWRITE
 
-#define CONFIG_HAS_ETH0                                /* add support for "ethaddr" */
-#define CONFIG_ETHADDR 00:04:9f:ef:04:01
-#define CONFIG_HAS_ETH1                                /* add support for "eth1addr" */
-#define CONFIG_ETH1ADDR        00:04:9f:ef:04:02
+#ifdef CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR         00:04:9f:ef:04:01
+#endif
+
+#ifdef CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR                00:04:9f:ef:04:02
+#endif
 
 #define CONFIG_IPADDR          10.0.0.2
 #define CONFIG_SERVERIP                10.0.0.1