]> git.sur5r.net Git - u-boot/commitdiff
exynos: Update origen and smdkv310 to use common tzpc_init
authorInderpal Singh <inderpal.singh@linaro.org>
Thu, 4 Apr 2013 23:09:21 +0000 (23:09 +0000)
committerMinkyu Kang <mk7.kang@samsung.com>
Tue, 4 Jun 2013 06:23:21 +0000 (15:23 +0900)
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
board/samsung/origen/lowlevel_init.S
board/samsung/origen/origen_setup.h
board/samsung/smdkv310/lowlevel_init.S
include/configs/origen.h
include/configs/smdkv310.h

index 9daa0da6143ec0051c181067d77b833c2a0407c8..be9d418265c2fda2f64928edeb542fb3d1950003 100644 (file)
@@ -87,12 +87,14 @@ lowlevel_init:
 1:
        /* for UART */
        bl uart_asm_init
+       bl arch_cpu_init
        bl tzpc_init
        pop     {pc}
 
 wakeup_reset:
        bl system_clock_init
        bl mem_ctrl_asm_init
+       bl arch_cpu_init
        bl tzpc_init
 
 exit_wakeup:
@@ -353,45 +355,3 @@ uart_asm_init:
        nop
        nop
 
-/* Setting TZPC[TrustZone Protection Controller] */
-tzpc_init:
-       ldr     r0, =TZPC0_BASE
-       mov     r1, #R0SIZE
-       str     r1, [r0]
-       mov     r1, #DECPROTXSET
-       str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-       ldr     r0, =TZPC1_BASE
-       str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-       ldr     r0, =TZPC2_BASE
-       str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-       ldr     r0, =TZPC3_BASE
-       str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-       ldr     r0, =TZPC4_BASE
-       str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-       ldr     r0, =TZPC5_BASE
-       str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-       str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-       mov     pc, lr
index 930b9485055693c1413524bf36a9c2b49560480d..926a4ccc2921151a09b5b9530fefece99dc27803 100644 (file)
 #define UBRDIV_OFFSET          0x28
 #define UFRACVAL_OFFSET                0x2C
 
-/* TZPC : Register Offsets */
-#define TZPC0_BASE             0x10110000
-#define TZPC1_BASE             0x10120000
-#define TZPC2_BASE             0x10130000
-#define TZPC3_BASE             0x10140000
-#define TZPC4_BASE             0x10150000
-#define TZPC5_BASE             0x10160000
-
-#define TZPC_DECPROT0SET_OFFSET        0x804
-#define TZPC_DECPROT1SET_OFFSET        0x810
-#define TZPC_DECPROT2SET_OFFSET        0x81C
-#define TZPC_DECPROT3SET_OFFSET        0x828
-
 /* CLK_SRC_CPU */
 #define MUX_HPM_SEL_MOUTAPLL           0x0
 #define MUX_HPM_SEL_SCLKMPLL           0x1
  * UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
  */
 #define UFRACVAL_VAL           0x4
-
-/*
- * TZPC Register Value :
- * R0SIZE: 0x0 : Size of secured ram
- */
-#define R0SIZE                 0x0
-
-/*
- * TZPC Decode Protection Register Value :
- * DECPROTXSET: 0xFF : Set Decode region to non-secure
- */
-#define DECPROTXSET            0xFF
 #endif
index 7a1ea98aed74f4d16056e26a42993c162fc167d7..31e0e2edaf1477070db420293894028e72f65cec 100644 (file)
@@ -85,12 +85,14 @@ lowlevel_init:
 1:
        /* for UART */
        bl uart_asm_init
+       bl arch_cpu_init
        bl tzpc_init
        pop     {pc}
 
 wakeup_reset:
        bl system_clock_init
        bl mem_ctrl_asm_init
+       bl arch_cpu_init
        bl tzpc_init
 
 exit_wakeup:
@@ -410,61 +412,3 @@ uart_asm_init:
        nop
        nop
        nop
-
-/* Setting TZPC[TrustZone Protection Controller] */
-tzpc_init:
-       ldr     r0, =0x10110000
-       mov     r1, #0x0
-       str     r1, [r0]
-       mov     r1, #0xff
-       str     r1, [r0, #0x0804]
-       str     r1, [r0, #0x0810]
-       str     r1, [r0, #0x081C]
-       str     r1, [r0, #0x0828]
-
-       ldr     r0, =0x10120000
-       mov     r1, #0x0
-       str     r1, [r0]
-       mov     r1, #0xff
-       str     r1, [r0, #0x0804]
-       str     r1, [r0, #0x0810]
-       str     r1, [r0, #0x081C]
-       str     r1, [r0, #0x0828]
-
-       ldr     r0, =0x10130000
-       mov     r1, #0x0
-       str     r1, [r0]
-       mov     r1, #0xff
-       str     r1, [r0, #0x0804]
-       str     r1, [r0, #0x0810]
-       str     r1, [r0, #0x081C]
-       str     r1, [r0, #0x0828]
-
-       ldr     r0, =0x10140000
-       mov     r1, #0x0
-       str     r1, [r0]
-       mov     r1, #0xff
-       str     r1, [r0, #0x0804]
-       str     r1, [r0, #0x0810]
-       str     r1, [r0, #0x081C]
-       str     r1, [r0, #0x0828]
-
-       ldr     r0, =0x10150000
-       mov     r1, #0x0
-       str     r1, [r0]
-       mov     r1, #0xff
-       str     r1, [r0, #0x0804]
-       str     r1, [r0, #0x0810]
-       str     r1, [r0, #0x081C]
-       str     r1, [r0, #0x0828]
-
-       ldr     r0, =0x10160000
-       mov     r1, #0x0
-       str     r1, [r0]
-       mov     r1, #0xff
-       str     r1, [r0, #0x0804]
-       str     r1, [r0, #0x0810]
-       str     r1, [r0, #0x081C]
-       str     r1, [r0, #0x0828]
-
-       mov     pc, lr
index ff2b24d97f4305f923f5c36dbf6c3f3b32f49913..e179911d0c3baf59f1cf09d12ed42b0000f28975 100644 (file)
@@ -96,6 +96,8 @@
 #define CONFIG_SPL
 #define COPY_BL2_FNPTR_ADDR    0x02020030
 
+#define CONFIG_SPL_TEXT_BASE   0x02021410
+
 #define CONFIG_BOOTCOMMAND     "fatload mmc 0 40007000 uImage; bootm 40007000"
 
 /* Miscellaneous configurable options */
index b796b46a7f6b8f39ad65cf309477df3bd66b9024..5e430660f12439de595c6af35e6fcc8d0abe66f5 100644 (file)
@@ -95,6 +95,8 @@
 #define CONFIG_SPL
 #define COPY_BL2_FNPTR_ADDR    0x00002488
 
+#define CONFIG_SPL_TEXT_BASE   0x02021410
+
 #define CONFIG_BOOTCOMMAND     "fatload mmc 0 40007000 uImage; bootm 40007000"
 
 /* Miscellaneous configurable options */